vdp fifo, another revision

diff --git a/pico/pico_int.h b/pico/pico_int.h
index 12f35b5..65b56f1 100644 (file)
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -296,10 +296,9 @@ extern SH2 sh2s[2];
 // not part of real SR\r
 #define PVS_ACTIVE    (1 << 16)\r
 #define PVS_VB2       (1 << 17) // ignores forced blanking\r
-#define PVS_CPUWR     (1 << 18) // CPU hold by FIFO full\r
-#define PVS_CPURD     (1 << 19) // CPU hold by FIFO full\r
-#define PVS_DMAPEND   (1 << 20) // DMA operation waiting for start\r
-#define PVS_DMAFILL   (1 << 21) // DMA fill is in progress\r
+#define PVS_CPUWR     (1 << 18) // CPU write blocked by FIFO full\r
+#define PVS_CPURD     (1 << 19) // CPU read blocked by FIFO not empty\r
+#define PVS_DMAFILL   (1 << 20) // DMA fill is waiting for fill data\r
 \r
 struct PicoVideo\r
 {\r

diff --git a/pico/videoport.c b/pico/videoport.c
index b9e0401..533c788 100644 (file)
--- a/pico/videoport.c
+++ b/pico/videoport.c
@@ -37,8 +37,10 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
  * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles\r
  * implies blocking the 68k up to that slot.\r
  *\r
- * A FIFO write goes to the end of the fifo queue. There can be more pending\r
- * writes than FIFO slots, but the 68k will be blocked in most of those cases.\r
+ * A FIFO write goes to the end of the FIFO queue, but DMA running in background\r
+ * is always the last queue entry (transfers by CPU intervene and come 1st).\r
+ * There can be more pending writes than FIFO slots, but the CPU will be blocked\r
+ * until FIFO level (without background DMA) <= 4.\r
  * This is only about correct timing, data xfer must be handled by the caller.\r
  * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be\r
  * executed by the caller.\r
@@ -50,16 +52,14 @@ int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned
  * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.\r
  */\r
 \r
-// FIFO transfer slots per line: H32 blank, H40 blank, H32 active, H40 active\r
-static const short vdpslots[] = { 166, 204, 16, 18 };\r
-// mapping between slot# and 68k cycles in a blanked scanline\r
-static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488, (16<<16)/488, (18<<16)/488 };\r
-static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204, (488<<16)/16, (488<<16)/18 };\r
+// mapping between slot# and 68k cycles in a blanked scanline [H32, H40]\r
+static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488 };\r
+static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204 };\r
 \r
 // VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538\r
 // 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:\r
 // (HINT=slot 0): 13,27,42,50,58,74,82,90,106,114,122,138,146,154,169,170\r
-const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #\r
+static const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 to slot #\r
 //  4  8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
  0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,\r
  1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,\r
@@ -70,14 +70,14 @@ const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #
 11,11,12,12,12,12,12,12,13,13,13,13,13,13,14,14,\r
 14,14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,\r
 };\r
-const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4 since HINT\r
-  0,  9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,123\r
+static const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4\r
+  0,  9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,131\r
 };\r
 \r
 // VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238\r
 // 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:\r
 // (HINT=0): 23,49,57,65,81,89,97,113,121,129,145,153,161,177,185,193,208,209\r
-const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #\r
+static const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 to slot #\r
 //  4  8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,\r
  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,\r
@@ -88,8 +88,8 @@ const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #
 13,13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,\r
 16,16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,\r
 };\r
-const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT\r
-  0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,123\r
+static const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4\r
+  0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,135\r
 };\r
 \r
 // NB code assumes fifo_* arrays have size 2^n\r
@@ -97,51 +97,79 @@ const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT
 static short fifo_data[4], fifo_dx; // XXX must go into save?\r
 \r
 // queued FIFO transfers, ...x = index, ...l = queue length\r
-// each entry has 2 values: [n]>>2=#writes, [n]&3=flags:2=DMA fill 1=byte access\r
+// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags\r
 static int fifo_queue[8], fifo_qx, fifo_ql; // XXX must go into save?\r
-unsigned int fifo_total;        // total# of pending FIFO entries\r
+enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!\r
+unsigned int fifo_total;        // total# of pending FIFO entries (w/o BGDMA)\r
 \r
 unsigned short fifo_slot;       // last executed slot in current scanline\r
 \r
+// map cycles to FIFO slot\r
+static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)\r
+{\r
+  int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+  int h40 = pv->reg[12] & 1;\r
+\r
+  if (active)  return (h40 ? vdpcyc2sl_40 : vdpcyc2sl_32)[cycles/4];\r
+  else         return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;\r
+}\r
+\r
+// map FIFO slot to cycles\r
+static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)\r
+{\r
+  int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+  int h40 = pv->reg[12] & 1;\r
+\r
+  if (active)  return (h40 ? vdpsl2cyc_40 : vdpsl2cyc_32)[slot]*4;\r
+  else         return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);\r
+}\r
+\r
 // do the FIFO math\r
 static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)\r
 {\r
-  int l = slots, b = fifo_queue[fifo_qx&7] & 1;\r
+  int l = slots, b = fifo_queue[fifo_qx] & FQ_BYTE;\r
 \r
+  // advance currently active FIFO entry\r
   if (l > pv->fifo_cnt)\r
     l = pv->fifo_cnt;\r
-  fifo_total -= ((pv->fifo_cnt & b) + l) >> b;\r
+  if (!(fifo_queue[fifo_qx] & FQ_BGDMA))\r
+    fifo_total -= ((pv->fifo_cnt & b) + l) >> b;\r
   pv->fifo_cnt -= l;\r
 \r
+  // if entry has been processed...\r
   if (pv->fifo_cnt == 0) {\r
+    if (fifo_ql) {\r
+      // terminate DMA if applicable\r
+      if ((pv->status & SR_DMA) && (fifo_queue[fifo_qx] & FQ_BGDMA)) {\r
+        pv->status &= ~SR_DMA;\r
+        pv->command &= ~0x80;\r
+      }\r
+      // remove entry from FIFO\r
+      fifo_qx ++, fifo_qx &= 7, fifo_ql --;\r
+    }\r
+    // start processing for next entry if there is one\r
     if (fifo_ql)\r
-      fifo_qx ++, fifo_ql --;\r
-    if (fifo_ql)\r
-      pv->fifo_cnt= (fifo_queue[fifo_qx&7] >> 2) << (fifo_queue[fifo_qx&7] & 1);\r
+      pv->fifo_cnt= (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);\r
     else\r
       fifo_total = 0;\r
   }\r
   return l;\r
 }\r
 \r
-static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)\r
-{\r
-  int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
-  int h40 = pv->reg[12] & 1;\r
-  const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
-\r
-  if (active)  return cs[cycles/4];\r
-  else         return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;\r
-}\r
-\r
-static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)\r
+static __inline void SetFIFOState(struct PicoVideo *pv)\r
 {\r
-  int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
-  int h40 = pv->reg[12] & 1;\r
-  const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;\r
-\r
-  if (active)  return sc[slot]*4;\r
-  else         return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);\r
+  // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
+  if (fifo_total == 0)\r
+    pv->status &= ~PVS_CPURD;\r
+  if (fifo_total <= 4) {\r
+    int x = (fifo_qx + fifo_ql - 1) & 7;\r
+    if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL) &&\r
+                fifo_ql && !(fifo_queue[x] & FQ_BGDMA)) {\r
+      pv->status &= ~SR_DMA;\r
+      pv->command &= ~0x80;\r
+    }\r
+    pv->status &= ~PVS_CPUWR;\r
+  }\r
 }\r
 \r
 // sync FIFO to cycles\r
@@ -161,57 +189,40 @@ void PicoVideoFIFOSync(int cycles)
     done -= l;\r
   }\r
 \r
-  // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
-  if (fifo_total <= 4) {\r
-    pv->status &= ~PVS_CPUWR;\r
-    pv->command &= ~0x80;\r
-    if (!(pv->status & PVS_DMAPEND))\r
-      pv->status &= ~(SR_DMA|PVS_DMAFILL);\r
-  }\r
-  if (fifo_total == 0)\r
-    pv->status &= ~PVS_CPURD;\r
+  SetFIFOState(pv);\r
 }\r
 \r
 // drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.\r
-int PicoVideoFIFODrain(int level, int cycles)\r
+int PicoVideoFIFODrain(int level, int cycles, int bgdma)\r
 {\r
   struct PicoVideo *pv = &Pico.video;\r
-  int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
-  int h40 = pv->reg[12] & 1;\r
-  int maxsl = vdpslots[h40 + 2*active]; // max xfer slots in this scanline\r
+  int maxsl = GetFIFOSlot(pv, 488); // max xfer slots in this scanline\r
   int burn = 0;\r
 \r
-  while (fifo_total > level && fifo_slot < maxsl) {\r
-    int b = fifo_queue[fifo_qx&7] & 1;\r
-    int cnt = (fifo_total-level) << b;\r
+  // process FIFO entries until low level is reached\r
+  while (fifo_total > level && fifo_slot < maxsl &&\r
+                 (!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {\r
+    int b = fifo_queue[fifo_qx] & FQ_BYTE;\r
+    int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);\r
     int last = fifo_slot;\r
-    int slot = (pv->fifo_cnt<cnt?pv->fifo_cnt:cnt) + last; // target slot\r
+    int slot = (pv->fifo_cnt < cnt ? pv->fifo_cnt : cnt) + last; // target slot\r
     unsigned ocyc = cycles;\r
 \r
     if (slot > maxsl) {\r
       // target in later scanline, advance to eol\r
       slot = maxsl;\r
-      fifo_slot = maxsl;\r
       cycles = 488;\r
     } else {\r
       // advance FIFO to target slot and CPU to cycles at that slot\r
-      fifo_slot = slot;\r
       cycles = GetFIFOCycles(pv, slot);\r
     }\r
+    fifo_slot = slot;\r
     burn += cycles - ocyc;\r
 \r
     AdvanceFIFOEntry(pv, slot - last);\r
   }\r
 \r
-  // release CPU and terminate DMA if FIFO isn't blocking the bus anymore\r
-  if (fifo_total <= 4) {\r
-    pv->status &= ~PVS_CPUWR;\r
-    pv->command &= ~0x80;\r
-    if (!(pv->status & PVS_DMAPEND))\r
-      pv->status &= ~(SR_DMA|PVS_DMAFILL);\r
-  }\r
-  if (fifo_total == 0)\r
-    pv->status &= ~PVS_CPURD;\r
+  SetFIFOState(pv);\r
 \r
   return burn;\r
 }\r
@@ -220,13 +231,13 @@ int PicoVideoFIFODrain(int level, int cycles)
 int PicoVideoFIFORead(void)\r
 {\r
   struct PicoVideo *pv = &Pico.video;\r
-  int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;\r
+  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
   int burn = 0;\r
 \r
   PicoVideoFIFOSync(lc);\r
 \r
   // advance FIFO and CPU until FIFO is empty\r
-  burn = PicoVideoFIFODrain(0, lc);\r
+  burn = PicoVideoFIFODrain(0, lc, 1);\r
   lc += burn;\r
   if (fifo_total > 0)\r
     pv->status |= PVS_CPURD; // target slot is in later scanline\r
@@ -243,34 +254,41 @@ int PicoVideoFIFORead(void)
 int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)\r
 {\r
   struct PicoVideo *pv = &Pico.video;\r
-  int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;\r
-  int burn = 0;\r
+  int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
+  int burn = 0, x;\r
 \r
   PicoVideoFIFOSync(lc);\r
   pv->status = (pv->status & ~sr_mask) | sr_flags;\r
 \r
   if (count && fifo_ql < 8) {\r
     // update FIFO state if it was empty\r
-    if (fifo_total == 0 && count) {\r
-      fifo_slot = GetFIFOSlot(pv, lc);\r
-      pv->fifo_cnt = count << (flags&1);\r
+    if (fifo_ql == 0) {\r
+      fifo_slot = GetFIFOSlot(pv, lc+10); // FIFO latency ~4 vdp slots\r
+      pv->fifo_cnt = count << (flags & FQ_BYTE);\r
     }\r
 \r
     // create xfer queue entry\r
-    int x = (fifo_qx + fifo_ql) & 7;\r
-    fifo_queue[x] = (count << 2) | flags;\r
+    x = (fifo_qx + fifo_ql - 1) & 7;\r
+    if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {\r
+      // CPU FIFO writes have priority over a background DMA Fill/Copy\r
+      fifo_queue[(x+1) & 7] = fifo_queue[x];\r
+      if (fifo_ql == 1) {\r
+        // XXX if interrupting a DMA fill, fill data changes\r
+        int f = fifo_queue[x] & 7;\r
+        fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
+        pv->fifo_cnt = count << (flags & FQ_BYTE);\r
+      }\r
+    } else\r
+      x = (x+1) & 7;\r
+    fifo_queue[x] = (count << 3) | flags;\r
     fifo_ql ++;\r
-    fifo_total += count;\r
+    if (!(flags & FQ_BGDMA))\r
+      fifo_total += count;\r
   }\r
 \r
   // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
-  if ((pv->status & (PVS_CPUWR|PVS_DMAFILL)) == PVS_CPUWR)\r
-    burn = PicoVideoFIFODrain(4, lc);\r
-  else if (fifo_queue[fifo_qx&7]&2) {\r
-    // if interrupting a DMA fill terminate it XXX wrong, changes fill data\r
-    AdvanceFIFOEntry(pv, pv->fifo_cnt);\r
-    pv->status &= ~PVS_DMAFILL;\r
-  }\r
+  if (pv->status & PVS_CPUWR)\r
+    burn = PicoVideoFIFODrain(4, lc, 0);\r
 \r
   return burn;\r
 }\r
@@ -287,7 +305,7 @@ int PicoVideoFIFOHint(void)
   // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
   if (pv->status & PVS_CPURD)\r
     burn = PicoVideoFIFORead();\r
-  if (pv->status & PVS_CPUWR)\r
+  else if (pv->status & PVS_CPUWR)\r
     burn = PicoVideoFIFOWrite(0, 0, 0, 0);\r
 \r
   return burn;\r
@@ -297,16 +315,15 @@ int PicoVideoFIFOHint(void)
 void PicoVideoFIFOMode(int active)\r
 {\r
   struct PicoVideo *pv = &Pico.video;\r
-  const unsigned char *cs = pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
   int h40 = pv->reg[12] & 1;\r
   int lc = SekCyclesDone() - Pico.t.m68c_line_start;\r
 \r
   PicoVideoFIFOSync(lc);\r
 \r
-  if (fifo_total) {\r
+  if (fifo_ql) {\r
     // recalculate FIFO slot for new mode\r
     if (!(pv->status & SR_VB) && active)\r
-          fifo_slot = cs[lc/4];\r
+          fifo_slot = (pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32)[lc/4];\r
     else  fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);\r
   }\r
 }\r
@@ -421,8 +438,8 @@ static void DmaSlow(int len, unsigned int source)
     Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),\r
     SekCyclesDone(), SekPc);\r
 \r
-  SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_DMAPEND,\r
-                                        SR_DMA | PVS_CPUWR) + 8);\r
+  SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),\r
+                              0, SR_DMA| PVS_CPUWR));\r
 \r
   if ((source & 0xe00000) == 0xe00000) { // Ram\r
     base = (u16 *)PicoMem.ram;\r
@@ -546,7 +563,8 @@ static void DmaCopy(int len)
   int source;\r
   elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());\r
 \r
-  SekCyclesBurnRun(PicoVideoFIFOWrite(len, 1, PVS_CPUWR | PVS_DMAPEND, SR_DMA));\r
+  SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,\r
+                              PVS_CPUWR, SR_DMA));\r
 \r
   source =Pico.video.reg[0x15];\r
   source|=Pico.video.reg[0x16]<<8;\r
@@ -577,8 +595,8 @@ static NOINLINE void DmaFill(int data)
   len = GetDmaLength();\r
   elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());\r
 \r
-  SekCyclesBurnRun(PicoVideoFIFOWrite(len, 2|(Pico.video.type == 1),\r
-                                          PVS_CPUWR | PVS_DMAPEND, SR_DMA));\r
+  SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),\r
+                              PVS_CPUWR | PVS_DMAFILL, SR_DMA));\r
 \r
   switch (Pico.video.type)\r
   {\r
@@ -648,7 +666,6 @@ static NOINLINE void CommandDma(void)
   u32 len, method;\r
   u32 source;\r
 \r
-  pvid->status |= PVS_DMAPEND;\r
   PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);\r
   if (pvid->status & SR_DMA) {\r
     elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",\r
@@ -748,12 +765,14 @@ PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d)
     VideoWrite(d);\r
 \r
     // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.\r
-    if ((pvid->status & (PVS_DMAPEND|PVS_DMAFILL)) == (PVS_DMAPEND|PVS_DMAFILL))\r
+    if (pvid->status & PVS_DMAFILL)\r
       DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);\r
 \r
     break;\r
 \r
   case 0x04: // Control (command) port 4 or 6\r
+    if (pvid->status & SR_DMA)\r
+      SekCyclesBurnRun(PicoVideoFIFORead()); // kludge, flush out running DMA\r
     if (pvid->pending)\r
     {\r
       // Low word of command:\r
@@ -886,14 +905,12 @@ static u32 VideoSr(const struct PicoVideo *pv)
   unsigned int hp = pv->reg[12]&1 ? 32:40; // HBLANK start\r
   unsigned int hl = pv->reg[12]&1 ? 94:84; // HBLANK length\r
 \r
-  c = SekCyclesDone();\r
-  if (c - Pico.t.m68c_line_start - hp < hl)\r
+  c = SekCyclesDone() - Pico.t.m68c_line_start;\r
+  if (c - hp < hl)\r
     d |= SR_HB;\r
 \r
-  PicoVideoFIFOSync(c-Pico.t.m68c_line_start);\r
-  if (pv->status & SR_DMA)\r
-    d |= SR_EMPT;       // unused by DMA, or rather flags not updated?\r
-  else if (fifo_total >= 4)\r
+  PicoVideoFIFOSync(c);\r
+  if (fifo_total >= 4)\r
     d |= SR_FULL;\r
   else if (!fifo_total)\r
     d |= SR_EMPT;\r
@@ -1010,7 +1027,7 @@ void PicoVideoSave(void)
 \r
   // account for all outstanding xfers XXX kludge, entry attr's not saved\r
   for (l = fifo_ql, x = fifo_qx + l-1; l > 1; l--, x--)\r
-    pv->fifo_cnt += (fifo_queue[x&7] >> 2) << (fifo_queue[x&7] & 1);\r
+    pv->fifo_cnt += (fifo_queue[x&7] >> 2) << (fifo_queue[x&7] & FQ_BYTE);\r
 }\r
 \r
 void PicoVideoLoad(void)\r