\r
\r
#ifndef _ASM_MEMORY_C\r
-// address must already be checked\r
-static int SRAMRead(u32 a)\r
+static\r
+#endif\r
+u32 SRAMRead(u32 a)\r
{\r
- u8 *d = SRam.data-SRam.start+a;\r
- return (d[0]<<8)|d[1];\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
+ Pico.m.sram_reg|=0x10; // should be normal SRAM\r
+ }\r
+ if(sreg & 4) // EEPROM read\r
+ return SRAMReadEEPROM();\r
+ else // if(sreg & 1) // (sreg&5) is one of prerequisites\r
+ return *(u8 *)(SRam.data-SRam.start+a);\r
}\r
-#endif\r
\r
+static void SRAMWrite(u32 a, u32 d)\r
+{\r
+ dprintf("sram_w: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
+ unsigned int sreg = Pico.m.sram_reg;\r
+ if(!(sreg & 0x10)) {\r
+ // not detected SRAM\r
+ if((a&~1)==0x200000) {\r
+ Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
+ SRam.start=0x200000; SRam.end=SRam.start+1;\r
+ }\r
+ Pico.m.sram_reg|=0x10;\r
+ }\r
+ if(sreg & 4) { // EEPROM write\r
+ if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
+ // just update pending state\r
+ SRAMUpdPending(a, d);\r
+ } else {\r
+ SRAMWriteEEPROM(sreg>>6); // execute pending\r
+ SRAMUpdPending(a, d);\r
+ lastSSRamWrite = SekCyclesDoneT();\r
+ }\r
+ } else if(!(sreg & 2)) {\r
+ u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
+ if(*pm != (u8)d) {\r
+ SRam.changed = 1;\r
+ *pm=(u8)d;\r
+ }\r
+ }\r
+}\r
\r
// for nonstandard reads\r
#ifndef _ASM_MEMORY_C\r
//if(a==0x200000) dprintf("cc : %02x @ %06x [%i|%i]", d, SekPc, SekCyclesDoneT(), SekCyclesDone());\r
//if(a==0x200001) dprintf("w8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
if(a >= SRam.start && a <= SRam.end) {\r
- dprintf("sram w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10)) {\r
- // not detected SRAM\r
- if((a&~1)==0x200000) {\r
- Pico.m.sram_reg|=4; // this should be a game with EEPROM (like NBA Jam)\r
- SRam.start=0x200000; SRam.end=SRam.start+1;\r
- }\r
- Pico.m.sram_reg|=0x10;\r
- }\r
- if(sreg & 4) { // EEPROM write\r
- if(SekCyclesDoneT()-lastSSRamWrite < 46) {\r
- // just update pending state\r
- SRAMUpdPending(a, d);\r
- } else {\r
- SRAMWriteEEPROM(sreg>>6); // execute pending\r
- SRAMUpdPending(a, d);\r
- lastSSRamWrite = SekCyclesDoneT();\r
- }\r
- } else if(!(sreg & 2)) {\r
- u8 *pm=(u8 *)(SRam.data-SRam.start+a);\r
- if(*pm != (u8)d) {\r
- SRam.changed = 1;\r
- *pm=(u8)d;\r
- }\r
- }\r
+ SRAMWrite(a, d);\r
return;\r
}\r
\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end) {\r
- unsigned int sreg = Pico.m.sram_reg;\r
- if(!(sreg & 0x10) && (sreg & 1) && a > 0x200001) { // not yet detected SRAM\r
- Pico.m.sram_reg|=0x10; // should be normal SRAM\r
- }\r
- if(sreg & 4) { // EEPROM read\r
- d = SRAMReadEEPROM();\r
- goto end;\r
- } else if(sreg & 1) {\r
- d = *(u8 *)(SRam.data-SRam.start+a);\r
- goto end;\r
- }\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
+ d = SRAMRead(a);\r
+ goto end;\r
}\r
#endif\r
\r
//if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
// dprintf("r8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
- //if(a==0x200001) dprintf("r8 : %02x @ %06x [%i]", d, SekPc, SekCyclesDoneT());\r
+ //if(a==0x200001||a==0x200000) printf("r8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
//dprintf("r8 : %06x, %02x @%06x [%03i]", a&0xffffff, (u8)d, SekPc, Pico.m.scanline);\r
#ifdef __debug_io\r
dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r
\r
#if !(defined(EMU_C68K) && defined(EMU_M68K))\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = SRAMRead(a);\r
+ d |= d<<8;\r
goto end;\r
}\r
#endif\r
end:\r
//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
// dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+ //if(a==0x200000) printf("r16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
#ifdef __debug_io\r
dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
a&=0xfffffe;\r
\r
// sram\r
- if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg & 1)) {\r
+ if(a >= SRam.start && a <= SRam.end && (Pico.m.sram_reg&5)) {\r
d = (SRAMRead(a)<<16)|SRAMRead(a+2);\r
+ d |= d<<8;\r
goto end;\r
}\r
\r
d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r
\r
end:\r
+ //if(a==0x200000) printf("r32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
#ifdef __debug_io\r
dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r
#endif\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
//if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r
+ //if(a==0x200000||a==0x200001) printf("w8 : %02x [%06x] @ %06x [%i]\n", d, a, SekPc, SekCyclesDoneT());\r
// dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r
\r
if ((a&0xe00000)==0xe00000) { *(u8 *)(Pico.ram+((a^1)&0xffff))=d; return; } // Ram\r
#endif\r
//if ((a&0xe0ffff)==0xe0AF0E+0x69c||(a&0xe0ffff)==0xe0A9A8+0x69c||(a&0xe0ffff)==0xe0A9AA+0x69c||(a&0xe0ffff)==0xe0A9AC+0x69c)\r
// dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r
+ //if(a==0x200000) printf("w16: %04x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r
log_io(a, 16, 1);\r
#if defined(EMU_C68K) && defined(EMU_M68K)\r
lastwrite_cyc_d[lwp_cyc++&15] = d;\r
#endif\r
+ //if(a==0x200000) printf("w32: %08x @ %06x [%i]\n", d, SekPc, SekCyclesDoneT());\r
\r
if ((a&0xe00000)==0xe00000)\r
{\r
.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read8_vdp @ 0xC00000 - 0xC7FFFF\r
.long m_read8_vdp @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read8_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read8_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read8_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read8_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read8_ram @ 0xF00000 - 0xF7FFFF\r
.long m_read_null @ 0xB00000 - 0xB7FFFF\r
.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read16_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read_null @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read16_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read16_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read16_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read16_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read16_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read16_ram @ 0xF00000 - 0xF7FFFF\r
.long m_read_null @ 0xB00000 - 0xB7FFFF\r
.long m_read_null @ 0xB80000 - 0xBFFFFF\r
.long m_read32_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read_null @ 0xC80000 - 0xCFFFFF\r
- .long m_read_null @ 0xD00000 - 0xD7FFFF\r
- .long m_read_null @ 0xD80000 - 0xDFFFFF\r
+ .long m_read32_vdp @ 0xC80000 - 0xCFFFFF\r
+ .long m_read32_vdp @ 0xD00000 - 0xD7FFFF\r
+ .long m_read32_vdp @ 0xD80000 - 0xDFFFFF\r
.long m_read32_ram @ 0xE00000 - 0xE7FFFF\r
.long m_read32_ram @ 0xE80000 - 0xEFFFFF\r
.long m_read32_ram @ 0xF00000 - 0xF7FFFF\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read8_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read8_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (1ci)\r
- sub r12,r0, #0x200000\r
- tst r1, #0x10\r
- bne m_read8_detected\r
- cmp r12,#1\r
- ble m_read8_detected\r
- tst r1, #1\r
- orrne r1, r1, #0x10\r
- strneb r1, [r3, #0x11]\r
-m_read8_detected:\r
- tst r1, #4 @ EEPROM read?\r
- bne SRAMReadEEPROM\r
-m_read8_noteeprom:\r
- tst r1, #1\r
- beq m_read8_nosram\r
- ldr r3, [r2] @ SRam.data\r
- ldr r2, [r2, #4] @ SRam.start (1ci)\r
- sub r3, r3, r2\r
- ldrb r0, [r3, r0]\r
- bx lr\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ bne SRAMRead\r
m_read8_nosram:\r
- ldr r1, [r3, #4] @ 1ci\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read16_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (2ci)\r
- tst r1, #1\r
- beq m_read16_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read16_nosram\r
- ldr r2, [r2] @ SRam.data (1ci)\r
- sub r2, r2, r1\r
- ldrh r0, [r2, r0] @ 2ci\r
- and r1, r0, #0xff\r
- mov r0, r0, lsr #8\r
- orr r0, r0, r1, lsl #8\r
- bx lr\r
-\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read16_nosram\r
+ stmfd sp!,{lr}\r
+ bl SRAMRead\r
+ orr r0, r0, r0, lsl #8\r
+ ldmfd sp!,{pc}\r
m_read16_nosram:\r
- ldr r1, [r3, #4] @ 1ci\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
b OtherRead16\r
\r
m_read16_vdp:\r
- tst r0, #0x70000\r
+ tst r0, #0x70000 @ if ((a&0xe700e0)==0xc00000)\r
tsteq r0, #0x000e0\r
bxne lr @ invalid read\r
bic r0, r0, #1\r
orr r0, r0, #0x200000\r
cmp r0, r1\r
bgt m_read32_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg (2ci)\r
- tst r1, #1\r
- beq m_read32_nosram\r
- ldr r1, [r2, #4] @ SRam.start (1ci)\r
+ ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read32_nosram\r
- ldr r2, [r2] @ SRam.data (1ci)\r
- sub r2, r2, r1\r
- ldrh r0, [r2, r0]! @ (1ci)\r
- ldrh r1, [r2, #2]\r
- orr r0, r0, r0, lsl #16\r
- mov r0, r0, ror #8\r
- mov r0, r0, lsl #16\r
- orr r0, r0, r1, lsr #8\r
- and r1, r1, #0xff\r
- orr r0, r0, r1, lsl #8\r
+ ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ tst r1, #5\r
+ beq m_read32_nosram\r
+ stmfd sp!,{r0,lr}\r
+ bl SRAMRead\r
+ ldmfd sp!,{r1,lr}\r
+ stmfd sp!,{r0,lr}\r
+ add r0, r1, #2\r
+ bl SRAMRead\r
+ ldmfd sp!,{r1,lr}\r
+ orr r0, r1, r0, lsl #16\r
+ orr r0, r0, r0, lsl #8\r
bx lr\r
-\r
m_read32_nosram:\r
- ldr r1, [r3, #4] @ (1ci)\r
+ ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
return;
}
- OtherWrite8End(a, d>>8, 16);
- OtherWrite8End(a+1,d&0xff, 16);
+ if (a >= SRam.start && a <= SRam.end) {
+ if ((a&0x16)==0x10) { // detected, not EEPROM, write not disabled
+ u8 *pm=(u8 *)(SRam.data-SRam.start+a);
+ *pm++=d>>8;
+ *pm++=d;
+ SRam.changed = 1;
+ }
+ else
+ SRAMWrite(a, d); // ??
+ return;
+ }
+ //OtherWrite8End(a, d>>8, 16);
+ //OtherWrite8End(a+1,d&0xff, 16);
}
{\r
unsigned int sreg = Pico.m.sram_reg, saddr = Pico.m.sram_addr, scyc = Pico.m.sram_cycle, ssa = Pico.m.sram_slave;\r
\r
- //dprintf("[%02x]", d);\r
+ //printf("EEPROM write %i\n", d&3);\r
sreg |= saddr&0xc000; // we store word count in add reg: dw?a aaaa ... (d=word count detected, w=words(0==use 2 words, else 1))\r
saddr&=0x1fff;\r
\r
if((sreg & 1) && !(d&1)) {\r
// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter\r
//dprintf("-start-");\r
- if(!(sreg&0x8000) && scyc >= 9) {\r
- if(scyc != 28) sreg |= 0x4000; // 1 word\r
+ if(!(sreg&0x8000) && scyc >= 9) {\r
+ if(scyc != 28) sreg |= 0x4000; // 1 word\r
//dprintf("detected word count: %i", scyc==28 ? 2 : 1);\r
- sreg |= 0x8000;\r
- }\r
+ sreg |= 0x8000;\r
+ }\r
//saddr = 0;\r
scyc = 0;\r
sreg |= 8;\r
else if((sreg & 8) && !(sreg & 2) && (d&2)) {\r
// we are started and SCL went high - next cycle\r
scyc++; // pre-increment\r
- if(sreg & 0x20) {\r
+ if(sreg & 0x20) {\r
// X24C02+\r
- if((ssa&1) && scyc == 18) {\r
- scyc = 9;\r
- saddr++; // next address in read mode\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
- }\r
- else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
- else if(scyc == 36) scyc = 27;\r
- } else {\r
- // X24C01\r
+ if((ssa&1) && scyc == 18) {\r
+ scyc = 9;\r
+ saddr++; // next address in read mode\r
+ if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ }\r
+ else if((sreg&0x4000) && scyc == 27) scyc = 18;\r
+ else if(scyc == 36) scyc = 27;\r
+ } else {\r
+ // X24C01\r
if(scyc == 18) {\r
scyc = 9; // wrap\r
if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode\r
- }\r
- }\r
- //dprintf("scyc: %i", scyc);\r
+ }\r
+ }\r
+ //dprintf("scyc: %i", scyc);\r
}\r
else if((sreg & 8) && (sreg & 2) && !(d&2)) {\r
// we are started and SCL went low (falling edge)\r
if(sreg & 0x20) {\r
- // X24C02+\r
- if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
- else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
+ // X24C02+\r
+ if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
+ else if( (!(sreg&0x4000) && scyc > 27) || ((sreg&0x4000) && scyc > 18) ) {\r
if(!(ssa&1)) {\r
// data write\r
unsigned char *pm=SRam.data+saddr;\r
} else if(scyc > 9) {\r
if(!(ssa&1)) {\r
// we latch another addr bit\r
- saddr<<=1;\r
- if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
- saddr|=d&1;\r
+ saddr<<=1;\r
+ if(sreg&0x4000) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ saddr|=d&1;\r
//if(scyc==17||scyc==26) dprintf("addr reg done: %x", saddr);\r
- }\r
+ }\r
} else {\r
- // slave address\r
- ssa<<=1; ssa|=d&1;\r
+ // slave address\r
+ ssa<<=1; ssa|=d&1;\r
//if(scyc==8) dprintf("slave done: %x", ssa);\r
}\r
- } else {\r
- // X24C01\r
+ } else {\r
+ // X24C01\r
if(scyc == 9); // ACK cycle, do nothing\r
else if(scyc > 9) {\r
if(!(saddr&1)) {\r
saddr<<=1; saddr|=d&1; saddr&=0xff;\r
//if(scyc==8) dprintf("addr done: %x", saddr>>1);\r
}\r
- }\r
+ }\r
}\r
\r
sreg &= ~3; sreg |= d&3; // remember SCL and SDA\r
// started and first command word received\r
shift = 17-scyc;\r
if(sreg & 0x20) {\r
- // X24C02+\r
+ // X24C02+\r
if(ssa&1) {\r
//dprintf("read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
- d = (SRam.data[saddr]>>shift)&1;\r
- }\r
- } else {\r
- // X24C01\r
+ d = (SRam.data[saddr]>>shift)&1;\r
+ }\r
+ } else {\r
+ // X24C01\r
if(saddr&1) {\r
- d = (SRam.data[saddr>>1]>>shift)&1;\r
- }\r
- }\r
+ d = (SRam.data[saddr>>1]>>shift)&1;\r
+ }\r
+ }\r
}\r
//else dprintf("r ack");\r
\r
dstrp+=strlen(dstrp);\r
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,\r
bit(Pico.m.sram_reg, 4), bit(Pico.m.sram_reg, 2)); dstrp+=strlen(dstrp);\r
+ sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); dstrp+=strlen(dstrp);\r
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status);\r
dstrp+=strlen(dstrp);\r
#ifdef EMU_C68K\r
notaz.gp2x.de / picodrive.git / commitdiff