CPU->ICount -= CPU->ExtraCycles;\r
CPU->ExtraCycles = 0;\r
}\r
- goto Cz80_Exec;\r
+ if (!CPU->HaltState)\r
+ goto Cz80_Exec;\r
}\r
}\r
else CPU->ICount = 0;\r
OP(0x76): // HALT\r
OP_HALT:\r
CPU->HaltState = 1;\r
-// CPU->ICount = 0;\r
goto Cz80_Check_Interrupt;\r
\r
OP(0xf3): // DI\r
\r
static void PicoWrite16_vdp(u32 a, u32 d)\r
{\r
- if ((a & 0x00f9) == 0x0010) // PSG Sound\r
+ if ((a & 0x00f9) == 0x0010) { // PSG Sound\r
psg_write_68k(d);\r
+ return;\r
+ }\r
if ((a & 0x00e0) == 0x0000) {\r
PicoVideoWrite(a, d);\r
return;\r
int xcycles = z80_cycles << 8;\r
\r
/* check for overflows */\r
- if ((mode_old & 4) && xcycles > Pico.t.timer_a_next_oflow)\r
+ if ((mode_old & 4) && xcycles >= Pico.t.timer_a_next_oflow)\r
ym2612.OPN.ST.status |= 1;\r
\r
- if ((mode_old & 8) && xcycles > Pico.t.timer_b_next_oflow)\r
+ if ((mode_old & 8) && xcycles >= Pico.t.timer_b_next_oflow)\r
ym2612.OPN.ST.status |= 2;\r
\r
/* update timer a */\r
void ym2612_unpack_state(void);\r
\r
#define TIMER_NO_OFLOW 0x70000000\r
-// tA = 72 * (1024 - NA) / M\r
-#define TIMER_A_TICK_ZCYCLES 17203\r
-// tB = 1152 * (256 - NA) / M\r
-#define TIMER_B_TICK_ZCYCLES 262800 // 275251 broken, see Dai Makaimura\r
+// tA = 72 * (1024 - NA) / M, with M = mclock/2 -> tick = 72 * 2/mclock\r
+#define TIMER_A_TICK_ZCYCLES 17203 // zcycles = Q8*tick*zclock = Q8*77*2*7/15\r
+// tB = 1152 * (256 - NA) / M,\r
+#define TIMER_B_TICK_ZCYCLES 275251 // zcycles = Q8*1152*2*7/15\r
\r
#define timers_cycle() \\r
if (Pico.t.timer_a_next_oflow > 0 && Pico.t.timer_a_next_oflow < TIMER_NO_OFLOW) \\r
#define timers_reset() \\r
Pico.t.timer_a_next_oflow = Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW; \\r
Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * 1024; \\r
- Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * 256;\r
+ Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * 256; \\r
+ ym2612.OPN.ST.status &= ~3;\r
\r
\r
// videoport.c\r
.macro update_ssg_eg
ldrh r0, [r5,#0x30] @ ssg+ssgn
ldrb r2, [r5,#0x17] @ state
+ and r3, r0, #0x08
+ cmp r3, #0x08 @ ssg enabled &&
ldrh r3, [r5,#0x1a] @ volume
- cmp r0, #0x08 @ ssg enabled &&
cmpge r2, #EG_REL+1 @ state > EG_REL &&
cmpge r3, #0x200 @ volume >= 0x200?
blt 9f