\r
struct Cyclone\r
{\r
- unsigned int d[8]; // [r7,#0x00]\r
- unsigned int a[8]; // [r7,#0x20]\r
- unsigned int pc; // [r7,#0x40] Memory Base+PC\r
- unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
- unsigned char xc; // [r7,#0x45] Extend flag (____??X?)\r
- unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
- unsigned char irq; // [r7,#0x47] IRQ level\r
- unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
- unsigned int vector; // [r7,#0x4c] IRQ vector (temporary)\r
- unsigned int prev_pc;// [r7,#0x50] set to start address of currently executed opcode + 2 (if enabled in config.h)\r
- unsigned int unused; // [r7,#0x54] Unused\r
- int stopped; // [r7,#0x58] 1 == processor is in stopped state\r
- int cycles; // [r7,#0x5c]\r
- int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
+ unsigned int d[8]; // [r7,#0x00]\r
+ unsigned int a[8]; // [r7,#0x20]\r
+ unsigned int pc; // [r7,#0x40] Memory Base+PC\r
+ unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
+ unsigned char unused; // [r7,#0x45] Unused\r
+ unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
+ unsigned char irq; // [r7,#0x47] IRQ level\r
+ unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
+ unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r
+ unsigned int prev_pc; // [r7,#0x50] set to start address of currently executed opcode + 2 (if enabled in config.h)\r
+ unsigned int unused1; // [r7,#0x54] Unused\r
+ int stopped; // [r7,#0x58] 1 == processor is in stopped state\r
+ int cycles; // [r7,#0x5c]\r
+ int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc\r
unsigned char (*read8 )(unsigned int a); // [r7,#0x68]\r
unsigned short (*read16 )(unsigned int a); // [r7,#0x6c]\r
// 110nnn - An + Disp + D/An\r
int areg=0,ext=0,off=0,da=0,reg=0,wol=0,scale=0;\r
ext=DisaWord(DisaPc)&0xffff;\r
- \r
+\r
areg=ea&7;\r
off=ext&0xff; da =ext&0x8000?'a':'d';\r
reg=(ext>>12)&7; wol=ext&0x0800?'l':'w';\r
// 111011 - PC Relative + D/An\r
int ext=0,off=0,da=0,reg=0,wol=0,scale=0;\r
ext=DisaWord(DisaPc)&0xffff;\r
- \r
+\r
off=ext&0xff; da =ext&0x8000?'a':'d';\r
reg=(ext>>12)&7; wol=ext&0x0800?'l':'w';\r
scale=1<<((ext>>9)&3);\r
\r
sea = op&0x003f;\r
DisaGetEa(seat,sea,size);\r
- \r
+\r
dea =(op&0x01c0)>>3;\r
dea|=(op&0x0e00)>>9;\r
DisaGetEa(deat,dea,size);\r
return 0;\r
}\r
\r
+static int OpChk(op)\r
+{\r
+ int sea=0,dea=0;\r
+ char seat[64]="",deat[64]="";\r
+\r
+ sea=op&0x003f;\r
+ DisaGetEa(seat,sea,0);\r
+\r
+ dea=(op>>9)&7; dea|=8;\r
+ DisaGetEa(deat,dea,2);\r
+\r
+ sprintf(DisaText,"chk %s, %s",seat,deat);\r
+ return 0;\r
+}\r
+\r
// ================ Opcodes 0x41c0+ ================\r
static int DisaLea(int op)\r
{\r
for (i=0;i<17;i++)\r
{\r
int bit=0;\r
- \r
+\r
// Mask off bit i:\r
if (reverse) bit=0x8000>>i; else bit=1<<i;\r
bit&=mask;\r
\r
// Knock off trailing '/'\r
len=strlen(list);\r
- if (len>0) if (list[len-1]=='/') list[len-1]=0; \r
+ if (len>0) if (list[len-1]=='/') list[len-1]=0;\r
+ return 0;\r
+}\r
+\r
+// ================ Opcodes 0x4800+ ================\r
+static int DisaNbcd(int op)\r
+{\r
+ // Nbcd 01001000 00eeeeee (eeeeee=ea)\r
+ int ea=0;\r
+ char eat[64]="";\r
+\r
+ ea=op&0x003f;\r
+ DisaGetEa(eat,ea,0);\r
+\r
+ sprintf(DisaText,"nbcd %s",eat);\r
return 0;\r
}\r
\r
// ================ Opcodes 0x4850+ ================\r
static int DisaPea(int op)\r
{\r
- // Pea 01001000 01eeeeee (eeeeee=ea) pea \r
+ // Pea 01001000 01eeeeee (eeeeee=ea) pea\r
int ea=0;\r
char eat[64]="";\r
\r
sprintf(DisaText,"%s",inst[n]);\r
\r
//todo - 'stop' with 16 bit data\r
- \r
+\r
return 0;\r
}\r
\r
return 0;\r
}\r
\r
+static int DisaTas(int op)\r
+{\r
+ // Tas 01001010 11eeeeee (eeeeee=ea)\r
+ int ea=0;\r
+ char eat[64]="";\r
+\r
+ ea=op&0x003f;\r
+ DisaGetEa(eat,ea,0);\r
+\r
+ sprintf(DisaText,"tas %s",eat);\r
+ return 0;\r
+}\r
+\r
// ================ Opcodes 0x4e80+ ================\r
static int DisaJsr(int op)\r
{\r
return 0;\r
}\r
\r
+static int DisaCmpm(int op)\r
+{\r
+ char seat[64]="",deat[64]="";\r
+ int type=0,size=0,sea,dea;\r
+\r
+ type=(op>>8)&1;\r
+ size=(op>>6)&3; if (size>=3) return 1;\r
+ sea=(op&7)|0x18;\r
+ dea=(op>>9)&0x3f;\r
+ DisaGetEa(seat,sea,size);\r
+ DisaGetEa(deat,dea,size);\r
+\r
+ sprintf(DisaText,"cmpm.%c %s, %s",Tasm[size],seat,deat);\r
+ return 0;\r
+}\r
+\r
+\r
// ================ Opcodes 0xc140+ ================\r
// 1100ttt1 01000sss exg ds,dt\r
// 1100ttt1 01001sss exg as,at\r
static int DisaAddx(int op)\r
{\r
// 1t01ddd1 xx000sss addx\r
- int type=0,size=0,dea=0,sea=0;\r
+ int type=0,size=0,dea=0,sea=0,mem;\r
char deat[64]="",seat[64]="";\r
char *opcode[6]={"","subx","","","","addx"};\r
\r
type=(op>>12)&5;\r
dea =(op>> 9)&7;\r
size=(op>> 6)&3; if (size>=3) return 1;\r
- sea = op&0x3f;\r
+ sea = op&7;\r
+ mem = op&8;\r
+ if(mem) { sea+=0x20; dea+=0x20; }\r
\r
DisaGetEa(deat,dea,size);\r
DisaGetEa(seat,sea,size);\r
\r
static int DisaAsrEa(int op)\r
{\r
- // Asr/l/Ror/l etc EA - 11100ttd 11eeeeee \r
+ // Asr/l/Ror/l etc EA - 11100ttd 11eeeeee\r
int type=0,dir=0,size=1;\r
char eat[64]="";\r
\r
if ((op&0xff00)==0x0800) DisaBtstImm(op); // Btst/Bchg/Bclr/Bset\r
if ((op&0xc000)==0x0000) DisaMove(op);\r
if ((op&0xf900)==0x4000) DisaNeg(op); // Negx/Clr/Neg/Not\r
+ if ((op&0xf140)==0x4100) OpChk(op);\r
if ((op&0xf1c0)==0x41c0) DisaLea(op);\r
if ((op&0xf9c0)==0x40c0) DisaMoveSr(op);\r
+ if ((op&0xffc0)==0x4800) DisaNbcd(op);\r
if ((op&0xfff8)==0x4840) DisaSwap(op);\r
if ((op&0xffc0)==0x4840) DisaPea(op);\r
if ((op&0xffb8)==0x4880) DisaExt(op);\r
if ((op&0xfb80)==0x4880) DisaMovem(op);\r
if ((op&0xff00)==0x4a00) DisaTst(op);\r
+ if ((op&0xffc0)==0x4ac0) DisaTas(op);\r
if ((op&0xfff0)==0x4e40) DisaTrap(op);\r
if ((op&0xfff8)==0x4e50) DisaLink(op);\r
if ((op&0xfff8)==0x4e58) DisaUnlk(op);\r
if ((op&0xf100)==0x7000) DisaMoveq(op);\r
if ((op&0x90c0)==0x90c0) DisaAritha(op);\r
if ((op&0xf000)==0xb000) DisaCmpEor(op);\r
+ if ((op&0xf138)==0xb108) DisaCmpm(op);\r
if ((op&0xf130)==0xc100) DisaExg(op);\r
if ((op&0xf000)==0xe000) DisaAsr(op);\r
if ((op&0xf8c0)==0xe0c0) DisaAsrEa(op);\r
\r
if (ea>=8) needor=1; // Need to OR to access A0-7\r
\r
- if ((mask>>low)&8) if (ea&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8\r
+ if (((mask&g_op)>>low)&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8\r
\r
if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;)\r
\r
}\r
\r
// EaCalc - ARM Register 'a' = Effective Address\r
-// Trashes r0,r2 and r3\r
+// If ea>=0x10, trashes r0,r2 and r3, else nothing\r
// size values 0, 1, 2 ~ byte, word, long\r
+// mask shows usable bits in r8\r
int EaCalc(int a,int mask,int ea,int size,int top,int sign_extend)\r
{\r
char text[32]="";\r
\r
if ((ea&7)==7 && step<2) step=2; // move.b (a7)+ or -(a7) steps by 2 not 1\r
\r
- EaCalcReg(2,ea,mask,0,0,1);\r
- if(mask)\r
- for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
- lsl=2-low; // Having a lsl #x here saves one opcode\r
- if (lsl>=0) ot(" ldr r%d,[r7,r2,lsl #%i]\n",a,lsl);\r
- else if (lsl<0) ot(" ldr r%d,[r7,r2,lsr #%i]\n",a,-lsl);\r
+ if (ea==0x1f||ea==0x27) // A7 handlers are always separate\r
+ {\r
+ ot(" ldr r%d,[r7,#0x3c] ;@ A7\n",a);\r
+ }\r
+ else\r
+ {\r
+ EaCalcReg(2,ea,mask,0,0,1);\r
+ if(mask)\r
+ for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
+ lsl=2-low; // Having a lsl #x here saves one opcode\r
+ if (lsl>=0) ot(" ldr r%d,[r7,r2,lsl #%i]\n",a,lsl);\r
+ else if (lsl<0) ot(" ldr r%d,[r7,r2,lsr #%i]\n",a,-lsl);\r
+ }\r
\r
if ((ea&0x38)==0x18) // (An)+\r
{\r
\r
if ((ea&0x38)==0x18||(ea&0x38)==0x20)\r
{\r
- if (lsl>=0) ot(" str r%d,[r7,r2,lsl #%i]\n",strr,lsl);\r
- else if (lsl<0) ot(" str r%d,[r7,r2,lsr #%i]\n",strr,-lsl);\r
+ if (ea==0x1f||ea==0x27)\r
+ {\r
+ ot(" str r%d,[r7,#0x3c] ;@ A7\n",strr);\r
+ }\r
+ else\r
+ {\r
+ if (lsl>=0) ot(" str r%d,[r7,r2,lsl #%i]\n",strr,lsl);\r
+ else if (lsl<0) ot(" str r%d,[r7,r2,lsr #%i]\n",strr,-lsl);\r
+ }\r
}\r
\r
if ((ea&0x38)==0x20) Cycles+=size<2 ? 6:10; // -(An) Extra cycles\r
}\r
\r
ot(" ldrh r2,[r4],#2 ;@ Fetch immediate value\n");\r
- ot(" ldrh r0,[r4],#2\n"); pc_dirty=1;\r
- ot(" orr r%d,r0,r2,lsl #16\n",a);\r
+ ot(" ldrh r3,[r4],#2\n"); pc_dirty=1;\r
+ ot(" orr r%d,r3,r2,lsl #16\n",a);\r
Cycles+=8; // Extra cycles\r
return 0;\r
}\r
lsl=2-low; // Having a lsl #2 here saves one opcode\r
}\r
\r
- if (top) nsarm=3;\r
+ if (top||!sign_extend) nsarm=3;\r
\r
ot(";@ EaRead : Read register[r%d] into r%d:\n",a,v);\r
\r
ot("\n"); return 0;\r
}\r
\r
+// calculate EA and read\r
+// if (ea < 0x10) nothing is trashed\r
+// if (ea == 0x3c) r2 and r3 are trashed\r
+// else r0-r3 are trashed\r
+// size values 0, 1, 2 ~ byte, word, long\r
+// r_ea is reg to store ea in (-1 means ea is not needed), r is dst reg\r
+// if sign_extend is 0, non-32bit values will have MS bits undefined\r
+int EaCalcRead(int r_ea,int r,int ea,int size,int mask,int sign_extend)\r
+{\r
+ if (ea<0x10)\r
+ {\r
+ if (r_ea==-1)\r
+ {\r
+ r_ea=r;\r
+ if (!sign_extend) size=2;\r
+ }\r
+ }\r
+ else if (ea==0x3c) // #imm\r
+ {\r
+ r_ea=r;\r
+ }\r
+ else\r
+ {\r
+ if (r_ea==-1) r_ea=0;\r
+ }\r
+\r
+ EaCalc (r_ea,mask,ea,size,0,sign_extend);\r
+ EaRead (r_ea, r,ea,size,mask,0,sign_extend);\r
+\r
+ return 0;\r
+}\r
+\r
+int EaCalcReadNoSE(int r_ea,int r,int ea,int size,int mask)\r
+{\r
+ return EaCalcRead(r_ea,r,ea,size,mask,0);\r
+}\r
+\r
// Return 1 if we can read this ea\r
int EaCanRead(int ea,int size)\r
{\r
ot(" bx lr\n");\r
ot("\n");\r
#endif\r
+ // 68k: XNZVC, ARM: NZCV\r
if (ms) ot("CycloneSetSr\n");\r
else ot("CycloneSetSr:\n");\r
ot(" mov r2,r1,lsr #8\n");\r
ot(" str r3,[r0,#0x3C]\n");\r
ot(" str r2,[r0,#0x48]\n");\r
ot("setsr_noswap%s\n",ms?"":":");\r
- ot(" mov r2,r1,lsr #3\n");\r
- ot(" strb r2,[r0,#0x45] ;@ the X flag\n");\r
+ ot(" mov r2,r1,lsl #25\n");\r
+ ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
ot(" bic r2,r1,#0xf3\n");\r
ot(" tst r1,#1\n");\r
ot(" orrne r2,r2,#2\n");\r
ot(" orrne r2,r2,#2\n");\r
ot(" tst r1,#2\n");\r
ot(" orrne r2,r2,#1\n");\r
- ot(" ldrb r1,[r0,#0x45] ;@ the X flag\n");\r
- ot(" tst r1,#2\n");\r
+ ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
+ ot(" tst r1,#0x20000000\n");\r
ot(" orrne r2,r2,#0x10\n");\r
ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
ot(" orr r0,r2,r1,lsl #8\n");\r
addrreg=0;\r
#endif\r
if (addrreg != 0)\r
+ {\r
+ ot(" add lr,pc,#4\n"); // helps to prevent interlocks\r
ot(" mov r0,r%i\n", addrreg);\r
- ot(" mov lr,pc\n");\r
+ }\r
+ else\r
+ ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
\r
// Document what we are calling:\r
ot(" mov r0,#0x10\n");\r
ot(" bl Exception\n");\r
#endif\r
+ ot("\n");\r
Cycles=34;\r
OpEnd();\r
\r
ot(" mov r0,#0x28\n");\r
ot(" bl Exception\n");\r
#endif\r
+ ot("\n");\r
Cycles=4;\r
OpEnd();\r
\r
ot(" mov r0,#0x2c\n");\r
ot(" bl Exception\n");\r
#endif\r
+ ot("\n");\r
Cycles=4;\r
OpEnd();\r
\r
ot("\n");\r
}\r
\r
-int OpBase(int op,int sepa)\r
+int OpBase(int op,int size,int sepa)\r
{\r
int ea=op&0x3f; // Get Effective Address\r
if (ea<0x10) return sepa?(op&~0x7):(op&~0xf); // Use 1 handler for d0-d7 and a0-a7\r
- if (ea>=0x18 && ea<0x28 && (ea&7)==7) return op; // Specific handler for (a7)+ and -(a7)\r
+ if (size==0&&(ea==0x1f || ea==0x27)) return op; // Specific handler for (a7)+ and -(a7)\r
if (ea<0x38) return op&~7; // Use 1 handler for (a0)-(a7), etc...\r
return op;\r
}\r
\r
if (xbit)\r
{\r
- ot(" mov r2,r9,lsr #28\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Save X bit\n");\r
+ ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");\r
}\r
return 0;\r
}\r
\r
// -----------------------------------------------------------------\r
\r
+int g_op;\r
+\r
void OpAny(int op)\r
{\r
memset(OpData,0x33,sizeof(OpData));\r
OpData[0]=(unsigned char)(op>>8);\r
OpData[1]=(unsigned char)op;\r
-\r
- if ((op&0xf100)==0x0000) OpArith(op);\r
- if ((op&0xc000)==0x0000) OpMove(op);\r
- if ((op&0xf5bf)==0x003c) OpArithSr(op); // Ori/Andi/Eori $nnnn,sr\r
- if ((op&0xf100)==0x0100) OpBtstReg(op);\r
- if ((op&0xf138)==0x0108) OpMovep(op);\r
- if ((op&0xff00)==0x0800) OpBtstImm(op);\r
- if ((op&0xf900)==0x4000) OpNeg(op);\r
- if ((op&0xf140)==0x4100) OpChk(op);\r
- if ((op&0xf1c0)==0x41c0) OpLea(op);\r
- if ((op&0xf9c0)==0x40c0) OpMoveSr(op);\r
- if ((op&0xffc0)==0x4800) OpNbcd(op);\r
- if ((op&0xfff8)==0x4840) OpSwap(op);\r
- if ((op&0xffc0)==0x4840) OpPea(op);\r
- if ((op&0xffb8)==0x4880) OpExt(op);\r
- if ((op&0xfb80)==0x4880) OpMovem(op);\r
- if ((op&0xff00)==0x4a00) OpTst(op);\r
- if ((op&0xffc0)==0x4ac0) OpTas(op);\r
- if ((op&0xfff0)==0x4e40) OpTrap(op);\r
- if ((op&0xfff8)==0x4e50) OpLink(op);\r
- if ((op&0xfff8)==0x4e58) OpUnlk(op);\r
- if ((op&0xfff0)==0x4e60) OpMoveUsp(op);\r
- if ((op&0xfff8)==0x4e70) Op4E70(op); // Reset/Rts etc\r
- if ((op&0xfffd)==0x4e70) OpStopReset(op);\r
- if ((op&0xff80)==0x4e80) OpJsr(op);\r
- if ((op&0xf000)==0x5000) OpAddq(op);\r
- if ((op&0xf0c0)==0x50c0) OpSet(op);\r
- if ((op&0xf0f8)==0x50c8) OpDbra(op);\r
- if ((op&0xf000)==0x6000) OpBranch(op);\r
- if ((op&0xf100)==0x7000) OpMoveq(op);\r
- if ((op&0xa000)==0x8000) OpArithReg(op); // Or/Sub/And/Add\r
- if ((op&0xb1f0)==0x8100) OpAbcd(op);\r
- if ((op&0xb0c0)==0x80c0) OpMul(op);\r
- if ((op&0x90c0)==0x90c0) OpAritha(op);\r
- if ((op&0xb130)==0x9100) OpAddx(op);\r
- if ((op&0xf000)==0xb000) OpCmpEor(op);\r
- if ((op&0xf138)==0xb108) OpCmpm(op);\r
- if ((op&0xf130)==0xc100) OpExg(op);\r
- if ((op&0xf000)==0xe000) OpAsr(op); // Asr/l/Ror/l etc\r
- if ((op&0xf8c0)==0xe0c0) OpAsrEa(op);\r
+ g_op=op;\r
+\r
+ if ((op&0xf100)==0x0000) OpArith(op); // +\r
+ if ((op&0xc000)==0x0000) OpMove(op); // +\r
+ if ((op&0xf5bf)==0x003c) OpArithSr(op); // + Ori/Andi/Eori $nnnn,sr\r
+ if ((op&0xf100)==0x0100) OpBtstReg(op); // +\r
+ if ((op&0xf138)==0x0108) OpMovep(op); // +\r
+ if ((op&0xff00)==0x0800) OpBtstImm(op); // +\r
+ if ((op&0xf900)==0x4000) OpNeg(op); // +\r
+ if ((op&0xf140)==0x4100) OpChk(op); // +\r
+ if ((op&0xf1c0)==0x41c0) OpLea(op); // +\r
+ if ((op&0xf9c0)==0x40c0) OpMoveSr(op); // +\r
+ if ((op&0xffc0)==0x4800) OpNbcd(op); // +\r
+ if ((op&0xfff8)==0x4840) OpSwap(op); // +\r
+ if ((op&0xffc0)==0x4840) OpPea(op); // +\r
+ if ((op&0xffb8)==0x4880) OpExt(op); // +\r
+ if ((op&0xfb80)==0x4880) OpMovem(op); // +\r
+ if ((op&0xff00)==0x4a00) OpTst(op); // +\r
+ if ((op&0xffc0)==0x4ac0) OpTas(op); // +\r
+ if ((op&0xfff0)==0x4e40) OpTrap(op); // +\r
+ if ((op&0xfff8)==0x4e50) OpLink(op); // +\r
+ if ((op&0xfff8)==0x4e58) OpUnlk(op); // +\r
+ if ((op&0xfff0)==0x4e60) OpMoveUsp(op); // +\r
+ if ((op&0xfff8)==0x4e70) Op4E70(op); // + Reset/Rts etc\r
+ if ((op&0xfffd)==0x4e70) OpStopReset(op);// +\r
+ if ((op&0xff80)==0x4e80) OpJsr(op); // +\r
+ if ((op&0xf000)==0x5000) OpAddq(op); // +\r
+ if ((op&0xf0c0)==0x50c0) OpSet(op); // +\r
+ if ((op&0xf0f8)==0x50c8) OpDbra(op); // +\r
+ if ((op&0xf000)==0x6000) OpBranch(op); // +\r
+ if ((op&0xf100)==0x7000) OpMoveq(op); // +\r
+ if ((op&0xa000)==0x8000) OpArithReg(op); // + Or/Sub/And/Add\r
+ if ((op&0xb1f0)==0x8100) OpAbcd(op); // +\r
+ if ((op&0xb0c0)==0x80c0) OpMul(op); // +\r
+ if ((op&0x90c0)==0x90c0) OpAritha(op); // +\r
+ if ((op&0xb130)==0x9100) OpAddx(op); // +\r
+ if ((op&0xf000)==0xb000) OpCmpEor(op); // +\r
+ if ((op&0xf138)==0xb108) OpCmpm(op); // +\r
+ if ((op&0xf130)==0xc100) OpExg(op); // +\r
+ if ((op&0xf000)==0xe000) OpAsr(op); // + Asr/l/Ror/l etc\r
+ if ((op&0xf8c0)==0xe0c0) OpAsrEa(op); // +\r
+\r
+ if (op==0xffff)\r
+ {\r
+ SuperEnd();\r
+ }\r
}\r
+\r
if (EaCanRead(tea,size)==0) return 1;\r
if (EaCanWrite(tea)==0 || EaAn(tea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op, sea, tea); Cycles=4;\r
\r
- EaCalc(10,0x0000, sea,size,1);\r
- EaCalc(11,0x003f, tea,size,1);\r
- EaRead(10, 10, sea,size,0,0,0);\r
- EaRead(11, 0, tea,size,0x003f,1);\r
+ EaCalcReadNoSE((type!=6)?11:-1,0,tea,size,0x003f);\r
+ EaCalcReadNoSE(-1,10,sea,size,0);\r
\r
- if (size==0) shiftstr=",asl #24";\r
- else if (size==1) shiftstr=",asl #16";\r
+ if (size<2) shiftstr=(char *)(size?",asl #16":",asl #24");\r
+ if (size<2) ot(" mov r0,r0,asl %i\n",size?16:24);\r
\r
ot(";@ Do arithmetic:\n");\r
\r
if (EaCanWrite(ea) ==0) return 1;\r
if (size == 0 && EaAn(ea) ) return 1;\r
\r
- use=OpBase(op,1);\r
+ use=OpBase(op,size,1);\r
\r
if (num!=8) use|=0x0e00; // If num is not 8, use same handler\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
if (size>0 && (ea&0x38)==0x08) size=2; // addq.w #n,An is also 32-bit\r
\r
- EaCalc(10,0x003f, ea,size,1);\r
- EaRead(10, 0, ea,size,0x003f,1);\r
+ EaCalcReadNoSE(10,0,ea,size,0x003f);\r
\r
shift=32-(8<<size);\r
\r
sprintf(count,"#0x%.4x",8<<shift);\r
}\r
\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
+\r
if (type==0) ot(" adds r1,r0,%s\n",count);\r
if (type==1) ot(" subs r1,r0,%s\n",count);\r
\r
{\r
int use=0;\r
int type=0,size=0,dir=0,rea=0,ea=0;\r
+ char *asl="";\r
+ char *strop=0;\r
\r
type=(op>>12)&5;\r
rea =(op>> 9)&7;\r
if (dir && EaCanWrite(ea)==0) return 1;\r
if ((size==0||!(type&1))&&EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same opcode for Dn\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=4;\r
\r
- ot(";@ Get r10=EA r11=EA value\n");\r
- EaCalc(10,0x003f, ea,size,1);\r
- EaRead(10, 11, ea,size,0x003f,1);\r
- ot(";@ Get r0=Register r1=Register value\n");\r
- EaCalc( 0,0x0e00,rea,size,1);\r
- EaRead( 0, 1,rea,size,0x0e00,1);\r
+ EaCalcReadNoSE(dir?10:-1,0,ea,size,0x003f);\r
+\r
+ EaCalcReadNoSE(dir?-1:10,1,rea,size,0x0e00);\r
\r
ot(";@ Do arithmetic:\n");\r
- if (type==0) ot(" orr ");\r
- if (type==1) ot(" subs ");\r
- if (type==4) ot(" and ");\r
- if (type==5) ot(" adds ");\r
- if (dir) ot("r1,r11,r1\n");\r
- else ot("r1,r1,r11\n");\r
+ if (type==0) strop = "orr";\r
+ if (type==1) strop = (char *) (dir ? "subs" : "rsbs");\r
+ if (type==4) strop = "and";\r
+ if (type==5) strop = "adds";\r
+\r
+ if (size==0) asl=",asl #24";\r
+ if (size==1) asl=",asl #16";\r
+\r
+ if (size<2) ot(" mov r0,r0%s\n",asl);\r
+ ot(" %s r1,r0,r1%s\n",strop,asl);\r
\r
if ((type&1)==0) ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
\r
ot("\n");\r
\r
ot(";@ Save result:\n");\r
- if (dir) EaWrite(10, 1, ea,size,0x003f,1);\r
- else EaWrite( 0, 1,rea,size,0x0e00,1);\r
+ if (size<2) ot(" mov r1,r1,asr #%d\n",size?16:24);\r
+ if (dir) EaWrite(10, 1, ea,size,0x003f,0,0);\r
+ else EaWrite(10, 1,rea,size,0x0e00,0,0);\r
\r
if(rea==ea) {\r
if(ea<8) Cycles=(size>=2)?8:4; else Cycles+=(size>=2)?26:14;\r
// See if we can do this opcode:\r
if (EaCanRead(ea,1)==0||EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,1);\r
use&=~0x0e00; // Use same for all registers\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
if(type) Cycles=54;\r
else Cycles=sign?158:140;\r
\r
- EaCalc(10,0x003f, ea, 1);\r
- EaRead(10, 10, ea, 1,0x003f);\r
+ EaCalcReadNoSE(-1,0,ea,1,0x003f);\r
+\r
+ EaCalc(10,0x0e00,rea, 2);\r
+ EaRead(10, 2,rea, 2,0x0e00);\r
\r
- EaCalc (0,0x0e00,rea, 2,1);\r
- EaRead (0, 2,rea, 2,0x0e00,1);\r
+ ot(" movs r0,r0,asl #16\n");\r
\r
if (type==0) // div\r
{\r
// the manual says C is always cleared, but neither Musashi nor FAME do that\r
//ot(" bic r9,r9,#0x20000000 ;@ always clear C\n");\r
- ot(" tst r10,r10\n");\r
ot(" beq divzero%.4x ;@ division by zero\n",op);\r
ot("\n");\r
\r
{\r
ot(" mov r11,#0 ;@ r11 = 1 or 2 if the result is negative\n");\r
ot(" orrmi r11,r11,#1\n");\r
- ot(" rsbmi r10,r10,#0 ;@ Make r10 positive\n");\r
+ ot(" mov r0,r0,asr #16\n");\r
+ ot(" rsbmi r0,r0,#0 ;@ Make r0 positive\n");\r
ot("\n");\r
ot(" tst r2,r2\n");\r
ot(" orrmi r11,r11,#2\n");\r
}\r
else\r
{\r
- ot(" mov r10,r10,lsl #16 ;@ use only 16 bits of divisor\n");\r
- ot(" mov r10,r10,lsr #16\n");\r
+ ot(" mov r0,r0,lsr #16 ;@ use only 16 bits of divisor\n");\r
}\r
\r
- ot(";@ Divide r2 by r10\n");\r
+ ot(";@ Divide r2 by r0\n");\r
ot(" mov r3,#0\n");\r
- ot(" mov r1,r10\n");\r
+ ot(" mov r1,r0\n");\r
ot("\n");\r
ot(";@ Shift up divisor till it's just less than numerator\n");\r
ot("Shift%.4x%s\n",op,ms?"":":");\r
ot(" cmp r2,r1\n");\r
ot(" adc r3,r3,r3 ;@ Double r3 and add 1 if carry set\n");\r
ot(" subcs r2,r2,r1\n");\r
- ot(" teq r1,r10\n");\r
+ ot(" teq r1,r0\n");\r
ot(" movne r1,r1,lsr #1\n");\r
ot(" bne Divide%.4x\n",op);\r
ot("\n");\r
\r
if (type==1)\r
{\r
- char *shift="asr";\r
-\r
ot(";@ Get 16-bit signs right:\n");\r
- if (sign==0) { ot(" mov r10,r10,lsl #16\n"); shift="lsr"; }\r
+ ot(" mov r0,r0,%s #16\n",sign?"asr":"lsr");\r
ot(" mov r2,r2,lsl #16\n");\r
-\r
- if (sign==0) ot(" mov r10,r10,lsr #16\n");\r
- ot(" mov r2,r2,%s #16\n",shift);\r
+ ot(" mov r2,r2,%s #16\n",sign?"asr":"lsr");\r
ot("\n");\r
\r
- ot(" mul r1,r2,r10\n");\r
+ ot(" mul r1,r2,r0\n");\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
}\r
ot("\n");\r
\r
- EaWrite(0, 1,rea, 2,0x0e00,1);\r
+ EaWrite(10, 1,rea, 2,0x0e00,1);\r
\r
- ot("endofop%.4x%s\n",op,ms?"":":");\r
+ if (type==0) ot("endofop%.4x%s\n",op,ms?"":":");\r
OpEnd(ea);\r
\r
- ot("divzero%.4x%s\n",op,ms?"":":");\r
- ot(" mov r0,#0x14 ;@ Divide by zero\n");\r
- ot(" bl Exception\n");\r
- Cycles+=38;\r
- OpEnd(ea);\r
- ot("\n");\r
+ if (type==0) // div\r
+ {\r
+ ot("divzero%.4x%s\n",op,ms?"":":");\r
+ ot(" mov r0,#0x14 ;@ Divide by zero\n");\r
+ ot(" bl Exception\n");\r
+ Cycles+=38;\r
+ OpEnd(ea);\r
+ ot("\n");\r
+ }\r
\r
return 0;\r
}\r
int GetXBit(int subtract)\r
{\r
ot(";@ Get X bit:\n");\r
- ot(" ldrb r2,[r7,#0x45]\n");\r
- if (subtract) ot(" mvn r2,r2,lsl #28 ;@ Invert it\n");\r
- else ot(" mov r2,r2,lsl #28\n");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ if (subtract) ot(" mvn r2,r2 ;@ Invert it\n");\r
ot(" msr cpsr_flg,r2 ;@ Get into Carry\n");\r
ot("\n");\r
return 0;\r
int OpAbcd(int op)\r
{\r
int use=0;\r
- int type=0,sea=0,addr=0,dea=0;\r
+ int type=0,sea=0,mem=0,dea=0;\r
\r
type=(op>>14)&1; // sbcd/abcd\r
dea =(op>> 9)&7;\r
- addr=(op>> 3)&1;\r
+ mem =(op>> 3)&1;\r
sea = op &7;\r
\r
- if (addr) { sea|=0x20; dea|=0x20; }\r
+ if (mem) { sea|=0x20; dea|=0x20; }\r
\r
use=op&~0x0e07; // Use same opcode for all registers..\r
- if (sea==0x27||dea==0x27) use=op; // ..except -(a7)\r
+ if (sea==0x27) use|=0x0007; // ___x.b -(a7)\r
+ if (dea==0x27) use|=0x0e00; // ___x.b -(a7)\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea,dea); Cycles=6;\r
\r
- EaCalc( 0,0x0007, sea,0,1);\r
- EaRead( 0, 10, sea,0,0x0007,1);\r
- EaCalc(11,0x0e00, dea,0,1);\r
- EaRead(11, 1, dea,0,0x0e00,1);\r
+ if (mem)\r
+ {\r
+ ot(";@ Get src/dest EA vals\n");\r
+ EaCalc (0,0x000f, sea,0,1);\r
+ EaRead (0, 10, sea,0,0x000f,1);\r
+ EaCalcReadNoSE(11,0,dea,0,0x1e00);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Get src/dest reg vals\n");\r
+ EaCalcReadNoSE(-1,10,sea,0,0x0007);\r
+ EaCalcReadNoSE(11,0,dea,0,0x0e00);\r
+ ot(" mov r10,r10,asl #24\n");\r
+ }\r
+ ot(" mov r1,r0,asl #24\n\n");\r
\r
ot(" bic r9,r9,#0xb1000000 ;@ clear all flags except old Z\n");\r
\r
if (type)\r
{\r
- ot(" ldrb r0,[r7,#0x45] ;@ Get X bit\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ Get X bit\n");\r
ot(" mov r3,#0x00f00000\n");\r
ot(" and r2,r3,r1,lsr #4\n");\r
- ot(" tst r0,#2\n");\r
+ ot(" tst r0,#0x20000000\n");\r
ot(" and r0,r3,r10,lsr #4\n");\r
ot(" add r0,r0,r2\n");\r
ot(" addne r0,r0,#0x00100000\n");\r
}\r
else\r
{\r
- ot(" ldrb r0,[r7,#0x45] ;@ Get X bit\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ Get X bit\n");\r
ot(" mov r3,#0x00f00000\n");\r
ot(" and r2,r3,r10,lsr #4\n");\r
- ot(" tst r0,#2\n");\r
+ ot(" tst r0,#0x20000000\n");\r
ot(" and r0,r3,r1,lsr #4\n");\r
ot(" sub r0,r0,r2\n");\r
ot(" subne r0,r0,#0x00100000\n");\r
ot(" bicne r9,r9,#0x40000000 ;@ Z flag\n");\r
}\r
\r
- ot(" mov r2,r9,lsr #28\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Save X bit\n");\r
+ ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");\r
+ ot("\n");\r
\r
EaWrite(11, 0, dea,0,0x0e00,1);\r
OpEnd(sea,dea);\r
return 0;\r
}\r
\r
-// 01008000 00eeeeee - nbcd <ea>\r
+// 01001000 00eeeeee - nbcd <ea>\r
int OpNbcd(int op)\r
{\r
int use=0;\r
\r
if(EaCanWrite(ea)==0||EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if(op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=6;\r
if(ea >= 8) Cycles+=2;\r
\r
- EaCalc(10,0x3f, ea,0,1);\r
- EaRead(10, 0, ea,0,0x3f,1);\r
+ EaCalcReadNoSE(10,0,ea,0,0x003f);\r
\r
// this is rewrite of Musashi's code\r
- ot(" ldrb r2,[r7,#0x45]\n");\r
- ot(" tst r2,#2\n");\r
- ot(" mov r2,r0\n");\r
- ot(" addne r2,r0,#0x01000000 ;@ add X\n");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
+ ot(" bic r9,r9,#0xb0000000 ;@ clear all flags, except Z\n");\r
+ ot(" mov r0,r0,asl #24\n");\r
+ ot(" and r2,r2,#0x20000000\n");\r
+ ot(" add r2,r0,r2,lsr #5 ;@ add X\n");\r
ot(" rsbs r1,r2,#0x9a000000 ;@ do arithmetic\n");\r
\r
- ot(" bic r9,r9,#0xb0000000 ;@ clear all flags, except Z\n");\r
ot(" orrmi r9,r9,#0x80000000 ;@ N\n");\r
ot(" cmp r1,#0x9a000000\n");\r
ot(" beq finish%.4x\n",op);\r
EaWrite(10, 1, ea,0,0x3f,1);\r
\r
ot("finish%.4x%s\n",op,ms?"":":");\r
- ot(" mov r2,r9,lsr #28\n");\r
- ot(" strb r2, [r7,#0x45]\n");\r
+ ot(" str r9,[r7,#0x4c] ;@ Save X\n");\r
\r
OpEnd(ea);\r
\r
{\r
int use=0;\r
int type=0,size=0,sea=0,dea=0;\r
+ char *asr="";\r
\r
// Suba/Cmpa/Adda/(invalid):\r
type=(op>>13)&3; if (type>=3) return 1;\r
// See if we can do this opcode:\r
if (EaCanRead(sea,size)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same opcode for An\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
if(size==2&&(sea<0x10||sea==0x3c)) Cycles+=2;\r
if(type==1) Cycles=6;\r
\r
- \r
// must calculate reg EA first, because of situations like: suba.w (A0)+, A0\r
- EaCalc (10,0x0e00, dea,2,1);\r
- EaRead (10, 11, dea,2,0x0e00);\r
+ EaCalc (10,0x1e00, dea,2,1);\r
+ EaRead (10, 11, dea,2,0x1e00);\r
+\r
+ EaCalc ( 0,0x003f, sea,size,1);\r
+ EaRead ( 0, 0, sea,size,0x003f,1);\r
\r
- EaCalc ( 0,0x003f, sea,size);\r
- EaRead ( 0, 0, sea,size,0x003f);\r
+ if (size<2) asr=(char *)(size?",asr #16":",asr #24");\r
\r
- if (type==0) ot(" sub r11,r11,r0\n");\r
- if (type==1) ot(" cmp r11,r0 ;@ Defines NZCV\n");\r
+ if (type==0) ot(" sub r11,r11,r0%s\n",asr);\r
+ if (type==1) ot(" cmp r11,r0%s ;@ Defines NZCV\n",asr);\r
if (type==1) OpGetFlags(1,0); // Get Cmp flags\r
- if (type==2) ot(" add r11,r11,r0\n");\r
+ if (type==2) ot(" add r11,r11,r0%s\n",asr);\r
ot("\n");\r
\r
if (type!=1) EaWrite(10, 11, dea,2,0x0e00,1);\r
{\r
int use=0;\r
int type=0,size=0,dea=0,sea=0,mem=0;\r
+ char *asl="";\r
\r
- type=(op>>12)&5;\r
+ type=(op>>14)&1;\r
dea =(op>> 9)&7;\r
size=(op>> 6)&3; if (size>=3) return 1;\r
sea = op&7;\r
if(mem) { sea+=0x20; dea+=0x20; }\r
\r
use=op&~0x0e07; // Use same opcode for Dn\r
- if (size==0&&(sea==0x27||dea==0x27)) use=op; // ___x.b -(a7)\r
+ if (size==0&&sea==0x27) use|=0x0007; // ___x.b -(a7)\r
+ if (size==0&&dea==0x27) use|=0x0e00; // ___x.b -(a7)\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea,dea); Cycles=4;\r
if(size>=2) Cycles+=4;\r
if(sea>=0x10) Cycles+=2;\r
\r
- ot(";@ Get r10=EA r11=EA value\n");\r
- EaCalc( 0,0x0007,sea,size,1);\r
- EaRead( 0, 11,sea,size,0x0007,1);\r
- ot(";@ Get r0=Register r1=Register value\n");\r
- EaCalc( 0,0x0e00,dea,size,1);\r
- EaRead( 0, 1,dea,size,0x0e00,1);\r
+ if (mem)\r
+ {\r
+ ot(";@ Get src/dest EA vals\n");\r
+ EaCalc (0,0x000f, sea,size,1);\r
+ EaRead (0, 11, sea,size,0x000f,1);\r
+ EaCalcReadNoSE(10,0,dea,size,0x1e00);\r
+ }\r
+ else\r
+ {\r
+ ot(";@ Get src/dest reg vals\n");\r
+ EaCalcReadNoSE(-1,11,sea,size,0x0007);\r
+ EaCalcReadNoSE(10,0,dea,size,0x0e00);\r
+ if (size<2) ot(" mov r11,r11,asl #%d\n\n",size?16:24);\r
+ }\r
+\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
\r
ot(";@ Do arithmetic:\n");\r
- GetXBit(type==1);\r
+ GetXBit(type==0);\r
\r
- if (type==5 && size<2)\r
+ if (type==1 && size<2)\r
{\r
ot(";@ Make sure the carry bit will tip the balance:\n");\r
ot(" mvn r2,#0\n");\r
ot("\n");\r
}\r
\r
- if (type==1) ot(" sbcs r1,r1,r11\n");\r
- if (type==5) ot(" adcs r1,r1,r11\n");\r
+ if (type==0) ot(" rscs r1,r11,r0%s\n",asl);\r
+ if (type==1) ot(" adcs r1,r11,r0%s\n",asl);\r
ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
- OpGetFlags(type==1,1,0); // subtract\r
+ OpGetFlags(type==0,1,0); // subtract\r
if (size<2) {\r
ot(" movs r2,r1,lsr #%i\n", size?16:24);\r
ot(" orreq r9,r9,#0x40000000 ;@ add potentially missed Z\n");\r
ot("\n");\r
\r
ot(";@ Save result:\n");\r
- EaWrite( 0, 1, dea,size,0x0e00,1);\r
+ EaWrite(10, 1, dea,size,0x0e00,1);\r
\r
OpEnd(sea,dea);\r
\r
{\r
int rea=0,eor=0;\r
int size=0,ea=0,use=0;\r
+ char *asl="";\r
\r
// Get EA and register EA\r
rea=(op>>9)&7;\r
if (eor && EaCanWrite(ea)==0) return 1;\r
if (EaAn(ea)&&(eor||size==0)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use 1 handler for register d0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
}\r
\r
ot(";@ Get EA into r10 and value into r0:\n");\r
- EaCalc (10,0x003f, ea,size,1);\r
- EaRead (10, 0, ea,size,0x003f,1);\r
+ EaCalcReadNoSE(eor?10:-1,0,ea,size,0x003f);\r
\r
ot(";@ Get register operand into r1:\n");\r
- EaCalc (1, 0x0e00, rea,size,1);\r
- EaRead (1, 1, rea,size,0x0e00,1);\r
+ EaCalcReadNoSE(-1,1,rea,size,0x0e00);\r
+\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n\n",size?16:24);\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
\r
ot(";@ Do arithmetic:\n");\r
- if (eor==0) ot(" cmp r1,r0\n");\r
+ if (eor==0) ot(" rsbs r1,r0,r1%s\n",asl);\r
if (eor)\r
{\r
- ot(" eor r1,r0,r1\n");\r
+ ot(" eor r1,r0,r1%s\n",asl);\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
}\r
\r
int OpCmpm(int op)\r
{\r
int size=0,sea=0,dea=0,use=0;\r
+ char *asl="";\r
\r
// get size, get EAs\r
size=(op>>6)&3; if (size>=3) return 1;\r
dea=(op>>9)&0x3f;\r
\r
use=op&~0x0e07; // Use 1 handler for all registers..\r
- if (size==0&&(sea==0x1f||dea==0x1f)) use=op; // ..except (a7)+\r
+ if (size==0&&sea==0x1f) use|=0x0007; // ..except (a7)+\r
+ if (size==0&&dea==0x1f) use|=0x0e00;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea); Cycles=4;\r
\r
ot(";@ Get src operand into r10:\n");\r
- EaCalc (0,0x000f, sea,size,1);\r
+ EaCalc (0,0x1e00, sea,size,1);\r
EaRead (0, 10, sea,size,0x000f,1);\r
\r
ot(";@ Get dst operand into r0:\n");\r
- EaCalc (0,0x1e00, dea,size,1);\r
- EaRead (0, 0, dea,size,0x1e00,1);\r
+ EaCalcReadNoSE(-1,0,dea,size,0x1e00);\r
\r
- ot(" cmp r0,r10\n");\r
+ if (size<2) asl=(char *)(size?",asl #16":",asl #24");\r
+\r
+ ot(" rsbs r0,r10,r0%s\n",asl);\r
OpGetFlags(1,0); // Cmp like subtract\r
+ ot("\n");\r
\r
OpEnd(sea);\r
return 0;\r
// See if we can do this opcode:\r
if (EaCanRead(ea,size)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use 1 handler for register d0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=10;\r
\r
ot(";@ Get EA into r10 and value into r0:\n");\r
- EaCalc (10,0x003f, ea,size,1);\r
- EaRead (10, 0, ea,size,0x003f,1);\r
+ EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
\r
ot(";@ Get register operand into r1:\n");\r
- EaCalc (1, 0x0e00, rea,size,1);\r
- EaRead (1, 1, rea,size,0x0e00,1);\r
+ EaCalcReadNoSE(-1,1,rea,size,0x0e00);\r
+\r
+ if (size<2) ot(" mov r0,r0,asl #%d\n",size?16:24);\r
+ if (size<2) ot(" mov r1,r1,asl #%d\n\n",size?16:24);\r
\r
ot(";@ get flags, including undocumented ones\n");\r
ot(" and r3,r9,#0x80000000\n");\r
ot(" bmi chktrap%.4x\n",op);\r
\r
ot(";@ Do arithmetic:\n");\r
+ ot(" bic r9,r9,#0x80000000 ;@ N\n");\r
ot(" cmp r1,r0\n");\r
- ot(" bicgt r9,r9,#0x80000000 ;@ N\n");\r
ot(" bgt chktrap%.4x\n",op);\r
\r
ot(";@ old N remains\n");\r
- ot(" bic r9,r9,#0x80000000 ;@ N\n");\r
ot(" orr r9,r9,r3\n");\r
OpEnd(ea);\r
\r
OpStart(op,0x10);\r
\r
ot(";@ Get An\n");\r
- EaCalc(10, 7, 8, 2, 1);\r
- EaRead(10, 0, 8, 2, 7, 1);\r
+ EaCalc(10, 0xf, 8, 2, 1);\r
+ EaRead(10, 0, 8, 2, 0xf, 1);\r
\r
ot(" add r11,r0,#4 ;@ A7+=4\n");\r
ot("\n");\r
ot("\n");\r
ot(";@ An = value from stack:\n");\r
EaWrite(10, 0, 8, 2, 7, 1);\r
- \r
+\r
Cycles=12;\r
OpEnd(0x10);\r
return 0;\r
SuperChange(op);\r
CheckInterrupt(op);\r
OpEnd(0x10);\r
- SuperEnd(op);\r
return 0;\r
\r
case 5: // rts\r
// See if we can do this opcode:\r
if (EaCanRead(sea,-1)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,(op&0x40)?0:0x10);\r
break;\r
case 2: // hi\r
ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
- ot(" beq DbraTrue%.4x\n\n",op);\r
+ ot(" beq DbraTrue\n\n");\r
break;\r
case 3: // ls\r
ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
- ot(" bne DbraTrue%.4x\n\n",op);\r
+ ot(" bne DbraTrue\n\n");\r
break;\r
default:\r
ot(";@ Is the condition true?\n");\r
ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
ot(";@ If so, don't dbra\n");\r
- ot(" b%s DbraTrue%.4x\n\n",Cond[cc],op);\r
+ ot(" b%s DbraTrue\n\n",Cond[cc]);\r
break;\r
}\r
\r
OpEnd();\r
}\r
\r
- if (cc==0||cc>=2)\r
+ //if (cc==0||cc>=2)\r
+ if (op==0x50c8)\r
{\r
ot(";@ condition true:\n");\r
- ot("DbraTrue%.4x%s\n", op, ms?"":":");\r
+ ot("DbraTrue%s\n", ms?"":":");\r
ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
ot("\n");\r
Cycles=12;\r
int size=0,use=0;\r
int offset=0;\r
int cc=0;\r
+ char *asr_r11="";\r
\r
offset=(char)(op&0xff);\r
cc=(op>>8)&15;\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
OpStart(op,size?0x10:0);\r
-\r
- ot(";@ Get Branch offset:\n");\r
- if (size) \r
- {\r
- EaCalc(0,0,0x3c,size);\r
- EaRead(0,0,0x3c,size,0);\r
- }\r
- else\r
- ot(" mov r0,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
-\r
- // above code messes cycles\r
Cycles=10; // Assume branch taken\r
\r
if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
\r
- if (cc>=2)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000\n");\r
-\r
- ot(" b%s DontBranch%.4x\n",Cond[cc^1],op);\r
- ot("\n");\r
+ case 0: // T\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" bne BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" beq BccDontBranch%i\n\n",8<<size);\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
+ ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
+ break;\r
}\r
\r
- if (size==0) ot(" mov r0,r0,asr #24 ;@ ...shift down\n\n");\r
+ if (size) \r
+ {\r
+ if (size<2)\r
+ {\r
+ ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
+ }\r
+ else\r
+ {\r
+ ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
+ ot(" ldrh r11,[r4,#2]\n");\r
+ ot(" orr r11,r11,r2,lsl #16\n");\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
+ asr_r11=",asr #24";\r
+ }\r
\r
ot(";@ Branch taken - Add on r0 to PC\n");\r
\r
{\r
ot(";@ Bsr - remember old PC\n");\r
ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
+ if (size) ot(" add r1,r1,#%d\n",1<<size);\r
ot(" mov r1,r1, lsl #8\n");\r
+ ot(" ldr r2,[r7,#0x3c]\n");\r
ot(" mov r1,r1, asr #8\n");\r
ot("\n");\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
- ot(" ldr r2,[r7,#0x3c]\n");\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
ot(";@ Push r1 onto stack\n");\r
ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
if (offset==0 || offset==-1)\r
{\r
ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
- CheckPc(4);\r
+ ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+ CheckPc(0);\r
}\r
+ else\r
+ ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
}\r
else\r
{\r
- if (size) ot(" sub r4,r4,#%d ;@ (Branch is relative to Opcode+2)\n",1<<size);\r
if (offset==0 || offset==-1)\r
{\r
- ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
+ ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
CheckPc(0);\r
}\r
else\r
{\r
- ot(" add r4,r4,r0 ;@ r4 = New PC\n");\r
+ ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
ot("\n");\r
}\r
}\r
\r
-\r
OpEnd(size?0x10:0);\r
\r
- if (cc>=2)\r
+ // since all "DontBranch" code is same for every size, output only once\r
+ if (cc>=2&&(op&0xff00)==0x6200)\r
{\r
- ot("DontBranch%.4x%s\n", op, ms?"":":");\r
- Cycles+=(size==1)? 2 : -2; // Branch not taken\r
- OpEnd(size?0x10:0);\r
+ ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
+ if (size) ot(" add r4,r4,#%d\n",8<<size);\r
+ Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
+ OpEnd(0);\r
}\r
\r
return 0;\r
if (EaCanWrite(tea)==0) return 1;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
use&=~0x0e00; // Use same handler for all registers\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalc (10,0x0e00,sea,0,0,0);\r
- EaRead (10, 10,sea,0,0x0e00,0,0);\r
+ EaCalcReadNoSE(-1,10,sea,0,0x0e00);\r
\r
- EaCalc ( 0,0x003f,tea,size,0,0);\r
- if (type>0)\r
- ot(" mov r11,r0\n");\r
- EaRead ( 0, 0,tea,size,0x003f,0,0);\r
+ EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
\r
if (tea>=0x10)\r
ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0\r
if (EaCanWrite(tea)==0) return 1;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea,tea);\r
\r
ot("\n");\r
- EaCalc ( 0,0x0000,sea,0,0,0);\r
- EaRead ( 0, 0,sea,0,0,0,0);\r
+ EaCalcReadNoSE(-1,0,sea,0,0);\r
ot(" mov r10,#1\n");\r
ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
if (tea>=0x10)\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalc (11,0x003f,tea,size,0,0);\r
- EaRead (11, 0,tea,size,0x003f,0,0);\r
+ EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
ot(" tst r0,r10 ;@ Do arithmetic\n");\r
ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
ot("\n");\r
if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
if (EaCanWrite(ea )==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=size<2?4:6;\r
\r
EaCalc (10,0x003f,ea,size,0,0);\r
\r
- if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for dummy read?)\r
+ if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
if (type==1) ot("\n");\r
\r
if (type==0)\r
// See if we can do this opcode:\r
if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea); Cycles=4;\r
size=(op>>6)&1;\r
shift=32-(8<<size);\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op); Cycles=4;\r
// See if we can do this opcode:\r
if (EaCanWrite(ea)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=8;\r
if (usereg)\r
{\r
ot(";@ Use Dn for count:\n");\r
- ot(" and r2,r8,#7<<9\n");\r
+ ot(" and r2,r8,#0x0e00\n");\r
ot(" ldr r2,[r7,r2,lsr #7]\n");\r
ot(" and r2,r2,#63\n");\r
ot("\n");\r
if (usereg) { // store X only if count is not 0\r
ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");\r
- ot(" movne r1,r9,lsr #28\n");\r
- ot(" strneb r1,[r7,#0x45] ;@ else Save X bit\n");\r
+ ot(" strne r9,[r7,#0x4c] ;@ else Save X bit\n");\r
} else {\r
// count will never be 0 if we use immediate\r
- ot(" mov r1,r9,lsr #28\n");\r
- ot(" strb r1,[r7,#0x45] ;@ Save X bit\n");\r
+ ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");\r
}\r
\r
if (type==0 && dir) {\r
ot(" movs r0,r0,rrx\n");\r
OpGetFlags(0,1);\r
} else {\r
- ot(" ldrb r3,[r7,#0x45]\n");\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
ot(" movs r0,r0,lsl #1\n");\r
OpGetFlags(0,1);\r
- ot(" tst r3,#2\n");\r
+ ot(" tst r3,#0x20000000\n");\r
ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");\r
}\r
ot(" orr r0,r3,r0 ;@ r0=Rotated value\n");\r
\r
ot(";@ Insert X bit into r2-1:\n");\r
- ot(" ldrb r3,[r7,#0x45]\n");\r
+ ot(" ldr r3,[r7,#0x4c]\n");\r
ot(" sub r2,r2,#1\n");\r
- ot(" and r3,r3,#2\n");\r
- ot(" mov r3,r3,lsr #1\n");\r
+ ot(" and r3,r3,#0x20000000\n");\r
+ ot(" mov r3,r3,lsr #29\n");\r
ot(" orr r0,r0,r3,lsl r2\n");\r
ot("\n");\r
\r
ot(" bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");\r
}\r
if (usereg) { // store X only if count is not 0\r
- ot(" mov r2,r9,lsr #28\n");\r
- ot(" strb r2,[r7,#0x45] ;@ if not 0, Save X bit\n");\r
+ ot(" str r9,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
ot(" b nozerox%.4x\n",op);\r
ot("norotx%.4x%s\n",op,ms?"":":");\r
- ot(" ldrb r2,[r7,#0x45]\n");\r
+ ot(" ldr r2,[r7,#0x4c]\n");\r
ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
- ot(" and r2,r2,#2\n");\r
- ot(" orr r9,r9,r2,lsl #28 ;@ C = old_X\n");\r
+ ot(" and r2,r2,#0x20000000\n");\r
+ ot(" orr r9,r9,r2 ;@ C = old_X\n");\r
ot("nozerox%.4x%s\n",op,ms?"":":");\r
}\r
\r
if (EaCanRead(ea,0)==0) return 1;\r
if (EaCanWrite(ea)==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
// See if we can do this opcode:\r
if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
if (!gen_special) OpStart(op,ea);\r
// trashes r0,r2\r
void OpFlagsToReg(int high)\r
{\r
- ot(" ldrb r0,[r7,#0x45] ;@ X bit\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
ot("\n");\r
if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r
- ot(" and r0,r0,#0x02\n");\r
- ot(" orr r1,r1,r0,lsl #3 ;@ ___XNZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
if (high) ot(" orr r1,r1,r2,lsl #8\n");\r
ot("\n");\r
}\r
void OpRegToFlags(int high)\r
{\r
ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
- ot(" mov r2,r0,lsr #3 ;@ r2=___XN\n");\r
+ ot(" mov r2,r0,lsl #25\n");\r
ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
- ot(" strb r2,[r7,#0x45] ;@ Store X bit\n");\r
+ ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");\r
ot(" mov r9,r0,lsl #28 ;@ r9=NZCV...\n");\r
\r
if (high)\r
{\r
ot(" ldr r11,[r7,#0x44] ;@ Get SR high\n");\r
ot(" tst r11,#0x20 ;@ Check we are in supervisor mode\n");\r
- ot(" beq WrongMode%.4x ;@ No\n",op);\r
+ ot(" beq WrongPrivilegeMode ;@ No\n");\r
ot("\n");\r
}\r
\r
-void SuperEnd(int op)\r
+void SuperEnd(void)\r
{\r
- ot("WrongMode%.4x%s\n",op,ms?"":":");\r
- ot(" sub r4,r4,#2 ;@ this opcode wasn't executed - go back\n");\r
+ ot(";@ ----------\n");\r
+ ot(";@ tried execute privileged instruction in user mode\n");\r
+ ot("WrongPrivilegeMode%s\n",ms?"":":");\r
+ ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
ot(" mov r0,#0x20 ;@ privilege violation\n");\r
ot(" bl Exception\n");\r
Cycles=34;\r
\r
// does OSP and A7 swapping if needed\r
// new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r
-// trashes r1,r11\r
-void SuperChange(int op)\r
+// trashes r0,r11\r
+void SuperChange(int op,int load_srh)\r
{\r
ot(";@ A7 <-> OSP?\n");\r
- ot(" ldr r1,[r7,#0x44] ;@ Get other SR high\n");\r
- ot(" and r11,r11,#0x20\n");\r
- ot(" and r1,r1,#0x20\n");\r
- ot(" teq r11,r1 ;@ r11 xor r1\n");\r
+ if (load_srh)\r
+ ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r
+ ot(" eor r0,r0,r11\n");\r
+ ot(" tst r0,#0x20\n");\r
ot(" beq no_sp_swap%.4x\n",op);\r
ot(" ;@ swap OSP and A7:\n");\r
ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");\r
- ot(" ldr r1, [r7,#0x48] ;@ Get OSP\n");\r
+ ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");\r
ot(" str r11,[r7,#0x48]\n");\r
- ot(" str r1, [r7,#0x3C]\n");\r
+ ot(" str r0, [r7,#0x3C]\n");\r
ot("no_sp_swap%.4x%s\n", op, ms?"":":");\r
}\r
\r
if (EaCanRead (sea,size)==0) return 1;\r
if (EaCanWrite(tea )==0) return 1;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7\r
\r
- if (tea>=0x18 && tea<0x28 && (tea&7)==7) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
+ if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea,tea); Cycles=4;\r
\r
- EaCalc(0,0x003f,sea,size);\r
- EaRead(0, 1,sea,size,0x003f);\r
+ EaCalcRead(-1,1,sea,size,0x003f);\r
\r
- if (movea==0) {\r
+ if (movea==0)\r
+ {\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
ot(" mrs r9,cpsr ;@ r9=NZCV flags\n");\r
ot("\n");\r
\r
if (movea) size=2; // movea always expands to 32-bits\r
\r
- EaCalc (0,0x0e00,tea,size,0,0);\r
#if SPLIT_MOVEL_PD\r
+ EaCalc (10,0x1e00,tea,size,0,0);\r
if ((tea&0x38)==0x20 && size==2) { // -(An)\r
- ot(" mov r10,r0\n");\r
ot(" mov r11,r1\n");\r
- ot(" add r0,r0,#2\n");\r
- EaWrite(0, 1,tea,1,0x0e00,0,0);\r
- EaWrite(10, 11,tea,1,0x0e00,1);\r
+ ot(" add r0,r10,#2\n");\r
+ EaWrite(0, 1,tea,1,0x1e00,0,0);\r
+ EaWrite(10, 11,tea,1,0x1e00,1);\r
} else {\r
- EaWrite(0, 1,tea,size,0x0e00,0,0);\r
+ EaWrite(0, 1,tea,size,0x1e00,0,0);\r
}\r
#else\r
- EaWrite(0, 1,tea,size,0x0e00,0,0);\r
+ EaCalc (0,0x1e00,tea,size,0,0);\r
+ EaWrite(0, 1,tea,size,0x1e00,0,0);\r
#endif\r
\r
#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
\r
if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
use&=~0x0e00; // Also use 1 handler for target ?0-7\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,sea,tea);\r
\r
EaCalc (1,0x003f,sea,0); // Lea\r
- EaCalc (0,0x0e00,tea,2,1);\r
- EaWrite(0, 1,tea,2,0x0e00,1);\r
+ EaCalc (0,0x1e00,tea,2);\r
+ EaWrite(0, 1,tea,2,0x1e00);\r
\r
Cycles=Ea_add_ns(g_lea_cycle_table,sea);\r
\r
break;\r
}\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea);\r
\r
if (type==2 || type==3)\r
{\r
- EaCalc(0,0x003f,ea,size,0,0);\r
- EaRead(0, 0,ea,size,0x003f,0,0);\r
+ EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
OpRegToFlags(type==3);\r
if (type==3) {\r
- SuperChange(op);\r
+ SuperChange(op,0);\r
CheckInterrupt(op);\r
}\r
}\r
\r
OpEnd(ea);\r
\r
- if (type==3) SuperEnd(op);\r
-\r
return 0;\r
}\r
\r
size=(op>>6)&1; // ccr or sr?\r
ea=0x3c;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea); Cycles=16;\r
if (type==5) ot(" eor r0,r1,r10\n");\r
OpRegToFlags(size);\r
if (size) {\r
- SuperChange(op);\r
+ SuperChange(op,0);\r
CheckInterrupt(op);\r
}\r
\r
OpEnd(ea);\r
- if (size) SuperEnd(op);\r
\r
return 0;\r
}\r
ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode\r
if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,0);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea);\r
\r
cea=ea; if (change) cea=0x10;\r
\r
- use=OpBase(op);\r
+ use=OpBase(op,size);\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
OpStart(op,ea);\r
if (dir)\r
{\r
ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r
- EaCalc (0,0x0007,8,2,1);\r
- EaWrite(0, 1,8,2,0x0007,1);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaWrite(0, 1,8,2,0x000f,1);\r
}\r
else\r
{\r
- EaCalc (0,0x0007,8,2,1);\r
- EaRead (0, 0,8,2,0x0007,1);\r
+ EaCalc (0,0x000f,8,2,1);\r
+ EaRead (0, 0,8,2,0x000f,1);\r
ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");\r
}\r
\r
OpEnd();\r
\r
- SuperEnd(op);\r
-\r
return 0;\r
}\r
\r
// 0000sss1 1z001ddd (to mem)\r
int OpMovep(int op)\r
{\r
- int ea=0;\r
- int size=1,use=0,dir;\r
+ int ea=0,rea=0;\r
+ int size=1,use=0,dir,aadd=0;\r
\r
use=op&0xf1f8;\r
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)\r
\r
// Get EA\r
ea = (op&0x0007)|0x28;\r
+ rea= op&0x0e00;\r
dir = (op>>7)&1;\r
\r
// Find size extension\r
OpStart(op,ea);\r
\r
if(dir) { // reg to mem\r
- EaCalc(11,0x0e00,0,size); // reg number -> r11\r
- EaRead(11,11,0,size,0x0e00); // regval -> r11\r
- EaCalc(10,0x0007,ea,size);\r
+ EaCalcReadNoSE(-1,11,rea,size,0x1e00);\r
+\r
+ EaCalc(10,0x000f,ea,size);\r
if(size==2) { // if operand is long\r
ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r
- EaWrite(10,1,ea,0,0x0007); // store first byte\r
- ot(" add r10,r10,#2\n");\r
+ EaWrite(10,1,ea,0,0x000f); // store first byte\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r
- EaWrite(10,1,ea,0,0x0007); // store second byte\r
- ot(" add r10,r10,#2\n");\r
+ EaWrite(0,1,ea,0,0x000f); // store second byte\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
+ } else {\r
+ ot(" mov r0,r10\n");\r
}\r
ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r
- EaWrite(10,1,ea,0,0x0007);\r
- ot(" add r10,r10,#2\n");\r
+ EaWrite(0,1,ea,0,0x000f);\r
+ ot(" add r0,r10,#%i\n",(aadd+=2));\r
ot(" and r1,r11,#0xff\n");\r
- EaWrite(10,1,ea,0,0x0007);\r
+ EaWrite(0,1,ea,0,0x000f);\r
} else { // mem to reg\r
- EaCalc(10,0x0007,ea,size,1);\r
- EaRead(10,11,ea,0,0x0007,1); // read first byte\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1); // read second byte\r
+ EaCalc(10,0x000f,ea,size,1);\r
+ EaRead(10,11,ea,0,0x000f,1); // read first byte\r
+ ot(" add r0,r10,#2\n");\r
+ EaRead(0,1,ea,0,0x000f,1); // read second byte\r
if(size==2) { // if operand is long\r
ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1);\r
+ ot(" add r0,r10,#4\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");\r
- ot(" add r10,r10,#2\n");\r
- EaRead(10,1,ea,0,0x0007,1);\r
- ot(" orr r0,r11,r1,lsr #24 ;@ fourth byte\n");\r
+ ot(" add r0,r10,#6\n");\r
+ EaRead(0,1,ea,0,0x000f,1);\r
+ ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");\r
} else {\r
- ot(" orr r0,r11,r1,lsr #8 ;@ second byte\n");\r
+ ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");\r
}\r
// store the result\r
- EaCalc(11,0x0e00,0,size,1); // reg number -> r11\r
- EaWrite(11,0,0,size,0x0e00,1);\r
+ EaCalc(11,0x0e00,rea,size,1); // reg number -> r11\r
+ EaWrite(11,1,rea,size,0x0e00,1);\r
}\r
\r
Cycles=(size==2)?24:16;\r
// Emit a Stop/Reset opcodes, 01001110 011100t0 imm\r
int OpStopReset(int op)\r
{\r
- int type=(op>>1)&1; // reset/stop\r
+ int type=(op>>1)&1; // stop/reset\r
\r
OpStart(op);\r
\r
if(type) {\r
// copy immediate to SR, stop the CPU and eat all remaining cycles.\r
ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");\r
- SuperChange(op);\r
OpRegToFlags(1);\r
+ SuperChange(op,0);\r
\r
ot("\n");\r
\r
ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");\r
ot(" tst r11,r11\n");\r
ot(" movne lr,pc\n");\r
- ot(" movne pc,r11 ;@ call ResetCallback if it is defined\n");\r
+ ot(" bxne r11 ;@ call ResetCallback if it is defined\n");\r
ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
ot(" mov r9,r9,lsl #28\n");\r
+ ot("\n");\r
#endif\r
}\r
\r
OpEnd();\r
- SuperEnd(op);\r
\r
return 0;\r
}\r
int Ea_add_ns(int *tab, int ea); // add nonstandard EA cycles\r
int EaCalc(int a,int mask,int ea,int size,int top=0,int sign_extend=1); // 6\r
int EaRead(int a,int v,int ea,int size,int mask,int top=0,int sign_extend=1); // 7\r
+int EaCalcRead(int r_ea,int r,int ea,int size,int mask,int sign_extend=1); // 6\r
+int EaCalcReadNoSE(int r_ea,int r,int ea,int size,int mask);\r
int EaCanRead(int ea,int size);\r
int EaWrite(int a,int v,int ea,int size,int mask,int top=0,int sign_extend_ea=1);\r
int EaCanWrite(int ea);\r
void FlushPC(void);\r
\r
// OpAny.cpp\r
+extern int g_op;\r
int OpGetFlags(int subtract,int xbit,int sprecialz=0);\r
void OpUse(int op,int use);\r
void OpStart(int op,int sea=0,int tea=0);\r
void OpEnd(int sea=0,int tea=0);\r
-int OpBase(int op,int sepa=0);\r
+int OpBase(int op,int size,int sepa=0);\r
void OpAny(int op);\r
\r
//----------------------\r
int OpMoveq(int op);\r
int OpMoveUsp(int op);\r
int OpExg(int op);\r
-int OpMovep(int op); // notaz\r
+int OpMovep(int op);\r
int OpStopReset(int op);\r
void SuperCheck(int op);\r
-void SuperEnd(int op);\r
-void SuperChange(int op);\r
+void SuperEnd(void);\r
+void SuperChange(int op,int load_srh=1);\r
+\r
notaz.gp2x.de / picodrive.git / commitdiff