* sys reg 0004000-00040ff 1 1
* vdp reg 0004100-00041ff 5 5
* vdp pal 0004200-00043ff 5 5
- * rom 2000000-23fffff 6-15
+ * cart 2000000-23fffff 6-15
* dram/fb 4000000-401ffff 5-12 1-3
* fb ovr 4020000-403ffff
* sdram 6000000-603ffff 12 2 (cycles)
{
u32 d = 0;
+ sh2_burn_cycles(sh2, 1*2);
+
// 0x3ff00 is veridied
if ((a & 0x3ff00) == 0x4000) {
d = p32x_sh2reg_read16(a, sh2);
{
u32 d = 0;
+ sh2_burn_cycles(sh2, 1*2);
+
if ((a & 0x3ff00) == 0x4000) {
d = p32x_sh2reg_read16(a, sh2);
if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
Pico32xMem->sdram[a1 ^ 1] = d;
}
+static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2)
+{
+ // xmen sync hack..
+ if (a < 0x26000200)
+ sh2_end_run(sh2, 32);
+
+ sh2_write8_sdram(a, d, sh2);
+}
+
static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
{
u32 a1 = a & 0xfff;
// CS3 - SDRAM
sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
- sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
+ sh2_write8_map[0x06/2] = sh2_write8_sdram;
+ sh2_write8_map[0x26/2] = sh2_write8_sdram_wt;
sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r