unsigned int vbr;
// initial data
- idl_src = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3d4)) & ~0xf0000000;
- idl_dst = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3d8)) & ~0xf0000000;
- idl_size= CPU_BE2(*(unsigned int *)(Pico.rom + 0x3dc));
+ idl_src = CPU_BE2(*(u32 *)(Pico.rom + 0x3d4)) & ~0xf0000000;
+ idl_dst = CPU_BE2(*(u32 *)(Pico.rom + 0x3d8)) & ~0xf0000000;
+ idl_size= CPU_BE2(*(u32 *)(Pico.rom + 0x3dc));
if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
// VBR
- vbr = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3e8));
+ vbr = CPU_BE2(*(u32 *)(Pico.rom + 0x3e8));
sh2_set_vbr(0, vbr);
// checksum and M_OK
- Pico32x.regs[0x28 / 2] = *(unsigned short *)(Pico.rom + 0x18e);
+ Pico32x.regs[0x28 / 2] = *(u16 *)(Pico.rom + 0x18e);
}
// program will set M_OK
}
unsigned int vbr;
// GBR/VBR
- vbr = CPU_BE2(*(unsigned int *)(Pico.rom + 0x3ec));
+ vbr = CPU_BE2(*(u32 *)(Pico.rom + 0x3ec));
sh2_set_gbr(1, 0x20004000);
sh2_set_vbr(1, vbr);
// program will set S_OK
addr=PicoPatches[i].addr;
addr &= ~1;
if (addr < Pico.romsize)
- PicoPatches[i].data_old = *(unsigned short *)(Pico.rom + addr);
+ PicoPatches[i].data_old = *(u16 *)(Pico.rom + addr);
else
{
if(!(PicoIn.AHW & PAHW_SMS))
- PicoPatches[i].data_old = (unsigned short) m68k_read16(addr);
+ PicoPatches[i].data_old = (u16) m68k_read16(addr);
else
;// wrong: PicoPatches[i].data_old = (unsigned char) PicoRead8_z80(addr);
}
if (PicoPatches[i].active)
{
if (!(PicoIn.AHW & PAHW_SMS))
- *(unsigned short *)(Pico.rom + addr) = PicoPatches[i].data;
+ *(u16 *)(Pico.rom + addr) = PicoPatches[i].data;
else if (!PicoPatches[i].comp || PicoPatches[i].comp == *(char *)(Pico.rom + addr))
*(char *)(Pico.rom + addr) = (char) PicoPatches[i].data;
}
if (u == i)
{
if (!(PicoIn.AHW & PAHW_SMS))
- *(unsigned short *)(Pico.rom + addr) = PicoPatches[i].data_old;
+ *(u16 *)(Pico.rom + addr) = PicoPatches[i].data_old;
else
*(char *)(Pico.rom + addr) = (char) PicoPatches[i].data_old;
}
}
// fprintf(stderr, "patched %i: %06x:%04x\n", PicoPatches[i].active, addr,
- // *(unsigned short *)(Pico.rom + addr));
+ // *(u16 *)(Pico.rom + addr));
}
else
{
// XXX: rename\r
PICO_INTERNAL void SekPackCpu(unsigned char *cpu, int is_sub)\r
{\r
- unsigned int pc=0;\r
+ u32 pc=0;\r
\r
#if defined(EMU_C68K)\r
struct Cyclone *context = is_sub ? &PicoCpuCS68k : &PicoCpuCM68k;\r
memcpy(cpu,context->d,0x40);\r
pc=context->pc-context->membase;\r
- *(unsigned int *)(cpu+0x44)=CycloneGetSr(context);\r
- *(unsigned int *)(cpu+0x48)=context->osp;\r
+ *(u32 *)(cpu+0x44)=CycloneGetSr(context);\r
+ *(u32 *)(cpu+0x48)=context->osp;\r
cpu[0x4c] = context->irq;\r
cpu[0x4d] = context->state_flags & 1;\r
#elif defined(EMU_M68K)\r
m68k_set_context(is_sub ? &PicoCpuMS68k : &PicoCpuMM68k);\r
memcpy(cpu,m68ki_cpu_p->dar,0x40);\r
pc=m68ki_cpu_p->pc;\r
- *(unsigned int *)(cpu+0x44)=m68k_get_reg(NULL, M68K_REG_SR);\r
- *(unsigned int *)(cpu+0x48)=m68ki_cpu_p->sp[m68ki_cpu_p->s_flag^SFLAG_SET];\r
+ *(u32 *)(cpu+0x44)=m68k_get_reg(NULL, M68K_REG_SR);\r
+ *(u32 *)(cpu+0x48)=m68ki_cpu_p->sp[m68ki_cpu_p->s_flag^SFLAG_SET];\r
cpu[0x4c] = CPU_INT_LEVEL>>8;\r
cpu[0x4d] = CPU_STOPPED;\r
m68k_set_context(oldcontext);\r
M68K_CONTEXT *context = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;\r
memcpy(cpu,context->dreg,0x40);\r
pc=context->pc;\r
- *(unsigned int *)(cpu+0x44)=context->sr;\r
- *(unsigned int *)(cpu+0x48)=context->asp;\r
+ *(u32 *)(cpu+0x44)=context->sr;\r
+ *(u32 *)(cpu+0x48)=context->asp;\r
cpu[0x4c] = context->interrupts[0];\r
cpu[0x4d] = (context->execinfo & FM68K_HALTED) ? 1 : 0;\r
#endif\r
\r
- *(unsigned int *)(cpu+0x40) = pc;\r
- *(unsigned int *)(cpu+0x50) =\r
+ *(u32 *)(cpu+0x40) = pc;\r
+ *(u32 *)(cpu+0x50) =\r
is_sub ? SekCycleCntS68k : Pico.t.m68c_cnt;\r
}\r
\r
{\r
#if defined(EMU_C68K)\r
struct Cyclone *context = is_sub ? &PicoCpuCS68k : &PicoCpuCM68k;\r
- CycloneSetSr(context, *(unsigned int *)(cpu+0x44));\r
- context->osp=*(unsigned int *)(cpu+0x48);\r
+ CycloneSetSr(context, *(u32 *)(cpu+0x44));\r
+ context->osp=*(u32 *)(cpu+0x48);\r
memcpy(context->d,cpu,0x40);\r
context->membase = 0;\r
- context->pc = *(unsigned int *)(cpu+0x40);\r
+ context->pc = *(u32 *)(cpu+0x40);\r
CycloneUnpack(context, NULL); // rebase PC\r
context->irq = cpu[0x4c];\r
context->state_flags = 0;\r
#elif defined(EMU_M68K)\r
void *oldcontext = m68ki_cpu_p;\r
m68k_set_context(is_sub ? &PicoCpuMS68k : &PicoCpuMM68k);\r
- m68k_set_reg(M68K_REG_SR, *(unsigned int *)(cpu+0x44));\r
+ m68k_set_reg(M68K_REG_SR, *(u32 *)(cpu+0x44));\r
memcpy(m68ki_cpu_p->dar,cpu,0x40);\r
- m68ki_cpu_p->pc=*(unsigned int *)(cpu+0x40);\r
- m68ki_cpu_p->sp[m68ki_cpu_p->s_flag^SFLAG_SET]=*(unsigned int *)(cpu+0x48);\r
+ m68ki_cpu_p->pc=*(u32 *)(cpu+0x40);\r
+ m68ki_cpu_p->sp[m68ki_cpu_p->s_flag^SFLAG_SET]=*(u32 *)(cpu+0x48);\r
CPU_INT_LEVEL = cpu[0x4c] << 8;\r
CPU_STOPPED = cpu[0x4d];\r
m68k_set_context(oldcontext);\r
#elif defined(EMU_F68K)\r
M68K_CONTEXT *context = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;\r
memcpy(context->dreg,cpu,0x40);\r
- context->pc =*(unsigned int *)(cpu+0x40);\r
- context->sr =*(unsigned int *)(cpu+0x44);\r
- context->asp=*(unsigned int *)(cpu+0x48);\r
+ context->pc =*(u32 *)(cpu+0x40);\r
+ context->sr =*(u32 *)(cpu+0x44);\r
+ context->asp=*(u32 *)(cpu+0x48);\r
context->interrupts[0] = cpu[0x4c];\r
context->execinfo &= ~FM68K_HALTED;\r
if (cpu[0x4d]&1) context->execinfo |= FM68K_HALTED;\r
#endif\r
if (is_sub)\r
- SekCycleCntS68k = *(unsigned int *)(cpu+0x50);\r
+ SekCycleCntS68k = *(u32 *)(cpu+0x50);\r
else\r
- Pico.t.m68c_cnt = *(unsigned int *)(cpu+0x50);\r
+ Pico.t.m68c_cnt = *(u32 *)(cpu+0x50);\r
}\r
\r
\r