emu_32x_startup();
}
+void Pico32xShutdown(void)
+{
+ sh2_finish(&msh2);
+ sh2_finish(&ssh2);
+
+ Pico32x.vdp_regs[6] = P32XS_RV;
+
+ rendstatus_old = -1;
+
+ PicoIn.AHW &= ~PAHW_32X;
+ PicoMemSetup();
+ emu_32x_startup();
+}
+
void p32x_reset_sh2s(void)
{
elprintf(EL_32X, "sh2 reset");
void PicoUnload32x(void)
{
- sh2_finish(&msh2);
- sh2_finish(&ssh2);
+ Pico32xShutdown();
+
if (Pico32xMem != NULL)
plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
Pico32xMem = NULL;
-
- PicoIn.AHW &= ~PAHW_32X;
}
void PicoReset32x(void)
elprintf(EL_32X, "sh2 sync to %u", m68k_target);
- if (!(Pico32x.regs[0] & P32XS_nRES)) {
+ if (!(Pico32x.regs[0] & P32XS_nRES) || !(Pico32x.regs[0] & P32XS_ADEN)) {
msh2.m68krcycles_done = ssh2.m68krcycles_done = m68k_target;
return; // rare
}
REG8IN16(r, 0x00) = d & 0x80;
return;
case 0x01: // adapter ctl: RES and ADEN writable
- if ((d ^ r[0]) & d & P32XS_nRES)
+ if ((d ^ r[0]) & ~d & P32XS_ADEN) {
+ d |= P32XS_nRES;
+ Pico32xShutdown();
+ } else if ((d ^ r[0]) & d & P32XS_nRES)
p32x_reset_sh2s();
REG8IN16(r, 0x01) &= ~(P32XS_nRES|P32XS_ADEN);
REG8IN16(r, 0x01) |= d & (P32XS_nRES|P32XS_ADEN);
switch (a/2) {
case 0x00/2: // adapter ctl
- if ((d ^ r[0]) & d & P32XS_nRES)
+ if ((d ^ r[0]) & ~d & P32XS_ADEN) {
+ d |= P32XS_nRES;
+ Pico32xShutdown();
+ } else if ((d ^ r[0]) & d & P32XS_nRES)
p32x_reset_sh2s();
r[0] &= ~(P32XS_FM|P32XS_nRES|P32XS_ADEN);
r[0] |= d & (P32XS_FM|P32XS_nRES|P32XS_ADEN);
}
return;
}
-
+ if (a == 7) {
+ r[0x06/2] &= ~P32XS_RV;
+ r[0x06/2] |= d & P32XS_RV;
+ }
// allow only COMM for now
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)r;
}
return;
}
+ if (a == 6) {
+ r[0x06/2] &= ~P32XS_RV;
+ r[0x06/2] |= d & P32XS_RV;
+ }
// allow only COMM for now
if ((a & 0x30) == 0x20)