core, fix z80 irq handling, reset defaults (cz80, drz80)

diff --git a/cpu/DrZ80/drz80.S b/cpu/DrZ80/drz80.S
index edcebb8..37e6e88 100644 (file)
--- a/cpu/DrZ80/drz80.S
+++ b/cpu/DrZ80/drz80.S
@@ -855,7 +855,8 @@ z80_xmap_rebase_sp:
        strb \reg,[z80sp,#-1]!\r
 .else\r
     mov r0,\reg\r
-       sub z80sp,z80sp,#2\r
+       subs z80sp,z80sp,#2\r
+       @ addcc z80sp,z80sp,#1<<16\r
        mov r1,z80sp\r
        writemem16\r
 .endif\r
@@ -872,7 +873,8 @@ z80_xmap_rebase_sp:
        strb r1,[z80sp,#-1]!\r
 .else\r
        mov r0,\reg,lsr #16\r
-       sub z80sp,z80sp,#2\r
+       subs z80sp,z80sp,#2\r
+       @ addcc z80sp,z80sp,#1<<16\r
        mov r1,z80sp\r
        writemem16\r
 .endif\r
@@ -1472,7 +1474,7 @@ DoInterrupt:
        ;@ r0 == z80if\r
        stmfd sp!,{r2,lr}\r
 \r
-       tst r0,#4 ;@ check halt\r
+       tst r0,#Z80_HALT ;@ check halt\r
        addne z80pc,z80pc,#1\r
 \r
        ldrb r1,[cpucontext,#z80im]\r
@@ -1503,7 +1505,8 @@ DoInterrupt_mode0:
        strb r1,[z80sp,#-1]!\r
        strb r0,[z80sp,#-1]!\r
 .else\r
-       sub z80sp,z80sp,#2\r
+       subs z80sp,z80sp,#2\r
+       @ addcc z80sp,z80sp,#1<<16\r
        mov r1,z80sp\r
        writemem16\r
        ldr r2,[cpucontext, #z80irqvector]\r
@@ -1577,7 +1580,9 @@ DoInterrupt_end:
        ;@ interupt accepted so callback irq interface\r
        ldr r0,[cpucontext, #z80irqcallback]\r
        tst r0,r0\r
-       streqb r0,[cpucontext,#z80irq]       ;@ default handling\r
+       ldreqb r0,[cpucontext,#z80irq]       ;@ default handling\r
+       biceq r0,r0,#1\r
+       streqb r0,[cpucontext,#z80irq]\r
        ldmeqfd sp!,{r2,pc}\r
        stmfd sp!,{r3,r12}\r
        mov lr,pc\r
@@ -5758,7 +5763,10 @@ opcode_F_3:
        ldrb r1,[cpucontext,#z80if]\r
        bic r1,r1,#(Z80_IF1)|(Z80_IF2)\r
        strb r1,[cpucontext,#z80if]\r
-       fetch 4\r
+\r
+       ldrb r0,[z80pc],#1\r
+       eatcycles 4\r
+       ldr pc,[opcodes, r0, lsl #2]\r
 ;@CALL P,NN\r
 opcode_F_4:\r
        tst z80f,#1<<SFlag\r

diff --git a/cpu/cz80/cz80.c b/cpu/cz80/cz80.c
index 888478e..9035601 100644 (file)
--- a/cpu/cz80/cz80.c
+++ b/cpu/cz80/cz80.c
@@ -212,6 +212,8 @@ void Cz80_Reset(cz80_struc *CPU)
 {\r
        // I, R, CPU and interrupts logic is reset, registers are untouched\r
        memset(&CPU->R, 0, (FPTR)&CPU->BasePC - (FPTR)&CPU->R);\r
+       Cz80_Set_Reg(CPU, CZ80_FA, 0xffff);\r
+       Cz80_Set_Reg(CPU, CZ80_SP, 0xffff);\r
        Cz80_Set_Reg(CPU, CZ80_PC, 0);\r
 }\r
 \r

diff --git a/cpu/cz80/cz80_op.c b/cpu/cz80/cz80_op.c
index cf3062e..566782c 100644 (file)
--- a/cpu/cz80/cz80_op.c
+++ b/cpu/cz80/cz80_op.c
@@ -711,15 +711,6 @@ OP_EI:
                USE_CYCLES(4)\r
                if (!zIFF1)\r
                {\r
-                       zIFF1 = zIFF2 = (1 << 2);\r
-                       while (GET_OP() == 0xfb)\r
-                       {\r
-                               USE_CYCLES(4)\r
-                               PC++;\r
-#if CZ80_EMULATE_R_EXACTLY\r
-                               zR++;\r
-#endif\r
-                       }\r
                        if (CPU->IRQState)\r
                        {\r
                                CPU->Status |= CZ80_HAS_INT;\r
@@ -727,7 +718,7 @@ OP_EI:
                                CPU->ICount = 0;\r
                        }\r
                }\r
-               else zIFF2 = (1 << 2);\r
+               zIFF1 = zIFF2 = (1 << 2);\r
                goto Cz80_Exec_nocheck;\r
 \r
 /*-----------------------------------------\r

diff --git a/cpu/cz80/cz80_opED.c b/cpu/cz80/cz80_opED.c
index 71f7dbc..844d91e 100644 (file)
--- a/cpu/cz80/cz80_opED.c
+++ b/cpu/cz80/cz80_opED.c
@@ -407,36 +407,29 @@ OP_SBC16:
                RET(8)\r
 \r
 /*-----------------------------------------\r
- RETN\r
+ RETI/RETN\r
 -----------------------------------------*/\r
 \r
-       OPED(0x45): // RETN;\r
-       OPED(0x55): // RETN;\r
-       OPED(0x65): // RETN;\r
-       OPED(0x75): // RETN;\r
+       // works the same, but Z80 PIO can detect the opcode\r
+       OPED(0x45): // RETN\r
+       OPED(0x55): // RETN\r
+       OPED(0x65): // RETN\r
+       OPED(0x75): // RETN\r
+\r
+       OPED(0x4d): // RETI\r
+       OPED(0x5d): // RETI\r
+       OPED(0x6d): // RETI\r
+       OPED(0x7d): // RETI\r
                POP_16(res);\r
                SET_PC(res);\r
                if (!zIFF1 && zIFF2)\r
                {\r
-                       zIFF1 = (1 << 2);\r
                        if (CPU->IRQState)\r
                        {\r
                                CPU->Status |= CZ80_HAS_INT;\r
                        }\r
                }\r
-               else zIFF1 = zIFF2;\r
-               RET(10)\r
-\r
-/*-----------------------------------------\r
- RETI\r
------------------------------------------*/\r
-\r
-       OPED(0x4d): // RETI\r
-       OPED(0x5d): // RETI\r
-       OPED(0x6d): // RETI\r
-       OPED(0x7d): // RETI\r
-               POP_16(res);\r
-               SET_PC(res);\r
+               zIFF1 = zIFF2;\r
                RET(10)\r
 \r
 /*-----------------------------------------\r

diff --git a/pico/pico_int.h b/pico/pico_int.h
index 86259cd..a3c8756 100644 (file)
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -166,7 +166,7 @@ extern struct DrZ80 drZ80;
 #define z80_run(cycles)    ((cycles) - DrZ80Run(&drZ80, cycles))\r
 #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
 #define z80_int()          drZ80.Z80_IRQ = 1\r
-#define z80_int_assert(a)  drZ80.Z80_IRQ = (a)\r
+#define z80_int_assert(a)  drZ80.Z80_IRQ = (a ? 2 : 0)\r
 #define z80_nmi()          drZ80.Z80IF |= 8\r
 \r
 #define z80_cyclesLeft     drZ80.cycles\r

diff --git a/pico/z80if.c b/pico/z80if.c
index 7fbfc34..35710cb 100644 (file)
--- a/pico/z80if.c
+++ b/pico/z80if.c
@@ -112,10 +112,11 @@ void z80_reset(void)
   drZ80.Z80IF = 0;
   drZ80.z80irqvector = 0xff0000; // RST 38h
   drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0] << 1;
+  drZ80.Z80SP = 0xffff;
+  drZ80.Z80F = 0xff;
+  drZ80.Z80A = 0xff << 24;
   // others not changed, undefined on cold boot
 /*
-  drZ80.Z80F  = (1<<2);  // set ZFlag
-  drZ80.Z80F2 = (1<<2);  // set ZFlag
   drZ80.Z80IX = 0xFFFF << 16;
   drZ80.Z80IY = 0xFFFF << 16;
 */