// program will set S_OK
}
- msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
+ msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
}
void Pico32xInit(void)
void PicoReset32x(void)
{
if (PicoAHW & PAHW_32X) {
- msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
- p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES);
+ msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDone();
+ p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VRES);
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
}
- p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT);
+ p32x_trigger_irq(NULL, SekCyclesDone(), P32XI_VINT);
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
}
-// compare cycles, handling overflows
-// check if a > b
-#define CYCLES_GT(a, b) \
- ((int)((a) - (b)) > 0)
-// check if a >= b
-#define CYCLES_GE(a, b) \
- ((int)((a) - (b)) >= 0)
-
/* events */
static void fillend_event(unsigned int now)
{
typedef void (event_cb)(unsigned int now);
-unsigned int event_times[P32X_EVENT_COUNT];
+/* times are in m68k (7.6MHz) cycles */
+unsigned int p32x_event_times[P32X_EVENT_COUNT];
static unsigned int event_time_next;
-static event_cb *event_cbs[] = {
+static event_cb *p32x_event_cbs[P32X_EVENT_COUNT] = {
[P32X_EVENT_PWM] = p32x_pwm_irq_event,
[P32X_EVENT_FILLEND] = fillend_event,
[P32X_EVENT_HINT] = hint_event,
when = (now + after) | 1;
- elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
- event_times[event] = when;
+ elprintf(EL_32X, "32x: new event #%u %u->%u", event, now, when);
+ p32x_event_times[event] = when;
if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
event_time_next = when;
sh2_end_run(sh2, left_to_next);
}
-static void run_events(unsigned int until)
+static void p32x_run_events(unsigned int until)
{
int oldest, oldest_diff, time;
int i, diff;
oldest = -1, oldest_diff = 0x7fffffff;
for (i = 0; i < P32X_EVENT_COUNT; i++) {
- if (event_times[i]) {
- diff = event_times[i] - until;
+ if (p32x_event_times[i]) {
+ diff = p32x_event_times[i] - until;
if (diff < oldest_diff) {
oldest_diff = diff;
oldest = i;
}
if (oldest_diff <= 0) {
- time = event_times[oldest];
- event_times[oldest] = 0;
- elprintf(EL_32X, "run event #%d %u", oldest, time);
- event_cbs[oldest](time);
+ time = p32x_event_times[oldest];
+ p32x_event_times[oldest] = 0;
+ elprintf(EL_32X, "32x: run event #%d %u", oldest, time);
+ p32x_event_cbs[oldest](time);
}
else if (oldest_diff < 0x7fffffff) {
- event_time_next = event_times[oldest];
+ event_time_next = p32x_event_times[oldest];
break;
}
else {
}
if (oldest != -1)
- elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
+ elprintf(EL_32X, "32x: next event #%d at %u",
+ oldest, event_time_next);
}
static inline void run_sh2(SH2 *sh2, int m68k_cycles)
while (CYCLES_GT(m68k_target, now))
{
if (event_time_next && CYCLES_GE(now, event_time_next))
- run_events(now);
+ p32x_run_events(now);
target = m68k_target;
if (event_time_next && CYCLES_GT(target, event_time_next))
}
}
-#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
+#define CPUS_RUN(m68k_cycles) do { \
SekRunM68k(m68k_cycles); \
- if (Pico32x.emu_flags & P32XF_Z80_32X_IO) \
- PicoSyncZ80(SekCycleCnt); \
+ if ((Pico32x.emu_flags & P32XF_Z80_32X_IO) && Pico.m.z80Run \
+ && !Pico.m.z80_reset && (PicoOpt & POPT_EN_Z80)) \
+ PicoSyncZ80(SekCyclesDone()); \
if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
- p32x_sync_sh2s(SekCyclesDoneT2()); \
+ p32x_sync_sh2s(SekCyclesDone()); \
} while (0)
#define PICO_32X
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
if (!(Pico32x.sh2_regs[0] & 0x80))
- p32x_schedule_hint(NULL, SekCyclesDoneT2());
+ p32x_schedule_hint(NULL, SekCyclesDone());
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
return;
}
- SekCycleCnt = 0;
- sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
- p32x_update_irls(NULL, SekCycleCntT);
+ sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCyclesDone();
+ p32x_update_irls(NULL, SekCyclesDone());
p32x_pwm_state_loaded();
- run_events(SekCycleCntT);
+ p32x_run_events(SekCyclesDone());
}
// vim:shiftwidth=2:ts=2:expandtab
#else
if ((a & 0x30) == 0x20) {
static u32 dr2 = 0;
- unsigned int cycles = SekCyclesDoneT();
+ unsigned int cycles = SekCyclesDone();
int comreg = 1 << (a & 0x0f) / 2;
// evil X-Men proto polls in a dbra loop and expects it to expire..
#endif
if (a == 2) { // INTM, INTS
- unsigned int cycles = SekCyclesDoneT();
+ unsigned int cycles = SekCyclesDone();
if (cycles - msh2.m68krcycles_done > 64)
p32x_sync_sh2s(cycles);
goto out;
}
if ((a & 0x30) == 0x30)
- return p32x_pwm_read16(a, NULL, SekCyclesDoneT());
+ return p32x_pwm_read16(a, NULL, SekCyclesDone());
out:
return Pico32x.regs[a / 2];
r[6 / 2] &= ~P32XS_68S;
if ((Pico32x.dmac0_fifo_ptr & 3) == 0) {
- p32x_sync_sh2s(SekCyclesDoneT());
+ p32x_sync_sh2s(SekCyclesDone());
p32x_dreq0_trigger();
}
}
return;
case 0x03: // irq ctl
if ((d ^ r[0x02 / 2]) & 3) {
- int cycles = SekCyclesDoneT();
+ int cycles = SekCyclesDone();
p32x_sync_sh2s(cycles);
r[0x02 / 2] = d & 3;
p32x_update_cmd_irq(NULL, cycles);
case 0x3f:
return;
pwm_write:
- p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDoneT());
+ p32x_pwm_write16(a & ~1, d, NULL, SekCyclesDone());
return;
}
if ((a & 0x30) == 0x20) {
- int cycles = SekCyclesDoneT();
+ int cycles = SekCyclesDone();
int comreg;
if (REG8IN16(r, a) == d)
case 0x30: // PWM control
d = (r[a / 2] & ~0x0f) | (d & 0x0f);
r[a / 2] = d;
- p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
+ p32x_pwm_write16(a, d, NULL, SekCyclesDone());
return;
}
// comm port
if ((a & 0x30) == 0x20) {
- int cycles = SekCyclesDoneT();
+ int cycles = SekCyclesDone();
int comreg;
if (r[a / 2] == d)
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
+ p32x_pwm_write16(a, d, NULL, SekCyclesDone());
return;
}
int p = 0;
int xmd;
- consume_fifo(NULL, SekCyclesDoneT2());
+ consume_fifo(NULL, SekCyclesDone());
xmd = Pico32x.regs[0x30 / 2] & 0x0f;
if (xmd == 0 || xmd == 0x06 || xmd == 0x09 || xmd == 0x0f)
p32x_pwm_ctl_changed();
// for old savestates
- cycles_diff_sh2 = SekCycleCntT * 3 - Pico32x.pwm_cycle_p;
+ cycles_diff_sh2 = SekCycleCnt * 3 - Pico32x.pwm_cycle_p;
if (cycles_diff_sh2 >= pwm_cycles || cycles_diff_sh2 < 0) {
Pico32x.pwm_irq_cnt = pwm_irq_reload;
- Pico32x.pwm_cycle_p = SekCycleCntT * 3;
- p32x_pwm_schedule(SekCycleCntT);
+ Pico32x.pwm_cycle_p = SekCycleCnt * 3;
+ p32x_pwm_schedule(SekCycleCnt);
}
}
{
chan->chcr |= DMA_TE; // DMA has ended normally
- p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
+ p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
if (chan->chcr & DMA_IE)
dmac_te_irq(sh2, chan);
}
unsigned short *dest;\r
unsigned char *src;\r
\r
- if (Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
+ if (1) //Pico_mcd->cdc.DBC.N <= (CDC_DMA_SPEED * 2))\r
{\r
length = (Pico_mcd->cdc.DBC.N + 1) >> 1;\r
Pico_mcd->scd.Status_CDC &= ~0x08; // Last transfer\r
{\r
Pico_mcd->cdc.IFSTAT &= ~0x40;\r
\r
- if (Pico_mcd->s68k_regs[0x33] & (1<<5))\r
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN5)\r
{\r
elprintf(EL_INTS, "cdc DTE irq 5");\r
SekInterruptS68k(5);\r
cdprintf("************** Starting Data Transfer ***********");\r
cdprintf("RS0 = %.4X DAC = %.4X DBC = %.4X DMA adr = %.4X\n\n", Pico_mcd->s68k_regs[4]<<8,\r
Pico_mcd->cdc.DAC.N, Pico_mcd->cdc.DBC.N, (Pico_mcd->s68k_regs[0xA]<<8) | Pico_mcd->s68k_regs[0xB]);\r
+\r
+ // tmp\r
+ {\r
+ int ddx = Pico_mcd->s68k_regs[4] & 7;\r
+ if (ddx < 2) break; // invalid\r
+ if (ddx < 4) {\r
+ Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port\r
+ break;\r
+ }\r
+ if (ddx == 6) break; // invalid\r
+\r
+ pcd_event_schedule_s68k(PCD_EVENT_DMA, Pico_mcd->cdc.DBC.N / 2);\r
+ }\r
}\r
break;\r
\r
\r
Pico_mcd->s68k_regs[0x37] &= 3; // CDD.Control\r
\r
- if (Pico_mcd->s68k_regs[0x33] & (1<<4))\r
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4)\r
{\r
elprintf(EL_INTS, "cdd export irq 4");\r
SekInterruptS68k(4);\r
#define _rot_comp Pico_mcd->rot_comp
-static const int Table_Rot_Time[] =
-{
- 0x00054000, 0x00048000, 0x00040000, 0x00036000, //; 008-032 ; briefing - sprite
- 0x0002E000, 0x00028000, 0x00024000, 0x00022000, //; 036-064 ; arbre souvent
- 0x00021000, 0x00020000, 0x0001E000, 0x0001B800, //; 068-096 ; map thunderstrike
- 0x00019800, 0x00017A00, 0x00015C00, 0x00013E00, //; 100-128 ; logo défoncé
-
- 0x00012000, 0x00011800, 0x00011000, 0x00010800, //; 132-160 ; briefing - map
- 0x00010000, 0x0000F800, 0x0000F000, 0x0000E800, //; 164-192
- 0x0000E000, 0x0000D800, 0x0000D000, 0x0000C800, //; 196-224
- 0x0000C000, 0x0000B800, 0x0000B000, 0x0000A800, //; 228-256 ; batman visage
-
- 0x0000A000, 0x00009F00, 0x00009E00, 0x00009D00, //; 260-288
- 0x00009C00, 0x00009B00, 0x00009A00, 0x00009900, //; 292-320
- 0x00009800, 0x00009700, 0x00009600, 0x00009500, //; 324-352
- 0x00009400, 0x00009300, 0x00009200, 0x00009100, //; 356-384
-
- 0x00009000, 0x00008F00, 0x00008E00, 0x00008D00, //; 388-416
- 0x00008C00, 0x00008B00, 0x00008A00, 0x00008900, //; 420-448
- 0x00008800, 0x00008700, 0x00008600, 0x00008500, //; 452-476
- 0x00008400, 0x00008300, 0x00008200, 0x00008100, //; 480-512
-};
-
+static void gfx_do_line(unsigned int func, unsigned short *stamp_base,
+ unsigned int H_Dot);
static void gfx_cd_start(void)
{
- int upd_len;
+ int w, h;
+
+ w = _rot_comp.Reg_62;
+ h = _rot_comp.Reg_64;
+ if (w == 0 || h == 0) {
+ elprintf(EL_CD|EL_ANOMALY, "gfx_cd_start with %ux%u", w, h);
+ _rot_comp.Reg_64 = 0;
+ // irq?
+ return;
+ }
// _rot_comp.XD_Mul = ((_rot_comp.Reg_5C & 0x1f) + 1) * 4; // unused
_rot_comp.Function = (_rot_comp.Reg_58 & 7) | (Pico_mcd->s68k_regs[3] & 0x18); // Jmp_Adr
_rot_comp.YD = (_rot_comp.Reg_60 >> 3) & 7;
_rot_comp.Vector_Adr = (_rot_comp.Reg_66 & 0xfffe) << 2;
- upd_len = (_rot_comp.Reg_62 >> 3) & 0x3f;
- upd_len = Table_Rot_Time[upd_len];
- _rot_comp.Draw_Speed = _rot_comp.Float_Part = upd_len;
-
_rot_comp.Reg_58 |= 0x8000; // Stamp_Size, we start a new GFX operation
+ pcd_event_schedule_s68k(PCD_EVENT_GFX, 5 * w * h);
+
switch (_rot_comp.Reg_58 & 6) // Scr_16?
{
case 0: // ?
break;
}
- dprintf("gfx_cd_start, stamp_map_addr=%06x", _rot_comp.Stamp_Map_Adr);
+ if (PicoOpt & POPT_EN_MCD_GFX)
+ {
+ unsigned int func = _rot_comp.Function;
+ unsigned short *stamp_base = (unsigned short *) (Pico_mcd->word_ram2M + _rot_comp.Stamp_Map_Adr);
- gfx_cd_update();
+ while (h--)
+ gfx_do_line(func, stamp_base, w);
+ }
}
-static void gfx_completed(void)
+PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a)
{
- _rot_comp.Reg_58 &= 0x7fff; // Stamp_Size
- _rot_comp.Reg_64 = 0;
- if (Pico_mcd->s68k_regs[0x33] & (1<<1))
- {
- elprintf(EL_INTS, "gfx_cd irq 1");
- SekInterruptS68k(1);
+ unsigned int d = 0;
+
+ switch (a) {
+ case 0x58: d = _rot_comp.Reg_58; break;
+ case 0x5A: d = _rot_comp.Reg_5A; break;
+ case 0x5C: d = _rot_comp.Reg_5C; break;
+ case 0x5E: d = _rot_comp.Reg_5E; break;
+ case 0x60: d = _rot_comp.Reg_60; break;
+ case 0x62: d = _rot_comp.Reg_62; break;
+ case 0x64:
+ d = _rot_comp.Reg_64;
+ if (_rot_comp.Reg_64 > 1)
+ // fudge..
+ _rot_comp.Reg_64--;
+ break;
+ case 0x66: break;
+ default: dprintf("gfx_cd_read FIXME: unexpected address: %02x", a); break;
}
-}
+ dprintf("gfx_cd_read(%02x) = %04x", a, d);
+
+ return d;
+
+}
-static void gfx_do(unsigned int func, unsigned short *stamp_base, unsigned int H_Dot)
+static void gfx_do_line(unsigned int func, unsigned short *stamp_base,
+ unsigned int H_Dot)
{
unsigned int eax, ebx, ecx, edx, esi, edi, pixel;
unsigned int XD, Buffer_Adr;
}
-PICO_INTERNAL void gfx_cd_update(void)
-{
- int V_Dot = _rot_comp.Reg_64 & 0xff;
- int jobs;
-
- dprintf("gfx_cd_update, Reg_64 = %04x", _rot_comp.Reg_64);
-
- if (!V_Dot)
- {
- gfx_completed();
- return;
- }
-
- jobs = _rot_comp.Float_Part >> 16;
-
- if (!jobs)
- {
- _rot_comp.Float_Part += _rot_comp.Draw_Speed;
- return;
- }
-
- _rot_comp.Float_Part &= 0xffff;
- _rot_comp.Float_Part += _rot_comp.Draw_Speed;
-
- if (PicoOpt & POPT_EN_MCD_GFX)
- {
- unsigned int func = _rot_comp.Function;
- unsigned int H_Dot = _rot_comp.Reg_62 & 0x1ff;
- unsigned short *stamp_base = (unsigned short *) (Pico_mcd->word_ram2M + _rot_comp.Stamp_Map_Adr);
-
- while (jobs--)
- {
- gfx_do(func, stamp_base, H_Dot); // jmp [Jmp_Adr]:
-
- V_Dot--; // dec byte [V_Dot]
- if (V_Dot == 0)
- {
- // GFX_Completed:
- gfx_completed();
- return;
- }
- }
- }
- else
- {
- if (jobs >= V_Dot)
- {
- gfx_completed();
- return;
- }
- V_Dot -= jobs;
- }
-
- _rot_comp.Reg_64 = V_Dot;
-}
-
-
-PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a)
-{
- unsigned int d = 0;
-
- switch (a) {
- case 0x58: d = _rot_comp.Reg_58; break;
- case 0x5A: d = _rot_comp.Reg_5A; break;
- case 0x5C: d = _rot_comp.Reg_5C; break;
- case 0x5E: d = _rot_comp.Reg_5E; break;
- case 0x60: d = _rot_comp.Reg_60; break;
- case 0x62: d = _rot_comp.Reg_62; break;
- case 0x64: d = _rot_comp.Reg_64; break;
- case 0x66: break;
- default: dprintf("gfx_cd_read FIXME: unexpected address: %02x", a); break;
- }
-
- dprintf("gfx_cd_read(%02x) = %04x", a, d);
-
- return d;
-}
-
PICO_INTERNAL_ASM void gfx_cd_write16(unsigned int a, unsigned int d)
{
dprintf("gfx_cd_write16(%x, %04x)", a, d);
+ if (_rot_comp.Reg_58 & 0x8000)
+ elprintf(EL_CD|EL_ANOMALY, "cd: busy gfx reg write %02x %04x", a, d);
+
switch (a) {
case 0x58: // .Reg_Stamp_Size
_rot_comp.Reg_58 = d & 7;
} Rot_Comp;
-PICO_INTERNAL void gfx_cd_update(void);
-
PICO_INTERNAL_ASM unsigned int gfx_cd_read(unsigned int a);
PICO_INTERNAL_ASM void gfx_cd_write16(unsigned int a, unsigned int d);
case 0xA:\r
elprintf(EL_UIO, "m68k FIXME: reserved read");\r
goto end;\r
- case 0xC:\r
- d = Pico_mcd->m.timer_stopwatch >> 16;\r
+ case 0xC: // 384 cycle stopwatch timer\r
+ // ugh..\r
+ d = pcd_cycles_m68k_to_s68k(SekCyclesDone());\r
+ d = (d - Pico_mcd->m.stopwatch_base_c) / 384;\r
+ d &= 0x0fff;\r
elprintf(EL_CDREGS, "m68k stopwatch timer read (%04x)", d);\r
goto end;\r
}\r
case 8:\r
return Read_CDC_Host(1); // Gens returns 0 here on byte reads\r
case 0xC:\r
- d = Pico_mcd->m.timer_stopwatch >> 16;\r
+ d = SekCyclesDoneS68k() - Pico_mcd->m.stopwatch_base_c;\r
+ d /= 384;\r
+ d &= 0x0fff;\r
elprintf(EL_CDREGS, "s68k stopwatch timer read (%04x)", d);\r
return d;\r
case 0x30:\r
elprintf(EL_CDREGS, "s68k set CDC dma addr");\r
break;\r
case 0xc:\r
- case 0xd:\r
- elprintf(EL_CDREGS, "s68k set stopwatch timer");\r
- Pico_mcd->m.timer_stopwatch = 0;\r
+ case 0xd: // 384 cycle stopwatch timer\r
+ elprintf(EL_CDREGS|EL_CD, "s68k clear stopwatch (%x)", d);\r
+ // does this also reset internal 384 cycle counter?\r
+ Pico_mcd->m.stopwatch_base_c = SekCyclesDoneS68k();\r
return;\r
case 0xe:\r
Pico_mcd->s68k_regs[0xf] = (d>>1) | (d<<7); // ror8 1, Gens note: Dragons lair\r
return;\r
- case 0x31:\r
- elprintf(EL_CDREGS, "s68k set int3 timer: %02x", d);\r
- Pico_mcd->m.timer_int3 = (d & 0xff) << 16;\r
+ case 0x31: // 384 cycle int3 timer\r
+ d &= 0xff;\r
+ elprintf(EL_CDREGS|EL_CD, "s68k set int3 timer: %02x", d);\r
+ Pico_mcd->s68k_regs[a] = (u8) d;\r
+ if (d) // d or d+1??\r
+ pcd_event_schedule_s68k(PCD_EVENT_TIMER3, d * 384);\r
+ else\r
+ pcd_event_schedule(0, PCD_EVENT_TIMER3, 0);\r
break;\r
case 0x33: // IRQ mask\r
- elprintf(EL_CDREGS, "s68k irq mask: %02x", d);\r
- if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r
- CDD_Export_Status();\r
+ elprintf(EL_CDREGS|EL_CD, "s68k irq mask: %02x", d);\r
+ d &= 0x7e;\r
+ if ((d ^ Pico_mcd->s68k_regs[0x33]) & d & PCDS_IEN4) {\r
+ if (Pico_mcd->s68k_regs[0x37] & 4)\r
+ CDD_Export_Status();\r
}\r
break;\r
case 0x34: // fader\r
#endif\r
}\r
\r
-void PicoMemStateLoaded(void)\r
+void pcd_state_loaded_mem(void)\r
{\r
int r3 = Pico_mcd->s68k_regs[3];\r
\r
}\r
#endif // EMU_M68K\r
\r
+// vim:shiftwidth=2:ts=2:expandtab\r
/*
* PicoDrive
- * (C) notaz, 2007
+ * (C) notaz, 2007,2013
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
#include "../sound/ym2612.h"
extern unsigned char formatted_bram[4*0x10];
-extern unsigned int s68k_poll_adclk;
+
+static unsigned int m68k_cycle_mult;
void (*PicoMCDopenTray)(void) = NULL;
void (*PicoMCDcloseTray)(void) = NULL;
}
SRam.start = SRam.end = 0; // unused
+ pcd_event_schedule(0, PCD_EVENT_CDC, 12500000/75);
+
return 0;
}
-static __inline void SekRunS68k(int cyc)
+static __inline void SekRunS68k(unsigned int to)
{
int cyc_do;
- SekCycleAimS68k+=cyc;
- if ((cyc_do=SekCycleAimS68k-SekCycleCntS68k) <= 0) return;
-#if defined(EMU_CORE_DEBUG)
- SekCycleCntS68k+=CM_compareRun(cyc_do, 1);
-#elif defined(EMU_C68K)
- PicoCpuCS68k.cycles=cyc_do;
+
+ SekCycleAimS68k = to;
+ if ((cyc_do = SekCycleAimS68k - SekCycleCntS68k) <= 0)
+ return;
+
+ SekCycleCntS68k += cyc_do;
+#if defined(EMU_C68K)
+ PicoCpuCS68k.cycles = cyc_do;
CycloneRun(&PicoCpuCS68k);
- SekCycleCntS68k+=cyc_do-PicoCpuCS68k.cycles;
+ SekCycleCntS68k -= PicoCpuCS68k.cycles;
#elif defined(EMU_M68K)
m68k_set_context(&PicoCpuMS68k);
- SekCycleCntS68k+=m68k_execute(cyc_do);
+ SekCycleCntS68k += m68k_execute(cyc_do) - cyc_do;
m68k_set_context(&PicoCpuMM68k);
#elif defined(EMU_F68K)
- g_m68kcontext=&PicoCpuFS68k;
- SekCycleCntS68k+=fm68k_emulate(cyc_do, 0, 0);
- g_m68kcontext=&PicoCpuFM68k;
+ g_m68kcontext = &PicoCpuFS68k;
+ SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0) - cyc_do;
+ g_m68kcontext = &PicoCpuFM68k;
#endif
}
-#define PS_STEP_M68K ((488<<16)/20) // ~24
-//#define PS_STEP_S68K 13
-#if defined(_ASM_CD_PICO_C)
-extern void SekRunPS(int cyc_m68k, int cyc_s68k);
-#elif defined(EMU_F68K)
-static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
+unsigned int pcd_cycles_m68k_to_s68k(unsigned int c)
{
- SekCycleAim+=cyc_m68k;
- SekCycleAimS68k+=cyc_s68k;
- fm68k_emulate(0, 1, 0);
+ return (long long)c * m68k_cycle_mult >> 16;
}
-#else
-static __inline void SekRunPS(int cyc_m68k, int cyc_s68k)
+
+/* events */
+static void pcd_cdc_event(unsigned int now)
{
- int cycn, cycn_s68k, cyc_do;
- SekCycleAim+=cyc_m68k;
- SekCycleAimS68k+=cyc_s68k;
+ // 75Hz CDC update
+ Check_CD_Command();
+ pcd_event_schedule(now, PCD_EVENT_CDC, 12500000/75);
+}
-// fprintf(stderr, "=== start %3i/%3i [%3i/%3i] {%05i.%i} ===\n", cyc_m68k, cyc_s68k,
-// SekCycleAim-SekCycleCnt, SekCycleAimS68k-SekCycleCntS68k, Pico.m.frame_count, Pico.m.scanline);
+static void pcd_int3_timer_event(unsigned int now)
+{
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN3) {
+ elprintf(EL_INTS|EL_CD, "s68k: timer irq 3");
+ SekInterruptS68k(3);
+ }
- /* loop 488 downto 0 in steps of PS_STEP */
- for (cycn = (488<<16)-PS_STEP_M68K; cycn >= 0; cycn -= PS_STEP_M68K)
- {
- cycn_s68k = (cycn + cycn/2 + cycn/8) >> 16;
- if ((cyc_do = SekCycleAim-SekCycleCnt-(cycn>>16)) > 0) {
-#if defined(EMU_C68K)
- PicoCpuCM68k.cycles = cyc_do;
- CycloneRun(&PicoCpuCM68k);
- SekCycleCnt += cyc_do - PicoCpuCM68k.cycles;
-#elif defined(EMU_M68K)
- m68k_set_context(&PicoCpuMM68k);
- SekCycleCnt += m68k_execute(cyc_do);
-#elif defined(EMU_F68K)
- g_m68kcontext = &PicoCpuFM68k;
- SekCycleCnt += fm68k_emulate(cyc_do, 0, 0);
-#endif
- }
- if ((cyc_do = SekCycleAimS68k-SekCycleCntS68k-cycn_s68k) > 0) {
-#if defined(EMU_C68K)
- PicoCpuCS68k.cycles = cyc_do;
- CycloneRun(&PicoCpuCS68k);
- SekCycleCntS68k += cyc_do - PicoCpuCS68k.cycles;
-#elif defined(EMU_M68K)
- m68k_set_context(&PicoCpuMS68k);
- SekCycleCntS68k += m68k_execute(cyc_do);
-#elif defined(EMU_F68K)
- g_m68kcontext = &PicoCpuFS68k;
- SekCycleCntS68k += fm68k_emulate(cyc_do, 0, 0);
-#endif
+ if (Pico_mcd->s68k_regs[0x31] != 0)
+ pcd_event_schedule(now, PCD_EVENT_TIMER3,
+ Pico_mcd->s68k_regs[0x31] * 384);
+}
+
+static void pcd_gfx_event(unsigned int now)
+{
+ // update gfx chip
+ if (Pico_mcd->rot_comp.Reg_58 & 0x8000) {
+ Pico_mcd->rot_comp.Reg_58 &= 0x7fff;
+ Pico_mcd->rot_comp.Reg_64 = 0;
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1) {
+ elprintf(EL_INTS |EL_CD, "s68k: gfx_cd irq 1");
+ SekInterruptS68k(1);
}
}
}
-#endif
+static void pcd_dma_event(unsigned int now)
+{
+ int ddx = Pico_mcd->s68k_regs[4] & 7;
+ Update_CDC_TRansfer(ddx);
+}
-static __inline void check_cd_dma(void)
+typedef void (event_cb)(unsigned int now);
+
+/* times are in s68k (12.5MHz) cycles */
+unsigned int pcd_event_times[PCD_EVENT_COUNT];
+static unsigned int event_time_next;
+static event_cb *pcd_event_cbs[PCD_EVENT_COUNT] = {
+ [PCD_EVENT_CDC] = pcd_cdc_event,
+ [PCD_EVENT_TIMER3] = pcd_int3_timer_event,
+ [PCD_EVENT_GFX] = pcd_gfx_event,
+ [PCD_EVENT_DMA] = pcd_dma_event,
+};
+
+void pcd_event_schedule(unsigned int now, enum pcd_event event, int after)
{
- int ddx;
+ unsigned int when;
+
+ when = now + after;
+ if (when == 0) {
+ // event cancelled
+ pcd_event_times[event] = 0;
+ return;
+ }
- if (!(Pico_mcd->scd.Status_CDC & 0x08)) return;
+ when |= 1;
- ddx = Pico_mcd->s68k_regs[4] & 7;
- if (ddx < 2) return; // invalid
- if (ddx < 4) {
- Pico_mcd->s68k_regs[4] |= 0x40; // Data set ready in host port
- return;
- }
- if (ddx == 6) return; // invalid
+ elprintf(EL_CD, "cd: new event #%u %u->%u", event, now, when);
+ pcd_event_times[event] = when;
- Update_CDC_TRansfer(ddx); // now go and do the actual transfer
+ if (event_time_next == 0 || CYCLES_GT(event_time_next, when))
+ event_time_next = when;
}
-static __inline void update_chips(void)
+void pcd_event_schedule_s68k(enum pcd_event event, int after)
{
- int counter_timer, int3_set;
- int counter75hz_lim = Pico.m.pal ? 2080 : 2096;
+ if (SekCyclesLeftS68k > after)
+ SekEndRunS68k(after);
- // 75Hz CDC update
- if ((Pico_mcd->m.counter75hz+=10) >= counter75hz_lim) {
- Pico_mcd->m.counter75hz -= counter75hz_lim;
- Check_CD_Command();
- }
+ pcd_event_schedule(SekCyclesDoneS68k(), event, after);
+}
- // update timers
- counter_timer = Pico.m.pal ? 0x21630 : 0x2121c; // 136752 : 135708;
- Pico_mcd->m.timer_stopwatch += counter_timer;
- if ((int3_set = Pico_mcd->s68k_regs[0x31])) {
- Pico_mcd->m.timer_int3 -= counter_timer;
- if (Pico_mcd->m.timer_int3 < 0) {
- if (Pico_mcd->s68k_regs[0x33] & (1<<3)) {
- elprintf(EL_INTS, "s68k: timer irq 3");
- SekInterruptS68k(3);
- Pico_mcd->m.timer_int3 += int3_set << 16;
- }
- // is this really what happens if irq3 is masked out?
- Pico_mcd->m.timer_int3 &= 0xffffff;
- }
- }
+static void pcd_run_events(unsigned int until)
+{
+ int oldest, oldest_diff, time;
+ int i, diff;
+
+ while (1) {
+ oldest = -1, oldest_diff = 0x7fffffff;
+
+ for (i = 0; i < PCD_EVENT_COUNT; i++) {
+ if (pcd_event_times[i]) {
+ diff = pcd_event_times[i] - until;
+ if (diff < oldest_diff) {
+ oldest_diff = diff;
+ oldest = i;
+ }
+ }
+ }
+
+ if (oldest_diff <= 0) {
+ time = pcd_event_times[oldest];
+ pcd_event_times[oldest] = 0;
+ elprintf(EL_CD, "cd: run event #%d %u", oldest, time);
+ pcd_event_cbs[oldest](time);
+ }
+ else if (oldest_diff < 0x7fffffff) {
+ event_time_next = pcd_event_times[oldest];
+ break;
+ }
+ else {
+ event_time_next = 0;
+ break;
+ }
+ }
- // update gfx chip
- if (Pico_mcd->rot_comp.Reg_58 & 0x8000)
- gfx_cd_update();
+ if (oldest != -1)
+ elprintf(EL_CD, "cd: next event #%d at %u",
+ oldest, event_time_next);
}
+static void pcd_sync_s68k(unsigned int m68k_target)
+{
+ #define now SekCycleCntS68k
+ unsigned int s68k_target =
+ (unsigned long long)m68k_target * m68k_cycle_mult >> 16;
+ unsigned int target;
-#define PICO_CD
-#define CPUS_RUN(m68k_cycles,s68k_cycles) \
-{ \
- if ((PicoOpt&POPT_EN_MCD_PSYNC) && (Pico_mcd->m.busreq&3) == 1) { \
- SekRunPS(m68k_cycles, s68k_cycles); /* "better/perfect sync" */ \
- } else { \
- SekRunM68k(m68k_cycles); \
- if ((Pico_mcd->m.busreq&3) == 1) /* no busreq/no reset */ \
- SekRunS68k(s68k_cycles); \
- } \
+ elprintf(EL_CD, "s68k sync to %u/%u", m68k_target, s68k_target);
+
+ if ((Pico_mcd->m.busreq & 3) != 1) { /* busreq/reset */
+ SekCycleCntS68k = SekCycleAimS68k = s68k_target;
+ pcd_run_events(m68k_target);
+ return;
+ }
+
+ while (CYCLES_GT(s68k_target, now)) {
+ if (event_time_next && CYCLES_GE(now, event_time_next))
+ pcd_run_events(now);
+
+ target = s68k_target;
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+
+ SekRunS68k(target);
+ }
+ #undef now
}
+
+#define PICO_CD
+#define CPUS_RUN(m68k_cycles) \
+ SekRunM68k(m68k_cycles)
+
#include "../pico_cmn.c"
if (!(PicoOpt&POPT_ALT_RENDERER))
PicoFrameStart();
+ // ~1.63 for NTSC, ~1.645 for PAL
+ if (Pico.m.pal)
+ m68k_cycle_mult = ((12500000ull << 16) / (50*312*488));
+ else
+ m68k_cycle_mult = ((12500000ull << 16) / (60*262*488)) + 1;
+
PicoFrameHints();
}
+void pcd_state_loaded(void)
+{
+ unsigned int cycles;
+ int diff;
+
+ pcd_state_loaded_mem();
+
+ // old savestates..
+ cycles = pcd_cycles_m68k_to_s68k(SekCycleAim);
+ diff = cycles - SekCycleAimS68k;
+ if (diff < -1000 || diff > 1000) {
+ SekCycleCntS68k = SekCycleAimS68k = cycles;
+ }
+ if (pcd_event_times[PCD_EVENT_CDC] == 0) {
+ pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_CDC, 12500000/75);
+
+ if (Pico_mcd->s68k_regs[0x31])
+ pcd_event_schedule(SekCycleAimS68k, PCD_EVENT_TIMER3,
+ Pico_mcd->s68k_regs[0x31] * 384);
+
+ if (Pico_mcd->rot_comp.Reg_58 & 0x8000) {
+ Pico_mcd->rot_comp.Reg_58 &= 0x7fff;
+ Pico_mcd->rot_comp.Reg_64 = 0;
+ if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1)
+ SekInterruptS68k(1);
+ }
+ if (Pico_mcd->scd.Status_CDC & 0x08)
+ Update_CDC_TRansfer(Pico_mcd->s68k_regs[4] & 7);
+ }
+}
+// vim:shiftwidth=2:ts=2:expandtab
#include "../pico_int.h"
-int SekCycleCntS68k=0; // cycles done in this frame
-int SekCycleAimS68k=0; // cycle aim
+unsigned int SekCycleCntS68k;
+unsigned int SekCycleAimS68k;
/* context */
!!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
- sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDoneT()); MVP;
+ sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %i\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDone()); MVP;
sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
#if defined(EMU_C68K)
sprintf(dstrp - 1, ", st_flg: %x\n", PicoCpuCM68k.state_flags); MVP;
unsigned int scyc = Pico.m.eeprom_cycle, ssa = Pico.m.eeprom_slave;\r
\r
elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1,\r
- (d&2)>>1, d&1, SekCyclesDoneT() - last_write);\r
+ (d&2)>>1, d&1, SekCyclesDone() - last_write);\r
saddr &= 0x1fff;\r
\r
if(sreg & d & 2) {\r
void EEPROM_write16(unsigned int d)\r
{\r
// this diff must be at most 16 for NBA Jam to work\r
- if (SekCyclesDoneT() - last_write < 16) {\r
+ if (SekCyclesDone() - last_write < 16) {\r
// just update pending state\r
elprintf(EL_EEPROM, "eeprom: skip because cycles=%i",\r
- SekCyclesDoneT() - last_write);\r
+ SekCyclesDone() - last_write);\r
EEPROM_upd_pending(d);\r
} else {\r
int srs = Pico.m.eeprom_status;\r
EEPROM_write_do(srs >> 6); // execute pending\r
EEPROM_upd_pending(d);\r
if ((srs ^ Pico.m.eeprom_status) & 0xc0) // update time only if SDA/SCL changed\r
- last_write = SekCyclesDoneT();\r
+ last_write = SekCyclesDone();\r
}\r
}\r
\r
EEPROM_write_do(Pico.m.eeprom_status>>6);\r
\r
sreg = Pico.m.eeprom_status; saddr = Pico.m.eeprom_addr&0x1fff; scyc = Pico.m.eeprom_cycle; ssa = Pico.m.eeprom_slave;\r
- interval = SekCyclesDoneT() - last_write;\r
+ interval = SekCyclesDone() - last_write;\r
d = (sreg>>6)&1; // use SDA as "open bus"\r
\r
// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.\r
Pico.ioports[a] = d;\r
}\r
\r
+// lame..\r
+static int z80_cycles_from_68k(void)\r
+{\r
+ return z80_cycle_aim\r
+ + cycles_68k_to_z80(SekCyclesDone() - last_z80_sync);\r
+}\r
+\r
void NOINLINE ctl_write_z80busreq(u32 d)\r
{\r
d&=1; d^=1;\r
{\r
if (d)\r
{\r
- z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
+ z80_cycle_cnt = z80_cycles_from_68k();\r
}\r
else\r
{\r
- z80stopCycle = SekCyclesDone();\r
if ((PicoOpt&POPT_EN_Z80) && !Pico.m.z80_reset) {\r
pprof_start(m68k);\r
- PicoSyncZ80(z80stopCycle);\r
+ PicoSyncZ80(SekCyclesDone());\r
pprof_end_sub(m68k);\r
}\r
}\r
}\r
else\r
{\r
- z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());\r
+ z80_cycle_cnt = z80_cycles_from_68k();\r
z80_reset();\r
}\r
Pico.m.z80_reset = d;\r
}\r
\r
if ((a & 0x4000) == 0x0000) { // z80 RAM\r
- SekCyclesBurn(2); // hack\r
+ SekCyclesBurnRun(2); // FIXME hack\r
Pico.zram[a & 0x1fff] = (u8)d;\r
return;\r
}\r
timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);\r
if (ym2612.OPN.ST.mode & 1) {\r
// this is not right, should really be done on overflow only\r
- int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
+ int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
timer_a_next_oflow = (cycles << 8) + timer_a_step;\r
}\r
elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, timer_a_next_oflow>>8);\r
//ym2612.OPN.ST.TBT = 0;\r
timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800\r
if (ym2612.OPN.ST.mode & 2) {\r
- int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
+ int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
timer_b_next_oflow = (cycles << 8) + timer_b_step;\r
}\r
elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, timer_b_next_oflow>>8);\r
return 0;\r
case 0x27: { /* mode, timer control */\r
int old_mode = ym2612.OPN.ST.mode;\r
- int cycles = is_from_z80 ? z80_cyclesDone() : cycles_68k_to_z80(SekCyclesDone());\r
+ int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();\r
ym2612.OPN.ST.mode = d;\r
\r
elprintf(EL_YMTIMER, "st mode %02x", d);\r
\r
static u32 ym2612_read_local_68k(void)\r
{\r
- int xcycles = cycles_68k_to_z80(SekCyclesDone()) << 8;\r
+ int xcycles = z80_cycles_from_68k() << 8;\r
\r
ym2612_read_local();\r
\r
SekReset();\r
// s68k doesn't have the TAS quirk, so we just globally set normal TAS handler in MCD mode (used by Batman games).\r
SekSetRealTAS(PicoAHW & PAHW_MCD);\r
- SekCycleCntT = SekCycleCnt = SekCycleAim = 0;\r
+ SekCycleCnt = SekCycleAim = 0;\r
\r
if (PicoAHW & PAHW_MCD)\r
// needed for MCD to reset properly, probably some bug hides behind this..\r
\r
#include "pico_cmn.c"\r
\r
-int z80stopCycle;\r
-int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
+unsigned int last_z80_sync; /* in 68k cycles */\r
+int z80_cycle_cnt;\r
int z80_cycle_aim;\r
int z80_scanline;\r
int z80_scanline_cycles; /* cycles done until z80_scanline */\r
\r
/* sync z80 to 68k */\r
-PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done)\r
+PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done)\r
{\r
int cnt;\r
- z80_cycle_aim = cycles_68k_to_z80(m68k_cycles_done);\r
+ z80_cycle_aim += cycles_68k_to_z80(m68k_cycles_done - last_z80_sync);\r
cnt = z80_cycle_aim - z80_cycle_cnt;\r
+ last_z80_sync = m68k_cycles_done;\r
\r
pprof_start(z80);\r
\r
- elprintf(EL_BUSREQ, "z80 sync %i (%i|%i -> %i|%i)", cnt, z80_cycle_cnt, z80_cycle_cnt / 228,\r
- z80_cycle_aim, z80_cycle_aim / 228);\r
+ elprintf(EL_BUSREQ, "z80 sync %i (%u|%u -> %u|%u)", cnt,\r
+ z80_cycle_cnt, z80_cycle_cnt / 288,\r
+ z80_cycle_aim, z80_cycle_aim / 288);\r
\r
if (cnt > 0)\r
z80_cycle_cnt += z80_run(cnt);\r
#define CYCLES_M68K_LINE 488 // suitable for both PAL/NTSC
#define CYCLES_M68K_VINT_LAG 68
#define CYCLES_M68K_ASD 148
-#define CYCLES_S68K_LINE 795
-#define CYCLES_S68K_VINT_LAG 111
-#define CYCLES_S68K_ASD 241
// pad delay (for 6 button pads)
#define PAD_DELAY() { \
// CPUS_RUN
#ifndef CPUS_RUN
-#define CPUS_RUN(m68k_cycles,s68k_cycles) \
+#define CPUS_RUN(m68k_cycles) \
SekRunM68k(m68k_cycles)
#endif
pprof_start(m68k);
pevt_log_m68k_o(EVT_RUN_START);
- SekCycleAim+=cyc;
- if ((cyc_do=SekCycleAim-SekCycleCnt) <= 0)
- goto out;
-
-#if defined(EMU_CORE_DEBUG)
- // this means we do run-compare
- SekCycleCnt+=CM_compareRun(cyc_do, 0);
-#elif defined(EMU_C68K)
- PicoCpuCM68k.cycles=cyc_do;
- CycloneRun(&PicoCpuCM68k);
- SekCycleCnt+=cyc_do-PicoCpuCM68k.cycles;
+ SekCycleAim += cyc;
+ while ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
+ SekCycleCnt += cyc_do;
+
+#if defined(EMU_C68K)
+ PicoCpuCM68k.cycles = cyc_do;
+ CycloneRun(&PicoCpuCM68k);
+ SekCycleCnt -= PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
- SekCycleCnt+=m68k_execute(cyc_do);
+ SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
#elif defined(EMU_F68K)
- SekCycleCnt+=fm68k_emulate(cyc_do, 0, 0);
+ SekCycleCnt += fm68k_emulate(cyc_do, 0, 0) - cyc_do;
#endif
+ }
+
+ SekCyclesLeft = 0;
-out:
SekTrace(0);
pevt_log_m68k_o(EVT_RUN_END);
pprof_end(m68k);
{
struct PicoVideo *pv=&Pico.video;
int lines, y, lines_vis = 224, line_sample, skip, vcnt_wrap;
+ unsigned int cycles;
int hint; // Hint counter
pevt_log_m68k_o(EVT_FRAME_START);
line_sample = 93;
}
- SekCyclesReset();
z80_resetCycles();
-#ifdef PICO_CD
- SekCyclesResetS68k();
-#endif
PsndDacLine = 0;
emustatus &= ~1;
//dprintf("-hint: %i", hint);
// This is to make active scan longer (needed for Double Dragon 2, mainly)
- CPUS_RUN(CYCLES_M68K_ASD, CYCLES_S68K_ASD);
+ CPUS_RUN(CYCLES_M68K_ASD);
for (y = 0; y < lines_vis; y++)
{
}
PAD_DELAY();
-#ifdef PICO_CD
- check_cd_dma();
-#endif
// H-Interrupts:
if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
hint=pv->reg[10]; // Reload H-Int counter
pv->pending_ints|=0x10;
if (pv->reg[0]&0x10) {
- elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCycleCnt);
+ elprintf(EL_INTS, "hint: @ %06x [%i]", SekPc, SekCyclesDone());
SekInterrupt(4);
}
}
// get samples from sound chips
if ((y == 224 || y == line_sample) && PsndOut)
{
+ cycles = SekCyclesDone();
+
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
- PicoSyncZ80(SekCycleCnt);
+ PicoSyncZ80(cycles);
if (ym2612.dacen && PsndDacLine <= y)
PsndDoDAC(y);
+#ifdef PICO_CD
+ pcd_sync_s68k(cycles);
+#endif
#ifdef PICO_32X
- p32x_sync_sh2s(SekCyclesDoneT2());
+ p32x_sync_sh2s(cycles);
#endif
PsndGetSamples(y);
}
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
- CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
+ CPUS_RUN(CYCLES_M68K_LINE);
-#ifdef PICO_CD
- update_chips();
-#else
if (PicoLineHook) PicoLineHook();
-#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
}
memcpy(PicoPadInt, PicoPad, sizeof(PicoPadInt));
PAD_DELAY();
-#ifdef PICO_CD
- check_cd_dma();
-#endif
// Last H-Int:
if (--hint < 0)
{
hint=pv->reg[10]; // Reload H-Int counter
pv->pending_ints|=0x10;
- //printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCycleCnt);
+ //printf("rhint: %i @ %06x [%i|%i]\n", hint, SekPc, y, SekCyclesDone());
if (pv->reg[0]&0x10) SekInterrupt(4);
}
// there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
// also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
// also delay between last H-int and V-int (Golden Axe 3)
- CPUS_RUN(CYCLES_M68K_VINT_LAG, CYCLES_S68K_VINT_LAG);
+ CPUS_RUN(CYCLES_M68K_VINT_LAG);
if (pv->reg[1]&0x20) {
- elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCycleCnt);
+ elprintf(EL_INTS, "vint: @ %06x [%i]", SekPc, SekCyclesDone());
SekInterrupt(6);
}
+
+ cycles = SekCyclesDone();
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
- PicoSyncZ80(SekCycleCnt);
+ PicoSyncZ80(cycles);
elprintf(EL_INTS, "zint");
z80_int();
}
+#ifdef PICO_CD
+ pcd_sync_s68k(cycles);
+#endif
#ifdef PICO_32X
- p32x_sync_sh2s(SekCyclesDoneT2());
+ p32x_sync_sh2s(cycles);
p32x_start_blank();
#endif
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
- CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD,
- CYCLES_S68K_LINE - CYCLES_S68K_VINT_LAG - CYCLES_S68K_ASD);
+ CPUS_RUN(CYCLES_M68K_LINE - CYCLES_M68K_VINT_LAG - CYCLES_M68K_ASD);
-#ifdef PICO_CD
- update_chips();
-#else
if (PicoLineHook) PicoLineHook();
-#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
lines = scanlines_total;
pv->v_counter &= 0xff;
PAD_DELAY();
-#ifdef PICO_CD
- check_cd_dma();
-#endif
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
- CPUS_RUN(CYCLES_M68K_LINE, CYCLES_S68K_LINE);
+ CPUS_RUN(CYCLES_M68K_LINE);
-#ifdef PICO_CD
- update_chips();
-#else
if (PicoLineHook) PicoLineHook();
-#endif
pevt_log_m68k_o(EVT_NEXT_LINE);
}
- // sync z80
+ // sync cpus
+ cycles = SekCyclesDone();
if (Pico.m.z80Run && !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
- PicoSyncZ80(Pico.m.pal ? 151809 : 127671); // cycles adjusted for converter
+ PicoSyncZ80(cycles);
if (PsndOut && ym2612.dacen && PsndDacLine <= lines-1)
PsndDoDAC(lines-1);
+#ifdef PICO_CD
+ pcd_sync_s68k(cycles);
+#endif
#ifdef PICO_32X
- p32x_sync_sh2s(SekCyclesDoneT2());
+ p32x_sync_sh2s(cycles);
#endif
timers_cycle();
#undef PAD_DELAY
#undef CPUS_RUN
+// vim:shiftwidth=2:ts=2:expandtab
#ifdef EMU_C68K\r
#include "../cpu/cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
-#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
-#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
+#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
+#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
#define SekIrqLevel PicoCpuCM68k.irq\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
-#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
-#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
+#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
+#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
-#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
-#define SekEndTimeslice(after) SET_CYCLES(after)\r
-#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
+#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
+#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
#define SekDar(x) PicoCpuMM68k.dar[x]\r
#endif\r
#endif // EMU_M68K\r
\r
-extern int SekCycleCnt; // cycles done in this frame\r
-extern int SekCycleAim; // cycle aim\r
-extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
+// while running, cnt represents target of current timeslice\r
+// while not in SekRun(), it's actual cycles done\r
+// (but always use SekCyclesDone() if you need current position)\r
+// cnt may change if timeslice is ended prematurely or extended,\r
+// so we use SekCycleAim for the actual target\r
+extern unsigned int SekCycleCnt;\r
+extern unsigned int SekCycleAim;\r
\r
-#define SekCyclesReset() { \\r
- SekCycleCntT+=SekCycleAim; \\r
- SekCycleCnt-=SekCycleAim; \\r
- SekCycleAim=0; \\r
-}\r
-#define SekCyclesBurn(c) SekCycleCnt+=c\r
-#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
-#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
-#define SekCyclesDoneT2() (SekCycleCntT + SekCycleCnt) // same as above but not from memhandlers\r
+// number of cycles done (can be checked anywhere)\r
+#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
+\r
+// burn cycles while not in SekRun() and while in\r
+#define SekCyclesBurn(c) SekCycleCnt += c\r
+#define SekCyclesBurnRun(c) SekCyclesLeft -= c\r
\r
+// note: sometimes may extend timeslice to delay an irq\r
#define SekEndRun(after) { \\r
- SekCycleCnt -= SekCyclesLeft - (after); \\r
- if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
- SekEndTimeslice(after); \\r
+ SekCycleCnt -= SekCyclesLeft - (after); \\r
+ SekCyclesLeft = after; \\r
}\r
\r
+extern unsigned int SekCycleCntS68k;\r
+extern unsigned int SekCycleAimS68k;\r
+\r
#define SekEndRunS68k(after) { \\r
- SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
- if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
- SekEndTimesliceS68k(after); \\r
+ if (SekCyclesLeftS68k > (after)) { \\r
+ SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
+ SekCyclesLeftS68k = after; \\r
+ } \\r
}\r
\r
-extern int SekCycleCntS68k;\r
-extern int SekCycleAimS68k;\r
+#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
\r
-#define SekCyclesResetS68k() { \\r
- SekCycleCntS68k-=SekCycleAimS68k; \\r
- SekCycleAimS68k=0; \\r
-}\r
-#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
-\r
-#ifdef EMU_CORE_DEBUG\r
-extern int dbg_irq_level;\r
-#undef SekEndTimeslice\r
-#undef SekCyclesBurn\r
-#undef SekEndRun\r
-#undef SekInterrupt\r
-#define SekEndTimeslice(c)\r
-#define SekCyclesBurn(c) c\r
-#define SekEndRun(c)\r
-#define SekInterrupt(irq) dbg_irq_level=irq\r
-#endif\r
+// compare cycles, handling overflows\r
+// check if a > b\r
+#define CYCLES_GT(a, b) \\r
+ ((int)((a) - (b)) > 0)\r
+// check if a >= b\r
+#define CYCLES_GE(a, b) \\r
+ ((int)((a) - (b)) >= 0)\r
\r
// ----------------------- Z80 CPU -----------------------\r
\r
\r
#define Z80_STATE_SIZE 0x60\r
\r
-extern int z80stopCycle; /* in 68k cycles */\r
+extern unsigned int last_z80_sync;\r
extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
extern int z80_cycle_aim;\r
extern int z80_scanline;\r
extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
\r
#define z80_resetCycles() \\r
+ last_z80_sync = SekCyclesDone(); \\r
z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
\r
#define z80_cyclesDone() \\r
unsigned char busreq;\r
unsigned char s68k_pend_ints;\r
unsigned int state_flags; // 04: emu state: reset_pending\r
- unsigned int counter75hz;\r
- unsigned int pad0;\r
- int timer_int3; // 10\r
- unsigned int timer_stopwatch;\r
+ unsigned int stopwatch_base_c;\r
+ unsigned int pad[3];\r
unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
unsigned char pad2;\r
unsigned short pad3;\r
- int pad[9];\r
+ int pad4[9];\r
};\r
\r
typedef struct\r
\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
-void PicoMemStateLoaded(void);\r
+void pcd_state_loaded_mem(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int CheckDMA(void);\r
PICO_INTERNAL void PicoDetectRegion(void);\r
-PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
+PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
\r
// cd/pico.c\r
+#define PCDS_IEN1 (1<<1)\r
+#define PCDS_IEN2 (1<<2)\r
+#define PCDS_IEN3 (1<<3)\r
+#define PCDS_IEN4 (1<<4)\r
+#define PCDS_IEN5 (1<<5)\r
+#define PCDS_IEN6 (1<<6)\r
+\r
PICO_INTERNAL void PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL void PicoPowerMCD(void);\r
PICO_INTERNAL int PicoResetMCD(void);\r
PICO_INTERNAL void PicoFrameMCD(void);\r
\r
+enum pcd_event {\r
+ PCD_EVENT_CDC,\r
+ PCD_EVENT_TIMER3,\r
+ PCD_EVENT_GFX,\r
+ PCD_EVENT_DMA,\r
+ PCD_EVENT_COUNT,\r
+};\r
+extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
+void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
+void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
+unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
+void pcd_state_loaded(void);\r
+\r
// pico/pico.c\r
PICO_INTERNAL void PicoInitPico(void);\r
PICO_INTERNAL void PicoReratePico(void);\r
P32X_EVENT_HINT,\r
P32X_EVENT_COUNT,\r
};\r
-extern unsigned int event_times[P32X_EVENT_COUNT];\r
+extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
\r
void Pico32xInit(void);\r
void PicoPower32x(void);\r
#define EL_32X 0x00080000\r
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
#define EL_32XP 0x00200000 /* 32X peripherals */\r
+#define EL_CD 0x00400000 /* MCD */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
#include "memory.h"\r
\r
\r
-int SekCycleCnt=0; // cycles done in this frame\r
-int SekCycleAim=0; // cycle aim\r
-unsigned int SekCycleCntT=0;\r
+unsigned int SekCycleCnt;\r
+unsigned int SekCycleAim;\r
\r
\r
/* context */\r
#endif\r
\r
*(unsigned int *)(cpu+0x40) = pc;\r
- *(unsigned int *)(cpu+0x50) = SekCycleCntT;\r
+ *(unsigned int *)(cpu+0x50) =\r
+ is_sub ? SekCycleCntS68k : SekCycleCnt;\r
}\r
\r
PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub)\r
context->execinfo &= ~FM68K_HALTED;\r
if (cpu[0x4d]&1) context->execinfo |= FM68K_HALTED;\r
#endif\r
- SekCycleCntT = *(unsigned int *)(cpu+0x50);\r
+ if (is_sub)\r
+ SekCycleCntS68k = *(unsigned int *)(cpu+0x50);\r
+ else\r
+ SekCycleCnt = *(unsigned int *)(cpu+0x50);\r
}\r
\r
\r
CHUNK_32X_EVT,\r
CHUNK_32X_FIRST = CHUNK_MSH2,\r
CHUNK_32X_LAST = CHUNK_32X_EVT,\r
+ // add new stuff here\r
+ CHUNK_CD_EVT = 50,\r
//\r
CHUNK_DEFAULT_COUNT,\r
- CHUNK_CARTHW_ = CHUNK_CARTHW, // defined in PicoInt\r
+ CHUNK_CARTHW_ = CHUNK_CARTHW, // 64 (defined in PicoInt)\r
} chunk_name_e;\r
\r
static const char * const chunk_names[] = {\r
CHECKED_WRITE_BUFF(CHUNK_SCD, Pico_mcd->scd);\r
CHECKED_WRITE_BUFF(CHUNK_RC, Pico_mcd->rot_comp);\r
CHECKED_WRITE_BUFF(CHUNK_MISC_CD, Pico_mcd->m);\r
+ memset(buff, 0, 0x40);\r
+ memcpy(buff, pcd_event_times, sizeof(pcd_event_times));\r
+ CHECKED_WRITE(CHUNK_CD_EVT, 0x40, buff);\r
\r
if (Pico_mcd->s68k_regs[3] & 4) // convert back\r
wram_2M_to_1M(Pico_mcd->word_ram2M);\r
CHECKED_WRITE_BUFF(CHUNK_32XPAL, Pico32xMem->pal);\r
\r
memset(buff, 0, 0x40);\r
- memcpy(buff, event_times, sizeof(event_times));\r
+ memcpy(buff, p32x_event_times, sizeof(p32x_event_times));\r
CHECKED_WRITE(CHUNK_32X_EVT, 0x40, buff);\r
}\r
#endif\r
R_ERROR_RETURN("bad header");\r
CHECKED_READ(4, &ver);\r
\r
+ memset(pcd_event_times, 0, sizeof(pcd_event_times));\r
+ memset(p32x_event_times, 0, sizeof(p32x_event_times));\r
+\r
while (!areaEof(file))\r
{\r
CHECKED_READ(1, &chunk);\r
case CHUNK_RC: CHECKED_READ_BUFF(Pico_mcd->rot_comp); break;\r
case CHUNK_MISC_CD: CHECKED_READ_BUFF(Pico_mcd->m); break;\r
\r
+ case CHUNK_CD_EVT:\r
+ CHECKED_READ_BUFF(buff);\r
+ memcpy(pcd_event_times, buff, sizeof(pcd_event_times));\r
+ break;\r
+\r
// 32x stuff\r
#ifndef NO_32X\r
case CHUNK_MSH2:\r
\r
case CHUNK_32X_EVT:\r
CHECKED_READ_BUFF(buff);\r
- memcpy(event_times, buff, sizeof(event_times));\r
+ memcpy(p32x_event_times, buff, sizeof(p32x_event_times));\r
break;\r
#endif\r
default:\r
if (PicoAHW & PAHW_SMS)\r
PicoStateLoadedMS();\r
\r
- if (PicoAHW & PAHW_MCD)\r
- {\r
- PicoMemStateLoaded();\r
-\r
- if (!(Pico_mcd->s68k_regs[0x36] & 1) && (Pico_mcd->scd.Status_CDC & 1))\r
- cdda_start_play();\r
- }\r
-\r
if (PicoAHW & PAHW_32X)\r
Pico32xStateLoaded(1);\r
\r
z80_unpack(buff_z80);\r
\r
// due to dep from 68k cycles..\r
+ SekCycleAim = SekCycleCnt;\r
if (PicoAHW & PAHW_32X)\r
Pico32xStateLoaded(0);\r
+ if (PicoAHW & PAHW_MCD)\r
+ {\r
+ SekCycleAimS68k = SekCycleCntS68k;\r
+ pcd_state_loaded();\r
+\r
+ if (!(Pico_mcd->s68k_regs[0x36] & 1) && (Pico_mcd->scd.Status_CDC & 1))\r
+ cdda_start_play();\r
+ }\r
\r
return 0;\r
}\r
SekCyclesDone(), SekPc);\r
\r
Pico.m.dma_xfers += len;\r
- if ((PicoAHW & PAHW_MCD) && (PicoOpt & POPT_EN_MCD_PSYNC)) SekCyclesBurn(CheckDMA());\r
- else SekEndTimeslice(SekCyclesLeftNoMCD - CheckDMA());\r
+ SekCyclesBurnRun(CheckDMA());\r
\r
if ((source&0xe00000)==0xe00000) { // Ram\r
pd=(u16 *)(Pico.ram+(source&0xfffe));\r
pvid->lwrite_cnt++;\r
if (pvid->lwrite_cnt >= 4) pvid->status|=0x100; // FIFO full\r
if (pvid->lwrite_cnt > 4) {\r
- SekCyclesBurn(32); // penalty // 488/12-8\r
- if (SekCycleCnt>=SekCycleAim) SekEndRun(0);\r
+ SekCyclesBurnRun(32); // penalty // 488/12-8\r
}\r
elprintf(EL_ASVDP, "VDP data write: %04x [%06x] {%i} #%i @ %06x", d, Pico.video.addr,\r
Pico.video.type, pvid->lwrite_cnt, SekPc);\r
notaz.gp2x.de / picodrive.git / commitdiff