#define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
/* ldr and str */
-#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
+#define EOP_LDR_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,0,1,rn,rd,offset_12)
+#define EOP_LDRB_IMM2(cond,rd,rn,offset_12) EOP_C_AM2_IMM(cond,1,1,1,rn,rd,offset_12)
#define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
#define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
#define EOP_LDR_REG_LSL(cond,rd,rn,rm,shift_imm) EOP_C_AM2_REG(cond,1,0,1,rn,rd,shift_imm,A_AM1_LSL,rm)
+#define EOP_LDRH_IMM2(cond,rd,rn,offset_8) EOP_C_AM3_IMM(cond,1,1,rn,rd,0,1,offset_8)
+
#define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
#define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
#define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
}
// fake "simple" or "short" jump - using cond insns instead
-#define EMITH_SJMP_START(cond) \
+#define EMITH_NOTHING1(cond) \
(void)(cond)
-#define EMITH_SJMP_END(cond) \
- (void)(cond)
+#define EMITH_SJMP_START(cond) EMITH_NOTHING1(cond)
+#define EMITH_SJMP_END(cond) EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_START(cond) EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_MID(cond) EMITH_NOTHING1(cond)
+#define EMITH_SJMP3_END()
#define emith_move_r_r(d, s) \
EOP_MOV_REG_SIMPLE(d, s)
#define emith_asr(d, s, cnt) \
EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ASR,cnt)
+#define emith_ror_c(cond, d, s, cnt) \
+ EOP_MOV_REG(cond,0,d,s,A_AM1_ROR,cnt)
+
#define emith_ror(d, s, cnt) \
- EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
+ emith_ror_c(A_COND_AL, d, s, cnt)
#define emith_rol(d, s, cnt) \
EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
// misc
+#define emith_read_r_r_offs_c(cond, r, rs, offs) \
+ EOP_LDR_IMM2(cond, r, rs, offs)
+
+#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
+ EOP_LDRB_IMM2(cond, r, rs, offs)
+
+#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
+ EOP_LDRH_IMM2(cond, r, rs, offs)
+
+#define emith_read_r_r_offs(r, rs, offs) \
+ emith_read_r_r_offs_c(A_COND_AL, r, rs, offs)
+
+#define emith_read8_r_r_offs(r, rs, offs) \
+ emith_read8_r_r_offs_c(A_COND_AL, r, rs, offs)
+
+#define emith_read16_r_r_offs(r, rs, offs) \
+ emith_read16_r_r_offs_c(A_COND_AL, r, rs, offs)
+
#define emith_ctx_read(r, offs) \
- EOP_LDR_IMM(r, CONTEXT_REG, offs)
+ emith_read_r_r_offs(r, CONTEXT_REG, offs)
#define emith_ctx_write(r, offs) \
EOP_STR_IMM(r, CONTEXT_REG, offs)
emith_add_r_imm(r, imm); \
}
-#define emith_or_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_or_r_imm(r, imm); \
-}
-
-#define emith_eor_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_eor_r_imm(r, imm); \
-}
-
#define emith_sub_r_imm_c(cond, r, imm) { \
(void)(cond); \
emith_sub_r_imm(r, imm); \
}
-#define emith_bic_r_imm_c(cond, r, imm) { \
- (void)(cond); \
- emith_bic_r_imm(r, imm); \
-}
-
-#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
-#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
-#define emith_ret_c(cond) emith_ret()
+#define emith_or_r_imm_c(cond, r, imm) \
+ emith_or_r_imm(r, imm)
+#define emith_eor_r_imm_c(cond, r, imm) \
+ emith_eor_r_imm(r, imm)
+#define emith_bic_r_imm_c(cond, r, imm) \
+ emith_bic_r_imm(r, imm)
+#define emith_ror_c(cond, d, s, cnt) \
+ emith_ror(d, s, cnt)
+
+#define emith_read_r_r_offs_c(cond, r, rs, offs) \
+ emith_read_r_r_offs(r, rs, offs)
+#define emith_write_r_r_offs_c(cond, r, rs, offs) \
+ emith_write_r_r_offs(r, rs, offs)
+#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
+ emith_read8_r_r_offs(r, rs, offs)
+#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
+ emith_write8_r_r_offs(r, rs, offs)
+#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
+ emith_read16_r_r_offs(r, rs, offs)
+#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
+ emith_write16_r_r_offs(r, rs, offs)
+#define emith_jump_reg_c(cond, r) \
+ emith_jump_reg(r)
+#define emith_jump_ctx_c(cond, offs) \
+ emith_jump_ctx(offs)
+#define emith_ret_c(cond) \
+ emith_ret()
// _r_r_imm
#define emith_add_r_r_imm(d, s, imm) { \
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc
-#define emith_ctx_op(op, r, offs) do { \
+#define emith_deref_op(op, r, rs, offs) do { \
/* mov r <-> [ebp+#offs] */ \
if ((offs) >= 0x80) { \
- EMIT_OP_MODRM(op, 2, r, xBP); \
+ EMIT_OP_MODRM(op, 2, r, rs); \
EMIT(offs, u32); \
} else { \
- EMIT_OP_MODRM(op, 1, r, xBP); \
+ EMIT_OP_MODRM(op, 1, r, rs); \
EMIT(offs, u8); \
} \
} while (0)
+#define emith_read_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x8b, r, rs, offs)
+
+#define emith_write_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x89, r, rs, offs)
+
+#define emith_read8_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x8a, r, rs, offs)
+
+#define emith_write8_r_r_offs(r, rs, offs) \
+ emith_deref_op(0x88, r, rs, offs)
+
+#define emith_read16_r_r_offs(r, rs, offs) { \
+ EMIT(0x66, u8); /* operand override */ \
+ emith_read_r_r_offs(r, rs, offs); \
+}
+
+#define emith_write16_r_r_offs(r, rs, offs) { \
+ EMIT(0x66, u8); \
+ emith_write16_r_r_offs(r, rs, offs) \
+}
+
#define emith_ctx_read(r, offs) \
- emith_ctx_op(0x8b, r, offs)
+ emith_read_r_r_offs(r, CONTEXT_REG, offs)
#define emith_ctx_write(r, offs) \
- emith_ctx_op(0x89, r, offs)
+ emith_write_r_r_offs(r, CONTEXT_REG, offs)
#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
int r_ = r, offs_ = offs, cnt_ = cnt; \
EMIT_OP_MODRM(0xff, 3, 2, r)
#define emith_call_ctx(offs) { \
- EMIT_OP_MODRM(0xff, 2, 2, xBP); \
+ EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
EMIT(offs, u32); \
}
EMIT_OP_MODRM(0xff, 3, 4, r)
#define emith_jump_ctx(offs) { \
- EMIT_OP_MODRM(0xff, 2, 4, xBP); \
+ EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
EMIT(offs, u32); \
}
JMP8_EMIT(cond, cond_ptr); \
}
+#define EMITH_JMP3_START(cond) { \
+ u8 *cond_ptr, *else_ptr; \
+ JMP8_POS(cond_ptr)
+
+#define EMITH_JMP3_MID(cond) \
+ JMP8_POS(else_ptr); \
+ JMP8_EMIT(cond, cond_ptr);
+
+#define EMITH_JMP3_END() \
+ JMP8_EMIT_NC(else_ptr); \
+}
+
// "simple" jump (no more then a few insns)
+// ARM will use conditional instructions here
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END
+#define EMITH_SJMP3_START EMITH_JMP3_START
+#define EMITH_SJMP3_MID EMITH_JMP3_MID
+#define EMITH_SJMP3_END EMITH_JMP3_END
+
#define host_arg2reg(rd, arg) \
switch (arg) { \
case 0: rd = xAX; break; \
// reg cache must be clean before call
static int emit_memhandler_read(int size)
{
- int ctxr;
- host_arg2reg(ctxr, 1);
- emith_move_r_r(ctxr, CONTEXT_REG);
- switch (size) {
- case 0: // 8
- // must writeback cycles for poll detection stuff
- if (reg_map_g2h[SHR_SR] != -1)
- emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
- emith_call(p32x_sh2_read8);
- break;
- case 1: // 16
- if (reg_map_g2h[SHR_SR] != -1)
- emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
- emith_call(p32x_sh2_read16);
- break;
- case 2: // 32
- emith_call(p32x_sh2_read32);
- break;
+ int arg0, arg1;
+ host_arg2reg(arg0, 0);
+
+ // must writeback cycles for poll detection stuff
+ if (reg_map_g2h[SHR_SR] != -1)
+ emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
+ arg1 = rcache_get_tmp_arg(1);
+ emith_move_r_r(arg1, CONTEXT_REG);
+
+#if 1
+ if (Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
+ int tmp = rcache_get_tmp();
+ emith_and_r_r_imm(tmp, arg0, 0xfb000000);
+ emith_cmp_r_imm(tmp, 0x02000000);
+ switch (size) {
+ case 0: // 8
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
+ emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, p32x_sh2_read8);
+ EMITH_SJMP3_END();
+ break;
+ case 1: // 16
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, p32x_sh2_read16);
+ EMITH_SJMP3_END();
+ break;
+ case 2: // 32
+ EMITH_SJMP3_START(DCOND_NE);
+ emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
+ emith_ror_c(DCOND_EQ, arg0, arg0, 16);
+ EMITH_SJMP3_MID(DCOND_NE);
+ emith_call_cond(DCOND_NE, p32x_sh2_read32);
+ EMITH_SJMP3_END();
+ break;
+ }
+ }
+ else
+#endif
+ {
+ switch (size) {
+ case 0: // 8
+ emith_call(p32x_sh2_read8);
+ break;
+ case 1: // 16
+ emith_call(p32x_sh2_read16);
+ break;
+ case 2: // 32
+ emith_call(p32x_sh2_read32);
+ break;
+ }
}
rcache_invalidate();
// assuming arg0 and retval reg matches
void PicoUnload32x(void)
{
if (Pico32xMem != NULL)
- free(Pico32xMem);
+ plat_munmap(Pico32xMem, sizeof(*Pico32xMem));
Pico32xMem = NULL;
sh2_finish(&msh2);
sh2_finish(&ssh2);
unsigned int rs;
int i;
- Pico32xMem = calloc(1, sizeof(*Pico32xMem));
+ Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem));
if (Pico32xMem == NULL) {
elprintf(EL_STATUS, "OOM");
return;
#include "../unzip/unzip_stream.h"\r
\r
\r
+static int rom_alloc_size;\r
static const char *rom_exts[] = { "bin", "gen", "smd", "iso", "sms", "gg", "sg" };\r
\r
void (*PicoCartUnloadHook)(void);\r
return 0;\r
}\r
\r
-static unsigned char *cd_realloc(void *old, int filesize)\r
-{\r
- unsigned char *rom;\r
- rom=realloc(old, sizeof(mcd_state));\r
- if (rom) memset(rom+0x20000, 0, sizeof(mcd_state)-0x20000);\r
- return rom;\r
-}\r
-\r
static unsigned char *PicoCartAlloc(int filesize, int is_sms)\r
{\r
- int alloc_size;\r
unsigned char *rom;\r
\r
- if (PicoAHW & PAHW_MCD)\r
- return cd_realloc(NULL, filesize);\r
-\r
if (is_sms) {\r
// make size power of 2 for easier banking handling\r
int s = 0, tmp = filesize;\r
s++;\r
if (filesize > (1 << s))\r
s++;\r
- alloc_size = 1 << s;\r
+ rom_alloc_size = 1 << s;\r
}\r
else {\r
+ // make alloc size at least sizeof(mcd_state),\r
+ // in case we want to switch to CD mode\r
+ if (filesize < sizeof(mcd_state))\r
+ filesize = sizeof(mcd_state);\r
+\r
// align to 512K for memhandlers\r
- alloc_size = (filesize + 0x7ffff) & ~0x7ffff;\r
+ rom_alloc_size = (filesize + 0x7ffff) & ~0x7ffff;\r
}\r
\r
- if (alloc_size - filesize < 4)\r
- alloc_size += 4; // padding for out-of-bound exec protection\r
+ if (rom_alloc_size - filesize < 4)\r
+ rom_alloc_size += 4; // padding for out-of-bound exec protection\r
\r
// Allocate space for the rom plus padding\r
- rom = calloc(alloc_size, 1);\r
+ // use special address for 32x dynarec\r
+ rom = plat_mmap(0x02000000, rom_alloc_size);\r
return rom;\r
}\r
\r
if (!(PicoAHW & PAHW_MCD) && size == 0x20000 && (!strncmp((char *)rom+0x124, "BOOT", 4) ||\r
!strncmp((char *)rom+0x128, "BOOT", 4))) {\r
PicoAHW |= PAHW_MCD;\r
- rom = cd_realloc(rom, size);\r
}\r
\r
// Check for SMD:\r
\r
if (Pico.rom != NULL) {\r
SekFinishIdleDet();\r
- free(Pico.rom);\r
- Pico.rom=NULL;\r
+ plat_munmap(Pico.rom, rom_alloc_size);\r
+ Pico.rom = NULL;\r
}\r
}\r
\r
\r
// this function should write-back d-cache and invalidate i-cache\r
// on a mem region [start_addr, end_addr)\r
-// used by SVP dynarec\r
+// used by dynarecs\r
extern void cache_flush_d_inval_i(const void *start_addr, const void *end_addr);\r
\r
+// attempt to alloc mem at specified address.\r
+// alloc anywhere else if that fails (callers should handle that)\r
+extern void *plat_mmap(unsigned long addr, size_t size);\r
+extern void plat_munmap(void *ptr, size_t size);\r
+\r
// this one should handle display mode changes\r
extern void emu_video_mode_change(int start_line, int line_count, int is_32cols);\r
\r
#include <sys/time.h>
#include <time.h>
#include <unistd.h>
+#include <sys/mman.h>
#include "../common/plat.h"
return ret;
}
+void *plat_mmap(unsigned long addr, size_t size)
+{
+ void *req, *ret;
+ req = (void *)addr;
+ ret = mmap(req, size, PROT_READ|PROT_WRITE, MAP_SHARED|MAP_ANONYMOUS, -1, 0);
+ if (ret == MAP_FAILED)
+ return NULL;
+ if (ret != req)
+ printf("warning: mmaped to %p, requested %p\n", ret, req);
+
+ return ret;
+}
+
+void plat_munmap(void *ptr, size_t size)
+{
+ munmap(ptr, size);
+}
+
notaz.gp2x.de / picodrive.git / commitdiff