// others are usual SH2 flags
sh2c->sr &= 0x3f3;
sh2c->sr |= cycles << 12;
+
+ sh2c->state |= SH2_IN_DRC;
sh2_drc_entry(sh2c);
+ sh2c->state &= ~SH2_IN_DRC;
// TODO: irq cycles
ret_cycles = (int32_t)sh2c->sr >> 12;
#define DRC_DECLARE_SR register long _sh2_sr asm(DRC_SR_REG)
#endif
#define DRC_SAVE_SR(sh2) \
- if (likely((sh2->state&(SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
+ if (likely(sh2->state & SH2_IN_DRC)) \
sh2->sr = (s32)_sh2_sr
// sh2_drc_save_sr(sh2)
#define DRC_RESTORE_SR(sh2) \
- if (likely((sh2->state&(SH2_STATE_RUN|SH2_STATE_SLEEP)) == SH2_STATE_RUN)) \
+ if (likely(sh2->state & SH2_IN_DRC)) \
_sh2_sr = (s32)sh2->sr
// sh2_drc_restore_sr(sh2)
#else
#define SH2_STATE_CPOLL (1 << 2) // polling comm regs\r
#define SH2_STATE_VPOLL (1 << 3) // polling VDP\r
#define SH2_STATE_RPOLL (1 << 4) // polling address in SDRAM\r
-#define SH2_TIMER_RUN (1 << 8) // SOC WDT timer is running\r
+#define SH2_TIMER_RUN (1 << 7) // SOC WDT timer is running\r
+#define SH2_IN_DRC (1 << 8) // DRC in use\r
unsigned int state;\r
uint32_t poll_addr;\r
int poll_cycles;\r