unsigned char irq; // [r7,#0x47] IRQ level\r
unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
unsigned int vector; // [r7,#0x4c] IRQ vector (temporary)\r
- unsigned int prev_pc;// [r7,#0x50] set to start address of currently executed opcode (if enabled in config.h)\r
+ unsigned int prev_pc;// [r7,#0x50] set to start address of currently executed opcode + 2 (if enabled in config.h)\r
unsigned int unused; // [r7,#0x54] Unused\r
int stopped; // [r7,#0x58] 1 == processor is in stopped state\r
int cycles; // [r7,#0x5c]\r
// EaCalc - ARM Register 'a' = Effective Address\r
// Trashes r0,r2 and r3\r
// size values 0, 1, 2 ~ byte, word, long\r
-int EaCalc(int a,int mask,int ea,int size,int top)\r
+int EaCalc(int a,int mask,int ea,int size,int top,int sign_extend)\r
{\r
char text[32]="";\r
int func=0;\r
if (ea<0x10)\r
{\r
int noshift=0;\r
- if (size>=2||(size==0&&top)) noshift=1; // Saves one opcode\r
+ if (size>=2||(size==0&&(top||!sign_extend))) noshift=1; // Saves one opcode\r
\r
ot(";@ EaCalc : Get register index into r%d:\n",a);\r
\r
\r
if (ea<0x30) // ($nn,An) (di)\r
{\r
- EaCalcReg(2,8,mask,0,0);\r
ot(" ldrsh r0,[r4],#2 ;@ Fetch offset\n"); pc_dirty=1;\r
+ EaCalcReg(2,8,mask,0,0);\r
ot(" ldr r2,[r7,r2,lsl #2]\n");\r
ot(" add r%d,r0,r2 ;@ Add on offset\n",a);\r
Cycles+=size<2 ? 8:12; // Extra cycles\r
// 'a' and 'v' can be anything but 0 is generally best (for both)\r
// If (ea<0x10) nothing is trashed, else r0-r3 is trashed\r
// If 'top' is given, the ARM register v shifted to the top, e.g. 0xc000 -> 0xc0000000\r
-// Otherwise the ARM register v is sign extended, e.g. 0xc000 -> 0xffffc000\r
+// If top is 0 and sign_extend is not, then ARM register v is sign extended,\r
+// e.g. 0xc000 -> 0xffffc000 (else it may or may not be sign extended)\r
\r
-int EaRead(int a,int v,int ea,int size,int mask,int top)\r
+int EaRead(int a,int v,int ea,int size,int mask,int top,int sign_extend)\r
{\r
char text[32]="";\r
int shift=0;\r
if (ea<0x10)\r
{\r
int lsl=0,low=0,i;\r
- if (size>=2||(size==0&&top)) {\r
+ if (size>=2||(size==0&&(top||!sign_extend))) {\r
if(mask)\r
for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
lsl=2-low; // Having a lsl #2 here saves one opcode\r
\r
if (top) asl=shift;\r
\r
- if (v!=a || asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r
+ if (asl) ot(" mov r%d,r%d,asl #%d\n",v,a,asl);\r
+ else if (v!=a) ot(" mov r%d,r%d\n",v,a);\r
ot("\n"); return 0;\r
}\r
\r
if (ea>=0x3a && ea<=0x3b) MemHandler(2,size,a); // Fetch\r
else MemHandler(0,size,a); // Read\r
\r
- if (v!=0 || shift) {\r
- if (shift) ot(" mov r%d,r0,asl #%d\n",v,shift);\r
- else ot(" mov r%d,r0\n",v);\r
+ if (sign_extend)\r
+ {\r
+ int d_reg=0;\r
+ if (shift) {\r
+ ot(" mov r%d,r%d,asl #%d\n",v,d_reg,shift);\r
+ d_reg=v;\r
+ }\r
+ if (!top && shift) {\r
+ ot(" mov r%d,r%d,asr #%d\n",v,d_reg,shift);\r
+ d_reg=v;\r
+ }\r
+ if (d_reg != v)\r
+ ot(" mov r%d,r%d\n",v,d_reg);\r
+ }\r
+ else\r
+ {\r
+ if (top && shift)\r
+ ot(" mov r%d,r0,asl #%d\n",v,shift);\r
+ else if (v!=0)\r
+ ot(" mov r%d,r0\n",v);\r
}\r
- if (top==0 && shift) ot(" mov r%d,r%d,asr #%d\n",v,v,shift);\r
\r
ot("\n"); return 0;\r
}\r
// Write effective address (ARM Register 'a') with ARM register 'v'\r
// Trashes r0-r3,r12,lr; 'a' can be 0 or 2+, 'v' can be 1 or higher\r
// If a==0 and v==1 it's faster though.\r
-int EaWrite(int a,int v,int ea,int size,int mask,int top)\r
+int EaWrite(int a,int v,int ea,int size,int mask,int top,int sign_extend_ea)\r
{\r
char text[32]="";\r
int shift=0;\r
if (ea<0x10)\r
{\r
int lsl=0,low=0,i;\r
- if (size>=2||(size==0&&top)) {\r
+ if (size>=2||(size==0&&(top||!sign_extend_ea))) {\r
if(mask)\r
for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is\r
lsl=2-low; // Having a lsl #x here saves one opcode\r
\r
if (ea==0x3c) { ot("Error! Write EA=0x%x\n\n",ea); return 1; }\r
\r
- if (v!=1 || shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
+ if (shift) ot(" mov r1,r%d,asr #%d\n",v,shift);\r
+ else if (v!=1) ot(" mov r1,r%d\n",v);\r
\r
MemHandler(1,size,a); // Call write handler\r
\r
char *Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
int Cycles; // Current cycles for opcode\r
int pc_dirty; // something changed PC during processing\r
+static int arm_op_count;\r
\r
\r
void ot(const char *format, ...)\r
for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
\r
+ if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
+ arm_op_count++;\r
+\r
va_start(valist,format);\r
if (AsmFile) vfprintf(AsmFile,format,valist);\r
va_end(valist);\r
static void PrintOpcodes()\r
{\r
int op=0;\r
- \r
+\r
printf("Creating Opcodes: [");\r
\r
ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
ot("\n");\r
\r
PrintFramework();\r
+ arm_op_count = 0;\r
PrintOpcodes();\r
+ printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
PrintJumpTable();\r
\r
if (ms) ot(" END\n");\r
#if (MEMHANDLERS_NEED_PREV_PC || MEMHANDLERS_NEED_CYCLES)\r
if ((sea >= 0x10 && sea != 0x3c) || (tea >= 0x10 && tea != 0x3c)) {\r
#if MEMHANDLERS_NEED_PREV_PC\r
- ot(" sub r0,r4,#2\n");\r
- ot(" str r0,[r7,#0x50] ;@ Save prev PC\n");\r
+ ot(" str r4,[r7,#0x50] ;@ Save prev PC + 2\n");\r
#endif\r
#if MEMHANDLERS_NEED_CYCLES\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
int type=0,size=0;\r
int sea=0,tea=0;\r
int use=0;\r
+ char *shiftstr="";\r
\r
// Get source and target EA\r
type=(op>>9)&7; if (type==4 || type>=7) return 1;\r
\r
EaCalc(10,0x0000, sea,size,1);\r
EaCalc(11,0x003f, tea,size,1);\r
- EaRead(10, 10, sea,size,0,1);\r
+ EaRead(10, 10, sea,size,0,0,0);\r
EaRead(11, 0, tea,size,0x003f,1);\r
\r
+ if (size==0) shiftstr=",asl #24";\r
+ else if (size==1) shiftstr=",asl #16";\r
+\r
ot(";@ Do arithmetic:\n");\r
\r
- if (type==0) ot(" orr r1,r0,r10\n");\r
- if (type==1) ot(" and r1,r0,r10\n");\r
- if (type==2) ot(" subs r1,r0,r10 ;@ Defines NZCV\n");\r
- if (type==3) ot(" adds r1,r0,r10 ;@ Defines NZCV\n");\r
- if (type==5) ot(" eor r1,r0,r10\n");\r
- if (type==6) ot(" cmp r0,r10 ;@ Defines NZCV\n");\r
+ if (type==0) ot(" orr r1,r0,r10%s\n",shiftstr);\r
+ if (type==1) ot(" and r1,r0,r10%s\n",shiftstr);\r
+ if (type==2) ot(" subs r1,r0,r10%s ;@ Defines NZCV\n",shiftstr);\r
+ if (type==3) ot(" adds r1,r0,r10%s ;@ Defines NZCV\n",shiftstr);\r
+ if (type==5) ot(" eor r1,r0,r10%s\n",shiftstr);\r
+ if (type==6) ot(" cmp r0,r10%s ;@ Defines NZCV\n",shiftstr);\r
\r
if (type<2 || type==5) ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n"); // 0,1,5\r
\r
if(type==1) Cycles=6;\r
\r
\r
- EaCalc ( 0,0x003f, sea,size);\r
- EaRead ( 0, 10, sea,size,0x003f);\r
+ // must calculate reg EA first, because of situations like: suba.w (A0)+, A0\r
+ EaCalc (10,0x0e00, dea,2,1);\r
+ EaRead (10, 11, dea,2,0x0e00);\r
\r
- EaCalc ( 0,0x0e00, dea,2,1);\r
- EaRead ( 0, 1, dea,2,0x0e00);\r
+ EaCalc ( 0,0x003f, sea,size);\r
+ EaRead ( 0, 0, sea,size,0x003f);\r
\r
- if (type==0) ot(" sub r1,r1,r10\n");\r
- if (type==1) ot(" cmp r1,r10 ;@ Defines NZCV\n");\r
+ if (type==0) ot(" sub r11,r11,r0\n");\r
+ if (type==1) ot(" cmp r11,r0 ;@ Defines NZCV\n");\r
if (type==1) OpGetFlags(1,0); // Get Cmp flags\r
- if (type==2) ot(" add r1,r1,r10\n");\r
+ if (type==2) ot(" add r11,r11,r0\n");\r
ot("\n");\r
\r
- if (type!=1) EaWrite( 0, 1, dea,2,0x0e00,1);\r
+ if (type!=1) EaWrite(10, 11, dea,2,0x0e00,1);\r
\r
OpEnd(sea);\r
\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalc (0,0x0e00,sea,0);\r
- EaRead (0, 0,sea,0,0x0e00);\r
+ EaCalc (10,0x0e00,sea,0,0,0);\r
+ EaRead (10, 10,sea,0,0x0e00,0,0);\r
+\r
+ EaCalc ( 0,0x003f,tea,size,0,0);\r
+ if (type>0)\r
+ ot(" mov r11,r0\n");\r
+ EaRead ( 0, 0,tea,size,0x003f,0,0);\r
+\r
if (tea>=0x10)\r
- ot(" and r10,r0,#7 ;@ mem - do mod 8\n");\r
- else ot(" and r10,r0,#31 ;@ reg - do mod 32\n");\r
+ ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r10,r10,#31 ;@ reg - do mod 32\n"); // size always 2\r
ot("\n");\r
\r
- EaCalc(11,0x003f,tea,size);\r
- EaRead(11, 0,tea,size,0x003f);\r
ot(" mov r1,#1\n");\r
ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");\r
ot(" bicne r9,r9,#0x40000000\n");\r
if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");\r
if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(11, 1,tea,size,0x003f);\r
+ EaWrite(11, 1,tea,size,0x003f,0,0);\r
}\r
OpEnd(tea);\r
\r
\r
OpStart(op,sea,tea);\r
\r
- ot(" mov r10,#1\n");\r
ot("\n");\r
- EaCalc ( 0,0x0000,sea,0);\r
- EaRead ( 0, 0,sea,0,0);\r
+ EaCalc ( 0,0x0000,sea,0,0,0);\r
+ EaRead ( 0, 0,sea,0,0,0,0);\r
+ ot(" mov r10,#1\n");\r
ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
if (tea>=0x10)\r
- ot(" and r0,r0,#7 ;@ mem - do mod 8\n");\r
- else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n");\r
+ ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
+ else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
ot("\n");\r
\r
if(size>=2) Cycles+=2;\r
}\r
\r
- EaCalc (11,0x003f,tea,size);\r
- EaRead (11, 0,tea,size,0x003f);\r
+ EaCalc (11,0x003f,tea,size,0,0);\r
+ EaRead (11, 0,tea,size,0x003f,0,0);\r
ot(" tst r0,r10 ;@ Do arithmetic\n");\r
ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
ot("\n");\r
if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
ot("\n");\r
- EaWrite(11, 1,tea,size,0x003f);\r
+ EaWrite(11, 1,tea,size,0x003f,0,0);\r
}\r
\r
OpEnd(sea,tea);\r
#endif\r
}\r
\r
- EaCalc (10,0x003f,ea,size);\r
+ EaCalc (10,0x003f,ea,size,0,0);\r
\r
- if (type!=1) EaRead (10,0,ea,size,0x003f); // Don't need to read for 'clr'\r
+ if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for dummy read?)\r
if (type==1) ot("\n");\r
\r
if (type==0)\r
{\r
ot(";@ Negx:\n");\r
GetXBit(1);\r
- if(size!=2) ot(" mov r0,r0,lsl #%i\n",size?16:24);\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
OpGetFlags(1,1,0);\r
if (type==2)\r
{\r
ot(";@ Neg:\n");\r
- if(size!=2) ot(" mov r0,r0,lsl #%i\n",size?16:24);\r
+ if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
ot(" rsbs r1,r0,#0\n");\r
OpGetFlags(1,1);\r
if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
if (type==3)\r
{\r
ot(";@ Not:\n");\r
- ot(" mvn r1,r0\n");\r
+ if(size!=2) {\r
+ ot(" mov r0,r0,asl #%i\n",size?16:24);\r
+ ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
+ }\r
+ else\r
+ ot(" mvn r1,r0\n");\r
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
OpGetFlags(0,0);\r
ot("\n");\r
}\r
\r
- EaWrite(10, 1,ea,size,0x003f);\r
+ EaWrite(10, 1,ea,size,0x003f,0,0);\r
\r
OpEnd(ea);\r
\r
\r
OpStart(op); Cycles=4;\r
\r
- EaCalc (10,0x0007,ea,size+1);\r
- EaRead (10, 0,ea,size+1,0x0007);\r
+ EaCalc (10,0x0007,ea,size+1,0,0);\r
+ EaRead (10, 0,ea,size+1,0x0007,0,0);\r
\r
ot(" mov r0,r0,asl #%d\n",shift);\r
ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
ot(" mov r1,r0,asr #%d\n",shift);\r
ot("\n");\r
\r
- EaWrite(10, 1,ea,size+1,0x0007);\r
+ EaWrite(10, 1,ea,size+1,0x0007,0,0);\r
\r
OpEnd();\r
return 0;\r
OpStart(op,ea); Cycles=8;\r
if (ea<8) Cycles=4;\r
\r
- ot(" mov r1,#0\n");\r
+ if (cc)\r
+ ot(" mov r1,#0\n");\r
\r
- if (cc!=1)\r
+ switch (cc)\r
{\r
- ot(";@ Is the condition true?\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
- if ((cc&~1)==2) ot(" eor r9,r9,#0x20000000 ;@ Invert carry for hi/ls\n");\r
- ot(" mvn%s r1,r1\n",cond[cc]);\r
+ case 0: // T\r
+ ot(" mvn r1,#0\n");\r
+ if (ea<8) Cycles+=2;\r
+ break;\r
+ case 1: // F\r
+ break;\r
+ case 2: // hi\r
+ ot(" ands r0,r9,#0x60000000 ;@ hi: !C && !Z\n");\r
+ ot(" mvneq r1,r1\n");\r
+ if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ case 3: // ls\r
+ ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
+ ot(" mvnne r1,r1\n");\r
+ if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
+ break;\r
+ default:\r
+ ot(";@ Is the condition true?\n");\r
+ ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
+ ot(" mvn%s r1,r1\n",cond[cc]);\r
+ if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
+ break;\r
}\r
\r
- if (cc!=1 && ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
ot("\n");\r
\r
- EaCalc (0,0x003f, ea,size);\r
- EaWrite(0, 1, ea,size,0x003f);\r
+ EaCalc (0,0x003f, ea,size,0,0);\r
+ EaWrite(0, 1, ea,size,0x003f,0,0);\r
\r
OpEnd(ea);\r
return 0;\r
\r
if (movea) size=2; // movea always expands to 32-bits\r
\r
- EaCalc (0,0x0e00,tea,size);\r
+ EaCalc (0,0x0e00,tea,size,0,0);\r
#if SPLIT_MOVEL_PD\r
if ((tea&0x38)==0x20 && size==2) { // -(An)\r
ot(" mov r10,r0\n");\r
ot(" mov r11,r1\n");\r
ot(" add r0,r0,#2\n");\r
- EaWrite(0, 1,tea,1,0x0e00);\r
+ EaWrite(0, 1,tea,1,0x0e00,0,0);\r
EaWrite(10, 11,tea,1,0x0e00,1);\r
} else {\r
- EaWrite(0, 1,tea,size,0x0e00);\r
+ EaWrite(0, 1,tea,size,0x0e00,0,0);\r
}\r
#else\r
- EaWrite(0, 1,tea,size,0x0e00);\r
+ EaWrite(0, 1,tea,size,0x0e00,0,0);\r
#endif\r
\r
#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
if (type==0 || type==1)\r
{\r
OpFlagsToReg(type==0);\r
- EaCalc (0,0x003f,ea,size);\r
- EaWrite(0, 1,ea,size,0x003f);\r
+ EaCalc (0,0x003f,ea,size,0,0);\r
+ EaWrite(0, 1,ea,size,0x003f,0,0);\r
}\r
\r
if (type==2 || type==3)\r
{\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 0,ea,size,0x003f);\r
+ EaCalc(0,0x003f,ea,size,0,0);\r
+ EaRead(0, 0,ea,size,0x003f,0,0);\r
OpRegToFlags(type==3);\r
if (type==3) {\r
SuperChange(op);\r
\r
if (size) SuperCheck(op);\r
\r
- EaCalc(0,0x003f,ea,size);\r
- EaRead(0, 10,ea,size,0x003f);\r
+ EaCalc(10,0x003f,ea,size);\r
+ EaRead(10, 10,ea,size,0x003f);\r
\r
OpFlagsToReg(size);\r
if (type==0) ot(" orr r0,r1,r10\n");\r
\r
OpStart(op,ea);\r
\r
- ot(" stmdb sp!,{r9} ;@ Push r9\n"); // can't just use r12 or lr here, because memhandlers touch them\r
ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");\r
\r
- ot("\n");\r
- ot(";@ Get the address into r9:\n");\r
- EaCalc(9,0x003f,cea,size);\r
-\r
ot(";@ r10=Register Index*4:\n");\r
- if (decr) ot(" mov r10,#0x3c ;@ order reversed for -(An)\n");\r
- else ot(" mov r10,#0\n");\r
+ if (decr) ot(" mov r10,#0x40 ;@ order reversed for -(An)\n");\r
+ else ot(" mov r10,#-4\n");\r
\r
ot("\n");\r
- ot("MoreReg%.4x%s\n",op, ms?"":":");\r
+ ot(";@ Get the address into r6:\n");\r
+ EaCalc(6,0x003f,cea,size);\r
\r
- ot(" tst r11,#1\n");\r
- ot(" beq SkipReg%.4x\n",op);\r
ot("\n");\r
+ ot(" tst r11,r11\n"); // sanity check\r
+ ot(" beq NoRegs%.4x\n",op);\r
\r
- if (decr) ot(" sub r9,r9,#%d ;@ Pre-decrement address\n",1<<size);\r
+ ot("\n");\r
+ ot("Movemloop%.4x%s\n",op, ms?"":":");\r
+ ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
+ ot(" movs r11,r11,lsr #1\n");\r
+ ot(" bcc Movemloop%.4x\n",op);\r
+ ot("\n");\r
+\r
+ if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);\r
\r
if (dir)\r
{\r
ot(" ;@ Copy memory to register:\n",1<<size);\r
- EaRead (9,0,ea,size,0x003f);\r
+ EaRead (6,0,ea,size,0x003f);\r
ot(" str r0,[r7,r10] ;@ Save value into Dn/An\n");\r
}\r
else\r
{\r
ot(" ;@ Copy register to memory:\n",1<<size);\r
ot(" ldr r1,[r7,r10] ;@ Load value from Dn/An\n");\r
- EaWrite(9,1,ea,size,0x003f);\r
+ EaWrite(6,1,ea,size,0x003f);\r
}\r
\r
- if (decr==0) ot(" add r9,r9,#%d ;@ Post-increment address\n",1<<size);\r
+ if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);\r
\r
ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);\r
- ot("\n");\r
- ot("SkipReg%.4x%s\n",op, ms?"":":");\r
- ot(" movs r11,r11,lsr #1;@ Shift mask:\n");\r
- ot(" add r10,r10,#%d ;@ r10=Next Register\n",decr?-4:4);\r
- ot(" bne MoreReg%.4x\n",op);\r
+ ot(" tst r11,r11\n");\r
+ ot(" bne Movemloop%.4x\n",op);\r
ot("\n");\r
\r
if (change)\r
{\r
ot(";@ Write back address:\n");\r
EaCalc (0,0x0007,8|(ea&7),2);\r
- EaWrite(0, 9,8|(ea&7),2,0x0007);\r
+ EaWrite(0, 6,8|(ea&7),2,0x0007);\r
}\r
\r
- ot(" ldmia sp!,{r9} ;@ Pop r9\n");\r
+ ot("NoRegs%.4x%s\n",op, ms?"":":");\r
+ ot(" ldr r6,=CycloneJumpTab ;@ restore Opcode Jump table\n");\r
ot("\n");\r
\r
if(dir) { // er\r
Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
\r
OpEnd(ea);\r
+ ot("\n");\r
+ ltorg();\r
\r
return 0;\r
}\r
extern int g_pea_cycle_table[];\r
extern int g_movem_cycle_table[];\r
int Ea_add_ns(int *tab, int ea); // add nonstandard EA cycles\r
-int EaCalc(int a,int mask,int ea,int size,int top=0);\r
-int EaRead(int a,int v,int ea,int size,int mask,int top=0);\r
+int EaCalc(int a,int mask,int ea,int size,int top=0,int sign_extend=1); // 6\r
+int EaRead(int a,int v,int ea,int size,int mask,int top=0,int sign_extend=1); // 7\r
int EaCanRead(int ea,int size);\r
-int EaWrite(int a,int v,int ea,int size,int mask,int top=0);\r
+int EaWrite(int a,int v,int ea,int size,int mask,int top=0,int sign_extend_ea=1);\r
int EaCanWrite(int ea);\r
int EaAn(int ea);\r
\r
* MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
* when memhandler was called (opcode address + unknown amount).\r
* MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
- * opcode address.\r
+ * opcode address + 2.\r
* Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
* subtract .membase to get M68k PC value.\r
* Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
notaz.gp2x.de / picodrive.git / commitdiff