\r
PicoDetectRegion();\r
Pico.video.status = 0x3428 | Pico.m.pal; // 'always set' bits | vblank | collision | pal\r
+ Pico.video.hint_irq = (PicoIn.AHW & PAHW_PICO ? 5 : 4);\r
\r
PsndReset(); // pal must be known here\r
\r
pv->pending_ints |= 0x10;
if (pv->reg[0] & 0x10) {
elprintf(EL_INTS, "hint: @ %06x [%u]", SekPc, SekCyclesDone());
- if (SekIrqLevel < 4)
- SekInterrupt(4);
+ if (SekIrqLevel < pv->hint_irq)
+ SekInterrupt(pv->hint_irq);
}
}
unsigned char debug_p; // ... parsed: PVD_*\r
unsigned char addr_u; // bit16 of .addr\r
unsigned char hint_cnt;\r
- unsigned char pad2;\r
+ unsigned char hint_irq; // irq# of HINT (4 on MD, 5 on Pico)\r
unsigned short hv_latch; // latched hvcounter value\r
signed int fifo_cnt; // pending xfers for blocking FIFO queue entries\r
signed int fifo_bgcnt; // pending xfers for background FIFO queue entries\r
if (pv->pending_ints & pv->reg[1] & 0x20) {\r
pv->pending_ints &= ~0x20;\r
pv->status &= ~SR_F;\r
- return (pv->reg[0] & pv->pending_ints & 0x10) >> 2;\r
+ if (pv->reg[0] & pv->pending_ints & 0x10)\r
+ return pv->hint_irq;\r
}\r
else if (pv->pending_ints & pv->reg[0] & 0x10)\r
pv->pending_ints &= ~0x10;\r
}\r
SATaddr = ((pvid->reg[5]&0x7f) << 9) | ((pvid->reg[6]&0x20) << 11);\r
SATmask = ~0x1ff;\r
- if (Pico.video.reg[12]&1)\r
+ if (pvid->reg[12]&1)\r
SATaddr &= ~0x200, SATmask &= ~0x200; // H40, zero lowest SAT bit\r
//elprintf(EL_STATUS, "spritep moved to %04x", SATaddr);\r
return;\r
lines = (pvid->reg[1] & 0x20) | (pvid->reg[0] & 0x10);\r
pints = pvid->pending_ints & lines;\r
if (pints & 0x20) irq = 6;\r
- else if (pints & 0x10) irq = 4;\r
- SekInterrupt(irq); // update line\r
+ else if (pints & 0x10) irq = pvid->hint_irq;\r
+ if (SekIrqLevel < irq)\r
+ SekInterrupt(irq); // update line\r
\r
// this is broken because cost of current insn isn't known here\r
if (irq) SekEndRun(21); // make it delayed\r