core z80, more timing fixes

diff --git a/pico/memory.c b/pico/memory.c
index fc7ad74..fc8e33d 100644 (file)
--- a/pico/memory.c
+++ b/pico/memory.c
@@ -521,7 +521,7 @@ void NOINLINE ctl_write_z80busreq(u32 d)
   {\r
     if (d)\r
     {\r
-      Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
+      Pico.t.z80c_cnt = z80_cycles_from_68k() + 1;\r
     }\r
     else\r
     {\r
@@ -553,7 +553,7 @@ void NOINLINE ctl_write_z80reset(u32 d)
     }\r
     else\r
     {\r
-      Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
+      Pico.t.z80c_cnt = z80_cycles_from_68k() + 1;\r
       z80_reset();\r
     }\r
     Pico.m.z80_reset = d;\r
@@ -680,7 +680,6 @@ static u32 PicoRead8_z80(u32 a)
     // open bus. Pulled down if MegaCD2 is attached.\r
     return (PicoIn.AHW & PAHW_MCD ? 0 : d);\r
   }\r
-  Pico.t.z80c_cnt += 3;\r
   SekCyclesBurnRun(1);\r
 \r
   if ((a & 0x4000) == 0x0000) {\r
@@ -705,7 +704,6 @@ static void PicoWrite8_z80(u32 a, u32 d)
     elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
     return;\r
   }\r
-  Pico.t.z80c_cnt += 3;\r
   SekCyclesBurnRun(1);\r
 \r
   if ((a & 0x4000) == 0x0000) { // z80 RAM\r
@@ -1359,7 +1357,7 @@ static void access_68k_bus(int delay) // bus delay as Q8
   z80_subCLeft((delay>>8) + (Pico.t.z80_busdelay>>8));\r
   // don't use SekCyclesBurn() here since the Z80 doesn't run in cycle lock to\r
   // the 68K. Count the stolen cycles to be accounted later in the 68k CPU runs\r
-  Pico.t.z80_buscycles += 7;\r
+  Pico.t.z80_buscycles += 8;\r
 }\r
 \r
 static unsigned char z80_md_vdp_read(unsigned short a)\r

diff --git a/pico/z80if.c b/pico/z80if.c
index 4df40da..6243675 100644 (file)
--- a/pico/z80if.c
+++ b/pico/z80if.c
@@ -112,12 +112,13 @@ void z80_reset(void)
   drZ80.Z80IF = 0;
   drZ80.z80irqvector = 0xff0000; // RST 38h
   drZ80.Z80PC_BASE = drZ80.Z80PC = z80_read_map[0] << 1;
-  // others not changed, undefined on cold boot
+  // other registers not changed, undefined on cold boot
 #ifdef FAST_Z80SP
   // drZ80 is locked in single bank
   drz80_sp_base = (PicoIn.AHW & PAHW_SMS) ? 0xc000 : 0x0000;
   drZ80.Z80SP_BASE = z80_read_map[drz80_sp_base >> Z80_MEM_SHIFT] << 1;
 #endif
+  drZ80.Z80SP = drZ80.Z80SP_BASE + 0xffff;
   drZ80.z80_irq_callback = NULL; // use auto-clear
   if (PicoIn.AHW & PAHW_SMS) {
     drZ80.Z80SP = drZ80.Z80SP_BASE + 0xdff0; // simulate BIOS
@@ -128,6 +129,7 @@ void z80_reset(void)
 #endif
 #ifdef _USE_CZ80
   Cz80_Reset(&CZ80);
+  Cz80_Set_Reg(&CZ80, CZ80_SP, 0xffff);
   if (PicoIn.AHW & PAHW_SMS)
     Cz80_Set_Reg(&CZ80, CZ80_SP, 0xdff0);
 #endif