0x82,0x83,0x83,0x84,0x85,0x85,0x86,0x87,0x87,0x88,0x89,0x8a,0x8a,0x8b,0x8c,0x8c,\r
};\r
\r
+// VDP transfer slots for blanked and active display in 32col and 40col mode.\r
+// 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40\r
+// In blanked display, all slots but 5(h32) / 6(h40) are usable for transfers,\r
+// in active display only 16(h32) / 18(h40) slots can be used.\r
+\r
+// XXX inactive tables by slot#=cycles*maxslot#/488. should be through hv tables\r
+// VDP transfer slots in inactive (blanked) display 32col mode.\r
+// refresh slots: 250, 26, 58, 90, 122 -> 32, 64, 96, 128, 160\r
+const unsigned char vdpcyc2sl_32_bl[] = { // 68k cycles/2 to slot #\r
+// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30\r
+ 0, 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10,\r
+ 10, 11, 12, 12, 13, 14, 14, 15, 16, 17, 17, 18, 19, 19, 20, 21,\r
+ 21, 22, 23, 23, 24, 25, 25, 26, 27, 27, 28, 29, 29, 30, 31, 31,\r
+ 32, 33, 34, 34, 35, 36, 36, 37, 38, 38, 39, 40, 40, 41, 42, 42,\r
+ 43, 44, 44, 45, 46, 46, 47, 48, 48, 49, 50, 51, 51, 52, 53, 53,\r
+ 54, 55, 55, 56, 57, 57, 58, 59, 59, 60, 61, 61, 62, 63, 63, 64,\r
+ 65, 65, 66, 67, 68, 68, 69, 70, 70, 71, 72, 72, 73, 74, 74, 75,\r
+ 76, 76, 77, 78, 78, 79, 80, 80, 81, 82, 83, 83, 84, 85, 85, 86,\r
+ 87, 87, 88, 89, 89, 90, 91, 91, 92, 93, 93, 94, 95, 95, 96, 97,\r
+ 97, 98, 99,100,100,101,102,102,103,104,104,105,106,106,107,108,\r
+ 108,109,110,110,111,112,112,113,114,114,115,116,117,117,118,119,\r
+ 119,120,121,121,122,123,123,124,125,125,126,127,127,128,129,129,\r
+ 130,131,131,132,133,134,134,135,136,136,137,138,138,139,140,140,\r
+ 141,142,142,143,144,144,145,146,146,147,148,148,149,150,151,151,\r
+ 152,153,153,154,155,155,156,157,157,158,159,159,160,161,161,162,\r
+ 163,163,164,165,166,166,167,168,168,169,170,170,171,172,172,173,\r
+};\r
+// VDP transfer slots in inactive (blanked) display 40col mode.\r
+// refresh slots: 250, 26, 58, 90, 122, 154 -> 40, 72, 104, 136, 168, 200\r
+const unsigned char vdpcyc2sl_40_bl[] = { // 68k cycles/2 to slot #\r
+// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30\r
+ 0, 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 9, 10, 10, 11, 12,\r
+ 13, 14, 15, 15, 16, 17, 18, 19, 20, 20, 21, 22, 23, 24, 25, 25,\r
+ 26, 27, 28, 29, 30, 30, 31, 32, 33, 34, 35, 35, 36, 37, 38, 39,\r
+ 40, 40, 41, 42, 43, 44, 45, 45, 46, 47, 48, 49, 50, 51, 51, 52,\r
+ 53, 54, 55, 56, 56, 57, 58, 59, 60, 61, 61, 62, 63, 64, 65, 66,\r
+ 66, 67, 68, 69, 70, 71, 71, 72, 73, 74, 75, 76, 76, 77, 78, 79,\r
+ 80, 81, 81, 82, 83, 84, 85, 86, 86, 87, 88, 89, 90, 91, 91, 92,\r
+ 93, 94, 95, 96, 96, 97, 98, 99,100,101,102,102,103,104,105,106,\r
+ 107,107,108,109,110,111,112,112,113,114,115,116,117,117,118,119,\r
+ 120,121,122,122,123,124,125,126,127,127,128,129,130,131,132,132,\r
+ 133,134,135,136,137,137,138,139,140,141,142,142,143,144,145,146,\r
+ 147,147,148,149,150,151,152,153,153,154,155,156,157,158,158,159,\r
+ 160,161,162,163,163,164,165,166,167,168,168,169,170,171,172,173,\r
+ 173,174,175,176,177,178,178,179,180,181,182,183,183,184,185,186,\r
+ 187,188,188,189,190,191,192,193,193,194,195,196,197,198,198,199,\r
+ 200,201,202,203,204,204,205,206,207,208,209,209,210,211,212,213,\r
+};\r
+// VDP transfer slots in active display 32col mode. Transfer slots (Hint=0):\r
+// 11,25,40,48,56,72,80,88,104,112,120,136,144,152,167,168\r
+const unsigned char vdpcyc2sl_32[] = { // 68k cycles/2 to slot #\r
+// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
+ 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,\r
+ 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5,\r
+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
+ 5, 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r
+ 6, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 8, 8, 8,\r
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,\r
+ 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10,\r
+ 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11,\r
+ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,\r
+ 11, 11, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13,\r
+ 13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, 14, 14,\r
+ 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 15,\r
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,\r
+};\r
+// VDP transfer slots in active display 40col mode. Transfer slots (Hint=0):\r
+// 21,47,55,63,79,87,95,111,119,127,143,151,159,175,183,191,206,207\r
+const unsigned char vdpcyc2sl_40[] = { // 68k cycles/2 to slot #\r
+// 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 0\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, // 32\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 64\r
+ 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, // 96\r
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, // 128\r
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, // 160\r
+ 5, 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 7, 7, // 192\r
+ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, // 224\r
+ 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, // 256\r
+ 9, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, // 288\r
+ 10, 10, 10, 10, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 12, // 320\r
+ 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13, 13, 13, 13, // 352\r
+ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 14, 14, 14, 14, 14, // 384\r
+ 14, 14, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 16, 16, 16, // 416\r
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 17, // 448\r
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, 18, // 480\r
+};\r
+\r
+// XXX inactive tables by cyc=slot#*488/maxslot#. should be through hv tables\r
+const unsigned short vdpsl2cyc_32_bl[] = { // slot # to 68k cycles/2\r
+ 0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23,\r
+ 24, 25, 27, 28, 30, 31, 33, 34, 36, 37, 39, 40, 42, 43, 45, 46,\r
+ 48, 49, 50, 52, 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70,\r
+ 71, 73, 74, 75, 77, 78, 80, 81, 83, 84, 86, 87, 89, 90, 92, 93,\r
+ 95, 96, 98, 99,100,102,103,105,106,108,109,111,112,114,115,117,\r
+ 118,120,121,122,124,125,127,128,130,131,133,134,136,137,139,140,\r
+ 142,143,145,146,147,149,150,152,153,155,156,158,159,161,162,164,\r
+ 165,167,168,170,171,172,174,175,177,178,180,181,183,184,186,187,\r
+ 189,190,192,193,195,196,197,199,200,202,203,205,206,208,209,211,\r
+ 212,214,215,217,218,220,221,222,224,225,227,228,230,231,233,234,\r
+ 236,237,239,240,242,243,244,246,\r
+};\r
+const unsigned short vdpsl2cyc_40_bl[] = { // slot # to 68k cycles/2\r
+ 0, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18,\r
+ 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 38,\r
+ 39, 40, 41, 42, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 56, 57,\r
+ 58, 59, 60, 61, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76,\r
+ 77, 78, 79, 81, 82, 83, 84, 85, 87, 88, 89, 90, 91, 93, 94, 95,\r
+ 96, 97, 99,100,101,102,103,105,106,107,108,109,111,112,113,114,\r
+ 115,117,118,119,120,121,122,124,125,126,127,128,130,131,132,133,\r
+ 134,136,137,138,139,140,142,143,144,145,146,148,149,150,151,152,\r
+ 154,155,156,157,158,160,161,162,163,164,166,167,168,169,170,172,\r
+ 173,174,175,176,178,179,180,181,182,183,185,186,187,188,189,191,\r
+ 192,193,194,195,197,198,199,200,201,203,204,205,206,207,209,210,\r
+ 211,212,213,215,216,217,218,219,221,222,223,224,225,227,228,229,\r
+ 230,231,233,234,235,236,237,239,240,241,242,243,244,246,\r
+};\r
+const unsigned short vdpsl2cyc_32[] = { // slot # to 68k cycles/2\r
+ 0, 16, 36, 56, 67, 79,102,113,125,148,159,171,194,205,217,239,\r
+ 240,260\r
+};\r
+const unsigned short vdpsl2cyc_40[] = { // slot # to 68k cycles/2\r
+ 0, 24, 55, 64, 73, 92,101,110,129,138,147,166,175,184,203,212,\r
+ 221,239,240,268\r
+};\r
+\r
#ifndef _ASM_MISC_C\r
PICO_INTERNAL_ASM void memcpy16bswap(unsigned short *dest, void *src, int count)\r
{\r
#define NEED_DMA_SOURCE\r
#include "memory.h"\r
\r
-extern const unsigned char hcounts_32[];\r
-extern const unsigned char hcounts_40[];\r
+extern const unsigned char hcounts_32[], hcounts_40[];\r
+extern const unsigned char vdpcyc2sl_32_bl[], vdpcyc2sl_40_bl[];\r
+extern const unsigned char vdpcyc2sl_32[], vdpcyc2sl_40[];\r
+extern const unsigned short vdpsl2cyc_32_bl[], vdpsl2cyc_40_bl[];\r
+extern const unsigned short vdpsl2cyc_32[], vdpsl2cyc_40[];\r
\r
static int blankline; // display disabled for this line\r
static unsigned sat; // VRAM addr of sprite attribute table\r
* FIFORead executes a 68k read. 68k is blocked until the next transfer slot.\r
*/\r
\r
-// FIFO transfer slots per line: [active][h40]\r
-static const short vdpslots[2][2] = {{ 166, 204 },{ 16, 18 }};\r
-// mapping between slot# and 68k cycles in a blanked scanline [H32, H40]\r
-static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488 };\r
-static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204 };\r
-\r
-// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538\r
-// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:\r
-// (HINT=slot 0): 11,25,40,48,56,72,80,88,104,112,120,136,144,152,167,168\r
-static const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 to slot #\r
-// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
- 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,\r
- 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3,\r
- 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r
- 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 8, 8,\r
- 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9,10,\r
-10,10,10,10,10,11,11,11,11,11,11,11,11,11,11,11,\r
-11,12,12,12,12,12,13,13,13,13,13,13,14,14,14,14,\r
-14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,16,\r
-};\r
-static const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4\r
- 0, 8, 18, 28, 33, 39, 51, 56, 62, 74, 79, 85, 97,102,108,119,120,130\r
-};\r
-\r
-// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238\r
-// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:\r
-// (HINT=0): 21,47,55,63,79,87,95,111,119,127,143,151,159,175,183,191,206,207,\r
-static const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 to slot #\r
-// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,\r
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2,\r
- 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5,\r
- 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r
- 8, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,10,10,10,\r
-10,10,10,11,11,11,11,12,12,12,12,12,13,13,13,13,\r
-13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,16,\r
-16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,18,\r
-};\r
-static const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4\r
- 0, 12, 27, 32, 36, 46, 50, 55, 64, 69, 73, 83, 87, 92,101,106,111,119,120,134\r
-};\r
-\r
// NB code assumes fifo_* arrays have size 2^n\r
// last transferred FIFO data, ...x = index XXX currently only CPU\r
static short fifo_data[4], fifo_dx; // XXX must go into save?\r
static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)\r
\r
static unsigned short fifo_slot; // last executed slot in current scanline\r
+static unsigned short fifo_maxslot;// #slots in scanline\r
\r
-// map cycles to FIFO slot\r
-static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)\r
-{\r
- int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
- int h40 = pv->reg[12] & 1;\r
-\r
- if (active) return (h40 ? vdpcyc2sl_40 : vdpcyc2sl_32)[cycles/4];\r
- else return (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;\r
-}\r
-\r
-static __inline int GetMaxFIFOSlot(struct PicoVideo *pv)\r
-{\r
- int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
- int h40 = pv->reg[12] & 1;\r
-\r
- return vdpslots[active][h40];\r
-}\r
-\r
-// map FIFO slot to cycles\r
-static __inline int GetFIFOCycles(struct PicoVideo *pv, int slot)\r
-{\r
- int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
- int h40 = pv->reg[12] & 1;\r
-\r
- if (active) return (h40 ? vdpsl2cyc_40 : vdpsl2cyc_32)[slot]*4;\r
- else return ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);\r
-}\r
+static const unsigned char *fifo_cyc2sl;\r
+static const unsigned short *fifo_sl2cyc;\r
\r
// do the FIFO math\r
static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)\r
\r
// if entry has been processed...\r
if (pv->fifo_cnt == 0) {\r
- if (fifo_ql) {\r
- // terminate DMA if applicable\r
- if ((pv->status & SR_DMA) && (fifo_queue[fifo_qx] & FQ_BGDMA)) {\r
- pv->status &= ~SR_DMA;\r
- pv->command &= ~0x80;\r
- }\r
- // remove entry from FIFO\r
+ // remove entry from FIFO\r
+ if (fifo_ql)\r
fifo_qx ++, fifo_qx &= 7, fifo_ql --;\r
- }\r
// start processing for next entry if there is one\r
if (fifo_ql)\r
pv->fifo_cnt = (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);\r
- else\r
+ else { // FIFO empty\r
+ pv->status &= ~PVS_FIFORUN;\r
fifo_total = 0;\r
+ }\r
}\r
return l;\r
}\r
static __inline void SetFIFOState(struct PicoVideo *pv)\r
{\r
// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
- if (fifo_total == 0)\r
- pv->status &= ~PVS_CPURD;\r
if (fifo_total <= 4) {\r
- int x = (fifo_qx + fifo_ql - 1) & 7;\r
- if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL) &&\r
- (!fifo_ql || !(fifo_queue[x] & FQ_BGDMA))) {\r
+ pv->status &= ~PVS_CPUWR;\r
+ if (!(pv->status & (PVS_DMABG|PVS_DMAFILL))) {\r
pv->status &= ~SR_DMA;\r
pv->command &= ~0x80;\r
}\r
- pv->status &= ~PVS_CPUWR;\r
+ }\r
+ if (fifo_total == 0) {\r
+ pv->status &= ~PVS_CPURD;\r
+ // terminate DMA if applicable\r
+ if (!(pv->status & (PVS_FIFORUN|PVS_DMAFILL))) {\r
+ pv->status &= ~(SR_DMA|PVS_DMABG);\r
+ pv->command &= ~0x80;\r
+ }\r
}\r
}\r
\r
int slots, done;\r
\r
// calculate #slots since last executed slot\r
- slots = GetFIFOSlot(pv, cycles) - fifo_slot;\r
+ slots = fifo_cyc2sl[cycles>>1] - fifo_slot;\r
\r
// advance FIFO queue by #done slots\r
done = slots;\r
int PicoVideoFIFODrain(int level, int cycles, int bgdma)\r
{\r
struct PicoVideo *pv = &Pico.video;\r
- int maxsl = GetMaxFIFOSlot(pv); // max xfer slots in this scanline\r
+ unsigned ocyc = cycles;\r
int burn = 0;\r
\r
// process FIFO entries until low level is reached\r
- while (fifo_total > level && fifo_slot < maxsl &&\r
+ while (fifo_total > level && fifo_slot < fifo_maxslot &&\r
(!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {\r
int b = fifo_queue[fifo_qx] & FQ_BYTE;\r
int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);\r
- int last = fifo_slot;\r
- int slot = (pv->fifo_cnt < cnt ? pv->fifo_cnt : cnt) + last; // target slot\r
- unsigned ocyc = cycles;\r
+ int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + fifo_slot; // target slot\r
\r
- if (slot > maxsl) {\r
+ if (slot > fifo_maxslot) {\r
// target in later scanline, advance to eol\r
- slot = maxsl;\r
+ slot = fifo_maxslot;\r
cycles = 488;\r
} else {\r
// advance FIFO to target slot and CPU to cycles at that slot\r
- cycles = GetFIFOCycles(pv, slot);\r
+ cycles = fifo_sl2cyc[slot]<<1;\r
}\r
+ AdvanceFIFOEntry(pv, slot - fifo_slot);\r
fifo_slot = slot;\r
- burn += cycles - ocyc;\r
-\r
- AdvanceFIFOEntry(pv, slot - last);\r
}\r
+ burn = cycles - ocyc;\r
\r
SetFIFOState(pv);\r
\r
int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
int burn = 0;\r
\r
- PicoVideoFIFOSync(lc);\r
+ if (pv->fifo_cnt) {\r
+ PicoVideoFIFOSync(lc);\r
+ // advance FIFO and CPU until FIFO is empty\r
+ burn = PicoVideoFIFODrain(0, lc, 1);\r
+ lc += burn;\r
+ }\r
\r
- // advance FIFO and CPU until FIFO is empty\r
- burn = PicoVideoFIFODrain(0, lc, 1);\r
- lc += burn;\r
if (fifo_total > 0)\r
pv->status |= PVS_CPURD; // target slot is in later scanline\r
else {\r
// use next VDP access slot for reading, block 68k until then\r
- fifo_slot = GetFIFOSlot(pv, lc) + 1;\r
- burn += GetFIFOCycles(pv, fifo_slot) - lc;\r
+ fifo_slot = fifo_cyc2sl[lc>>1] + 1;\r
+ burn += (fifo_sl2cyc[fifo_slot]<<1) - lc;\r
}\r
\r
return burn;\r
{\r
struct PicoVideo *pv = &Pico.video;\r
int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
- int burn = 0, x;\r
+ int burn = 0, x, head = 0;\r
\r
- PicoVideoFIFOSync(lc);\r
+ if (pv->fifo_cnt)\r
+ PicoVideoFIFOSync(lc);\r
pv->status = (pv->status & ~sr_mask) | sr_flags;\r
\r
if (count && fifo_ql < 8) {\r
// update FIFO state if it was empty\r
if (fifo_ql == 0) {\r
- fifo_slot = GetFIFOSlot(pv, lc+9); // FIFO latency ~3 vdp slots\r
+ fifo_slot = fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots\r
pv->fifo_cnt = count << (flags & FQ_BYTE);\r
+ pv->status |= PVS_FIFORUN;\r
}\r
\r
- // create xfer queue entry\r
+ // determine queue position for entry\r
x = (fifo_qx + fifo_ql - 1) & 7;\r
if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {\r
// CPU FIFO writes have priority over a background DMA Fill/Copy\r
fifo_queue[(x+1) & 7] = fifo_queue[x];\r
- if (fifo_ql == 1) {\r
+ if (x == fifo_qx) { // overtaking to queue head?\r
// XXX if interrupting a DMA fill, fill data changes\r
int f = fifo_queue[x] & 7;\r
fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
pv->fifo_cnt = count << (flags & FQ_BYTE);\r
+ head = 1;\r
}\r
x = (x-1) & 7;\r
}\r
- if (fifo_ql && (fifo_queue[x] & 7) == flags) {\r
+\r
+ // create xfer queue entry\r
+ if (fifo_ql && !head && (fifo_queue[x] & 7) == flags) {\r
// amalgamate entries if of same type\r
fifo_queue[x] += (count << 3);\r
- if (fifo_ql == 1) pv->fifo_cnt += count << (flags & FQ_BYTE);\r
+ if (x == fifo_qx) // modifiying fifo head, adjust count\r
+ pv->fifo_cnt += count << (flags & FQ_BYTE);\r
} else {\r
fifo_ql ++;\r
x = (x+1) & 7;\r
}\r
\r
// switch FIFO mode between active/inactive display\r
-static void PicoVideoFIFOMode(int active)\r
+void PicoVideoFIFOMode(int active, int h40)\r
{\r
+ static const unsigned char *vdpcyc2sl[2][2] =\r
+ { {vdpcyc2sl_32_bl, vdpcyc2sl_40_bl} , {vdpcyc2sl_32, vdpcyc2sl_40} };\r
+ static const unsigned short *vdpsl2cyc[2][2] =\r
+ { {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };\r
+\r
struct PicoVideo *pv = &Pico.video;\r
- int h40 = pv->reg[12] & 1;\r
int lc = SekCyclesDone() - Pico.t.m68c_line_start;\r
+ active = active && !(pv->status & PVS_VB2);\r
\r
- PicoVideoFIFOSync(lc);\r
+ if (fifo_maxslot)\r
+ PicoVideoFIFOSync(lc);\r
\r
- if (fifo_ql) {\r
- // recalculate FIFO slot for new mode\r
- if (!(pv->status & SR_VB) && active)\r
- fifo_slot = (pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32)[lc/4];\r
- else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);\r
- }\r
+ fifo_cyc2sl = vdpcyc2sl[active][h40];\r
+ fifo_sl2cyc = vdpsl2cyc[active][h40];\r
+ // recalculate FIFO slot for new mode\r
+ fifo_slot = fifo_cyc2sl[lc>>1]-1;\r
+ fifo_maxslot = fifo_cyc2sl[488>>1];\r
}\r
\r
\r
SekCyclesDone(), SekPc);\r
\r
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (Pico.video.type == 1),\r
- 0, SR_DMA| PVS_CPUWR));\r
+ PVS_DMABG, SR_DMA | PVS_CPUWR));\r
\r
if ((source & 0xe00000) == 0xe00000) { // Ram\r
base = (u16 *)PicoMem.ram;\r
int source;\r
elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());\r
\r
+ // XXX implement VRAM 128k? Is this even working? xfer/count still FQ_BYTE?\r
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | FQ_BYTE,\r
- PVS_CPUWR, SR_DMA));\r
+ PVS_CPUWR, SR_DMA | PVS_DMABG));\r
\r
source =Pico.video.reg[0x15];\r
source|=Pico.video.reg[0x16]<<8;\r
\r
- // XXX implement VRAM 128k? Is this even working? count still in bytes?\r
for (; len; len--)\r
{\r
vr[(u16)a] = vr[(u16)(source++)];\r
elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());\r
\r
SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_BGDMA | (Pico.video.type == 1),\r
- PVS_CPUWR | PVS_DMAFILL, SR_DMA));\r
+ PVS_CPUWR | PVS_DMAFILL, SR_DMA | PVS_DMABG));\r
\r
switch (Pico.video.type)\r
{\r
if (num == 0 && !(pvid->reg[0]&2) && (d&2))\r
pvid->hv_latch = PicoVideoRead(0x08);\r
if (num == 1 && ((pvid->reg[1]^d)&0x40)) {\r
- PicoVideoFIFOMode(d & 0x40);\r
+ PicoVideoFIFOMode(d & 0x40, pvid->reg[12]&1);\r
// handle line blanking before line rendering\r
if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)\r
blankline = d&0x40 ? -1 : Pico.m.scanline;\r
}\r
+ if (num == 12 && ((pvid->reg[12]^d)&0x01))\r
+ PicoVideoFIFOMode(pvid->reg[1]&0x40, d & 1);\r
DrawSync(SekCyclesDone() - Pico.t.m68c_line_start <= 488-390);\r
pvid->reg[num]=(unsigned char)d;\r
switch (num)\r
\r
// convert former dma_xfers (why was this in PicoMisc anyway?)\r
if (Pico.m.dma_xfers) {\r
+ pv->status = SR_DMA|PVS_FIFORUN;\r
pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);\r
fifo_total = Pico.m.dma_xfers;\r
Pico.m.dma_xfers = 0;\r
notaz.gp2x.de / picodrive.git / commitdiff