Pico.t.z80_busdelay &= 0xff; // leftover cycle fraction\r
// don't use SekCyclesBurn() here since the Z80 doesn't run in cycle lock to\r
// the 68K. Count the stolen cycles to be accounted later in the 68k CPU runs\r
- Pico.t.z80_buscycles += 8;\r
+ Pico.t.z80_buscycles += 8; // TODO <=8.4 for Rick 2, but >=8.9 for misc_test\r
}\r
\r
static unsigned char z80_md_vdp_read(unsigned short a)\r
Pico.t.vcnt_wrap = 0xEB;\r
Pico.t.vcnt_adj = 6;\r
}\r
+ PicoVideoFIFOMode(Pico.video.reg[1]&0x40, Pico.video.reg[12]&1);\r
\r
Pico.m.dirtyPal = 1;\r
rendstatus_old = -1;\r
*(u32 *)(cpu+0x50) = SekCycleCntS68k;\r
*(s16 *)(cpu+0x4e) = SekCycleCntS68k - SekCycleAimS68k;\r
} else {\r
- *(u32 *)(cpu+0x50) = Pico.t.m68c_cnt;\r
+ *(u32 *)(cpu+0x50) = Pico.t.m68c_cnt + Pico.t.z80_buscycles +\r
+ ((Pico.t.refresh_delay + (1<<14)/2) >> 14);\r
*(s16 *)(cpu+0x4e) = Pico.t.m68c_cnt - Pico.t.m68c_aim;\r
}\r
}\r
} else {\r
Pico.t.m68c_cnt = *(u32 *)(cpu+0x50);\r
Pico.t.m68c_aim = Pico.t.m68c_cnt - *(s16 *)(cpu+0x4e);\r
+ Pico.t.z80_buscycles = 0;\r
+ Pico.t.refresh_delay = 0;\r
}\r
}\r
\r
unsigned short vram[0x8000];\r
unsigned short cram[0x40];\r
unsigned short vsram[0x40];\r
- unsigned int satcache[0x80];\r
+ unsigned int satcache[2*0x80];\r
\r
//struct PicoMisc m;\r
struct PicoVideo video;\r
\r
if (vf->fifo_maxslot)\r
PicoVideoFIFOSync(lc);\r
+ else\r
+ lc = 0;\r
\r
vf->fifo_cyc2sl = vdpcyc2sl[active][h40];\r
vf->fifo_sl2cyc = vdpsl2cyc[active][h40];\r
vf->fifo_ql = vf->fifo_qx = vf->fifo_total = 0;\r
if (pv->fifo_cnt) {\r
int wc = pv->fifo_cnt;\r
- pv->status |= PVS_CPUWR;\r
vf->fifo_total = (wc+b) >> b;\r
vf->fifo_queue[vf->fifo_qx + vf->fifo_ql] = (wc << 3) | b | FQ_FGDMA;\r
vf->fifo_ql ++;\r
+ if (vf->fifo_total > 4 && !(pv->status & (PVS_CPUWR|PVS_CPURD)))\r
+ pv->status |= PVS_CPUWR;\r
}\r
if (pv->fifo_bgcnt) {\r
int wc = pv->fifo_bgcnt;\r
vf->fifo_queue[vf->fifo_qx + vf->fifo_ql] = (wc << 3) | FQ_BGDMA;\r
vf->fifo_ql ++;\r
}\r
- if (vf->fifo_ql)\r
- pv->status |= SR_DMA;\r
PicoVideoCacheSAT(1);\r
+ vf->fifo_maxslot = 0;\r
}\r
// vim:shiftwidth=2:ts=2:expandtab\r
struct z80_state *s = data;
memset(data, 0, Z80_STATE_SIZE);
memcpy(s->magic, "Z80a", 4);
- s->cyc = Pico.t.z80c_cnt;
+ s->cyc = Pico.t.z80c_cnt + ((Pico.t.z80_busdelay + (1<<8)/2) >> 8);
#if defined(_USE_DRZ80)
#define DRR8(n) (drZ80.Z80##n >> 24)
#define DRR16(n) (drZ80.Z80##n >> 16)
return 0;
}
Pico.t.z80c_cnt = s->cyc;
+ Pico.t.z80_busdelay = 0;
#if defined(_USE_DRZ80)
#define DRW8(n, v) drZ80.Z80##n = (u32)(v) << 24