dbra tracking and branch improvements

diff --git a/Cyclone.h b/Cyclone.h
index c2c27d8..1933a46 100644 (file)
--- a/Cyclone.h
+++ b/Cyclone.h
@@ -25,7 +25,7 @@ struct Cyclone
   unsigned int a[8];    // [r7,#0x20]\r
   unsigned int pc;      // [r7,#0x40] Memory Base (.membase) + 68k PC\r
   unsigned char srh;    // [r7,#0x44] Status Register high (T_S__III)\r
-  unsigned char unused; // [r7,#0x45] Unused\r
+  unsigned char not_pol;// [r7,#0x45] not polling\r
   unsigned char flags;  // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
   unsigned char irq;    // [r7,#0x47] IRQ level\r
   unsigned int osp;     // [r7,#0x48] Other Stack Pointer (USP/SSP)\r

diff --git a/Main.cpp b/Main.cpp
index 1637047..9ef8a2b 100644 (file)
--- a/Main.cpp
+++ b/Main.cpp
@@ -25,8 +25,8 @@ int arm_op_count;
 \r
 // opcodes often used by games\r
 static const unsigned short hot_opcodes[] = {\r
-  0x6701, // beq     $3\r
-  0x6601, // bne     $3\r
+  0x6702, // beq     $3\r
+  0x6602, // bne     $3\r
   0x51c8, // dbra    Dn, $2\r
   0x4a38, // tst.b   $0.w\r
   0xd040, // add.w   Dn, Dn\r
@@ -34,7 +34,7 @@ static const unsigned short hot_opcodes[] = {
   0x0240, // andi.w  #$0, D0\r
   0x2038, // move.l  $0.w, D0\r
   0xb0b8, // cmp.l   $0.w, D0\r
-  0x6001, // bra     $3\r
+  0x6002, // bra     $3\r
   0x30c0, // move.w  D0, (A0)+\r
   0x3028, // move.w  ($0,A0), D0\r
   0x0c40, // cmpi.w  #$0, D0\r
@@ -52,7 +52,7 @@ static const unsigned short hot_opcodes[] = {
   0xb038, // cmp.b   $0.w, D0\r
   0x3039, // move.w  $0.l, D0\r
   0x4840, // swap    D0\r
-  0x6101, // bsr     $3\r
+  0x6102, // bsr     $3\r
   0x6100, // bsr     $2\r
   0x5e40, // addq.w  #7, D0\r
   0x1039, // move.b  $0.l, D0\r
@@ -64,10 +64,10 @@ static const unsigned short hot_opcodes[] = {
   0xc040, // and.w   D0, D0\r
   0x3180, // move.w  D0, (A0,D0.w)\r
   0x1198, // move.b  (A0)+, (A0,D0.w)\r
-  0x6501, // bcs     $3\r
+  0x6502, // bcs     $3\r
   0x6500, // bcs     $2\r
-  0x6401, // bcc     $3\r
-  0x6a01, // bpl     $3\r
+  0x6402, // bcc     $3\r
+  0x6a02, // bpl     $3\r
   0x41f0, // lea     (A0,D0.w), A0\r
   0x4a28, // tst.b   ($0,A0)\r
   0x0828, // btst    #$0, ($0,A0)\r
@@ -1267,9 +1267,9 @@ static int CycloneMake()
   ot("  %s CycloneDoTrace\n",globl);\r
   ot("  %s CycloneJumpTab\n",globl);\r
   ot("  %s Op____\n",globl);\r
-  ot("  %s Op6001\n",globl);\r
-  ot("  %s Op6601\n",globl);\r
-  ot("  %s Op6701\n",globl);\r
+  ot("  %s Op6002\n",globl);\r
+  ot("  %s Op6602\n",globl);\r
+  ot("  %s Op6702\n",globl);\r
 #endif\r
   ot("\n");\r
   ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r

diff --git a/OpBranch.cpp b/OpBranch.cpp
index c37620a..fb4f561 100644 (file)
--- a/OpBranch.cpp
+++ b/OpBranch.cpp
@@ -348,6 +348,7 @@ int OpDbra(int op)
     ot("  and r1,r8,#0x0007\n");\r
     ot("  mov r1,r1,lsl #2\n");\r
     ot("  ldrsh r0,[r7,r1]\n");\r
+    ot("  strb r8,[r7,#0x45] ;@ not polling\n");\r
     ot("  sub r0,r0,#1\n");\r
     ot("  strh r0,[r7,r1]\n");\r
     ot("\n");\r
@@ -418,6 +419,7 @@ int OpBranch(int op)
   int offset=0;\r
   int cc=0;\r
   const char *asr_r11="";\r
+  int pc_reg=0;\r
 \r
   offset=(char)(op&0xff);\r
   cc=(op>>8)&15;\r
@@ -428,7 +430,7 @@ int OpBranch(int op)
 \r
   if (size==2) size=0; // 000 model does not support long displacement\r
   if (size) use=op; // 16-bit or 32-bit\r
-  else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
+  else use=(op&0xff01)+2; // Use same opcode for all 8-bit branches\r
 \r
   if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
   OpStart(op,size?0x10:0);\r
@@ -491,8 +493,6 @@ int OpBranch(int op)
     Cycles=18; // always 18\r
   }\r
 \r
-  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
-\r
 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
   if (offset!=0 && offset!=-1) checkpc=1;\r
 #endif\r
@@ -502,20 +502,48 @@ int OpBranch(int op)
 #if USE_CHECKPC_CALLBACK\r
   if (offset==-1) checkpc=1;\r
 #endif\r
-  if (checkpc) CheckPc();\r
+  if (checkpc)\r
+  {\r
+    ot("  add r0,r4,r11%s ;@ New PC\n",asr_r11);\r
+    CheckPc();\r
+    pc_reg=0;\r
+  }\r
+  else\r
+  {\r
+    ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+    pc_reg=4;\r
+  }\r
+\r
+  if ((op & 1) || size != 0)\r
+  {\r
 #if EMULATE_ADDRESS_ERRORS_JUMP\r
-  ot("  mov r4,r0\n");\r
-  ot("  tst r4,#1 ;@ address error?\n");\r
-  ot("  bne ExceptionAddressError_r_prg_r4\n");\r
+    if (pc_reg!=4)\r
+    {\r
+      ot("  mov r4,r%d\n",pc_reg);\r
+      pc_reg=4;\r
+    }\r
+    if (size)\r
+    {\r
+      ot("  tst r4,#1 ;@ address error?\n");\r
+      ot("  bne ExceptionAddressError_r_prg_r4\n");\r
+    }\r
+    else\r
+    {\r
+      ot("  b ExceptionAddressError_r_prg_r4\n");\r
+    }\r
 #else\r
-  ot("  bic r4,r0,#1\n");\r
+    ot("  bic r4,r%d,#1\n",pc_reg);\r
+    pc_reg=4;\r
 #endif\r
+  }\r
+  if (pc_reg!=4)\r
+    ot("  mov r4,r%d\n",pc_reg);\r
   ot("\n");\r
 \r
   OpEnd(size?0x10:0);\r
 \r
   // since all "DontBranch" code is same for every size, output only once\r
-  if (cc>=2&&(op&0xff00)==0x6700)\r
+  if (cc>=2&&(op&0xff01)==0x6700)\r
   {\r
     ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
     if (size) ot("  add r4,r4,#%d\n",1<<size);\r

diff --git a/tools/idle.s b/tools/idle.s
index 279079b..e970d2e 100644 (file)
--- a/tools/idle.s
+++ b/tools/idle.s
@@ -14,16 +14,16 @@ have_patches:
 .equ patch_desc_table_size, 10
 
 patch_desc_table:
-  .word (0x71fa<<16) | 0x66fa, idle_detector_bcc8, idle_bne, Op6601  @ bne.s
-  .word (0x71f8<<16) | 0x66f8, idle_detector_bcc8, idle_bne, Op6601  @ bne.s
-  .word (0x71f6<<16) | 0x66f6, idle_detector_bcc8, idle_bne, Op6601  @ bne.s
-  .word (0x71f2<<16) | 0x66f2, idle_detector_bcc8, idle_bne, Op6601  @ bne.s
-  .word (0x75fa<<16) | 0x67fa, idle_detector_bcc8, idle_beq, Op6701  @ beq.s
-  .word (0x75f8<<16) | 0x67f8, idle_detector_bcc8, idle_beq, Op6701  @ beq.s
-  .word (0x75f6<<16) | 0x67f6, idle_detector_bcc8, idle_beq, Op6701  @ beq.s
-  .word (0x75f2<<16) | 0x67f2, idle_detector_bcc8, idle_beq, Op6701  @ beq.s
-  .word (0x7dfe<<16) | 0x60fe, idle_detector_bcc8, idle_bra, Op6001  @ bra.s
-  .word (0x7dfc<<16) | 0x60fc, idle_detector_bcc8, idle_bra, Op6001  @ bra.s
+  .word (0x71fa<<16) | 0x66fa, idle_detector_bcc8, idle_bne, Op6602  @ bne.s
+  .word (0x71f8<<16) | 0x66f8, idle_detector_bcc8, idle_bne, Op6602  @ bne.s
+  .word (0x71f6<<16) | 0x66f6, idle_detector_bcc8, idle_bne, Op6602  @ bne.s
+  .word (0x71f2<<16) | 0x66f2, idle_detector_bcc8, idle_bne, Op6602  @ bne.s
+  .word (0x75fa<<16) | 0x67fa, idle_detector_bcc8, idle_beq, Op6702  @ beq.s
+  .word (0x75f8<<16) | 0x67f8, idle_detector_bcc8, idle_beq, Op6702  @ beq.s
+  .word (0x75f6<<16) | 0x67f6, idle_detector_bcc8, idle_beq, Op6702  @ beq.s
+  .word (0x75f2<<16) | 0x67f2, idle_detector_bcc8, idle_beq, Op6702  @ beq.s
+  .word (0x7dfe<<16) | 0x60fe, idle_detector_bcc8, idle_bra, Op6002  @ bra.s
+  .word (0x7dfc<<16) | 0x60fc, idle_detector_bcc8, idle_bra, Op6002  @ bra.s
 
 
 .text
@@ -101,19 +101,19 @@ cfi_loop:
 idle_bra:
     mov     r5, #2
     inc_counter
-    b       Op6001
+    b       Op6002
 
 idle_bne:
     msr     cpsr_flg, r10
     movne   r5, #2                @ 2 is intentional due to strange timing issues
     inc_counter ne
-    b       Op6601
+    b       Op6602
 
 idle_beq:
     msr     cpsr_flg, r10 ;@ ARM flags = 68000 flags
     moveq   r5, #2
     inc_counter eq
-    b       Op6701
+    b       Op6702
 
 
 @ @@@ @
@@ -156,9 +156,9 @@ idle_detector_bcc8:
     @ remove detector from Cyclone
     mov     r0, r8, lsr #8
     cmp     r0, #0x66
-    ldrlt   r1, =Op6001
-    ldreq   r1, =Op6601
-    ldrgt   r1, =Op6701
+    ldrlt   r1, =Op6002
+    ldreq   r1, =Op6602
+    ldrgt   r1, =Op6702
 
     ldr     r3, =CycloneJumpTab
     str     r1, [r3, r8, lsl #2]
@@ -167,7 +167,7 @@ idle_detector_bcc8:
 exit_detector:
     mov     r0, r8, lsr #8
     cmp     r0, #0x66
-    blt     Op6001
-    beq     Op6601
-    b       Op6701
+    blt     Op6002
+    beq     Op6602
+    b       Op6702