// my MD1 VA6 console has this in IO\r
PicoMem.ioports[1] = PicoMem.ioports[2] = PicoMem.ioports[3] = 0xff;\r
\r
+ // powerup default VDP register values from TMSS BIOS\r
+ Pico.video.reg[0] = Pico.video.reg[1] = 0x04;\r
+ Pico.video.reg[0xc] = 0x81;\r
+ Pico.video.reg[0xf] = 0x02;\r
+ SATaddr = 0x0000;\r
+ SATmask = ~0x3ff;\r
+\r
+ Pico.video.hint_irq = (PicoIn.AHW & PAHW_PICO ? 5 : 4);\r
+\r
if (PicoIn.AHW & PAHW_MCD)\r
PicoPowerMCD();\r
\r
case 0x0c:\r
// renderers should update their palettes if sh/hi mode is changed\r
if ((d^dold)&8) Pico.m.dirtyPal = 1;\r
+ if ((d^dold)&1) Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
break;\r
default:\r
return;\r
\r
void PicoVideoReset(void)\r
{\r
- Pico.video.hint_irq = (PicoIn.AHW & PAHW_PICO ? 5 : 4);\r
Pico.video.pending_ints=0;\r
+ Pico.video.reg[1] &= ~0x40; // TODO verify display disabled after reset\r
+ Pico.video.reg[10] = 0xff; // HINT is turned off after reset\r
+ Pico.video.status = 0x3428 | Pico.m.pal; // 'always set' bits | vblank | collision | pal\r
\r
- // default VDP register values (based on Fusion)\r
- Pico.video.reg[0] = Pico.video.reg[1] = 0x04;\r
- Pico.video.reg[0xc] = 0x81;\r
- Pico.video.reg[0xf] = 0x02;\r
- SATaddr = 0x0000;\r
- SATmask = ~0x1ff;\r
-\r
- memset(VdpSATCache, 0, sizeof(VdpSATCache));\r
memset(&VdpFIFO, 0, sizeof(VdpFIFO));\r
Pico.m.dirtyPal = 1;\r
\r
- Pico.video.status = 0x3428 | Pico.m.pal; // 'always set' bits | vblank | collision | pal\r
-\r
PicoDrawBgcDMA(NULL, 0, 0, 0, 0);\r
PicoVideoFIFOMode(0, 1);\r
}\r