int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2)
{
int ret = 0;
+ unsigned int mult_m68k_to_sh2 = sh2->mult_m68k_to_sh2;
+ unsigned int mult_sh2_to_m68k = sh2->mult_sh2_to_m68k;
- memset(sh2, 0, offsetof(SH2, mult_m68k_to_sh2));
+ memset(sh2, 0, sizeof(*sh2));
sh2->is_slave = is_slave;
sh2->other_sh2 = other_sh2;
+ sh2->mult_m68k_to_sh2 = mult_m68k_to_sh2;
+ sh2->mult_sh2_to_m68k = mult_sh2_to_m68k;
+
pdb_register_cpu(sh2, PDBCT_SH2, is_slave ? "ssh2" : "msh2");
#ifdef DRC_SH2
ret = sh2_drc_init(sh2);
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
- PREG8(msh2.peri_regs, 4) =
- PREG8(ssh2.peri_regs, 4) = 0x84; // SCI SSR
-
rendstatus_old = -1;
emu_32x_startup();
sh2_reset(&msh2);
sh2_reset(&ssh2);
+ sh2_peripheral_reset(&msh2);
+ sh2_peripheral_reset(&ssh2);
// if we don't have BIOS set, perform it's work here.
// MSH2
}
}
+void sh2_peripheral_reset(SH2 *sh2)
+{
+ memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
+ PREG8(sh2->peri_regs, 4) = 0x84; // SCI SSR
+}
+
// ------------------------------------------------------------------
// SH2 internal peripheral memhandlers
// we keep them in little endian format
void p32x_dreq1_trigger(void);\r
void p32x_timers_recalc(void);\r
void p32x_timers_do(unsigned int m68k_slice);\r
+void sh2_peripheral_reset(SH2 *sh2);\r
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r