void PicoFrame32x(void)
{
+ pwm_frame_smp_cnt = 0;
+
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
- if ((Pico32x.vdp_regs[0] & 3 ) != 0) // no forced blanking
- Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no pal access
+ if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
+ Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
p32x_poll_event(1);
PicoFrameStart();
PicoFrameHints();
}
+
Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
if (dmac0->tcr0 == 0)
dmac0->chcr0 |= 2; // DMA has ended normally
- p32x_poll_undetect(&m68k_poll, 0);
}
// ------------------------------------------------------------------
if ((a & 0x30) == 0x20)
return sh2_comm_faker(a);
#else
- if (p32x_poll_detect(&m68k_poll, a, SekPc, 0)) {
+ if ((a & 0x30) == 0x20 && p32x_poll_detect(&m68k_poll, a, SekPc, 0)) {
SekEndRun(16);
}
#endif
if (a == 0x24 || a == 0x26)
return sh2_comm_faker(a);
#endif
+ if ((a & 0x30) == 0x30)
+ return p32x_pwm_read16(a);
return Pico32x.regs[a / 2];
}
u16 *r = Pico32x.regs;
a &= 0x3e;
- // for write loops with FIFO checks..
- m68k_poll.cnt = 0;
-
switch (a) {
case 0x00: // adapter ctl
r[0] = (r[0] & 0x83) | (d & P32XS_FM);
SekEndRun(16);
return;
}
+ // PWM
+ else if ((a & 0x30) == 0x30) {
+ p32x_pwm_write16(a, d);
+ return;
+ }
p32x_reg_write8(a + 1, d);
}
return r[a / 2];
}
- // DREQ src, dst; comm port
- if ((a & 0x38) == 0x08 || (a & 0x30) == 0x20)
+ // DREQ src, dst
+ if ((a & 0x38) == 0x08)
return r[a / 2];
+ // comm port
+ if ((a & 0x30) == 0x20) {
+ if (p32x_poll_detect(&sh2_poll[cpuid], a, sh2_pc(cpuid), 0))
+ ash2_end_run(8);
+ return r[a / 2];
+ }
+ if ((a & 0x30) == 0x30) {
+ sh2_poll[cpuid].cnt = 0;
+ return p32x_pwm_read16(a);
+ }
return 0;
}
{
a &= 0xfe;
+ // comm
if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
Pico32x.regs[a / 2] = d;
p32x_poll_undetect(&m68k_poll, 0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
return;
}
+ // PWM
+ else if ((a & 0x30) == 0x30) {
+ p32x_pwm_write16(a, d);
+ return;
+ }
switch (a) {
case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
u32 p32x_sh2_read8(u32 a, int id)
{
- int pd_vdp = 0;
u32 d = 0;
if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
if ((a & 0x0fffff00) == 0x4000) {
d = p32x_sh2reg_read16(a, id);
- goto out_pd;
+ goto out_16to8;
}
if ((a & 0x0fffff00) == 0x4100) {
d = p32x_vdp_read16(a);
- pd_vdp = 1;
- goto out_pd;
+ if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1))
+ ash2_end_run(8);
+ goto out_16to8;
}
if ((a & 0x0fffff00) == 0x4200) {
id ? 's' : 'm', a, d, sh2_pc(id));
return d;
-out_pd:
- if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), pd_vdp))
- ash2_end_run(8);
-
out_16to8:
if (a & 1)
d &= 0xff;
u32 p32x_sh2_read16(u32 a, int id)
{
- int pd_vdp = 0;
u32 d = 0;
if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
if ((a & 0x0fffff00) == 0x4000) {
d = p32x_sh2reg_read16(a, id);
- goto out_pd;
+ goto out;
}
if ((a & 0x0fffff00) == 0x4100) {
d = p32x_vdp_read16(a);
- pd_vdp = 1;
- goto out_pd;
+ if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), 1))
+ ash2_end_run(8);
+ goto out;
}
if ((a & 0x0fffff00) == 0x4200) {
id ? 's' : 'm', a, d, sh2_pc(id));
return d;
-out_pd:
- if (p32x_poll_detect(&sh2_poll[id], a, sh2_pc(id), pd_vdp))
- ash2_end_run(8);
-
out:
elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
id ? 's' : 'm', a, d, sh2_pc(id));
--- /dev/null
+#include "../pico_int.h"
+
+static int pwm_line_samples;
+static int pwm_cycles;
+static int pwm_mult;
+static int pwm_ptr;
+int pwm_frame_smp_cnt;
+
+
+void p32x_pwm_refresh(void)
+{
+ int cycles = Pico32x.regs[0x32 / 2];
+ int frame_samples;
+
+ cycles = (cycles - 1) & 0x0fff;
+ if (cycles < 500) {
+ elprintf(EL_32X|EL_ANOMALY, "pwm: low cycle value: %d", cycles + 1);
+ cycles = 500;
+ }
+ pwm_cycles = cycles;
+ pwm_mult = 0x10000 / cycles;
+ if (Pico.m.pal)
+ frame_samples = OSC_PAL / 7 * 3 / 50 / cycles;
+ else
+ frame_samples = OSC_NTSC / 7 * 3 / 60 / cycles;
+
+ pwm_line_samples = (frame_samples << 16) / scanlines_total;
+}
+
+// irq for every sample??
+// FIXME: we need to hit more than once per line :(
+void p32x_pwm_irq_check(void)
+{
+ int tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
+ if (tm == 0)
+ return; // TODO: verify
+
+ Pico32x.pwm_irq_sample_cnt += pwm_line_samples;
+ if (Pico32x.pwm_irq_sample_cnt >= (tm << 16)) {
+ Pico32x.pwm_irq_sample_cnt -= tm << 16;
+ Pico32x.sh2irqs |= P32XI_PWM;
+ p32x_update_irls();
+ }
+}
+
+unsigned int p32x_pwm_read16(unsigned int a)
+{
+ unsigned int d = 0;
+ int predict;
+
+ a &= 0x0e;
+ switch (a) {
+ case 0: // control
+ case 2: // cycle
+ return Pico32x.regs[(0x30 + a) / 2];
+
+ case 4: // L ch
+ case 6: // R ch
+ case 8: // MONO
+ predict = (pwm_line_samples * Pico.m.scanline) >> 16;
+ elprintf(EL_32X, "pwm: read status: ptr %d/%d, predict %d",
+ pwm_frame_smp_cnt, (pwm_line_samples * scanlines_total) >> 16, predict);
+ if (pwm_frame_smp_cnt > predict + 3)
+ d |= P32XP_FULL;
+ else if (pwm_frame_smp_cnt == 0 || pwm_frame_smp_cnt < predict - 1)
+ d |= P32XP_EMPTY;
+ break;
+ }
+
+ return d;
+}
+
+void p32x_pwm_write16(unsigned int a, unsigned int d)
+{
+ a &= 0x0e;
+ if (a == 0) // control
+ Pico32x.regs[0x30 / 2] = d;
+ else if (a == 2) { // cycle
+ Pico32x.regs[0x32 / 2] = d & 0x0fff;
+ p32x_pwm_refresh();
+ Pico32x.pwm_irq_sample_cnt = 0; // resets?
+ }
+ else if (a <= 8) {
+ d &= 0x0fff;
+ if (d > pwm_cycles)
+ d = pwm_cycles;
+ d = (d - pwm_cycles / 2) * pwm_mult;
+
+ if (a < 6) // L ch
+ Pico32xMem->pwm[pwm_ptr * 2] = d;
+ else if (a == 6) // R ch
+ Pico32xMem->pwm[pwm_ptr * 2 + 1] = d;
+ else // MONO
+ Pico32xMem->pwm[pwm_ptr * 2] = Pico32xMem->pwm[pwm_ptr * 2 + 1] = d;
+
+ if (a >= 6) { // R or MONO
+ pwm_frame_smp_cnt++;
+ pwm_ptr = (pwm_ptr + 1) & (PWM_BUFF_LEN - 1);
+ elprintf(EL_32X, "pwm: smp_cnt %d, ptr %d, smp %x", pwm_frame_smp_cnt, pwm_ptr, d);
+ }
+ }
+}
+
+void p32x_pwm_update(int *buf32, int length, int stereo)
+{
+ extern int pwm_ptr;
+ short *pwmb;
+ int step;
+ int p = 0;
+
+ if (pwm_ptr <= 16) // at least some samples..
+ return;
+
+ step = (pwm_ptr << 16) / length; // FIXME: division..
+ pwmb = Pico32xMem->pwm;
+
+ if (stereo)
+ {
+ while (length-- > 0) {
+ *buf32++ += pwmb[0];
+ *buf32++ += pwmb[1];
+
+ p += step;
+ pwmb += (p >> 16) * 2;
+ p &= 0xffff;
+ }
+ }
+ else
+ {
+ while (length-- > 0) {
+ *buf32++ += pwmb[0];
+
+ p += step;
+ pwmb += (p >> 16) * 2;
+ p &= 0xffff;
+ }
+ }
+
+ elprintf(EL_STATUS, "pwm_update: pwm_ptr %d, len %d, step %04x, done %d",
+ pwm_ptr, length, step, (pwmb - Pico32xMem->pwm) / 2);
+
+ pwm_ptr = 0;
+}
+
dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
+ dump_ram(Pico32xMem->data_array[0], "dumps/data_array0.bin");
+ dump_ram(Pico32xMem->data_array[1], "dumps/data_array1.bin");
}
}
goto end;\r
}\r
\r
- if (!(PicoOpt & POPT_DIS_32X)) {\r
+ if (PicoOpt & POPT_EN_32X) {\r
d = PicoRead8_32x(a);\r
goto end;\r
}\r
goto end;\r
}\r
\r
- if (!(PicoOpt & POPT_DIS_32X)) {\r
+ if (PicoOpt & POPT_EN_32X) {\r
d = PicoRead16_32x(a);\r
goto end;\r
}\r
Pico.m.sram_reg |= (u8)(d & 3);\r
return;\r
}\r
- if (!(PicoOpt & POPT_DIS_32X)) {\r
+ if (PicoOpt & POPT_EN_32X) {\r
PicoWrite8_32x(a, d);\r
return;\r
}\r
Pico.m.sram_reg |= (u8)(d & 3);\r
return;\r
}\r
- if (!(PicoOpt & POPT_DIS_32X)) {\r
+ if (PicoOpt & POPT_EN_32X) {\r
PicoWrite16_32x(a, d);\r
return;\r
}\r
.equ SRR_READONLY, (1 << 1)\r
.equ SRF_EEPROM, (1 << 1)\r
.equ POPT_6BTN_PAD, (1 << 5)\r
-.equ POPT_DIS_32X, (1 << 20)\r
+.equ POPT_EN_32X, (1 << 20)\r
\r
.text\r
.align 4\r
m_read8_not_brq:\r
ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- tst r2, #POPT_DIS_32X\r
- beq PicoRead8_32x\r
+ tst r2, #POPT_EN_32X\r
+ bne PicoRead8_32x\r
mov r0, #0\r
bx lr\r
\r
m_read16_not_brq:\r
ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- tst r2, #POPT_DIS_32X\r
- beq PicoRead16_32x\r
+ tst r2, #POPT_EN_32X\r
+ bne PicoRead16_32x\r
mov r0, #0\r
bx lr\r
\r
m_write8_not_sreg:\r
ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- tst r2, #POPT_DIS_32X\r
- beq PicoWrite8_32x\r
+ tst r2, #POPT_EN_32X\r
+ bne PicoWrite8_32x\r
bx lr\r
\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
m_write16_not_sreg:\r
ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- tst r2, #POPT_DIS_32X\r
- beq PicoWrite16_32x\r
+ tst r2, #POPT_EN_32X\r
+ bne PicoWrite16_32x\r
bx lr\r
\r
.pool\r
if (PicoAHW & PAHW_MCD)\r
PicoPowerMCD();\r
\r
- if (!(PicoOpt & POPT_DIS_32X))\r
+ if (PicoOpt & POPT_EN_32X)\r
PicoPower32x();\r
\r
PicoReset();\r
if (!(PicoOpt & POPT_DIS_IDLE_DET))\r
SekInitIdleDet();\r
\r
- if (!(PicoOpt & POPT_DIS_32X)) {\r
+ if (PicoOpt & POPT_EN_32X) {\r
PicoReset32x();\r
return 0;\r
}\r
\r
// FIXME: PAL has 313 scanlines..\r
scanlines_total = Pico.m.pal ? 312 : 262;\r
+\r
+ if (PicoAHW & PAHW_32X)\r
+ p32x_pwm_refresh();\r
}\r
\r
\r
#define POPT_EN_SVP_DRC (1<<17)\r
#define POPT_DIS_SPRITE_LIM (1<<18)\r
#define POPT_DIS_IDLE_DET (1<<19)\r
-#define POPT_DIS_32X (1<<20)\r
-#define POPT_DIS_PWM (1<<21)\r
+#define POPT_EN_32X (1<<20)\r
+#define POPT_EN_PWM (1<<21)\r
extern int PicoOpt; // bitfield\r
\r
#define PAHW_MCD (1<<0)\r
#ifdef PICO_CD
check_cd_dma();
#endif
+#ifdef PICO_32X
+ p32x_pwm_irq_check();
+#endif
// H-Interrupts:
if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
#ifdef PICO_CD
check_cd_dma();
#endif
+#ifdef PICO_32X
+ p32x_pwm_irq_check();
+#endif
// Last H-Int:
if (--hint < 0)
#ifdef PICO_CD
check_cd_dma();
#endif
+#ifdef PICO_32X
+ p32x_pwm_irq_check();
+#endif
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
// Pico Library - Internal Header File\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
-// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
+// (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
#define P32XV_nFEN (1<< 1)\r
#define P32XV_FS (1<< 0)\r
\r
+#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_EMPTY (1<<14)\r
+\r
#define P32XF_68KPOLL (1 << 0)\r
#define P32XF_MSH2POLL (1 << 1)\r
#define P32XF_SSH2POLL (1 << 2)\r
\r
// real one is 4*2, but we use more because we don't lockstep\r
#define DMAC_FIFO_LEN (4*4)\r
+#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
struct Pico32x\r
{\r
unsigned int sh2irqs; // common irqs\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
unsigned int dmac_ptr;\r
+ unsigned int pwm_irq_sample_cnt;\r
};\r
\r
struct Pico32xMem\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
+ signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
};\r
\r
// area.c\r
// 32x/draw.c\r
void FinalizeLine32xRGB555(int sh, int line);\r
\r
+// 32x/pwm.c\r
+unsigned int p32x_pwm_read16(unsigned int a);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d);\r
+void p32x_pwm_refresh(void);\r
+void p32x_pwm_irq_check(void);\r
+void p32x_pwm_update(int *buf32, int length, int stereo);\r
+extern int pwm_frame_smp_cnt;\r
+\r
/* avoid dependency on newer glibc */\r
static __inline int isspace_(int c)\r
{\r
cdda_raw_update(buf32, length);\r
}\r
\r
+ if ((PicoAHW & PAHW_32X) && (PicoOpt & POPT_EN_PWM))\r
+ p32x_pwm_update(buf32, length, stereo);\r
+\r
// convert + limit to normal 16bit output\r
PsndMix_32_to_16l(PsndOut+offset, buf32, length);\r
\r
return 0;\r
}\r
\r
+// ------------ 32X options menu ------------\r
+\r
+static menu_entry e_menu_32x_options[] =\r
+{\r
+ mee_onoff("32X enabled", MA_32XOPT_ENABLE_32X, PicoOpt, POPT_EN_32X),\r
+ mee_onoff("PWM sound", MA_32XOPT_PWM, PicoOpt, POPT_EN_PWM),\r
+};\r
+\r
+static int menu_loop_32x_options(menu_id id, int keys)\r
+{\r
+ static int sel = 0;\r
+ me_loop(e_menu_32x_options, &sel, NULL);\r
+ return 0;\r
+}\r
+\r
// ------------ adv options menu ------------\r
\r
static menu_entry e_menu_adv_options[] =\r
mee_range (cpu_clk_name, MA_OPT_CPU_CLOCKS, currentConfig.CPUclock, 20, 900),\r
mee_handler ("[Display options]", menu_loop_gfx_options),\r
mee_handler ("[Sega/Mega CD options]", menu_loop_cd_options),\r
+ mee_handler ("[32X options]", menu_loop_32x_options),\r
mee_handler ("[Advanced options]", menu_loop_adv_options),\r
mee_handler_mkname_id(MA_OPT_SAVECFG, mh_saveloadcfg, mgn_savecfg),\r
mee_handler_id("Save cfg for current game only", MA_OPT_SAVECFG_GAME, mh_saveloadcfg),\r
e_menu_gfx_options,\r
e_menu_adv_options,\r
e_menu_cd_options,\r
+ e_menu_32x_options,\r
e_menu_keyconfig,\r
e_menu_hidden,\r
};\r
MA_CDOPT_SCALEROT_CHIP,
MA_CDOPT_BETTER_SYNC,
MA_CDOPT_DONE,
+ MA_32XOPT_ENABLE_32X,
+ MA_32XOPT_PWM,
MA_CTRL_PLAYER1,
MA_CTRL_PLAYER2,
MA_CTRL_EMU,
pico/cd/area.o pico/cd/misc.o pico/cd/pcm.o pico/cd/buffering.o\r
endif\r
# Pico - 32X\r
-OBJS += pico/32x/32x.o pico/32x/memory.o pico/32x/draw.o\r
+OBJS += pico/32x/32x.o pico/32x/memory.o pico/32x/draw.o pico/32x/pwm.o\r
# Pico - Pico\r
OBJS += pico/pico/pico.o pico/pico/memory.o pico/pico/xpcm.o\r
# Pico - carthw\r
\r
memset(&defaultConfig, 0, sizeof(defaultConfig));\r
defaultConfig.EmuOpt = 0x9d | EOPT_RAM_TIMINGS|EOPT_CONFIRM_SAVE|EOPT_EN_CD_LEDS;\r
- defaultConfig.s_PicoOpt = 0x0f | POPT_EN_MCD_PCM|POPT_EN_MCD_CDDA|POPT_EN_SVP_DRC|POPT_ACC_SPRITES;\r
+ defaultConfig.s_PicoOpt = POPT_EN_STEREO|POPT_EN_FM|POPT_EN_PSG|POPT_EN_Z80 |\r
+ POPT_EN_MCD_PCM|POPT_EN_MCD_CDDA|POPT_EN_SVP_DRC|POPT_ACC_SPRITES |\r
+ POPT_EN_32X|POPT_EN_PWM;\r
defaultConfig.s_PsndRate = 44100;\r
defaultConfig.s_PicoRegion = 0; // auto\r
defaultConfig.s_PicoAutoRgnOrder = 0x184; // US, EU, JP\r
pico/cd/cd_sys.o pico/cd/cd_file.o pico/cd/cue.o pico/cd/gfx_cd.o \
pico/cd/area.o pico/cd/misc.o pico/cd/pcm.o pico/cd/buffering.o
# Pico - 32X
-OBJS += pico/32x/32x.o pico/32x/memory.o pico/32x/draw.o
+OBJS += pico/32x/32x.o pico/32x/memory.o pico/32x/draw.o pico/32x/pwm.o
# Pico - Pico
OBJS += pico/pico/pico.o pico/pico/memory.o pico/pico/xpcm.o
# Pico - sound