\r
\r
/* OPN Mode Register Write */\r
-INLINE void set_timers( int v )\r
+static INLINE void set_timers( int v )\r
{\r
/* b7 = CSM MODE */\r
/* b6 = 3 slot mode */\r
}\r
\r
/* set total level */\r
-INLINE void set_tl(FM_SLOT *SLOT, int v)\r
+static INLINE void set_tl(FM_SLOT *SLOT, int v)\r
{\r
SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */\r
}\r
\r
/* set attack rate & key scale */\r
-INLINE void set_ar_ksr(FM_CH *CH, FM_SLOT *SLOT, int v)\r
+static INLINE void set_ar_ksr(FM_CH *CH, FM_SLOT *SLOT, int v)\r
{\r
UINT8 old_KSR = SLOT->KSR;\r
\r
}\r
\r
/* set decay rate */\r
-INLINE void set_dr(FM_SLOT *SLOT, int v)\r
+static INLINE void set_dr(FM_SLOT *SLOT, int v)\r
{\r
int eg_sh_d1r, eg_sel_d1r;\r
\r
}\r
\r
/* set sustain rate */\r
-INLINE void set_sr(FM_SLOT *SLOT, int v)\r
+static INLINE void set_sr(FM_SLOT *SLOT, int v)\r
{\r
int eg_sh_d2r, eg_sel_d2r;\r
\r
}\r
\r
/* set release rate */\r
-INLINE void set_sl_rr(FM_SLOT *SLOT, int v)\r
+static INLINE void set_sl_rr(FM_SLOT *SLOT, int v)\r
{\r
int eg_sh_rr, eg_sel_rr;\r
\r
SLOT->eg_pack_rr = eg_inc_pack[eg_sel_rr] | (eg_sh_rr<<24);\r
}\r
\r
-\r
-\r
INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm)\r
{\r
int ret, sin = (phase>>16) + (pm>>1);\r