{
/* update IRQ level */
elprintf(EL_INTS, "cdc DTE irq 5");
- SekInterruptS68k(5);
+ pcd_irq_s68k(5, 1);
}
}
{
/* update IRQ level */
elprintf(EL_INTS, "cdc DEC irq 5");
- SekInterruptS68k(5);
+ pcd_irq_s68k(5, 1);
}
}
{
/* update IRQ level */
elprintf(EL_INTS, "cdc pending irq 5");
- SekInterruptS68k(5);
+ pcd_irq_s68k(5, 1);
}
}
else // if (scd.pending & (1 << 5))
{
/* clear pending level 5 interrupts */
- SekInterruptClearS68k(5);
+ pcd_irq_s68k(5, 0);
}
/* abort any data transfer if data output is disabled */
if ((cdc.ifstat | BIT_DECI) || !(cdc.ifctrl & BIT_DECIEN))
{
/* clear pending level 5 interrupt */
- SekInterruptClearS68k(5);
+ pcd_irq_s68k(5, 0);
}
#endif
Pico_mcd->s68k_regs[0x04+1] = 0x08;
if ((cdc.ifstat | BIT_DTEI) || !(cdc.ifctrl & BIT_DTEIEN))
{
/* clear pending level 5 interrupt */
- SekInterruptClearS68k(5);
+ pcd_irq_s68k(5, 0);
}
#endif
{
/* update IRQ level */
elprintf(EL_INTS, "cdc DTE irq 5");
- SekInterruptS68k(5);
+ pcd_irq_s68k(5, 1);
}
}
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN1) {
elprintf(EL_INTS|EL_CD, "s68k: gfx_cd irq 1");
- SekInterruptS68k(1);
+ pcd_irq_s68k(1, 1);
}
}
else {
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) {
elprintf(EL_INTS|EL_CD, "s68k: cdd irq 4");
- SekInterruptS68k(4);
+ pcd_irq_s68k(4, 1);
}
}
{
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN3) {
elprintf(EL_INTS|EL_CD, "s68k: timer irq 3");
- SekInterruptS68k(3);
+ pcd_irq_s68k(3, 1);
}
if (Pico_mcd->s68k_regs[0x31] != 0)
oldest, event_time_next);
}
+void pcd_irq_s68k(int irq, int state)
+{
+ if (state) {
+ SekInterruptS68k(irq);
+ SekSetStopS68k(0);
+ Pico_mcd->m.s68k_poll_a = 0;
+ } else
+ SekInterruptClearS68k(irq);
+}
+
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync)
{
#define now SekCycleCntS68k
if (d && (Pico_mcd->s68k_regs[0x33] & PCDS_IEN2)) {\r
elprintf(EL_INTS, "m68k: s68k irq 2");\r
pcd_sync_s68k(SekCyclesDone(), 0);\r
- SekInterruptS68k(2);\r
+ pcd_irq_s68k(2, 1);\r
}\r
return;\r
case 1:\r
// XXX: emulate pending irq instead?\r
if (Pico_mcd->s68k_regs[0x37] & 4) {\r
elprintf(EL_INTS, "cdd export irq 4 (unmask)");\r
- SekInterruptS68k(4);\r
+ pcd_irq_s68k(4, 1);\r
}\r
}\r
break;\r
\r
if (Pico_mcd->s68k_regs[0x33] & PCDS_IEN4) {\r
elprintf(EL_INTS, "cdd export irq 4");\r
- SekInterruptS68k(4);\r
+ pcd_irq_s68k(4, 1);\r
}\r
}\r
return;\r
void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
void pcd_prepare_frame(void);\r
unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
+void pcd_irq_s68k(int irq, int state);\r
int pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
void pcd_run_cpus(int m68k_cycles);\r
void pcd_soft_reset(void);\r