\r
/*****************************************************************************\r
Changes\r
+ 20130129 Angelo Salese\r
+ - added illegal opcode exception handling, side effect of some Saturn games\r
+ on loading like Feda or Falcom Classics Vol. 1\r
+ (i.e. Master CPU Incautiously transfers memory from CD to work RAM H, and\r
+ wipes out Slave CPU program code too while at it).\r
+\r
20051129 Mariusz Wojcieszek\r
- introduced memory_decrypted_read_word() for opcode fetching\r
\r
\r
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)\r
\r
-//int sh2_icount;\r
-//SH2 *sh2;\r
-\r
#if 0\r
-INLINE UINT8 RB(offs_t A)\r
+INLINE UINT8 RB(sh2_state *sh2, offs_t A)\r
{\r
if (A >= 0xe0000000)\r
- return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);\r
+ return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);\r
\r
if (A >= 0xc0000000)\r
- return memory_read_byte_32be(sh2->program, A);\r
+ return sh2->program->read_byte(A);\r
\r
if (A >= 0x40000000)\r
return 0xa5;\r
\r
- return memory_read_byte_32be(sh2->program, A & AM);\r
+ return sh2->program->read_byte(A & AM);\r
}\r
\r
-INLINE UINT16 RW(offs_t A)\r
+INLINE UINT16 RW(sh2_state *sh2, offs_t A)\r
{\r
if (A >= 0xe0000000)\r
- return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);\r
+ return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);\r
\r
if (A >= 0xc0000000)\r
- return memory_read_word_32be(sh2->program, A);\r
+ return sh2->program->read_word(A);\r
\r
if (A >= 0x40000000)\r
return 0xa5a5;\r
\r
- return memory_read_word_32be(sh2->program, A & AM);\r
+ return sh2->program->read_word(A & AM);\r
}\r
\r
-INLINE UINT32 RL(offs_t A)\r
+INLINE UINT32 RL(sh2_state *sh2, offs_t A)\r
{\r
if (A >= 0xe0000000)\r
- return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffffffff);\r
+ return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);\r
\r
if (A >= 0xc0000000)\r
- return memory_read_dword_32be(sh2->program, A);\r
+ return sh2->program->read_dword(A);\r
\r
if (A >= 0x40000000)\r
return 0xa5a5a5a5;\r
\r
- return memory_read_dword_32be(sh2->program, A & AM);\r
+ return sh2->program->read_dword(A & AM);\r
}\r
\r
-INLINE void WB(offs_t A, UINT8 V)\r
+INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)\r
{\r
-\r
if (A >= 0xe0000000)\r
{\r
- sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));\r
+ sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));\r
return;\r
}\r
\r
if (A >= 0xc0000000)\r
{\r
- memory_write_byte_32be(sh2->program, A,V);\r
+ sh2->program->write_byte(A,V);\r
return;\r
}\r
\r
if (A >= 0x40000000)\r
return;\r
\r
- memory_write_byte_32be(sh2->program, A & AM,V);\r
+ sh2->program->write_byte(A & AM,V);\r
}\r
\r
-INLINE void WW(offs_t A, UINT16 V)\r
+INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)\r
{\r
if (A >= 0xe0000000)\r
{\r
- sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));\r
+ sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));\r
return;\r
}\r
\r
if (A >= 0xc0000000)\r
{\r
- memory_write_word_32be(sh2->program, A,V);\r
+ sh2->program->write_word(A,V);\r
return;\r
}\r
\r
if (A >= 0x40000000)\r
return;\r
\r
- memory_write_word_32be(sh2->program, A & AM,V);\r
+ sh2->program->write_word(A & AM,V);\r
}\r
\r
-INLINE void WL(offs_t A, UINT32 V)\r
+INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)\r
{\r
if (A >= 0xe0000000)\r
{\r
- sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);\r
+ sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);\r
return;\r
}\r
\r
if (A >= 0xc0000000)\r
{\r
- memory_write_dword_32be(sh2->program, A,V);\r
+ sh2->program->write_dword(A,V);\r
return;\r
}\r
\r
if (A >= 0x40000000)\r
return;\r
\r
- memory_write_dword_32be(sh2->program, A & AM,V);\r
+ sh2->program->write_dword(A & AM,V);\r
}\r
#endif\r
\r
* 0011 nnnn mmmm 1100 1 -\r
* ADD Rm,Rn\r
*/\r
-INLINE void ADD(UINT32 m, UINT32 n)\r
+INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] += sh2->r[m];\r
}\r
* 0111 nnnn iiii iiii 1 -\r
* ADD #imm,Rn\r
*/\r
-INLINE void ADDI(UINT32 i, UINT32 n)\r
+INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)\r
{\r
sh2->r[n] += (INT32)(INT16)(INT8)i;\r
}\r
* 0011 nnnn mmmm 1110 1 carry\r
* ADDC Rm,Rn\r
*/\r
-INLINE void ADDC(UINT32 m, UINT32 n)\r
+INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 tmp0, tmp1;\r
\r
* 0011 nnnn mmmm 1111 1 overflow\r
* ADDV Rm,Rn\r
*/\r
-INLINE void ADDV(UINT32 m, UINT32 n)\r
+INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
INT32 dest, src, ans;\r
\r
* 0010 nnnn mmmm 1001 1 -\r
* AND Rm,Rn\r
*/\r
-INLINE void AND(UINT32 m, UINT32 n)\r
+INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] &= sh2->r[m];\r
}\r
* 1100 1001 iiii iiii 1 -\r
* AND #imm,R0\r
*/\r
-INLINE void ANDI(UINT32 i)\r
+INLINE void ANDI(sh2_state *sh2, UINT32 i)\r
{\r
sh2->r[0] &= i;\r
}\r
* 1100 1101 iiii iiii 1 -\r
* AND.B #imm,@(R0,GBR)\r
*/\r
-INLINE void ANDM(UINT32 i)\r
+INLINE void ANDM(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 temp;\r
\r
sh2->ea = sh2->gbr + sh2->r[0];\r
- temp = i & RB( sh2->ea );\r
- WB( sh2->ea, temp );\r
- sh2_icount -= 2;\r
+ temp = i & RB( sh2, sh2->ea );\r
+ WB( sh2, sh2->ea, temp );\r
+ sh2->icount -= 2;\r
}\r
\r
/* code cycles t-bit\r
* 1000 1011 dddd dddd 3/1 -\r
* BF disp8\r
*/\r
-INLINE void BF(UINT32 d)\r
+INLINE void BF(sh2_state *sh2, UINT32 d)\r
{\r
if ((sh2->sr & T) == 0)\r
{\r
INT32 disp = ((INT32)d << 24) >> 24;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
}\r
\r
* 1000 1111 dddd dddd 3/1 -\r
* BFS disp8\r
*/\r
-INLINE void BFS(UINT32 d)\r
+INLINE void BFS(sh2_state *sh2, UINT32 d)\r
{\r
if ((sh2->sr & T) == 0)\r
{\r
INT32 disp = ((INT32)d << 24) >> 24;\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
}\r
\r
* 1010 dddd dddd dddd 2 -\r
* BRA disp12\r
*/\r
-INLINE void BRA(UINT32 d)\r
+INLINE void BRA(sh2_state *sh2, UINT32 d)\r
{\r
INT32 disp = ((INT32)d << 20) >> 20;\r
\r
#if BUSY_LOOP_HACKS\r
if (disp == -2)\r
{\r
- UINT32 next_opcode = RW(sh2->pc & AM);\r
+ UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
/* BRA $\r
- * NOP\r
- */\r
+ * NOP\r
+ */\r
if (next_opcode == 0x0009)\r
- sh2_icount %= 3; /* cycles for BRA $ and NOP taken (3) */\r
+ sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */\r
}\r
#endif\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* code cycles t-bit\r
* 0000 mmmm 0010 0011 2 -\r
* BRAF Rm\r
*/\r
-INLINE void BRAF(UINT32 m)\r
+INLINE void BRAF(sh2_state *sh2, UINT32 m)\r
{\r
sh2->delay = sh2->pc;\r
sh2->pc += sh2->r[m] + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* code cycles t-bit\r
* 1011 dddd dddd dddd 2 -\r
* BSR disp12\r
*/\r
-INLINE void BSR(UINT32 d)\r
+INLINE void BSR(sh2_state *sh2, UINT32 d)\r
{\r
INT32 disp = ((INT32)d << 20) >> 20;\r
\r
sh2->pr = sh2->pc + 2;\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* code cycles t-bit\r
* 0000 mmmm 0000 0011 2 -\r
* BSRF Rm\r
*/\r
-INLINE void BSRF(UINT32 m)\r
+INLINE void BSRF(sh2_state *sh2, UINT32 m)\r
{\r
sh2->pr = sh2->pc + 2;\r
sh2->delay = sh2->pc;\r
sh2->pc += sh2->r[m] + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* code cycles t-bit\r
* 1000 1001 dddd dddd 3/1 -\r
* BT disp8\r
*/\r
-INLINE void BT(UINT32 d)\r
+INLINE void BT(sh2_state *sh2, UINT32 d)\r
{\r
if ((sh2->sr & T) != 0)\r
{\r
INT32 disp = ((INT32)d << 24) >> 24;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
}\r
\r
* 1000 1101 dddd dddd 2/1 -\r
* BTS disp8\r
*/\r
-INLINE void BTS(UINT32 d)\r
+INLINE void BTS(sh2_state *sh2, UINT32 d)\r
{\r
if ((sh2->sr & T) != 0)\r
{\r
INT32 disp = ((INT32)d << 24) >> 24;\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
}\r
\r
* 0000 0000 0010 1000 1 -\r
* CLRMAC\r
*/\r
-INLINE void CLRMAC(void)\r
+INLINE void CLRMAC(sh2_state *sh2)\r
{\r
sh2->mach = 0;\r
sh2->macl = 0;\r
* 0000 0000 0000 1000 1 -\r
* CLRT\r
*/\r
-INLINE void CLRT(void)\r
+INLINE void CLRT(sh2_state *sh2)\r
{\r
sh2->sr &= ~T;\r
}\r
* 0011 nnnn mmmm 0000 1 comparison result\r
* CMP_EQ Rm,Rn\r
*/\r
-INLINE void CMPEQ(UINT32 m, UINT32 n)\r
+INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if (sh2->r[n] == sh2->r[m])\r
sh2->sr |= T;\r
* 0011 nnnn mmmm 0011 1 comparison result\r
* CMP_GE Rm,Rn\r
*/\r
-INLINE void CMPGE(UINT32 m, UINT32 n)\r
+INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])\r
sh2->sr |= T;\r
* 0011 nnnn mmmm 0111 1 comparison result\r
* CMP_GT Rm,Rn\r
*/\r
-INLINE void CMPGT(UINT32 m, UINT32 n)\r
+INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((INT32) sh2->r[n] > (INT32) sh2->r[m])\r
sh2->sr |= T;\r
* 0011 nnnn mmmm 0110 1 comparison result\r
* CMP_HI Rm,Rn\r
*/\r
-INLINE void CMPHI(UINT32 m, UINT32 n)\r
+INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])\r
sh2->sr |= T;\r
* 0011 nnnn mmmm 0010 1 comparison result\r
* CMP_HS Rm,Rn\r
*/\r
-INLINE void CMPHS(UINT32 m, UINT32 n)\r
+INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])\r
sh2->sr |= T;\r
* 0100 nnnn 0001 0101 1 comparison result\r
* CMP_PL Rn\r
*/\r
-INLINE void CMPPL(UINT32 n)\r
+INLINE void CMPPL(sh2_state *sh2, UINT32 n)\r
{\r
if ((INT32) sh2->r[n] > 0)\r
sh2->sr |= T;\r
* 0100 nnnn 0001 0001 1 comparison result\r
* CMP_PZ Rn\r
*/\r
-INLINE void CMPPZ(UINT32 n)\r
+INLINE void CMPPZ(sh2_state *sh2, UINT32 n)\r
{\r
if ((INT32) sh2->r[n] >= 0)\r
sh2->sr |= T;\r
* 0010 nnnn mmmm 1100 1 comparison result\r
* CMP_STR Rm,Rn\r
*/\r
-INLINE void CMPSTR(UINT32 m, UINT32 n)\r
- {\r
- UINT32 temp;\r
- INT32 HH, HL, LH, LL;\r
- temp = sh2->r[n] ^ sh2->r[m];\r
- HH = (temp >> 24) & 0xff;\r
- HL = (temp >> 16) & 0xff;\r
- LH = (temp >> 8) & 0xff;\r
- LL = temp & 0xff;\r
- if (HH && HL && LH && LL)\r
- sh2->sr &= ~T;\r
- else\r
- sh2->sr |= T;\r
- }\r
+INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)\r
+ {\r
+ UINT32 temp;\r
+ INT32 HH, HL, LH, LL;\r
+ temp = sh2->r[n] ^ sh2->r[m];\r
+ HH = (temp >> 24) & 0xff;\r
+ HL = (temp >> 16) & 0xff;\r
+ LH = (temp >> 8) & 0xff;\r
+ LL = temp & 0xff;\r
+ if (HH && HL && LH && LL)\r
+ sh2->sr &= ~T;\r
+ else\r
+ sh2->sr |= T;\r
+ }\r
\r
\r
/* code cycles t-bit\r
* 1000 1000 iiii iiii 1 comparison result\r
* CMP/EQ #imm,R0\r
*/\r
-INLINE void CMPIM(UINT32 i)\r
+INLINE void CMPIM(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;\r
\r
* 0010 nnnn mmmm 0111 1 calculation result\r
* DIV0S Rm,Rn\r
*/\r
-INLINE void DIV0S(UINT32 m, UINT32 n)\r
+INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((sh2->r[n] & 0x80000000) == 0)\r
sh2->sr &= ~Q;\r
* 0000 0000 0001 1001 1 0\r
* DIV0U\r
*/\r
-INLINE void DIV0U(void)\r
+INLINE void DIV0U(sh2_state *sh2)\r
{\r
sh2->sr &= ~(M | Q | T);\r
}\r
* 0011 nnnn mmmm 0100 1 calculation result\r
* DIV1 Rm,Rn\r
*/\r
-INLINE void DIV1(UINT32 m, UINT32 n)\r
+INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 tmp0;\r
UINT32 old_q;\r
}\r
\r
/* DMULS.L Rm,Rn */\r
-INLINE void DMULS(UINT32 m, UINT32 n)\r
+INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
UINT32 temp0, temp1, temp2, temp3;\r
}\r
sh2->mach = Res2;\r
sh2->macl = Res0;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* DMULU.L Rm,Rn */\r
-INLINE void DMULU(UINT32 m, UINT32 n)\r
+INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
UINT32 temp0, temp1, temp2, temp3;\r
Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
sh2->mach = Res2;\r
sh2->macl = Res0;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* DT Rn */\r
-INLINE void DT(UINT32 n)\r
+INLINE void DT(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n]--;\r
if (sh2->r[n] == 0)\r
sh2->sr &= ~T;\r
#if BUSY_LOOP_HACKS\r
{\r
- UINT32 next_opcode = RW(sh2->pc & AM);\r
+ UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
/* DT Rn\r
- * BF $-2\r
- */\r
+ * BF $-2\r
+ */\r
if (next_opcode == 0x8bfd)\r
{\r
- while (sh2->r[n] > 1 && sh2_icount > 4)\r
+ while (sh2->r[n] > 1 && sh2->icount > 4)\r
{\r
sh2->r[n]--;\r
- sh2_icount -= 4; /* cycles for DT (1) and BF taken (3) */\r
+ sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */\r
}\r
}\r
}\r
}\r
\r
/* EXTS.B Rm,Rn */\r
-INLINE void EXTSB(UINT32 m, UINT32 n)\r
+INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;\r
}\r
\r
/* EXTS.W Rm,Rn */\r
-INLINE void EXTSW(UINT32 m, UINT32 n)\r
+INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;\r
}\r
\r
/* EXTU.B Rm,Rn */\r
-INLINE void EXTUB(UINT32 m, UINT32 n)\r
+INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = sh2->r[m] & 0x000000ff;\r
}\r
\r
/* EXTU.W Rm,Rn */\r
-INLINE void EXTUW(UINT32 m, UINT32 n)\r
+INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = sh2->r[m] & 0x0000ffff;\r
}\r
\r
+/* ILLEGAL */\r
+INLINE void ILLEGAL(sh2_state *sh2)\r
+{\r
+ logerror("SH2: Illegal opcode at %08x\n", sh2->pc - 2);\r
+ sh2->r[15] -= 4;\r
+ WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */\r
+ sh2->r[15] -= 4;\r
+ WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */\r
+\r
+ /* fetch PC */\r
+ sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );\r
+\r
+ /* TODO: timing is a guess */\r
+ sh2->icount -= 5;\r
+}\r
+\r
+\r
/* JMP @Rm */\r
-INLINE void JMP(UINT32 m)\r
+INLINE void JMP(sh2_state *sh2, UINT32 m)\r
{\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->r[m];\r
}\r
\r
/* JSR @Rm */\r
-INLINE void JSR(UINT32 m)\r
+INLINE void JSR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->delay = sh2->pc;\r
sh2->pr = sh2->pc + 2;\r
sh2->pc = sh2->ea = sh2->r[m];\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
\r
/* LDC Rm,SR */\r
-INLINE void LDCSR(UINT32 m)\r
+INLINE void LDCSR(sh2_state *sh2, UINT32 m)\r
{\r
- sh2->sr &= ~0xfff;\r
- sh2->sr |= sh2->r[m] & FLAGS;\r
+ sh2->sr = sh2->r[m] & FLAGS;\r
sh2->test_irq = 1;\r
}\r
\r
/* LDC Rm,GBR */\r
-INLINE void LDCGBR(UINT32 m)\r
+INLINE void LDCGBR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->gbr = sh2->r[m];\r
}\r
\r
/* LDC Rm,VBR */\r
-INLINE void LDCVBR(UINT32 m)\r
+INLINE void LDCVBR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->vbr = sh2->r[m];\r
}\r
\r
/* LDC.L @Rm+,SR */\r
-INLINE void LDCMSR(UINT32 m)\r
+INLINE void LDCMSR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->sr &= ~0xfff;\r
- sh2->sr |= RL( sh2->ea ) & FLAGS;\r
+ sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
sh2->r[m] += 4;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
sh2->test_irq = 1;\r
}\r
\r
/* LDC.L @Rm+,GBR */\r
-INLINE void LDCMGBR(UINT32 m)\r
+INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->gbr = RL( sh2->ea );\r
+ sh2->gbr = RL( sh2, sh2->ea );\r
sh2->r[m] += 4;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
\r
/* LDC.L @Rm+,VBR */\r
-INLINE void LDCMVBR(UINT32 m)\r
+INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->vbr = RL( sh2->ea );\r
+ sh2->vbr = RL( sh2, sh2->ea );\r
sh2->r[m] += 4;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
\r
/* LDS Rm,MACH */\r
-INLINE void LDSMACH(UINT32 m)\r
+INLINE void LDSMACH(sh2_state *sh2, UINT32 m)\r
{\r
sh2->mach = sh2->r[m];\r
}\r
\r
/* LDS Rm,MACL */\r
-INLINE void LDSMACL(UINT32 m)\r
+INLINE void LDSMACL(sh2_state *sh2, UINT32 m)\r
{\r
sh2->macl = sh2->r[m];\r
}\r
\r
/* LDS Rm,PR */\r
-INLINE void LDSPR(UINT32 m)\r
+INLINE void LDSPR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->pr = sh2->r[m];\r
}\r
\r
/* LDS.L @Rm+,MACH */\r
-INLINE void LDSMMACH(UINT32 m)\r
+INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->mach = RL( sh2->ea );\r
+ sh2->mach = RL( sh2, sh2->ea );\r
sh2->r[m] += 4;\r
}\r
\r
/* LDS.L @Rm+,MACL */\r
-INLINE void LDSMMACL(UINT32 m)\r
+INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->macl = RL( sh2->ea );\r
+ sh2->macl = RL( sh2, sh2->ea );\r
sh2->r[m] += 4;\r
}\r
\r
/* LDS.L @Rm+,PR */\r
-INLINE void LDSMPR(UINT32 m)\r
+INLINE void LDSMPR(sh2_state *sh2, UINT32 m)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->pr = RL( sh2->ea );\r
+ sh2->pr = RL( sh2, sh2->ea );\r
sh2->r[m] += 4;\r
}\r
\r
/* MAC.L @Rm+,@Rn+ */\r
-INLINE void MAC_L(UINT32 m, UINT32 n)\r
+INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
UINT32 temp0, temp1, temp2, temp3;\r
INT32 tempm, tempn, fnLmL;\r
\r
- tempn = (INT32) RL( sh2->r[n] );\r
+ tempn = (INT32) RL( sh2, sh2->r[n] );\r
sh2->r[n] += 4;\r
- tempm = (INT32) RL( sh2->r[m] );\r
+ tempm = (INT32) RL( sh2, sh2->r[m] );\r
sh2->r[m] += 4;\r
if ((INT32) (tempn ^ tempm) < 0)\r
fnLmL = -1;\r
sh2->mach = Res2;\r
sh2->macl = Res0;\r
}\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
\r
/* MAC.W @Rm+,@Rn+ */\r
-INLINE void MAC_W(UINT32 m, UINT32 n)\r
+INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
INT32 tempm, tempn, dest, src, ans;\r
UINT32 templ;\r
\r
- tempn = (INT32) RW( sh2->r[n] );\r
+ tempn = (INT32) RW( sh2, sh2->r[n] );\r
sh2->r[n] += 2;\r
- tempm = (INT32) RW( sh2->r[m] );\r
+ tempm = (INT32) RW( sh2, sh2->r[m] );\r
sh2->r[m] += 2;\r
templ = sh2->macl;\r
tempm = ((INT32) (short) tempn * (INT32) (short) tempm);\r
sh2->mach += tempn;\r
if (templ > sh2->macl)\r
sh2->mach += 1;\r
- }\r
- sh2_icount -= 2;\r
+ }\r
+ sh2->icount -= 2;\r
}\r
\r
/* MOV Rm,Rn */\r
-INLINE void MOV(UINT32 m, UINT32 n)\r
+INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = sh2->r[m];\r
}\r
\r
/* MOV.B Rm,@Rn */\r
-INLINE void MOVBS(UINT32 m, UINT32 n)\r
+INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n];\r
- WB( sh2->ea, sh2->r[m] & 0x000000ff);\r
+ WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);\r
}\r
\r
/* MOV.W Rm,@Rn */\r
-INLINE void MOVWS(UINT32 m, UINT32 n)\r
+INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n];\r
- WW( sh2->ea, sh2->r[m] & 0x0000ffff);\r
+ WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);\r
}\r
\r
/* MOV.L Rm,@Rn */\r
-INLINE void MOVLS(UINT32 m, UINT32 n)\r
+INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->r[m] );\r
+ WL( sh2, sh2->ea, sh2->r[m] );\r
}\r
\r
/* MOV.B @Rm,Rn */\r
-INLINE void MOVBL(UINT32 m, UINT32 n)\r
+INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
}\r
\r
/* MOV.W @Rm,Rn */\r
-INLINE void MOVWL(UINT32 m, UINT32 n)\r
+INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
}\r
\r
/* MOV.L @Rm,Rn */\r
-INLINE void MOVLL(UINT32 m, UINT32 n)\r
+INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m];\r
- sh2->r[n] = RL( sh2->ea );\r
+ sh2->r[n] = RL( sh2, sh2->ea );\r
}\r
\r
/* MOV.B Rm,@-Rn */\r
-INLINE void MOVBM(UINT32 m, UINT32 n)\r
+INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
/* SMG : bug fix, was reading sh2->r[n] */\r
UINT32 data = sh2->r[m] & 0x000000ff;\r
\r
sh2->r[n] -= 1;\r
- WB( sh2->r[n], data );\r
+ WB( sh2, sh2->r[n], data );\r
}\r
\r
/* MOV.W Rm,@-Rn */\r
-INLINE void MOVWM(UINT32 m, UINT32 n)\r
+INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 data = sh2->r[m] & 0x0000ffff;\r
\r
sh2->r[n] -= 2;\r
- WW( sh2->r[n], data );\r
+ WW( sh2, sh2->r[n], data );\r
}\r
\r
/* MOV.L Rm,@-Rn */\r
-INLINE void MOVLM(UINT32 m, UINT32 n)\r
+INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 data = sh2->r[m];\r
\r
sh2->r[n] -= 4;\r
- WL( sh2->r[n], data );\r
+ WL( sh2, sh2->r[n], data );\r
}\r
\r
/* MOV.B @Rm+,Rn */\r
-INLINE void MOVBP(UINT32 m, UINT32 n)\r
+INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->r[m] );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );\r
if (n != m)\r
sh2->r[m] += 1;\r
}\r
\r
/* MOV.W @Rm+,Rn */\r
-INLINE void MOVWP(UINT32 m, UINT32 n)\r
+INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->r[m] );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );\r
if (n != m)\r
sh2->r[m] += 2;\r
}\r
\r
/* MOV.L @Rm+,Rn */\r
-INLINE void MOVLP(UINT32 m, UINT32 n)\r
+INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
- sh2->r[n] = RL( sh2->r[m] );\r
+ sh2->r[n] = RL( sh2, sh2->r[m] );\r
if (n != m)\r
sh2->r[m] += 4;\r
}\r
\r
/* MOV.B Rm,@(R0,Rn) */\r
-INLINE void MOVBS0(UINT32 m, UINT32 n)\r
+INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n] + sh2->r[0];\r
- WB( sh2->ea, sh2->r[m] & 0x000000ff );\r
+ WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );\r
}\r
\r
/* MOV.W Rm,@(R0,Rn) */\r
-INLINE void MOVWS0(UINT32 m, UINT32 n)\r
+INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n] + sh2->r[0];\r
- WW( sh2->ea, sh2->r[m] & 0x0000ffff );\r
+ WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );\r
}\r
\r
/* MOV.L Rm,@(R0,Rn) */\r
-INLINE void MOVLS0(UINT32 m, UINT32 n)\r
+INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[n] + sh2->r[0];\r
- WL( sh2->ea, sh2->r[m] );\r
+ WL( sh2, sh2->ea, sh2->r[m] );\r
}\r
\r
/* MOV.B @(R0,Rm),Rn */\r
-INLINE void MOVBL0(UINT32 m, UINT32 n)\r
+INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m] + sh2->r[0];\r
- sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
}\r
\r
/* MOV.W @(R0,Rm),Rn */\r
-INLINE void MOVWL0(UINT32 m, UINT32 n)\r
+INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m] + sh2->r[0];\r
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
}\r
\r
/* MOV.L @(R0,Rm),Rn */\r
-INLINE void MOVLL0(UINT32 m, UINT32 n)\r
+INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->ea = sh2->r[m] + sh2->r[0];\r
- sh2->r[n] = RL( sh2->ea );\r
+ sh2->r[n] = RL( sh2, sh2->ea );\r
}\r
\r
/* MOV #imm,Rn */\r
-INLINE void MOVI(UINT32 i, UINT32 n)\r
+INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)\r
{\r
sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;\r
}\r
\r
/* MOV.W @(disp8,PC),Rn */\r
-INLINE void MOVWI(UINT32 d, UINT32 n)\r
+INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->pc + disp * 2 + 2;\r
- sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r
+ sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
}\r
\r
/* MOV.L @(disp8,PC),Rn */\r
-INLINE void MOVLI(UINT32 d, UINT32 n)\r
+INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
- sh2->r[n] = RL( sh2->ea );\r
+ sh2->r[n] = RL( sh2, sh2->ea );\r
}\r
\r
/* MOV.B @(disp8,GBR),R0 */\r
-INLINE void MOVBLG(UINT32 d)\r
+INLINE void MOVBLG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp;\r
- sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r
+ sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
}\r
\r
/* MOV.W @(disp8,GBR),R0 */\r
-INLINE void MOVWLG(UINT32 d)\r
+INLINE void MOVWLG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp * 2;\r
- sh2->r[0] = (INT32)(INT16) RW( sh2->ea );\r
+ sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );\r
}\r
\r
/* MOV.L @(disp8,GBR),R0 */\r
-INLINE void MOVLLG(UINT32 d)\r
+INLINE void MOVLLG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp * 4;\r
- sh2->r[0] = RL( sh2->ea );\r
+ sh2->r[0] = RL( sh2, sh2->ea );\r
}\r
\r
/* MOV.B R0,@(disp8,GBR) */\r
-INLINE void MOVBSG(UINT32 d)\r
+INLINE void MOVBSG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp;\r
- WB( sh2->ea, sh2->r[0] & 0x000000ff );\r
+ WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
}\r
\r
/* MOV.W R0,@(disp8,GBR) */\r
-INLINE void MOVWSG(UINT32 d)\r
+INLINE void MOVWSG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp * 2;\r
- WW( sh2->ea, sh2->r[0] & 0x0000ffff );\r
+ WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
}\r
\r
/* MOV.L R0,@(disp8,GBR) */\r
-INLINE void MOVLSG(UINT32 d)\r
+INLINE void MOVLSG(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = sh2->gbr + disp * 4;\r
- WL( sh2->ea, sh2->r[0] );\r
+ WL( sh2, sh2->ea, sh2->r[0] );\r
}\r
\r
/* MOV.B R0,@(disp4,Rn) */\r
-INLINE void MOVBS4(UINT32 d, UINT32 n)\r
+INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[n] + disp;\r
- WB( sh2->ea, sh2->r[0] & 0x000000ff );\r
+ WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
}\r
\r
/* MOV.W R0,@(disp4,Rn) */\r
-INLINE void MOVWS4(UINT32 d, UINT32 n)\r
+INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[n] + disp * 2;\r
- WW( sh2->ea, sh2->r[0] & 0x0000ffff );\r
+ WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
}\r
\r
/* MOV.L Rm,@(disp4,Rn) */\r
-INLINE void MOVLS4(UINT32 m, UINT32 d, UINT32 n)\r
+INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[n] + disp * 4;\r
- WL( sh2->ea, sh2->r[m] );\r
+ WL( sh2, sh2->ea, sh2->r[m] );\r
}\r
\r
/* MOV.B @(disp4,Rm),R0 */\r
-INLINE void MOVBL4(UINT32 m, UINT32 d)\r
+INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[m] + disp;\r
- sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );\r
+ sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
}\r
\r
/* MOV.W @(disp4,Rm),R0 */\r
-INLINE void MOVWL4(UINT32 m, UINT32 d)\r
+INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[m] + disp * 2;\r
- sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2->ea );\r
+ sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
}\r
\r
/* MOV.L @(disp4,Rm),Rn */\r
-INLINE void MOVLL4(UINT32 m, UINT32 d, UINT32 n)\r
+INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
{\r
UINT32 disp = d & 0x0f;\r
sh2->ea = sh2->r[m] + disp * 4;\r
- sh2->r[n] = RL( sh2->ea );\r
+ sh2->r[n] = RL( sh2, sh2->ea );\r
}\r
\r
/* MOVA @(disp8,PC),R0 */\r
-INLINE void MOVA(UINT32 d)\r
+INLINE void MOVA(sh2_state *sh2, UINT32 d)\r
{\r
UINT32 disp = d & 0xff;\r
sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
}\r
\r
/* MOVT Rn */\r
-INLINE void MOVT(UINT32 n)\r
+INLINE void MOVT(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->sr & T;\r
}\r
\r
/* MUL.L Rm,Rn */\r
-INLINE void MULL(UINT32 m, UINT32 n)\r
+INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->macl = sh2->r[n] * sh2->r[m];\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* MULS Rm,Rn */\r
-INLINE void MULS(UINT32 m, UINT32 n)\r
+INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];\r
}\r
\r
/* MULU Rm,Rn */\r
-INLINE void MULU(UINT32 m, UINT32 n)\r
+INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];\r
}\r
\r
/* NEG Rm,Rn */\r
-INLINE void NEG(UINT32 m, UINT32 n)\r
+INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = 0 - sh2->r[m];\r
}\r
\r
/* NEGC Rm,Rn */\r
-INLINE void NEGC(UINT32 m, UINT32 n)\r
+INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 temp;\r
\r
}\r
\r
/* NOT Rm,Rn */\r
-INLINE void NOT(UINT32 m, UINT32 n)\r
+INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] = ~sh2->r[m];\r
}\r
\r
/* OR Rm,Rn */\r
-INLINE void OR(UINT32 m, UINT32 n)\r
+INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] |= sh2->r[m];\r
}\r
\r
/* OR #imm,R0 */\r
-INLINE void ORI(UINT32 i)\r
+INLINE void ORI(sh2_state *sh2, UINT32 i)\r
{\r
sh2->r[0] |= i;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
\r
/* OR.B #imm,@(R0,GBR) */\r
-INLINE void ORM(UINT32 i)\r
+INLINE void ORM(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 temp;\r
\r
sh2->ea = sh2->gbr + sh2->r[0];\r
- temp = RB( sh2->ea );\r
+ temp = RB( sh2, sh2->ea );\r
temp |= i;\r
- WB( sh2->ea, temp );\r
+ WB( sh2, sh2->ea, temp );\r
}\r
\r
/* ROTCL Rn */\r
-INLINE void ROTCL(UINT32 n)\r
+INLINE void ROTCL(sh2_state *sh2, UINT32 n)\r
{\r
UINT32 temp;\r
\r
}\r
\r
/* ROTCR Rn */\r
-INLINE void ROTCR(UINT32 n)\r
+INLINE void ROTCR(sh2_state *sh2, UINT32 n)\r
{\r
UINT32 temp;\r
temp = (sh2->sr & T) << 31;\r
}\r
\r
/* ROTL Rn */\r
-INLINE void ROTL(UINT32 n)\r
+INLINE void ROTL(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);\r
}\r
\r
/* ROTR Rn */\r
-INLINE void ROTR(UINT32 n)\r
+INLINE void ROTR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);\r
}\r
\r
/* RTE */\r
-INLINE void RTE(void)\r
+INLINE void RTE(sh2_state *sh2)\r
{\r
sh2->ea = sh2->r[15];\r
sh2->delay = sh2->pc;\r
- sh2->pc = RL( sh2->ea );\r
+ sh2->pc = RL( sh2, sh2->ea );\r
sh2->r[15] += 4;\r
sh2->ea = sh2->r[15];\r
- sh2->sr &= ~0xfff;\r
- sh2->sr |= RL( sh2->ea ) & FLAGS;\r
+ sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
sh2->r[15] += 4;\r
- sh2_icount -= 3;\r
+ sh2->icount -= 3;\r
sh2->test_irq = 1;\r
}\r
\r
/* RTS */\r
-INLINE void RTS(void)\r
+INLINE void RTS(sh2_state *sh2)\r
{\r
sh2->delay = sh2->pc;\r
sh2->pc = sh2->ea = sh2->pr;\r
- sh2_icount--;\r
+ sh2->icount--;\r
}\r
\r
/* SETT */\r
-INLINE void SETT(void)\r
+INLINE void SETT(sh2_state *sh2)\r
{\r
sh2->sr |= T;\r
}\r
\r
/* SHAL Rn (same as SHLL) */\r
-INLINE void SHAL(UINT32 n)\r
+INLINE void SHAL(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
sh2->r[n] <<= 1;\r
}\r
\r
/* SHAR Rn */\r
-INLINE void SHAR(UINT32 n)\r
+INLINE void SHAR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);\r
}\r
\r
/* SHLL Rn (same as SHAL) */\r
-INLINE void SHLL(UINT32 n)\r
+INLINE void SHLL(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
sh2->r[n] <<= 1;\r
}\r
\r
/* SHLL2 Rn */\r
-INLINE void SHLL2(UINT32 n)\r
+INLINE void SHLL2(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] <<= 2;\r
}\r
\r
/* SHLL8 Rn */\r
-INLINE void SHLL8(UINT32 n)\r
+INLINE void SHLL8(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] <<= 8;\r
}\r
\r
/* SHLL16 Rn */\r
-INLINE void SHLL16(UINT32 n)\r
+INLINE void SHLL16(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] <<= 16;\r
}\r
\r
/* SHLR Rn */\r
-INLINE void SHLR(UINT32 n)\r
+INLINE void SHLR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
sh2->r[n] >>= 1;\r
}\r
\r
/* SHLR2 Rn */\r
-INLINE void SHLR2(UINT32 n)\r
+INLINE void SHLR2(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] >>= 2;\r
}\r
\r
/* SHLR8 Rn */\r
-INLINE void SHLR8(UINT32 n)\r
+INLINE void SHLR8(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] >>= 8;\r
}\r
\r
/* SHLR16 Rn */\r
-INLINE void SHLR16(UINT32 n)\r
+INLINE void SHLR16(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] >>= 16;\r
}\r
\r
/* SLEEP */\r
-INLINE void SLEEP(void)\r
+INLINE void SLEEP(sh2_state *sh2)\r
{\r
- sh2->pc -= 2;\r
- sh2_icount -= 2;\r
+ //if(sh2->sleep_mode != 2)\r
+ sh2->pc -= 2;\r
+ sh2->icount -= 2;\r
/* Wait_for_exception; */\r
+ /*if(sh2->sleep_mode == 0)\r
+ sh2->sleep_mode = 1;\r
+ else if(sh2->sleep_mode == 2)\r
+ sh2->sleep_mode = 0;*/\r
}\r
\r
/* STC SR,Rn */\r
-INLINE void STCSR(UINT32 n)\r
+INLINE void STCSR(sh2_state *sh2, UINT32 n)\r
{\r
- sh2->r[n] = sh2->sr & FLAGS;\r
+ sh2->r[n] = sh2->sr;\r
}\r
\r
/* STC GBR,Rn */\r
-INLINE void STCGBR(UINT32 n)\r
+INLINE void STCGBR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->gbr;\r
}\r
\r
/* STC VBR,Rn */\r
-INLINE void STCVBR(UINT32 n)\r
+INLINE void STCVBR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->vbr;\r
}\r
\r
/* STC.L SR,@-Rn */\r
-INLINE void STCMSR(UINT32 n)\r
+INLINE void STCMSR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->sr & FLAGS );\r
- sh2_icount--;\r
+ WL( sh2, sh2->ea, sh2->sr );\r
+ sh2->icount--;\r
}\r
\r
/* STC.L GBR,@-Rn */\r
-INLINE void STCMGBR(UINT32 n)\r
+INLINE void STCMGBR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->gbr );\r
- sh2_icount--;\r
+ WL( sh2, sh2->ea, sh2->gbr );\r
+ sh2->icount--;\r
}\r
\r
/* STC.L VBR,@-Rn */\r
-INLINE void STCMVBR(UINT32 n)\r
+INLINE void STCMVBR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->vbr );\r
- sh2_icount--;\r
+ WL( sh2, sh2->ea, sh2->vbr );\r
+ sh2->icount--;\r
}\r
\r
/* STS MACH,Rn */\r
-INLINE void STSMACH(UINT32 n)\r
+INLINE void STSMACH(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->mach;\r
}\r
\r
/* STS MACL,Rn */\r
-INLINE void STSMACL(UINT32 n)\r
+INLINE void STSMACL(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->macl;\r
}\r
\r
/* STS PR,Rn */\r
-INLINE void STSPR(UINT32 n)\r
+INLINE void STSPR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] = sh2->pr;\r
}\r
\r
/* STS.L MACH,@-Rn */\r
-INLINE void STSMMACH(UINT32 n)\r
+INLINE void STSMMACH(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->mach );\r
+ WL( sh2, sh2->ea, sh2->mach );\r
}\r
\r
/* STS.L MACL,@-Rn */\r
-INLINE void STSMMACL(UINT32 n)\r
+INLINE void STSMMACL(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->macl );\r
+ WL( sh2, sh2->ea, sh2->macl );\r
}\r
\r
/* STS.L PR,@-Rn */\r
-INLINE void STSMPR(UINT32 n)\r
+INLINE void STSMPR(sh2_state *sh2, UINT32 n)\r
{\r
sh2->r[n] -= 4;\r
sh2->ea = sh2->r[n];\r
- WL( sh2->ea, sh2->pr );\r
+ WL( sh2, sh2->ea, sh2->pr );\r
}\r
\r
/* SUB Rm,Rn */\r
-INLINE void SUB(UINT32 m, UINT32 n)\r
+INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] -= sh2->r[m];\r
}\r
\r
/* SUBC Rm,Rn */\r
-INLINE void SUBC(UINT32 m, UINT32 n)\r
+INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 tmp0, tmp1;\r
\r
}\r
\r
/* SUBV Rm,Rn */\r
-INLINE void SUBV(UINT32 m, UINT32 n)\r
+INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
INT32 dest, src, ans;\r
\r
}\r
\r
/* SWAP.B Rm,Rn */\r
-INLINE void SWAPB(UINT32 m, UINT32 n)\r
+INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 temp0, temp1;\r
\r
}\r
\r
/* SWAP.W Rm,Rn */\r
-INLINE void SWAPW(UINT32 m, UINT32 n)\r
+INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 temp;\r
\r
}\r
\r
/* TAS.B @Rn */\r
-INLINE void TAS(UINT32 n)\r
+INLINE void TAS(sh2_state *sh2, UINT32 n)\r
{\r
UINT32 temp;\r
sh2->ea = sh2->r[n];\r
/* Bus Lock enable */\r
- temp = RB( sh2->ea );\r
+ temp = RB( sh2, sh2->ea );\r
if (temp == 0)\r
sh2->sr |= T;\r
else\r
sh2->sr &= ~T;\r
temp |= 0x80;\r
/* Bus Lock disable */\r
- WB( sh2->ea, temp );\r
- sh2_icount -= 3;\r
+ WB( sh2, sh2->ea, temp );\r
+ sh2->icount -= 3;\r
}\r
\r
/* TRAPA #imm */\r
-INLINE void TRAPA(UINT32 i)\r
+INLINE void TRAPA(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = i & 0xff;\r
\r
sh2->ea = sh2->vbr + imm * 4;\r
\r
sh2->r[15] -= 4;\r
- WL( sh2->r[15], sh2->sr & FLAGS );\r
+ WL( sh2, sh2->r[15], sh2->sr );\r
sh2->r[15] -= 4;\r
- WL( sh2->r[15], sh2->pc );\r
+ WL( sh2, sh2->r[15], sh2->pc );\r
\r
- sh2->pc = RL( sh2->ea );\r
+ sh2->pc = RL( sh2, sh2->ea );\r
\r
- sh2_icount -= 7;\r
+ sh2->icount -= 7;\r
}\r
\r
/* TST Rm,Rn */\r
-INLINE void TST(UINT32 m, UINT32 n)\r
+INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
if ((sh2->r[n] & sh2->r[m]) == 0)\r
sh2->sr |= T;\r
}\r
\r
/* TST #imm,R0 */\r
-INLINE void TSTI(UINT32 i)\r
+INLINE void TSTI(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = i & 0xff;\r
\r
}\r
\r
/* TST.B #imm,@(R0,GBR) */\r
-INLINE void TSTM(UINT32 i)\r
+INLINE void TSTM(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = i & 0xff;\r
\r
sh2->ea = sh2->gbr + sh2->r[0];\r
- if ((imm & RB( sh2->ea )) == 0)\r
+ if ((imm & RB( sh2, sh2->ea )) == 0)\r
sh2->sr |= T;\r
else\r
sh2->sr &= ~T;\r
- sh2_icount -= 2;\r
+ sh2->icount -= 2;\r
}\r
\r
/* XOR Rm,Rn */\r
-INLINE void XOR(UINT32 m, UINT32 n)\r
+INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
sh2->r[n] ^= sh2->r[m];\r
}\r
\r
/* XOR #imm,R0 */\r
-INLINE void XORI(UINT32 i)\r
+INLINE void XORI(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = i & 0xff;\r
sh2->r[0] ^= imm;\r
}\r
\r
/* XOR.B #imm,@(R0,GBR) */\r
-INLINE void XORM(UINT32 i)\r
+INLINE void XORM(sh2_state *sh2, UINT32 i)\r
{\r
UINT32 imm = i & 0xff;\r
UINT32 temp;\r
\r
sh2->ea = sh2->gbr + sh2->r[0];\r
- temp = RB( sh2->ea );\r
+ temp = RB( sh2, sh2->ea );\r
temp ^= imm;\r
- WB( sh2->ea, temp );\r
- sh2_icount -= 2;\r
+ WB( sh2, sh2->ea, temp );\r
+ sh2->icount -= 2;\r
}\r
\r
/* XTRCT Rm,Rn */\r
-INLINE void XTRCT(UINT32 m, UINT32 n)\r
+INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)\r
{\r
UINT32 temp;\r
\r
* OPCODE DISPATCHERS\r
*****************************************************************************/\r
\r
-INLINE void op0000(UINT16 opcode)\r
+INLINE void op0000(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & 0x3F)\r
{\r
- case 0x00: NOP(); rlog(0); break;\r
- case 0x01: NOP(); rlog(0); break;\r
- case 0x02: STCSR(Rn); rlog(LRN); break;\r
- case 0x03: BSRF(Rn); rlog(LRN); break;\r
- case 0x04: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x05: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x06: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x07: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
- case 0x08: CLRT(); rlog(0); break;\r
+ case 0x00: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x01: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x02: STCSR(sh2, Rn); rlog(LRN); break;\r
+ case 0x03: BSRF(sh2, Rn); rlog(LRN); break;\r
+ case 0x04: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x05: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x06: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x07: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 0x08: CLRT(sh2); rlog(0); break;\r
case 0x09: NOP(); rlog(0); break;\r
- case 0x0a: STSMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
- case 0x0b: RTS(); rlog(0); rlog1(SHR_PR); break;\r
- case 0x0c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x0d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x0e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x0f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
-\r
- case 0x10: NOP(); rlog(0); break;\r
- case 0x11: NOP(); rlog(0); break;\r
- case 0x12: STCGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
- case 0x13: NOP(); rlog(0); break;\r
- case 0x14: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x15: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x16: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x17: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
- case 0x18: SETT(); rlog(0); break;\r
- case 0x19: DIV0U(); rlog(0); break;\r
- case 0x1a: STSMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
- case 0x1b: SLEEP(); rlog(0); break;\r
- case 0x1c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x1d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x1e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x1f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
-\r
- case 0x20: NOP(); rlog(0); break;\r
- case 0x21: NOP(); rlog(0); break;\r
- case 0x22: STCVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
- case 0x23: BRAF(Rn); rlog(LRN); break;\r
- case 0x24: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x25: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x26: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x27: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
- case 0x28: CLRMAC(); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;\r
- case 0x29: MOVT(Rn); rlog(LRN); break;\r
- case 0x2a: STSPR(Rn); rlog(LRN); rlog1(SHR_PR); break;\r
- case 0x2b: RTE(); rlog(0); break;\r
- case 0x2c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x2d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x2e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x2f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
-\r
- case 0x30: NOP(); rlog(0); break;\r
- case 0x31: NOP(); rlog(0); break;\r
- case 0x32: NOP(); rlog(0); break;\r
- case 0x33: NOP(); rlog(0); break;\r
- case 0x34: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x35: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x36: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x37: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
- case 0x38: NOP(); rlog(0); break;\r
- case 0x39: NOP(); rlog(0); break;\r
- case 0x3c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x3d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x3e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;\r
- case 0x3f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
- case 0x3a: NOP(); rlog(0); break;\r
- case 0x3b: NOP(); rlog(0); break;\r
+ case 0x0a: STSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
+ case 0x0b: RTS(sh2); rlog(0); rlog1(SHR_PR); break;\r
+ case 0x0c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x0d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x0e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x0f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+\r
+ case 0x10: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x11: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x12: STCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
+ case 0x13: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x14: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x15: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x16: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x17: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 0x18: SETT(sh2); rlog(0); break;\r
+ case 0x19: DIV0U(sh2); rlog(0); break;\r
+ case 0x1a: STSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
+ case 0x1b: SLEEP(sh2); rlog(0); break;\r
+ case 0x1c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x1d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x1e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x1f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+\r
+ case 0x20: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x21: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x22: STCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
+ case 0x23: BRAF(sh2, Rn); rlog(LRN); break;\r
+ case 0x24: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x25: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x26: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x27: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 0x28: CLRMAC(sh2); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 0x29: MOVT(sh2, Rn); rlog(LRN); break;\r
+ case 0x2a: STSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
+ case 0x2b: RTE(sh2); rlog(0); break;\r
+ case 0x2c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x2d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x2e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x2f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+\r
+ case 0x30: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x31: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x32: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x33: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x34: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x35: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x36: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x37: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 0x38: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x39: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x3c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x3d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x3e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
+ case 0x3f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 0x3a: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x3b: ILLEGAL(sh2); rlog(0); break;\r
}\r
}\r
\r
-INLINE void op0001(UINT16 opcode)\r
+INLINE void op0001(sh2_state *sh2, UINT16 opcode)\r
{\r
- MOVLS4(Rm, opcode & 0x0f, Rn);\r
+ MOVLS4(sh2, Rm, opcode & 0x0f, Rn);\r
rlog(LRNM);\r
}\r
\r
-INLINE void op0010(UINT16 opcode)\r
+INLINE void op0010(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & 15)\r
{\r
- case 0: MOVBS(Rm, Rn); rlog(LRNM); break;\r
- case 1: MOVWS(Rm, Rn); rlog(LRNM); break;\r
- case 2: MOVLS(Rm, Rn); rlog(LRNM); break;\r
- case 3: NOP(); rlog(0); break;\r
- case 4: MOVBM(Rm, Rn); rlog(LRNM); break;\r
- case 5: MOVWM(Rm, Rn); rlog(LRNM); break;\r
- case 6: MOVLM(Rm, Rn); rlog(LRNM); break;\r
- case 7: DIV0S(Rm, Rn); rlog(LRNM); break;\r
- case 8: TST(Rm, Rn); rlog(LRNM); break;\r
- case 9: AND(Rm, Rn); rlog(LRNM); break;\r
- case 10: XOR(Rm, Rn); rlog(LRNM); break;\r
- case 11: OR(Rm, Rn); rlog(LRNM); break;\r
- case 12: CMPSTR(Rm, Rn); rlog(LRNM); break;\r
- case 13: XTRCT(Rm, Rn); rlog(LRNM); break;\r
- case 14: MULU(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
- case 15: MULS(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 0: MOVBS(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 1: MOVWS(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 2: MOVLS(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 3: ILLEGAL(sh2); rlog(0); break;\r
+ case 4: MOVBM(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 5: MOVWM(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 6: MOVLM(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 7: DIV0S(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 8: TST(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 9: AND(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 10: XOR(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 11: OR(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 12: CMPSTR(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 13: XTRCT(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 14: MULU(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
+ case 15: MULS(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
}\r
}\r
\r
-INLINE void op0011(UINT16 opcode)\r
+INLINE void op0011(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & 15)\r
{\r
- case 0: CMPEQ(Rm, Rn); rlog(LRNM); break;\r
- case 1: NOP(); rlog(0); break;\r
- case 2: CMPHS(Rm, Rn); rlog(LRNM); break;\r
- case 3: CMPGE(Rm, Rn); rlog(LRNM); break;\r
- case 4: DIV1(Rm, Rn); rlog(LRNM); break;\r
- case 5: DMULU(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
- case 6: CMPHI(Rm, Rn); rlog(LRNM); break;\r
- case 7: CMPGT(Rm, Rn); rlog(LRNM); break;\r
- case 8: SUB(Rm, Rn); rlog(LRNM); break;\r
- case 9: NOP(); rlog(0); break;\r
- case 10: SUBC(Rm, Rn); rlog(LRNM); break;\r
- case 11: SUBV(Rm, Rn); rlog(LRNM); break;\r
- case 12: ADD(Rm, Rn); rlog(LRNM); break;\r
- case 13: DMULS(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
- case 14: ADDC(Rm, Rn); rlog(LRNM); break;\r
- case 15: ADDV(Rm, Rn); rlog(LRNM); break;\r
+ case 0: CMPEQ(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 1: ILLEGAL(sh2); rlog(0); break;\r
+ case 2: CMPHS(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 3: CMPGE(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 4: DIV1(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 5: DMULU(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 6: CMPHI(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 7: CMPGT(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 8: SUB(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 9: ILLEGAL(sh2); rlog(0); break;\r
+ case 10: SUBC(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 11: SUBV(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 12: ADD(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 13: DMULS(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 14: ADDC(sh2, Rm, Rn); rlog(LRNM); break;\r
+ case 15: ADDV(sh2, Rm, Rn); rlog(LRNM); break;\r
}\r
}\r
\r
-INLINE void op0100(UINT16 opcode)\r
+INLINE void op0100(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & 0x3F)\r
{\r
- case 0x00: SHLL(Rn); rlog(LRN); break;\r
- case 0x01: SHLR(Rn); rlog(LRN); break;\r
- case 0x02: STSMMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
- case 0x03: STCMSR(Rn); rlog(LRN); break;\r
- case 0x04: ROTL(Rn); rlog(LRN); break;\r
- case 0x05: ROTR(Rn); rlog(LRN); break;\r
- case 0x06: LDSMMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
- case 0x07: LDCMSR(Rn); rlog(LRN); break;\r
- case 0x08: SHLL2(Rn); rlog(LRN); break;\r
- case 0x09: SHLR2(Rn); rlog(LRN); break;\r
- case 0x0a: LDSMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
- case 0x0b: JSR(Rn); rlog(LRN); rlog1(SHR_PR); break;\r
- case 0x0c: NOP(); rlog(0); break;\r
- case 0x0d: NOP(); rlog(0); break;\r
- case 0x0e: LDCSR(Rn); rlog(LRN); break;\r
- case 0x0f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
-\r
- case 0x10: DT(Rn); rlog(LRN); break;\r
- case 0x11: CMPPZ(Rn); rlog(LRN); break;\r
- case 0x12: STSMMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
- case 0x13: STCMGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
- case 0x14: NOP(); rlog(0); break;\r
- case 0x15: CMPPL(Rn); rlog(LRN); break;\r
- case 0x16: LDSMMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
- case 0x17: LDCMGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
- case 0x18: SHLL8(Rn); rlog(LRN); break;\r
- case 0x19: SHLR8(Rn); rlog(LRN); break;\r
- case 0x1a: LDSMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
- case 0x1b: TAS(Rn); rlog(LRN); break;\r
- case 0x1c: NOP(); rlog(0); break;\r
- case 0x1d: NOP(); rlog(0); break;\r
- case 0x1e: LDCGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
- case 0x1f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
-\r
- case 0x20: SHAL(Rn); rlog(LRN); break;\r
- case 0x21: SHAR(Rn); rlog(LRN); break;\r
- case 0x22: STSMPR(Rn); rlog(LRN); rlog1(SHR_PR); break;\r
- case 0x23: STCMVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
- case 0x24: ROTCL(Rn); rlog(LRN); break;\r
- case 0x25: ROTCR(Rn); rlog(LRN); break;\r
- case 0x26: LDSMPR(Rn); rlog(LRN); rlog1(SHR_PR); break;\r
- case 0x27: LDCMVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
- case 0x28: SHLL16(Rn); rlog(LRN); break;\r
- case 0x29: SHLR16(Rn); rlog(LRN); break;\r
- case 0x2a: LDSPR(Rn); rlog(LRN); rlog1(SHR_PR); break;\r
- case 0x2b: JMP(Rn); rlog(LRN); break;\r
- case 0x2c: NOP(); rlog(0); break;\r
- case 0x2d: NOP(); rlog(0); break;\r
- case 0x2e: LDCVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
- case 0x2f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 0x00: SHLL(sh2, Rn); rlog(LRN); break;\r
+ case 0x01: SHLR(sh2, Rn); rlog(LRN); break;\r
+ case 0x02: STSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
+ case 0x03: STCMSR(sh2, Rn); rlog(LRN); break;\r
+ case 0x04: ROTL(sh2, Rn); rlog(LRN); break;\r
+ case 0x05: ROTR(sh2, Rn); rlog(LRN); break;\r
+ case 0x06: LDSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
+ case 0x07: LDCMSR(sh2, Rn); rlog(LRN); break;\r
+ case 0x08: SHLL2(sh2, Rn); rlog(LRN); break;\r
+ case 0x09: SHLR2(sh2, Rn); rlog(LRN); break;\r
+ case 0x0a: LDSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
+ case 0x0b: JSR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
+ case 0x0c: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x0d: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x0e: LDCSR(sh2, Rn); rlog(LRN); break;\r
+ case 0x0f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+\r
+ case 0x10: DT(sh2, Rn); rlog(LRN); break;\r
+ case 0x11: CMPPZ(sh2, Rn); rlog(LRN); break;\r
+ case 0x12: STSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
+ case 0x13: STCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
+ case 0x14: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x15: CMPPL(sh2, Rn); rlog(LRN); break;\r
+ case 0x16: LDSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
+ case 0x17: LDCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
+ case 0x18: SHLL8(sh2, Rn); rlog(LRN); break;\r
+ case 0x19: SHLR8(sh2, Rn); rlog(LRN); break;\r
+ case 0x1a: LDSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
+ case 0x1b: TAS(sh2, Rn); rlog(LRN); break;\r
+ case 0x1c: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x1d: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x1e: LDCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
+ case 0x1f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+\r
+ case 0x20: SHAL(sh2, Rn); rlog(LRN); break;\r
+ case 0x21: SHAR(sh2, Rn); rlog(LRN); break;\r
+ case 0x22: STSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
+ case 0x23: STCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
+ case 0x24: ROTCL(sh2, Rn); rlog(LRN); break;\r
+ case 0x25: ROTCR(sh2, Rn); rlog(LRN); break;\r
+ case 0x26: LDSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
+ case 0x27: LDCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
+ case 0x28: SHLL16(sh2, Rn); rlog(LRN); break;\r
+ case 0x29: SHLR16(sh2, Rn); rlog(LRN); break;\r
+ case 0x2a: LDSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
+ case 0x2b: JMP(sh2, Rn); rlog(LRN); break;\r
+ case 0x2c: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x2d: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x2e: LDCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
+ case 0x2f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
\r
case 0x30:\r
case 0x31:\r
case 0x3b:\r
case 0x3c:\r
case 0x3d:\r
- case 0x3e: NOP(); rlog(0); break;\r
- case 0x3f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
+ case 0x3e: ILLEGAL(sh2); rlog(0); break;\r
+ case 0x3f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
}\r
}\r
\r
-INLINE void op0101(UINT16 opcode)\r
+INLINE void op0101(sh2_state *sh2, UINT16 opcode)\r
{\r
- MOVLL4(Rm, opcode & 0x0f, Rn);\r
+ MOVLL4(sh2, Rm, opcode & 0x0f, Rn);\r
rlog(LRNM);\r
}\r
\r
-INLINE void op0110(UINT16 opcode)\r
+INLINE void op0110(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & 15)\r
{\r
- case 0: MOVBL(Rm, Rn); break;\r
- case 1: MOVWL(Rm, Rn); break;\r
- case 2: MOVLL(Rm, Rn); break;\r
- case 3: MOV(Rm, Rn); break;\r
- case 4: MOVBP(Rm, Rn); break;\r
- case 5: MOVWP(Rm, Rn); break;\r
- case 6: MOVLP(Rm, Rn); break;\r
- case 7: NOT(Rm, Rn); break;\r
- case 8: SWAPB(Rm, Rn); break;\r
- case 9: SWAPW(Rm, Rn); break;\r
- case 10: NEGC(Rm, Rn); break;\r
- case 11: NEG(Rm, Rn); break;\r
- case 12: EXTUB(Rm, Rn); break;\r
- case 13: EXTUW(Rm, Rn); break;\r
- case 14: EXTSB(Rm, Rn); break;\r
- case 15: EXTSW(Rm, Rn); break;\r
+ case 0: MOVBL(sh2, Rm, Rn); break;\r
+ case 1: MOVWL(sh2, Rm, Rn); break;\r
+ case 2: MOVLL(sh2, Rm, Rn); break;\r
+ case 3: MOV(sh2, Rm, Rn); break;\r
+ case 4: MOVBP(sh2, Rm, Rn); break;\r
+ case 5: MOVWP(sh2, Rm, Rn); break;\r
+ case 6: MOVLP(sh2, Rm, Rn); break;\r
+ case 7: NOT(sh2, Rm, Rn); break;\r
+ case 8: SWAPB(sh2, Rm, Rn); break;\r
+ case 9: SWAPW(sh2, Rm, Rn); break;\r
+ case 10: NEGC(sh2, Rm, Rn); break;\r
+ case 11: NEG(sh2, Rm, Rn); break;\r
+ case 12: EXTUB(sh2, Rm, Rn); break;\r
+ case 13: EXTUW(sh2, Rm, Rn); break;\r
+ case 14: EXTSB(sh2, Rm, Rn); break;\r
+ case 15: EXTSW(sh2, Rm, Rn); break;\r
}\r
rlog(LRNM);\r
}\r
\r
-INLINE void op0111(UINT16 opcode)\r
+INLINE void op0111(sh2_state *sh2, UINT16 opcode)\r
{\r
- ADDI(opcode & 0xff, Rn);\r
+ ADDI(sh2, opcode & 0xff, Rn);\r
rlog(LRN);\r
}\r
\r
-INLINE void op1000(UINT16 opcode)\r
+INLINE void op1000(sh2_state *sh2, UINT16 opcode)\r
{\r
switch ( opcode & (15<<8) )\r
{\r
- case 0<< 8: MOVBS4(opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
- case 1<< 8: MOVWS4(opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
- case 2<< 8: NOP(); rlog(0); break;\r
- case 3<< 8: NOP(); rlog(0); break;\r
- case 4<< 8: MOVBL4(Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
- case 5<< 8: MOVWL4(Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
- case 6<< 8: NOP(); rlog(0); break;\r
- case 7<< 8: NOP(); rlog(0); break;\r
- case 8<< 8: CMPIM(opcode & 0xff); rlog(0); rlog1(0); break;\r
- case 9<< 8: BT(opcode & 0xff); rlog(0); break;\r
- case 10<< 8: NOP(); rlog(0); break;\r
- case 11<< 8: BF(opcode & 0xff); rlog(0); break;\r
- case 12<< 8: NOP(); rlog(0); break;\r
- case 13<< 8: BTS(opcode & 0xff); rlog(0); break;\r
- case 14<< 8: NOP(); rlog(0); break;\r
- case 15<< 8: BFS(opcode & 0xff); rlog(0); break;\r
+ case 0<< 8: MOVBS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
+ case 1<< 8: MOVWS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
+ case 2<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 3<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
+ case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
+ case 6<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 7<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 8<< 8: CMPIM(sh2, opcode & 0xff); rlog(0); rlog1(0); break;\r
+ case 9<< 8: BT(sh2, opcode & 0xff); rlog(0); break;\r
+ case 10<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 11<< 8: BF(sh2, opcode & 0xff); rlog(0); break;\r
+ case 12<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 13<< 8: BTS(sh2, opcode & 0xff); rlog(0); break;\r
+ case 14<< 8: ILLEGAL(sh2); rlog(0); break;\r
+ case 15<< 8: BFS(sh2, opcode & 0xff); rlog(0); break;\r
}\r
}\r
\r
\r
-INLINE void op1001(UINT16 opcode)\r
+INLINE void op1001(sh2_state *sh2, UINT16 opcode)\r
{\r
- MOVWI(opcode & 0xff, Rn);\r
+ MOVWI(sh2, opcode & 0xff, Rn);\r
rlog(LRN);\r
}\r
\r
-INLINE void op1010(UINT16 opcode)\r
+INLINE void op1010(sh2_state *sh2, UINT16 opcode)\r
{\r
- BRA(opcode & 0xfff);\r
+ BRA(sh2, opcode & 0xfff);\r
rlog(0);\r
}\r
\r
-INLINE void op1011(UINT16 opcode)\r
+INLINE void op1011(sh2_state *sh2, UINT16 opcode)\r
{\r
- BSR(opcode & 0xfff);\r
+ BSR(sh2, opcode & 0xfff);\r
rlog(0);\r
rlog1(SHR_PR);\r
}\r
\r
-INLINE void op1100(UINT16 opcode)\r
+INLINE void op1100(sh2_state *sh2, UINT16 opcode)\r
{\r
switch (opcode & (15<<8))\r
{\r
- case 0<<8: MOVBSG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 1<<8: MOVWSG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 2<<8: MOVLSG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 3<<8: TRAPA(opcode & 0xff); rlog1(SHR_VBR); break;\r
- case 4<<8: MOVBLG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 5<<8: MOVWLG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 6<<8: MOVLLG(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 7<<8: MOVA(opcode & 0xff); rlog1(0); break;\r
- case 8<<8: TSTI(opcode & 0xff); rlog1(0); break;\r
- case 9<<8: ANDI(opcode & 0xff); rlog1(0); break;\r
- case 10<<8: XORI(opcode & 0xff); rlog1(0); break;\r
- case 11<<8: ORI(opcode & 0xff); rlog1(0); break;\r
- case 12<<8: TSTM(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 13<<8: ANDM(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 14<<8: XORM(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
- case 15<<8: ORM(opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 0<<8: MOVBSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 1<<8: MOVWSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 2<<8: MOVLSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 3<<8: TRAPA(sh2, opcode & 0xff); rlog1(SHR_VBR); break;\r
+ case 4<<8: MOVBLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 5<<8: MOVWLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 6<<8: MOVLLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 7<<8: MOVA(sh2, opcode & 0xff); rlog1(0); break;\r
+ case 8<<8: TSTI(sh2, opcode & 0xff); rlog1(0); break;\r
+ case 9<<8: ANDI(sh2, opcode & 0xff); rlog1(0); break;\r
+ case 10<<8: XORI(sh2, opcode & 0xff); rlog1(0); break;\r
+ case 11<<8: ORI(sh2, opcode & 0xff); rlog1(0); break;\r
+ case 12<<8: TSTM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 13<<8: ANDM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 14<<8: XORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
+ case 15<<8: ORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
}\r
rlog(0);\r
}\r
\r
-INLINE void op1101(UINT16 opcode)\r
+INLINE void op1101(sh2_state *sh2, UINT16 opcode)\r
{\r
- MOVLI(opcode & 0xff, Rn);\r
+ MOVLI(sh2, opcode & 0xff, Rn);\r
rlog(LRN);\r
}\r
\r
-INLINE void op1110(UINT16 opcode)\r
+INLINE void op1110(sh2_state *sh2, UINT16 opcode)\r
{\r
- MOVI(opcode & 0xff, Rn);\r
+ MOVI(sh2, opcode & 0xff, Rn);\r
rlog(LRN);\r
}\r
\r
-INLINE void op1111(UINT16 opcode)\r
+INLINE void op1111(sh2_state *sh2, UINT16 opcode)\r
{\r
- NOP();\r
+ ILLEGAL(sh2);\r
rlog(0);\r
}\r
\r
notaz.gp2x.de / picodrive.git / commitdiff