sh2 drc, fix powerpc cache handling

diff --git a/cpu/drc/emit_ppc.c b/cpu/drc/emit_ppc.c
index a11dc1c..0b4f064 100644 (file)
--- a/cpu/drc/emit_ppc.c
+++ b/cpu/drc/emit_ppc.c
@@ -1559,10 +1559,11 @@ static int emith_cond_check(int cond)
 static NOINLINE void host_instructions_updated(void *base, void *end, int force)
 {
        int step = 32, lgstep = 5;
-       char *_base = base, *_end = end;
-       int count = (_end - _base + step-1) >> lgstep;
+       char *_base = (char *)((uptr)base & ~(step-1));
+       int count = (((char *)end - _base) >> lgstep) + 1;
 
        if (count <= 0) count = 1;      // make sure count is positive
+       base = _base;
 
        asm volatile(
        "       mtctr   %1;"

diff --git a/cpu/sh2/compiler.h b/cpu/sh2/compiler.h
index dda3b91..8892b23 100644 (file)
--- a/cpu/sh2/compiler.h
+++ b/cpu/sh2/compiler.h
@@ -47,7 +47,7 @@ u16 scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc,
 #elif defined(__riscv__) || defined(__riscv)
 #define        DRC_SR_REG      "s11"
 #define DRC_REG_LL     0       // no ABI for (__ILP32__ && __riscv_xlen != 32)
-#elif defined(__powerpc__)
+#elif defined(__powerpc__) || defined(__ppc__)
 #define        DRC_SR_REG      "r28"
 #define DRC_REG_LL     0       // no ABI for __ILP32__
 #elif defined(__i386__)

diff --git a/platform/linux/emu.c b/platform/linux/emu.c
index 73ee36a..fa15d3f 100644 (file)
--- a/platform/linux/emu.c
+++ b/platform/linux/emu.c
@@ -32,7 +32,7 @@ void pemu_prep_defconfig(void)
 \r
 void pemu_validate_config(void)\r
 {\r
-#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv__) &&  !defined(__riscv) && !defined(__powerpc__) && !defined(__i386__) && !defined(__x86_64__)\r
+#if !defined(__arm__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv__) &&  !defined(__riscv) && !defined(__powerpc__) && !defined(__ppc__) && !defined(__i386__) && !defined(__x86_64__)\r
        PicoIn.opt &= ~POPT_EN_DRC;\r
 #endif\r
 }\r