From: notaz <notasas@gmail.com>
Date: Fri, 25 Oct 2024 19:25:09 +0000 (+0300)
Subject: 3ds: only invalidate icache on non-compiler core
X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=589a895a25be11540c05b694202d4c68f503ab3d;p=pcsx_rearmed.git

3ds: only invalidate icache on non-compiler core

seems enough, or is it?
---

diff --git a/frontend/3ds/3ds_utils.h b/frontend/3ds/3ds_utils.h
index bde9c491..5c5ad3c5 100644
--- a/frontend/3ds/3ds_utils.h
+++ b/frontend/3ds/3ds_utils.h
@@ -14,7 +14,7 @@
 void wait_for_input(void);
 void ctr_clear_cache(void);
 void ctr_clear_cache_range(void *start, void *end);
-//void ctr_invalidate_icache(void); // only icache
+void ctr_invalidate_icache(void); // only icache
 
 extern __attribute__((weak)) int  __ctr_svchax;
 
diff --git a/frontend/3ds/utils.S b/frontend/3ds/utils.S
index 6f7a6a2f..be4eb97f 100644
--- a/frontend/3ds/utils.S
+++ b/frontend/3ds/utils.S
@@ -61,13 +61,14 @@ ctr_clear_cache_range:
   bx lr
   .endfunc
 
-#if 0
   .func ctr_invalidate_icache_kernel
 ctr_invalidate_icache_kernel:
+  mrs r3, cpsr
   cpsid aif
   mov r0, #0
   mcr p15, 0, r0, c7, c10, 4    @ Data Sync Barrier
   mcr p15, 0, r0, c7, c5, 0     @ Invalidate entire instruction cache / Flush BTB
+  msr cpsr, r3
   bx lr
   .endfunc
 
@@ -78,4 +79,3 @@ ctr_invalidate_icache:
   svc 0x80                      @ svcCustomBackdoor
   bx lr
   .endfunc
-#endif
diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 8ebf2746..62e984b6 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -320,7 +320,7 @@ static void clear_local_cache(void)
 #ifdef _3DS
 	if (ndrc_g.thread.cache_dirty) {
 		ndrc_g.thread.cache_dirty = 0;
-		ctr_clear_cache();
+		ctr_invalidate_icache();
 	}
 #else
 	// hopefully nothing is needed, as tested on r-pi4 and switch