From: notaz Date: Sun, 5 May 2024 14:45:23 +0000 (+0300) Subject: testpico: check irq vector also X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=6474d733133dc605ee02e4e2e02f025c41d202df;p=megadrive.git testpico: check irq vector also --- diff --git a/testpico/main.c b/testpico/main.c index bd99ac3..d02a468 100644 --- a/testpico/main.c +++ b/testpico/main.c @@ -1759,9 +1759,11 @@ static int t_irq_f_flag_h32(void) #define IRQ_CNT_FB_BASE 0x1ff00 +// see do_cmd() static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave) { u16 v, *r = (u16 *)0xa15120; + u8 *r8 = (u8 *)r; u16 cmd_s = cmd | (is_slave << 15); int i; @@ -1775,7 +1777,7 @@ static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave) if (v != 0) { printf("cmd clr: %x\n", v); mem_barrier(); - printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]); + printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]); write16(r, 0); } v = read16(&r[1]); @@ -1817,7 +1819,7 @@ static int t_32x_reset_btn(void) expect(ok, r32[0x20/4], 0x00005a20); expect(ok, r32[0x24/4], 0x5a5a5a24); expect(ok, r32[0x28/4], 0x5a5a5a28); - expect(ok, r32[0x2c/4], 0x5a5a5a2c); + expect(ok, r32[0x2c/4], 0x07075a2c); // 7 - last_irq_vec if (!(r16[0x00/2] & 0x8000)) { expect(ok, r8 [0x81], 0); expect(ok, r16[0x82/2], 0); @@ -1941,13 +1943,16 @@ static int t_32x_init(void) static int t_32x_echo(void) { - u16 *r = (u16 *)0xa15120; + u16 *r16 = (u16 *)0xa15100; int ok = 1; + r16[0x2c/2] = r16[0x2e/2] = 0; x32_cmd(CMD_ECHO, 0x12340000, 0, 0); - expect_sh2(ok, 0, r[0x06/2], 0x1234); + expect_sh2(ok, 0, r16[0x26/2], 0x1234); x32_cmd(CMD_ECHO, 0x23450000, 0, 1); - expect_sh2(ok, 1, r[0x06/2], 0xa345); + expect_sh2(ok, 1, r16[0x26/2], 0xa345); + expect(ok, r16[0x2c/2], 0); // no last_irq_vec + expect(ok, r16[0x2e/2], 0); // no exception_index return ok; } @@ -2069,9 +2074,11 @@ static int t_32x_irq(void) u16 *s_icnt = m_icnt + 8; u32 *r = (u32 *)0xa15100; u16 *r16 = (u16 *)r; + u8 *r8 = (u8 *)r; int ok = 1, i; write8(r, 0x00); // FM=0 + r[0x2c/4] = 0; mem_barrier(); for (i = 0; i < 8; i++) write32(&fbl_icnt[i], 0); @@ -2085,6 +2092,9 @@ static int t_32x_irq(void) write8(r, 0x00); // FM=0 (hangs without) mem_barrier(); expect(ok, r16[0x02/2], 0); + expect(ok, r8 [0x2c], 4); + expect(ok, r8 [0x2d], 0); + expect(ok, r16[0x2e/2], 0); // no exception_index expect(ok, m_icnt[4], 1); expect(ok, s_icnt[4], 0); write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits @@ -2093,6 +2103,9 @@ static int t_32x_irq(void) burn10(10); mem_barrier(); expect(ok, r16[0x02/2], 0); + expect(ok, r8 [0x2c], 4); + expect(ok, r8 [0x2d], 4); + expect(ok, r16[0x2e/2], 0); // no exception_index write8(r, 0x00); // FM=0 mem_barrier(); expect(ok, m_icnt[4], 1); @@ -2139,6 +2152,7 @@ static int t_32x_reset_prep(void) expect(ok, r16[0x00/2], 0x83); write8(r8, 0x00); // FM=0 + r32[0x2c/4] = 0; mem_barrier(); expect(ok, r8[0x8b] & ~2, 0); for (i = 0; i < 8; i++) @@ -2147,6 +2161,7 @@ static int t_32x_reset_prep(void) x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave burn10(10); write8(r8, 0x00); // FM=0 + expect(ok, r32[0x2c/4], 0); mem_barrier(); for (i = 0; i < 8; i++) expect(ok, fbl_icnt[i], 0x01000100); diff --git a/testpico/sh2_main.c b/testpico/sh2_main.c index 6fe8ad7..1bd9b90 100644 --- a/testpico/sh2_main.c +++ b/testpico/sh2_main.c @@ -3,6 +3,15 @@ void spin(int loops); u16 read_frt(void); +// comm area map: +// 00-01: cmd +// 02-03: error +// 04-07: arg0/response +// 08-0b: arg1 +// 0c: last_irq_vec_master +// 0d: last_irq_vec_slave +// 0e: exception_index_master +// 0f: exception_index_slave static void do_cmd(u16 cmd, u16 r[6], u32 is_slave) { u32 *rl = (u32 *)r; diff --git a/testpico/sh2_test.sh2 b/testpico/sh2_test.sh2 index 692fd92..0201827 100644 --- a/testpico/sh2_test.sh2 +++ b/testpico/sh2_test.sh2 @@ -17,21 +17,21 @@ .long master_e11 /* NMI vector */ .long master_e12 /* User break vector */ .rept 19 - .long main_err /* reserved */ + .long master_err /* reserved */ .endr .rept 32 - .long main_err /* TRAPA #32-63 */ + .long master_err /* TRAPA #32-63 */ .endr - .long main_irq /* Level 1 IRQ */ - .long main_irq /* Level 2 & 3 IRQ's */ - .long main_irq /* Level 4 & 5 IRQ's */ - .long main_irq /* PWM interupt */ - .long main_irq /* Command interupt */ - .long main_irq /* H Blank interupt */ - .long main_irq /* V Blank interupt */ - .long main_irq /* Reset Button */ + .long master_irq0 /* Level 1 IRQ */ + .long master_irq1 /* Level 2 & 3 IRQ's */ + .long master_irq2 /* Level 4 & 5 IRQ's */ + .long master_irq3 /* PWM interupt */ + .long master_irq4 /* Command interupt */ + .long master_irq5 /* H Blank interupt */ + .long master_irq6 /* V Blank interupt */ + .long master_irq7 /* Reset Button */ .rept 56 - .long main_err /* peripherals */ + .long master_err /* peripherals */ .endr ! Slave Vector Base Table at 0x06000200 @@ -55,14 +55,14 @@ .rept 32 .long slave_err /* TRAPA #32-63 */ .endr - .long slave_irq /* Level 1 IRQ */ - .long slave_irq /* Level 2 & 3 IRQ's */ - .long slave_irq /* Level 4 & 5 IRQ's */ - .long slave_irq /* PWM interupt */ - .long slave_irq /* Command interupt */ - .long slave_irq /* H Blank interupt */ - .long slave_irq /* V Blank interupt */ - .long slave_irq /* Reset Button */ + .long slave_irq0 /* Level 1 IRQ */ + .long slave_irq1 /* Level 2 & 3 IRQ's */ + .long slave_irq2 /* Level 4 & 5 IRQ's */ + .long slave_irq3 /* PWM interupt */ + .long slave_irq4 /* Command interupt */ + .long slave_irq5 /* H Blank interupt */ + .long slave_irq6 /* V Blank interupt */ + .long slave_irq7 /* Reset Button */ .rept 56 .long slave_err /* peripherals */ .endr @@ -106,8 +106,9 @@ xstart: jmp @r0 nop -main_irq: - mov.l r0, @-r15 +! r0=vector_number +do_irq_master: + mov.b r0, @(0x2c, gbr) mov.l r1, @-r15 mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ @@ -186,15 +187,16 @@ _read_frt: .global _start _start: -main_err: +master_err: bra do_exc_master mov #0xff, r0 slave_err: bra do_exc_slave mov #0xff, r0 -slave_irq: - mov.l r0, @-r15 +! r0=vector_number +do_irq_slave: + mov.b r0, @(0x2d, gbr) mov.l r1, @-r15 mov.l l_irq_cnt, r1 /* counters in fb (0x2401ff00) */ bra do_irq_cmn @@ -225,6 +227,20 @@ slave_e\num: mov #\num, r0 .endm +.macro irq_master num +master_irq\num: + mov.l r0, @-r15 + bra do_irq_master + mov #\num, r0 +.endm + +.macro irq_slave num +slave_irq\num: + mov.l r0, @-r15 + bra do_irq_slave + mov #\num, r0 +.endm + exc_master 4 exc_master 5 exc_master 6 @@ -234,6 +250,14 @@ exc_master 9 exc_master 10 exc_master 11 exc_master 12 +irq_master 0 +irq_master 1 +irq_master 2 +irq_master 3 +irq_master 4 +irq_master 5 +irq_master 6 +irq_master 7 exc_slave 4 exc_slave 5 @@ -244,15 +268,23 @@ exc_slave 9 exc_slave 10 exc_slave 11 exc_slave 12 +irq_slave 0 +irq_slave 1 +irq_slave 2 +irq_slave 3 +irq_slave 4 +irq_slave 5 +irq_slave 6 +irq_slave 7 do_exc_master: - mov.w r0, @(0x2c, gbr) + mov.b r0, @(0x2e, gbr) 0: bra 0b nop do_exc_slave: - mov.w r0, @(0x2e, gbr) + mov.b r0, @(0x2f, gbr) 0: bra 0b nop