From: notaz Date: Wed, 2 Feb 2022 21:40:48 +0000 (+0200) Subject: drc: rm unneeded &63 masking X-Git-Tag: r24l~515 X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=91af94f057bcc1e20f69c11a8e0fa78b81611b7e;p=pcsx_rearmed.git drc: rm unneeded &63 masking 64bit leftover --- diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 32ef9794..da32f5b7 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -1808,7 +1808,7 @@ static void inline_readstub(enum stub_type type, int i, u_int addr, { int rs=get_reg(regmap,target); int rt=get_reg(regmap,target); - if(rs<0) rs=get_reg(regmap,-1); + if(rs<0) rs=get_reg_temp(regmap); assert(rs>=0); u_int is_dynamic; uintptr_t host_addr = 0; @@ -1962,7 +1962,7 @@ static void do_writestub(int n) static void inline_writestub(enum stub_type type, int i, u_int addr, const signed char regmap[], int target, int adj, u_int reglist) { - int rs=get_reg(regmap,-1); + int rs=get_reg_temp(regmap); int rt=get_reg(regmap,target); assert(rs>=0); assert(rt>=0); diff --git a/libpcsxcore/new_dynarec/assem_arm64.c b/libpcsxcore/new_dynarec/assem_arm64.c index 84e4fc6e..1157aafe 100644 --- a/libpcsxcore/new_dynarec/assem_arm64.c +++ b/libpcsxcore/new_dynarec/assem_arm64.c @@ -1479,7 +1479,7 @@ static void inline_readstub(enum stub_type type, int i, u_int addr, { int rs=get_reg(regmap,target); int rt=get_reg(regmap,target); - if(rs<0) rs=get_reg(regmap,-1); + if(rs<0) rs=get_reg_temp(regmap); assert(rs>=0); u_int is_dynamic=0; uintptr_t host_addr = 0; @@ -1633,7 +1633,7 @@ static void do_writestub(int n) static void inline_writestub(enum stub_type type, int i, u_int addr, const signed char regmap[], int target, int adj, u_int reglist) { - int rs = get_reg(regmap,-1); + int rs = get_reg_temp(regmap); int rt = get_reg(regmap,target); assert(rs >= 0); assert(rt >= 0); diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index cc6c094d..abb0d076 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -607,10 +607,27 @@ static void clear_all_regs(signed char regmap[]) memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); } -static signed char get_reg(const signed char regmap[],int r) +static signed char get_reg(const signed char regmap[], signed char r) { int hr; - for (hr=0;hrregmap[hr]&63)==reg) { - cur->dirty|=1<regmap, reg); + if (hr >= 0) + cur->dirty |= 1<regmap[hr]==reg) { - cur->isconst|=1<regmap, reg); + if (hr >= 0) { + cur->isconst |= 1<regmap[hr]&63)==reg) { - cur->isconst&=~(1<regmap, reg); + if (hr >= 0) + cur->isconst &= ~(1<regmap[hr]&63)==reg) { - return (cur->isconst>>hr)&1; - } - } + if (reg < 0) return 0; + if (!reg) return 1; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return (cur->isconst>>hr)&1; return 0; } -static uint32_t get_const(struct regstat *cur, signed char reg) +static uint32_t get_const(const struct regstat *cur, signed char reg) { int hr; - if(!reg) return 0; - for (hr=0;hrregmap[hr]==reg) { - return current_constmap[hr]; - } - } - SysPrintf("Unknown constant in r%d\n",reg); + if (!reg) return 0; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return current_constmap[hr]; + + SysPrintf("Unknown constant in r%d\n", reg); abort(); } @@ -879,14 +888,14 @@ void alloc_all(struct regstat *cur,int i) for(hr=0;hrregmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&& - ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2)) + if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& + (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) { cur->regmap[hr]=-1; cur->dirty&=~(1<regmap[hr]&63)==0) + if(cur->regmap[hr]==0) { cur->regmap[hr]=-1; cur->dirty&=~(1<regmap[preferred_reg]&63]==j) { for(hr=0;hrregmap[hr]&63)==r) { + if(cur->regmap[hr]==r) { cur->regmap[hr]=-1; cur->dirty&=~(1<isconst&=~(1<>hr)&1) { assert(regmap[hr]<64); emit_storereg(r,hr); @@ -2148,7 +2157,7 @@ static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int for(hr=0;hr>(reg&63))&1) { + if(((~u)>>reg)&1) { if(reg>0) { if(((dirty_pre&~dirty)>>hr)&1) { if(reg>0&®<34) { @@ -2806,12 +2815,12 @@ static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) // could be FIFO, must perform the read // ||dummy read assem_debug("(forced read)\n"); - tl=get_reg(i_regs->regmap,-1); + tl=get_reg_temp(i_regs->regmap); assert(tl>=0); } if(offset||s<0||c) addr=tl; else addr=s; - //if(tl<0) tl=get_reg(i_regs->regmap,-1); + //if(tl<0) tl=get_reg_temp(i_regs->regmap); if(tl>=0) { //printf("load_assemble: c=%d\n",c); //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); @@ -2942,7 +2951,7 @@ static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rt1); s=get_reg(i_regs->regmap,dops[i].rs1); - temp=get_reg(i_regs->regmap,-1); + temp=get_reg_temp(i_regs->regmap); temp2=get_reg(i_regs->regmap,FTEMP); addr=get_reg(i_regs->regmap,AGEN1+(i&1)); assert(addr<0); @@ -3028,7 +3037,7 @@ static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->wasconst>>s)&1; @@ -3153,7 +3162,7 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->isconst>>s)&1; @@ -3582,7 +3591,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) { int j, known_cycles = 0; u_int reglist = get_host_reglist(i_regs->regmap); - int rtmp = get_reg(i_regs->regmap, -1); + int rtmp = get_reg_temp(i_regs->regmap); if (rtmp < 0) rtmp = reglist_find_free(reglist); if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3731,7 +3740,7 @@ static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) // get the address if (dops[i].opcode==0x3a) { // SWC2 ar=get_reg(i_regs->regmap,agr); - if(ar<0) ar=get_reg(i_regs->regmap,-1); + if(ar<0) ar=get_reg_temp(i_regs->regmap); reglist|=1<>11) & 0x1f; - signed char temp = get_reg(i_regs->regmap, -1); + signed char temp = get_reg_temp(i_regs->regmap); if (!HACK_ENABLED(NDHACK_NO_STALLS)) { u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); @@ -4216,7 +4225,7 @@ static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,u for(hr=0;hr=0&&(pre[hr]&63)=0&&pre[hr]=0) { emit_mov(hr,nr); @@ -4291,7 +4300,7 @@ void address_generation(int i, const struct regstat *i_regs, signed char entry[] int agr=AGEN1+(i&1); if(dops[i].itype==LOAD) { ra=get_reg(i_regs->regmap,dops[i].rt1); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); assert(ra>=0); } if(dops[i].itype==LOADLR) { @@ -4299,14 +4308,14 @@ void address_generation(int i, const struct regstat *i_regs, signed char entry[] } if(dops[i].itype==STORE||dops[i].itype==STORELR) { ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } if(dops[i].itype==C2LS) { if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 ra=get_reg(i_regs->regmap,FTEMP); else { // SWC1/SDC1/SWC2/SDC2 ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } } int rs=get_reg(i_regs->regmap,dops[i].rs1); @@ -4553,7 +4562,7 @@ static void load_all_regs(const signed char i_regmap[]) emit_zeroreg(hr); } else - if(i_regmap[hr]>0 && (i_regmap[hr]&63)0 && i_regmap[hr]0 && (i_regmap[hr]&63)0 && i_regmap[hr]regmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { addr=hr++;break; } @@ -5913,8 +5922,8 @@ static void pagespan_assemble(int i, const struct regstat *i_regs) while(hrregmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { alt=hr++;break; } @@ -5925,8 +5934,8 @@ static void pagespan_assemble(int i, const struct regstat *i_regs) while(hrregmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { ntaddr=hr;break; } @@ -6122,7 +6131,7 @@ static void pagespan_ds() } int btaddr=get_reg(regs[0].regmap,BTREG); if(btaddr<0) { - btaddr=get_reg(regs[0].regmap,-1); + btaddr=get_reg_temp(regs[0].regmap); emit_readword(&branch_target,btaddr); } assert(btaddr!=HOST_CCREG); @@ -6328,6 +6337,7 @@ void clean_registers(int istart,int iend,int wr) } for (i=iend;i>=istart;i--) { + __builtin_prefetch(regs[i-1].regmap); if(dops[i].is_jump) { if(ba[i]=(start+slen*4)) @@ -6341,18 +6351,18 @@ void clean_registers(int istart,int iend,int wr) // Merge in delay slot (will dirty) for(r=0;r33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<0 && (regmap_pre[i][r]&63)<34) { - temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<0 && regmap_pre[i][r]<34) { + temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>2]&(1<=0) { - will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<>2]>>(branch_regs[i].regmap[r]&63))&1)<>2]>>branch_regs[i].regmap[r])&1)<>2]>>branch_regs[i].regmap[r])&1)<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<start+i*4) { // Disable recursion (for debugging) + //if(ba[i]>start+i*4) // Disable recursion (for debugging) for(r=0;r>2]&(1<=0) { - will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<>2]>>(target_reg&63))&1)<>2]>>target_reg)&1)<>2]>>target_reg)&1)<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<istart) { if (!dops[i].is_jump) { // Don't store a register immediately after writing it, // may prevent dual-issue. - if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<0 && (regmap_pre[i][r]&63)<34) { - will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<0 && regmap_pre[i][r]<34) { + will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>r)&1));*/ @@ -8105,7 +8113,7 @@ int new_recompile_block(u_int addr) if(r!=regmap_pre[i][hr]) { // TODO: delay slot (?) or=get_reg(regmap_pre[i],r); // Get old mapping for this register - if(or<0||(r&63)>=TEMPREG){ + if(or<0||r>=TEMPREG){ regs[i].regmap_entry[hr]=-1; } else @@ -8113,7 +8121,7 @@ int new_recompile_block(u_int addr) // Just move it to a different register regs[i].regmap_entry[hr]=r; // If it was dirty before, it's still dirty - if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); + if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); } } else @@ -8449,8 +8457,8 @@ int new_recompile_block(u_int addr) // Merge in delay slot for(hr=0;hr0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) { if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { - if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { - if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1< %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); if(r<34&&((unneeded_reg[j]>>r)&1)) break; assert(r < 64); - if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63) %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); int k; if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { @@ -8992,7 +9000,7 @@ int new_recompile_block(u_int addr) ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); - if(hr<0) hr=get_reg(regs[i+1].regmap,-1); + if(hr<0) hr=get_reg_temp(regs[i+1].regmap); else { regs[i+1].regmap[hr]=AGEN1+((i+1)&1); regs[i+1].isconst&=~(1<=0&®s[i].regmap[hr]<0) { int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); @@ -9258,6 +9266,7 @@ int new_recompile_block(u_int addr) } for(i=0;i