From: notaz Date: Thu, 27 Jul 2023 00:09:34 +0000 (+0300) Subject: drc: update according to the interpreter (3) X-Git-Tag: r24~230 X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=de6dbc5289bc76996ad4e3133e0eeb90e13b2ed4;p=pcsx_rearmed.git drc: update according to the interpreter (3) --- diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 2850d4e3..a7bdfbda 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -442,7 +442,6 @@ static void emit_loadreg(int r, int hr) //case HIREG: addr = &hi; break; //case LOREG: addr = &lo; break; case CCREG: addr = &cycle_count; break; - case CSREG: addr = &psxRegs.CP0.n.SR; break; case INVCP: addr = &invc_ptr; break; case ROREG: addr = &ram_offset; break; default: @@ -882,7 +881,7 @@ static void emit_cmovs_imm(int imm,int rt) output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval); } -static void emit_cmovne_reg(int rs,int rt) +static unused void emit_cmovne_reg(int rs,int rt) { assem_debug("movne %s,%s\n",regname[rt],regname[rs]); output_w32(0x11a00000|rd_rn_rm(rt,0,rs)); diff --git a/libpcsxcore/new_dynarec/assem_arm64.c b/libpcsxcore/new_dynarec/assem_arm64.c index 670f3799..0a29eaf4 100644 --- a/libpcsxcore/new_dynarec/assem_arm64.c +++ b/libpcsxcore/new_dynarec/assem_arm64.c @@ -484,7 +484,6 @@ static void emit_loadreg(u_int r, u_int hr) //case HIREG: addr = &hi; break; //case LOREG: addr = &lo; break; case CCREG: addr = &cycle_count; break; - case CSREG: addr = &psxRegs.CP0.n.SR; break; case INVCP: addr = &invc_ptr; is64 = 1; break; case ROREG: addr = &ram_offset; is64 = 1; break; default: diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c index 2590b3ab..2862c546 100644 --- a/libpcsxcore/new_dynarec/emu_if.c +++ b/libpcsxcore/new_dynarec/emu_if.c @@ -28,7 +28,9 @@ void pcsx_mtc0(u32 reg, u32 val) evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle); MTC0(&psxRegs, reg, val); gen_interupt(&psxRegs.CP0); - if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.SR & 0x0300) // possible sw irq + + //if (psxRegs.CP0.n.Cause & psxRegs.CP0.n.SR & 0x0300) // possible sw irq + if ((psxRegs.pc & 0x803ffeff) == 0x80000080) pending_exception = 1; } diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S index a7f4d796..6b429b08 100644 --- a/libpcsxcore/new_dynarec/linkage_arm.S +++ b/libpcsxcore/new_dynarec/linkage_arm.S @@ -239,10 +239,9 @@ FUNCTION(cc_interrupt): add r10, r0, r10 str r1, [fp, #LO_pending_exception] str r10, [fp, #LO_cycle] /* PCSX cycles */ -@@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */ mov r10, lr - add r0, fp, #(LO_psxRegs + 34*4) /* CP0 */ + add r0, fp, #LO_reg_cop0 /* CP0 */ bl gen_interupt mov lr, r10 ldr r10, [fp, #LO_cycle] @@ -298,7 +297,7 @@ call_psxException: str r2, [fp, #LO_pcaddr] add r10, r3, r10 str r10, [fp, #LO_cycle] /* PCSX cycles */ - add r2, fp, #(LO_psxRegs + 34*4) /* CP0 */ + add r2, fp, #LO_reg_cop0 /* CP0 */ bl psxException /* note: psxException might do recursive recompiler call from it's HLE code, @@ -518,7 +517,7 @@ FUNCTION(jump_handle_swl): mov r12,r0,lsr #12 ldr r3, [r3, r12, lsl #2] lsls r3, #1 - bcs 4f + bcs jump_handle_swx_interp add r3, r0, r3 mov r0, r2 tst r3, #2 @@ -541,11 +540,6 @@ FUNCTION(jump_handle_swl): strhne r1, [r3, #-1] strbeq r12, [r3] bx lr -4: - mov r0, r2 -@ b abort - bx lr @ TODO? - FUNCTION(jump_handle_swr): /* r0 = address, r1 = data, r2 = cycles */ @@ -553,7 +547,7 @@ FUNCTION(jump_handle_swr): mov r12,r0,lsr #12 ldr r3, [r3, r12, lsl #2] lsls r3, #1 - bcs 4f + bcs jump_handle_swx_interp add r3, r0, r3 and r12,r3, #3 mov r0, r2 @@ -567,11 +561,14 @@ FUNCTION(jump_handle_swr): strb r1, [r3] strh r2, [r3, #1] bx lr -4: - mov r0, r2 -@ b abort - bx lr @ TODO? +jump_handle_swx_interp: /* almost never happens */ + ldr r3, [fp, #LO_last_count] + add r0, fp, #LO_psxRegs + add r2, r3, r2 + str r2, [fp, #LO_cycle] /* PCSX cycles */ + bl execI + b jump_to_new_pc .macro rcntx_read_mode0 num /* r0 = address, r2 = cycles */ diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S index 8d11fcfa..644b0356 100644 --- a/libpcsxcore/new_dynarec/linkage_arm64.S +++ b/libpcsxcore/new_dynarec/linkage_arm64.S @@ -97,10 +97,9 @@ FUNCTION(cc_interrupt): add rCC, w0, rCC str wzr, [rFP, #LO_pending_exception] str rCC, [rFP, #LO_cycle] /* PCSX cycles */ -# str rCC, [rFP, #LO_reg_cop0+36] /* Count */ mov x21, lr 1: - add x0, rFP, #(LO_psxRegs + 34*4) /* CP0 */ + add x0, rFP, #LO_reg_cop0 /* CP0 */ bl gen_interupt mov lr, x21 ldr rCC, [rFP, #LO_cycle] @@ -156,7 +155,7 @@ call_psxException: str w2, [rFP, #LO_pcaddr] add rCC, w3, rCC str rCC, [rFP, #LO_cycle] /* PCSX cycles */ - add x2, rFP, #(LO_psxRegs + 34*4) /* CP0 */ + add x2, rFP, #LO_reg_cop0 /* CP0 */ bl psxException /* note: psxException might do recursive recompiler call from it's HLE code, @@ -302,7 +301,7 @@ FUNCTION(jump_handle_swl): orr w4, wzr, w0, lsr #12 ldr x3, [x3, w4, uxtw #3] adds x3, x3, x3 - bcs 4f + bcs jump_handle_swx_interp add x3, x0, x3 mov w0, w2 tbz x3, #1, 10f // & 2 @@ -326,10 +325,6 @@ FUNCTION(jump_handle_swl): lsr w2, w1, #24 strb w2, [x3] ret -4: - mov w0, w2 // todo - bl abort - ret FUNCTION(jump_handle_swr): /* w0 = address, w1 = data, w2 = cycles */ @@ -337,7 +332,7 @@ FUNCTION(jump_handle_swr): orr w4, wzr, w0, lsr #12 ldr x3, [x3, w4, uxtw #3] adds x3, x3, x3 - bcs 4f + bcs jump_handle_swx_interp add x3, x0, x3 mov w0, w2 tbz x3, #1, 10f // & 2 @@ -358,10 +353,14 @@ FUNCTION(jump_handle_swr): 0: str w1, [x3] ret -4: - mov w0, w2 // todo - bl abort - ret + +jump_handle_swx_interp: /* almost never happens */ + ldr w3, [rFP, #LO_last_count] + add x0, rFP, #LO_psxRegs + add w2, w3, w2 + str w2, [rFP, #LO_cycle] /* PCSX cycles */ + bl execI + b jump_to_new_pc FUNCTION(call_gteStall): /* w0 = op_cycles, w1 = cycles */ diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 61b078fe..e95d165c 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -320,7 +320,7 @@ static struct compile_info #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x)) - extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 + extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG) extern int last_count; // last absolute target, often = next_interupt extern int pcaddr; extern int pending_exception; @@ -333,7 +333,7 @@ static struct compile_info #define LOREG 32 // lo #define HIREG 33 // hi //#define FSREG 34 // FPU status (FCSR) -#define CSREG 35 // Coprocessor status +//#define CSREG 35 // Coprocessor status #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code //#define MMREG 38 // Pointer to memory_map @@ -419,7 +419,7 @@ static void load_regs_entry(int t); static void load_all_consts(const signed char regmap[], u_int dirty, int i); static u_int get_host_reglist(const signed char *regmap); -static int get_final_value(int hr, int i, int *value); +static int get_final_value(int hr, int i, u_int *value); static void add_stub(enum stub_type type, void *addr, void *retaddr, u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e); static void add_stub_r(enum stub_type type, void *addr, void *retaddr, @@ -748,6 +748,26 @@ static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page) return NULL; } +// this doesn't normally happen +static noinline u_int generate_exception(u_int pc) +{ + //if (execBreakCheck(&psxRegs, pc)) + // return psxRegs.pc; + + // generate an address or bus error + psxRegs.CP0.n.Cause &= 0x300; + psxRegs.CP0.n.EPC = pc; + if (pc & 3) { + psxRegs.CP0.n.Cause |= R3000E_AdEL << 2; + psxRegs.CP0.n.BadVAddr = pc; +#ifdef DRC_DBG + last_count -= 2; +#endif + } else + psxRegs.CP0.n.Cause |= R3000E_IBE << 2; + return (psxRegs.pc = 0x80000080); +} + // Get address from virtual address // This is called from the recompiled JR/JALR instructions static void noinline *get_addr(u_int vaddr, int can_compile) @@ -782,22 +802,10 @@ static void noinline *get_addr(u_int vaddr, int can_compile) return NULL; int r = new_recompile_block(vaddr); - if (r == 0) + if (likely(r == 0)) return ndrc_get_addr_ht(vaddr); - // generate an address error -#ifdef DRC_DBG - last_count -= 2; -#endif - psxRegs.CP0.n.Cause &= 0x300; - psxRegs.CP0.n.EPC = vaddr; - if (vaddr & 3) { - psxRegs.CP0.n.Cause |= R3000E_AdEL << 2; - psxRegs.CP0.n.BadVAddr = vaddr; - } else - psxRegs.CP0.n.Cause |= R3000E_IBE << 2; - psxRegs.pc = 0x80000080; - return ndrc_get_addr_ht(0x80000080); + return ndrc_get_addr_ht(generate_exception(vaddr)); } // Look up address in hash table first @@ -1247,6 +1255,7 @@ static const char *fpofs_name(u_int ofs) switch (ofs) { #define ofscase(x) case LO_##x: return " ; " #x ofscase(next_interupt); + ofscase(cycle_count); ofscase(last_count); ofscase(pending_exception); ofscase(stop); @@ -1960,8 +1969,6 @@ static void shiftimm_alloc(struct regstat *current,int i) static void shift_alloc(struct regstat *current,int i) { if(dops[i].rt1) { - if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV - { if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1); if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2); alloc_reg(current,i,dops[i].rt1); @@ -1969,9 +1976,6 @@ static void shift_alloc(struct regstat *current,int i) alloc_reg_temp(current,i,-1); cinfo[i].min_free_regs=1; } - } else { // DSLLV/DSRLV/DSRAV - assert(0); - } clear_const(current,dops[i].rs1); clear_const(current,dops[i].rs2); clear_const(current,dops[i].rt1); @@ -2154,17 +2158,11 @@ static void multdiv_alloc(struct regstat *current,int i) // case 0x19: MULTU // case 0x1A: DIV // case 0x1B: DIVU - // case 0x1C: DMULT - // case 0x1D: DMULTU - // case 0x1E: DDIV - // case 0x1F: DDIVU clear_const(current,dops[i].rs1); clear_const(current,dops[i].rs2); alloc_cc(current,i); // for stalls if(dops[i].rs1&&dops[i].rs2) { - if((dops[i].opcode2&4)==0) // 32-bit - { current->u&=~(1LL<u&=~(1LL<>11)&0x1e) == 12) { + alloc_cc(current, i); + dirty_reg(current, CCREG); + } if(dops[i].rs1){ clear_const(current,dops[i].rs1); alloc_reg(current,i,dops[i].rs1); @@ -3474,7 +3472,6 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) assert(addr >= 0); if(!c) { emit_cmpimm(addr, RAM_SIZE); - if (!offset && s != addr) emit_mov(s, addr); jaddr=out; emit_jno(0); } @@ -3488,10 +3485,6 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) if (ram_offset) offset_reg = get_ro_reg(i_regs, 0); - if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR - assert(0); - } - emit_testimm(addr,2); case23=out; emit_jne(0); @@ -3578,22 +3571,18 @@ static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) } else if(dops[i].opcode2==4) // MTC0 { - signed char s=get_reg(i_regs->regmap,dops[i].rs1); + int s = get_reg(i_regs->regmap, dops[i].rs1); + int cc = get_reg(i_regs->regmap, CCREG); char copr=(source[i]>>11)&0x1f; assert(s>=0); wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty); - if(copr==9||copr==11||copr==12||copr==13) { + if (copr == 12 || copr == 13) { emit_readword(&last_count,HOST_TEMPREG); - emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc - emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); - emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); - emit_writeword(HOST_CCREG,&psxRegs.cycle); - } - // What a mess. The status register (12) can enable interrupts, - // so needs a special case to handle a pending interrupt. - // The interrupt must be taken immediately, because a subsequent - // instruction might disable interrupts again. - if(copr==12||copr==13) { + if (cc != HOST_CCREG) + emit_loadreg(CCREG, HOST_CCREG); + emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG); + emit_writeword(HOST_CCREG, &psxRegs.cycle); if (is_delayslot) { // burn cycles to cause cc_interrupt, which will // reschedule next_interupt. Relies on CCREG from above. @@ -3612,31 +3601,27 @@ static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) emit_movimm(0,HOST_TEMPREG); emit_writeword(HOST_TEMPREG,&pending_exception); } - if(s==HOST_CCREG) - emit_loadreg(dops[i].rs1,1); - else if(s!=1) - emit_mov(s,1); - emit_movimm(copr,0); + if( s != 1) + emit_mov(s, 1); + emit_movimm(copr, 0); emit_far_call(pcsx_mtc0); - if(copr==9||copr==11||copr==12||copr==13) { + if (copr == 12 || copr == 13) { emit_readword(&psxRegs.cycle,HOST_CCREG); - emit_readword(&next_interupt,HOST_TEMPREG); - emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); + emit_readword(&last_count,HOST_TEMPREG); emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); - emit_writeword(HOST_TEMPREG,&last_count); - emit_storereg(CCREG,HOST_CCREG); - } - if(copr==12||copr==13) { + //emit_writeword(HOST_TEMPREG,&last_count); assert(!is_delayslot); emit_readword(&pending_exception,HOST_TEMPREG); emit_test(HOST_TEMPREG,HOST_TEMPREG); void *jaddr = out; emit_jeq(0); emit_readword(&pcaddr, 0); - emit_addimm(HOST_CCREG,2,HOST_CCREG); emit_far_call(ndrc_get_addr_ht); emit_jmpreg(0); set_jump_target(jaddr, out); + emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG); + if (cc != HOST_CCREG) + emit_storereg(CCREG, HOST_CCREG); } emit_loadreg(dops[i].rs1,s); } @@ -3968,7 +3953,6 @@ static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) s=get_reg(i_regs->regmap,dops[i].rs1); tl=get_reg(i_regs->regmap,FTEMP); offset=cinfo[i].imm; - assert(dops[i].rs1>0); assert(tl>=0); if(i_regs->regmap[HOST_CCREG]==CCREG) @@ -4119,6 +4103,8 @@ static void do_unalignedwritestub(int n) if(cc<0) emit_loadreg(CCREG,2); emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); + emit_movimm(start + i*4,3); + emit_writeword(3,&psxRegs.pc); emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); if(cc<0) @@ -4286,7 +4272,8 @@ static void speculate_register_values(int i) // fallthrough case IMM16: if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) { - int value,hr=get_reg_w(regs[i].regmap, dops[i].rt1); + int hr = get_reg_w(regs[i].regmap, dops[i].rt1); + u_int value; if(hr>=0) { if(get_final_value(hr,i,&value)) smrv[dops[i].rt1]=value; @@ -4647,7 +4634,7 @@ static void address_generation(int i, const struct regstat *i_regs, signed char } } -static int get_final_value(int hr, int i, int *value) +static int get_final_value(int hr, int i, u_int *value) { int reg=regs[i].regmap[hr]; while(i>hr)&1)) { assert(regmap[hr]<64); if(((regs[i].isconst>>hr)&1)&®map[hr]>0) { - int value,similar=0; + u_int value, similar=0; if(get_final_value(hr,i,&value)) { // see if some other register has similar value for(hr2=0;hr2=0); return_address=start+i*4+8; if(rt>=0) { @@ -5367,7 +5358,8 @@ static void ujump_assemble_write_ra(int i) if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif - emit_movimm(return_address,rt); // PC into link register + if (!((regs[i].loadedconst >> rt) & 1)) + emit_movimm(return_address, rt); // PC into link register #ifdef IMM_PREFETCH emit_prefetch(hash_table_get(return_address)); #endif @@ -5377,7 +5369,6 @@ static void ujump_assemble_write_ra(int i) static void ujump_assemble(int i, const struct regstat *i_regs) { - int ra_done=0; if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n"); address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH @@ -5390,17 +5381,13 @@ static void ujump_assemble(int i, const struct regstat *i_regs) if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif - if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { + if (dops[i].rt1 == 31) ujump_assemble_write_ra(i); // writeback ra for DS - ra_done=1; - } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; bc_unneeded|=1|(1LL<=0); return_address=start+i*4+8; #ifdef REG_PREFETCH @@ -5439,7 +5424,8 @@ static void rjump_assemble_write_ra(int i) if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp); } #endif - emit_movimm(return_address,rt); // PC into link register + if (!((regs[i].loadedconst >> rt) & 1)) + emit_movimm(return_address, rt); // PC into link register #ifdef IMM_PREFETCH emit_prefetch(hash_table_get(return_address)); #endif @@ -5449,7 +5435,6 @@ static void rjump_assemble(int i, const struct regstat *i_regs) { int temp; int rs,cc; - int ra_done=0; rs=get_reg(branch_regs[i].regmap,dops[i].rs1); assert(rs>=0); if (ds_writes_rjump_rs(i)) { @@ -5477,18 +5462,14 @@ static void rjump_assemble(int i, const struct regstat *i_regs) if(rh>=0) do_preload_rhash(rh); } #endif - if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) { + if (dops[i].rt1 != 0) rjump_assemble_write_ra(i); - ra_done=1; - } ds_assemble(i+1,i_regs); uint64_t bc_unneeded=branch_regs[i].u; bc_unneeded|=1|(1LL<=0) { // Save the PC even if the branch is not taken return_address=start+i*4+8; @@ -6004,7 +5985,7 @@ static void sjump_assemble(int i, const struct regstat *i_regs) // In-order execution (branch first) //printf("IOE\n"); void *nottaken = NULL; - if (!unconditional) { + if (!unconditional && !nevertaken) { assert(s1l >= 0); emit_test(s1l, s1l); } @@ -6020,7 +6001,7 @@ static void sjump_assemble(int i, const struct regstat *i_regs) #endif } } - if (!unconditional) { + if (!unconditional && !nevertaken) { nottaken = out; if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL emit_jns(DJT_1); @@ -6067,7 +6048,10 @@ static void sjump_assemble(int i, const struct regstat *i_regs) } // branch not taken if(!unconditional) { - set_jump_target(nottaken, out); + if (!nevertaken) { + assert(nottaken); + set_jump_target(nottaken, out); + } assem_debug("1:\n"); wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); @@ -6601,26 +6585,36 @@ static int apply_hacks(void) return 0; } -static noinline void pass1_disassemble(u_int pagelimit) +static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op) { - int i, j, done = 0, ni_count = 0; - unsigned int type,op,op2,op3; + return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2) + && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP; +} - for (i = 0; !done; i++) - { - int force_j_to_interpreter = 0; +static void force_intcall(int i) +{ + memset(&dops[i], 0, sizeof(dops[i])); + dops[i].itype = INTCALL; + dops[i].rs1 = CCREG; + dops[i].is_exception = 1; + cinfo[i].ba = -1; +} + +static void disassemble_one(int i, u_int src) +{ + unsigned int type, op, op2, op3; memset(&dops[i], 0, sizeof(dops[i])); memset(&cinfo[i], 0, sizeof(cinfo[i])); cinfo[i].ba = -1; cinfo[i].addr = -1; - dops[i].opcode = op = source[i] >> 26; + dops[i].opcode = op = src >> 26; op2 = 0; type = INTCALL; set_mnemonic(i, "???"); switch(op) { case 0x00: set_mnemonic(i, "special"); - op2=source[i]&0x3f; + op2 = src & 0x3f; switch(op2) { case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; @@ -6633,7 +6627,6 @@ static noinline void pass1_disassemble(u_int pagelimit) case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; - case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break; case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; @@ -6656,7 +6649,7 @@ static noinline void pass1_disassemble(u_int pagelimit) break; case 0x01: set_mnemonic(i, "regimm"); type = SJUMP; - op2 = (source[i] >> 16) & 0x1f; + op2 = (src >> 16) & 0x1f; switch(op2) { case 0x10: set_mnemonic(i, "BLTZAL"); break; @@ -6683,9 +6676,9 @@ static noinline void pass1_disassemble(u_int pagelimit) case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; case 0x10: set_mnemonic(i, "COP0"); - op2 = (source[i]>>21) & 0x1f; + op2 = (src >> 21) & 0x1f; if (op2 & 0x10) { - op3 = source[i] & 0x1f; + op3 = src & 0x1f; switch (op3) { case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break; @@ -6699,7 +6692,7 @@ static noinline void pass1_disassemble(u_int pagelimit) u32 rd; case 0x00: set_mnemonic(i, "MFC0"); - rd = (source[i] >> 11) & 0x1F; + rd = (src >> 11) & 0x1F; if (!(0x00000417u & (1u << rd))) type = COP0; break; @@ -6710,18 +6703,18 @@ static noinline void pass1_disassemble(u_int pagelimit) } break; case 0x11: set_mnemonic(i, "COP1"); - op2=(source[i]>>21)&0x1f; + op2 = (src >> 21) & 0x1f; break; case 0x12: set_mnemonic(i, "COP2"); - op2=(source[i]>>21)&0x1f; + op2 = (src >> 21) & 0x1f; if (op2 & 0x10) { type = OTHER; - if (gte_handlers[source[i]&0x3f]!=NULL) { + if (gte_handlers[src & 0x3f] != NULL) { #ifdef DISASM - if (gte_regnames[source[i]&0x3f]!=NULL) - strcpy(insn[i],gte_regnames[source[i]&0x3f]); + if (gte_regnames[src & 0x3f] != NULL) + strcpy(insn[i], gte_regnames[src & 0x3f]); else - snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); + snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f); #endif type = C2OP; } @@ -6735,7 +6728,7 @@ static noinline void pass1_disassemble(u_int pagelimit) } break; case 0x13: set_mnemonic(i, "COP3"); - op2=(source[i]>>21)&0x1f; + op2 = (src >> 21) & 0x1f; break; case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; @@ -6752,7 +6745,7 @@ static noinline void pass1_disassemble(u_int pagelimit) case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; case 0x3B: - if (Config.HLE && (source[i] & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) { + if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) { set_mnemonic(i, "HLECALL"); type = HLECALL; } @@ -6761,7 +6754,7 @@ static noinline void pass1_disassemble(u_int pagelimit) break; } if (type == INTCALL) - SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start); + SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start); dops[i].itype=type; dops[i].opcode2=op2; /* Get registers/immediates */ @@ -6773,33 +6766,33 @@ static noinline void pass1_disassemble(u_int pagelimit) dops[i].rt2 = 0; switch(type) { case LOAD: - dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rt1=(source[i]>>16)&0x1f; - cinfo[i].imm=(short)source[i]; + dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rt1 = (src >> 16) & 0x1f; + cinfo[i].imm = (short)src; break; case STORE: case STORELR: - dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rs2=(source[i]>>16)&0x1f; - cinfo[i].imm=(short)source[i]; + dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rs2 = (src >> 16) & 0x1f; + cinfo[i].imm = (short)src; break; case LOADLR: // LWL/LWR only load part of the register, // therefore the target register must be treated as a source too - dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rs2=(source[i]>>16)&0x1f; - dops[i].rt1=(source[i]>>16)&0x1f; - cinfo[i].imm=(short)source[i]; + dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rs2 = (src >> 16) & 0x1f; + dops[i].rt1 = (src >> 16) & 0x1f; + cinfo[i].imm = (short)src; break; case IMM16: if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register - else dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rs2=0; - dops[i].rt1=(source[i]>>16)&0x1f; + else dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rs2 = 0; + dops[i].rt1 = (src >> 16) & 0x1f; if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI - cinfo[i].imm=(unsigned short)source[i]; + cinfo[i].imm = (unsigned short)src; }else{ - cinfo[i].imm=(short)source[i]; + cinfo[i].imm = (short)src; } break; case UJUMP: @@ -6810,36 +6803,36 @@ static noinline void pass1_disassemble(u_int pagelimit) dops[i].rs2=CCREG; break; case RJUMP: - dops[i].rs1=(source[i]>>21)&0x1f; + dops[i].rs1 = (src >> 21) & 0x1f; // The JALR instruction writes to rd. if (op2&1) { - dops[i].rt1=(source[i]>>11)&0x1f; + dops[i].rt1 = (src >> 11) & 0x1f; } dops[i].rs2=CCREG; break; case CJUMP: - dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rs2=(source[i]>>16)&0x1f; + dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rs2 = (src >> 16) & 0x1f; if(op&2) { // BGTZ/BLEZ dops[i].rs2=0; } break; case SJUMP: - dops[i].rs1=(source[i]>>21)&0x1f; - dops[i].rs2=CCREG; + dops[i].rs1 = (src >> 21) & 0x1f; + dops[i].rs2 = CCREG; if (op2 == 0x10 || op2 == 0x11) { // BxxAL dops[i].rt1 = 31; // NOTE: If the branch is not taken, r31 is still overwritten } break; case ALU: - dops[i].rs1=(source[i]>>21)&0x1f; // source - dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount - dops[i].rt1=(source[i]>>11)&0x1f; // destination + dops[i].rs1=(src>>21)&0x1f; // source + dops[i].rs2=(src>>16)&0x1f; // subtract amount + dops[i].rt1=(src>>11)&0x1f; // destination break; case MULTDIV: - dops[i].rs1=(source[i]>>21)&0x1f; // source - dops[i].rs2=(source[i]>>16)&0x1f; // divisor + dops[i].rs1=(src>>21)&0x1f; // source + dops[i].rs2=(src>>16)&0x1f; // divisor dops[i].rt1=HIREG; dops[i].rt2=LOREG; break; @@ -6848,30 +6841,29 @@ static noinline void pass1_disassemble(u_int pagelimit) if(op2==0x11) dops[i].rt1=HIREG; // MTHI if(op2==0x12) dops[i].rs1=LOREG; // MFLO if(op2==0x13) dops[i].rt1=LOREG; // MTLO - if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx - if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx + if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx + if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx break; case SHIFT: - dops[i].rs1=(source[i]>>16)&0x1f; // target of shift - dops[i].rs2=(source[i]>>21)&0x1f; // shift amount - dops[i].rt1=(source[i]>>11)&0x1f; // destination + dops[i].rs1=(src>>16)&0x1f; // target of shift + dops[i].rs2=(src>>21)&0x1f; // shift amount + dops[i].rt1=(src>>11)&0x1f; // destination break; case SHIFTIMM: - dops[i].rs1=(source[i]>>16)&0x1f; + dops[i].rs1=(src>>16)&0x1f; dops[i].rs2=0; - dops[i].rt1=(source[i]>>11)&0x1f; - cinfo[i].imm=(source[i]>>6)&0x1f; + dops[i].rt1=(src>>11)&0x1f; + cinfo[i].imm=(src>>6)&0x1f; break; case COP0: - if(op2==0) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0 - if(op2==4) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0 - if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status + if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0 + if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0 + if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG; break; case COP2: - if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2 - if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2 - dops[i].rs2=CSREG; - int gr=(source[i]>>11)&0x1F; + if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2 + if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2 + int gr=(src>>11)&0x1F; switch(op2) { case 0x00: gte_rs[i]=1ll<>21)&0x1F; - cinfo[i].imm=(short)source[i]; - if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2 - else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2 + dops[i].rs1=(src>>21)&0x1F; + cinfo[i].imm=(short)src; + if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2 + else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2 break; case C2OP: - gte_rs[i]=gte_reg_reads[source[i]&0x3f]; - gte_rt[i]=gte_reg_writes[source[i]&0x3f]; + gte_rs[i]=gte_reg_reads[src&0x3f]; + gte_rt[i]=gte_reg_writes[src&0x3f]; gte_rt[i]|=1ll<<63; // every op changes flags - if((source[i]&0x3f)==GTE_MVMVA) { - int v = (source[i] >> 15) & 3; + if((src&0x3f)==GTE_MVMVA) { + int v = (src >> 15) & 3; gte_rs[i]&=~0xe3fll; if(v==3) gte_rs[i]|=0xe00ll; else gte_rs[i]|=3ll<<(v*2); @@ -6905,6 +6897,22 @@ static noinline void pass1_disassemble(u_int pagelimit) default: break; } +} + +static noinline void pass1_disassemble(u_int pagelimit) +{ + int i, j, done = 0, ni_count = 0; + + for (i = 0; !done; i++) + { + int force_j_to_interpreter = 0; + unsigned int type, op, op2; + + disassemble_one(i, source[i]); + type = dops[i].itype; + op = dops[i].opcode; + op2 = dops[i].opcode2; + /* Calculate branch target addresses */ if(type==UJUMP) cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4); @@ -6950,14 +6958,30 @@ static noinline void pass1_disassemble(u_int pagelimit) SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start); force_j_to_interpreter = 1; } - // basic load delay detection through a branch + // load delay detection through a branch else if (dops[i].is_delay_load && dops[i].rt1 != 0) { - int t=(cinfo[i-1].ba-start)/4; - if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) { + const struct decoded_insn *dop = NULL; + int t = -1; + if (cinfo[i-1].ba != -1) { + t = (cinfo[i-1].ba - start) / 4; + if (t < 0 || t > i) { + u_int limit = 0; + u_int *mem = get_source_start(cinfo[i-1].ba, &limit); + if (mem != NULL) { + disassemble_one(MAXBLOCK - 1, mem[0]); + dop = &dops[MAXBLOCK - 1]; + } + } + else + dop = &dops[t]; + } + if ((dop && is_ld_use_hazard(dops[i].rt1, dop)) + || (!dop && Config.PreciseExceptions)) { // jump target wants DS result - potential load delay effect SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start); force_j_to_interpreter = 1; - dops[t+1].bt=1; // expected return from interpreter + if (0 <= t && t < i) + dops[t + 1].bt = 1; // expected return from interpreter } else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& !(i>=3&&dops[i-3].is_jump)) { @@ -6967,8 +6991,9 @@ static noinline void pass1_disassemble(u_int pagelimit) } } } - else if (i > 0 && dops[i-1].is_delay_load && dops[i-1].rt1 != 0 - && (dops[i].rs1 == dops[i-1].rt1 || dops[i].rs2 == dops[i-1].rt1)) { + else if (i > 0 && dops[i-1].is_delay_load + && is_ld_use_hazard(dops[i-1].rt1, &dops[i]) + && (i < 2 || !dops[i-2].is_ujump)) { SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--) if (dops[j-1].rt1 != dops[i-1].rt1) @@ -6976,13 +7001,20 @@ static noinline void pass1_disassemble(u_int pagelimit) force_j_to_interpreter = 1; } if (force_j_to_interpreter) { - memset(&dops[j], 0, sizeof(dops[j])); - dops[j].itype = INTCALL; - dops[j].rs1 = CCREG; - cinfo[j].ba = -1; + force_intcall(j); done = 2; i = j; // don't compile the problematic branch/load/etc } + if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) { + SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start); + i--; + force_intcall(i); + done = 2; + } + if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12 + dops[i].bt = 1; + if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13 + dops[i].bt = 1; /* Is this the end of the block? */ if (i > 0 && dops[i-1].is_ujump) { @@ -7350,8 +7382,6 @@ static noinline void pass3_register_alloc(u_int addr) if (dops[i].rt1!=0) { alloc_reg(¤t,i,dops[i].rt1); dirty_reg(¤t,dops[i].rt1); - assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1); - assert(dops[i+1].rt1!=dops[i].rt1); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif @@ -7937,7 +7967,7 @@ static noinline void pass4_cull_unused_regs(void) } } // Cycle count is needed at branches. Assume it is needed at the target too. - if(i==0||dops[i].bt||dops[i].itype==CJUMP) { + if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) { if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<pc; @@ -178,6 +178,7 @@ index be15f782..6f07478f 100644 regs->code = fetch(regs, memRLUT, pc); psxBSC[regs->code >> 26](regs, regs->code); + psxRegs.cycle += 2; ++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check } static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { @@ -188,15 +189,16 @@ index be15f782..6f07478f 100644 dloadStep(regs); if (execBreakCheck(regs, pc)) -@@ -1195,6 +1198,7 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { +@@ -1187,6 +1191,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { regs->pc += 4; regs->code = fetch(regs, memRLUT, pc); psxBSC[regs->code >> 26](regs, regs->code); + psxRegs.cycle += 2; ++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check } static void intExecute() { -@@ -1224,6 +1228,30 @@ void intExecuteBlock(enum blockExecCaller caller) { +@@ -1216,6 +1222,30 @@ void intExecuteBlock(enum blockExecCaller caller) { execI_(memRLUT, regs_); } @@ -227,7 +229,7 @@ index be15f782..6f07478f 100644 static void intClear(u32 Addr, u32 Size) { } -@@ -1271,7 +1299,7 @@ void intApplyConfig() { +@@ -1263,7 +1293,7 @@ void intApplyConfig() { assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c index e212d8a9..f473ddf6 100644 --- a/libpcsxcore/psxinterpreter.c +++ b/libpcsxcore/psxinterpreter.c @@ -1340,6 +1340,7 @@ static void intShutdown() { } // single step (may do several ops in case of a branch or load delay) +// called by asm/dynarec void execI(psxRegisters *regs) { do { execIbp(psxMemRLUT, regs);