From: kub Date: Fri, 28 Oct 2022 19:55:40 +0000 (+0000) Subject: 32x, reset handling and synchronization changes X-Git-Tag: v2.00~273 X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=eb990fd62a7a657c21679afd9918e2d615c3e90e;p=picodrive.git 32x, reset handling and synchronization changes --- diff --git a/pico/32x/32x.c b/pico/32x/32x.c index dad13616..f7654360 100644 --- a/pico/32x/32x.c +++ b/pico/32x/32x.c @@ -212,6 +212,7 @@ void PicoReset32x(void) p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, SekCyclesDone()); p32x_pwm_ctl_changed(); p32x_timers_recalc(); + Pico32x.vdp_regs[0] &= ~P32XV_Mx; // 32X graphics disabled } } diff --git a/pico/32x/memory.c b/pico/32x/memory.c index cb533d5f..7a61e89e 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -59,7 +59,7 @@ static void (*m68k_write16_io)(u32 a, u32 d); #define REG8IN16(ptr, offs) ((u8 *)ptr)[MEM_BE2(offs)] // poll detection -#define POLL_THRESHOLD 9 // cosmic carnage +#define POLL_THRESHOLD 9 // Primal Rage static struct { u32 addr1, addr2, cycles; @@ -203,7 +203,7 @@ static NOINLINE u32 sh2_poll_read(u32 a, u32 d, unsigned int cycles, SH2* sh2) idx = (idx+1) % PFIFO_SZ; if (cpu != p->cpu) { - if (CYCLES_GT(cycles, p->cycles+80)) { + if (CYCLES_GT(cycles, p->cycles+60)) { // ~180 sh2 cycles, Spiderman // drop older fifo stores that may cause synchronisation problems. p->a = -1; } else if (p->a == a) { @@ -1694,23 +1694,6 @@ static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2) } #endif -static NOINLINE void REGPARM(3) sh2_write8_sdram_sync(u32 a, u32 d, SH2 *sh2) -{ - DRC_SAVE_SR(sh2); - sh2_end_run(sh2, 32); - DRC_RESTORE_SR(sh2); - sh2_write8_sdram(a, d, sh2); -} - -static void REGPARM(3) sh2_write8_sdram_wt(u32 a, u32 d, SH2 *sh2) -{ - // xmen sync hack.. - if ((a << 8) >> 17) // ((a & 0x00ffffff) < 0x200) - sh2_write8_sdram(a, d, sh2); - else - sh2_write8_sdram_sync(a, d, sh2); -} - // write16 static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2) { @@ -2403,7 +2386,6 @@ void PicoMemSetup32x(void) msh2_read16_map[0x06/2].addr = msh2_read16_map[0x26/2].addr = msh2_read32_map[0x06/2].addr = msh2_read32_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram); msh2_write8_map[0x06/2] = msh2_write8_map[0x26/2] = sh2_write8_sdram; - msh2_write8_map[0x26/2] = sh2_write8_sdram_wt; msh2_write16_map[0x06/2] = msh2_write16_map[0x26/2] = sh2_write16_sdram; msh2_write32_map[0x06/2] = msh2_write32_map[0x26/2] = sh2_write32_sdram; diff --git a/pico/pico.c b/pico/pico.c index e924cc10..bc06d7b1 100644 --- a/pico/pico.c +++ b/pico/pico.c @@ -192,6 +192,9 @@ int PicoReset(void) SekFinishIdleDet(); + if (PicoIn.opt & POPT_EN_32X) + PicoReset32x(); + if (PicoIn.AHW & PAHW_MCD) { PicoResetMCD(); return 0; @@ -201,9 +204,6 @@ int PicoReset(void) if (!(PicoIn.opt & POPT_DIS_IDLE_DET)) SekInitIdleDet(); - if (PicoIn.opt & POPT_EN_32X) - PicoReset32x(); - // reset sram state; enable sram access by default if it doesn't overlap with ROM Pico.m.sram_reg = 0; if ((Pico.sv.flags & SRF_EEPROM) || Pico.romsize <= Pico.sv.start)