From 9e1fa0a6cf997b9e4ad38a532d6a9628253fefa7 Mon Sep 17 00:00:00 2001 From: notaz Date: Sat, 17 Aug 2013 22:46:07 +0300 Subject: [PATCH] 32x: improve interrupt handling ..hopefully.. --- pico/32x/32x.c | 40 ++++++++++++++++++++++++++------- pico/32x/memory.c | 57 ++++++++++++++++++++++++++--------------------- pico/32x/pwm.c | 11 +++++---- pico/pico_int.h | 3 +++ 4 files changed, 74 insertions(+), 37 deletions(-) diff --git a/pico/32x/32x.c b/pico/32x/32x.c index 0d56b98..0eb2974 100644 --- a/pico/32x/32x.c +++ b/pico/32x/32x.c @@ -39,13 +39,13 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) m68k_cycles = sh2_cycles_done_m68k(active_sh2); // msh2 - irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES); + irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0]; while ((irqs >>= 1)) mlvl++; mlvl *= 2; // ssh2 - irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES); + irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1]; while ((irqs >>= 1)) slvl++; slvl *= 2; @@ -67,6 +67,33 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles) elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun); } +// the mask register is inconsistent, CMD is supposed to be a mask, +// while others are actually irq trigger enables? +// TODO: test on hw.. +void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask) +{ + Pico32x.sh2irqs |= mask & P32XI_VRES; + Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3); + Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3); + + p32x_update_irls(sh2, m68k_cycles); +} + +void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles) +{ + if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1)) + Pico32x.sh2irqi[0] |= P32XI_CMD; + else + Pico32x.sh2irqi[0] &= ~P32XI_CMD; + + if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2)) + Pico32x.sh2irqi[1] |= P32XI_CMD; + else + Pico32x.sh2irqi[1] &= ~P32XI_CMD; + + p32x_update_irls(sh2, m68k_cycles); +} + void Pico32xStartup(void) { elprintf(EL_STATUS|EL_32X, "32X startup"); @@ -174,8 +201,7 @@ void PicoReset32x(void) { if (PicoAHW & PAHW_32X) { msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT(); - Pico32x.sh2irqs |= P32XI_VRES; - p32x_update_irls(NULL, SekCyclesDoneT2()); + p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES); p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0); p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0); p32x_pwm_ctl_changed(); @@ -222,8 +248,7 @@ static void p32x_start_blank(void) Pico32xSwapDRAM(Pico32x.pending_fb ^ 1); } - Pico32x.sh2irqs |= P32XI_VINT; - p32x_update_irls(NULL, SekCyclesDoneT2()); + p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT); p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0); p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0); } @@ -265,8 +290,7 @@ static void fillend_event(unsigned int now) static void hint_event(unsigned int now) { - Pico32x.sh2irqs |= P32XI_HINT; - p32x_update_irls(NULL, now); + p32x_trigger_irq(NULL, now, P32XI_HINT); p32x_schedule_hint(NULL, now); } diff --git a/pico/32x/memory.c b/pico/32x/memory.c index 5d882e3..a6c977b 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -212,7 +212,7 @@ static u32 p32x_reg_read16(u32 a) unsigned int cycles = SekCyclesDoneT(); if (cycles - msh2.m68krcycles_done > 64) p32x_sync_sh2s(cycles); - return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); + goto out; } if ((a & 0x30) == 0x30) @@ -269,21 +269,11 @@ static void p32x_reg_write8(u32 a, u32 d) case 0x02: // ignored, always 0 return; case 0x03: // irq ctl - if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) { - p32x_sync_sh2s(SekCyclesDoneT()); - if (d & 1) - Pico32x.sh2irqi[0] |= P32XI_CMD; - else - Pico32x.sh2irqi[0] &= ~P32XI_CMD; - p32x_update_irls(NULL, SekCyclesDoneT2()); - } - if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) { - p32x_sync_sh2s(SekCyclesDoneT()); - if (d & 2) - Pico32x.sh2irqi[1] |= P32XI_CMD; - else - Pico32x.sh2irqi[1] &= ~P32XI_CMD; - p32x_update_irls(NULL, SekCyclesDoneT2()); + if ((d ^ r[0x02 / 2]) & 3) { + int cycles = SekCyclesDoneT(); + p32x_sync_sh2s(cycles); + r[0x02 / 2] = d & 3; + p32x_update_cmd_irq(NULL, cycles); } return; case 0x04: // ignored, always 0 @@ -625,8 +615,9 @@ static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2) static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2) { - a &= 0xff; + u32 old; + a &= 0xff; sh2->poll_addr = 0; switch (a) { @@ -635,14 +626,20 @@ static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2) Pico32x.regs[0] |= (d << 8) & P32XS_FM; return; case 1: // HEN/irq masks + old = Pico32x.sh2irq_mask[sh2->is_slave]; + if ((d ^ old) & 1) + p32x_pwm_sync_to_sh2(sh2); + Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x0f; Pico32x.sh2_regs[0] &= ~0x80; Pico32x.sh2_regs[0] |= d & 0x80; - if (d & 1) + + if ((d ^ old) & 1) p32x_pwm_schedule_sh2(sh2); - if (d & 4) + if ((old ^ d) & 2) + p32x_update_cmd_irq(sh2, 0); + if ((old ^ d) & 4) p32x_schedule_hint(sh2, 0); - p32x_update_irls(sh2, 0); return; case 5: // H count d &= 0xff; @@ -702,12 +699,22 @@ static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2) Pico32x.regs[0] &= ~P32XS_FM; Pico32x.regs[0] |= d & P32XS_FM; break; - case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; - case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; - case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; - case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls; + case 0x14: + Pico32x.sh2irqs &= ~P32XI_VRES; + goto irls; + case 0x16: + Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_VINT; + goto irls; + case 0x18: + Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_HINT; + goto irls; + case 0x1a: + Pico32x.regs[2 / 2] &= ~(1 << sh2->is_slave); + p32x_update_cmd_irq(sh2, 0); + return; case 0x1c: - Pico32x.sh2irqs &= ~P32XI_PWM; + p32x_pwm_sync_to_sh2(sh2); + Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_PWM; p32x_pwm_schedule_sh2(sh2); goto irls; } diff --git a/pico/32x/pwm.c b/pico/32x/pwm.c index 6fe7954..97edb9e 100644 --- a/pico/32x/pwm.c +++ b/pico/32x/pwm.c @@ -31,8 +31,7 @@ void p32x_pwm_ctl_changed(void) static void do_pwm_irq(SH2 *sh2, unsigned int m68k_cycles) { - Pico32x.sh2irqs |= P32XI_PWM; - p32x_update_irls(sh2, m68k_cycles); + p32x_trigger_irq(sh2, m68k_cycles, P32XI_PWM); if (Pico32x.regs[0x30 / 2] & P32XP_RTP) { p32x_event_schedule(m68k_cycles, P32X_EVENT_PWM, pwm_cycles / 3 + 1); @@ -105,8 +104,6 @@ static int p32x_pwm_schedule_(SH2 *sh2, unsigned int m68k_now) if (cycles_diff_sh2 >= pwm_cycles) consume_fifo_do(sh2, m68k_now, cycles_diff_sh2); - if (Pico32x.sh2irqs & P32XI_PWM) - return 0; // previous not acked if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1)) return 0; // masked by everyone @@ -129,6 +126,12 @@ void p32x_pwm_schedule_sh2(SH2 *sh2) p32x_event_schedule_sh2(sh2, P32X_EVENT_PWM, after); } +void p32x_pwm_sync_to_sh2(SH2 *sh2) +{ + int m68k_cycles = sh2_cycles_done_m68k(sh2); + consume_fifo(sh2, m68k_cycles); +} + void p32x_pwm_irq_event(unsigned int m68k_now) { p32x_pwm_schedule(m68k_now); diff --git a/pico/pico_int.h b/pico/pico_int.h index 8a760c6..e71245a 100644 --- a/pico/pico_int.h +++ b/pico/pico_int.h @@ -763,6 +763,8 @@ void Pico32xStateLoaded(int is_early); void p32x_sync_sh2s(unsigned int m68k_target); void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target); void p32x_update_irls(SH2 *active_sh2, int m68k_cycles); +void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask); +void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles); void p32x_reset_sh2s(void); void p32x_event_schedule(unsigned int now, enum p32x_event event, int after); void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after); @@ -803,6 +805,7 @@ void p32x_pwm_update(int *buf32, int length, int stereo); void p32x_pwm_ctl_changed(void); void p32x_pwm_schedule(unsigned int m68k_now); void p32x_pwm_schedule_sh2(SH2 *sh2); +void p32x_pwm_sync_to_sh2(SH2 *sh2); void p32x_pwm_irq_event(unsigned int m68k_now); void p32x_pwm_state_loaded(void); -- 2.39.2