From 03c5768cb5cb2cd8a7ea3e4383fd10065d27970e Mon Sep 17 00:00:00 2001 From: notaz Date: Thu, 5 Jul 2007 20:25:06 +0000 Subject: [PATCH] bugfixes, test_misc2, checkpc options git-svn-id: file:///home/notaz/opt/svn/PicoDrive@181 be3aeb3a-fb24-0410-a615-afba39da0efa --- cpu/Cyclone/Cyclone.txt | 17 +++- cpu/Cyclone/Ea.cpp | 11 +-- cpu/Cyclone/OpArith.cpp | 39 +++++----- cpu/Cyclone/OpBranch.cpp | 67 ++++++++++------ cpu/Cyclone/OpLogic.cpp | 79 ++++++++++--------- cpu/Cyclone/OpMove.cpp | 20 ++--- cpu/Cyclone/config.h | 17 +++- cpu/Cyclone/tests/test_misc2_gen.c | 120 +++++++++++++++++++++++++++++ 8 files changed, 267 insertions(+), 103 deletions(-) create mode 100644 cpu/Cyclone/tests/test_misc2_gen.c diff --git a/cpu/Cyclone/Cyclone.txt b/cpu/Cyclone/Cyclone.txt index 6e4749d8..4858b181 100644 --- a/cpu/Cyclone/Cyclone.txt +++ b/cpu/Cyclone/Cyclone.txt @@ -14,11 +14,11 @@ ___________________________________________________________________________ Cyclone 68000 (c) Copyright 2004 Dave. Free for non-commercial use Homepage: http://www.finalburn.com/ - Dave's e-mail: dev(atsymbol)finalburn.com + Dave's e-mail: emudave(atsymbol)googlemail.com Replace (atsymbol) with @ - Additional coding and bugfixes done by notaz, 2005, 2006 - Homepage: http://mif.vu.lt/~grig2790/Cyclone/ + Additional coding and bugfixes done by notaz, 2005-2007 + Homepage: http://mif.vu.lt/~grig2790/Cyclone/ , http://notaz.gp2x.de e-mail: notasas(atsymbol)gmail.com ___________________________________________________________________________ @@ -35,6 +35,17 @@ Flags are mapped onto ARM flags whenever possible, which speeds up the processin What's New ---------- +v0.0087 notaz + - Reduced amount of code in opcode handlers by ~23% by doing the following: + - Removed duplicate opcode handlers + - Optimized code to use less ARM instructions + - Merged some duplicate handler endings + + Cyclone now does better job avoiding pipeline interlocks. + + Replaced incorrect handler of DBT with proper one. + + Fixed "MOVEA (An)+ An" behaviour. + + Fixed flags for ROXR and LSR. Hopefully got them right now. + + Additional functionality added for MAME and other ports (see config.h). + v0.0086 notaz + Cyclone now can be customized to better suit your project, see config.h . + Added an option to compress the jumptable at compile-time. Must call CycloneInit() diff --git a/cpu/Cyclone/Ea.cpp b/cpu/Cyclone/Ea.cpp index 8b103c93..35f0048a 100644 --- a/cpu/Cyclone/Ea.cpp +++ b/cpu/Cyclone/Ea.cpp @@ -98,11 +98,12 @@ static int EaCalcReg(int r,int ea,int mask,int forceor,int shift,int noshift=0) for (i=mask|0x8000; (i&1)==0; i>>=1) low++; // Find out how high up the EA mask is mask&=0xf<=8) needor=1; // Need to OR to access A0-7 - - if (((mask&g_op)>>low)&8) needor=0; // Ah - no we don't actually need to or, since the bit is high in r8 - - if (forceor) needor=1; // Special case for 0x30-0x38 EAs ;) + if (ea>=8) + { + needor=1; // Need to OR to access A0-7 + if ((g_op>>low)&8) { needor=0; mask|=8<=2&&(op&0xff00)==0x6200) { ot("BccDontBranch%i%s\n", 8<>9; dir = (op>>7)&1; // Find size extension @@ -522,7 +522,7 @@ int OpMovep(int op) OpStart(op,ea); if(dir) { // reg to mem - EaCalcReadNoSE(-1,11,rea,size,0x1e00); + EaCalcReadNoSE(-1,11,rea,size,0x0e00); EaCalc(10,0x000f,ea,size); if(size==2) { // if operand is long diff --git a/cpu/Cyclone/config.h b/cpu/Cyclone/config.h index b10ee423..3af4103b 100644 --- a/cpu/Cyclone/config.h +++ b/cpu/Cyclone/config.h @@ -27,7 +27,7 @@ * Warning: if you enable this, you MUST call CycloneInit() before calling * CycloneRun(), or else it will crash. */ -#define COMPRESS_JUMPTABLE 1 +#define COMPRESS_JUMPTABLE 0 /* * Address mask for memory hadlers. The bits set will be masked out of address @@ -107,10 +107,23 @@ */ #define USE_CHECKPC_CALLBACK 1 +/* + * This determines if checkpc() should be called after jumps when 8 and 16 bit + * displacement values were used. + */ +#define USE_CHECKPC_OFFSETBITS_16 1 +#define USE_CHECKPC_OFFSETBITS_8 0 + +/* + * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to + * 0.0087 never did that. + */ +#define USE_CHECKPC_DBRA 0 + /* * When this option is enabled Cyclone will do two word writes instead of one * long write when handling MOVE.L with pre-decrementing destination, as described in * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt). * Enable this if you are emulating a 16 bit system. */ -#define SPLIT_MOVEL_PD 1 +#define SPLIT_MOVEL_PD 0 diff --git a/cpu/Cyclone/tests/test_misc2_gen.c b/cpu/Cyclone/tests/test_misc2_gen.c new file mode 100644 index 00000000..8341ea4b --- /dev/null +++ b/cpu/Cyclone/tests/test_misc2_gen.c @@ -0,0 +1,120 @@ +#include +#include +#include + + +static FILE *f; + +#define bswap16(x) (x=(unsigned short)((x<<8)|(x>>8))) +#define bswap32(x) (x=((x<<24)|((x<<8)&0xff0000)|((x>>8)&0x00ff00)|((unsigned)x>>24))) + +static void write_op(unsigned short op, unsigned short word0, unsigned short word1, unsigned short word2) +{ + bswap16(op); + bswap16(word0); + bswap16(word1); + bswap16(word2); + + fwrite(&op, 1, sizeof(op), f); + fwrite(&word0, 1, sizeof(word0), f); + fwrite(&word1, 1, sizeof(word1), f); + fwrite(&word2, 1, sizeof(word2), f); +} + +static void write32(unsigned int a) +{ + bswap32(a); + fwrite(&a, 1, sizeof(a), f); +} + +static int op_check(unsigned short op) +{ + if ((op&0xf000) == 0x6000) return 0; // Bxx + if ((op&0xf0f8) == 0x50c8) return 0; // DBxx + if ((op&0xff80) == 0x4e80) return 0; // Jsr + if ((op&0xf000) == 0xa000) return 0; // a-line + if ((op&0xf000) == 0xf000) return 0; // f-line + if ((op&0xfff8)==0x4e70&&op!=0x4e71&&op!=0x4e76) return 0; // reset, rte, rts + + if ((op&0x3f) >= 0x28) op = (op&~0x3f) | (rand() % 0x28); + return 1; +} + +static unsigned short safe_rand(void) +{ + unsigned short op; + + /* avoid branch opcodes */ + do + { + op = rand(); + } + while (!op_check(op)); + + return op; +} + +int main() +{ + int i, op; + + srand(time(0)); + + f = fopen("test_misc2.bin", "wb"); + if (!f) return 1; + + write32(0x00ff8000); // stack + write32(0x300); // IP + + for (i=0x100/4-2; i; i--) + { + write32(0x200+i*4); // exception vectors + } + + for (i=0x100/4; i; i--) + { + write32(0); // pad + } + + for (i=0x100/4; i; i--) + { + write32(0x4e734e73); // fill with rte instructions + } + + for (op = 0; op < 0x10000; op++) + { + if ((op&0xf000) == 0x6000) // Bxx + { + if ((op&0x00ff) == 0) + write_op(op, 6, 0, 0); + else if ((op&0x00ff) == 0xff) + write_op(op, 0, 6, 0); + } + else if ((op&0xf0f8)==0x50c8) // DBxx + { + write_op(op, 6, 0, 0); + } + else if ((op&0xff80)==0x4e80) // Jsr + { + int addr = 0x300 + i*8 + 8; + if ((op&0x3f) == 0x39) + write_op(op, addr >> 16, addr & 0xffff, 0); + } + else if ((op&0xf000)==0xa000 || (op&0xf000)==0xf000) // a-line, f-line + { + if (op != 0xa000 && op != 0xf000) continue; + } + else if ((op&0xfff8)==0x4e70&&op!=0x4e71&&op!=0x4e76); // rte, rts, stop, reset + else + { + write_op(op, safe_rand(), safe_rand(), safe_rand()); + } + } + + // jump to the beginning + write_op(0x4ef8, 0x300, 0, 0); + + fclose(f); + return 0; +} + -- 2.39.5