From 2b540629bca02d96eab845f47afddf929abbfcce Mon Sep 17 00:00:00 2001
From: notaz <notasas@gmail.com>
Date: Mon, 21 Oct 2024 00:38:07 +0300
Subject: [PATCH] 3ds: update ctr_clear_cache

DMB looks insufficient before invalidate, also doesn't match what Linux
does, so adjust. Hopefully will solve some weird rare crashes.
---
 frontend/3ds/3ds_utils.h |  4 ++--
 frontend/3ds/utils.S     | 24 +++++++++++++++++++++---
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/frontend/3ds/3ds_utils.h b/frontend/3ds/3ds_utils.h
index f7c8ddc2..25bcc42a 100644
--- a/frontend/3ds/3ds_utils.h
+++ b/frontend/3ds/3ds_utils.h
@@ -17,6 +17,8 @@
 #define DEBUG_HOLD() do{printf("%s@%s:%d.\n",__FUNCTION__, __FILE__, __LINE__);fflush(stdout);wait_for_input();}while(0)
 
 void wait_for_input(void);
+void ctr_clear_cache(void);
+//void ctr_invalidate_icache(void); // only icache
 
 extern __attribute__((weak)) int  __ctr_svchax;
 
@@ -36,8 +38,6 @@ static inline void check_rosalina() {
   }
 }
 
-void ctr_clear_cache(void);
-
 typedef int32_t (*ctr_callback_type)(void);
 
 static inline void ctr_invalidate_ICache_kernel(void)
diff --git a/frontend/3ds/utils.S b/frontend/3ds/utils.S
index c8df651a..61da1554 100644
--- a/frontend/3ds/utils.S
+++ b/frontend/3ds/utils.S
@@ -7,9 +7,8 @@ ctr_clear_cache_kernel:
   cpsid aif
   mov r0, #0
   mcr p15, 0, r0, c7, c10, 0    @ Clean entire data cache
-  mcr p15, 0, r0, c7, c10, 5    @ Data Memory Barrier
-  mcr p15, 0, r0, c7, c5, 0     @ Invalidate entire instruction cache / Flush BTB
   mcr p15, 0, r0, c7, c10, 4    @ Data Sync Barrier
+  mcr p15, 0, r0, c7, c5, 0     @ Invalidate entire instruction cache / Flush BTB
   bx lr
   .endfunc
 
@@ -19,7 +18,26 @@ ctr_clear_cache_kernel:
   .global ctr_clear_cache
   .func ctr_clear_cache
 ctr_clear_cache:
-  ldr r0, =ctr_clear_cache_kernel
+  adr r0, ctr_clear_cache_kernel
+  svc 0x80                      @ svcCustomBackdoor
+  bx lr
+  .endfunc
+
+#if 0
+  .func ctr_invalidate_icache_kernel
+ctr_invalidate_icache_kernel:
+  cpsid aif
+  mov r0, #0
+  mcr p15, 0, r0, c7, c10, 4    @ Data Sync Barrier
+  mcr p15, 0, r0, c7, c5, 0     @ Invalidate entire instruction cache / Flush BTB
+  bx lr
+  .endfunc
+
+  .global ctr_invalidate_icache
+  .func ctr_invalidate_icache
+ctr_invalidate_icache:
+  adr r0, ctr_invalidate_icache_kernel
   svc 0x80                      @ svcCustomBackdoor
   bx lr
   .endfunc
+#endif
-- 
2.39.5