From 38b1da12aade33bf94bdbe71a3988db6f57fb012 Mon Sep 17 00:00:00 2001 From: notaz Date: Wed, 21 Sep 2016 02:21:27 +0300 Subject: [PATCH] partially revert c4052f4d79cf See github issue #74 for details. --- libpcsxcore/new_dynarec/assem_arm.c | 4 +--- libpcsxcore/new_dynarec/assem_arm.h | 4 ---- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 3cc3737d..708c8aea 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -30,9 +30,7 @@ #endif #include "arm_features.h" -#ifdef VITA -char* translation_cache = 0; -#elif !BASE_ADDR_FIXED +#if !BASE_ADDR_FIXED char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096))); #endif diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h index da4144dc..22546386 100644 --- a/libpcsxcore/new_dynarec/assem_arm.h +++ b/libpcsxcore/new_dynarec/assem_arm.h @@ -64,10 +64,6 @@ extern char *invc_ptr; // "round" address helpful for debug #define BASE_ADDR 0x1000000 #else -#if defined(VITA) -extern char* translation_cache; -#else extern char translation_cache[1 << TARGET_SIZE_2]; -#endif #define BASE_ADDR (u_int)translation_cache #endif -- 2.39.5