From 503807e3ed3ea54a3c3e9549cdca0e656b79757e Mon Sep 17 00:00:00 2001 From: notaz Date: Wed, 15 Apr 2026 03:05:22 +0300 Subject: [PATCH] drc: try to get out of some unfortunate timing conditions libretro/pcsx_rearmed#920 libretro/pcsx_rearmed#921 --- libpcsxcore/new_dynarec/new_dynarec.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 2c7bb702..39ab8c9a 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -7550,8 +7550,8 @@ static noinline void pass3_register_alloc(struct compile_state *st, u_int addr) current.loadedconst = 0; current.noevict = 0; //current.waswritten = 0; + int cc = 0, cc_raw = 0; int ds=0; - int cc=0; int hr; int i, j; @@ -8073,10 +8073,10 @@ static noinline void pass3_register_alloc(struct compile_state *st, u_int addr) } // Count cycles in between branches - cinfo[i].ccadj = CLOCK_ADJUST(cc); + cinfo[i].ccadj = CLOCK_ADJUST(cc) + cc_raw; if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception)) { - cc=0; + cc = cc_raw = 0; } #if !defined(DRC_DBG) else if(dops[i].itype==C2OP&>e_cycletab[st->source[i]&0x3f]>2) @@ -8084,16 +8084,16 @@ static noinline void pass3_register_alloc(struct compile_state *st, u_int addr) // this should really be removed since the real stalls have been implemented, // but doing so causes sizeable perf regression against the older version u_int gtec = gte_cycletab[st->source[i] & 0x3f]; - cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; + cc_raw += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2; } else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt) { - cc+=4; + cc_raw += 4; } else if(dops[i].itype==C2LS) { // same as with C2OP - cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; + cc_raw += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2; } #endif else -- 2.47.3