From 61124a6d0fb6a2980f9025630382d9b76c07066f Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Fri, 13 Sep 2019 23:09:11 +0200 Subject: [PATCH] Get rid of bit fields in union Long story short, bit fields aren't endian-safe. More info: http://mjfrazer.org/mjfrazer/bitfields/ Simplify that by just using a few macros to access the needed bits. Signed-off-by: Paul Cercueil --- plugins/gpulib/gpu.c | 41 ++++++++++++++++++++++------------------ plugins/gpulib/gpu.h | 38 +++++++++++-------------------------- plugins/gpulib/vout_pl.c | 13 +++++++------ 3 files changed, 41 insertions(+), 51 deletions(-) diff --git a/plugins/gpulib/gpu.c b/plugins/gpulib/gpu.c index f89e52d2..03e341df 100644 --- a/plugins/gpulib/gpu.c +++ b/plugins/gpulib/gpu.c @@ -59,7 +59,7 @@ static noinline void do_reset(void) memset(gpu.regs, 0, sizeof(gpu.regs)); for (i = 0; i < sizeof(gpu.ex_regs) / sizeof(gpu.ex_regs[0]); i++) gpu.ex_regs[i] = (0xe0 + i) << 24; - gpu.status.reg = 0x14802000; + gpu.status = 0x14802000; gpu.gp0 = 0; gpu.regs[3] = 1; gpu.screen.hres = gpu.screen.w = 256; @@ -80,7 +80,7 @@ static noinline void update_height(void) { // TODO: emulate this properly.. int sh = gpu.screen.y2 - gpu.screen.y1; - if (gpu.status.dheight) + if (gpu.status & PSX_GPU_STATUS_DHEIGHT) sh *= 2; if (sh <= 0 || sh > gpu.screen.vres) sh = gpu.screen.vres; @@ -121,7 +121,7 @@ static noinline int decide_frameskip_allow(uint32_t cmd_e3) // but not for interlace since it'll most likely always do that uint32_t x = cmd_e3 & 0x3ff; uint32_t y = (cmd_e3 >> 10) & 0x3ff; - gpu.frameskip.allow = gpu.status.interlace || + gpu.frameskip.allow = (gpu.status & PSX_GPU_STATUS_INTERLACE) || (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w || (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h; return gpu.frameskip.allow; @@ -289,10 +289,14 @@ void GPUwriteStatus(uint32_t data) do_cmd_reset(); break; case 0x03: - gpu.status.blanking = data & 1; + if (data & 1) + gpu.status |= PSX_GPU_STATUS_BLANKING; + else + gpu.status &= ~PSX_GPU_STATUS_BLANKING; break; case 0x04: - gpu.status.dma = data & 3; + gpu.status &= ~PSX_GPU_STATUS_DMA_MASK; + gpu.status |= PSX_GPU_STATUS_DMA(data & 3); break; case 0x05: gpu.screen.x = data & 0x3ff; @@ -316,9 +320,9 @@ void GPUwriteStatus(uint32_t data) update_height(); break; case 0x08: - gpu.status.reg = (gpu.status.reg & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10); - gpu.screen.hres = hres[(gpu.status.reg >> 16) & 7]; - gpu.screen.vres = vres[(gpu.status.reg >> 19) & 3]; + gpu.status = (gpu.status & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10); + gpu.screen.hres = hres[(gpu.status >> 16) & 7]; + gpu.screen.vres = vres[(gpu.status >> 19) & 3]; update_width(); update_height(); renderer_notify_res_change(); @@ -432,7 +436,7 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re renderer_flush_queues(); if (is_read) { - gpu.status.img = 1; + gpu.status |= PSX_GPU_STATUS_IMG; // XXX: wrong for width 1 memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4); gpu.state.last_vram_read_frame = *gpu.state.frame_count; @@ -445,7 +449,7 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re static void finish_vram_transfer(int is_read) { if (is_read) - gpu.status.img = 0; + gpu.status &= ~PSX_GPU_STATUS_IMG; else renderer_update_caches(gpu.dma_start.x, gpu.dma_start.y, gpu.dma_start.w, gpu.dma_start.h); @@ -560,9 +564,9 @@ static noinline int do_cmd_buffer(uint32_t *data, int count) break; } - gpu.status.reg &= ~0x1fff; - gpu.status.reg |= gpu.ex_regs[1] & 0x7ff; - gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11; + gpu.status &= ~0x1fff; + gpu.status |= gpu.ex_regs[1] & 0x7ff; + gpu.status |= (gpu.ex_regs[6] & 3) << 11; gpu.state.fb_dirty |= vram_dirty; @@ -700,7 +704,7 @@ uint32_t GPUreadStatus(void) if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); - ret = gpu.status.reg; + ret = gpu.status; log_io("gpu_read_status %08x\n", ret); return ret; } @@ -726,14 +730,14 @@ long GPUfreeze(uint32_t type, struct GPUFreeze *freeze) memcpy(freeze->psxVRam, gpu.vram, 1024 * 512 * 2); memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs)); memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs)); - freeze->ulStatus = gpu.status.reg; + freeze->ulStatus = gpu.status; break; case 0: // load renderer_sync(); memcpy(gpu.vram, freeze->psxVRam, 1024 * 512 * 2); memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs)); memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs)); - gpu.status.reg = freeze->ulStatus; + gpu.status = freeze->ulStatus; gpu.cmd_len = 0; for (i = 8; i > 0; i--) { gpu.regs[i] ^= 1; // avoid reg change detection @@ -753,7 +757,7 @@ void GPUupdateLace(void) flush_cmd_buffer(); renderer_flush_queues(); - if (gpu.status.blanking) { + if (gpu.status & PSX_GPU_STATUS_BLANKING) { if (!gpu.state.blanked) { vout_blank(); gpu.state.blanked = 1; @@ -785,7 +789,8 @@ void GPUupdateLace(void) void GPUvBlank(int is_vblank, int lcf) { int interlace = gpu.state.allow_interlace - && gpu.status.interlace && gpu.status.dheight; + && (gpu.status & PSX_GPU_STATUS_INTERLACE) + && (gpu.status & PSX_GPU_STATUS_DHEIGHT); // interlace doesn't look nice on progressive displays, // so we have this "auto" mode here for games that don't read vram if (gpu.state.allow_interlace == 2 diff --git a/plugins/gpulib/gpu.h b/plugins/gpulib/gpu.h index d1a3a75b..9f427140 100644 --- a/plugins/gpulib/gpu.h +++ b/plugins/gpulib/gpu.h @@ -19,37 +19,21 @@ extern "C" { #define CMD_BUFFER_LEN 1024 +#define BIT(x) (1 << (x)) + +#define PSX_GPU_STATUS_DHEIGHT BIT(19) +#define PSX_GPU_STATUS_RGB24 BIT(21) +#define PSX_GPU_STATUS_INTERLACE BIT(22) +#define PSX_GPU_STATUS_BLANKING BIT(23) +#define PSX_GPU_STATUS_IMG BIT(27) +#define PSX_GPU_STATUS_DMA(x) ((x) << 29) +#define PSX_GPU_STATUS_DMA_MASK (BIT(29) | BIT(30)) + struct psx_gpu { uint32_t cmd_buffer[CMD_BUFFER_LEN]; uint32_t regs[16]; uint16_t *vram; - union { - uint32_t reg; - struct { - uint32_t tx:4; // 0 texture page - uint32_t ty:1; - uint32_t abr:2; - uint32_t tp:2; // 7 t.p. mode (4,8,15bpp) - uint32_t dtd:1; // 9 dither - uint32_t dfe:1; - uint32_t md:1; // 11 set mask bit when drawing - uint32_t me:1; // 12 no draw on mask - uint32_t unkn:3; - uint32_t width1:1; // 16 - uint32_t width0:2; - uint32_t dheight:1; // 19 double height - uint32_t video:1; // 20 NTSC,PAL - uint32_t rgb24:1; - uint32_t interlace:1; // 22 interlace on - uint32_t blanking:1; // 23 display not enabled - uint32_t unkn2:2; - uint32_t busy:1; // 26 !busy drawing - uint32_t img:1; // 27 ready to DMA image data - uint32_t com:1; // 28 ready for commands - uint32_t dma:2; // 29 off, ?, to vram, from vram - uint32_t lcf:1; // 31 - }; - } status; + uint32_t status; uint32_t gp0; uint32_t ex_regs[8]; struct { diff --git a/plugins/gpulib/vout_pl.c b/plugins/gpulib/vout_pl.c index 064b3490..05da217b 100644 --- a/plugins/gpulib/vout_pl.c +++ b/plugins/gpulib/vout_pl.c @@ -36,7 +36,7 @@ static void check_mode_change(int force) gpu.state.enhancement_active = gpu.get_enhancement_bufer != NULL && gpu.state.enhancement_enable - && w <= 512 && h <= 256 && !gpu.status.rgb24; + && w <= 512 && h <= 256 && !(gpu.status & PSX_GPU_STATUS_RGB24); if (gpu.state.enhancement_active) { w_out *= 2; @@ -53,12 +53,13 @@ static void check_mode_change(int force) } // width|rgb24 change? - if (force || (gpu.status.reg ^ old_status) & ((7<<16)|(1<<21)) || h != old_h) + if (force || (gpu.status ^ old_status) & ((7<<16)|(1<<21)) || h != old_h) { - old_status = gpu.status.reg; + old_status = gpu.status; old_h = h; - cbs->pl_vout_set_mode(w_out, h_out, w, h, gpu.status.rgb24 ? 24 : 16); + cbs->pl_vout_set_mode(w_out, h_out, w, h, + (gpu.status & PSX_GPU_STATUS_RGB24) ? 24 : 16); } } @@ -94,7 +95,7 @@ void vout_update(void) vram += y * 1024 + x; - cbs->pl_vout_flip(vram, 1024, gpu.status.rgb24, w, h); + cbs->pl_vout_flip(vram, 1024, gpu.status & PSX_GPU_STATUS_RGB24, w, h); } void vout_blank(void) @@ -107,7 +108,7 @@ void vout_blank(void) w *= 2; h *= 2; } - cbs->pl_vout_flip(NULL, 1024, gpu.status.rgb24, w, h); + cbs->pl_vout_flip(NULL, 1024, gpu.status & PSX_GPU_STATUS_RGB24, w, h); } long GPUopen(void **unused) -- 2.39.5