From afec9d44d1170fd6391528f4985211ffb00e8bea Mon Sep 17 00:00:00 2001 From: notaz Date: Wed, 10 Nov 2021 23:44:25 +0200 Subject: [PATCH] drc: adjust bogus looking check not really sure what's going on, but at the start of "Pass 3 - Register allocation" zero reg allocations are removed, so "regmap_pre[i+1][hr] != regs[i].regmap[hr]" assert will not hold. --- libpcsxcore/new_dynarec/new_dynarec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 08153298..f2dbb86a 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -166,7 +166,7 @@ struct link_entry static char ooo[MAXBLOCK]; static uint64_t unneeded_reg[MAXBLOCK]; static uint64_t branch_unneeded_reg[MAXBLOCK]; - static signed char regmap_pre[MAXBLOCK][HOST_REGS]; + static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i? static uint64_t current_constmap[HOST_REGS]; static uint64_t constmap[MAXBLOCK][HOST_REGS]; static struct regstat regs[MAXBLOCK]; @@ -7891,7 +7891,7 @@ int new_recompile_block(int addr) { if(i0) if(regmap_pre[i+1][hr]!=regs[i].regmap[hr]) { SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]); -- 2.39.5