From bb0379b73d4d084b713f1d84755eb288bb0d5097 Mon Sep 17 00:00:00 2001 From: notaz Date: Sun, 29 Oct 2023 23:58:03 +0200 Subject: [PATCH] rework memhandlers to deal with some bus details notaz/pcsx_rearmed#327 --- libpcsxcore/new_dynarec/pcsxmem.c | 90 ++- libpcsxcore/psxcounters.c | 6 +- libpcsxcore/psxhw.c | 1009 ++++++++--------------------- libpcsxcore/psxhw.h | 10 +- libpcsxcore/psxinterpreter.c | 8 +- libpcsxcore/psxmem.c | 4 +- libpcsxcore/psxmem.h | 4 +- 7 files changed, 363 insertions(+), 768 deletions(-) diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c index e16f5ee7..e61e8a35 100644 --- a/libpcsxcore/new_dynarec/pcsxmem.c +++ b/libpcsxcore/new_dynarec/pcsxmem.c @@ -75,12 +75,12 @@ static void write_mem_dummy(u32 data) /* IO handlers */ static u32 io_read_sio16() { - return sioRead8() | (sioRead8() << 8); + return sioRead8(); } static u32 io_read_sio32() { - return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24); + return sioRead8(); } static void io_write_sio16(u32 value) @@ -97,6 +97,11 @@ static void io_write_sio32(u32 value) sioWrite8((unsigned char)(value >> 24)); } +static u32 io_read_sio2_status() +{ + return 0x80; +} + #if !defined(DRC_DBG) && defined(__arm__) static void map_rcnt_rcount0(u32 mode) @@ -164,22 +169,6 @@ make_rcnt_funcs(0) make_rcnt_funcs(1) make_rcnt_funcs(2) -#define make_dma_func(n) \ -static void io_write_chcr##n(u32 value) \ -{ \ - HW_DMA##n##_CHCR = value; \ - if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \ - psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \ - } \ -} - -make_dma_func(0) -make_dma_func(1) -make_dma_func(2) -make_dma_func(3) -make_dma_func(4) -make_dma_func(6) - static u32 io_spu_read8_even(u32 addr) { return SPU_readRegister(addr, psxRegs.cycle) & 0xff; @@ -262,6 +251,29 @@ static void write_biu(u32 value) psxRegs.biuReg = value; } +/* scph7001 (pc = 8003de60, v1 = 1f8010f0): + lhu $t9, 0($v1) + li $at, 0xFFF0FFFF + and $t0, $t9, $at + lui $at, 8 + or $t1, $t0, $at + sh $t1, 0($v1) +*/ +#define make_forcew32_func(addr) \ +static void io_write_force32_##addr(u32 value) \ +{ \ + psxHu32ref(0x##addr) = SWAPu32(value); \ +} +make_forcew32_func(1014) +make_forcew32_func(1060) +make_forcew32_func(1080) +make_forcew32_func(1090) +make_forcew32_func(10a0) +make_forcew32_func(10b0) +make_forcew32_func(10c0) +make_forcew32_func(10e0) +make_forcew32_func(10f0) + void new_dyna_pcsx_mem_load_state(void) { map_rcnt_rcount0(rcnts[0].mode); @@ -354,6 +366,7 @@ void new_dyna_pcsx_mem_init(void) } map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); + map_item(&mem_iortab[IOMEM32(0x1044)], sioReadStat16, 1); map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); @@ -373,6 +386,7 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); + map_item(&mem_iortab[IOMEM16(0x1054)], io_read_sio2_status, 1); map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); @@ -400,12 +414,18 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1); map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1); - map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); - map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); - map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); - map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); - map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); - map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); + map_item(&mem_iowtab[IOMEM32(0x1088)], psxHwWriteChcr0, 1); + map_item(&mem_iowtab[IOMEM32(0x108c)], psxHwWriteChcr0, 1); + map_item(&mem_iowtab[IOMEM32(0x1098)], psxHwWriteChcr1, 1); + map_item(&mem_iowtab[IOMEM32(0x109c)], psxHwWriteChcr1, 1); + map_item(&mem_iowtab[IOMEM32(0x10a8)], psxHwWriteChcr2, 1); + map_item(&mem_iowtab[IOMEM32(0x10ac)], psxHwWriteChcr2, 1); + map_item(&mem_iowtab[IOMEM32(0x10b8)], psxHwWriteChcr3, 1); + map_item(&mem_iowtab[IOMEM32(0x10bc)], psxHwWriteChcr3, 1); + map_item(&mem_iowtab[IOMEM32(0x10c8)], psxHwWriteChcr4, 1); + map_item(&mem_iowtab[IOMEM32(0x10cc)], psxHwWriteChcr4, 1); + map_item(&mem_iowtab[IOMEM32(0x10e8)], psxHwWriteChcr6, 1); + map_item(&mem_iowtab[IOMEM32(0x10ec)], psxHwWriteChcr6, 1); map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1); map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); @@ -421,13 +441,35 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); + map_item(&mem_iowtab[IOMEM16(0x1014)], io_write_force32_1014, 1); map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1); map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1); map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); + map_item(&mem_iowtab[IOMEM16(0x1060)], io_write_force32_1060, 1); map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1); map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1); + map_item(&mem_iowtab[IOMEM16(0x1080)], io_write_force32_1080, 1); + map_item(&mem_iowtab[IOMEM16(0x1088)], psxHwWriteChcr0, 1); + map_item(&mem_iowtab[IOMEM16(0x108c)], psxHwWriteChcr0, 1); + map_item(&mem_iowtab[IOMEM16(0x1090)], io_write_force32_1090, 1); + map_item(&mem_iowtab[IOMEM16(0x1098)], psxHwWriteChcr1, 1); + map_item(&mem_iowtab[IOMEM16(0x109c)], psxHwWriteChcr1, 1); + map_item(&mem_iowtab[IOMEM16(0x10a0)], io_write_force32_10a0, 1); + map_item(&mem_iowtab[IOMEM16(0x10a8)], psxHwWriteChcr2, 1); + map_item(&mem_iowtab[IOMEM16(0x10ac)], psxHwWriteChcr2, 1); + map_item(&mem_iowtab[IOMEM16(0x10b0)], io_write_force32_10b0, 1); + map_item(&mem_iowtab[IOMEM16(0x10b8)], psxHwWriteChcr3, 1); + map_item(&mem_iowtab[IOMEM16(0x10bc)], psxHwWriteChcr3, 1); + map_item(&mem_iowtab[IOMEM16(0x10c0)], io_write_force32_10c0, 1); + map_item(&mem_iowtab[IOMEM16(0x10c8)], psxHwWriteChcr4, 1); + map_item(&mem_iowtab[IOMEM16(0x10cc)], psxHwWriteChcr4, 1); + map_item(&mem_iowtab[IOMEM16(0x10e0)], io_write_force32_10e0, 1); + map_item(&mem_iowtab[IOMEM16(0x10e8)], psxHwWriteChcr6, 1); + map_item(&mem_iowtab[IOMEM16(0x10ec)], psxHwWriteChcr6, 1); + map_item(&mem_iowtab[IOMEM16(0x10f0)], io_write_force32_10f0, 1); + map_item(&mem_iowtab[IOMEM16(0x10f4)], psxHwWriteDmaIcr32, 1); map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c index f7491b3d..c6271203 100644 --- a/libpcsxcore/psxcounters.c +++ b/libpcsxcore/psxcounters.c @@ -118,11 +118,7 @@ void verboseLog( u32 level, const char *str, ... ) static inline void _psxRcntWcount( u32 index, u32 value ) { - if( value > 0xffff ) - { - verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value ); - value &= 0xffff; - } + value &= 0xffff; rcnts[index].cycleStart = psxRegs.cycle; rcnts[index].cycleStart -= value * rcnts[index].rate; diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c index f5efa22b..8179d959 100644 --- a/libpcsxcore/psxhw.c +++ b/libpcsxcore/psxhw.c @@ -27,12 +27,6 @@ #include "cdrom.h" #include "gpu.h" -//#undef PSXHW_LOG -//#define PSXHW_LOG printf -#ifndef PAD_LOG -#define PAD_LOG(...) -#endif - static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR; void psxHwReset() { @@ -70,6 +64,23 @@ void psxHwWriteImask(u32 value) psxRegs.CP0.n.Cause |= 0x400; } +#define make_dma_func(n) \ +void psxHwWriteChcr##n(u32 value) \ +{ \ + if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \ + log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \ + HW_DMA##n##_CHCR = SWAPu32(value); \ + if (value & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8u << (n * 4))) \ + psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), value); \ +} + +make_dma_func(0) +make_dma_func(1) +make_dma_func(2) +make_dma_func(3) +make_dma_func(4) +make_dma_func(6) + void psxHwWriteDmaIcr32(u32 value) { u32 tmp = value & 0x00ff803f; @@ -123,763 +134,303 @@ u32 psxHwReadGpuSRbusyHack(void) } u8 psxHwRead8(u32 add) { - unsigned char hard; - - switch (add & 0x1fffffff) { - case 0x1f801040: hard = sioRead8(); break; - case 0x1f801800: hard = cdrRead0(); break; - case 0x1f801801: hard = cdrRead1(); break; - case 0x1f801802: hard = cdrRead2(); break; - case 0x1f801803: hard = cdrRead3(); break; - - case 0x1f801041: case 0x1f801042: case 0x1f801043: - case 0x1f801044: case 0x1f801045: - case 0x1f801046: case 0x1f801047: - case 0x1f801048: case 0x1f801049: - case 0x1f80104a: case 0x1f80104b: - case 0x1f80104c: case 0x1f80104d: - case 0x1f80104e: case 0x1f80104f: - case 0x1f801050: case 0x1f801051: - case 0x1f801054: case 0x1f801055: - case 0x1f801058: case 0x1f801059: - case 0x1f80105a: case 0x1f80105b: - case 0x1f80105c: case 0x1f80105d: - case 0x1f801100: case 0x1f801101: - case 0x1f801104: case 0x1f801105: - case 0x1f801108: case 0x1f801109: - case 0x1f801110: case 0x1f801111: - case 0x1f801114: case 0x1f801115: - case 0x1f801118: case 0x1f801119: - case 0x1f801120: case 0x1f801121: - case 0x1f801124: case 0x1f801125: - case 0x1f801128: case 0x1f801129: - case 0x1f801810: case 0x1f801811: - case 0x1f801812: case 0x1f801813: - case 0x1f801814: case 0x1f801815: - case 0x1f801816: case 0x1f801817: - case 0x1f801820: case 0x1f801821: - case 0x1f801822: case 0x1f801823: - case 0x1f801824: case 0x1f801825: - case 0x1f801826: case 0x1f801827: - log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - if (0x1f801c00 <= add && add < 0x1f802000) { - u16 val = SPU_readRegister(add & ~1, psxRegs.cycle); - hard = (add & 1) ? val >> 8 : val; - break; - } - hard = psxHu8(add); -#ifdef PSXHW_LOG - PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add); -#endif - return hard; + u8 hard; + + switch (add & 0xffff) { + case 0x1040: hard = sioRead8(); break; + case 0x1800: hard = cdrRead0(); break; + case 0x1801: hard = cdrRead1(); break; + case 0x1802: hard = cdrRead2(); break; + case 0x1803: hard = cdrRead3(); break; + + case 0x1041: case 0x1042: case 0x1043: + case 0x1044: case 0x1045: + case 0x1046: case 0x1047: + case 0x1048: case 0x1049: + case 0x104a: case 0x104b: + case 0x104c: case 0x104d: + case 0x104e: case 0x104f: + case 0x1050: case 0x1051: + case 0x1054: case 0x1055: + case 0x1058: case 0x1059: + case 0x105a: case 0x105b: + case 0x105c: case 0x105d: + case 0x1100: case 0x1101: + case 0x1104: case 0x1105: + case 0x1108: case 0x1109: + case 0x1110: case 0x1111: + case 0x1114: case 0x1115: + case 0x1118: case 0x1119: + case 0x1120: case 0x1121: + case 0x1124: case 0x1125: + case 0x1128: case 0x1129: + case 0x1810: case 0x1811: + case 0x1812: case 0x1813: + case 0x1814: case 0x1815: + case 0x1816: case 0x1817: + case 0x1820: case 0x1821: + case 0x1822: case 0x1823: + case 0x1824: case 0x1825: + case 0x1826: case 0x1827: + log_unhandled("unhandled r8 %08x @%08x\n", add, psxRegs.pc); + // falthrough + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + u16 val = SPU_readRegister(add & ~1, psxRegs.cycle); + hard = (add & 1) ? val >> 8 : val; + break; + } + hard = psxHu8(add); } -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard); -#endif + //printf("r8 %08x %02x @%08x\n", add, hard, psxRegs.pc); return hard; } u16 psxHwRead16(u32 add) { unsigned short hard; - switch (add & 0x1fffffff) { -#ifdef PSXHW_LOG - case 0x1f801070: PSXHW_LOG("IREG 16bit read %x\n", psxHu16(0x1070)); - return psxHu16(0x1070); - case 0x1f801074: PSXHW_LOG("IMASK 16bit read %x\n", psxHu16(0x1074)); - return psxHu16(0x1074); -#endif - case 0x1f801040: - hard = sioRead8(); - hard|= sioRead8() << 8; - PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); - return hard; - case 0x1f801044: - hard = sioReadStat16(); - PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); - return hard; - case 0x1f801048: - hard = sioReadMode16(); - PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); - return hard; - case 0x1f80104a: - hard = sioReadCtrl16(); - PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); - return hard; - case 0x1f80104e: - hard = sioReadBaud16(); - PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); - return hard; - - /* Fixes Armored Core misdetecting the Link cable being detected. - * We want to turn that thing off and force it to do local multiplayer instead. - * Thanks Sony for the fix, they fixed it in their PS Classic fork. - */ - case 0x1f801054: - return 0x80; - - case 0x1f801100: - hard = psxRcntRcount0(); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 count read16: %x\n", hard); -#endif - return hard; - case 0x1f801104: - hard = psxRcntRmode(0); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 mode read16: %x\n", hard); -#endif - return hard; - case 0x1f801108: - hard = psxRcntRtarget(0); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 target read16: %x\n", hard); -#endif - return hard; - case 0x1f801110: - hard = psxRcntRcount1(); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 count read16: %x\n", hard); -#endif - return hard; - case 0x1f801114: - hard = psxRcntRmode(1); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 mode read16: %x\n", hard); -#endif - return hard; - case 0x1f801118: - hard = psxRcntRtarget(1); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 target read16: %x\n", hard); -#endif - return hard; - case 0x1f801120: - hard = psxRcntRcount2(); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 count read16: %x\n", hard); -#endif - return hard; - case 0x1f801124: - hard = psxRcntRmode(2); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 mode read16: %x\n", hard); -#endif - return hard; - case 0x1f801128: - hard = psxRcntRtarget(2); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 target read16: %x\n", hard); -#endif - return hard; - - //case 0x1f802030: hard = //int_2000???? - //case 0x1f802040: hard =//dip switches...?? - - case 0x1f801042: - case 0x1f801046: - case 0x1f80104c: - case 0x1f801050: - case 0x1f801058: - case 0x1f80105a: - case 0x1f80105c: - case 0x1f801800: - case 0x1f801802: - case 0x1f801810: - case 0x1f801812: - case 0x1f801814: - case 0x1f801816: - case 0x1f801820: - case 0x1f801822: - case 0x1f801824: - case 0x1f801826: - log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - if (0x1f801c00 <= add && add < 0x1f802000) - return SPU_readRegister(add, psxRegs.cycle); - hard = psxHu16(add); -#ifdef PSXHW_LOG - PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add); -#endif - return hard; + switch (add & 0xffff) { + case 0x1040: hard = sioRead8(); break; + case 0x1044: hard = sioReadStat16(); break; + case 0x1048: hard = sioReadMode16(); break; + case 0x104a: hard = sioReadCtrl16(); break; + case 0x104e: hard = sioReadBaud16(); break; + case 0x1054: hard = 0x80; break; // Armored Core Link cable misdetection + case 0x1100: hard = psxRcntRcount0(); break; + case 0x1104: hard = psxRcntRmode(0); break; + case 0x1108: hard = psxRcntRtarget(0); break; + case 0x1110: hard = psxRcntRcount1(); break; + case 0x1114: hard = psxRcntRmode(1); break; + case 0x1118: hard = psxRcntRtarget(1); break; + case 0x1120: hard = psxRcntRcount2(); break; + case 0x1124: hard = psxRcntRmode(2); break; + case 0x1128: hard = psxRcntRtarget(2); break; + + case 0x1042: + case 0x1046: + case 0x104c: + case 0x1050: + case 0x1058: + case 0x105a: + case 0x105c: + case 0x1800: + case 0x1802: + case 0x1810: + case 0x1812: + case 0x1814: + case 0x1816: + case 0x1820: + case 0x1822: + case 0x1824: + case 0x1826: + log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc); + // falthrough + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + hard = SPU_readRegister(add, psxRegs.cycle); + break; + } + hard = psxHu16(add); } -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard); -#endif + //printf("r16 %08x %04x @%08x\n", add, hard, psxRegs.pc); return hard; } u32 psxHwRead32(u32 add) { u32 hard; - switch (add & 0x1fffffff) { - case 0x1f801040: - hard = sioRead8(); - hard |= sioRead8() << 8; - hard |= sioRead8() << 16; - hard |= sioRead8() << 24; - PAD_LOG("sio read32 ;ret = %x\n", hard); - return hard; - case 0x1f801044: - hard = sioReadStat16(); - PAD_LOG("sio read32 %x; ret = %x\n", add&0xf, hard); - return hard; -#ifdef PSXHW_LOG - case 0x1f801060: - PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060)); - return psxHu32(0x1060); - case 0x1f801070: PSXHW_LOG("IREG 32bit read %x\n", psxHu32(0x1070)); - return psxHu32(0x1070); - case 0x1f801074: PSXHW_LOG("IMASK 32bit read %x\n", psxHu32(0x1074)); - return psxHu32(0x1074); -#endif - - case 0x1f801810: - hard = GPU_readData(); -#ifdef PSXHW_LOG - PSXHW_LOG("GPU DATA 32bit read %x\n", hard); -#endif - return hard; - case 0x1f801814: - hard = psxHwReadGpuSRptr(); -#ifdef PSXHW_LOG - PSXHW_LOG("GPU STATUS 32bit read %x\n", hard); -#endif - return hard; - - case 0x1f801820: hard = mdecRead0(); break; - case 0x1f801824: hard = mdecRead1(); break; - -#ifdef PSXHW_LOG - case 0x1f8010a0: - PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0)); - return SWAPu32(HW_DMA2_MADR); - case 0x1f8010a4: - PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4)); - return SWAPu32(HW_DMA2_BCR); - case 0x1f8010a8: - PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8)); - return SWAPu32(HW_DMA2_CHCR); -#endif - -#ifdef PSXHW_LOG - case 0x1f8010b0: - PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0)); - return SWAPu32(HW_DMA3_MADR); - case 0x1f8010b4: - PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4)); - return SWAPu32(HW_DMA3_BCR); - case 0x1f8010b8: - PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8)); - return SWAPu32(HW_DMA3_CHCR); -#endif - -#ifdef PSXHW_LOG -/* case 0x1f8010f0: - PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0)); - return SWAPu32(HW_DMA_PCR); // dma rest channel - case 0x1f8010f4: - PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4)); - return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/ -#endif - - // time for rootcounters :) - case 0x1f801100: - hard = psxRcntRcount0(); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 count read32: %x\n", hard); -#endif - return hard; - case 0x1f801104: - hard = psxRcntRmode(0); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 mode read32: %x\n", hard); -#endif - return hard; - case 0x1f801108: - hard = psxRcntRtarget(0); -#ifdef PSXHW_LOG - PSXHW_LOG("T0 target read32: %x\n", hard); -#endif - return hard; - case 0x1f801110: - hard = psxRcntRcount1(); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 count read32: %x\n", hard); -#endif - return hard; - case 0x1f801114: - hard = psxRcntRmode(1); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 mode read32: %x\n", hard); -#endif - return hard; - case 0x1f801118: - hard = psxRcntRtarget(1); -#ifdef PSXHW_LOG - PSXHW_LOG("T1 target read32: %x\n", hard); -#endif - return hard; - case 0x1f801120: - hard = psxRcntRcount2(); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 count read32: %x\n", hard); -#endif - return hard; - case 0x1f801124: - hard = psxRcntRmode(2); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 mode read32: %x\n", hard); -#endif - return hard; - case 0x1f801128: - hard = psxRcntRtarget(2); -#ifdef PSXHW_LOG - PSXHW_LOG("T2 target read32: %x\n", hard); -#endif - return hard; - - case 0x1f801048: - case 0x1f80104c: - case 0x1f801050: - case 0x1f801054: - case 0x1f801058: - case 0x1f80105c: - case 0x1f801800: - log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - if (0x1f801c00 <= add && add < 0x1f802000) { - hard = SPU_readRegister(add, psxRegs.cycle); - hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16; - return hard; - } - hard = psxHu32(add); -#ifdef PSXHW_LOG - PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add); -#endif - return hard; + switch (add & 0xffff) { + case 0x1040: hard = sioRead8(); break; + case 0x1044: hard = sioReadStat16(); break; + case 0x1100: hard = psxRcntRcount0(); break; + case 0x1104: hard = psxRcntRmode(0); break; + case 0x1108: hard = psxRcntRtarget(0); break; + case 0x1110: hard = psxRcntRcount1(); break; + case 0x1114: hard = psxRcntRmode(1); break; + case 0x1118: hard = psxRcntRtarget(1); break; + case 0x1120: hard = psxRcntRcount2(); break; + case 0x1124: hard = psxRcntRmode(2); break; + case 0x1128: hard = psxRcntRtarget(2); break; + case 0x1810: hard = GPU_readData(); break; + case 0x1814: hard = psxHwReadGpuSRptr(); break; + case 0x1820: hard = mdecRead0(); break; + case 0x1824: hard = mdecRead1(); break; + + case 0x1048: + case 0x104c: + case 0x1050: + case 0x1054: + case 0x1058: + case 0x105c: + case 0x1800: + log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc); + // falthrough + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + hard = SPU_readRegister(add, psxRegs.cycle); + hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16; + break; + } + hard = psxHu32(add); } -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 32bit read at address %x\n", add); -#endif + //printf("r32 %08x %08x @%08x\n", add, hard, psxRegs.pc); return hard; } -void psxHwWrite8(u32 add, u8 value) { - switch (add & 0x1fffffff) { - case 0x1f801040: sioWrite8(value); break; - case 0x1f8010f6: - // nocash documents it as forced w32, but still games use this? - break; - case 0x1f801800: cdrWrite0(value); break; - case 0x1f801801: cdrWrite1(value); break; - case 0x1f801802: cdrWrite2(value); break; - case 0x1f801803: cdrWrite3(value); break; - - case 0x1f801810: case 0x1f801811: - case 0x1f801812: case 0x1f801813: - case 0x1f801814: case 0x1f801815: - case 0x1f801816: case 0x1f801817: - case 0x1f801820: case 0x1f801821: - case 0x1f801822: case 0x1f801823: - case 0x1f801824: case 0x1f801825: - case 0x1f801826: case 0x1f801827: - log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - if (0x1f801c00 <= add && add < 0x1f802000) { - log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc); - if (!(add & 1)) - SPU_writeRegister(add, value, psxRegs.cycle); - return; - } - else if (0x1f801000 <= add && add < 0x1f801800) - log_unhandled("unhandled w8 %08x @%08x\n", add, psxRegs.pc); - - psxHu8(add) = value; -#ifdef PSXHW_LOG - PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); -#endif +void psxHwWrite8(u32 add, u32 value) { + switch (add & 0xffff) { + case 0x1040: sioWrite8(value); return; + case 0x10f6: + // nocash documents it as forced w32, but still games use this? + break; + case 0x1800: cdrWrite0(value); return; + case 0x1801: cdrWrite1(value); return; + case 0x1802: cdrWrite2(value); return; + case 0x1803: cdrWrite3(value); return; + case 0x2041: break; // "POST (external 7 segment display)" + + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc); + if (!(add & 1)) + SPU_writeRegister(add, value, psxRegs.cycle); return; + } + else + log_unhandled("unhandled w8 %08x %08x @%08x\n", + add, value, psxRegs.pc); } psxHu8(add) = value; -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); -#endif } -void psxHwWrite16(u32 add, u16 value) { - switch (add & 0x1fffffff) { - case 0x1f801040: - sioWrite8((unsigned char)value); - sioWrite8((unsigned char)(value>>8)); - PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); - return; - case 0x1f801044: - sioWriteStat16(value); - PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); - return; - case 0x1f801048: - sioWriteMode16(value); - PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); - return; - case 0x1f80104a: // control register - sioWriteCtrl16(value); - PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); - return; - case 0x1f80104e: // baudrate register - sioWriteBaud16(value); - PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); - return; - case 0x1f801070: -#ifdef PSXHW_LOG - PSXHW_LOG("IREG 16bit write %x\n", value); -#endif - psxHwWriteIstat(value); - return; - - case 0x1f801074: -#ifdef PSXHW_LOG - PSXHW_LOG("IMASK 16bit write %x\n", value); -#endif - psxHwWriteImask(value); - return; - - case 0x1f801100: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 COUNT 16bit write %x\n", value); -#endif - psxRcntWcount(0, value); return; - case 0x1f801104: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 MODE 16bit write %x\n", value); -#endif - psxRcntWmode(0, value); return; - case 0x1f801108: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 TARGET 16bit write %x\n", value); -#endif - psxRcntWtarget(0, value); return; - - case 0x1f801110: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 COUNT 16bit write %x\n", value); -#endif - psxRcntWcount(1, value); return; - case 0x1f801114: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 MODE 16bit write %x\n", value); -#endif - psxRcntWmode(1, value); return; - case 0x1f801118: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 TARGET 16bit write %x\n", value); -#endif - psxRcntWtarget(1, value); return; - - case 0x1f801120: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 COUNT 16bit write %x\n", value); -#endif - psxRcntWcount(2, value); return; - case 0x1f801124: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 MODE 16bit write %x\n", value); -#endif - psxRcntWmode(2, value); return; - case 0x1f801128: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 TARGET 16bit write %x\n", value); -#endif - psxRcntWtarget(2, value); return; - - case 0x1f801042: - case 0x1f801046: - case 0x1f80104c: - case 0x1f801050: - case 0x1f801054: - case 0x1f801058: - case 0x1f80105a: - case 0x1f80105c: - case 0x1f801800: - case 0x1f801802: - case 0x1f801810: - case 0x1f801812: - case 0x1f801814: - case 0x1f801816: - case 0x1f801820: - case 0x1f801822: - case 0x1f801824: - case 0x1f801826: - log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - if (0x1f801c00 <= add && add < 0x1f802000) { - SPU_writeRegister(add, value, psxRegs.cycle); - return; - } - - psxHu16ref(add) = SWAPu16(value); -#ifdef PSXHW_LOG - PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); -#endif +void psxHwWrite16(u32 add, u32 value) { + switch (add & 0xffff) { + case 0x1040: sioWrite8(value); return; + case 0x1044: sioWriteStat16(value); return; + case 0x1048: sioWriteMode16(value); return; + case 0x104a: sioWriteCtrl16(value); return; + case 0x104e: sioWriteBaud16(value); return; + case 0x1070: psxHwWriteIstat(value); return; + case 0x1074: psxHwWriteImask(value); return; + case 0x1100: psxRcntWcount(0, value); return; + case 0x1104: psxRcntWmode(0, value); return; + case 0x1108: psxRcntWtarget(0, value); return; + case 0x1110: psxRcntWcount(1, value); return; + case 0x1114: psxRcntWmode(1, value); return; + case 0x1118: psxRcntWtarget(1, value); return; + case 0x1120: psxRcntWcount(2, value); return; + case 0x1124: psxRcntWmode(2, value); return; + case 0x1128: psxRcntWtarget(2, value); return; + + // forced write32: + case 0x1088: // DMA0 chcr (MDEC in DMA) + case 0x108c: psxHwWriteChcr0(value); return; + case 0x1098: // DMA1 chcr (MDEC out DMA) + case 0x109c: psxHwWriteChcr1(value); return; + case 0x10a8: // DMA2 chcr (GPU DMA) + case 0x10ac: psxHwWriteChcr2(value); return; + case 0x10b8: // DMA3 chcr (CDROM DMA) + case 0x10bc: psxHwWriteChcr3(value); return; + case 0x10c8: // DMA4 chcr (SPU DMA) + case 0x10cc: psxHwWriteChcr4(value); return; + case 0x10e8: // DMA6 chcr (OT clear) + case 0x10ec: psxHwWriteChcr6(value); return; + case 0x10f4: psxHwWriteDmaIcr32(value); return; + + // forced write32 with no immediate effect: + case 0x1014: + case 0x1060: + case 0x1080: + case 0x1090: + case 0x10a0: + case 0x10b0: + case 0x10c0: + case 0x10d0: + case 0x10e0: + case 0x10f0: + psxHu32ref(add) = SWAPu32(value); + return; + + case 0x1800: + case 0x1802: + case 0x1810: + case 0x1812: + case 0x1814: + case 0x1816: + case 0x1820: + case 0x1822: + case 0x1824: + case 0x1826: + log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc); + break; + + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + SPU_writeRegister(add, value, psxRegs.cycle); return; + } + else if (0x1f801000 <= add && add < 0x1f801800) + log_unhandled("unhandled w16 %08x %08x @%08x\n", + add, value, psxRegs.pc); } psxHu16ref(add) = SWAPu16(value); -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value); -#endif -} - -#define DmaExec(n) { \ - if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \ - log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \ - HW_DMA##n##_CHCR = SWAPu32(value); \ -\ - if (SWAPu32(HW_DMA##n##_CHCR) & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8 << (n * 4))) { \ - psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), SWAPu32(HW_DMA##n##_CHCR)); \ - } \ } void psxHwWrite32(u32 add, u32 value) { - switch (add & 0x1fffffff) { - case 0x1f801040: - sioWrite8((unsigned char)value); - sioWrite8((unsigned char)((value&0xff) >> 8)); - sioWrite8((unsigned char)((value&0xff) >> 16)); - sioWrite8((unsigned char)((value&0xff) >> 24)); - PAD_LOG("sio write32 %x\n", value); - return; -#ifdef PSXHW_LOG - case 0x1f801060: - PSXHW_LOG("RAM size write %x\n", value); - psxHu32ref(add) = SWAPu32(value); - return; // Ram size -#endif - - case 0x1f801070: -#ifdef PSXHW_LOG - PSXHW_LOG("IREG 32bit write %x\n", value); -#endif - psxHwWriteIstat(value); - return; - case 0x1f801074: -#ifdef PSXHW_LOG - PSXHW_LOG("IMASK 32bit write %x\n", value); -#endif - psxHwWriteImask(value); - return; - -#ifdef PSXHW_LOG - case 0x1f801080: - PSXHW_LOG("DMA0 MADR 32bit write %x\n", value); - HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr - case 0x1f801084: - PSXHW_LOG("DMA0 BCR 32bit write %x\n", value); - HW_DMA0_BCR = SWAPu32(value); return; // DMA0 bcr -#endif - case 0x1f801088: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value); -#endif - DmaExec(0); // DMA0 chcr (MDEC in DMA) - return; - -#ifdef PSXHW_LOG - case 0x1f801090: - PSXHW_LOG("DMA1 MADR 32bit write %x\n", value); - HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr - case 0x1f801094: - PSXHW_LOG("DMA1 BCR 32bit write %x\n", value); - HW_DMA1_BCR = SWAPu32(value); return; // DMA1 bcr -#endif - case 0x1f801098: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value); -#endif - DmaExec(1); // DMA1 chcr (MDEC out DMA) - return; - -#ifdef PSXHW_LOG - case 0x1f8010a0: - PSXHW_LOG("DMA2 MADR 32bit write %x\n", value); - HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr - case 0x1f8010a4: - PSXHW_LOG("DMA2 BCR 32bit write %x\n", value); - HW_DMA2_BCR = SWAPu32(value); return; // DMA2 bcr -#endif - case 0x1f8010a8: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value); -#endif - DmaExec(2); // DMA2 chcr (GPU DMA) - return; - -#ifdef PSXHW_LOG - case 0x1f8010b0: - PSXHW_LOG("DMA3 MADR 32bit write %x\n", value); - HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr - case 0x1f8010b4: - PSXHW_LOG("DMA3 BCR 32bit write %x\n", value); - HW_DMA3_BCR = SWAPu32(value); return; // DMA3 bcr -#endif - case 0x1f8010b8: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value); -#endif - DmaExec(3); // DMA3 chcr (CDROM DMA) - - return; - -#ifdef PSXHW_LOG - case 0x1f8010c0: - PSXHW_LOG("DMA4 MADR 32bit write %x\n", value); - HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr - case 0x1f8010c4: - PSXHW_LOG("DMA4 BCR 32bit write %x\n", value); - HW_DMA4_BCR = SWAPu32(value); return; // DMA4 bcr -#endif - case 0x1f8010c8: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value); -#endif - DmaExec(4); // DMA4 chcr (SPU DMA) - return; - -#if 0 - case 0x1f8010d0: break; //DMA5write_madr(); - case 0x1f8010d4: break; //DMA5write_bcr(); - case 0x1f8010d8: break; //DMA5write_chcr(); // Not needed -#endif - -#ifdef PSXHW_LOG - case 0x1f8010e0: - PSXHW_LOG("DMA6 MADR 32bit write %x\n", value); - HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr - case 0x1f8010e4: - PSXHW_LOG("DMA6 BCR 32bit write %x\n", value); - HW_DMA6_BCR = SWAPu32(value); return; // DMA6 bcr -#endif - case 0x1f8010e8: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value); -#endif - DmaExec(6); // DMA6 chcr (OT clear) - return; - -#ifdef PSXHW_LOG - case 0x1f8010f0: - PSXHW_LOG("DMA PCR 32bit write %x\n", value); - HW_DMA_PCR = SWAPu32(value); - return; -#endif - - case 0x1f8010f4: -#ifdef PSXHW_LOG - PSXHW_LOG("DMA ICR 32bit write %x\n", value); -#endif - psxHwWriteDmaIcr32(value); - return; - - case 0x1f801810: -#ifdef PSXHW_LOG - PSXHW_LOG("GPU DATA 32bit write %x\n", value); -#endif - GPU_writeData(value); return; - case 0x1f801814: -#ifdef PSXHW_LOG - PSXHW_LOG("GPU STATUS 32bit write %x\n", value); -#endif - psxHwWriteGpuSR(value); - return; - - case 0x1f801820: - mdecWrite0(value); break; - case 0x1f801824: - mdecWrite1(value); break; - - case 0x1f801100: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value); -#endif - psxRcntWcount(0, value & 0xffff); return; - case 0x1f801104: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value); -#endif - psxRcntWmode(0, value); return; - case 0x1f801108: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value); -#endif - psxRcntWtarget(0, value & 0xffff); return; // HW_DMA_ICR&= SWAP32((~value)&0xff000000); - - case 0x1f801110: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value); -#endif - psxRcntWcount(1, value & 0xffff); return; - case 0x1f801114: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value); -#endif - psxRcntWmode(1, value); return; - case 0x1f801118: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value); -#endif - psxRcntWtarget(1, value & 0xffff); return; - - case 0x1f801120: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value); -#endif - psxRcntWcount(2, value & 0xffff); return; - case 0x1f801124: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value); -#endif - psxRcntWmode(2, value); return; - case 0x1f801128: -#ifdef PSXHW_LOG - PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value); -#endif - psxRcntWtarget(2, value & 0xffff); return; - - case 0x1f801044: - case 0x1f801048: - case 0x1f80104c: - case 0x1f801050: - case 0x1f801054: - case 0x1f801058: - case 0x1f80105c: - case 0x1f801800: - log_unhandled("unhandled w32 %08x @%08x\n", add, psxRegs.pc); - // falthrough - default: - // Dukes of Hazard 2 - car engine noise - if (0x1f801c00 <= add && add < 0x1f802000) { - SPU_writeRegister(add, value&0xffff, psxRegs.cycle); - SPU_writeRegister(add + 2, value>>16, psxRegs.cycle); - return; - } - - psxHu32ref(add) = SWAPu32(value); -#ifdef PSXHW_LOG - PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); -#endif + switch (add & 0xffff) { + case 0x1040: sioWrite8(value); return; + case 0x1070: psxHwWriteIstat(value); return; + case 0x1074: psxHwWriteImask(value); return; + case 0x1088: // DMA0 chcr (MDEC in DMA) + case 0x108c: psxHwWriteChcr0(value); return; + case 0x1098: // DMA1 chcr (MDEC out DMA) + case 0x109c: psxHwWriteChcr1(value); return; + case 0x10a8: // DMA2 chcr (GPU DMA) + case 0x10ac: psxHwWriteChcr2(value); return; + case 0x10b8: // DMA3 chcr (CDROM DMA) + case 0x10bc: psxHwWriteChcr3(value); return; + case 0x10c8: // DMA4 chcr (SPU DMA) + case 0x10cc: psxHwWriteChcr4(value); return; + case 0x10e8: // DMA6 chcr (OT clear) + case 0x10ec: psxHwWriteChcr6(value); return; + case 0x10f4: psxHwWriteDmaIcr32(value); return; + + case 0x1810: GPU_writeData(value); return; + case 0x1814: psxHwWriteGpuSR(value); return; + case 0x1820: mdecWrite0(value); break; + case 0x1824: mdecWrite1(value); break; + + case 0x1100: psxRcntWcount(0, value & 0xffff); return; + case 0x1104: psxRcntWmode(0, value); return; + case 0x1108: psxRcntWtarget(0, value & 0xffff); return; + case 0x1110: psxRcntWcount(1, value & 0xffff); return; + case 0x1114: psxRcntWmode(1, value); return; + case 0x1118: psxRcntWtarget(1, value & 0xffff); return; + case 0x1120: psxRcntWcount(2, value & 0xffff); return; + case 0x1124: psxRcntWmode(2, value); return; + case 0x1128: psxRcntWtarget(2, value & 0xffff); return; + + case 0x1044: + case 0x1048: + case 0x104c: + case 0x1050: + case 0x1054: + case 0x1058: + case 0x105c: + case 0x1800: + log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc); + break; + + default: + if (0x1f801c00 <= add && add < 0x1f802000) { + SPU_writeRegister(add, value&0xffff, psxRegs.cycle); + SPU_writeRegister(add + 2, value>>16, psxRegs.cycle); return; + } } psxHu32ref(add) = SWAPu32(value); -#ifdef PSXHW_LOG - PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value); -#endif } int psxHwFreeze(void *f, int Mode) { diff --git a/libpcsxcore/psxhw.h b/libpcsxcore/psxhw.h index 91256ce3..574ee333 100644 --- a/libpcsxcore/psxhw.h +++ b/libpcsxcore/psxhw.h @@ -77,13 +77,19 @@ void psxHwReset(); u8 psxHwRead8(u32 add); u16 psxHwRead16(u32 add); u32 psxHwRead32(u32 add); -void psxHwWrite8(u32 add, u8 value); -void psxHwWrite16(u32 add, u16 value); +void psxHwWrite8(u32 add, u32 value); +void psxHwWrite16(u32 add, u32 value); void psxHwWrite32(u32 add, u32 value); int psxHwFreeze(void *f, int Mode); void psxHwWriteIstat(u32 value); void psxHwWriteImask(u32 value); +void psxHwWriteChcr0(u32 value); +void psxHwWriteChcr1(u32 value); +void psxHwWriteChcr2(u32 value); +void psxHwWriteChcr3(u32 value); +void psxHwWriteChcr4(u32 value); +void psxHwWriteChcr6(u32 value); void psxHwWriteDmaIcr32(u32 value); void psxHwWriteGpuSR(u32 value); u32 psxHwReadGpuSR(void); diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c index 5f6971df..30608535 100644 --- a/libpcsxcore/psxinterpreter.c +++ b/libpcsxcore/psxinterpreter.c @@ -869,12 +869,12 @@ OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); } OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); } OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); } -OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); } -OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); } +OP(psxSB) { psxMemWrite8 (_oB_, _rRt_); } +OP(psxSH) { psxMemWrite16(_oB_, _rRt_); } OP(psxSW) { psxMemWrite32(_oB_, _rRt_); } -OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); } -OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); } +OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_); } +OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_); } OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); } static void doSWL(psxRegisters *regs, u32 rt, u32 addr) { diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c index 2196fa7b..4e03b24b 100644 --- a/libpcsxcore/psxmem.c +++ b/libpcsxcore/psxmem.c @@ -388,7 +388,7 @@ u32 psxMemRead32(u32 mem) { } } -void psxMemWrite8(u32 mem, u8 value) { +void psxMemWrite8(u32 mem, u32 value) { char *p; u32 t; @@ -415,7 +415,7 @@ void psxMemWrite8(u32 mem, u8 value) { } } -void psxMemWrite16(u32 mem, u16 value) { +void psxMemWrite16(u32 mem, u32 value) { char *p; u32 t; diff --git a/libpcsxcore/psxmem.h b/libpcsxcore/psxmem.h index 4e95c4dd..f9cc8f0c 100644 --- a/libpcsxcore/psxmem.h +++ b/libpcsxcore/psxmem.h @@ -178,8 +178,8 @@ void psxMemShutdown(); u8 psxMemRead8 (u32 mem); u16 psxMemRead16(u32 mem); u32 psxMemRead32(u32 mem); -void psxMemWrite8 (u32 mem, u8 value); -void psxMemWrite16(u32 mem, u16 value); +void psxMemWrite8 (u32 mem, u32 value); +void psxMemWrite16(u32 mem, u32 value); void psxMemWrite32(u32 mem, u32 value); void *psxMemPointer(u32 mem); -- 2.39.5