From c1812e1a85f2c396bd162c93f629bc1db38050f2 Mon Sep 17 00:00:00 2001 From: kub Date: Fri, 28 Jun 2024 00:20:31 +0200 Subject: [PATCH] core vdp, some cleanup --- pico/draw.c | 3 +-- pico/videoport.c | 9 +++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/pico/draw.c b/pico/draw.c index 7c170baf..95b82b19 100644 --- a/pico/draw.c +++ b/pico/draw.c @@ -2125,7 +2125,6 @@ void PicoDrawSync(int to, int off, int on) { int width2 = (est->Pico->video.reg[12]&1) ? 160 : 128; - // technically, VDP starts active display output at slot 12 if (unlikely(on|off) && (off >= width2 || // hack for timing inaccuracy, if on/off near borders (off && off <= 24) || (on < width2 && on >= width2-24))) @@ -2178,7 +2177,7 @@ void PicoDrawBgcDMA(u16 *base, u32 source, u32 mask, int dlen, int sl) BgcDMAoffs = 0; // handle slot offset in 1st line - if (sl-12 > 0) // active display output only starts at slot 12 + if (sl-12 > 0) BgcDMAoffs = 2*(sl-12); else if (sl < 0) { // DMA starts before active display BgcDMAsrc += 2*-sl; diff --git a/pico/videoport.c b/pico/videoport.c index 79ee508d..462e4703 100644 --- a/pico/videoport.c +++ b/pico/videoport.c @@ -24,7 +24,7 @@ enum { clkdiv = 2 }; // CPU clock granularity: one of 1,2,4,8 // One scanline is 63.7us/64.3us (ntsc/pal) long which is ~488.57 68k cycles. // Approximate by 488 for VDP. // 1 slot is 20/7 = 2.857 68k cycles in h32, and 16/7 = 2.286 in h40. That's -// 171 slots in h32, and ~213.8 (really 193 plus 17 prolonged in HSYNC) in h40. +// 171 slots in h32, and ~214 (really 193 plus 17 prolonged in HSYNC) in h40. enum { slcpu = 488 }; // VDP has a slot counter running from 0x00 to 0xff every scanline, but it has @@ -35,6 +35,11 @@ enum { slcpu = 488 }; enum { hint32 = 0x85, gapstart32 = 0x94, gapend32 = 0xe9}; enum { hint40 = 0xa5, gapstart40 = 0xb7, gapend40 = 0xe5}; +// Basic timing in h32: 38 slots (~108.5 cycles) from hint to VDP output start +// at slot 0x00. vint takes place on the 1st VBLANK line in slot 0x01 (~111.5). +// Rendering takes 128 slots (~365.5), and right border starts at slot 0x80 +// (~474 cycles). hint occurs after 5 slots into the border (~488.5 cycles). + // The horizontal sync period (HBLANK) is 30/37 slots (h32/h40): // h32: 4 slots front porch (1.49us), 13 HSYNC (4.84us), 13 back porch (4.84us) // h40: 5 slots front porch (1.49us), 16 HSYNC (4.77us), 16 back porch (4.77us) @@ -621,7 +626,7 @@ static void DmaSlow(int len, u32 source) if (sl > VdpFIFO.fifo_hcounts[0]-5) // hint delay is 5 slots sl = (s8)sl; // TODO this is needed to cover timing inaccuracies - if (sl <= 12) sl = -2; + if (sl <= 12) sl = -2; PicoDrawBgcDMA(base, source, mask, len, sl); // do last DMA cycle since it's all going to the same cram location source = source+len-1; -- 2.39.2