From d5715559cf1bc112e4a879b4c9e6f3a4272fc5cf Mon Sep 17 00:00:00 2001
From: notaz <notasas@gmail.com>
Date: Sat, 8 Sep 2007 20:28:09 +0000
Subject: [PATCH] timing hack removed, seems to be no longer needed
git-svn-id: file:///home/notaz/opt/svn/PicoDrive@242 be3aeb3a-fb24-0410-a615-afba39da0efa
---
cpu/Cyclone/OpLogic.cpp | 12 ++----------
cpu/Cyclone/config.h | 1 -
cpu/Cyclone/config_mamegp2x.h | 1 -
cpu/Cyclone/config_pico.h | 3 +--
cpu/Cyclone/config_uae4all.h | 1 -
cpu/musashi/m68k_in.c | 4 ++--
6 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/cpu/Cyclone/OpLogic.cpp b/cpu/Cyclone/OpLogic.cpp
index 4bd08695..94b00172 100644
--- a/cpu/Cyclone/OpLogic.cpp
+++ b/cpu/Cyclone/OpLogic.cpp
@@ -143,16 +143,8 @@ int OpNeg(int op)
use=OpBase(op,size);
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
- OpStart(op,ea); Cycles=size<2?4:6;
- if(ea >= 0x10) {
- Cycles*=2;
-#if CYCLONE_FOR_GENESIS
- // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.
- // May be this is similar case as with TAS opcode, but this time the dummy
- // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.
- if(type==1&&size<2) Cycles-=2;
-#endif
- }
+ OpStart(op,ea); Cycles=size<2?4:6;
+ if(ea >= 0x10) Cycles*=2;
EaCalc (10,0x003f,ea,size,0,0);
diff --git a/cpu/Cyclone/config.h b/cpu/Cyclone/config.h
index 7736712b..e180490e 100644
--- a/cpu/Cyclone/config.h
+++ b/cpu/Cyclone/config.h
@@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
- * This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0
diff --git a/cpu/Cyclone/config_mamegp2x.h b/cpu/Cyclone/config_mamegp2x.h
index 307b9055..bb3f81a6 100644
--- a/cpu/Cyclone/config_mamegp2x.h
+++ b/cpu/Cyclone/config_mamegp2x.h
@@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
- * This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0
diff --git a/cpu/Cyclone/config_pico.h b/cpu/Cyclone/config_pico.h
index 8f7a336b..d3229ace 100644
--- a/cpu/Cyclone/config_pico.h
+++ b/cpu/Cyclone/config_pico.h
@@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
- * This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 2
@@ -58,7 +57,7 @@
* MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle
* count and this will screw timing (if not cause a deadlock).
*/
-#define MEMHANDLERS_NEED_PC 1
+#define MEMHANDLERS_NEED_PC 0
#define MEMHANDLERS_NEED_PREV_PC 0
#define MEMHANDLERS_NEED_FLAGS 0
#define MEMHANDLERS_NEED_CYCLES 1
diff --git a/cpu/Cyclone/config_uae4all.h b/cpu/Cyclone/config_uae4all.h
index d1f68c61..f84dc6d2 100644
--- a/cpu/Cyclone/config_uae4all.h
+++ b/cpu/Cyclone/config_uae4all.h
@@ -16,7 +16,6 @@
* Mega Drive system. As VDP chip in these systems had control of the bus,
* several instructions were acting differently, for example TAS did'n have
* the write-back phase. That will be emulated, if this option is enabled.
- * This option also alters timing slightly.
*/
#define CYCLONE_FOR_GENESIS 0
diff --git a/cpu/musashi/m68k_in.c b/cpu/musashi/m68k_in.c
index d3ee8667..5c9cc066 100644
--- a/cpu/musashi/m68k_in.c
+++ b/cpu/musashi/m68k_in.c
@@ -496,9 +496,9 @@ chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23
chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23
chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18
clr 8 . d 0100001000000... .......... U U U U 4 4 2 2
-clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind
+clr 8 . . 0100001000...... A+-DXWL... U U U U 8 4 4 4
clr 16 . d 0100001001000... .......... U U U U 4 4 2 2
-clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto
+clr 16 . . 0100001001...... A+-DXWL... U U U U 8 4 4 4
clr 32 . d 0100001010000... .......... U U U U 6 6 2 2
clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4
cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2
--
2.39.5