From f4bb5d6b2c96a94317c4edb7805eb6d6ed8589ef Mon Sep 17 00:00:00 2001 From: notaz Date: Sun, 18 Oct 2009 20:52:50 +0000 Subject: [PATCH] 32x: drc: new smc handling, write handlers adjusted. git-svn-id: file:///home/notaz/opt/svn/PicoDrive@820 be3aeb3a-fb24-0410-a615-afba39da0efa --- cpu/drc/cmn.c | 2 +- cpu/drc/cmn.h | 2 +- cpu/drc/emit_x86.c | 45 +++-- cpu/sh2/compiler.c | 348 +++++++++++++++++++++++++++++-------- cpu/sh2/compiler.h | 2 + cpu/sh2/sh2.h | 10 +- pico/32x/memory.c | 115 +++++++----- pico/carthw/svp/compiler.c | 4 +- pico/pico_int.h | 13 ++ 9 files changed, 390 insertions(+), 151 deletions(-) diff --git a/cpu/drc/cmn.c b/cpu/drc/cmn.c index e286ccf6..08059f2d 100644 --- a/cpu/drc/cmn.c +++ b/cpu/drc/cmn.c @@ -5,7 +5,7 @@ #include "cmn.h" -u32 __attribute__((aligned(4096))) tcache[DRC_TCACHE_SIZE/4]; +u8 __attribute__((aligned(4096))) tcache[DRC_TCACHE_SIZE]; void drc_cmn_init(void) diff --git a/cpu/drc/cmn.h b/cpu/drc/cmn.h index a4bce322..d5ed9ba8 100644 --- a/cpu/drc/cmn.h +++ b/cpu/drc/cmn.h @@ -4,7 +4,7 @@ typedef unsigned int u32; #define DRC_TCACHE_SIZE (512*1024) -extern u32 tcache[DRC_TCACHE_SIZE/4]; +extern u8 tcache[DRC_TCACHE_SIZE]; void drc_cmn_init(void); void drc_cmn_cleanup(void); diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c index e2eef38e..3fe31047 100644 --- a/cpu/drc/emit_x86.c +++ b/cpu/drc/emit_x86.c @@ -7,6 +7,8 @@ #define COUNT_OP #endif +enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; + // TODO: move static int reg_map_g2h[] = { -1, -1, -1, -1, @@ -17,14 +19,14 @@ static int reg_map_g2h[] = { -1, -1, -1, -1, }; -enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; +#define CONTEXT_REG xBP #define EMIT_PTR(ptr, val, type) \ *(type *)(ptr) = val #define EMIT(val, type) { \ EMIT_PTR(tcache_ptr, val, type); \ - tcache_ptr = (char *)tcache_ptr + sizeof(type); \ + tcache_ptr += sizeof(type); \ } #define EMIT_OP(op) { \ @@ -99,32 +101,29 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; } #define EMIT_CONDITIONAL(code, is_nonzero) { \ - char *ptr = tcache_ptr; \ - tcache_ptr = (char *)tcache_ptr + 2; \ + u8 *ptr = tcache_ptr; \ + tcache_ptr = tcache_ptr + 2; \ code; \ EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \ - EMIT_PTR(ptr + 1, ((char *)tcache_ptr - (ptr + 2)), u8); \ + EMIT_PTR(ptr + 1, (tcache_ptr - (ptr + 2)), u8); \ } -static void emith_pass_arg(int count, ...) -{ - va_list vl; - int i; - - va_start(vl, count); - - for (i = 0; i < count; i++) { - long av = va_arg(vl, long); - int r = 7; - - switch (i) { - case 0: r = xAX; break; - case 1: r = xDX; break; - case 2: r = xCX; break; - } - emith_move_r_imm(r, av); +#define arg2reg(rd, arg) \ + switch (arg) { \ + case 0: rd = xAX; break; \ + case 1: rd = xDX; break; \ + case 2: rd = xCX; break; \ } - va_end(vl); +#define emith_pass_arg_r(arg, reg) { \ + int rd = 7; \ + arg2reg(rd, arg); \ + emith_move_r_r(rd, reg); \ +} + +#define emith_pass_arg_imm(arg, imm) { \ + int rd = 7; \ + arg2reg(rd, arg); \ + emith_move_r_imm(rd, imm); \ } diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c index 7c3a1368..a243aca2 100644 --- a/cpu/sh2/compiler.c +++ b/cpu/sh2/compiler.c @@ -5,6 +5,7 @@ #include #include +#include "../../pico/pico_int.h" #include "sh2.h" #include "compiler.h" #include "../drc/cmn.h" @@ -13,19 +14,43 @@ #define DRC_DEBUG 0 #endif +#define dbg(l,...) { \ + if ((l) & DRC_DEBUG) \ + elprintf(EL_STATUS, ##__VA_ARGS__); \ +} + #if DRC_DEBUG #include "mame/sh2dasm.h" #include static int insns_compiled, hash_collisions, host_insn_count; #endif #if (DRC_DEBUG & 2) -static void *tcache_dsm_ptr = tcache; +static u8 *tcache_dsm_ptrs[3]; static char sh2dasm_buff[64]; +#define do_host_disasm(tcid) \ + host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \ + tcache_dsm_ptrs[tcid] = tcache_ptr +#else +#define do_host_disasm(x) #endif #define BLOCK_CYCLE_LIMIT 100 +#define MAX_BLOCK_SIZE (BLOCK_CYCLE_LIMIT * 6 * 6) + +// we have 3 translation cache buffers, split from one drc/cmn buffer. +// BIOS shares tcache with data array because it's only used for init +// and can be discarded early +static const int tcache_sizes[3] = { + DRC_TCACHE_SIZE * 6 / 8, // ROM, DRAM + DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2 + DRC_TCACHE_SIZE / 8, // ... slave +}; -static void *tcache_ptr; +static u8 *tcache_bases[3]; +static u8 *tcache_ptrs[3]; + +// ptr for code emiters +static u8 *tcache_ptr; #include "../drc/emit_x86.c" @@ -37,16 +62,26 @@ typedef enum { typedef struct block_desc_ { u32 addr; // SH2 PC address + u32 end_addr; // TODO rm? void *tcache_ptr; // translated block for above PC - struct block_desc_ *next; // next block with the same PC hash + struct block_desc_ *next; // next block with the same PC hash +#if (DRC_DEBUG & 1) + int refcount; +#endif } block_desc; -#define MAX_BLOCK_COUNT (4*1024) -static block_desc *block_table; -static int block_count; +static const int block_max_counts[3] = { + 4*1024, + 256, + 256, +}; +static block_desc *block_tables[3]; +static int block_counts[3]; +// ROM hash table #define MAX_HASH_ENTRIES 1024 #define HASH_MASK (MAX_HASH_ENTRIES - 1) +static void **hash_table; extern void sh2_drc_entry(SH2 *sh2, void *block); extern void sh2_drc_exit(void); @@ -55,6 +90,25 @@ extern void sh2_drc_exit(void); extern void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2, int opcode); static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2); +static void flush_tcache(int tcid) +{ + printf("tcache #%d flush! (%d/%d, bds %d/%d)\n", tcid, + tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid], + block_counts[tcid], block_max_counts[tcid]); + + block_counts[tcid] = 0; + tcache_ptrs[tcid] = tcache_bases[tcid]; + if (tcid == 0) { // ROM, RAM + memset(hash_table, 0, sizeof(hash_table[0]) * MAX_HASH_ENTRIES); + memset(Pico32xMem->drcblk_ram, 0, sizeof(Pico32xMem->drcblk_ram)); + } + else + memset(Pico32xMem->drcblk_da[tcid - 1], 0, sizeof(Pico32xMem->drcblk_da[0])); +#if (DRC_DEBUG & 2) + tcache_dsm_ptrs[tcid] = tcache_bases[tcid]; +#endif +} + static void *dr_find_block(block_desc *tab, u32 addr) { for (tab = tab->next; tab != NULL; tab = tab->next) @@ -68,20 +122,19 @@ static void *dr_find_block(block_desc *tab, u32 addr) return NULL; } -static block_desc *dr_add_block(u32 addr, void *tcache_ptr) +static block_desc *dr_add_block(u32 addr, int tcache_id, int *blk_id) { + int *bcount = &block_counts[tcache_id]; block_desc *bd; - if (block_count == MAX_BLOCK_COUNT) { - // FIXME: flush cache instead - printf("block descriptor overflow\n"); - exit(1); - } + if (*bcount >= block_max_counts[tcache_id]) + return NULL; - bd = &block_table[block_count]; + bd = &block_tables[tcache_id][*bcount]; bd->addr = addr; bd->tcache_ptr = tcache_ptr; - block_count++; + *blk_id = *bcount; + (*bcount)++; return bd; } @@ -162,22 +215,46 @@ static int sh2_translate_op4(int op) static void *sh2_translate(SH2 *sh2, block_desc *other_block) { - void *block_entry = tcache_ptr; + void *block_entry; block_desc *this_block; unsigned int pc = sh2->pc; int op, delayed_op = 0, test_irq = 0; + int tcache_id = 0, blkid = 0; int cycles = 0; u32 tmp, tmp2; - this_block = dr_add_block(pc, block_entry); - if (other_block != NULL) - this_block->next = other_block; + // validate PC + tmp = sh2->pc >> 29; + if ((tmp != 0 && tmp != 1 && tmp != 6) || sh2->pc == 0) { + printf("invalid PC, aborting: %08x\n", sh2->pc); + // FIXME: be less destructive + exit(1); + } + + if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { + // data_array, BIOS have separate tcache (shared) + tcache_id = 1 + sh2->is_slave; + } + + tcache_ptr = tcache_ptrs[tcache_id]; + this_block = dr_add_block(pc, tcache_id, &blkid); + + tmp = tcache_ptr - tcache_bases[tcache_id]; + if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE || this_block == NULL) { + flush_tcache(tcache_id); + tcache_ptr = tcache_ptrs[tcache_id]; + other_block = NULL; // also gone too due to flush + this_block = dr_add_block(pc, tcache_id, &blkid); + } - HASH_FUNC(sh2->pc_hashtab, pc) = this_block; + this_block->next = other_block; + if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM + HASH_FUNC(hash_table, pc) = this_block; + block_entry = tcache_ptr; #if (DRC_DEBUG & 1) - printf("== %csh2 block #%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', - block_count, pc, block_entry); + printf("== %csh2 block #%d,%d %08x -> %p\n", sh2->is_slave ? 's' : 'm', + tcache_id, block_counts[tcache_id], pc, block_entry); if (other_block != NULL) { printf(" hash collision with %08x\n", other_block->addr); hash_collisions++; @@ -231,7 +308,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) // RTE 0000000000101011 //emit_move_r_r(SHR_PC, SHR_PR); emit_move_r_imm32(SHR_PC, pc - 2); - emith_pass_arg(2, sh2, op); + emith_pass_arg_r(0, CONTEXT_REG); + emith_pass_arg_imm(1, op); emith_call(sh2_do_op); emit_move_r_r(SHR_PPC, SHR_PC); test_irq = 1; @@ -312,7 +390,8 @@ static void *sh2_translate(SH2 *sh2, block_desc *other_block) default: default_: emit_move_r_imm32(SHR_PC, pc - 2); - emith_pass_arg(2, sh2, op); + emith_pass_arg_r(0, CONTEXT_REG); + emith_pass_arg_imm(1, op); emith_call(sh2_do_op); break; } @@ -322,24 +401,41 @@ end_op: emit_move_r_r(SHR_PC, SHR_PPC); if (test_irq && delayed_op != 2) { - emith_pass_arg(1, sh2); + emith_pass_arg_r(0, CONTEXT_REG); emith_call(sh2_test_irq); break; } if (delayed_op == 1) break; -#if (DRC_DEBUG & 2) - host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); - tcache_dsm_ptr = tcache_ptr; -#endif + do_host_disasm(tcache_id); } end_block: - if ((char *)tcache_ptr - (char *)tcache > DRC_TCACHE_SIZE) { - printf("tcache overflow!\n"); - fflush(stdout); - exit(1); + this_block->end_addr = pc; + + // mark memory blocks as containing compiled code + if ((sh2->pc & 0xe0000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { + // data array, BIOS + u16 *drcblk = Pico32xMem->drcblk_da[sh2->is_slave]; + tmp = (this_block->addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; + tmp2 = (this_block->end_addr & 0xfff) >> SH2_DRCBLK_DA_SHIFT; + Pico32xMem->drcblk_da[sh2->is_slave][tmp] = (blkid << 1) | 1; + for (++tmp; tmp < tmp2; tmp++) { + if (drcblk[tmp]) + break; // dont overwrite overlay block + drcblk[tmp] = blkid << 1; + } + } + else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM + tmp = (this_block->addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; + tmp2 = (this_block->end_addr & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT; + Pico32xMem->drcblk_ram[tmp] = (blkid << 1) | 1; + for (++tmp; tmp < tmp2; tmp++) { + if (Pico32xMem->drcblk_ram[tmp]) + break; + Pico32xMem->drcblk_ram[tmp] = blkid << 1; + } } if (reg_map_g2h[SHR_SR] == -1) { @@ -347,26 +443,22 @@ end_block: } else emith_sub_r_imm(reg_map_g2h[SHR_SR], cycles << 12); emith_jump(sh2_drc_exit); - -#if (DRC_DEBUG & 2) - host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); - tcache_dsm_ptr = tcache_ptr; -#endif -#if (DRC_DEBUG & 1) - printf(" tcache %d/%d, hash collisions %d/%d, insns %d -> %d %.3f\n", - (char *)tcache_ptr - (char *)tcache, DRC_TCACHE_SIZE, - hash_collisions, block_count, insns_compiled, host_insn_count, - (double)host_insn_count / insns_compiled); -#endif + tcache_ptrs[tcache_id] = tcache_ptr; + + do_host_disasm(tcache_id); + dbg(1, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f", + tcache_id, block_counts[tcache_id], + tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id], + insns_compiled, host_insn_count, (double)host_insn_count / insns_compiled); + if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM + dbg(1, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]); return block_entry; - +/* unimplemented: // last op -#if (DRC_DEBUG & 2) - host_dasm(tcache_dsm_ptr, (char *)tcache_ptr - (char *)tcache_dsm_ptr); - tcache_dsm_ptr = tcache_ptr; -#endif + do_host_disasm(tcache_id); exit(1); +*/ } void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) @@ -374,30 +466,95 @@ void __attribute__((noinline)) sh2_drc_dispatcher(SH2 *sh2) while (((signed int)sh2->sr >> 12) > 0) { void *block = NULL; - block_desc *bd; + block_desc *bd = NULL; // FIXME: must avoid doing it so often.. sh2_test_irq(sh2); - bd = HASH_FUNC(sh2->pc_hashtab, sh2->pc); - - if (bd != NULL) { - if (bd->addr == sh2->pc) + // we have full block id tables for data_array and RAM + // BIOS goes to data_array table too + if ((sh2->pc & 0xff000000) == 0xc0000000 || (sh2->pc & ~0xfff) == 0) { + int blkid = Pico32xMem->drcblk_da[sh2->is_slave][(sh2->pc & 0xfff) >> SH2_DRCBLK_DA_SHIFT]; + if (blkid & 1) { + bd = &block_tables[1 + sh2->is_slave][blkid >> 1]; + block = bd->tcache_ptr; + } + } + // RAM + else if ((sh2->pc & 0xc6000000) == 0x06000000) { + int blkid = Pico32xMem->drcblk_ram[(sh2->pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT]; + if (blkid & 1) { + bd = &block_tables[0][blkid >> 1]; block = bd->tcache_ptr; - else - block = dr_find_block(bd, sh2->pc); + } + } + // ROM + else if ((sh2->pc & 0xc6000000) == 0x02000000) { + bd = HASH_FUNC(hash_table, sh2->pc); + + if (bd != NULL) { + if (bd->addr == sh2->pc) + block = bd->tcache_ptr; + else + block = dr_find_block(bd, sh2->pc); + } } if (block == NULL) block = sh2_translate(sh2, bd); -#if (DRC_DEBUG & 4) - printf("= %csh2 enter %08x %p\n", sh2->is_slave ? 's' : 'm', sh2->pc, block); + dbg(4, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm', + sh2->pc, block, (signed int)sh2->sr >> 12); +#if (DRC_DEBUG & 1) + if (bd != NULL) + bd->refcount++; #endif sh2_drc_entry(sh2, block); } } +static void sh2_smc_rm_block(u16 *drcblk, u16 *p, block_desc *btab, u32 a) +{ + u16 id = *p >> 1; + block_desc *bd = btab + id; + + dbg(1, " killing block %08x", bd->addr); + bd->addr = bd->end_addr = 0; + + while (p > drcblk && (p[-1] >> 1) == id) + p--; + + // check for possible overlay block + if (p > 0 && p[-1] != 0) { + bd = btab + (p[-1] >> 1); + if (bd->addr <= a && a < bd->end_addr) + sh2_smc_rm_block(drcblk, p - 1, btab, a); + } + + do { + *p++ = 0; + } + while ((*p >> 1) == id); +} + +void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid) +{ + u16 *drcblk = Pico32xMem->drcblk_ram; + u16 *p = drcblk + ((a & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT); + + dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); + sh2_smc_rm_block(drcblk, p, block_tables[0], a); +} + +void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid) +{ + u16 *drcblk = Pico32xMem->drcblk_da[cpuid]; + u16 *p = drcblk + ((a & 0xfff) >> SH2_DRCBLK_DA_SHIFT); + + dbg(1, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a); + sh2_smc_rm_block(drcblk, p, block_tables[1 + cpuid], a); +} + void sh2_execute(SH2 *sh2, int cycles) { sh2->cycles_aim += cycles; @@ -425,35 +582,84 @@ static void __attribute__((regparm(1))) sh2_test_irq(SH2 *sh2) } } +#if (DRC_DEBUG & 1) +static void block_stats(void) +{ + int c, b, i, total = 0; + + for (b = 0; b < ARRAY_SIZE(block_tables); b++) + for (i = 0; i < block_counts[b]; i++) + if (block_tables[b][i].addr != 0) + total += block_tables[b][i].refcount; + + for (c = 0; c < 10; c++) { + block_desc *blk, *maxb = NULL; + int max = 0; + for (b = 0; b < ARRAY_SIZE(block_tables); b++) { + for (i = 0; i < block_counts[b]; i++) { + blk = &block_tables[b][i]; + if (blk->addr != 0 && blk->refcount > max) { + max = blk->refcount; + maxb = blk; + } + } + } + if (maxb == NULL) + break; + printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount, + (double)maxb->refcount / total * 100.0); + maxb->refcount = 0; + } +} +#endif + int sh2_drc_init(SH2 *sh2) { - if (block_table == NULL) { - block_count = 0; - block_table = calloc(MAX_BLOCK_COUNT, sizeof(*block_table)); - if (block_table == NULL) + if (block_tables[0] == NULL) { + int i, cnt; + cnt = block_max_counts[0] + block_max_counts[1] + block_max_counts[2]; + block_tables[0] = calloc(cnt, sizeof(*block_tables[0])); + if (block_tables[0] == NULL) return -1; - tcache_ptr = tcache; + memset(block_counts, 0, sizeof(block_counts)); + tcache_bases[0] = tcache_ptrs[0] = tcache; + + for (i = 1; i < ARRAY_SIZE(block_tables); i++) { + block_tables[i] = block_tables[i - 1] + block_max_counts[i - 1]; + tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1]; + } + +#if (DRC_DEBUG & 2) + for (i = 0; i < ARRAY_SIZE(block_tables); i++) + tcache_dsm_ptrs[i] = tcache_bases[i]; +#endif #if (DRC_DEBUG & 1) hash_collisions = 0; #endif } - //assert(sh2->pc_hashtab == NULL); - sh2->pc_hashtab = calloc(sizeof(sh2->pc_hashtab[0]), MAX_HASH_ENTRIES); - if (sh2->pc_hashtab == NULL) - return -1; + if (hash_table == NULL) { + hash_table = calloc(sizeof(hash_table[0]), MAX_HASH_ENTRIES); + if (hash_table == NULL) + return -1; + } return 0; } void sh2_drc_finish(SH2 *sh2) { - if (block_table != NULL) { - free(block_table); - block_table = NULL; + if (block_tables[0] != NULL) { +#if (DRC_DEBUG & 1) + block_stats(); +#endif + free(block_tables[0]); + memset(block_tables, 0, sizeof(block_tables)); } - free(sh2->pc_hashtab); - sh2->pc_hashtab = NULL; + if (hash_table != NULL) { + free(hash_table); + hash_table = NULL; + } } diff --git a/cpu/sh2/compiler.h b/cpu/sh2/compiler.h index c6b6a571..37e8bc2d 100644 --- a/cpu/sh2/compiler.h +++ b/cpu/sh2/compiler.h @@ -1,3 +1,5 @@ int sh2_drc_init(SH2 *sh2); void sh2_drc_finish(SH2 *sh2); +void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid); +void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid); diff --git a/cpu/sh2/sh2.h b/cpu/sh2/sh2.h index f9435e04..d722dea4 100644 --- a/cpu/sh2/sh2.h +++ b/cpu/sh2/sh2.h @@ -18,13 +18,13 @@ typedef struct unsigned int test_irq; // common - void *read8_map; // 70 - void *read16_map; - void *write8_map; - void *write16_map; + const void *read8_map; // 70 + const void *read16_map; + const void **write8_tab; + const void **write16_tab; // drc stuff - void **pc_hashtab; // 80 + //void **pc_hashtab; // 80 int pending_level; // MAX(pending_irl, pending_int_irq) int pending_irl; diff --git a/pico/32x/memory.c b/pico/32x/memory.c index 7cad0304..57a28734 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -22,6 +22,9 @@ */ #include "../pico_int.h" #include "../memory.h" +#ifdef DRC_SH2 +#include "../../cpu/sh2/compiler.h" +#endif #if 0 #undef ash2_end_run @@ -1054,9 +1057,26 @@ static void sh2_write8_dram1(u32 a, u32 d, int id) sh2_write8_dramN(1); } +static void sh2_write8_sdram(u32 a, u32 d, int id) +{ + u32 a1 = a & 0x3ffff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; + if (t) + sh2_drc_wcheck_ram(a, t, id); +#endif + Pico32xMem->sdram[a1 ^ 1] = d; +} + static void sh2_write8_da(u32 a, u32 d, int id) { - Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d; + u32 a1 = a & 0xfff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; + if (t) + sh2_drc_wcheck_da(a, t, id); +#endif + Pico32xMem->data_array[id][a1 ^ 1] = d; } // write16 @@ -1113,9 +1133,26 @@ static void sh2_write16_dram1(u32 a, u32 d, int id) sh2_write16_dramN(1); } +static void sh2_write16_sdram(u32 a, u32 d, int id) +{ + u32 a1 = a & 0x3ffff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; + if (t) + sh2_drc_wcheck_ram(a, t, id); +#endif + ((u16 *)Pico32xMem->sdram)[a1 / 2] = d; +} + static void sh2_write16_da(u32 a, u32 d, int id) { - ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d; + u32 a1 = a & 0xfff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; + if (t) + sh2_drc_wcheck_da(a, t, id); +#endif + ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d; } @@ -1181,53 +1218,36 @@ u32 p32x_sh2_read32(u32 a, SH2 *sh2) void p32x_sh2_write8(u32 a, u32 d, SH2 *sh2) { - const sh2_memmap *sh2_map = sh2->write8_map; - uptr p; + const void **sh2_wmap = sh2->write8_tab; + sh2_write_handler *wh; - sh2_map += SH2MAP_ADDR2OFFS(a); - p = sh2_map->addr; - if (p & (1 << 31)) - ((sh2_write_handler *)(p << 1))(a, d, sh2->is_slave); - else - *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1)) = d; + wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)]; + wh(a, d, sh2->is_slave); } void p32x_sh2_write16(u32 a, u32 d, SH2 *sh2) { - const sh2_memmap *sh2_map = sh2->write16_map; - uptr p; + const void **sh2_wmap = sh2->write16_tab; + sh2_write_handler *wh; - sh2_map += SH2MAP_ADDR2OFFS(a); - p = sh2_map->addr; - if (p & (1 << 31)) - ((sh2_write_handler *)(p << 1))(a, d, sh2->is_slave); - else - *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)) = d; + wh = sh2_wmap[SH2MAP_ADDR2OFFS(a)]; + wh(a, d, sh2->is_slave); } void p32x_sh2_write32(u32 a, u32 d, SH2 *sh2) { - const sh2_memmap *sh2_map = sh2->write16_map; + const void **sh2_wmap = sh2->write16_tab; sh2_write_handler *handler; u32 offs; - uptr p; offs = SH2MAP_ADDR2OFFS(a); - sh2_map += offs; - p = sh2_map->addr; - if (!(p & (1 << 31))) { - u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); - pd[0] = d >> 16; - pd[1] = d; - return; - } if (offs == 0x1f) { sh2_peripheral_write32(a, d, sh2->is_slave); return; } - handler = (sh2_write_handler *)(p << 1); + handler = sh2_wmap[offs]; handler(a, d >> 16, sh2->is_slave); handler(a + 2, d, sh2->is_slave); } @@ -1355,7 +1375,8 @@ static void get_bios(void) #define MAP_HANDLER(h) (((uptr)(h) >> 1) | (1 << 31)) static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20]; -static sh2_memmap sh2_write8_map[0x20], sh2_write16_map[0x20]; +// for writes we are using handlers only +static void *sh2_write8_map[0x20], *sh2_write16_map[0x20]; void Pico32xSwapDRAM(int b) { @@ -1368,8 +1389,8 @@ void Pico32xSwapDRAM(int b) sh2_read8_map[2].addr = sh2_read8_map[6].addr = sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]); - sh2_write8_map[2].addr = sh2_write8_map[6].addr = MAP_HANDLER(b ? sh2_write8_dram1 : sh2_write8_dram0); - sh2_write16_map[2].addr = sh2_write16_map[6].addr = MAP_HANDLER(b ? sh2_write16_dram1 : sh2_write16_dram0); + sh2_write8_map[2] = sh2_write8_map[6] = b ? sh2_write8_dram1 : sh2_write8_dram0; + sh2_write16_map[2] = sh2_write16_map[6] = b ? sh2_write16_dram1 : sh2_write16_dram0; } void PicoMemSetup32x(void) @@ -1426,15 +1447,15 @@ void PicoMemSetup32x(void) for (i = 0; i < 0x20; i++) { sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped); sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped); - sh2_write8_map[i].addr = MAP_HANDLER(sh2_write8_unmapped); - sh2_write16_map[i].addr = MAP_HANDLER(sh2_write16_unmapped); + sh2_write8_map[i] = sh2_write8_unmapped; + sh2_write16_map[i] = sh2_write16_unmapped; } // CS0 sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0); sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0); - sh2_write8_map[0].addr = sh2_write8_map[4].addr = MAP_HANDLER(sh2_write8_cs0); - sh2_write16_map[0].addr = sh2_write16_map[4].addr = MAP_HANDLER(sh2_write16_cs0); + sh2_write8_map[0] = sh2_write8_map[4] = sh2_write8_cs0; + sh2_write16_map[0] = sh2_write16_map[4] = sh2_write16_cs0; // CS1 - ROM sh2_read8_map[1].addr = sh2_read8_map[5].addr = sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom); @@ -1445,31 +1466,29 @@ void PicoMemSetup32x(void) sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff; // CS3 - SDRAM sh2_read8_map[3].addr = sh2_read8_map[7].addr = - sh2_read16_map[3].addr = sh2_read16_map[7].addr = - sh2_write8_map[3].addr = sh2_write8_map[7].addr = - sh2_write16_map[3].addr = sh2_write16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram); + sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram); + sh2_write8_map[3] = sh2_write8_map[7] = sh2_write8_sdram; + sh2_write16_map[3] = sh2_write16_map[7] = sh2_write16_sdram; sh2_read8_map[3].mask = sh2_read8_map[7].mask = - sh2_read16_map[3].mask = sh2_read16_map[7].mask = - sh2_write8_map[3].mask = sh2_write8_map[7].mask = - sh2_write16_map[3].mask = sh2_write16_map[7].mask = 0x03ffff; + sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff; // SH2 data array sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da); sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da); - sh2_write8_map[0x18].addr = MAP_HANDLER(sh2_write8_da); - sh2_write16_map[0x18].addr = MAP_HANDLER(sh2_write16_da); + sh2_write8_map[0x18] = sh2_write8_da; + sh2_write16_map[0x18] = sh2_write16_da; // SH2 IO sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8); sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16); - sh2_write8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_write8); - sh2_write16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_write16); + sh2_write8_map[0x1f] = sh2_peripheral_write8; + sh2_write16_map[0x1f] = sh2_peripheral_write16; // map DRAM area, both 68k and SH2 Pico32xSwapDRAM(1); msh2.read8_map = ssh2.read8_map = sh2_read8_map; msh2.read16_map = ssh2.read16_map = sh2_read16_map; - msh2.write8_map = ssh2.write8_map = sh2_write8_map; - msh2.write16_map = ssh2.write16_map = sh2_write16_map; + msh2.write8_tab = ssh2.write8_tab = (const void **)sh2_write8_map; + msh2.write16_tab = ssh2.write16_tab = (const void **)sh2_write16_map; // setup poll detector m68k_poll.flag = P32XF_68KPOLL; diff --git a/pico/carthw/svp/compiler.c b/pico/carthw/svp/compiler.c index da25ea96..cda7df0f 100644 --- a/pico/carthw/svp/compiler.c +++ b/pico/carthw/svp/compiler.c @@ -1766,7 +1766,7 @@ void *ssp_translate_block(int pc) tr_flush_dirty_pmcrs(); emit_block_epilogue(ccount, end_cond, jump_pc, pc); - if (tcache_ptr - tcache > DRC_TCACHE_SIZE/4) { + if (tcache_ptr - (u32 *)tcache > DRC_TCACHE_SIZE/4) { elprintf(EL_ANOMALY|EL_STATUS|EL_SVP, "tcache overflow!\n"); fflush(stdout); exit(1); @@ -1825,7 +1825,7 @@ int ssp1601_dyn_startup(void) } memset(tcache, 0, DRC_TCACHE_SIZE); - tcache_ptr = tcache; + tcache_ptr = (void *)tcache; PicoLoadStateHook = ssp1601_state_load; diff --git a/pico/pico_int.h b/pico/pico_int.h index 4804ad17..cb6ae7c9 100644 --- a/pico/pico_int.h +++ b/pico/pico_int.h @@ -472,6 +472,9 @@ typedef struct #define DMAC_FIFO_LEN (4*4) #define PWM_BUFF_LEN 1024 // in one channel samples +#define SH2_DRCBLK_RAM_SHIFT 1 +#define SH2_DRCBLK_DA_SHIFT 1 + struct Pico32x { unsigned short regs[0x20]; @@ -491,9 +494,15 @@ struct Pico32x struct Pico32xMem { unsigned char sdram[0x40000]; +#ifdef DRC_SH2 + unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)]; +#endif unsigned short dram[2][0x20000/2]; // AKA fb unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM) +#ifdef DRC_SH2 + unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)]; +#endif unsigned char sh2_rom_m[0x800]; unsigned char sh2_rom_s[0x400]; unsigned short pal[0x100]; @@ -727,6 +736,10 @@ static __inline int isspace_(int c) return (0x09 <= c && c <= 0x0d) || c == ' '; } +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) +#endif + // emulation event logging #ifndef EL_LOGMASK #define EL_LOGMASK 0 -- 2.39.5