From f81107f59093904c3daac2e9c257261fddc6caf0 Mon Sep 17 00:00:00 2001
From: notaz <notasas@gmail.com>
Date: Wed, 7 Aug 2013 03:26:02 +0300
Subject: [PATCH] 32x: memhandler improvements

- use consistent read tables (with write)
- use sh2 ptr instead of id
- place data_array/peri_regs in sh2 struct
---
 cpu/drc/emit_arm.c |   2 +-
 cpu/drc/emit_x86.c |   2 +-
 cpu/sh2/compiler.c |   7 +-
 cpu/sh2/sh2.c      |  11 +-
 cpu/sh2/sh2.h      |  13 ++-
 pico/32x/32x.c     |  10 +-
 pico/32x/memory.c  | 278 ++++++++++++++++++++++-----------------------
 pico/32x/sh2soc.c  |  83 +++++++-------
 pico/debug.c       |   6 +-
 pico/pico_int.h    |  19 ++--
 pico/state.c       |  16 +--
 11 files changed, 224 insertions(+), 223 deletions(-)

diff --git a/cpu/drc/emit_arm.c b/cpu/drc/emit_arm.c
index 2ac8e326..64face12 100644
--- a/cpu/drc/emit_arm.c
+++ b/cpu/drc/emit_arm.c
@@ -739,7 +739,7 @@ static int emith_xbranch(int cond, void *target, int is_call)
 #define emith_sh2_wcall(a, tab) { \
 	emith_lsr(12, a, SH2_WRITE_SHIFT); \
 	EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
-	emith_ctx_read(2, offsetof(SH2, is_slave)); \
+	emith_move_r_r(2, CONTEXT_REG); \
 	emith_jump_reg(12); \
 }
 
diff --git a/cpu/drc/emit_x86.c b/cpu/drc/emit_x86.c
index f14430bf..754c27fe 100644
--- a/cpu/drc/emit_x86.c
+++ b/cpu/drc/emit_x86.c
@@ -635,7 +635,7 @@ enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
 	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
 	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
 	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
-	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
+	emith_move_r_r(arg2_, CONTEXT_REG); \
 	emith_jump_reg(xBX); \
 }
 
diff --git a/cpu/sh2/compiler.c b/cpu/sh2/compiler.c
index e9838978..015a0986 100644
--- a/cpu/sh2/compiler.c
+++ b/cpu/sh2/compiler.c
@@ -349,7 +349,7 @@ static u32  REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
 static u32  REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
-static int  REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
+static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
 
 // address space stuff
 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
@@ -363,6 +363,7 @@ static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
   }
   else if ((a & 0xfffff000) == 0xc0000000) {
     // data array
+    // FIXME: access sh2->data_array instead
     poffs = offsetof(SH2, p_da);
     *mask = 0xfff;
   }
@@ -3159,7 +3160,7 @@ void sh2_drc_mem_setup(SH2 *sh2)
 {
   // fill the convenience pointers
   sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
-  sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
+  sh2->p_da = sh2->data_array;
   sh2->p_sdram = Pico32xMem->sdram;
   sh2->p_rom = Pico.rom;
 }
@@ -3277,7 +3278,7 @@ static void *dr_get_pc_base(u32 pc, int is_slave)
   }
   else if ((pc & 0xfffff000) == 0xc0000000) {
     // data array
-    ret = Pico32xMem->data_array[is_slave];
+    ret = sh2s[is_slave].data_array;
     mask = 0xfff;
   }
   else if ((pc & 0xc6000000) == 0x06000000) {
diff --git a/cpu/sh2/sh2.c b/cpu/sh2/sh2.c
index fbf0c6d3..847035a5 100644
--- a/cpu/sh2/sh2.c
+++ b/cpu/sh2/sh2.c
@@ -14,12 +14,13 @@
 
 #define I 0xf0
 
-int sh2_init(SH2 *sh2, int is_slave)
+int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2)
 {
 	int ret = 0;
 
 	memset(sh2, 0, offsetof(SH2, mult_m68k_to_sh2));
 	sh2->is_slave = is_slave;
+	sh2->other_sh2 = other_sh2;
 	pdb_register_cpu(sh2, PDBCT_SH2, is_slave ? "ssh2" : "msh2");
 #ifdef DRC_SH2
 	ret = sh2_drc_init(sh2);
@@ -145,16 +146,13 @@ enum ctl_byte {
 	CTL_CYCLES = 0x85,
 };
 
-#define SH2MAP_ADDR2OFFS_R(a) \
-  ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
-
 static unsigned int local_read32(SH2 *sh2, u32 a)
 {
 	const sh2_memmap *sh2_map = sh2->read16_map;
 	u16 *pd;
 	uptr p;
 
-	sh2_map += SH2MAP_ADDR2OFFS_R(a);
+	sh2_map += (a >> 25);
 	p = sh2_map->addr;
 	if (!map_flag_set(p)) {
 		pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
@@ -163,8 +161,7 @@ static unsigned int local_read32(SH2 *sh2, u32 a)
 
 	if ((a & 0xfffff000) == 0xc0000000) {
 		// data array
-		pd = (u16 *)Pico32xMem->data_array[sh2->is_slave]
-			+ (a & 0xfff) / 2;
+		pd = (u16 *)sh2->data_array + (a & 0xfff) / 2;
 		return (pd[0] << 16) | pd[1];
 	}
 	if ((a & 0xdfffffc0) == 0x4000) {
diff --git a/cpu/sh2/sh2.h b/cpu/sh2/sh2.h
index 42de6305..d0b7377c 100644
--- a/cpu/sh2/sh2.h
+++ b/cpu/sh2/sh2.h
@@ -63,10 +63,15 @@ typedef struct SH2_
 
 	unsigned int	cycles_timeslice;
 
+	struct SH2_	*other_sh2;
+
 	// we use 68k reference cycles for easier sync
 	unsigned int	m68krcycles_done;
 	unsigned int	mult_m68k_to_sh2;
 	unsigned int	mult_sh2_to_m68k;
+
+	unsigned char	data_array[0x1000]; // cache (can be used as RAM)
+	unsigned int	peri_regs[0x200/4]; // periphereal regs
 } SH2;
 
 #define CYCLE_MULT_SHIFT 10
@@ -75,7 +80,7 @@ typedef struct SH2_
 #define C_SH2_TO_M68K(xsh2, c) \
 	((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)
 
-int  sh2_init(SH2 *sh2, int is_slave);
+int  sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);
 void sh2_finish(SH2 *sh2);
 void sh2_reset(SH2 *sh2);
 int  sh2_irl_irq(SH2 *sh2, int level, int nested_call);
@@ -94,9 +99,9 @@ int  sh2_execute(SH2 *sh2, int cycles);
 unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
 unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
 unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
-int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
-int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
-int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
+void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);
+void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
+void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
 
 // debug
 #ifdef DRC_CMP
diff --git a/pico/32x/32x.c b/pico/32x/32x.c
index ed0c2105..d0110c13 100644
--- a/pico/32x/32x.c
+++ b/pico/32x/32x.c
@@ -73,9 +73,9 @@ void Pico32xStartup(void)
 
   // TODO: OOM handling
   PicoAHW |= PAHW_32X;
-  sh2_init(&msh2, 0);
+  sh2_init(&msh2, 0, &ssh2);
   msh2.irq_callback = sh2_irq_cb;
-  sh2_init(&ssh2, 1);
+  sh2_init(&ssh2, 1, &msh2);
   ssh2.irq_callback = sh2_irq_cb;
 
   PicoMemSetup32x();
@@ -85,8 +85,8 @@ void Pico32xStartup(void)
   if (!Pico.m.pal)
     Pico32x.vdp_regs[0] |= P32XV_nPAL;
 
-  PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
-  PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
+  PREG8(msh2.peri_regs, 4) =
+  PREG8(ssh2.peri_regs, 4) = 0x84; // SCI SSR
 
   rendstatus_old = -1;
 
@@ -339,7 +339,7 @@ static inline void run_sh2(SH2 *sh2, int m68k_cycles)
 // note: recursive call
 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
 {
-  SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
+  SH2 *osh2 = sh2->other_sh2;
   int left_to_event;
   int m68k_cycles;
 
diff --git a/pico/32x/memory.c b/pico/32x/memory.c
index 45c192d5..fd6ff45e 100644
--- a/pico/32x/memory.c
+++ b/pico/32x/memory.c
@@ -432,17 +432,18 @@ static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
 // ------------------------------------------------------------------
 // SH2 regs
 
-static u32 p32x_sh2reg_read16(u32 a, int cpuid)
+static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
 {
   u16 *r = Pico32x.regs;
   a &= 0xfe; // ?
 
   switch (a) {
     case 0x00: // adapter/irq ctl
-      return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
+      return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
+        | Pico32x.sh2irq_mask[sh2->is_slave];
     case 0x04: // H count (often as comm too)
-      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
-      sh2s_sync_on_read(&sh2s[cpuid]);
+      sh2_poll_detect(sh2, a, SH2_STATE_CPOLL);
+      sh2s_sync_on_read(sh2);
       return Pico32x.sh2_regs[4 / 2];
     case 0x10: // DREQ len
       return r[a / 2];
@@ -457,22 +458,22 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     if (Pico32x.comm_dirty_68k & comreg)
       Pico32x.comm_dirty_68k &= ~comreg;
     else
-      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
-    sh2s_sync_on_read(&sh2s[cpuid]);
+      sh2_poll_detect(sh2, a, SH2_STATE_CPOLL);
+    sh2s_sync_on_read(sh2);
     return r[a / 2];
   }
   if ((a & 0x30) == 0x30) {
-    return p32x_pwm_read16(a, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
+    return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
   }
 
   return 0;
 }
 
-static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
 {
   a &= 0xff;
 
-  sh2s[cpuid].poll_addr = 0;
+  sh2->poll_addr = 0;
 
   switch (a) {
     case 0: // FM
@@ -482,20 +483,20 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
     case 1: // HEN/irq masks
       if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
         elprintf(EL_ANOMALY|EL_32X, "HEN");
-      Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
+      Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x8f;
       Pico32x.sh2_regs[0] &= ~0x80;
       Pico32x.sh2_regs[0] |= d & 0x80;
       if (d & 1)
-        p32x_pwm_schedule_sh2(&sh2s[cpuid]);
-      p32x_update_irls(&sh2s[cpuid], 0);
+        p32x_pwm_schedule_sh2(sh2);
+      p32x_update_irls(sh2, 0);
       return;
     case 5: // H count
       d &= 0xff;
       if (Pico32x.sh2_regs[4 / 2] != d) {
         Pico32x.sh2_regs[4 / 2] = d;
-        p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-          sh2_cycles_done_m68k(&sh2s[cpuid]));
-        sh2_end_run(&sh2s[cpuid], 4);
+        p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+          sh2_cycles_done_m68k(sh2));
+        sh2_end_run(sh2, 4);
       }
       return;
   }
@@ -508,19 +509,19 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
 
     r8[a ^ 1] = d;
     p32x_m68k_poll_event(P32XF_68KCPOLL);
-    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(sh2));
     comreg = 1 << (a & 0x0f) / 2;
     Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
 }
 
-static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
 {
   a &= 0xfe;
 
-  sh2s[cpuid].poll_addr = 0;
+  sh2->poll_addr = 0;
 
   // comm
   if ((a & 0x30) == 0x20) {
@@ -530,15 +531,15 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
 
     Pico32x.regs[a / 2] = d;
     p32x_m68k_poll_event(P32XF_68KCPOLL);
-    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(sh2));
     comreg = 1 << (a & 0x0f) / 2;
     Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
   // PWM
   else if ((a & 0x30) == 0x30) {
-    p32x_pwm_write16(a, d, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
     return;
   }
 
@@ -550,18 +551,18 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
     case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
     case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
     case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
-    case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
+    case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls;
     case 0x1c:
       Pico32x.sh2irqs &= ~P32XI_PWM;
-      p32x_pwm_schedule_sh2(&sh2s[cpuid]);
+      p32x_pwm_schedule_sh2(sh2);
       goto irls;
   }
 
-  p32x_sh2reg_write8(a | 1, d, cpuid);
+  p32x_sh2reg_write8(a | 1, d, sh2);
   return;
 
 irls:
-  p32x_update_irls(&sh2s[cpuid], 0);
+  p32x_update_irls(sh2, 0);
 }
 
 // ------------------------------------------------------------------
@@ -821,26 +822,25 @@ static void m68k_write8_dram1_ow(u32 a, u32 d)
   sh2_write8_dramN(1);
 }
 
-#define sh2_write16_dramN(n, ret) \
+#define sh2_write16_dramN(n) \
   u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
   if (!(a & 0x20000)) { \
     *pd = d; \
-    return ret; \
+    return; \
   } \
   /* overwrite */ \
   if (!(d & 0xff00)) d |= *pd & 0xff00; \
   if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
-  *pd = d; \
-  return ret
+  *pd = d;
 
 static void m68k_write16_dram0_ow(u32 a, u32 d)
 {
-  sh2_write16_dramN(0,);
+  sh2_write16_dramN(0);
 }
 
 static void m68k_write16_dram1_ow(u32 a, u32 d)
 {
-  sh2_write16_dramN(1,);
+  sh2_write16_dramN(1);
 }
 
 // -----------------------------------------------------------------
@@ -898,33 +898,33 @@ static void bank_switch(int b)
 // -----------------------------------------------------------------
 
 // read8
-static u32 sh2_read8_unmapped(u32 a, int id)
+static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped r8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, 0, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
   return 0;
 }
 
-static u32 sh2_read8_cs0(u32 a, int id)
+static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
 {
   u32 d = 0;
 
   // 0x3ff00 is veridied
   if ((a & 0x3ff00) == 0x4000) {
-    d = p32x_sh2reg_read16(a, id);
+    d = p32x_sh2reg_read16(a, sh2);
     goto out_16to8;
   }
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+    sh2_poll_detect(sh2, a, SH2_STATE_VPOLL);
     goto out_16to8;
   }
 
   // TODO: mirroring?
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+  if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
     return Pico32xMem->sh2_rom_m[a ^ 1];
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+  if (sh2->is_slave  && a < sizeof(Pico32xMem->sh2_rom_s))
     return Pico32xMem->sh2_rom_s[a ^ 1];
 
   if ((a & 0x3fe00) == 0x4200) {
@@ -932,7 +932,7 @@ static u32 sh2_read8_cs0(u32 a, int id)
     goto out_16to8;
   }
 
-  return sh2_read8_unmapped(a, id);
+  return sh2_read8_unmapped(a, sh2);
 
 out_16to8:
   if (a & 1)
@@ -941,29 +941,29 @@ out_16to8:
     d >>= 8;
 
   elprintf(EL_32X, "%csh2 r8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
   return d;
 }
 
-static u32 sh2_read8_da(u32 a, int id)
+static u32 sh2_read8_da(u32 a, SH2 *sh2)
 {
-  return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+  return sh2->data_array[(a & 0xfff) ^ 1];
 }
 
 // read16
-static u32 sh2_read16_unmapped(u32 a, int id)
+static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped r16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, 0, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
   return 0;
 }
 
-static u32 sh2_read16_cs0(u32 a, int id)
+static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
 {
   u32 d = 0;
 
   if ((a & 0x3ff00) == 0x4000) {
-    d = p32x_sh2reg_read16(a, id);
+    d = p32x_sh2reg_read16(a, sh2);
     if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
       return d;
     goto out;
@@ -971,13 +971,13 @@ static u32 sh2_read16_cs0(u32 a, int id)
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+    sh2_poll_detect(sh2, a, SH2_STATE_VPOLL);
     goto out;
   }
 
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+  if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
     return *(u16 *)(Pico32xMem->sh2_rom_m + a);
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+  if (sh2->is_slave  && a < sizeof(Pico32xMem->sh2_rom_s))
     return *(u16 *)(Pico32xMem->sh2_rom_s + a);
 
   if ((a & 0x3fe00) == 0x4200) {
@@ -985,165 +985,159 @@ static u32 sh2_read16_cs0(u32 a, int id)
     goto out;
   }
 
-  return sh2_read16_unmapped(a, id);
+  return sh2_read16_unmapped(a, sh2);
 
 out:
   elprintf(EL_32X, "%csh2 r16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
   return d;
 }
 
-static u32 sh2_read16_da(u32 a, int id)
+static u32 sh2_read16_da(u32 a, SH2 *sh2)
 {
-  return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+  return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
 }
 
-static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+// writes
+static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
 {
-  return 0;
 }
 
 // write8
-static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped w8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
-  return 0;
+    sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
 }
 
-static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_32X, "%csh2 w8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
 
   if (Pico32x.regs[0] & P32XS_FM) {
     if ((a & 0x3ff00) == 0x4100) {
-      sh2s[id].poll_addr = 0;
+      sh2->poll_addr = 0;
       p32x_vdp_write8(a, d);
-      return 0;
+      return;
     }
   }
 
   if ((a & 0x3ff00) == 0x4000) {
-    p32x_sh2reg_write8(a, d, id);
-    return 1;
+    p32x_sh2reg_write8(a, d, sh2);
+    return;
   }
 
-  return sh2_write8_unmapped(a, d, id);
+  sh2_write8_unmapped(a, d, sh2);
 }
 
-static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write8_dramN(0);
-  return 0;
 }
 
-static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write8_dramN(1);
-  return 0;
 }
 
-static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0x3ffff;
 #ifdef DRC_SH2
   int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
   if (t)
-    sh2_drc_wcheck_ram(a, t, id);
+    sh2_drc_wcheck_ram(a, t, sh2->is_slave);
 #endif
   Pico32xMem->sdram[a1 ^ 1] = d;
-  return 0;
 }
 
-static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0xfff;
 #ifdef DRC_SH2
+  int id = sh2->is_slave;
   int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
   if (t)
     sh2_drc_wcheck_da(a, t, id);
 #endif
-  Pico32xMem->data_array[id][a1 ^ 1] = d;
-  return 0;
+  sh2->data_array[a1 ^ 1] = d;
 }
 
 // write16
-static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped w16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
-  return 0;
+    sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
 }
 
-static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
 {
   if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
     elprintf(EL_32X, "%csh2 w16 [%08x]     %04x @%06x",
-      id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+      sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
 
   if (Pico32x.regs[0] & P32XS_FM) {
     if ((a & 0x3ff00) == 0x4100) {
-      sh2s[id].poll_addr = 0;
-      p32x_vdp_write16(a, d, &sh2s[id]);
-      return 0;
+      sh2->poll_addr = 0;
+      p32x_vdp_write16(a, d, sh2);
+      return;
     }
 
     if ((a & 0x3fe00) == 0x4200) {
       Pico32xMem->pal[(a & 0x1ff) / 2] = d;
       Pico32x.dirty_pal = 1;
-      return 0;
+      return;
     }
   }
 
   if ((a & 0x3ff00) == 0x4000) {
-    p32x_sh2reg_write16(a, d, id);
-    return 1;
+    p32x_sh2reg_write16(a, d, sh2);
+    return;
   }
 
-  return sh2_write16_unmapped(a, d, id);
+  sh2_write16_unmapped(a, d, sh2);
 }
 
-static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
 {
-  sh2_write16_dramN(0, 0);
+  sh2_write16_dramN(0);
 }
 
-static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
 {
-  sh2_write16_dramN(1, 0);
+  sh2_write16_dramN(1);
 }
 
-static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0x3ffff;
 #ifdef DRC_SH2
   int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
   if (t)
-    sh2_drc_wcheck_ram(a, t, id);
+    sh2_drc_wcheck_ram(a, t, sh2->is_slave);
 #endif
   ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
-  return 0;
 }
 
-static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0xfff;
 #ifdef DRC_SH2
+  int id = sh2->is_slave;
   int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
   if (t)
     sh2_drc_wcheck_da(a, t, id);
 #endif
-  ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
-  return 0;
+  ((u16 *)sh2->data_array)[a1 / 2] = d;
 }
 
 
-typedef u32 (sh2_read_handler)(u32 a, int id);
-typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
+typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
+typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
 
 #define SH2MAP_ADDR2OFFS_R(a) \
-  ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
+  ((u32)(a) >> SH2_READ_SHIFT)
 
 #define SH2MAP_ADDR2OFFS_W(a) \
   ((u32)(a) >> SH2_WRITE_SHIFT)
@@ -1156,7 +1150,7 @@ u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
   sh2_map += SH2MAP_ADDR2OFFS_R(a);
   p = sh2_map->addr;
   if (map_flag_set(p))
-    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+    return ((sh2_read_handler *)(p << 1))(a, sh2);
   else
     return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
 }
@@ -1169,7 +1163,7 @@ u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
   sh2_map += SH2MAP_ADDR2OFFS_R(a);
   p = sh2_map->addr;
   if (map_flag_set(p))
-    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+    return ((sh2_read_handler *)(p << 1))(a, sh2);
   else
     return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
 }
@@ -1191,48 +1185,46 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
   }
 
   if (offs == 0x1f)
-    return sh2_peripheral_read32(a, sh2->is_slave);
+    return sh2_peripheral_read32(a, sh2);
 
   handler = (sh2_read_handler *)(p << 1);
-  return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
+  return (handler(a, sh2) << 16) | handler(a + 2, sh2);
 }
 
-// return nonzero if write potentially causes an interrupt (used by drc)
-int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write8_tab;
   sh2_write_handler *wh;
 
   wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
-  return wh(a, d, sh2->is_slave);
+  wh(a, d, sh2);
 }
 
-int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write16_tab;
   sh2_write_handler *wh;
 
   wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
-  return wh(a, d, sh2->is_slave);
+  wh(a, d, sh2);
 }
 
-int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write16_tab;
-  sh2_write_handler *handler;
+  sh2_write_handler *wh;
   u32 offs;
 
   offs = SH2MAP_ADDR2OFFS_W(a);
 
   if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
-    sh2_peripheral_write32(a, d, sh2->is_slave);
-    return 0;
+    sh2_peripheral_write32(a, d, sh2);
+    return;
   }
 
-  handler = sh2_wmap[offs];
-  handler(a, d >> 16, sh2->is_slave);
-  handler(a + 2, d, sh2->is_slave);
-  return 0;
+  wh = sh2_wmap[offs];
+  wh(a, d >> 16, sh2);
+  wh(a + 2, d, sh2);
 }
 
 // -----------------------------------------------------------------
@@ -1359,7 +1351,7 @@ static void get_bios(void)
 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
 
-static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
+static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
 // for writes we are using handlers only
 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
 
@@ -1375,8 +1367,8 @@ void Pico32xSwapDRAM(int b)
                  b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
 
   // SH2
-  sh2_read8_map[2].addr   = sh2_read8_map[6].addr   =
-  sh2_read16_map[2].addr  = sh2_read16_map[6].addr  = MAP_MEMORY(Pico32xMem->dram[b]);
+  sh2_read8_map[0x04/2].addr  = sh2_read8_map[0x24/2].addr  =
+  sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
 
   sh2_write8_map[0x04/2]  = sh2_write8_map[0x24/2]  = b ? sh2_write8_dram1 : sh2_write8_dram0;
   sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
@@ -1448,35 +1440,35 @@ void PicoMemSetup32x(void)
   }
 
   // CS0
-  sh2_read8_map[0].addr   = sh2_read8_map[4].addr   = MAP_HANDLER(sh2_read8_cs0);
-  sh2_read16_map[0].addr  = sh2_read16_map[4].addr  = MAP_HANDLER(sh2_read16_cs0);
+  sh2_read8_map[0x00/2].addr  = sh2_read8_map[0x20/2].addr  = MAP_HANDLER(sh2_read8_cs0);
+  sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
   sh2_write8_map[0x00/2]  = sh2_write8_map[0x20/2]  = sh2_write8_cs0;
   sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
   // CS1 - ROM
-  sh2_read8_map[1].addr   = sh2_read8_map[5].addr   =
-  sh2_read16_map[1].addr  = sh2_read16_map[5].addr  = MAP_MEMORY(Pico.rom);
-  sh2_read8_map[1].mask   = sh2_read8_map[5].mask   =
-  sh2_read16_map[1].mask  = sh2_read16_map[5].mask  = 0x3fffff; // FIXME
+  sh2_read8_map[0x02/2].addr  = sh2_read8_map[0x22/2].addr  =
+  sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
+  sh2_read8_map[0x02/2].mask  = sh2_read8_map[0x22/2].mask  =
+  sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
   // CS2 - DRAM - done by Pico32xSwapDRAM()
-  sh2_read8_map[2].mask   = sh2_read8_map[6].mask   =
-  sh2_read16_map[2].mask  = sh2_read16_map[6].mask  = 0x01ffff;
+  sh2_read8_map[0x04/2].mask  = sh2_read8_map[0x24/2].mask  =
+  sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
   // CS3 - SDRAM
-  sh2_read8_map[3].addr   = sh2_read8_map[7].addr   =
-  sh2_read16_map[3].addr  = sh2_read16_map[7].addr  = MAP_MEMORY(Pico32xMem->sdram);
-  sh2_write8_map[0x06/2]  = sh2_write8_map[0x26/2]  = sh2_write8_sdram;
-  sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
-  sh2_read8_map[3].mask   = sh2_read8_map[7].mask   =
-  sh2_read16_map[3].mask  = sh2_read16_map[7].mask  = 0x03ffff;
+  sh2_read8_map[0x06/2].addr   = sh2_read8_map[0x26/2].addr   =
+  sh2_read16_map[0x06/2].addr  = sh2_read16_map[0x26/2].addr  = MAP_MEMORY(Pico32xMem->sdram);
+  sh2_write8_map[0x06/2]       = sh2_write8_map[0x26/2]       = sh2_write8_sdram;
+  sh2_write16_map[0x06/2]      = sh2_write16_map[0x26/2]      = sh2_write16_sdram;
+  sh2_read8_map[0x06/2].mask   = sh2_read8_map[0x26/2].mask   =
+  sh2_read16_map[0x06/2].mask  = sh2_read16_map[0x26/2].mask  = 0x03ffff;
   // SH2 data array
-  sh2_read8_map[0x18].addr   = MAP_HANDLER(sh2_read8_da);
-  sh2_read16_map[0x18].addr  = MAP_HANDLER(sh2_read16_da);
-  sh2_write8_map[0xc0/2]     = sh2_write8_da;
-  sh2_write16_map[0xc0/2]    = sh2_write16_da;
+  sh2_read8_map[0xc0/2].addr  = MAP_HANDLER(sh2_read8_da);
+  sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
+  sh2_write8_map[0xc0/2]      = sh2_write8_da;
+  sh2_write16_map[0xc0/2]     = sh2_write16_da;
   // SH2 IO
-  sh2_read8_map[0x1f].addr   = MAP_HANDLER(sh2_peripheral_read8);
-  sh2_read16_map[0x1f].addr  = MAP_HANDLER(sh2_peripheral_read16);
-  sh2_write8_map[0xff/2]     = sh2_peripheral_write8;
-  sh2_write16_map[0xff/2]    = sh2_peripheral_write16;
+  sh2_read8_map[0xff/2].addr  = MAP_HANDLER(sh2_peripheral_read8);
+  sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
+  sh2_write8_map[0xff/2]      = sh2_peripheral_write8;
+  sh2_write16_map[0xff/2]     = sh2_peripheral_write16;
 
   // map DRAM area, both 68k and SH2
   Pico32xSwapDRAM(1);
diff --git a/pico/32x/sh2soc.c b/pico/32x/sh2soc.c
index ab4ac529..bdd07a04 100644
--- a/pico/32x/sh2soc.c
+++ b/pico/32x/sh2soc.c
@@ -59,7 +59,7 @@ struct dmac {
 
 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
 {
-  char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
+  char *regs = (void *)sh2->peri_regs;
   struct dmac *dmac = (void *)(regs + 0x180);
   int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
   int vector = (chan == &dmac->chan[0]) ?
@@ -167,7 +167,7 @@ void p32x_timers_recalc(void)
 
   // SH2 timer step
   for (i = 0; i < 2; i++) {
-    tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7;
+    tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
     // Sclk cycles per timer tick
     if (tmp)
       cycles = 0x20 << tmp;
@@ -186,7 +186,7 @@ void p32x_timers_do(unsigned int m68k_slice)
 
   // WDT timers
   for (i = 0; i < 2; i++) {
-    void *pregs = Pico32xMem->sh2_peri_regs[i];
+    void *pregs = sh2s[i].peri_regs;
     if (PREG8(pregs, 0x80) & 0x20) { // TME
       timer_cycles[i] += cycles;
       cnt = PREG8(pregs, 0x81);
@@ -211,44 +211,48 @@ void p32x_timers_do(unsigned int m68k_slice)
 // SH2 internal peripheral memhandlers
 // we keep them in little endian format
 
-u32 sh2_peripheral_read8(u32 a, int id)
+u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
 {
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+  u8 *r = (void *)sh2->peri_regs;
   u32 d;
 
   a &= 0x1ff;
   d = PREG8(r, a);
 
-  elprintf(EL_32XP, "%csh2 peri r8  [%08x]       %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf(EL_32XP, "%csh2 peri r8  [%08x]       %02x @%06x",
+    sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-u32 sh2_peripheral_read16(u32 a, int id)
+u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
 {
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+  u16 *r = (void *)sh2->peri_regs;
   u32 d;
 
   a &= 0x1ff;
   d = r[(a / 2) ^ 1];
 
-  elprintf(EL_32XP, "%csh2 peri r16 [%08x]     %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf(EL_32XP, "%csh2 peri r16 [%08x]     %04x @%06x",
+    sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-u32 sh2_peripheral_read32(u32 a, int id)
+u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
 {
   u32 d;
   a &= 0x1fc;
-  d = Pico32xMem->sh2_peri_regs[id][a / 4];
+  d = sh2->peri_regs[a / 4];
 
-  elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x",
+    sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
+void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
 {
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w8  [%08x]       %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u8 *r = (void *)sh2->peri_regs;
+  elprintf(EL_32XP, "%csh2 peri w8  [%08x]       %02x @%06x",
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
 
   a &= 0x1ff;
   PREG8(r, a) = d;
@@ -256,22 +260,23 @@ int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
   // X-men SCI hack
   if ((a == 2 &&  (d & 0x20)) || // transmiter enabled
       (a == 4 && !(d & 0x80))) { // valid data in TDR
-    void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
+    void *oregs = sh2->other_sh2->peri_regs;
     if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
       int level = PREG8(oregs, 0x60) >> 4;
       int vector = PREG8(oregs, 0x63) & 0x7f;
-      elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
-      sh2_internal_irq(&sh2s[id ^ 1], level, vector);
-      return 1;
+      elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)",
+        (sh2->is_slave ^ 1) ? 's' : 'm', level, vector);
+      sh2_internal_irq(sh2->other_sh2, level, vector);
+      return;
     }
   }
-  return 0;
 }
 
-int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
+void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
 {
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w16 [%08x]     %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u16 *r = (void *)sh2->peri_regs;
+  elprintf(EL_32XP, "%csh2 peri w16 [%08x]     %04x @%06x",
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
 
   a &= 0x1ff;
 
@@ -283,17 +288,17 @@ int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
     }
     if ((d & 0xff00) == 0x5a00) // WTCNT
       PREG8(r, 0x81) = d;
-    return 0;
+    return;
   }
 
   r[(a / 2) ^ 1] = d;
-  return 0;
 }
 
-void sh2_peripheral_write32(u32 a, u32 d, int id)
+void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
 {
-  u32 *r = Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u32 *r = sh2->peri_regs;
+  elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x",
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
 
   a &= 0x1fc;
   r[a / 4] = d;
@@ -301,7 +306,8 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
   switch (a) {
     // division unit (TODO: verify):
     case 0x104: // DVDNT: divident L, starts divide
-      elprintf(EL_32XP, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
+      elprintf(EL_32XP, "%csh2 divide %08x / %08x",
+        sh2->is_slave ? 's' : 'm', d, r[0x100 / 4]);
       if (r[0x100 / 4]) {
         signed int divisor = r[0x100 / 4];
                        r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
@@ -312,7 +318,7 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
       break;
     case 0x114:
       elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
-        id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
+        sh2->is_slave ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
       if (r[0x100 / 4]) {
         signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
         signed int divisor = r[0x100 / 4];
@@ -322,7 +328,8 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
         r[0x11c / 4] = r[0x114 / 4] = divident;
         divident >>= 31;
         if ((unsigned long long)divident + 1 > 1) {
-          //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
+          //elprintf(EL_32XP, "%csh2 divide overflow! @%08x",
+          //  sh2->is_slave ? 's' : 'm', sh2_pc(sh2));
           r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
         }
       }
@@ -333,14 +340,14 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
 
   // perhaps starting a DMA?
   if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
-    struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
+    struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
     if (!(dmac->dmaor & DMA_DME))
       return;
 
     if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[0]);
+      dmac_trigger(sh2, &dmac->chan[0]);
     if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[1]);
+      dmac_trigger(sh2, &dmac->chan[1]);
   }
 }
 
@@ -401,8 +408,8 @@ static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
 
 void p32x_dreq0_trigger(void)
 {
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+  struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+  struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
 
   elprintf(EL_32XP, "dreq0_trigger");
   if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
@@ -415,8 +422,8 @@ void p32x_dreq0_trigger(void)
 
 void p32x_dreq1_trigger(void)
 {
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+  struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+  struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
   int hit = 0;
 
   elprintf(EL_32XP, "dreq1_trigger");
diff --git a/pico/debug.c b/pico/debug.c
index e579296a..03451201 100644
--- a/pico/debug.c
+++ b/pico/debug.c
@@ -83,7 +83,7 @@ char *PDebug32x(void)
     i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
 
   sprintf(dstrp, "                   mSH2              sSH2\n"); MVP;
-  sprintf(dstrp, "PC,SR %08x,     %03x %08x,     %03x\n", sh2_pc(0), sh2_sr(0), sh2_pc(1), sh2_sr(1)); MVP;
+  sprintf(dstrp, "PC,SR %08x,     %03x %08x,     %03x\n", sh2_pc(&msh2), sh2_sr(0), sh2_pc(&ssh2), sh2_sr(1)); MVP;
   for (i = 0; i < 16/2; i++) {
     sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
       sh2_reg(0,i), sh2_reg(0,i+8), sh2_reg(1,i), sh2_reg(1,i+8)); MVP;
@@ -345,8 +345,8 @@ void PDebugDumpMem(void)
     dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
     dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
     dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
-    dump_ram(Pico32xMem->data_array[0], "dumps/data_array0.bin");
-    dump_ram(Pico32xMem->data_array[1], "dumps/data_array1.bin");
+    dump_ram(msh2.data_array, "dumps/data_array0.bin");
+    dump_ram(ssh2.data_array, "dumps/data_array1.bin");
   }
 #endif
 }
diff --git a/pico/pico_int.h b/pico/pico_int.h
index 7c890c5a..339d1bf1 100644
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -245,7 +245,7 @@ extern SH2 sh2s[2];
   } \
 } while (0)
 # define sh2_cycles_left(sh2) (sh2)->icount
-# define sh2_pc(c)    (c) ? ssh2.ppc : msh2.ppc
+# define sh2_pc(sh2) (sh2)->ppc
 #else
 # define sh2_end_run(sh2, after_) do { \
   int left_ = (signed int)(sh2)->sr >> 12; \
@@ -256,7 +256,7 @@ extern SH2 sh2s[2];
   } \
 } while (0)
 # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)
-# define sh2_pc(c)    (c) ? ssh2.pc : msh2.pc
+# define sh2_pc(sh2) (sh2)->pc
 #endif
 
 #define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))
@@ -490,6 +490,7 @@ typedef struct
 #define SH2_DRCBLK_RAM_SHIFT 1
 #define SH2_DRCBLK_DA_SHIFT  1
 
+#define SH2_READ_SHIFT 25
 #define SH2_WRITE_SHIFT 25
 
 struct Pico32x
@@ -526,7 +527,6 @@ struct Pico32xMem
     unsigned char  m68k_rom[0x100];
     unsigned char  m68k_rom_bank[0x10000]; // M68K_BANK_SIZE
   };
-  unsigned char  data_array[2][0x1000]; // cache in SH2s (can be used as RAM)
 #ifdef DRC_SH2
   unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
 #endif
@@ -534,7 +534,6 @@ struct Pico32xMem
   unsigned char  sh2_rom_s[0x400];
   unsigned short pal[0x100];
   unsigned short pal_native[0x100];     // converted to native (for renderer)
-  unsigned int   sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s
   signed short   pwm[2*PWM_BUFF_LEN];   // PWM buffer for current frame
   signed short   pwm_fifo[2][4];        // [0] - current, others - fifo entries
 };
@@ -794,12 +793,12 @@ void p32x_dreq0_trigger(void);
 void p32x_dreq1_trigger(void);
 void p32x_timers_recalc(void);
 void p32x_timers_do(unsigned int m68k_slice);
-unsigned int sh2_peripheral_read8(unsigned int a, int id);
-unsigned int sh2_peripheral_read16(unsigned int a, int id);
-unsigned int sh2_peripheral_read32(unsigned int a, int id);
-int sh2_peripheral_write8(unsigned int a, unsigned int d, int id);
-int sh2_peripheral_write16(unsigned int a, unsigned int d, int id);
-void sh2_peripheral_write32(unsigned int a, unsigned int d, int id);
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);
+void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);
+void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);
+void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);
 
 #else
 #define Pico32xInit()
diff --git a/pico/state.c b/pico/state.c
index 3969e188..de2d8ab6 100644
--- a/pico/state.c
+++ b/pico/state.c
@@ -318,13 +318,13 @@ static int state_save(void *file)
 
     sh2_pack(&sh2s[0], cpubuff);
     CHECKED_WRITE_BUFF(CHUNK_MSH2,      cpubuff);
-    CHECKED_WRITE_BUFF(CHUNK_MSH2_DATA, Pico32xMem->data_array[0]);
-    CHECKED_WRITE_BUFF(CHUNK_MSH2_PERI, Pico32xMem->sh2_peri_regs[0]);
+    CHECKED_WRITE_BUFF(CHUNK_MSH2_DATA, sh2s[0].data_array);
+    CHECKED_WRITE_BUFF(CHUNK_MSH2_PERI, sh2s[0].peri_regs);
 
     sh2_pack(&sh2s[1], cpubuff);
     CHECKED_WRITE_BUFF(CHUNK_SSH2,      cpubuff);
-    CHECKED_WRITE_BUFF(CHUNK_SSH2_DATA, Pico32xMem->data_array[1]);
-    CHECKED_WRITE_BUFF(CHUNK_SSH2_PERI, Pico32xMem->sh2_peri_regs[1]);
+    CHECKED_WRITE_BUFF(CHUNK_SSH2_DATA, sh2s[1].data_array);
+    CHECKED_WRITE_BUFF(CHUNK_SSH2_PERI, sh2s[1].peri_regs);
 
     CHECKED_WRITE_BUFF(CHUNK_32XSYS,    Pico32x);
     CHECKED_WRITE_BUFF(CHUNK_M68K_BIOS, Pico32xMem->m68k_rom);
@@ -470,10 +470,10 @@ static int state_load(void *file)
         sh2_unpack(&sh2s[1], buff_sh2);
         break;
 
-      case CHUNK_MSH2_DATA:   CHECKED_READ_BUFF(Pico32xMem->data_array[0]); break;
-      case CHUNK_MSH2_PERI:   CHECKED_READ_BUFF(Pico32xMem->sh2_peri_regs[0]); break;
-      case CHUNK_SSH2_DATA:   CHECKED_READ_BUFF(Pico32xMem->data_array[1]); break;
-      case CHUNK_SSH2_PERI:   CHECKED_READ_BUFF(Pico32xMem->sh2_peri_regs[1]); break;
+      case CHUNK_MSH2_DATA:   CHECKED_READ_BUFF(sh2s[0].data_array); break;
+      case CHUNK_MSH2_PERI:   CHECKED_READ_BUFF(sh2s[0].peri_regs); break;
+      case CHUNK_SSH2_DATA:   CHECKED_READ_BUFF(sh2s[1].data_array); break;
+      case CHUNK_SSH2_PERI:   CHECKED_READ_BUFF(sh2s[1].peri_regs); break;
       case CHUNK_32XSYS:      CHECKED_READ_BUFF(Pico32x); break;
       case CHUNK_M68K_BIOS:   CHECKED_READ_BUFF(Pico32xMem->m68k_rom); break;
       case CHUNK_MSH2_BIOS:   CHECKED_READ_BUFF(Pico32xMem->sh2_rom_m); break;
-- 
2.39.5