From 2823a4c8196a02da86ee180cf55586d4e8c91a2f Mon Sep 17 00:00:00 2001 From: notaz Date: Thu, 21 May 2009 18:48:31 +0300 Subject: [PATCH 1/1] original source from gpsp09-2xb_src.tar.bz2 --- COPYING.DOC | 340 + build.txt | 11 + cheats.c | 388 + cheats.h | 44 + common.h | 276 + cpu.c | 4479 +++ cpu.h | 210 + cpu_threaded.c | 3508 ++ disasm.c | 184 + font.h | 5878 +++ game_config.txt | 932 + gp2x/Makefile | 51 + gp2x/align_test.c | 48 + gp2x/arm_codegen.h | 1392 + gp2x/arm_dpimacros.h | 1661 + gp2x/arm_emit.h | 1952 + gp2x/arm_stub.S | 1016 + gp2x/bios_cache.S | 478 + gp2x/cmdline.c | 256 + gp2x/cmdline.h | 3 + gp2x/cpu_speed.c | 1276 + gp2x/cpuctrl.c | 484 + gp2x/cpuctrl.h | 72 + gp2x/daemon.c | 671 + gp2x/daemon.h | 18 + gp2x/display.c | 139 + gp2x/display.h | 5 + gp2x/font.c | 143 + gp2x/gp2x.c | 93 + gp2x/gp2x.h | 50 + gp2x/gp2xminilib.c | 242 + gp2x/gp2xminilib.h | 58 + gp2x/load_imm_test.c | 135 + gp2x/readme_gp2x.txt | 262 + gp2x/rom_cache.S | 37007 +++++++++++++++++++ gp2x/speedtest.c | 205 + gp2x/speedtest.h | 3 + gp2x/video.S | 78790 +++++++++++++++++++++++++++++++++++++++++ gp2x/video_blend.S | 181 + gui.c | 1605 + gui.h | 40 + input.c | 899 + input.h | 92 + main.c | 1053 + main.h | 202 + memory.c | 3271 ++ memory.h | 219 + psp/Makefile | 26 + psp/mips_emit.h | 2531 ++ psp/mips_stub.S | 3427 ++ readme.txt | 880 + sound.c | 812 + sound.h | 328 + video.c | 3937 ++ video.h | 94 + x86/Makefile | 38 + x86/x86_emit.h | 2327 ++ x86/x86_stub.S | 501 + zip.c | 155 + zip.h | 26 + 60 files changed, 165404 insertions(+) create mode 100644 COPYING.DOC create mode 100644 build.txt create mode 100644 cheats.c create mode 100644 cheats.h create mode 100644 common.h create mode 100644 cpu.c create mode 100644 cpu.h create mode 100644 cpu_threaded.c create mode 100644 disasm.c create mode 100644 font.h create mode 100644 game_config.txt create mode 100644 gp2x/Makefile create mode 100644 gp2x/align_test.c create mode 100644 gp2x/arm_codegen.h create mode 100644 gp2x/arm_dpimacros.h create mode 100644 gp2x/arm_emit.h create mode 100644 gp2x/arm_stub.S create mode 100644 gp2x/bios_cache.S create mode 100644 gp2x/cmdline.c create mode 100644 gp2x/cmdline.h create mode 100644 gp2x/cpu_speed.c create mode 100644 gp2x/cpuctrl.c create mode 100644 gp2x/cpuctrl.h create mode 100644 gp2x/daemon.c create mode 100644 gp2x/daemon.h create mode 100644 gp2x/display.c create mode 100644 gp2x/display.h create mode 100644 gp2x/font.c create mode 100644 gp2x/gp2x.c create mode 100644 gp2x/gp2x.h create mode 100644 gp2x/gp2xminilib.c create mode 100644 gp2x/gp2xminilib.h create mode 100644 gp2x/load_imm_test.c create mode 100644 gp2x/readme_gp2x.txt create mode 100644 gp2x/rom_cache.S create mode 100644 gp2x/speedtest.c create mode 100644 gp2x/speedtest.h create mode 100644 gp2x/video.S create mode 100644 gp2x/video_blend.S create mode 100644 gui.c create mode 100644 gui.h create mode 100644 input.c create mode 100644 input.h create mode 100644 main.c create mode 100644 main.h create mode 100644 memory.c create mode 100644 memory.h create mode 100644 psp/Makefile create mode 100644 psp/mips_emit.h create mode 100644 psp/mips_stub.S create mode 100644 readme.txt create mode 100644 sound.c create mode 100644 sound.h create mode 100644 video.c create mode 100644 video.h create mode 100644 x86/Makefile create mode 100644 x86/x86_emit.h create mode 100644 x86/x86_stub.S create mode 100644 zip.c create mode 100644 zip.h diff --git a/COPYING.DOC b/COPYING.DOC new file mode 100644 index 0000000..f90922e --- /dev/null +++ b/COPYING.DOC @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/build.txt b/build.txt new file mode 100644 index 0000000..0d61216 --- /dev/null +++ b/build.txt @@ -0,0 +1,11 @@ +How to build gpSP for PSP: + +The makefile is in the psp directory, simply go there and type make. +make kxploit will build for 1.5 firmware. Be sure to include +game_config.txt and gpsp.cfg in the same directory as EBOOT.PBP, as +well as gba_bios.bin (not included). + +Dependencies as of v0.6: + + SDL + zlib diff --git a/cheats.c b/cheats.c new file mode 100644 index 0000000..7040b2f --- /dev/null +++ b/cheats.c @@ -0,0 +1,388 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "common.h" + +cheat_type cheats[MAX_CHEATS]; +u32 num_cheats; + +void decrypt_gsa_code(u32 *address_ptr, u32 *value_ptr, cheat_variant_enum + cheat_variant) +{ + u32 i, i2, code_position; + u32 address = *address_ptr; + u32 value = *value_ptr; + u32 r = 0xc6ef3720; + + u32 seeds_v1[4] = + { + 0x09f4fbbd, 0x9681884a, 0x352027e9, 0xf3dee5a7 + }; + u32 seeds_v3[4] = + { + 0x7aa9648f, 0x7fae6994, 0xc0efaad5, 0x42712c57 + }; + u32 *seeds; + + if(cheat_variant == CHEAT_TYPE_GAMESHARK_V1) + seeds = seeds_v1; + else + seeds = seeds_v3; + + for(i = 0; i < 32; i++) + { + value -= ((address << 4) + seeds[2]) ^ (address + r) ^ + ((address >> 5) + seeds[3]); + address -= ((value << 4) + seeds[0]) ^ (value + r) ^ + ((value >> 5) + seeds[1]); + r -= 0x9e3779b9; + } + + *address_ptr = address; + *value_ptr = value; +} + +void add_cheats(u8 *cheats_filename) +{ + FILE *cheats_file; + u8 current_line[256]; + u8 *name_ptr; + u32 *cheat_code_ptr; + u32 address, value; + u32 num_cheat_lines; + u32 cheat_name_length; + cheat_variant_enum current_cheat_variant; + + num_cheats = 0; + + cheats_file = fopen(cheats_filename, "rb"); + + if(cheats_file) + { + while(fgets(current_line, 256, cheats_file)) + { + // Get the header line first + name_ptr = strchr(current_line, ' '); + if(name_ptr) + { + *name_ptr = 0; + name_ptr++; + } + + if(!strcasecmp(current_line, "gameshark_v1") || + !strcasecmp(current_line, "gameshark_v2") || + !strcasecmp(current_line, "PAR_v1") || + !strcasecmp(current_line, "PAR_v2")) + { + current_cheat_variant = CHEAT_TYPE_GAMESHARK_V1; + } + else + + if(!strcasecmp(current_line, "gameshark_v3") || + !strcasecmp(current_line, "PAR_v3")) + { + current_cheat_variant = CHEAT_TYPE_GAMESHARK_V3; + } + else + { + current_cheat_variant = CHEAT_TYPE_INVALID; + } + + if(current_cheat_variant != CHEAT_TYPE_INVALID) + { + strncpy(cheats[num_cheats].cheat_name, name_ptr, CHEAT_NAME_LENGTH - 1); + cheats[num_cheats].cheat_name[CHEAT_NAME_LENGTH - 1] = 0; + cheat_name_length = strlen(cheats[num_cheats].cheat_name); + if(cheat_name_length && + (cheats[num_cheats].cheat_name[cheat_name_length - 1] == '\n') || + (cheats[num_cheats].cheat_name[cheat_name_length - 1] == '\r')) + { + cheats[num_cheats].cheat_name[cheat_name_length - 1] = 0; + cheat_name_length--; + } + + if(cheat_name_length && + cheats[num_cheats].cheat_name[cheat_name_length - 1] == '\r') + { + cheats[num_cheats].cheat_name[cheat_name_length - 1] = 0; + } + + cheats[num_cheats].cheat_variant = current_cheat_variant; + cheat_code_ptr = cheats[num_cheats].cheat_codes; + num_cheat_lines = 0; + + while(fgets(current_line, 256, cheats_file)) + { + if(strlen(current_line) < 3) + break; + + sscanf(current_line, "%08x %08x", &address, &value); + + decrypt_gsa_code(&address, &value, current_cheat_variant); + + cheat_code_ptr[0] = address; + cheat_code_ptr[1] = value; + + cheat_code_ptr += 2; + num_cheat_lines++; + } + + cheats[num_cheats].num_cheat_lines = num_cheat_lines; + + num_cheats++; + } + } + + fclose(cheats_file); + } +} + +void process_cheat_gs1(cheat_type *cheat) +{ + u32 cheat_opcode; + u32 *code_ptr = cheat->cheat_codes; + u32 address, value; + u32 i; + + for(i = 0; i < cheat->num_cheat_lines; i++) + { + address = code_ptr[0]; + value = code_ptr[1]; + + code_ptr += 2; + + cheat_opcode = address >> 28; + address &= 0xFFFFFFF; + + switch(cheat_opcode) + { + case 0x0: + write_memory8(address, value); + break; + + case 0x1: + write_memory16(address, value); + break; + + case 0x2: + write_memory32(address, value); + break; + + case 0x3: + { + u32 num_addresses = address & 0xFFFF; + u32 address1, address2; + u32 i2; + + for(i2 = 0; i2 < num_addresses; i2++) + { + address1 = code_ptr[0]; + address2 = code_ptr[1]; + code_ptr += 2; + i++; + + write_memory32(address1, value); + if(address2 != 0) + write_memory32(address2, value); + } + break; + } + + // ROM patch not supported yet + case 0x6: + break; + + // GS button down not supported yet + case 0x8: + break; + + // Reencryption (DEADFACE) not supported yet + case 0xD: + if(read_memory16(address) != (value & 0xFFFF)) + { + code_ptr += 2; + i++; + } + break; + + case 0xE: + if(read_memory16(value & 0xFFFFFFF) != (address & 0xFFFF)) + { + u32 skip = ((address >> 16) & 0x03); + code_ptr += skip * 2; + i += skip; + } + break; + + // Hook routine not supported yet (not important??) + case 0x0F: + break; + } + } +} + +// These are especially incomplete. + +void process_cheat_gs3(cheat_type *cheat) +{ + u32 cheat_opcode; + u32 *code_ptr = cheat->cheat_codes; + u32 address, value; + u32 i; + + for(i = 0; i < cheat->num_cheat_lines; i++) + { + address = code_ptr[0]; + value = code_ptr[1]; + + code_ptr += 2; + + cheat_opcode = address >> 28; + address &= 0xFFFFFFF; + + switch(cheat_opcode) + { + case 0x0: + cheat_opcode = address >> 24; + address = (address & 0xFFFFF) + ((address << 4) & 0xF000000); + + switch(cheat_opcode) + { + case 0x0: + { + u32 iterations = value >> 24; + u32 i2; + + value &= 0xFF; + + for(i2 = 0; i2 <= iterations; i2++, address++) + { + write_memory8(address, value); + } + break; + } + + case 0x2: + { + u32 iterations = value >> 16; + u32 i2; + + value &= 0xFFFF; + + for(i2 = 0; i2 <= iterations; i2++, address += 2) + { + write_memory16(address, value); + } + break; + } + + case 0x4: + write_memory32(address, value); + break; + } + break; + + case 0x4: + cheat_opcode = address >> 24; + address = (address & 0xFFFFF) + ((address << 4) & 0xF000000); + + switch(cheat_opcode) + { + case 0x0: + address = read_memory32(address) + (value >> 24); + write_memory8(address, value & 0xFF); + break; + + case 0x2: + address = read_memory32(address) + ((value >> 16) * 2); + write_memory16(address, value & 0xFFFF); + break; + + case 0x4: + address = read_memory32(address); + write_memory32(address, value); + break; + + } + break; + + case 0x8: + cheat_opcode = address >> 24; + address = (address & 0xFFFFF) + ((address << 4) & 0xF000000); + + switch(cheat_opcode) + { + case 0x0: + value = (value & 0xFF) + read_memory8(address); + write_memory8(address, value); + break; + + case 0x2: + value = (value & 0xFFFF) + read_memory16(address); + write_memory16(address, value); + break; + + case 0x4: + value = value + read_memory32(address); + write_memory32(address, value); + break; + } + break; + + case 0xC: + cheat_opcode = address >> 24; + address = (address & 0xFFFFFF) + 0x4000000; + + switch(cheat_opcode) + { + case 0x6: + write_memory16(address, value); + break; + + case 0x7: + write_memory32(address, value); + break; + } + break; + } + } +} + + +void process_cheats() +{ + u32 i; + + for(i = 0; i < num_cheats; i++) + { + if(cheats[i].cheat_active) + { + switch(cheats[i].cheat_variant) + { + case CHEAT_TYPE_GAMESHARK_V1: + process_cheat_gs1(cheats + i); + break; + + case CHEAT_TYPE_GAMESHARK_V3: + process_cheat_gs3(cheats + i); + break; + } + } + } +} diff --git a/cheats.h b/cheats.h new file mode 100644 index 0000000..65b46ae --- /dev/null +++ b/cheats.h @@ -0,0 +1,44 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define CHEAT_NAME_LENGTH 17 + +typedef enum +{ + CHEAT_TYPE_GAMESHARK_V1, + CHEAT_TYPE_GAMESHARK_V3, + CHEAT_TYPE_INVALID +} cheat_variant_enum; + +typedef struct +{ + u8 cheat_name[CHEAT_NAME_LENGTH]; + u32 cheat_active; + u32 cheat_codes[256]; + u32 num_cheat_lines; + cheat_variant_enum cheat_variant; +} cheat_type; + +void process_cheats(); +void add_cheats(u8 *cheats_filename); + +#define MAX_CHEATS 16 + +extern cheat_type cheats[MAX_CHEATS]; +extern u32 num_cheats; diff --git a/common.h b/common.h new file mode 100644 index 0000000..f111348 --- /dev/null +++ b/common.h @@ -0,0 +1,276 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef COMMON_H +#define COMMON_H + +#define ror(dest, value, shift) \ + dest = ((value) >> shift) | ((value) << (32 - shift)) \ + +// These includes must be used before SDL is included. +#ifdef ARM_ARCH + +#ifdef _WIN32_WCE + #include +#else + #include + #include + #include + #include + #include + #include + #include + #include + #include +#endif /* _WIN32_WCE */ + +#ifdef GIZ_BUILD + #include "giz/giz.h" +#endif +#endif /* ARM_ARCH */ + +// Huge thanks to pollux for the heads up on using native file I/O +// functions on PSP for vastly improved memstick performance. + +#define file_write_mem(filename_tag, buffer, size) \ +{ \ + memcpy(write_mem_ptr, buffer, size); \ + write_mem_ptr += size; \ +} \ + +#define file_write_mem_array(filename_tag, array) \ + file_write_mem(filename_tag, array, sizeof(array)) \ + +#define file_write_mem_variable(filename_tag, variable) \ + file_write_mem(filename_tag, &variable, sizeof(variable)) \ + +#ifdef PSP_BUILD + #define fastcall + + #include + #include + #include + #include + #include + #include + #include + + #define function_cc + + #define convert_palette(value) \ + value = ((value & 0x7FE0) << 1) | (value & 0x1F) \ + + #define psp_file_open_read PSP_O_RDONLY + #define psp_file_open_write (PSP_O_CREAT | PSP_O_WRONLY | PSP_O_TRUNC) + + #define file_open(filename_tag, filename, mode) \ + s32 filename_tag = sceIoOpen(filename, psp_file_open_##mode, 0777) \ + + #define file_check_valid(filename_tag) \ + (filename_tag >= 0) \ + + #define file_close(filename_tag) \ + sceIoClose(filename_tag) \ + + #define file_read(filename_tag, buffer, size) \ + sceIoRead(filename_tag, buffer, size) \ + + #define file_write(filename_tag, buffer, size) \ + sceIoWrite(filename_tag, buffer, size) \ + + #define file_seek(filename_tag, offset, type) \ + sceIoLseek(filename_tag, offset, PSP_##type) \ + + #define file_tag_type s32 + + #include + #include +#else + #include "SDL.h" + +#ifdef ARM_ARCH + #define function_cc +#else + #define function_cc __attribute__((regparm(2))) +#endif + + typedef unsigned char u8; + typedef signed char s8; + typedef unsigned short int u16; + typedef signed short int s16; + typedef unsigned long u32; + typedef signed long s32; + typedef unsigned long long int u64; + typedef signed long long int s64; + + #define convert_palette(value) \ + value = ((value & 0x1F) << 11) | ((value & 0x03E0) << 1) | (value >> 10) \ + + #define stdio_file_open_read "rb" + #define stdio_file_open_write "wb" + + #define file_open(filename_tag, filename, mode) \ + FILE *filename_tag = fopen(filename, stdio_file_open_##mode) \ + + #define file_check_valid(filename_tag) \ + (filename_tag) \ + +#ifdef GP2X_BUILD + + #define file_close(filename_tag) \ + { \ + sync(); \ + fclose(filename_tag); \ + } \ + +#else + + #define file_close(filename_tag) \ + fclose(filename_tag) \ + +#endif + + #define file_read(filename_tag, buffer, size) \ + fread(buffer, size, 1, filename_tag) \ + + #define file_write(filename_tag, buffer, size) \ + fwrite(buffer, size, 1, filename_tag) \ + + #define file_seek(filename_tag, offset, type) \ + fseek(filename_tag, offset, type) \ + + #define file_tag_type FILE * + + // The ARM arch uses SDL, and SDL requires you to know what resolution + // you want. Define the resolution for ARM arch builds here. + // Placed in common.h for use with video.c and gui.c. + + #ifndef PC_BUILD + + #define GP2X_SCREEN_WIDTH 320 + #define GP2X_SCREEN_HEIGHT 240 + + #define GIZ_SCREEN_WIDTH 320 + #define GIZ_SCREEN_HEIGHT 240 + + #ifdef GP2X_BUILD + #define SDL_SCREEN_WIDTH GP2X_SCREEN_WIDTH + #define SDL_SCREEN_HEIGHT GP2X_SCREEN_HEIGHT + + #elif defined(GIZ_BUILD) + + #define SDL_SCREEN_WIDTH GIZ_SCREEN_WIDTH + #define SDL_SCREEN_HEIGHT GIZ_SCREEN_HEIGHT + #endif + + #endif + +#endif + +// These must be variables, not constants. + +#define file_read_variable(filename_tag, variable) \ + file_read(filename_tag, &variable, sizeof(variable)) \ + +#define file_write_variable(filename_tag, variable) \ + file_write(filename_tag, &variable, sizeof(variable)) \ + +// These must be statically declared arrays (ie, global or on the stack, +// not dynamically allocated on the heap) + +#define file_read_array(filename_tag, array) \ + file_read(filename_tag, array, sizeof(array)) \ + +#define file_write_array(filename_tag, array) \ + file_write(filename_tag, array, sizeof(array)) \ + + + +typedef u32 fixed16_16; + +#define float_to_fp16_16(value) \ + (fixed16_16)((value) * 65536.0) \ + +#define fp16_16_to_float(value) \ + (float)((value) / 65536.0) \ + +#define u32_to_fp16_16(value) \ + ((value) << 16) \ + +#define fp16_16_to_u32(value) \ + ((value) >> 16) \ + +#define fp16_16_fractional_part(value) \ + ((value) & 0xFFFF) \ + +#define fixed_div(numerator, denominator, bits) \ + (((numerator * (1 << bits)) + (denominator / 2)) / denominator) \ + +#define address8(base, offset) \ + *((u8 *)((u8 *)base + (offset))) \ + +#define address16(base, offset) \ + *((u16 *)((u8 *)base + (offset))) \ + +#define address32(base, offset) \ + *((u32 *)((u8 *)base + (offset))) \ + +#include +#include +#include +#include +#include +#include +#include "SDL.h" +#include "cpu.h" +#include "memory.h" +#include "video.h" +#include "input.h" +#include "sound.h" +#include "main.h" +#include "gui.h" +#include "zip.h" +#include "cheats.h" + + +#ifdef PSP_BUILD + #define printf pspDebugScreenPrintf +#endif + +#ifdef PC_BUILD + #define STDIO_DEBUG + //#define REGISTER_USAGE_ANALYZE +#endif + +#ifdef GP2X_BUILD + #include + #include "gp2x/gp2x.h" + + #define printf(format, ...) \ + fprintf(stderr, format, ##__VA_ARGS__) \ + + #define vprintf(format, ap) \ + vfprintf(stderr, format, ap) \ + + void gp2x_overclock(void); + +// #define STDIO_DEBUG +#endif + +#endif diff --git a/cpu.c b/cpu.c new file mode 100644 index 0000000..63a9c6c --- /dev/null +++ b/cpu.c @@ -0,0 +1,4479 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Important todo: +// - stm reglist writeback when base is in the list needs adjustment +// - block memory needs psr swapping and user mode reg swapping + +#include +#include "common.h" + +u32 memory_region_access_read_u8[16]; +u32 memory_region_access_read_s8[16]; +u32 memory_region_access_read_u16[16]; +u32 memory_region_access_read_s16[16]; +u32 memory_region_access_read_u32[16]; +u32 memory_region_access_write_u8[16]; +u32 memory_region_access_write_u16[16]; +u32 memory_region_access_write_u32[16]; +u32 memory_reads_u8; +u32 memory_reads_s8; +u32 memory_reads_u16; +u32 memory_reads_s16; +u32 memory_reads_u32; +u32 memory_writes_u8; +u32 memory_writes_u16; +u32 memory_writes_u32; + +const u8 bit_count[256] = +{ + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, + 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, + 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, + 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, + 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, + 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, + 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, + 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, + 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, + 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, + 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, + 7, 7, 8 +}; + + +#ifdef REGISTER_USAGE_ANALYZE + +u64 instructions_total = 0; + +u64 arm_reg_freq[16]; +u64 arm_reg_access_total = 0; +u64 arm_instructions_total = 0; + +u64 thumb_reg_freq[16]; +u64 thumb_reg_access_total = 0; +u64 thumb_instructions_total = 0; + +// mla/long mla's addition operand are not counted yet. + +#define using_register(instruction_set, register, type) \ + instruction_set##_reg_freq[register]++; \ + instruction_set##_reg_access_total++ \ + +#define using_register_list(instruction_set, rlist, count) \ +{ \ + u32 i; \ + for(i = 0; i < count; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + using_register(instruction_set, i, memory_target); \ + } \ + } \ +} \ + +#define using_instruction(instruction_set) \ + instruction_set##_instructions_total++; \ + instructions_total++ \ + +int sort_tagged_element(const void *_a, const void *_b) +{ + const u64 *a = _a; + const u64 *b = _b; + + return (int)(b[1] - a[1]); +} + +void print_register_usage() +{ + u32 i; + u64 arm_reg_freq_tagged[32]; + u64 thumb_reg_freq_tagged[32]; + double percent; + double percent_total = 0.0; + + for(i = 0; i < 16; i++) + { + arm_reg_freq_tagged[i * 2] = i; + arm_reg_freq_tagged[(i * 2) + 1] = arm_reg_freq[i]; + thumb_reg_freq_tagged[i * 2] = i; + thumb_reg_freq_tagged[(i * 2) + 1] = thumb_reg_freq[i]; + } + + qsort(arm_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element); + qsort(thumb_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element); + + printf("ARM register usage (%lf%% ARM instructions):\n", + (arm_instructions_total * 100.0) / instructions_total); + for(i = 0; i < 16; i++) + { + percent = (arm_reg_freq_tagged[(i * 2) + 1] * 100.0) / + arm_reg_access_total; + percent_total += percent; + printf("r%02d: %lf%% (-- %lf%%)\n", + (u32)arm_reg_freq_tagged[(i * 2)], percent, percent_total); + } + + percent_total = 0.0; + + printf("\nThumb register usage (%lf%% Thumb instructions):\n", + (thumb_instructions_total * 100.0) / instructions_total); + for(i = 0; i < 16; i++) + { + percent = (thumb_reg_freq_tagged[(i * 2) + 1] * 100.0) / + thumb_reg_access_total; + percent_total += percent; + printf("r%02d: %lf%% (-- %lf%%)\n", + (u32)thumb_reg_freq_tagged[(i * 2)], percent, percent_total); + } + + memset(arm_reg_freq, 0, sizeof(u64) * 16); + memset(thumb_reg_freq, 0, sizeof(u64) * 16); + arm_reg_access_total = 0; + thumb_reg_access_total = 0; +} + +#else + +#define using_register(instruction_set, register, type) \ + +#define using_register_list(instruction_set, rlist, count) \ + +#define using_instruction(instruction_set) \ + +#endif + + +#define arm_decode_data_proc_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, op_dest); \ + using_register(arm, rn, op_src); \ + using_register(arm, rm, op_src) \ + +#define arm_decode_data_proc_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm; \ + ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \ + using_register(arm, rd, op_dest); \ + using_register(arm, rn, op_src) \ + +#define arm_decode_psr_reg() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, op_dest); \ + using_register(arm, rm, op_src) \ + +#define arm_decode_psr_imm() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm; \ + ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \ + using_register(arm, rd, op_dest) \ + +#define arm_decode_branchx() \ + u32 rn = opcode & 0x0F; \ + using_register(arm, rn, branch_target) \ + +#define arm_decode_multiply() \ + u32 rd = (opcode >> 16) & 0x0F; \ + u32 rn = (opcode >> 12) & 0x0F; \ + u32 rs = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, op_dest); \ + using_register(arm, rn, op_src); \ + using_register(arm, rm, op_src) \ + +#define arm_decode_multiply_long() \ + u32 rdhi = (opcode >> 16) & 0x0F; \ + u32 rdlo = (opcode >> 12) & 0x0F; \ + u32 rn = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rdhi, op_dest); \ + using_register(arm, rdlo, op_dest); \ + using_register(arm, rn, op_src); \ + using_register(arm, rm, op_src) \ + +#define arm_decode_swap() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, memory_target); \ + using_register(arm, rn, memory_base); \ + using_register(arm, rm, memory_target) \ + +#define arm_decode_half_trans_r() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, memory_target); \ + using_register(arm, rn, memory_base); \ + using_register(arm, rm, memory_offset) \ + +#define arm_decode_half_trans_of() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F); \ + using_register(arm, rd, memory_target); \ + using_register(arm, rn, memory_base) \ + +#define arm_decode_data_trans_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = opcode & 0x0FFF; \ + using_register(arm, rd, memory_target); \ + using_register(arm, rn, memory_base) \ + +#define arm_decode_data_trans_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F; \ + using_register(arm, rd, memory_target); \ + using_register(arm, rn, memory_base); \ + using_register(arm, rm, memory_offset) \ + +#define arm_decode_block_trans() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 reg_list = opcode & 0xFFFF; \ + using_register(arm, rn, memory_base); \ + using_register_list(arm, reg_list, 16) \ + +#define arm_decode_branch() \ + s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \ + + +#define thumb_decode_shift() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, op_dest); \ + using_register(thumb, rs, op_shift) \ + +#define thumb_decode_add_sub() \ + u32 rn = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, op_dest); \ + using_register(thumb, rn, op_src); \ + using_register(thumb, rn, op_src) \ + +#define thumb_decode_add_sub_imm() \ + u32 imm = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, op_src_dest); \ + using_register(thumb, rs, op_src) \ + +#define thumb_decode_imm() \ + u32 imm = opcode & 0xFF; \ + using_register(thumb, ((opcode >> 8) & 0x07), op_dest) \ + +#define thumb_decode_alu_op() \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, op_src_dest); \ + using_register(thumb, rs, op_src) \ + +#define thumb_decode_hireg_op() \ + u32 rs = (opcode >> 3) & 0x0F; \ + u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07); \ + using_register(thumb, rd, op_src_dest); \ + using_register(thumb, rs, op_src) \ + + +#define thumb_decode_mem_reg() \ + u32 ro = (opcode >> 6) & 0x07; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, memory_target); \ + using_register(thumb, rb, memory_base); \ + using_register(thumb, ro, memory_offset) \ + + +#define thumb_decode_mem_imm() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07; \ + using_register(thumb, rd, memory_target); \ + using_register(thumb, rb, memory_base) \ + + +#define thumb_decode_add_sp() \ + u32 imm = opcode & 0x7F; \ + using_register(thumb, REG_SP, op_dest) \ + +#define thumb_decode_rlist() \ + u32 reg_list = opcode & 0xFF; \ + using_register_list(thumb, rlist, 8) \ + +#define thumb_decode_branch_cond() \ + s32 offset = (s8)(opcode & 0xFF) \ + +#define thumb_decode_swi() \ + u32 comment = opcode & 0xFF \ + +#define thumb_decode_branch() \ + u32 offset = opcode & 0x07FF \ + + +#define get_shift_register(dest) \ + u32 shift = reg[(opcode >> 8) & 0x0F]; \ + using_register(arm, ((opcode >> 8) & 0x0F), op_shift); \ + dest = reg[rm]; \ + if(rm == 15) \ + dest += 4 \ + + +#define calculate_z_flag(dest) \ + z_flag = (dest == 0) \ + +#define calculate_n_flag(dest) \ + n_flag = ((signed)dest < 0) \ + +#define calculate_c_flag_sub(dest, src_a, src_b) \ + c_flag = ((unsigned)src_b <= (unsigned)src_a) \ + +#define calculate_v_flag_sub(dest, src_a, src_b) \ + v_flag = ((signed)src_b > (signed)src_a) != ((signed)dest < 0) \ + +#define calculate_c_flag_add(dest, src_a, src_b) \ + c_flag = ((unsigned)dest < (unsigned)src_a) \ + +#define calculate_v_flag_add(dest, src_a, src_b) \ + v_flag = ((signed)dest < (signed)src_a) != ((signed)src_b < 0) \ + + +#define calculate_reg_sh() \ + u32 reg_sh; \ + switch((opcode >> 4) & 0x07) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + reg_sh = reg[rm] << ((opcode >> 7) & 0x1F); \ + break; \ + } \ + \ + /* LSL reg */ \ + case 0x1: \ + { \ + get_shift_register(reg_sh); \ + if(shift <= 31) \ + reg_sh = reg_sh << shift; \ + else \ + reg_sh = 0; \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x2: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + if(imm == 0) \ + reg_sh = 0; \ + else \ + reg_sh = reg[rm] >> imm; \ + break; \ + } \ + \ + /* LSR reg */ \ + case 0x3: \ + { \ + get_shift_register(reg_sh); \ + if(shift <= 31) \ + reg_sh = reg_sh >> shift; \ + else \ + reg_sh = 0; \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x4: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + reg_sh = reg[rm]; \ + \ + if(imm == 0) \ + reg_sh = (s32)reg_sh >> 31; \ + else \ + reg_sh = (s32)reg_sh >> imm; \ + break; \ + } \ + \ + /* ASR reg */ \ + case 0x5: \ + { \ + get_shift_register(reg_sh); \ + if(shift <= 31) \ + reg_sh = (s32)reg_sh >> shift; \ + else \ + reg_sh = (s32)reg_sh >> 31; \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x6: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + \ + if(imm == 0) \ + reg_sh = (reg[rm] >> 1) | (c_flag << 31); \ + else \ + ror(reg_sh, reg[rm], imm); \ + break; \ + } \ + \ + /* ROR reg */ \ + case 0x7: \ + { \ + get_shift_register(reg_sh); \ + ror(reg_sh, reg_sh, shift); \ + break; \ + } \ + } \ + +#define calculate_reg_sh_flags() \ + u32 reg_sh; \ + switch((opcode >> 4) & 0x07) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + reg_sh = reg[rm]; \ + \ + if(imm != 0) \ + { \ + c_flag = (reg_sh >> (32 - imm)) & 0x01; \ + reg_sh <<= imm; \ + } \ + \ + break; \ + } \ + \ + /* LSL reg */ \ + case 0x1: \ + { \ + get_shift_register(reg_sh); \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + if(shift == 32) \ + c_flag = reg_sh & 0x01; \ + else \ + c_flag = 0; \ + reg_sh = 0; \ + } \ + else \ + { \ + c_flag = (reg_sh >> (32 - shift)) & 0x01; \ + reg_sh <<= shift; \ + } \ + } \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x2: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + reg_sh = reg[rm]; \ + if(imm == 0) \ + { \ + c_flag = reg_sh >> 31; \ + reg_sh = 0; \ + } \ + else \ + { \ + c_flag = (reg_sh >> (imm - 1)) & 0x01; \ + reg_sh >>= imm; \ + } \ + break; \ + } \ + \ + /* LSR reg */ \ + case 0x3: \ + { \ + get_shift_register(reg_sh); \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + if(shift == 32) \ + c_flag = (reg_sh >> 31) & 0x01; \ + else \ + c_flag = 0; \ + reg_sh = 0; \ + } \ + else \ + { \ + c_flag = (reg_sh >> (shift - 1)) & 0x01; \ + reg_sh >>= shift; \ + } \ + } \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x4: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + reg_sh = reg[rm]; \ + if(imm == 0) \ + { \ + reg_sh = (s32)reg_sh >> 31; \ + c_flag = reg_sh & 0x01; \ + } \ + else \ + { \ + c_flag = (reg_sh >> (imm - 1)) & 0x01; \ + reg_sh = (s32)reg_sh >> imm; \ + } \ + break; \ + } \ + \ + /* ASR reg */ \ + case 0x5: \ + { \ + get_shift_register(reg_sh); \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + reg_sh = (s32)reg_sh >> 31; \ + c_flag = reg_sh & 0x01; \ + } \ + else \ + { \ + c_flag = (reg_sh >> (shift - 1)) & 0x01; \ + reg_sh = (s32)reg_sh >> shift; \ + } \ + } \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x6: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + reg_sh = reg[rm]; \ + if(imm == 0) \ + { \ + u32 old_c_flag = c_flag; \ + c_flag = reg_sh & 0x01; \ + reg_sh = (reg_sh >> 1) | (old_c_flag << 31); \ + } \ + else \ + { \ + c_flag = (reg_sh >> (imm - 1)) & 0x01; \ + ror(reg_sh, reg_sh, imm); \ + } \ + break; \ + } \ + \ + /* ROR reg */ \ + case 0x7: \ + { \ + get_shift_register(reg_sh); \ + if(shift != 0) \ + { \ + c_flag = (reg_sh >> (shift - 1)) & 0x01; \ + ror(reg_sh, reg_sh, shift); \ + } \ + break; \ + } \ + } \ + +#define calculate_reg_offset() \ + u32 reg_offset; \ + switch((opcode >> 5) & 0x03) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + reg_offset = reg[rm] << ((opcode >> 7) & 0x1F); \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x1: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + if(imm == 0) \ + reg_offset = 0; \ + else \ + reg_offset = reg[rm] >> imm; \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x2: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + if(imm == 0) \ + reg_offset = (s32)reg[rm] >> 31; \ + else \ + reg_offset = (s32)reg[rm] >> imm; \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x3: \ + { \ + u32 imm = (opcode >> 7) & 0x1F; \ + if(imm == 0) \ + reg_offset = (reg[rm] >> 1) | (c_flag << 31); \ + else \ + ror(reg_offset, reg[rm], imm); \ + break; \ + } \ + } \ + +#define calculate_flags_add(dest, src_a, src_b) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + calculate_c_flag_add(dest, src_a, src_b); \ + calculate_v_flag_add(dest, src_a, src_b) \ + +#define calculate_flags_sub(dest, src_a, src_b) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + calculate_c_flag_sub(dest, src_a, src_b); \ + calculate_v_flag_sub(dest, src_a, src_b) \ + +#define calculate_flags_logic(dest) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest) \ + +#define extract_flags() \ + n_flag = reg[REG_CPSR] >> 31; \ + z_flag = (reg[REG_CPSR] >> 30) & 0x01; \ + c_flag = (reg[REG_CPSR] >> 29) & 0x01; \ + v_flag = (reg[REG_CPSR] >> 28) & 0x01; \ + +#define collapse_flags() \ + reg[REG_CPSR] = (n_flag << 31) | (z_flag << 30) | (c_flag << 29) | \ + (v_flag << 28) | (reg[REG_CPSR] & 0xFF) \ + +#define memory_region(r_dest, l_dest, address) \ + r_dest = memory_regions[address >> 24]; \ + l_dest = memory_limits[address >> 24] \ + + +#define pc_region() \ + memory_region(pc_region, pc_limit, pc) \ + +#define check_pc_region() \ + new_pc_region = (pc >> 15); \ + if(new_pc_region != pc_region) \ + { \ + pc_region = new_pc_region; \ + pc_address_block = memory_map_read[new_pc_region]; \ + \ + if(pc_address_block == NULL) \ + pc_address_block = load_gamepak_page(pc_region & 0x3FF); \ + } \ + +u32 branch_targets = 0; +u32 high_frequency_branch_targets = 0; + +#define BRANCH_ACTIVITY_THRESHOLD 50 + +#define arm_update_pc() \ + pc = reg[REG_PC] \ + +#define arm_pc_offset(val) \ + pc += val; \ + reg[REG_PC] = pc \ + +#define arm_pc_offset_update(val) \ + pc += val; \ + reg[REG_PC] = pc \ + +#define arm_pc_offset_update_direct(val) \ + pc = val; \ + reg[REG_PC] = pc \ + + +// It should be okay to still generate result flags, spsr will overwrite them. +// This is pretty infrequent (returning from interrupt handlers, et al) so +// probably not worth optimizing for. + +#define check_for_interrupts() \ + if((io_registers[REG_IE] & io_registers[REG_IF]) && \ + io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \ + { \ + reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4; \ + spsr[MODE_IRQ] = reg[REG_CPSR]; \ + reg[REG_CPSR] = 0xD2; \ + reg[REG_PC] = 0x00000018; \ + arm_update_pc(); \ + set_cpu_mode(MODE_IRQ); \ + goto arm_loop; \ + } \ + +#define arm_spsr_restore() \ + if(rd == 15) \ + { \ + if(reg[CPU_MODE] != MODE_USER) \ + { \ + reg[REG_CPSR] = spsr[reg[CPU_MODE]]; \ + extract_flags(); \ + set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \ + check_for_interrupts(); \ + } \ + arm_update_pc(); \ + \ + if(reg[REG_CPSR] & 0x20) \ + goto thumb_loop; \ + } \ + +#define arm_data_proc_flags_reg() \ + arm_decode_data_proc_reg(); \ + calculate_reg_sh_flags() \ + +#define arm_data_proc_reg() \ + arm_decode_data_proc_reg(); \ + calculate_reg_sh() \ + +#define arm_data_proc_flags_imm() \ + arm_decode_data_proc_imm() \ + +#define arm_data_proc_imm() \ + arm_decode_data_proc_imm() \ + +#define arm_data_proc(expr, type) \ +{ \ + u32 dest; \ + arm_pc_offset(8); \ + arm_data_proc_##type(); \ + dest = expr; \ + arm_pc_offset(-4); \ + reg[rd] = dest; \ + \ + if(rd == 15) \ + { \ + arm_update_pc(); \ + } \ +} \ + +#define flags_vars(src_a, src_b) \ + u32 dest; \ + const u32 _sa = src_a; \ + const u32 _sb = src_b \ + +#define arm_data_proc_logic_flags(expr, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_flags_##type(); \ + u32 dest = expr; \ + calculate_flags_logic(dest); \ + arm_pc_offset(-4); \ + reg[rd] = dest; \ + arm_spsr_restore(); \ +} \ + +#define arm_data_proc_add_flags(src_a, src_b, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_##type(); \ + flags_vars(src_a, src_b); \ + dest = _sa + _sb; \ + calculate_flags_add(dest, _sa, _sb); \ + arm_pc_offset(-4); \ + reg[rd] = dest; \ + arm_spsr_restore(); \ +} + +#define arm_data_proc_sub_flags(src_a, src_b, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_##type(); \ + flags_vars(src_a, src_b); \ + dest = _sa - _sb; \ + calculate_flags_sub(dest, _sa, _sb); \ + arm_pc_offset(-4); \ + reg[rd] = dest; \ + arm_spsr_restore(); \ +} \ + +#define arm_data_proc_test_logic(expr, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_flags_##type(); \ + u32 dest = expr; \ + calculate_flags_logic(dest); \ + arm_pc_offset(-4); \ +} \ + +#define arm_data_proc_test_add(src_a, src_b, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_##type(); \ + flags_vars(src_a, src_b); \ + dest = _sa + _sb; \ + calculate_flags_add(dest, _sa, _sb); \ + arm_pc_offset(-4); \ +} \ + +#define arm_data_proc_test_sub(src_a, src_b, type) \ +{ \ + arm_pc_offset(8); \ + arm_data_proc_##type(); \ + flags_vars(src_a, src_b); \ + dest = _sa - _sb; \ + calculate_flags_sub(dest, _sa, _sb); \ + arm_pc_offset(-4); \ +} \ + +#define arm_multiply_flags_yes(_dest) \ + calculate_z_flag(_dest); \ + calculate_n_flag(_dest); \ + +#define arm_multiply_flags_no(_dest) \ + +#define arm_multiply_long_flags_yes(_dest_lo, _dest_hi) \ + z_flag = (_dest_lo == 0) & (_dest_hi == 0); \ + calculate_n_flag(_dest_hi) \ + +#define arm_multiply_long_flags_no(_dest_lo, _dest_hi) \ + +#define arm_multiply(add_op, flags) \ +{ \ + u32 dest; \ + arm_decode_multiply(); \ + dest = (reg[rm] * reg[rs]) add_op; \ + arm_multiply_flags_##flags(dest); \ + reg[rd] = dest; \ + arm_pc_offset(4); \ +} \ + +#define arm_multiply_long_addop(type) \ + + ((type##64)((((type##64)reg[rdhi]) << 32) | reg[rdlo])); \ + +#define arm_multiply_long(add_op, flags, type) \ +{ \ + type##64 dest; \ + u32 dest_lo; \ + u32 dest_hi; \ + arm_decode_multiply_long(); \ + dest = ((type##64)((type##32)reg[rm]) * \ + (type##64)((type##32)reg[rn])) add_op; \ + dest_lo = (u32)dest; \ + dest_hi = (u32)(dest >> 32); \ + arm_multiply_long_flags_##flags(dest_lo, dest_hi); \ + reg[rdlo] = dest_lo; \ + reg[rdhi] = dest_hi; \ + arm_pc_offset(4); \ +} \ + +const u32 psr_masks[16] = +{ + 0x00000000, 0x000000FF, 0x0000FF00, 0x0000FFFF, 0x00FF0000, + 0x00FF00FF, 0x00FFFF00, 0x00FFFFFF, 0xFF000000, 0xFF0000FF, + 0xFF00FF00, 0xFF00FFFF, 0xFFFF0000, 0xFFFF00FF, 0xFFFFFF00, + 0xFFFFFFFF +}; + +#define arm_psr_read(dummy, psr_reg) \ + collapse_flags(); \ + reg[rd] = psr_reg \ + +#define arm_psr_store_cpsr(source) \ + reg[REG_CPSR] = (source & store_mask) | (reg[REG_CPSR] & (~store_mask)); \ + extract_flags(); \ + if(store_mask & 0xFF) \ + { \ + set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \ + check_for_interrupts(); \ + } \ + +#define arm_psr_store_spsr(source) \ + u32 _psr = spsr[reg[CPU_MODE]]; \ + spsr[reg[CPU_MODE]] = (source & store_mask) | (_psr & (~store_mask)) \ + +#define arm_psr_store(source, psr_reg) \ + const u32 store_mask = psr_masks[psr_field]; \ + arm_psr_store_##psr_reg(source) \ + +#define arm_psr_src_reg reg[rm] + +#define arm_psr_src_imm imm + +#define arm_psr(op_type, transfer_type, psr_reg) \ +{ \ + arm_decode_psr_##op_type(); \ + arm_pc_offset(4); \ + arm_psr_##transfer_type(arm_psr_src_##op_type, psr_reg); \ +} \ + +#define arm_data_trans_reg() \ + arm_decode_data_trans_reg(); \ + calculate_reg_offset() \ + +#define arm_data_trans_imm() \ + arm_decode_data_trans_imm() \ + +#define arm_data_trans_half_reg() \ + arm_decode_half_trans_r() \ + +#define arm_data_trans_half_imm() \ + arm_decode_half_trans_of() \ + +#define aligned_address_mask8 0xF0000000 +#define aligned_address_mask16 0xF0000001 +#define aligned_address_mask32 0xF0000003 + +#define fast_read_memory(size, type, address, dest) \ +{ \ + u8 *map; \ + u32 _address = address; \ + \ + if(_address < 0x10000000) \ + { \ + memory_region_access_read_##type[_address >> 24]++; \ + memory_reads_##type++; \ + } \ + if(((_address >> 24) == 0) && (pc >= 0x4000)) \ + { \ + dest = *((type *)((u8 *)&bios_read_protect + (_address & 0x03))); \ + } \ + else \ + \ + if(((_address & aligned_address_mask##size) == 0) && \ + (map = memory_map_read[address >> 15])) \ + { \ + dest = *((type *)((u8 *)map + (_address & 0x7FFF))); \ + } \ + else \ + { \ + dest = (type)read_memory##size(_address); \ + } \ +} \ + +#define fast_read_memory_s16(address, dest) \ +{ \ + u8 *map; \ + u32 _address = address; \ + if(_address < 0x10000000) \ + { \ + memory_region_access_read_s16[_address >> 24]++; \ + memory_reads_s16++; \ + } \ + if(((_address & aligned_address_mask16) == 0) && \ + (map = memory_map_read[_address >> 15])) \ + { \ + dest = *((s16 *)((u8 *)map + (_address & 0x7FFF))); \ + } \ + else \ + { \ + dest = (s16)read_memory16_signed(_address); \ + } \ +} \ + + +#define fast_write_memory(size, type, address, value) \ +{ \ + u8 *map; \ + u32 _address = (address) & ~(aligned_address_mask##size & 0x03); \ + if(_address < 0x10000000) \ + { \ + memory_region_access_write_##type[_address >> 24]++; \ + memory_writes_##type++; \ + } \ + \ + if(((_address & aligned_address_mask##size) == 0) && \ + (map = memory_map_write[_address >> 15])) \ + { \ + *((type *)((u8 *)map + (_address & 0x7FFF))) = value; \ + } \ + else \ + { \ + cpu_alert = write_memory##size(_address, value); \ + if(cpu_alert) \ + goto alert; \ + } \ +} \ + +#define load_aligned32(address, dest) \ +{ \ + u8 *map = memory_map_read[address >> 15]; \ + if(address < 0x10000000) \ + { \ + memory_region_access_read_u32[address >> 24]++; \ + memory_reads_u32++; \ + } \ + if(map) \ + { \ + dest = address32(map, address & 0x7FFF); \ + } \ + else \ + { \ + dest = read_memory32(address); \ + } \ +} \ + +#define store_aligned32(address, value) \ +{ \ + u8 *map = memory_map_write[address >> 15]; \ + if(address < 0x10000000) \ + { \ + memory_region_access_write_u32[address >> 24]++; \ + memory_writes_u32++; \ + } \ + if(map) \ + { \ + address32(map, address & 0x7FFF) = value; \ + } \ + else \ + { \ + cpu_alert = write_memory32(address, value); \ + if(cpu_alert) \ + goto alert; \ + } \ +} \ + +#define load_memory_u8(address, dest) \ + fast_read_memory(8, u8, address, dest) \ + +#define load_memory_u16(address, dest) \ + fast_read_memory(16, u16, address, dest) \ + +#define load_memory_u32(address, dest) \ + fast_read_memory(32, u32, address, dest) \ + +#define load_memory_s8(address, dest) \ + fast_read_memory(8, s8, address, dest) \ + +#define load_memory_s16(address, dest) \ + fast_read_memory_s16(address, dest) \ + +#define store_memory_u8(address, value) \ + fast_write_memory(8, u8, address, value) \ + +#define store_memory_u16(address, value) \ + fast_write_memory(16, u16, address, value) \ + +#define store_memory_u32(address, value) \ + fast_write_memory(32, u32, address, value) \ + +#define no_op \ + +#define arm_access_memory_writeback_yes(off_op) \ + reg[rn] = address off_op \ + +#define arm_access_memory_writeback_no(off_op) \ + +#define arm_access_memory_pc_preadjust_load() \ + +#define arm_access_memory_pc_preadjust_store() \ + u32 reg_op = reg[rd]; \ + if(rd == 15) \ + reg_op += 4 \ + +#define arm_access_memory_pc_postadjust_load() \ + arm_update_pc() \ + +#define arm_access_memory_pc_postadjust_store() \ + +#define load_reg_op reg[rd] \ + +#define store_reg_op reg_op \ + +#define arm_access_memory(access_type, off_op, off_type, mem_type, \ + wb, wb_off_op) \ +{ \ + arm_pc_offset(8); \ + arm_data_trans_##off_type(); \ + u32 address = reg[rn] off_op; \ + arm_access_memory_pc_preadjust_##access_type(); \ + \ + arm_pc_offset(-4); \ + arm_access_memory_writeback_##wb(wb_off_op); \ + access_type##_memory_##mem_type(address, access_type##_reg_op); \ + arm_access_memory_pc_postadjust_##access_type(); \ +} \ + +#define word_bit_count(word) \ + (bit_count[word >> 8] + bit_count[word & 0xFF]) \ + +#define sprint_no(access_type, offset_type, writeback_type) \ + +#define sprint_yes(access_type, offset_type, writeback_type) \ + printf("sbit on %s %s %s\n", #access_type, #offset_type, #writeback_type) \ + +#define arm_block_writeback_load() \ + if(!((reg_list >> rn) & 0x01)) \ + { \ + reg[rn] = address; \ + } \ + +#define arm_block_writeback_store() \ + reg[rn] = address \ + +#define arm_block_writeback_yes(access_type) \ + arm_block_writeback_##access_type() \ + +#define arm_block_writeback_no(access_type) \ + +#define load_block_memory(address, dest) \ + dest = address32(address_region, (address + offset) & 0x7FFF) \ + +#define store_block_memory(address, dest) \ + address32(address_region, (address + offset) & 0x7FFF) = dest \ + +#define arm_block_memory_offset_down_a() \ + (base - (word_bit_count(reg_list) * 4) + 4) \ + +#define arm_block_memory_offset_down_b() \ + (base - (word_bit_count(reg_list) * 4)) \ + +#define arm_block_memory_offset_no() \ + (base) \ + +#define arm_block_memory_offset_up() \ + (base + 4) \ + +#define arm_block_memory_writeback_down() \ + reg[rn] = base - (word_bit_count(reg_list) * 4) \ + +#define arm_block_memory_writeback_up() \ + reg[rn] = base + (word_bit_count(reg_list) * 4) \ + +#define arm_block_memory_writeback_no() \ + +#define arm_block_memory_load_pc() \ + load_aligned32(address, pc); \ + reg[REG_PC] = pc \ + +#define arm_block_memory_store_pc() \ + store_aligned32(address, pc + 4) \ + +#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \ +{ \ + arm_decode_block_trans(); \ + u32 base = reg[rn]; \ + u32 address = arm_block_memory_offset_##offset_type() & 0xFFFFFFFC; \ + u32 i; \ + \ + arm_block_memory_writeback_##writeback_type(); \ + \ + for(i = 0; i < 15; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + access_type##_aligned32(address, reg[i]); \ + address += 4; \ + } \ + } \ + \ + arm_pc_offset(4); \ + if(reg_list & 0x8000) \ + { \ + arm_block_memory_##access_type##_pc(); \ + } \ +} \ + +#define arm_swap(type) \ +{ \ + arm_decode_swap(); \ + u32 temp; \ + load_memory_##type(reg[rn], temp); \ + store_memory_##type(reg[rn], reg[rm]); \ + reg[rd] = temp; \ + arm_pc_offset(4); \ +} \ + +#define arm_next_instruction() \ +{ \ + arm_pc_offset(4); \ + goto skip_instruction; \ +} \ + +#define thumb_update_pc() \ + pc = reg[REG_PC] \ + +#define thumb_pc_offset(val) \ + pc += val; \ + reg[REG_PC] = pc \ + +#define thumb_pc_offset_update(val) \ + pc += val; \ + reg[REG_PC] = pc \ + +#define thumb_pc_offset_update_direct(val) \ + pc = val; \ + reg[REG_PC] = pc \ + +// Types: add_sub, add_sub_imm, alu_op, imm +// Affects N/Z/C/V flags + +#define thumb_add(type, dest_reg, src_a, src_b) \ +{ \ + thumb_decode_##type(); \ + const u32 _sa = src_a; \ + const u32 _sb = src_b; \ + u32 dest = _sa + _sb; \ + calculate_flags_add(dest, src_a, src_b); \ + reg[dest_reg] = dest; \ + thumb_pc_offset(2); \ +} \ + +#define thumb_add_noflags(type, dest_reg, src_a, src_b) \ +{ \ + thumb_decode_##type(); \ + u32 dest = src_a + src_b; \ + reg[dest_reg] = dest; \ + thumb_pc_offset(2); \ +} \ + +#define thumb_sub(type, dest_reg, src_a, src_b) \ +{ \ + thumb_decode_##type(); \ + const u32 _sa = src_a; \ + const u32 _sb = src_b; \ + u32 dest = _sa - _sb; \ + calculate_flags_sub(dest, src_a, src_b); \ + reg[dest_reg] = dest; \ + thumb_pc_offset(2); \ +} \ + +// Affects N/Z flags + +#define thumb_logic(type, dest_reg, expr) \ +{ \ + thumb_decode_##type(); \ + u32 dest = expr; \ + calculate_flags_logic(dest); \ + reg[dest_reg] = dest; \ + thumb_pc_offset(2); \ +} \ + +// Decode types: shift, alu_op +// Operation types: lsl, lsr, asr, ror +// Affects N/Z/C flags + +#define thumb_shift_lsl_reg() \ + u32 shift = reg[rs]; \ + u32 dest = reg[rd]; \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + if(shift == 32) \ + c_flag = dest & 0x01; \ + else \ + c_flag = 0; \ + dest = 0; \ + } \ + else \ + { \ + c_flag = (dest >> (32 - shift)) & 0x01; \ + dest <<= shift; \ + } \ + } \ + +#define thumb_shift_lsr_reg() \ + u32 shift = reg[rs]; \ + u32 dest = reg[rd]; \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + if(shift == 32) \ + c_flag = dest >> 31; \ + else \ + c_flag = 0; \ + dest = 0; \ + } \ + else \ + { \ + c_flag = (dest >> (shift - 1)) & 0x01; \ + dest >>= shift; \ + } \ + } \ + +#define thumb_shift_asr_reg() \ + u32 shift = reg[rs]; \ + u32 dest = reg[rd]; \ + if(shift != 0) \ + { \ + if(shift > 31) \ + { \ + dest = (s32)dest >> 31; \ + c_flag = dest & 0x01; \ + } \ + else \ + { \ + c_flag = (dest >> (shift - 1)) & 0x01; \ + dest = (s32)dest >> shift; \ + } \ + } \ + +#define thumb_shift_ror_reg() \ + u32 shift = reg[rs]; \ + u32 dest = reg[rd]; \ + if(shift != 0) \ + { \ + c_flag = (dest >> (shift - 1)) & 0x01; \ + ror(dest, dest, shift); \ + } \ + +#define thumb_shift_lsl_imm() \ + u32 dest = reg[rs]; \ + if(imm != 0) \ + { \ + c_flag = (dest >> (32 - imm)) & 0x01; \ + dest <<= imm; \ + } \ + +#define thumb_shift_lsr_imm() \ + u32 dest; \ + if(imm == 0) \ + { \ + dest = 0; \ + c_flag = reg[rs] >> 31; \ + } \ + else \ + { \ + dest = reg[rs]; \ + c_flag = (dest >> (imm - 1)) & 0x01; \ + dest >>= imm; \ + } \ + +#define thumb_shift_asr_imm() \ + u32 dest; \ + if(imm == 0) \ + { \ + dest = (s32)reg[rs] >> 31; \ + c_flag = dest & 0x01; \ + } \ + else \ + { \ + dest = reg[rs]; \ + c_flag = (dest >> (imm - 1)) & 0x01; \ + dest = (s32)dest >> imm; \ + } \ + +#define thumb_shift_ror_imm() \ + u32 dest = reg[rs]; \ + if(imm == 0) \ + { \ + u32 old_c_flag = c_flag; \ + c_flag = dest & 0x01; \ + dest = (dest >> 1) | (old_c_flag << 31); \ + } \ + else \ + { \ + c_flag = (dest >> (imm - 1)) & 0x01; \ + ror(dest, dest, imm); \ + } \ + +#define thumb_shift(decode_type, op_type, value_type) \ +{ \ + thumb_decode_##decode_type(); \ + thumb_shift_##op_type##_##value_type(); \ + calculate_flags_logic(dest); \ + reg[rd] = dest; \ + thumb_pc_offset(2); \ +} \ + +#define thumb_test_add(type, src_a, src_b) \ +{ \ + thumb_decode_##type(); \ + const u32 _sa = src_a; \ + const u32 _sb = src_b; \ + u32 dest = _sa + _sb; \ + calculate_flags_add(dest, src_a, src_b); \ + thumb_pc_offset(2); \ +} \ + +#define thumb_test_sub(type, src_a, src_b) \ +{ \ + thumb_decode_##type(); \ + const u32 _sa = src_a; \ + const u32 _sb = src_b; \ + u32 dest = _sa - _sb; \ + calculate_flags_sub(dest, src_a, src_b); \ + thumb_pc_offset(2); \ +} \ + +#define thumb_test_logic(type, expr) \ +{ \ + thumb_decode_##type(); \ + u32 dest = expr; \ + calculate_flags_logic(dest); \ + thumb_pc_offset(2); \ +} + +#define thumb_hireg_op(expr) \ +{ \ + thumb_pc_offset(4); \ + thumb_decode_hireg_op(); \ + u32 dest = expr; \ + thumb_pc_offset(-2); \ + if(rd == 15) \ + { \ + reg[REG_PC] = dest & ~0x01; \ + thumb_update_pc(); \ + } \ + else \ + { \ + reg[rd] = dest; \ + } \ +} \ + +// Operation types: imm, mem_reg, mem_imm + +#define thumb_access_memory(access_type, op_type, address, reg_op, \ + mem_type) \ +{ \ + thumb_decode_##op_type(); \ + access_type##_memory_##mem_type(address, reg_op); \ + thumb_pc_offset(2); \ +} \ + +#define thumb_block_address_preadjust_no_op() \ + +#define thumb_block_address_preadjust_up() \ + address += bit_count[reg_list] * 4 \ + +#define thumb_block_address_preadjust_down() \ + address -= bit_count[reg_list] * 4 \ + +#define thumb_block_address_preadjust_push_lr() \ + address -= (bit_count[reg_list] + 1) * 4 \ + +#define thumb_block_address_postadjust_no_op() \ + +#define thumb_block_address_postadjust_up() \ + address += offset \ + +#define thumb_block_address_postadjust_down() \ + address -= offset \ + +#define thumb_block_address_postadjust_pop_pc() \ + load_memory_u32(address + offset, pc); \ + pc &= ~0x01; \ + reg[REG_PC] = pc; \ + address += offset + 4 \ + +#define thumb_block_address_postadjust_push_lr() \ + store_memory_u32(address + offset, reg[REG_LR]); \ + +#define thumb_block_memory_wb_load(base_reg) \ + if(!((reg_list >> base_reg) & 0x01)) \ + { \ + reg[base_reg] = address; \ + } \ + +#define thumb_block_memory_wb_store(base_reg) \ + reg[base_reg] = address \ + +#define thumb_block_memory(access_type, pre_op, post_op, base_reg) \ +{ \ + u32 i; \ + u32 offset = 0; \ + thumb_decode_rlist(); \ + using_register(thumb, base_reg, memory_base); \ + u32 address = reg[base_reg] & ~0x03; \ + thumb_block_address_preadjust_##pre_op(); \ + \ + for(i = 0; i < 8; i++) \ + { \ + if((reg_list >> i) & 1) \ + { \ + access_type##_aligned32(address + offset, reg[i]); \ + offset += 4; \ + } \ + } \ + \ + thumb_pc_offset(2); \ + \ + thumb_block_address_postadjust_##post_op(); \ + thumb_block_memory_wb_##access_type(base_reg); \ +} \ + +#define thumb_conditional_branch(condition) \ +{ \ + thumb_decode_branch_cond(); \ + if(condition) \ + { \ + thumb_pc_offset((offset * 2) + 4); \ + } \ + else \ + { \ + thumb_pc_offset(2); \ + } \ +} \ + +// When a mode change occurs from non-FIQ to non-FIQ retire the current +// reg[13] and reg[14] into reg_mode[cpu_mode][5] and reg_mode[cpu_mode][6] +// respectively and load into reg[13] and reg[14] reg_mode[new_mode][5] and +// reg_mode[new_mode][6]. When swapping to/from FIQ retire/load reg[8] +// through reg[14] to/from reg_mode[MODE_FIQ][0] through reg_mode[MODE_FIQ][6]. + +u32 reg_mode[7][7]; + +u32 cpu_modes[32] = +{ + MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, + MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, + MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, + MODE_INVALID, MODE_USER, MODE_FIQ, MODE_IRQ, MODE_SUPERVISOR, MODE_INVALID, + MODE_INVALID, MODE_INVALID, MODE_ABORT, MODE_INVALID, MODE_INVALID, + MODE_INVALID, MODE_INVALID, MODE_UNDEFINED, MODE_INVALID, MODE_INVALID, + MODE_USER +}; + +u32 cpu_modes_cpsr[7] = { 0x10, 0x11, 0x12, 0x13, 0x17, 0x1B, 0x1F }; + +// When switching modes set spsr[new_mode] to cpsr. Modifying PC as the +// target of a data proc instruction will set cpsr to spsr[cpu_mode]. + +u32 initial_reg[64]; +u32 *reg = initial_reg; +u32 spsr[6]; + +// ARM/Thumb mode is stored in the flags directly, this is simpler than +// shadowing it since it has a constant 1bit represenation. + +char *reg_names[16] = +{ + " r0", " r1", " r2", " r3", " r4", " r5", " r6", " r7", + " r8", " r9", "r10", " fp", " ip", " sp", " lr", " pc" +}; + +char *cpu_mode_names[] = +{ + "user", "irq", "fiq", "svsr", "abrt", "undf", "invd" +}; + + +#define execute_arm_instruction() \ + using_instruction(arm); \ + check_pc_region(); \ + pc &= ~0x03; \ + opcode = address32(pc_address_block, (pc & 0x7FFF)); \ + condition = opcode >> 28; \ + \ + switch(condition) \ + { \ + case 0x0: \ + /* EQ */ \ + if(!z_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x1: \ + /* NE */ \ + if(z_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x2: \ + /* CS */ \ + if(!c_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x3: \ + /* CC */ \ + if(c_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x4: \ + /* MI */ \ + if(!n_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x5: \ + /* PL */ \ + if(n_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x6: \ + /* VS */ \ + if(!v_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x7: \ + /* VC */ \ + if(v_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x8: \ + /* HI */ \ + if((c_flag == 0) | z_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0x9: \ + /* LS */ \ + if(c_flag & (z_flag ^ 1)) \ + arm_next_instruction(); \ + break; \ + \ + case 0xA: \ + /* GE */ \ + if(n_flag != v_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0xB: \ + /* LT */ \ + if(n_flag == v_flag) \ + arm_next_instruction(); \ + break; \ + \ + case 0xC: \ + /* GT */ \ + if(z_flag | (n_flag != v_flag)) \ + arm_next_instruction(); \ + break; \ + \ + case 0xD: \ + /* LE */ \ + if((z_flag == 0) & (n_flag == v_flag)) \ + arm_next_instruction(); \ + break; \ + \ + case 0xE: \ + /* AL */ \ + break; \ + \ + case 0xF: \ + /* Reserved - treat as "never" */ \ + quit(); \ + arm_next_instruction(); \ + break; \ + } \ + \ + switch((opcode >> 20) & 0xFF) \ + { \ + case 0x00: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], -rm */ \ + arm_access_memory(store, no_op, half_reg, u16, yes, - reg[rm]); \ + } \ + else \ + { \ + /* MUL rd, rm, rs */ \ + arm_multiply(no_op, no); \ + } \ + } \ + else \ + { \ + /* AND rd, rn, reg_op */ \ + arm_data_proc(reg[rn] & reg_sh, reg); \ + } \ + break; \ + \ + case 0x01: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* MULS rd, rm, rs */ \ + arm_multiply(no_op, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, u16, yes, - reg[rm]); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, s8, yes, - reg[rm]); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, s16, yes, - reg[rm]); \ + break; \ + } \ + } \ + else \ + { \ + /* ANDS rd, rn, reg_op */ \ + arm_data_proc_logic_flags(reg[rn] & reg_sh, reg); \ + } \ + break; \ + \ + case 0x02: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], -rm */ \ + arm_access_memory(store, no_op, half_reg, u16, yes, - reg[rm]); \ + } \ + else \ + { \ + /* MLA rd, rm, rs, rn */ \ + arm_multiply(+ reg[rn], no); \ + } \ + } \ + else \ + { \ + /* EOR rd, rn, reg_op */ \ + arm_data_proc(reg[rn] ^ reg_sh, reg); \ + } \ + break; \ + \ + case 0x03: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* MLAS rd, rm, rs, rn */ \ + arm_multiply(+ reg[rn], yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, u16, yes, - reg[rm]); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, s8, yes, - reg[rm]); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -rm */ \ + arm_access_memory(load, no_op, half_reg, s16, yes, - reg[rm]); \ + break; \ + } \ + } \ + else \ + { \ + /* EORS rd, rn, reg_op */ \ + arm_data_proc_logic_flags(reg[rn] ^ reg_sh, reg); \ + } \ + break; \ + \ + case 0x04: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn], -imm */ \ + arm_access_memory(store, no_op, half_imm, u16, yes, - offset); \ + } \ + else \ + { \ + /* SUB rd, rn, reg_op */ \ + arm_data_proc(reg[rn] - reg_sh, reg); \ + } \ + break; \ + \ + case 0x05: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, u16, yes, - offset); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, s8, yes, - offset); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, s16, yes, - offset); \ + break; \ + } \ + } \ + else \ + { \ + /* SUBS rd, rn, reg_op */ \ + arm_data_proc_sub_flags(reg[rn], reg_sh, reg); \ + } \ + break; \ + \ + case 0x06: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn], -imm */ \ + arm_access_memory(store, no_op, half_imm, u16, yes, - offset); \ + } \ + else \ + { \ + /* RSB rd, rn, reg_op */ \ + arm_data_proc(reg_sh - reg[rn], reg); \ + } \ + break; \ + \ + case 0x07: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, u16, yes, - offset); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, s8, yes, - offset); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -imm */ \ + arm_access_memory(load, no_op, half_imm, s16, yes, - offset); \ + break; \ + } \ + } \ + else \ + { \ + /* RSBS rd, rn, reg_op */ \ + arm_data_proc_sub_flags(reg_sh, reg[rn], reg); \ + } \ + break; \ + \ + case 0x08: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +rm */ \ + arm_access_memory(store, no_op, half_reg, u16, yes, + reg[rm]); \ + } \ + else \ + { \ + /* UMULL rd, rm, rs */ \ + arm_multiply_long(no_op, no, u); \ + } \ + } \ + else \ + { \ + /* ADD rd, rn, reg_op */ \ + arm_data_proc(reg[rn] + reg_sh, reg); \ + } \ + break; \ + \ + case 0x09: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* UMULLS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(no_op, yes, u); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, u16, yes, + reg[rm]); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, s8, yes, + reg[rm]); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, s16, yes, + reg[rm]); \ + break; \ + } \ + } \ + else \ + { \ + /* ADDS rd, rn, reg_op */ \ + arm_data_proc_add_flags(reg[rn], reg_sh, reg); \ + } \ + break; \ + \ + case 0x0A: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +rm */ \ + arm_access_memory(store, no_op, half_reg, u16, yes, + reg[rm]); \ + } \ + else \ + { \ + /* UMLAL rd, rm, rs */ \ + arm_multiply_long(arm_multiply_long_addop(u), no, u); \ + } \ + } \ + else \ + { \ + /* ADC rd, rn, reg_op */ \ + arm_data_proc(reg[rn] + reg_sh + c_flag, reg); \ + } \ + break; \ + \ + case 0x0B: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* UMLALS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(arm_multiply_long_addop(u), yes, u); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, u16, yes, + reg[rm]); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, s8, yes, + reg[rm]); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +rm */ \ + arm_access_memory(load, no_op, half_reg, s16, yes, + reg[rm]); \ + break; \ + } \ + } \ + else \ + { \ + /* ADCS rd, rn, reg_op */ \ + arm_data_proc_add_flags(reg[rn], reg_sh + c_flag, reg); \ + } \ + break; \ + \ + case 0x0C: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +imm */ \ + arm_access_memory(store, no_op, half_imm, u16, yes, + offset); \ + } \ + else \ + { \ + /* SMULL rd, rm, rs */ \ + arm_multiply_long(no_op, no, s); \ + } \ + } \ + else \ + { \ + /* SBC rd, rn, reg_op */ \ + arm_data_proc(reg[rn] - (reg_sh + (c_flag ^ 1)), reg); \ + } \ + break; \ + \ + case 0x0D: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* SMULLS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(no_op, yes, s); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, u16, yes, + offset); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, s8, yes, + offset); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, s16, yes, + offset); \ + break; \ + } \ + } \ + else \ + { \ + /* SBCS rd, rn, reg_op */ \ + arm_data_proc_sub_flags(reg[rn], (reg_sh + (c_flag ^ 1)), reg); \ + } \ + break; \ + \ + case 0x0E: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +imm */ \ + arm_access_memory(store, no_op, half_imm, u16, yes, + offset); \ + } \ + else \ + { \ + /* SMLAL rd, rm, rs */ \ + arm_multiply_long(arm_multiply_long_addop(s), no, s); \ + } \ + } \ + else \ + { \ + /* RSC rd, rn, reg_op */ \ + arm_data_proc(reg_sh - reg[rn] + c_flag - 1, reg); \ + } \ + break; \ + \ + case 0x0F: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* SMLALS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(arm_multiply_long_addop(s), yes, s); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, u16, yes, + offset); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, s8, yes, + offset); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +imm */ \ + arm_access_memory(load, no_op, half_imm, s16, yes, + offset); \ + break; \ + } \ + } \ + else \ + { \ + /* RSCS rd, rn, reg_op */ \ + arm_data_proc_sub_flags((reg_sh + c_flag - 1), reg[rn], reg); \ + } \ + break; \ + \ + case 0x10: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn - rm] */ \ + arm_access_memory(store, - reg[rm], half_reg, u16, no, no_op); \ + } \ + else \ + { \ + /* SWP rd, rm, [rn] */ \ + arm_swap(u32); \ + } \ + } \ + else \ + { \ + /* MRS rd, cpsr */ \ + arm_psr(reg, read, reg[REG_CPSR]); \ + } \ + break; \ + \ + case 0x11: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - rm] */ \ + arm_access_memory(load, - reg[rm], half_reg, u16, no, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - rm] */ \ + arm_access_memory(load, - reg[rm], half_reg, s8, no, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - rm] */ \ + arm_access_memory(load, - reg[rm], half_reg, s16, no, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* TST rd, rn, reg_op */ \ + arm_data_proc_test_logic(reg[rn] & reg_sh, reg); \ + } \ + break; \ + \ + case 0x12: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn - rm]! */ \ + arm_access_memory(store, - reg[rm], half_reg, u16, yes, no_op); \ + } \ + else \ + { \ + if(opcode & 0x10) \ + { \ + /* BX rn */ \ + arm_decode_branchx(); \ + u32 src = reg[rn]; \ + if(src & 0x01) \ + { \ + src -= 1; \ + arm_pc_offset_update_direct(src); \ + reg[REG_CPSR] |= 0x20; \ + goto thumb_loop; \ + } \ + else \ + { \ + arm_pc_offset_update_direct(src); \ + } \ + } \ + else \ + { \ + /* MSR cpsr, rm */ \ + arm_psr(reg, store, cpsr); \ + } \ + } \ + break; \ + \ + case 0x13: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - rm]! */ \ + arm_access_memory(load, - reg[rm], half_reg, u16, yes, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - rm]! */ \ + arm_access_memory(load, - reg[rm], half_reg, s8, yes, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - rm]! */ \ + arm_access_memory(load, - reg[rm], half_reg, s16, yes, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* TEQ rd, rn, reg_op */ \ + arm_data_proc_test_logic(reg[rn] ^ reg_sh, reg); \ + } \ + break; \ + \ + case 0x14: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn - imm] */ \ + arm_access_memory(store, - offset, half_imm, u16, no, no_op); \ + } \ + else \ + { \ + /* SWPB rd, rm, [rn] */ \ + arm_swap(u8); \ + } \ + } \ + else \ + { \ + /* MRS rd, spsr */ \ + arm_psr(reg, read, spsr[reg[CPU_MODE]]); \ + } \ + break; \ + \ + case 0x15: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - imm] */ \ + arm_access_memory(load, - offset, half_imm, u16, no, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - imm] */ \ + arm_access_memory(load, - offset, half_imm, s8, no, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - imm] */ \ + arm_access_memory(load, - offset, half_imm, s16, no, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* CMP rn, reg_op */ \ + arm_data_proc_test_sub(reg[rn], reg_sh, reg); \ + } \ + break; \ + \ + case 0x16: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn - imm]! */ \ + arm_access_memory(store, - offset, half_imm, u16, yes, no_op); \ + } \ + else \ + { \ + /* MSR spsr, rm */ \ + arm_psr(reg, store, spsr); \ + } \ + break; \ + \ + case 0x17: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - imm]! */ \ + arm_access_memory(load, - offset, half_imm, u16, yes, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - imm]! */ \ + arm_access_memory(load, - offset, half_imm, s8, yes, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - imm]! */ \ + arm_access_memory(load, - offset, half_imm, s16, yes, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* CMN rd, rn, reg_op */ \ + arm_data_proc_test_add(reg[rn], reg_sh, reg); \ + } \ + break; \ + \ + case 0x18: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + rm] */ \ + arm_access_memory(store, + reg[rm], half_reg, u16, no, no_op); \ + } \ + else \ + { \ + /* ORR rd, rn, reg_op */ \ + arm_data_proc(reg[rn] | reg_sh, reg); \ + } \ + break; \ + \ + case 0x19: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + rm] */ \ + arm_access_memory(load, + reg[rm], half_reg, u16, no, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + rm] */ \ + arm_access_memory(load, + reg[rm], half_reg, s8, no, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + rm] */ \ + arm_access_memory(load, + reg[rm], half_reg, s16, no, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* ORRS rd, rn, reg_op */ \ + arm_data_proc_logic_flags(reg[rn] | reg_sh, reg); \ + } \ + break; \ + \ + case 0x1A: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + rm]! */ \ + arm_access_memory(store, + reg[rm], half_reg, u16, yes, no_op); \ + } \ + else \ + { \ + /* MOV rd, reg_op */ \ + arm_data_proc(reg_sh, reg); \ + } \ + break; \ + \ + case 0x1B: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + rm]! */ \ + arm_access_memory(load, + reg[rm], half_reg, u16, yes, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + rm]! */ \ + arm_access_memory(load, + reg[rm], half_reg, s8, yes, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + rm]! */ \ + arm_access_memory(load, + reg[rm], half_reg, s16, yes, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* MOVS rd, reg_op */ \ + arm_data_proc_logic_flags(reg_sh, reg); \ + } \ + break; \ + \ + case 0x1C: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + imm] */ \ + arm_access_memory(store, + offset, half_imm, u16, no, no_op); \ + } \ + else \ + { \ + /* BIC rd, rn, reg_op */ \ + arm_data_proc(reg[rn] & (~reg_sh), reg); \ + } \ + break; \ + \ + case 0x1D: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + imm] */ \ + arm_access_memory(load, + offset, half_imm, u16, no, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + imm] */ \ + arm_access_memory(load, + offset, half_imm, s8, no, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + imm] */ \ + arm_access_memory(load, + offset, half_imm, s16, no, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* BICS rd, rn, reg_op */ \ + arm_data_proc_logic_flags(reg[rn] & (~reg_sh), reg); \ + } \ + break; \ + \ + case 0x1E: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + imm]! */ \ + arm_access_memory(store, + offset, half_imm, u16, yes, no_op); \ + } \ + else \ + { \ + /* MVN rd, reg_op */ \ + arm_data_proc(~reg_sh, reg); \ + } \ + break; \ + \ + case 0x1F: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + imm]! */ \ + arm_access_memory(load, + offset, half_imm, u16, yes, no_op); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + imm]! */ \ + arm_access_memory(load, + offset, half_imm, s8, yes, no_op); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + imm]! */ \ + arm_access_memory(load, + offset, half_imm, s16, yes, no_op); \ + break; \ + } \ + } \ + else \ + { \ + /* MVNS rd, rn, reg_op */ \ + arm_data_proc_logic_flags(~reg_sh, reg); \ + } \ + break; \ + \ + case 0x20: \ + /* AND rd, rn, imm */ \ + arm_data_proc(reg[rn] & imm, imm); \ + break; \ + \ + case 0x21: \ + /* ANDS rd, rn, imm */ \ + arm_data_proc_logic_flags(reg[rn] & imm, imm); \ + break; \ + \ + case 0x22: \ + /* EOR rd, rn, imm */ \ + arm_data_proc(reg[rn] ^ imm, imm); \ + break; \ + \ + case 0x23: \ + /* EORS rd, rn, imm */ \ + arm_data_proc_logic_flags(reg[rn] ^ imm, imm); \ + break; \ + \ + case 0x24: \ + /* SUB rd, rn, imm */ \ + arm_data_proc(reg[rn] - imm, imm); \ + break; \ + \ + case 0x25: \ + /* SUBS rd, rn, imm */ \ + arm_data_proc_sub_flags(reg[rn], imm, imm); \ + break; \ + \ + case 0x26: \ + /* RSB rd, rn, imm */ \ + arm_data_proc(imm - reg[rn], imm); \ + break; \ + \ + case 0x27: \ + /* RSBS rd, rn, imm */ \ + arm_data_proc_sub_flags(imm, reg[rn], imm); \ + break; \ + \ + case 0x28: \ + /* ADD rd, rn, imm */ \ + arm_data_proc(reg[rn] + imm, imm); \ + break; \ + \ + case 0x29: \ + /* ADDS rd, rn, imm */ \ + arm_data_proc_add_flags(reg[rn], imm, imm); \ + break; \ + \ + case 0x2A: \ + /* ADC rd, rn, imm */ \ + arm_data_proc(reg[rn] + imm + c_flag, imm); \ + break; \ + \ + case 0x2B: \ + /* ADCS rd, rn, imm */ \ + arm_data_proc_add_flags(reg[rn] + imm, c_flag, imm); \ + break; \ + \ + case 0x2C: \ + /* SBC rd, rn, imm */ \ + arm_data_proc(reg[rn] - imm + c_flag - 1, imm); \ + break; \ + \ + case 0x2D: \ + /* SBCS rd, rn, imm */ \ + arm_data_proc_sub_flags(reg[rn], (imm + (c_flag ^ 1)), imm); \ + break; \ + \ + case 0x2E: \ + /* RSC rd, rn, imm */ \ + arm_data_proc(imm - reg[rn] + c_flag - 1, imm); \ + break; \ + \ + case 0x2F: \ + /* RSCS rd, rn, imm */ \ + arm_data_proc_sub_flags((imm + c_flag - 1), reg[rn], imm); \ + break; \ + \ + case 0x30 ... 0x31: \ + /* TST rn, imm */ \ + arm_data_proc_test_logic(reg[rn] & imm, imm); \ + break; \ + \ + case 0x32: \ + /* MSR cpsr, imm */ \ + arm_psr(imm, store, cpsr); \ + break; \ + \ + case 0x33: \ + /* TEQ rn, imm */ \ + arm_data_proc_test_logic(reg[rn] ^ imm, imm); \ + break; \ + \ + case 0x34 ... 0x35: \ + /* CMP rn, imm */ \ + arm_data_proc_test_sub(reg[rn], imm, imm); \ + break; \ + \ + case 0x36: \ + /* MSR spsr, imm */ \ + arm_psr(imm, store, spsr); \ + break; \ + \ + case 0x37: \ + /* CMN rn, imm */ \ + arm_data_proc_test_add(reg[rn], imm, imm); \ + break; \ + \ + case 0x38: \ + /* ORR rd, rn, imm */ \ + arm_data_proc(reg[rn] | imm, imm); \ + break; \ + \ + case 0x39: \ + /* ORRS rd, rn, imm */ \ + arm_data_proc_logic_flags(reg[rn] | imm, imm); \ + break; \ + \ + case 0x3A: \ + /* MOV rd, imm */ \ + arm_data_proc(imm, imm); \ + break; \ + \ + case 0x3B: \ + /* MOVS rd, imm */ \ + arm_data_proc_logic_flags(imm, imm); \ + break; \ + \ + case 0x3C: \ + /* BIC rd, rn, imm */ \ + arm_data_proc(reg[rn] & (~imm), imm); \ + break; \ + \ + case 0x3D: \ + /* BICS rd, rn, imm */ \ + arm_data_proc_logic_flags(reg[rn] & (~imm), imm); \ + break; \ + \ + case 0x3E: \ + /* MVN rd, imm */ \ + arm_data_proc(~imm, imm); \ + break; \ + \ + case 0x3F: \ + /* MVNS rd, imm */ \ + arm_data_proc_logic_flags(~imm, imm); \ + break; \ + \ + case 0x40: \ + /* STR rd, [rn], -imm */ \ + arm_access_memory(store, no_op, imm, u32, yes, - offset); \ + break; \ + \ + case 0x41: \ + /* LDR rd, [rn], -imm */ \ + arm_access_memory(load, no_op, imm, u32, yes, - offset); \ + break; \ + \ + case 0x42: \ + /* STRT rd, [rn], -imm */ \ + arm_access_memory(store, no_op, imm, u32, yes, - offset); \ + break; \ + \ + case 0x43: \ + /* LDRT rd, [rn], -imm */ \ + arm_access_memory(load, no_op, imm, u32, yes, - offset); \ + break; \ + \ + case 0x44: \ + /* STRB rd, [rn], -imm */ \ + arm_access_memory(store, no_op, imm, u8, yes, - offset); \ + break; \ + \ + case 0x45: \ + /* LDRB rd, [rn], -imm */ \ + arm_access_memory(load, no_op, imm, u8, yes, - offset); \ + break; \ + \ + case 0x46: \ + /* STRBT rd, [rn], -imm */ \ + arm_access_memory(store, no_op, imm, u8, yes, - offset); \ + break; \ + \ + case 0x47: \ + /* LDRBT rd, [rn], -imm */ \ + arm_access_memory(load, no_op, imm, u8, yes, - offset); \ + break; \ + \ + case 0x48: \ + /* STR rd, [rn], +imm */ \ + arm_access_memory(store, no_op, imm, u32, yes, + offset); \ + break; \ + \ + case 0x49: \ + /* LDR rd, [rn], +imm */ \ + arm_access_memory(load, no_op, imm, u32, yes, + offset); \ + break; \ + \ + case 0x4A: \ + /* STRT rd, [rn], +imm */ \ + arm_access_memory(store, no_op, imm, u32, yes, + offset); \ + break; \ + \ + case 0x4B: \ + /* LDRT rd, [rn], +imm */ \ + arm_access_memory(load, no_op, imm, u32, yes, + offset); \ + break; \ + \ + case 0x4C: \ + /* STRB rd, [rn], +imm */ \ + arm_access_memory(store, no_op, imm, u8, yes, + offset); \ + break; \ + \ + case 0x4D: \ + /* LDRB rd, [rn], +imm */ \ + arm_access_memory(load, no_op, imm, u8, yes, + offset); \ + break; \ + \ + case 0x4E: \ + /* STRBT rd, [rn], +imm */ \ + arm_access_memory(store, no_op, imm, u8, yes, + offset); \ + break; \ + \ + case 0x4F: \ + /* LDRBT rd, [rn], +imm */ \ + arm_access_memory(load, no_op, imm, u8, yes, + offset); \ + break; \ + \ + case 0x50: \ + /* STR rd, [rn - imm] */ \ + arm_access_memory(store, - offset, imm, u32, no, no_op); \ + break; \ + \ + case 0x51: \ + /* LDR rd, [rn - imm] */ \ + arm_access_memory(load, - offset, imm, u32, no, no_op); \ + break; \ + \ + case 0x52: \ + /* STR rd, [rn - imm]! */ \ + arm_access_memory(store, - offset, imm, u32, yes, no_op); \ + break; \ + \ + case 0x53: \ + /* LDR rd, [rn - imm]! */ \ + arm_access_memory(load, - offset, imm, u32, yes, no_op); \ + break; \ + \ + case 0x54: \ + /* STRB rd, [rn - imm] */ \ + arm_access_memory(store, - offset, imm, u8, no, no_op); \ + break; \ + \ + case 0x55: \ + /* LDRB rd, [rn - imm] */ \ + arm_access_memory(load, - offset, imm, u8, no, no_op); \ + break; \ + \ + case 0x56: \ + /* STRB rd, [rn - imm]! */ \ + arm_access_memory(store, - offset, imm, u8, yes, no_op); \ + break; \ + \ + case 0x57: \ + /* LDRB rd, [rn - imm]! */ \ + arm_access_memory(load, - offset, imm, u8, yes, no_op); \ + break; \ + \ + case 0x58: \ + /* STR rd, [rn + imm] */ \ + arm_access_memory(store, + offset, imm, u32, no, no_op); \ + break; \ + \ + case 0x59: \ + /* LDR rd, [rn + imm] */ \ + arm_access_memory(load, + offset, imm, u32, no, no_op); \ + break; \ + \ + case 0x5A: \ + /* STR rd, [rn + imm]! */ \ + arm_access_memory(store, + offset, imm, u32, yes, no_op); \ + break; \ + \ + case 0x5B: \ + /* LDR rd, [rn + imm]! */ \ + arm_access_memory(load, + offset, imm, u32, yes, no_op); \ + break; \ + \ + case 0x5C: \ + /* STRB rd, [rn + imm] */ \ + arm_access_memory(store, + offset, imm, u8, no, no_op); \ + break; \ + \ + case 0x5D: \ + /* LDRB rd, [rn + imm] */ \ + arm_access_memory(load, + offset, imm, u8, no, no_op); \ + break; \ + \ + case 0x5E: \ + /* STRB rd, [rn + imm]! */ \ + arm_access_memory(store, + offset, imm, u8, yes, no_op); \ + break; \ + \ + case 0x5F: \ + /* LDRBT rd, [rn + imm]! */ \ + arm_access_memory(load, + offset, imm, u8, yes, no_op); \ + break; \ + \ + case 0x60: \ + /* STR rd, [rn], -reg_op */ \ + arm_access_memory(store, no_op, reg, u32, yes, - reg_offset); \ + break; \ + \ + case 0x61: \ + /* LDR rd, [rn], -reg_op */ \ + arm_access_memory(load, no_op, reg, u32, yes, - reg_offset); \ + break; \ + \ + case 0x62: \ + /* STRT rd, [rn], -reg_op */ \ + arm_access_memory(store, no_op, reg, u32, yes, - reg_offset); \ + break; \ + \ + case 0x63: \ + /* LDRT rd, [rn], -reg_op */ \ + arm_access_memory(load, no_op, reg, u32, yes, - reg_offset); \ + break; \ + \ + case 0x64: \ + /* STRB rd, [rn], -reg_op */ \ + arm_access_memory(store, no_op, reg, u8, yes, - reg_offset); \ + break; \ + \ + case 0x65: \ + /* LDRB rd, [rn], -reg_op */ \ + arm_access_memory(load, no_op, reg, u8, yes, - reg_offset); \ + break; \ + \ + case 0x66: \ + /* STRBT rd, [rn], -reg_op */ \ + arm_access_memory(store, no_op, reg, u8, yes, - reg_offset); \ + break; \ + \ + case 0x67: \ + /* LDRBT rd, [rn], -reg_op */ \ + arm_access_memory(load, no_op, reg, u8, yes, - reg_offset); \ + break; \ + \ + case 0x68: \ + /* STR rd, [rn], +reg_op */ \ + arm_access_memory(store, no_op, reg, u32, yes, + reg_offset); \ + break; \ + \ + case 0x69: \ + /* LDR rd, [rn], +reg_op */ \ + arm_access_memory(load, no_op, reg, u32, yes, + reg_offset); \ + break; \ + \ + case 0x6A: \ + /* STRT rd, [rn], +reg_op */ \ + arm_access_memory(store, no_op, reg, u32, yes, + reg_offset); \ + break; \ + \ + case 0x6B: \ + /* LDRT rd, [rn], +reg_op */ \ + arm_access_memory(load, no_op, reg, u32, yes, + reg_offset); \ + break; \ + \ + case 0x6C: \ + /* STRB rd, [rn], +reg_op */ \ + arm_access_memory(store, no_op, reg, u8, yes, + reg_offset); \ + break; \ + \ + case 0x6D: \ + /* LDRB rd, [rn], +reg_op */ \ + arm_access_memory(load, no_op, reg, u8, yes, + reg_offset); \ + break; \ + \ + case 0x6E: \ + /* STRBT rd, [rn], +reg_op */ \ + arm_access_memory(store, no_op, reg, u8, yes, + reg_offset); \ + break; \ + \ + case 0x6F: \ + /* LDRBT rd, [rn], +reg_op */ \ + arm_access_memory(load, no_op, reg, u8, yes, + reg_offset); \ + break; \ + \ + case 0x70: \ + /* STR rd, [rn - reg_op] */ \ + arm_access_memory(store, - reg_offset, reg, u32, no, no_op); \ + break; \ + \ + case 0x71: \ + /* LDR rd, [rn - reg_op] */ \ + arm_access_memory(load, - reg_offset, reg, u32, no, no_op); \ + break; \ + \ + case 0x72: \ + /* STR rd, [rn - reg_op]! */ \ + arm_access_memory(store, - reg_offset, reg, u32, yes, no_op); \ + break; \ + \ + case 0x73: \ + /* LDR rd, [rn - reg_op]! */ \ + arm_access_memory(load, - reg_offset, reg, u32, yes, no_op); \ + break; \ + \ + case 0x74: \ + /* STRB rd, [rn - reg_op] */ \ + arm_access_memory(store, - reg_offset, reg, u8, no, no_op); \ + break; \ + \ + case 0x75: \ + /* LDRB rd, [rn - reg_op] */ \ + arm_access_memory(load, - reg_offset, reg, u8, no, no_op); \ + break; \ + \ + case 0x76: \ + /* STRB rd, [rn - reg_op]! */ \ + arm_access_memory(store, - reg_offset, reg, u8, yes, no_op); \ + break; \ + \ + case 0x77: \ + /* LDRB rd, [rn - reg_op]! */ \ + arm_access_memory(load, - reg_offset, reg, u8, yes, no_op); \ + break; \ + \ + case 0x78: \ + /* STR rd, [rn + reg_op] */ \ + arm_access_memory(store, + reg_offset, reg, u32, no, no_op); \ + break; \ + \ + case 0x79: \ + /* LDR rd, [rn + reg_op] */ \ + arm_access_memory(load, + reg_offset, reg, u32, no, no_op); \ + break; \ + \ + case 0x7A: \ + /* STR rd, [rn + reg_op]! */ \ + arm_access_memory(store, + reg_offset, reg, u32, yes, no_op); \ + break; \ + \ + case 0x7B: \ + /* LDR rd, [rn + reg_op]! */ \ + arm_access_memory(load, + reg_offset, reg, u32, yes, no_op); \ + break; \ + \ + case 0x7C: \ + /* STRB rd, [rn + reg_op] */ \ + arm_access_memory(store, + reg_offset, reg, u8, no, no_op); \ + break; \ + \ + case 0x7D: \ + /* LDRB rd, [rn + reg_op] */ \ + arm_access_memory(load, + reg_offset, reg, u8, no, no_op); \ + break; \ + \ + case 0x7E: \ + /* STRB rd, [rn + reg_op]! */ \ + arm_access_memory(store, + reg_offset, reg, u8, yes, no_op); \ + break; \ + \ + case 0x7F: \ + /* LDRBT rd, [rn + reg_op]! */ \ + arm_access_memory(load, + reg_offset, reg, u8, yes, no_op); \ + break; \ + \ + case 0x80: \ + /* STMDA rn, rlist */ \ + arm_block_memory(store, down_a, no, no); \ + break; \ + \ + case 0x81: \ + /* LDMDA rn, rlist */ \ + arm_block_memory(load, down_a, no, no); \ + break; \ + \ + case 0x82: \ + /* STMDA rn!, rlist */ \ + arm_block_memory(store, down_a, down, no); \ + break; \ + \ + case 0x83: \ + /* LDMDA rn!, rlist */ \ + arm_block_memory(load, down_a, down, no); \ + break; \ + \ + case 0x84: \ + /* STMDA rn, rlist^ */ \ + arm_block_memory(store, down_a, no, yes); \ + break; \ + \ + case 0x85: \ + /* LDMDA rn, rlist^ */ \ + arm_block_memory(load, down_a, no, yes); \ + break; \ + \ + case 0x86: \ + /* STMDA rn!, rlist^ */ \ + arm_block_memory(store, down_a, down, yes); \ + break; \ + \ + case 0x87: \ + /* LDMDA rn!, rlist^ */ \ + arm_block_memory(load, down_a, down, yes); \ + break; \ + \ + case 0x88: \ + /* STMIA rn, rlist */ \ + arm_block_memory(store, no, no, no); \ + break; \ + \ + case 0x89: \ + /* LDMIA rn, rlist */ \ + arm_block_memory(load, no, no, no); \ + break; \ + \ + case 0x8A: \ + /* STMIA rn!, rlist */ \ + arm_block_memory(store, no, up, no); \ + break; \ + \ + case 0x8B: \ + /* LDMIA rn!, rlist */ \ + arm_block_memory(load, no, up, no); \ + break; \ + \ + case 0x8C: \ + /* STMIA rn, rlist^ */ \ + arm_block_memory(store, no, no, yes); \ + break; \ + \ + case 0x8D: \ + /* LDMIA rn, rlist^ */ \ + arm_block_memory(load, no, no, yes); \ + break; \ + \ + case 0x8E: \ + /* STMIA rn!, rlist^ */ \ + arm_block_memory(store, no, up, yes); \ + break; \ + \ + case 0x8F: \ + /* LDMIA rn!, rlist^ */ \ + arm_block_memory(load, no, up, yes); \ + break; \ + \ + case 0x90: \ + /* STMDB rn, rlist */ \ + arm_block_memory(store, down_b, no, no); \ + break; \ + \ + case 0x91: \ + /* LDMDB rn, rlist */ \ + arm_block_memory(load, down_b, no, no); \ + break; \ + \ + case 0x92: \ + /* STMDB rn!, rlist */ \ + arm_block_memory(store, down_b, down, no); \ + break; \ + \ + case 0x93: \ + /* LDMDB rn!, rlist */ \ + arm_block_memory(load, down_b, down, no); \ + break; \ + \ + case 0x94: \ + /* STMDB rn, rlist^ */ \ + arm_block_memory(store, down_b, no, yes); \ + break; \ + \ + case 0x95: \ + /* LDMDB rn, rlist^ */ \ + arm_block_memory(load, down_b, no, yes); \ + break; \ + \ + case 0x96: \ + /* STMDB rn!, rlist^ */ \ + arm_block_memory(store, down_b, down, yes); \ + break; \ + \ + case 0x97: \ + /* LDMDB rn!, rlist^ */ \ + arm_block_memory(load, down_b, down, yes); \ + break; \ + \ + case 0x98: \ + /* STMIB rn, rlist */ \ + arm_block_memory(store, up, no, no); \ + break; \ + \ + case 0x99: \ + /* LDMIB rn, rlist */ \ + arm_block_memory(load, up, no, no); \ + break; \ + \ + case 0x9A: \ + /* STMIB rn!, rlist */ \ + arm_block_memory(store, up, up, no); \ + break; \ + \ + case 0x9B: \ + /* LDMIB rn!, rlist */ \ + arm_block_memory(load, up, up, no); \ + break; \ + \ + case 0x9C: \ + /* STMIB rn, rlist^ */ \ + arm_block_memory(store, up, no, yes); \ + break; \ + \ + case 0x9D: \ + /* LDMIB rn, rlist^ */ \ + arm_block_memory(load, up, no, yes); \ + break; \ + \ + case 0x9E: \ + /* STMIB rn!, rlist^ */ \ + arm_block_memory(store, up, up, yes); \ + break; \ + \ + case 0x9F: \ + /* LDMIB rn!, rlist^ */ \ + arm_block_memory(load, up, up, yes); \ + break; \ + \ + case 0xA0: \ + case 0xA1: \ + case 0xA2: \ + case 0xA3: \ + case 0xA4: \ + case 0xA5: \ + case 0xA6: \ + case 0xA7: \ + case 0xA8: \ + case 0xA9: \ + case 0xAA: \ + case 0xAB: \ + case 0xAC: \ + case 0xAD: \ + case 0xAE: \ + case 0xAF: \ + { \ + /* B offset */ \ + arm_decode_branch(); \ + arm_pc_offset_update(offset + 8); \ + break; \ + } \ + \ + case 0xB0 ... 0xBF: \ + { \ + /* BL offset */ \ + arm_decode_branch(); \ + reg[REG_LR] = pc + 4; \ + arm_pc_offset_update(offset + 8); \ + break; \ + } \ + \ + case 0xC0 ... 0xEF: \ + /* coprocessor instructions, reserved on GBA */ \ + break; \ + \ + case 0xF0 ... 0xFF: \ + { \ + /* SWI comment */ \ + u32 swi_comment = opcode & 0x00FFFFFF; \ + \ + switch(swi_comment >> 16) \ + { \ + /* Jump to BIOS SWI handler */ \ + default: \ + reg_mode[MODE_SUPERVISOR][6] = pc + 4; \ + collapse_flags(); \ + spsr[MODE_SUPERVISOR] = reg[REG_CPSR]; \ + reg[REG_PC] = 0x00000008; \ + arm_update_pc(); \ + reg[REG_CPSR] = (reg[REG_CPSR] & ~0x1F) | 0x13; \ + set_cpu_mode(MODE_SUPERVISOR); \ + break; \ + } \ + break; \ + } \ + } \ + \ + skip_instruction: \ + +#define execute_thumb_instruction() \ + using_instruction(thumb); \ + check_pc_region(); \ + pc &= ~0x01; \ + opcode = address16(pc_address_block, (pc & 0x7FFF)); \ + \ + switch((opcode >> 8) & 0xFF) \ + { \ + case 0x00 ... 0x07: \ + /* LSL rd, rs, offset */ \ + thumb_shift(shift, lsl, imm); \ + break; \ + \ + case 0x08 ... 0x0F: \ + /* LSR rd, rs, offset */ \ + thumb_shift(shift, lsr, imm); \ + break; \ + \ + case 0x10 ... 0x17: \ + /* ASR rd, rs, offset */ \ + thumb_shift(shift, asr, imm); \ + break; \ + \ + case 0x18 ... 0x19: \ + /* ADD rd, rs, rn */ \ + thumb_add(add_sub, rd, reg[rs], reg[rn]); \ + break; \ + \ + case 0x1A ... 0x1B: \ + /* SUB rd, rs, rn */ \ + thumb_sub(add_sub, rd, reg[rs], reg[rn]); \ + break; \ + \ + case 0x1C ... 0x1D: \ + /* ADD rd, rs, imm */ \ + thumb_add(add_sub_imm, rd, reg[rs], imm); \ + break; \ + \ + case 0x1E ... 0x1F: \ + /* SUB rd, rs, imm */ \ + thumb_sub(add_sub_imm, rd, reg[rs], imm); \ + break; \ + \ + case 0x20: \ + /* MOV r0, imm */ \ + thumb_logic(imm, 0, imm); \ + break; \ + \ + case 0x21: \ + /* MOV r1, imm */ \ + thumb_logic(imm, 1, imm); \ + break; \ + \ + case 0x22: \ + /* MOV r2, imm */ \ + thumb_logic(imm, 2, imm); \ + break; \ + \ + case 0x23: \ + /* MOV r3, imm */ \ + thumb_logic(imm, 3, imm); \ + break; \ + \ + case 0x24: \ + /* MOV r4, imm */ \ + thumb_logic(imm, 4, imm); \ + break; \ + \ + case 0x25: \ + /* MOV r5, imm */ \ + thumb_logic(imm, 5, imm); \ + break; \ + \ + case 0x26: \ + /* MOV r6, imm */ \ + thumb_logic(imm, 6, imm); \ + break; \ + \ + case 0x27: \ + /* MOV r7, imm */ \ + thumb_logic(imm, 7, imm); \ + break; \ + \ + case 0x28: \ + /* CMP r0, imm */ \ + thumb_test_sub(imm, reg[0], imm); \ + break; \ + \ + case 0x29: \ + /* CMP r1, imm */ \ + thumb_test_sub(imm, reg[1], imm); \ + break; \ + \ + case 0x2A: \ + /* CMP r2, imm */ \ + thumb_test_sub(imm, reg[2], imm); \ + break; \ + \ + case 0x2B: \ + /* CMP r3, imm */ \ + thumb_test_sub(imm, reg[3], imm); \ + break; \ + \ + case 0x2C: \ + /* CMP r4, imm */ \ + thumb_test_sub(imm, reg[4], imm); \ + break; \ + \ + case 0x2D: \ + /* CMP r5, imm */ \ + thumb_test_sub(imm, reg[5], imm); \ + break; \ + \ + case 0x2E: \ + /* CMP r6, imm */ \ + thumb_test_sub(imm, reg[6], imm); \ + break; \ + \ + case 0x2F: \ + /* CMP r7, imm */ \ + thumb_test_sub(imm, reg[7], imm); \ + break; \ + \ + case 0x30: \ + /* ADD r0, imm */ \ + thumb_add(imm, 0, reg[0], imm); \ + break; \ + \ + case 0x31: \ + /* ADD r1, imm */ \ + thumb_add(imm, 1, reg[1], imm); \ + break; \ + \ + case 0x32: \ + /* ADD r2, imm */ \ + thumb_add(imm, 2, reg[2], imm); \ + break; \ + \ + case 0x33: \ + /* ADD r3, imm */ \ + thumb_add(imm, 3, reg[3], imm); \ + break; \ + \ + case 0x34: \ + /* ADD r4, imm */ \ + thumb_add(imm, 4, reg[4], imm); \ + break; \ + \ + case 0x35: \ + /* ADD r5, imm */ \ + thumb_add(imm, 5, reg[5], imm); \ + break; \ + \ + case 0x36: \ + /* ADD r6, imm */ \ + thumb_add(imm, 6, reg[6], imm); \ + break; \ + \ + case 0x37: \ + /* ADD r7, imm */ \ + thumb_add(imm, 7, reg[7], imm); \ + break; \ + \ + case 0x38: \ + /* SUB r0, imm */ \ + thumb_sub(imm, 0, reg[0], imm); \ + break; \ + \ + case 0x39: \ + /* SUB r1, imm */ \ + thumb_sub(imm, 1, reg[1], imm); \ + break; \ + \ + case 0x3A: \ + /* SUB r2, imm */ \ + thumb_sub(imm, 2, reg[2], imm); \ + break; \ + \ + case 0x3B: \ + /* SUB r3, imm */ \ + thumb_sub(imm, 3, reg[3], imm); \ + break; \ + \ + case 0x3C: \ + /* SUB r4, imm */ \ + thumb_sub(imm, 4, reg[4], imm); \ + break; \ + \ + case 0x3D: \ + /* SUB r5, imm */ \ + thumb_sub(imm, 5, reg[5], imm); \ + break; \ + \ + case 0x3E: \ + /* SUB r6, imm */ \ + thumb_sub(imm, 6, reg[6], imm); \ + break; \ + \ + case 0x3F: \ + /* SUB r7, imm */ \ + thumb_sub(imm, 7, reg[7], imm); \ + break; \ + \ + case 0x40: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* AND rd, rs */ \ + thumb_logic(alu_op, rd, reg[rd] & reg[rs]); \ + break; \ + \ + case 0x01: \ + /* EOR rd, rs */ \ + thumb_logic(alu_op, rd, reg[rd] ^ reg[rs]); \ + break; \ + \ + case 0x02: \ + /* LSL rd, rs */ \ + thumb_shift(alu_op, lsl, reg); \ + break; \ + \ + case 0x03: \ + /* LSR rd, rs */ \ + thumb_shift(alu_op, lsr, reg); \ + break; \ + } \ + break; \ + \ + case 0x41: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* ASR rd, rs */ \ + thumb_shift(alu_op, asr, reg); \ + break; \ + \ + case 0x01: \ + /* ADC rd, rs */ \ + thumb_add(alu_op, rd, reg[rd] + reg[rs], c_flag); \ + break; \ + \ + case 0x02: \ + /* SBC rd, rs */ \ + thumb_sub(alu_op, rd, reg[rd] - reg[rs], (c_flag ^ 1)); \ + break; \ + \ + case 0x03: \ + /* ROR rd, rs */ \ + thumb_shift(alu_op, ror, reg); \ + break; \ + } \ + break; \ + \ + case 0x42: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* TST rd, rs */ \ + thumb_test_logic(alu_op, reg[rd] & reg[rs]); \ + break; \ + \ + case 0x01: \ + /* NEG rd, rs */ \ + thumb_sub(alu_op, rd, 0, reg[rs]); \ + break; \ + \ + case 0x02: \ + /* CMP rd, rs */ \ + thumb_test_sub(alu_op, reg[rd], reg[rs]); \ + break; \ + \ + case 0x03: \ + /* CMN rd, rs */ \ + thumb_test_add(alu_op, reg[rd], reg[rs]); \ + break; \ + } \ + break; \ + \ + case 0x43: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* ORR rd, rs */ \ + thumb_logic(alu_op, rd, reg[rd] | reg[rs]); \ + break; \ + \ + case 0x01: \ + /* MUL rd, rs */ \ + thumb_logic(alu_op, rd, reg[rd] * reg[rs]); \ + break; \ + \ + case 0x02: \ + /* BIC rd, rs */ \ + thumb_logic(alu_op, rd, reg[rd] & (~reg[rs])); \ + break; \ + \ + case 0x03: \ + /* MVN rd, rs */ \ + thumb_logic(alu_op, rd, ~reg[rs]); \ + break; \ + } \ + break; \ + \ + case 0x44: \ + /* ADD rd, rs */ \ + thumb_hireg_op(reg[rd] + reg[rs]); \ + break; \ + \ + case 0x45: \ + /* CMP rd, rs */ \ + { \ + thumb_pc_offset(4); \ + thumb_decode_hireg_op(); \ + u32 _sa = reg[rd]; \ + u32 _sb = reg[rs]; \ + u32 dest = _sa - _sb; \ + thumb_pc_offset(-2); \ + calculate_flags_sub(dest, _sa, _sb); \ + } \ + break; \ + \ + case 0x46: \ + /* MOV rd, rs */ \ + thumb_hireg_op(reg[rs]); \ + break; \ + \ + case 0x47: \ + /* BX rs */ \ + { \ + thumb_decode_hireg_op(); \ + u32 src; \ + thumb_pc_offset(4); \ + src = reg[rs]; \ + if(src & 0x01) \ + { \ + src -= 1; \ + thumb_pc_offset_update_direct(src); \ + } \ + else \ + { \ + /* Switch to ARM mode */ \ + thumb_pc_offset_update_direct(src); \ + reg[REG_CPSR] &= ~0x20; \ + collapse_flags(); \ + goto arm_loop; \ + } \ + } \ + break; \ + \ + case 0x48: \ + /* LDR r0, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[0], u32); \ + break; \ + \ + case 0x49: \ + /* LDR r1, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[1], u32); \ + break; \ + \ + case 0x4A: \ + /* LDR r2, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[2], u32); \ + break; \ + \ + case 0x4B: \ + /* LDR r3, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[3], u32); \ + break; \ + \ + case 0x4C: \ + /* LDR r4, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[4], u32); \ + break; \ + \ + case 0x4D: \ + /* LDR r5, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[5], u32); \ + break; \ + \ + case 0x4E: \ + /* LDR r6, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[6], u32); \ + break; \ + \ + case 0x4F: \ + /* LDR r7, [pc + imm] */ \ + thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[7], u32); \ + break; \ + \ + case 0x50 ... 0x51: \ + /* STR rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u32); \ + break; \ + \ + case 0x52 ... 0x53: \ + /* STRH rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u16); \ + break; \ + \ + case 0x54 ... 0x55: \ + /* STRB rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u8); \ + break; \ + \ + case 0x56 ... 0x57: \ + /* LDSB rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], s8); \ + break; \ + \ + case 0x58 ... 0x59: \ + /* LDR rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u32); \ + break; \ + \ + case 0x5A ... 0x5B: \ + /* LDRH rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u16); \ + break; \ + \ + case 0x5C ... 0x5D: \ + /* LDRB rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u8); \ + break; \ + \ + case 0x5E ... 0x5F: \ + /* LDSH rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], s16); \ + break; \ + \ + case 0x60 ... 0x67: \ + /* STR rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, reg[rb] + (imm * 4), reg[rd], u32); \ + break; \ + \ + case 0x68 ... 0x6F: \ + /* LDR rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, reg[rb] + (imm * 4), reg[rd], u32); \ + break; \ + \ + case 0x70 ... 0x77: \ + /* STRB rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, reg[rb] + imm, reg[rd], u8); \ + break; \ + \ + case 0x78 ... 0x7F: \ + /* LDRB rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, reg[rb] + imm, reg[rd], u8); \ + break; \ + \ + case 0x80 ... 0x87: \ + /* STRH rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, reg[rb] + (imm * 2), reg[rd], u16); \ + break; \ + \ + case 0x88 ... 0x8F: \ + /* LDRH rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, reg[rb] + (imm * 2), reg[rd], u16); \ + break; \ + \ + case 0x90: \ + /* STR r0, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[0], u32); \ + break; \ + \ + case 0x91: \ + /* STR r1, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[1], u32); \ + break; \ + \ + case 0x92: \ + /* STR r2, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[2], u32); \ + break; \ + \ + case 0x93: \ + /* STR r3, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[3], u32); \ + break; \ + \ + case 0x94: \ + /* STR r4, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[4], u32); \ + break; \ + \ + case 0x95: \ + /* STR r5, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[5], u32); \ + break; \ + \ + case 0x96: \ + /* STR r6, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[6], u32); \ + break; \ + \ + case 0x97: \ + /* STR r7, [sp + imm] */ \ + thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[7], u32); \ + break; \ + \ + case 0x98: \ + /* LDR r0, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[0], u32); \ + break; \ + \ + case 0x99: \ + /* LDR r1, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[1], u32); \ + break; \ + \ + case 0x9A: \ + /* LDR r2, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[2], u32); \ + break; \ + \ + case 0x9B: \ + /* LDR r3, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[3], u32); \ + break; \ + \ + case 0x9C: \ + /* LDR r4, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[4], u32); \ + break; \ + \ + case 0x9D: \ + /* LDR r5, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[5], u32); \ + break; \ + \ + case 0x9E: \ + /* LDR r6, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[6], u32); \ + break; \ + \ + case 0x9F: \ + /* LDR r7, [sp + imm] */ \ + thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[7], u32); \ + break; \ + \ + case 0xA0: \ + /* ADD r0, pc, +imm */ \ + thumb_add_noflags(imm, 0, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA1: \ + /* ADD r1, pc, +imm */ \ + thumb_add_noflags(imm, 1, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA2: \ + /* ADD r2, pc, +imm */ \ + thumb_add_noflags(imm, 2, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA3: \ + /* ADD r3, pc, +imm */ \ + thumb_add_noflags(imm, 3, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA4: \ + /* ADD r4, pc, +imm */ \ + thumb_add_noflags(imm, 4, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA5: \ + /* ADD r5, pc, +imm */ \ + thumb_add_noflags(imm, 5, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA6: \ + /* ADD r6, pc, +imm */ \ + thumb_add_noflags(imm, 6, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA7: \ + /* ADD r7, pc, +imm */ \ + thumb_add_noflags(imm, 7, (pc & ~2) + 4, (imm * 4)); \ + break; \ + \ + case 0xA8: \ + /* ADD r0, sp, +imm */ \ + thumb_add_noflags(imm, 0, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xA9: \ + /* ADD r1, sp, +imm */ \ + thumb_add_noflags(imm, 1, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAA: \ + /* ADD r2, sp, +imm */ \ + thumb_add_noflags(imm, 2, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAB: \ + /* ADD r3, sp, +imm */ \ + thumb_add_noflags(imm, 3, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAC: \ + /* ADD r4, sp, +imm */ \ + thumb_add_noflags(imm, 4, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAD: \ + /* ADD r5, sp, +imm */ \ + thumb_add_noflags(imm, 5, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAE: \ + /* ADD r6, sp, +imm */ \ + thumb_add_noflags(imm, 6, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xAF: \ + /* ADD r7, sp, +imm */ \ + thumb_add_noflags(imm, 7, reg[REG_SP], (imm * 4)); \ + break; \ + \ + case 0xB0 ... 0xB3: \ + if((opcode >> 7) & 0x01) \ + { \ + /* ADD sp, -imm */ \ + thumb_add_noflags(add_sp, 13, reg[REG_SP], -(imm * 4)); \ + } \ + else \ + { \ + /* ADD sp, +imm */ \ + thumb_add_noflags(add_sp, 13, reg[REG_SP], (imm * 4)); \ + } \ + break; \ + \ + case 0xB4: \ + /* PUSH rlist */ \ + thumb_block_memory(store, down, no_op, 13); \ + break; \ + \ + case 0xB5: \ + /* PUSH rlist, lr */ \ + thumb_block_memory(store, push_lr, push_lr, 13); \ + break; \ + \ + case 0xBC: \ + /* POP rlist */ \ + thumb_block_memory(load, no_op, up, 13); \ + break; \ + \ + case 0xBD: \ + /* POP rlist, pc */ \ + thumb_block_memory(load, no_op, pop_pc, 13); \ + break; \ + \ + case 0xC0: \ + /* STMIA r0!, rlist */ \ + thumb_block_memory(store, no_op, up, 0); \ + break; \ + \ + case 0xC1: \ + /* STMIA r1!, rlist */ \ + thumb_block_memory(store, no_op, up, 1); \ + break; \ + \ + case 0xC2: \ + /* STMIA r2!, rlist */ \ + thumb_block_memory(store, no_op, up, 2); \ + break; \ + \ + case 0xC3: \ + /* STMIA r3!, rlist */ \ + thumb_block_memory(store, no_op, up, 3); \ + break; \ + \ + case 0xC4: \ + /* STMIA r4!, rlist */ \ + thumb_block_memory(store, no_op, up, 4); \ + break; \ + \ + case 0xC5: \ + /* STMIA r5!, rlist */ \ + thumb_block_memory(store, no_op, up, 5); \ + break; \ + \ + case 0xC6: \ + /* STMIA r6!, rlist */ \ + thumb_block_memory(store, no_op, up, 6); \ + break; \ + \ + case 0xC7: \ + /* STMIA r7!, rlist */ \ + thumb_block_memory(store, no_op, up, 7); \ + break; \ + \ + case 0xC8: \ + /* LDMIA r0!, rlist */ \ + thumb_block_memory(load, no_op, up, 0); \ + break; \ + \ + case 0xC9: \ + /* LDMIA r1!, rlist */ \ + thumb_block_memory(load, no_op, up, 1); \ + break; \ + \ + case 0xCA: \ + /* LDMIA r2!, rlist */ \ + thumb_block_memory(load, no_op, up, 2); \ + break; \ + \ + case 0xCB: \ + /* LDMIA r3!, rlist */ \ + thumb_block_memory(load, no_op, up, 3); \ + break; \ + \ + case 0xCC: \ + /* LDMIA r4!, rlist */ \ + thumb_block_memory(load, no_op, up, 4); \ + break; \ + \ + case 0xCD: \ + /* LDMIA r5!, rlist */ \ + thumb_block_memory(load, no_op, up, 5); \ + break; \ + \ + case 0xCE: \ + /* LDMIA r6!, rlist */ \ + thumb_block_memory(load, no_op, up, 6); \ + break; \ + \ + case 0xCF: \ + /* LDMIA r7!, rlist */ \ + thumb_block_memory(load, no_op, up, 7); \ + break; \ + \ + case 0xD0: \ + /* BEQ label */ \ + thumb_conditional_branch(z_flag == 1); \ + break; \ + \ + case 0xD1: \ + /* BNE label */ \ + thumb_conditional_branch(z_flag == 0); \ + break; \ + \ + case 0xD2: \ + /* BCS label */ \ + thumb_conditional_branch(c_flag == 1); \ + break; \ + \ + case 0xD3: \ + /* BCC label */ \ + thumb_conditional_branch(c_flag == 0); \ + break; \ + \ + case 0xD4: \ + /* BMI label */ \ + thumb_conditional_branch(n_flag == 1); \ + break; \ + \ + case 0xD5: \ + /* BPL label */ \ + thumb_conditional_branch(n_flag == 0); \ + break; \ + \ + case 0xD6: \ + /* BVS label */ \ + thumb_conditional_branch(v_flag == 1); \ + break; \ + \ + case 0xD7: \ + /* BVC label */ \ + thumb_conditional_branch(v_flag == 0); \ + break; \ + \ + case 0xD8: \ + /* BHI label */ \ + thumb_conditional_branch(c_flag & (z_flag ^ 1)); \ + break; \ + \ + case 0xD9: \ + /* BLS label */ \ + thumb_conditional_branch((c_flag == 0) | z_flag); \ + break; \ + \ + case 0xDA: \ + /* BGE label */ \ + thumb_conditional_branch(n_flag == v_flag); \ + break; \ + \ + case 0xDB: \ + /* BLT label */ \ + thumb_conditional_branch(n_flag != v_flag); \ + break; \ + \ + case 0xDC: \ + /* BGT label */ \ + thumb_conditional_branch((z_flag == 0) & (n_flag == v_flag)); \ + break; \ + \ + case 0xDD: \ + /* BLE label */ \ + thumb_conditional_branch(z_flag | (n_flag != v_flag)); \ + break; \ + \ + case 0xDF: \ + { \ + /* SWI comment */ \ + u32 swi_comment = opcode & 0xFF; \ + \ + switch(swi_comment) \ + { \ + default: \ + reg_mode[MODE_SUPERVISOR][6] = pc + 2; \ + spsr[MODE_SUPERVISOR] = reg[REG_CPSR]; \ + reg[REG_PC] = 0x00000008; \ + thumb_update_pc(); \ + reg[REG_CPSR] = (reg[REG_CPSR] & ~0x3F) | 0x13; \ + set_cpu_mode(MODE_SUPERVISOR); \ + collapse_flags(); \ + goto arm_loop; \ + } \ + break; \ + } \ + \ + case 0xE0 ... 0xE7: \ + { \ + /* B label */ \ + thumb_decode_branch(); \ + thumb_pc_offset_update(((s32)(offset << 21) >> 20) + 4); \ + break; \ + } \ + \ + case 0xF0 ... 0xF7: \ + { \ + /* (low word) BL label */ \ + thumb_decode_branch(); \ + reg[REG_LR] = pc + 4 + ((s32)(offset << 21) >> 9); \ + thumb_pc_offset(2); \ + break; \ + } \ + \ + case 0xF8 ... 0xFF: \ + { \ + /* (high word) BL label */ \ + thumb_decode_branch(); \ + u32 lr = (pc + 2) | 0x01; \ + pc = reg[REG_LR] + (offset * 2); \ + reg[REG_LR] = lr; \ + reg[REG_PC] = pc; \ + break; \ + } \ + } \ + +void print_arm_registers() +{ + u32 i, i2, i3; + + for(i = 0, i3 = 0; i < 4; i++) + { + debug_screen_printf(" "); + for(i2 = 0; i2 < 4; i2++, i3++) + { + debug_screen_printf("R%02d %08x ", i3, reg[i3]); + } + debug_screen_newline(1); + } +} + +void print_thumb_instruction() +{ + debug_screen_printf("Thumb instruction at PC: %04x", + read_memory16(reg[REG_PC])); + debug_screen_newline(1); +} + +void print_arm_instruction() +{ + debug_screen_printf("ARM instruction at PC: %08x", + read_memory32(reg[REG_PC])); + debug_screen_newline(1); +} + +void print_flags() +{ + u32 cpsr = reg[REG_CPSR]; + debug_screen_newline(1); + debug_screen_printf( + " N: %d Z: %d C: %d V: %d CPSR: %08x SPSR: %08x mode: %s", + (cpsr >> 31) & 0x01, (cpsr >> 30) & 0x01, (cpsr >> 29) & 0x01, + (cpsr >> 28) & 0x01, cpsr, spsr[reg[CPU_MODE]], + cpu_mode_names[reg[CPU_MODE]]); + debug_screen_newline(2); +} + +const u32 stack_print_lines = 2; + +void print_stack() +{ + u32 i, i2, i3; + + debug_screen_printf("Stack:"); + debug_screen_newline(1); + + for(i = 0, i3 = reg[REG_SP]; i < stack_print_lines; i++) + { + for(i2 = 0; i2 < 5; i2++, i3 += 4) + { + debug_screen_printf(" %08x", read_memory32(i3)); + } + if(i != stack_print_lines) + debug_screen_newline(1); + } + + debug_screen_newline(1); +} + +u32 instruction_count = 0; + +u32 output_field = 0; +const u32 num_output_fields = 2; + +u32 last_instruction = 0; + +u32 in_interrupt = 0; + +u32 debug_on() +{ + current_debug_state = STEP; + debug_screen_start(); +} + +u32 debug_off(debug_state new_debug_state) +{ + current_debug_state = new_debug_state; + debug_screen_end(); +} + +u32 function_cc step_debug(u32 pc, u32 cycles) +{ + u32 thumb = 0; + + reg[REG_PC] = pc; + + if(reg[REG_CPSR] & 0x20) + thumb = 1; + + instruction_count++; + + switch(current_debug_state) + { + case PC_BREAKPOINT: + if(reg[REG_PC] == breakpoint_value) + debug_on(); + + break; + + case Z_BREAKPOINT: + if(reg[REG_Z_FLAG] == 1) + debug_on(); + + break; + + case VCOUNT_BREAKPOINT: + if(io_registers[REG_VCOUNT] == breakpoint_value) + debug_on(); + + break; + + case COUNTDOWN_BREAKPOINT: + if(breakpoint_value == 0) + debug_on(); + else + breakpoint_value--; + + break; + + case COUNTDOWN_BREAKPOINT_B: + if(breakpoint_value == instruction_count) + debug_on(); + + break; + + case COUNTDOWN_BREAKPOINT_C: + { + if(pc == 0x18) + in_interrupt++; + + if((breakpoint_value == 0) && (in_interrupt == 0)) + { + debug_on(); + } + else + + if(in_interrupt == 0) + breakpoint_value--; + + if(in_interrupt && (pc == 0x13c)) + in_interrupt--; + + break; + } + } + + if((current_debug_state == STEP) || + (current_debug_state == STEP_RUN)) + { + u32 key = 0; + + SDL_LockMutex(sound_mutex); + SDL_PauseAudio(1); + + if(output_field >= num_output_fields) + { + output_field = 0; + debug_screen_clear(); + } + + if(thumb) + print_thumb_instruction(cycles); + else + print_arm_instruction(cycles); + + print_arm_registers(); + print_flags(); + print_stack(); + + + printf("%x instructions in, VCOUNT %d, cycles remaining: %d \n", + instruction_count, io_registers[REG_VCOUNT], cycles); + + debug_screen_update(); + output_field++; + + if(current_debug_state != STEP_RUN) + { + +#ifdef STDIO_DEBUG + key = getchar(); +#else + + gui_action_type next_input = CURSOR_NONE; + while(next_input == CURSOR_NONE) + { + next_input = get_gui_input(); + + switch(next_input) + { + case CURSOR_BACK: + key = 'b'; + break; + + case CURSOR_UP: + key = 'r'; + break; + + case CURSOR_EXIT: + key = 'q'; + break; + + default: + key = 'n'; + break; + } + } +#endif + } + + switch(key) + { + case 'd': + dump_translation_cache(); + break; + + case 'z': + debug_off(Z_BREAKPOINT); + break; + +#ifdef STDIO_DEBUG + case 'x': + printf("break at PC (hex): "); + scanf("%08x", &breakpoint_value); + debug_off(PC_BREAKPOINT); + break; + + case 'c': + printf("break after N instructions (hex): "); + scanf("%08x", &breakpoint_value); + breakpoint_value -= 1; + debug_off(COUNTDOWN_BREAKPOINT); + break; + + case 'f': + printf("break after N instructions, skip in IRQ (hex): "); + scanf("%08x", &breakpoint_value); + breakpoint_value -= 1; + debug_off(COUNTDOWN_BREAKPOINT_C); + break; + + case 'g': + printf("break after N instructions (since start): "); + scanf("%d", &breakpoint_value); + debug_off(COUNTDOWN_BREAKPOINT_B); + break; + + case 'v': + printf("break at VCOUNT: "); + scanf("%d", &breakpoint_value); + debug_off(VCOUNT_BREAKPOINT); + break; +#endif + + case 's': + current_debug_state = STEP_RUN; + break; + + case 'r': + debug_off(RUN); + break; + + case 'b': + debug_off(PC_BREAKPOINT); + break; + + case 't': + global_cycles_per_instruction = 0; + debug_off(RUN); + break; + + case 'a': + { + u8 current_savestate_filename[512]; + u16 *current_screen = copy_screen(); + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + save_state(current_savestate_filename, current_screen); + free(current_screen); + break; + } + + case 'q': + quit(); + } + + SDL_PauseAudio(0); + SDL_UnlockMutex(sound_mutex); + } + + last_instruction = reg[REG_PC]; + + if(thumb) + reg[REG_PC] = pc + 2; + else + reg[REG_PC] = pc + 4; + + return 0; +} + +void set_cpu_mode(cpu_mode_type new_mode) +{ + u32 i; + cpu_mode_type cpu_mode = reg[CPU_MODE]; + + if(cpu_mode != new_mode) + { + if(new_mode == MODE_FIQ) + { + for(i = 8; i < 15; i++) + { + reg_mode[cpu_mode][i - 8] = reg[i]; + } + } + else + { + reg_mode[cpu_mode][5] = reg[REG_SP]; + reg_mode[cpu_mode][6] = reg[REG_LR]; + } + + if(cpu_mode == MODE_FIQ) + { + for(i = 8; i < 15; i++) + { + reg[i] = reg_mode[new_mode][i - 8]; + } + } + else + { + reg[REG_SP] = reg_mode[new_mode][5]; + reg[REG_LR] = reg_mode[new_mode][6]; + } + + reg[CPU_MODE] = new_mode; + } +} + +void raise_interrupt(irq_type irq_raised) +{ + // The specific IRQ must be enabled in IE, master IRQ enable must be on, + // and it must be on in the flags. + io_registers[REG_IF] |= irq_raised; + + if((io_registers[REG_IE] & irq_raised) && io_registers[REG_IME] && + ((reg[REG_CPSR] & 0x80) == 0)) + { + bios_read_protect = 0xe55ec002; + + // Interrupt handler in BIOS + reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4; + spsr[MODE_IRQ] = reg[REG_CPSR]; + reg[REG_CPSR] = 0xD2; + reg[REG_PC] = 0x00000018; + + bios_region_read_allow(); + + set_cpu_mode(MODE_IRQ); + reg[CPU_HALT_STATE] = CPU_ACTIVE; + reg[CHANGED_PC_STATUS] = 1; + } +} + +u32 execute_arm(u32 cycles) +{ + u32 pc = reg[REG_PC]; + u32 opcode; + u32 condition; + u32 n_flag, z_flag, c_flag, v_flag; + u32 pc_region = (pc >> 15); + u8 *pc_address_block = memory_map_read[pc_region]; + u32 new_pc_region; + s32 cycles_remaining; + u32 cycles_per_instruction = global_cycles_per_instruction; + cpu_alert_type cpu_alert; + + u32 old_pc; + + if(pc_address_block == NULL) + pc_address_block = load_gamepak_page(pc_region & 0x3FF); + + while(1) + { + cycles_remaining = cycles; + pc = reg[REG_PC]; + extract_flags(); + + if(reg[REG_CPSR] & 0x20) + goto thumb_loop; + + do + { + arm_loop: + + collapse_flags(); + step_debug(pc, cycles_remaining); + cycles_per_instruction = global_cycles_per_instruction; + + old_pc = pc; + execute_arm_instruction(); + cycles_remaining -= cycles_per_instruction; + } while(cycles_remaining > 0); + + collapse_flags(); + cycles = update_gba(); + continue; + + do + { + thumb_loop: + + collapse_flags(); + step_debug(pc, cycles_remaining); + + old_pc = pc; + execute_thumb_instruction(); + cycles_remaining -= cycles_per_instruction; + } while(cycles_remaining > 0); + + collapse_flags(); + cycles = update_gba(); + continue; + + alert: + + if(cpu_alert == CPU_ALERT_IRQ) + { + cycles = cycles_remaining; + } + else + { + collapse_flags(); + + while(reg[CPU_HALT_STATE] != CPU_ACTIVE) + { + cycles = update_gba(); + } + } + } +} + +void init_cpu() +{ + u32 i; + + for(i = 0; i < 16; i++) + { + reg[i] = 0; + } + + reg[REG_SP] = 0x03007F00; + reg[REG_PC] = 0x08000000; + reg[REG_CPSR] = 0x0000001F; + reg[CPU_HALT_STATE] = CPU_ACTIVE; + reg[CPU_MODE] = MODE_USER; + reg[CHANGED_PC_STATUS] = 0; + + reg_mode[MODE_USER][5] = 0x03007F00; + reg_mode[MODE_IRQ][5] = 0x03007FA0; + reg_mode[MODE_FIQ][5] = 0x03007FA0; + reg_mode[MODE_SUPERVISOR][5] = 0x03007FE0; +} + +void move_reg(u32 *new_reg) +{ + u32 i; + + for(i = 0; i < 32; i++) + { + new_reg[i] = reg[i]; + } + + reg = new_reg; +} + + +#define cpu_savestate_builder(type) \ +void cpu_##type##_savestate(file_tag_type savestate_file) \ +{ \ + file_##type(savestate_file, reg, 0x100); \ + file_##type##_array(savestate_file, spsr); \ + file_##type##_array(savestate_file, reg_mode); \ +} \ + +cpu_savestate_builder(read); +cpu_savestate_builder(write_mem); + diff --git a/cpu.h b/cpu.h new file mode 100644 index 0000000..bebe773 --- /dev/null +++ b/cpu.h @@ -0,0 +1,210 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_H +#define CPU_H + +// System mode and user mode are represented as the same here + +typedef enum +{ + MODE_USER, + MODE_IRQ, + MODE_FIQ, + MODE_SUPERVISOR, + MODE_ABORT, + MODE_UNDEFINED, + MODE_INVALID +} cpu_mode_type; + +typedef enum +{ + CPU_ALERT_NONE, + CPU_ALERT_HALT, + CPU_ALERT_SMC, + CPU_ALERT_IRQ +} cpu_alert_type; + +typedef enum +{ + CPU_ACTIVE, + CPU_HALT, + CPU_STOP +} cpu_halt_type; + +typedef enum +{ + IRQ_NONE = 0x0000, + IRQ_VBLANK = 0x0001, + IRQ_HBLANK = 0x0002, + IRQ_VCOUNT = 0x0004, + IRQ_TIMER0 = 0x0008, + IRQ_TIMER1 = 0x0010, + IRQ_TIMER2 = 0x0020, + IRQ_TIMER3 = 0x0040, + IRQ_SERIAL = 0x0080, + IRQ_DMA0 = 0x0100, + IRQ_DMA1 = 0x0200, + IRQ_DMA2 = 0x0400, + IRQ_DMA3 = 0x0800, + IRQ_KEYPAD = 0x1000, + IRQ_GAMEPAK = 0x2000, +} irq_type; + +typedef enum +{ + REG_SP = 13, + REG_LR = 14, + REG_PC = 15, + REG_N_FLAG = 16, + REG_Z_FLAG = 17, + REG_C_FLAG = 18, + REG_V_FLAG = 19, + REG_CPSR = 20, + REG_SAVE = 21, + REG_SAVE2 = 22, + REG_SAVE3 = 23, + CPU_MODE = 29, + CPU_HALT_STATE = 30, + CHANGED_PC_STATUS = 31 +} ext_reg_numbers; + +typedef enum +{ + STEP, + PC_BREAKPOINT, + VCOUNT_BREAKPOINT, + Z_BREAKPOINT, + COUNTDOWN_BREAKPOINT, + COUNTDOWN_BREAKPOINT_B, + COUNTDOWN_BREAKPOINT_C, + STEP_RUN, + RUN +} debug_state; + +typedef enum +{ + TRANSLATION_REGION_RAM, + TRANSLATION_REGION_ROM, + TRANSLATION_REGION_BIOS +} translation_region_type; + +extern debug_state current_debug_state; +extern u32 instruction_count; +extern u32 last_instruction; + +u32 function_cc step_debug(u32 pc, u32 cycles); +u32 execute_arm(u32 cycles); +void raise_interrupt(irq_type irq_raised); + +u32 function_cc execute_load_u8(u32 address); +u32 function_cc execute_load_u16(u32 address); +u32 function_cc execute_load_u32(u32 address); +u32 function_cc execute_load_s8(u32 address); +u32 function_cc execute_load_s16(u32 address); +void function_cc execute_store_u8(u32 address, u32 source); +void function_cc execute_store_u16(u32 address, u32 source); +void function_cc execute_store_u32(u32 address, u32 source); +u32 function_cc execute_arm_translate(u32 cycles); +void init_translater(); +void cpu_write_mem_savestate(file_tag_type savestate_file); +void cpu_read_savestate(file_tag_type savestate_file); + +u8 function_cc *block_lookup_address_arm(u32 pc); +u8 function_cc *block_lookup_address_thumb(u32 pc); +s32 translate_block_arm(u32 pc, translation_region_type translation_region, + u32 smc_enable); +s32 translate_block_thumb(u32 pc, translation_region_type translation_region, + u32 smc_enable); + +#ifdef GP2X_BUILD +#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5) +#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2) +#define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128 * 2) +#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32) + +#else + +#define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4) +#define RAM_TRANSLATION_CACHE_SIZE (1024 * 384) +#define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128) +#define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024) + +#endif + +extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]; +extern u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]; +extern u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]; +extern u8 *rom_translation_ptr; +extern u8 *ram_translation_ptr; +extern u8 *bios_translation_ptr; + +#define MAX_TRANSLATION_GATES 8 + +extern u32 idle_loop_target_pc; +extern u32 force_pc_update_target; +extern u32 iwram_stack_optimize; +extern u32 allow_smc_ram_u8; +extern u32 allow_smc_ram_u16; +extern u32 allow_smc_ram_u32; +extern u32 direct_map_vram; +extern u32 translation_gate_targets; +extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES]; + +extern u32 in_interrupt; + +#define ROM_BRANCH_HASH_SIZE (1024 * 64) + +/* EDIT: Shouldn't this be extern ?! */ +extern u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE]; + +void flush_translation_cache_rom(); +void flush_translation_cache_ram(); +void flush_translation_cache_bios(); +void dump_translation_cache(); + +extern u32 reg_mode[7][7]; +extern u32 spsr[6]; + +extern u32 cpu_modes[32]; +extern const u32 psr_masks[16]; + +extern u32 breakpoint_value; + +extern u32 memory_region_access_read_u8[16]; +extern u32 memory_region_access_read_s8[16]; +extern u32 memory_region_access_read_u16[16]; +extern u32 memory_region_access_read_s16[16]; +extern u32 memory_region_access_read_u32[16]; +extern u32 memory_region_access_write_u8[16]; +extern u32 memory_region_access_write_u16[16]; +extern u32 memory_region_access_write_u32[16]; +extern u32 memory_reads_u8; +extern u32 memory_reads_s8; +extern u32 memory_reads_u16; +extern u32 memory_reads_s16; +extern u32 memory_reads_u32; +extern u32 memory_writes_u8; +extern u32 memory_writes_u16; +extern u32 memory_writes_u32; + +void init_cpu(); +void move_reg(); + +#endif diff --git a/cpu_threaded.c b/cpu_threaded.c new file mode 100644 index 0000000..a753c17 --- /dev/null +++ b/cpu_threaded.c @@ -0,0 +1,3508 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Not-so-important todo: +// - stm reglist writeback when base is in the list needs adjustment +// - block memory needs psr swapping and user mode reg swapping + +#include +#include "common.h" + +u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]; +u8 *rom_translation_ptr = rom_translation_cache; + +u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]; +u8 *ram_translation_ptr = ram_translation_cache; +u32 iwram_code_min = 0xFFFFFFFF; +u32 iwram_code_max = 0xFFFFFFFF; +u32 ewram_code_min = 0xFFFFFFFF; +u32 ewram_code_max = 0xFFFFFFFF; + +u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]; +u8 *bios_translation_ptr = bios_translation_cache; + +u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE]; + +// Default +u32 idle_loop_target_pc = 0xFFFFFFFF; +u32 force_pc_update_target = 0xFFFFFFFF; +u32 translation_gate_target_pc[MAX_TRANSLATION_GATES]; +u32 translation_gate_targets = 0; +u32 iwram_stack_optimize = 1; +u32 allow_smc_ram_u8 = 1; +u32 allow_smc_ram_u16 = 1; +u32 allow_smc_ram_u32 = 1; + +typedef struct +{ + u8 *block_offset; + u16 flag_data; + u8 condition; + u8 update_cycles; +} block_data_type; + +typedef struct +{ + u32 branch_target; + u8 *branch_source; +} block_exit_type; + +extern u8 bit_count[256]; + +#define arm_decode_data_proc_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_data_proc_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm = opcode & 0xFF; \ + u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \ + +#define arm_decode_psr_reg() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_psr_imm() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm = opcode & 0xFF; \ + u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \ + +#define arm_decode_branchx() \ + u32 rn = opcode & 0x0F \ + +#define arm_decode_multiply() \ + u32 rd = (opcode >> 16) & 0x0F; \ + u32 rn = (opcode >> 12) & 0x0F; \ + u32 rs = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_multiply_long() \ + u32 rdhi = (opcode >> 16) & 0x0F; \ + u32 rdlo = (opcode >> 12) & 0x0F; \ + u32 rs = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_swap() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_half_trans_r() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_half_trans_of() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F) \ + +#define arm_decode_data_trans_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = opcode & 0x0FFF \ + +#define arm_decode_data_trans_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_block_trans() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 reg_list = opcode & 0xFFFF \ + +#define arm_decode_branch() \ + s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \ + +#define thumb_decode_shift() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sub() \ + u32 rn = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sub_imm() \ + u32 imm = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_imm() \ + u32 imm = opcode & 0xFF \ + +#define thumb_decode_alu_op() \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_hireg_op() \ + u32 rs = (opcode >> 3) & 0x0F; \ + u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07) \ + +#define thumb_decode_mem_reg() \ + u32 ro = (opcode >> 6) & 0x07; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_mem_imm() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sp() \ + u32 imm = opcode & 0x7F \ + +#define thumb_decode_rlist() \ + u32 reg_list = opcode & 0xFF \ + +#define thumb_decode_branch_cond() \ + s32 offset = (s8)(opcode & 0xFF) \ + +#define thumb_decode_swi() \ + u32 comment = opcode & 0xFF \ + +#define thumb_decode_branch() \ + u32 offset = opcode & 0x07FF \ + + +#ifdef PSP_BUILD + +#include "psp/mips_emit.h" + +#elif defined(GP2X_BUILD) + +#include "gp2x/arm_emit.h" + +#elif defined(GIZ_BUILD) + +#include "giz/arm_emit.h" + +#else + +#include "x86/x86_emit.h" + +#endif + + +#define check_pc_region(pc) \ + new_pc_region = (pc >> 15); \ + if(new_pc_region != pc_region) \ + { \ + pc_region = new_pc_region; \ + pc_address_block = memory_map_read[new_pc_region]; \ + \ + if(pc_address_block == NULL) \ + pc_address_block = load_gamepak_page(pc_region & 0x3FF); \ + } \ + +#define translate_arm_instruction() \ + check_pc_region(pc); \ + opcode = address32(pc_address_block, (pc & 0x7FFF)); \ + condition = block_data[block_data_position].condition; \ + \ + if((condition != last_condition) || (condition >= 0x20)) \ + { \ + if((last_condition & 0x0F) != 0x0E) \ + { \ + generate_branch_patch_conditional(backpatch_address, translation_ptr); \ + } \ + \ + last_condition = condition; \ + \ + condition &= 0x0F; \ + \ + if(condition != 0x0E) \ + { \ + arm_conditional_block_header(); \ + } \ + } \ + \ + switch((opcode >> 20) & 0xFF) \ + { \ + case 0x00: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u16, half_reg); \ + } \ + else \ + { \ + /* MUL rd, rm, rs */ \ + arm_multiply(no, no); \ + } \ + } \ + else \ + { \ + /* AND rd, rn, reg_op */ \ + arm_data_proc(and, reg, no_flags); \ + } \ + break; \ + \ + case 0x01: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* MULS rd, rm, rs */ \ + arm_multiply(no, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -rm */ \ + arm_access_memory(load, down, post, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -rm */ \ + arm_access_memory(load, down, post, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* ANDS rd, rn, reg_op */ \ + arm_data_proc(ands, reg_flags, flags); \ + } \ + break; \ + \ + case 0x02: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u16, half_reg); \ + } \ + else \ + { \ + /* MLA rd, rm, rs, rn */ \ + arm_multiply(yes, no); \ + } \ + } \ + else \ + { \ + /* EOR rd, rn, reg_op */ \ + arm_data_proc(eor, reg, no_flags); \ + } \ + break; \ + \ + case 0x03: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* MLAS rd, rm, rs, rn */ \ + arm_multiply(yes, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -rm */ \ + arm_access_memory(load, down, post, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -rm */ \ + arm_access_memory(load, down, post, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* EORS rd, rn, reg_op */ \ + arm_data_proc(eors, reg_flags, flags); \ + } \ + break; \ + \ + case 0x04: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u16, half_imm); \ + } \ + else \ + { \ + /* SUB rd, rn, reg_op */ \ + arm_data_proc(sub, reg, no_flags); \ + } \ + break; \ + \ + case 0x05: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -imm */ \ + arm_access_memory(load, down, post, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -imm */ \ + arm_access_memory(load, down, post, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* SUBS rd, rn, reg_op */ \ + arm_data_proc(subs, reg, flags); \ + } \ + break; \ + \ + case 0x06: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u16, half_imm); \ + } \ + else \ + { \ + /* RSB rd, rn, reg_op */ \ + arm_data_proc(rsb, reg, no_flags); \ + } \ + break; \ + \ + case 0x07: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], -imm */ \ + arm_access_memory(load, down, post, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], -imm */ \ + arm_access_memory(load, down, post, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* RSBS rd, rn, reg_op */ \ + arm_data_proc(rsbs, reg, flags); \ + } \ + break; \ + \ + case 0x08: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u16, half_reg); \ + } \ + else \ + { \ + /* UMULL rd, rm, rs */ \ + arm_multiply_long(u64, no, no); \ + } \ + } \ + else \ + { \ + /* ADD rd, rn, reg_op */ \ + arm_data_proc(add, reg, no_flags); \ + } \ + break; \ + \ + case 0x09: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* UMULLS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(u64, no, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +rm */ \ + arm_access_memory(load, up, post, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +rm */ \ + arm_access_memory(load, up, post, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* ADDS rd, rn, reg_op */ \ + arm_data_proc(adds, reg, flags); \ + } \ + break; \ + \ + case 0x0A: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u16, half_reg); \ + } \ + else \ + { \ + /* UMLAL rd, rm, rs */ \ + arm_multiply_long(u64_add, yes, no); \ + } \ + } \ + else \ + { \ + /* ADC rd, rn, reg_op */ \ + arm_data_proc(adc, reg, no_flags); \ + } \ + break; \ + \ + case 0x0B: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* UMLALS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(u64_add, yes, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +rm */ \ + arm_access_memory(load, up, post, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +rm */ \ + arm_access_memory(load, up, post, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* ADCS rd, rn, reg_op */ \ + arm_data_proc(adcs, reg, flags); \ + } \ + break; \ + \ + case 0x0C: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u16, half_imm); \ + } \ + else \ + { \ + /* SMULL rd, rm, rs */ \ + arm_multiply_long(s64, no, no); \ + } \ + } \ + else \ + { \ + /* SBC rd, rn, reg_op */ \ + arm_data_proc(sbc, reg, no_flags); \ + } \ + break; \ + \ + case 0x0D: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* SMULLS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(s64, no, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +imm */ \ + arm_access_memory(load, up, post, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +imm */ \ + arm_access_memory(load, up, post, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* SBCS rd, rn, reg_op */ \ + arm_data_proc(sbcs, reg, flags); \ + } \ + break; \ + \ + case 0x0E: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u16, half_imm); \ + } \ + else \ + { \ + /* SMLAL rd, rm, rs */ \ + arm_multiply_long(s64_add, yes, no); \ + } \ + } \ + else \ + { \ + /* RSC rd, rn, reg_op */ \ + arm_data_proc(rsc, reg, no_flags); \ + } \ + break; \ + \ + case 0x0F: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 0: \ + /* SMLALS rdlo, rdhi, rm, rs */ \ + arm_multiply_long(s64_add, yes, yes); \ + break; \ + \ + case 1: \ + /* LDRH rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn], +imm */ \ + arm_access_memory(load, up, post, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn], +imm */ \ + arm_access_memory(load, up, post, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* RSCS rd, rn, reg_op */ \ + arm_data_proc(rscs, reg, flags); \ + } \ + break; \ + \ + case 0x10: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn - rm] */ \ + arm_access_memory(store, down, pre, u16, half_reg); \ + } \ + else \ + { \ + /* SWP rd, rm, [rn] */ \ + arm_swap(u32); \ + } \ + } \ + else \ + { \ + /* MRS rd, cpsr */ \ + arm_psr(reg, read, cpsr); \ + } \ + break; \ + \ + case 0x11: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - rm] */ \ + arm_access_memory(load, down, pre, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - rm] */ \ + arm_access_memory(load, down, pre, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - rm] */ \ + arm_access_memory(load, down, pre, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* TST rd, rn, reg_op */ \ + arm_data_proc_test(tst, reg_flags); \ + } \ + break; \ + \ + case 0x12: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn - rm]! */ \ + arm_access_memory(store, down, pre_wb, u16, half_reg); \ + } \ + else \ + { \ + if(opcode & 0x10) \ + { \ + /* BX rn */ \ + arm_bx(); \ + } \ + else \ + { \ + /* MSR cpsr, rm */ \ + arm_psr(reg, store, cpsr); \ + } \ + } \ + break; \ + \ + case 0x13: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - rm]! */ \ + arm_access_memory(load, down, pre_wb, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - rm]! */ \ + arm_access_memory(load, down, pre_wb, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - rm]! */ \ + arm_access_memory(load, down, pre_wb, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* TEQ rd, rn, reg_op */ \ + arm_data_proc_test(teq, reg_flags); \ + } \ + break; \ + \ + case 0x14: \ + if((opcode & 0x90) == 0x90) \ + { \ + if(opcode & 0x20) \ + { \ + /* STRH rd, [rn - imm] */ \ + arm_access_memory(store, down, pre, u16, half_imm); \ + } \ + else \ + { \ + /* SWPB rd, rm, [rn] */ \ + arm_swap(u8); \ + } \ + } \ + else \ + { \ + /* MRS rd, spsr */ \ + arm_psr(reg, read, spsr); \ + } \ + break; \ + \ + case 0x15: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - imm] */ \ + arm_access_memory(load, down, pre, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - imm] */ \ + arm_access_memory(load, down, pre, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - imm] */ \ + arm_access_memory(load, down, pre, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* CMP rn, reg_op */ \ + arm_data_proc_test(cmp, reg); \ + } \ + break; \ + \ + case 0x16: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn - imm]! */ \ + arm_access_memory(store, down, pre_wb, u16, half_imm); \ + } \ + else \ + { \ + /* MSR spsr, rm */ \ + arm_psr(reg, store, spsr); \ + } \ + break; \ + \ + case 0x17: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn - imm]! */ \ + arm_access_memory(load, down, pre_wb, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn - imm]! */ \ + arm_access_memory(load, down, pre_wb, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn - imm]! */ \ + arm_access_memory(load, down, pre_wb, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* CMN rd, rn, reg_op */ \ + arm_data_proc_test(cmn, reg); \ + } \ + break; \ + \ + case 0x18: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + rm] */ \ + arm_access_memory(store, up, pre, u16, half_reg); \ + } \ + else \ + { \ + /* ORR rd, rn, reg_op */ \ + arm_data_proc(orr, reg, no_flags); \ + } \ + break; \ + \ + case 0x19: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + rm] */ \ + arm_access_memory(load, up, pre, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + rm] */ \ + arm_access_memory(load, up, pre, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + rm] */ \ + arm_access_memory(load, up, pre, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* ORRS rd, rn, reg_op */ \ + arm_data_proc(orrs, reg_flags, flags); \ + } \ + break; \ + \ + case 0x1A: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + rm]! */ \ + arm_access_memory(store, up, pre_wb, u16, half_reg); \ + } \ + else \ + { \ + /* MOV rd, reg_op */ \ + arm_data_proc_unary(mov, reg, no_flags); \ + } \ + break; \ + \ + case 0x1B: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + rm]! */ \ + arm_access_memory(load, up, pre_wb, u16, half_reg); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + rm]! */ \ + arm_access_memory(load, up, pre_wb, s8, half_reg); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + rm]! */ \ + arm_access_memory(load, up, pre_wb, s16, half_reg); \ + break; \ + } \ + } \ + else \ + { \ + /* MOVS rd, reg_op */ \ + arm_data_proc_unary(movs, reg_flags, flags); \ + } \ + break; \ + \ + case 0x1C: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + imm] */ \ + arm_access_memory(store, up, pre, u16, half_imm); \ + } \ + else \ + { \ + /* BIC rd, rn, reg_op */ \ + arm_data_proc(bic, reg, no_flags); \ + } \ + break; \ + \ + case 0x1D: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + imm] */ \ + arm_access_memory(load, up, pre, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + imm] */ \ + arm_access_memory(load, up, pre, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + imm] */ \ + arm_access_memory(load, up, pre, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* BICS rd, rn, reg_op */ \ + arm_data_proc(bics, reg_flags, flags); \ + } \ + break; \ + \ + case 0x1E: \ + if((opcode & 0x90) == 0x90) \ + { \ + /* STRH rd, [rn + imm]! */ \ + arm_access_memory(store, up, pre_wb, u16, half_imm); \ + } \ + else \ + { \ + /* MVN rd, reg_op */ \ + arm_data_proc_unary(mvn, reg, no_flags); \ + } \ + break; \ + \ + case 0x1F: \ + if((opcode & 0x90) == 0x90) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + case 1: \ + /* LDRH rd, [rn + imm]! */ \ + arm_access_memory(load, up, pre_wb, u16, half_imm); \ + break; \ + \ + case 2: \ + /* LDRSB rd, [rn + imm]! */ \ + arm_access_memory(load, up, pre_wb, s8, half_imm); \ + break; \ + \ + case 3: \ + /* LDRSH rd, [rn + imm]! */ \ + arm_access_memory(load, up, pre_wb, s16, half_imm); \ + break; \ + } \ + } \ + else \ + { \ + /* MVNS rd, rn, reg_op */ \ + arm_data_proc_unary(mvns, reg_flags, flags); \ + } \ + break; \ + \ + case 0x20: \ + /* AND rd, rn, imm */ \ + arm_data_proc(and, imm, no_flags); \ + break; \ + \ + case 0x21: \ + /* ANDS rd, rn, imm */ \ + arm_data_proc(ands, imm_flags, flags); \ + break; \ + \ + case 0x22: \ + /* EOR rd, rn, imm */ \ + arm_data_proc(eor, imm, no_flags); \ + break; \ + \ + case 0x23: \ + /* EORS rd, rn, imm */ \ + arm_data_proc(eors, imm_flags, flags); \ + break; \ + \ + case 0x24: \ + /* SUB rd, rn, imm */ \ + arm_data_proc(sub, imm, no_flags); \ + break; \ + \ + case 0x25: \ + /* SUBS rd, rn, imm */ \ + arm_data_proc(subs, imm, flags); \ + break; \ + \ + case 0x26: \ + /* RSB rd, rn, imm */ \ + arm_data_proc(rsb, imm, no_flags); \ + break; \ + \ + case 0x27: \ + /* RSBS rd, rn, imm */ \ + arm_data_proc(rsbs, imm, flags); \ + break; \ + \ + case 0x28: \ + /* ADD rd, rn, imm */ \ + arm_data_proc(add, imm, no_flags); \ + break; \ + \ + case 0x29: \ + /* ADDS rd, rn, imm */ \ + arm_data_proc(adds, imm, flags); \ + break; \ + \ + case 0x2A: \ + /* ADC rd, rn, imm */ \ + arm_data_proc(adc, imm, no_flags); \ + break; \ + \ + case 0x2B: \ + /* ADCS rd, rn, imm */ \ + arm_data_proc(adcs, imm, flags); \ + break; \ + \ + case 0x2C: \ + /* SBC rd, rn, imm */ \ + arm_data_proc(sbc, imm, no_flags); \ + break; \ + \ + case 0x2D: \ + /* SBCS rd, rn, imm */ \ + arm_data_proc(sbcs, imm, flags); \ + break; \ + \ + case 0x2E: \ + /* RSC rd, rn, imm */ \ + arm_data_proc(rsc, imm, no_flags); \ + break; \ + \ + case 0x2F: \ + /* RSCS rd, rn, imm */ \ + arm_data_proc(rscs, imm, flags); \ + break; \ + \ + case 0x30 ... 0x31: \ + /* TST rn, imm */ \ + arm_data_proc_test(tst, imm); \ + break; \ + \ + case 0x32: \ + /* MSR cpsr, imm */ \ + arm_psr(imm, store, cpsr); \ + break; \ + \ + case 0x33: \ + /* TEQ rn, imm */ \ + arm_data_proc_test(teq, imm); \ + break; \ + \ + case 0x34 ... 0x35: \ + /* CMP rn, imm */ \ + arm_data_proc_test(cmp, imm); \ + break; \ + \ + case 0x36: \ + /* MSR spsr, imm */ \ + arm_psr(imm, store, spsr); \ + break; \ + \ + case 0x37: \ + /* CMN rn, imm */ \ + arm_data_proc_test(cmn, imm); \ + break; \ + \ + case 0x38: \ + /* ORR rd, rn, imm */ \ + arm_data_proc(orr, imm, no_flags); \ + break; \ + \ + case 0x39: \ + /* ORRS rd, rn, imm */ \ + arm_data_proc(orrs, imm_flags, flags); \ + break; \ + \ + case 0x3A: \ + /* MOV rd, imm */ \ + arm_data_proc_unary(mov, imm, no_flags); \ + break; \ + \ + case 0x3B: \ + /* MOVS rd, imm */ \ + arm_data_proc_unary(movs, imm_flags, flags); \ + break; \ + \ + case 0x3C: \ + /* BIC rd, rn, imm */ \ + arm_data_proc(bic, imm, no_flags); \ + break; \ + \ + case 0x3D: \ + /* BICS rd, rn, imm */ \ + arm_data_proc(bics, imm_flags, flags); \ + break; \ + \ + case 0x3E: \ + /* MVN rd, imm */ \ + arm_data_proc_unary(mvn, imm, no_flags); \ + break; \ + \ + case 0x3F: \ + /* MVNS rd, imm */ \ + arm_data_proc_unary(mvns, imm_flags, flags); \ + break; \ + \ + case 0x40: \ + /* STR rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u32, imm); \ + break; \ + \ + case 0x41: \ + /* LDR rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u32, imm); \ + break; \ + \ + case 0x42: \ + /* STRT rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u32, imm); \ + break; \ + \ + case 0x43: \ + /* LDRT rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u32, imm); \ + break; \ + \ + case 0x44: \ + /* STRB rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u8, imm); \ + break; \ + \ + case 0x45: \ + /* LDRB rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u8, imm); \ + break; \ + \ + case 0x46: \ + /* STRBT rd, [rn], -imm */ \ + arm_access_memory(store, down, post, u8, imm); \ + break; \ + \ + case 0x47: \ + /* LDRBT rd, [rn], -imm */ \ + arm_access_memory(load, down, post, u8, imm); \ + break; \ + \ + case 0x48: \ + /* STR rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u32, imm); \ + break; \ + \ + case 0x49: \ + /* LDR rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u32, imm); \ + break; \ + \ + case 0x4A: \ + /* STRT rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u32, imm); \ + break; \ + \ + case 0x4B: \ + /* LDRT rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u32, imm); \ + break; \ + \ + case 0x4C: \ + /* STRB rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u8, imm); \ + break; \ + \ + case 0x4D: \ + /* LDRB rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u8, imm); \ + break; \ + \ + case 0x4E: \ + /* STRBT rd, [rn], +imm */ \ + arm_access_memory(store, up, post, u8, imm); \ + break; \ + \ + case 0x4F: \ + /* LDRBT rd, [rn], +imm */ \ + arm_access_memory(load, up, post, u8, imm); \ + break; \ + \ + case 0x50: \ + /* STR rd, [rn - imm] */ \ + arm_access_memory(store, down, pre, u32, imm); \ + break; \ + \ + case 0x51: \ + /* LDR rd, [rn - imm] */ \ + arm_access_memory(load, down, pre, u32, imm); \ + break; \ + \ + case 0x52: \ + /* STR rd, [rn - imm]! */ \ + arm_access_memory(store, down, pre_wb, u32, imm); \ + break; \ + \ + case 0x53: \ + /* LDR rd, [rn - imm]! */ \ + arm_access_memory(load, down, pre_wb, u32, imm); \ + break; \ + \ + case 0x54: \ + /* STRB rd, [rn - imm] */ \ + arm_access_memory(store, down, pre, u8, imm); \ + break; \ + \ + case 0x55: \ + /* LDRB rd, [rn - imm] */ \ + arm_access_memory(load, down, pre, u8, imm); \ + break; \ + \ + case 0x56: \ + /* STRB rd, [rn - imm]! */ \ + arm_access_memory(store, down, pre_wb, u8, imm); \ + break; \ + \ + case 0x57: \ + /* LDRB rd, [rn - imm]! */ \ + arm_access_memory(load, down, pre_wb, u8, imm); \ + break; \ + \ + case 0x58: \ + /* STR rd, [rn + imm] */ \ + arm_access_memory(store, up, pre, u32, imm); \ + break; \ + \ + case 0x59: \ + /* LDR rd, [rn + imm] */ \ + arm_access_memory(load, up, pre, u32, imm); \ + break; \ + \ + case 0x5A: \ + /* STR rd, [rn + imm]! */ \ + arm_access_memory(store, up, pre_wb, u32, imm); \ + break; \ + \ + case 0x5B: \ + /* LDR rd, [rn + imm]! */ \ + arm_access_memory(load, up, pre_wb, u32, imm); \ + break; \ + \ + case 0x5C: \ + /* STRB rd, [rn + imm] */ \ + arm_access_memory(store, up, pre, u8, imm); \ + break; \ + \ + case 0x5D: \ + /* LDRB rd, [rn + imm] */ \ + arm_access_memory(load, up, pre, u8, imm); \ + break; \ + \ + case 0x5E: \ + /* STRB rd, [rn + imm]! */ \ + arm_access_memory(store, up, pre_wb, u8, imm); \ + break; \ + \ + case 0x5F: \ + /* LDRBT rd, [rn + imm]! */ \ + arm_access_memory(load, up, pre_wb, u8, imm); \ + break; \ + \ + case 0x60: \ + /* STR rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u32, reg); \ + break; \ + \ + case 0x61: \ + /* LDR rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u32, reg); \ + break; \ + \ + case 0x62: \ + /* STRT rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u32, reg); \ + break; \ + \ + case 0x63: \ + /* LDRT rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u32, reg); \ + break; \ + \ + case 0x64: \ + /* STRB rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u8, reg); \ + break; \ + \ + case 0x65: \ + /* LDRB rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u8, reg); \ + break; \ + \ + case 0x66: \ + /* STRBT rd, [rn], -rm */ \ + arm_access_memory(store, down, post, u8, reg); \ + break; \ + \ + case 0x67: \ + /* LDRBT rd, [rn], -rm */ \ + arm_access_memory(load, down, post, u8, reg); \ + break; \ + \ + case 0x68: \ + /* STR rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u32, reg); \ + break; \ + \ + case 0x69: \ + /* LDR rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u32, reg); \ + break; \ + \ + case 0x6A: \ + /* STRT rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u32, reg); \ + break; \ + \ + case 0x6B: \ + /* LDRT rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u32, reg); \ + break; \ + \ + case 0x6C: \ + /* STRB rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u8, reg); \ + break; \ + \ + case 0x6D: \ + /* LDRB rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u8, reg); \ + break; \ + \ + case 0x6E: \ + /* STRBT rd, [rn], +rm */ \ + arm_access_memory(store, up, post, u8, reg); \ + break; \ + \ + case 0x6F: \ + /* LDRBT rd, [rn], +rm */ \ + arm_access_memory(load, up, post, u8, reg); \ + break; \ + \ + case 0x70: \ + /* STR rd, [rn - rm] */ \ + arm_access_memory(store, down, pre, u32, reg); \ + break; \ + \ + case 0x71: \ + /* LDR rd, [rn - rm] */ \ + arm_access_memory(load, down, pre, u32, reg); \ + break; \ + \ + case 0x72: \ + /* STR rd, [rn - rm]! */ \ + arm_access_memory(store, down, pre_wb, u32, reg); \ + break; \ + \ + case 0x73: \ + /* LDR rd, [rn - rm]! */ \ + arm_access_memory(load, down, pre_wb, u32, reg); \ + break; \ + \ + case 0x74: \ + /* STRB rd, [rn - rm] */ \ + arm_access_memory(store, down, pre, u8, reg); \ + break; \ + \ + case 0x75: \ + /* LDRB rd, [rn - rm] */ \ + arm_access_memory(load, down, pre, u8, reg); \ + break; \ + \ + case 0x76: \ + /* STRB rd, [rn - rm]! */ \ + arm_access_memory(store, down, pre_wb, u8, reg); \ + break; \ + \ + case 0x77: \ + /* LDRB rd, [rn - rm]! */ \ + arm_access_memory(load, down, pre_wb, u8, reg); \ + break; \ + \ + case 0x78: \ + /* STR rd, [rn + rm] */ \ + arm_access_memory(store, up, pre, u32, reg); \ + break; \ + \ + case 0x79: \ + /* LDR rd, [rn + rm] */ \ + arm_access_memory(load, up, pre, u32, reg); \ + break; \ + \ + case 0x7A: \ + /* STR rd, [rn + rm]! */ \ + arm_access_memory(store, up, pre_wb, u32, reg); \ + break; \ + \ + case 0x7B: \ + /* LDR rd, [rn + rm]! */ \ + arm_access_memory(load, up, pre_wb, u32, reg); \ + break; \ + \ + case 0x7C: \ + /* STRB rd, [rn + rm] */ \ + arm_access_memory(store, up, pre, u8, reg); \ + break; \ + \ + case 0x7D: \ + /* LDRB rd, [rn + rm] */ \ + arm_access_memory(load, up, pre, u8, reg); \ + break; \ + \ + case 0x7E: \ + /* STRB rd, [rn + rm]! */ \ + arm_access_memory(store, up, pre_wb, u8, reg); \ + break; \ + \ + case 0x7F: \ + /* LDRBT rd, [rn + rm]! */ \ + arm_access_memory(load, up, pre_wb, u8, reg); \ + break; \ + \ + case 0x80: \ + /* STMDA rn, rlist */ \ + arm_block_memory(store, down_a, no, no); \ + break; \ + \ + case 0x81: \ + /* LDMDA rn, rlist */ \ + arm_block_memory(load, down_a, no, no); \ + break; \ + \ + case 0x82: \ + /* STMDA rn!, rlist */ \ + arm_block_memory(store, down_a, down, no); \ + break; \ + \ + case 0x83: \ + /* LDMDA rn!, rlist */ \ + arm_block_memory(load, down_a, down, no); \ + break; \ + \ + case 0x84: \ + /* STMDA rn, rlist^ */ \ + arm_block_memory(store, down_a, no, yes); \ + break; \ + \ + case 0x85: \ + /* LDMDA rn, rlist^ */ \ + arm_block_memory(load, down_a, no, yes); \ + break; \ + \ + case 0x86: \ + /* STMDA rn!, rlist^ */ \ + arm_block_memory(store, down_a, down, yes); \ + break; \ + \ + case 0x87: \ + /* LDMDA rn!, rlist^ */ \ + arm_block_memory(load, down_a, down, yes); \ + break; \ + \ + case 0x88: \ + /* STMIA rn, rlist */ \ + arm_block_memory(store, no, no, no); \ + break; \ + \ + case 0x89: \ + /* LDMIA rn, rlist */ \ + arm_block_memory(load, no, no, no); \ + break; \ + \ + case 0x8A: \ + /* STMIA rn!, rlist */ \ + arm_block_memory(store, no, up, no); \ + break; \ + \ + case 0x8B: \ + /* LDMIA rn!, rlist */ \ + arm_block_memory(load, no, up, no); \ + break; \ + \ + case 0x8C: \ + /* STMIA rn, rlist^ */ \ + arm_block_memory(store, no, no, yes); \ + break; \ + \ + case 0x8D: \ + /* LDMIA rn, rlist^ */ \ + arm_block_memory(load, no, no, yes); \ + break; \ + \ + case 0x8E: \ + /* STMIA rn!, rlist^ */ \ + arm_block_memory(store, no, up, yes); \ + break; \ + \ + case 0x8F: \ + /* LDMIA rn!, rlist^ */ \ + arm_block_memory(load, no, up, yes); \ + break; \ + \ + case 0x90: \ + /* STMDB rn, rlist */ \ + arm_block_memory(store, down_b, no, no); \ + break; \ + \ + case 0x91: \ + /* LDMDB rn, rlist */ \ + arm_block_memory(load, down_b, no, no); \ + break; \ + \ + case 0x92: \ + /* STMDB rn!, rlist */ \ + arm_block_memory(store, down_b, down, no); \ + break; \ + \ + case 0x93: \ + /* LDMDB rn!, rlist */ \ + arm_block_memory(load, down_b, down, no); \ + break; \ + \ + case 0x94: \ + /* STMDB rn, rlist^ */ \ + arm_block_memory(store, down_b, no, yes); \ + break; \ + \ + case 0x95: \ + /* LDMDB rn, rlist^ */ \ + arm_block_memory(load, down_b, no, yes); \ + break; \ + \ + case 0x96: \ + /* STMDB rn!, rlist^ */ \ + arm_block_memory(store, down_b, down, yes); \ + break; \ + \ + case 0x97: \ + /* LDMDB rn!, rlist^ */ \ + arm_block_memory(load, down_b, down, yes); \ + break; \ + \ + case 0x98: \ + /* STMIB rn, rlist */ \ + arm_block_memory(store, up, no, no); \ + break; \ + \ + case 0x99: \ + /* LDMIB rn, rlist */ \ + arm_block_memory(load, up, no, no); \ + break; \ + \ + case 0x9A: \ + /* STMIB rn!, rlist */ \ + arm_block_memory(store, up, up, no); \ + break; \ + \ + case 0x9B: \ + /* LDMIB rn!, rlist */ \ + arm_block_memory(load, up, up, no); \ + break; \ + \ + case 0x9C: \ + /* STMIB rn, rlist^ */ \ + arm_block_memory(store, up, no, yes); \ + break; \ + \ + case 0x9D: \ + /* LDMIB rn, rlist^ */ \ + arm_block_memory(load, up, no, yes); \ + break; \ + \ + case 0x9E: \ + /* STMIB rn!, rlist^ */ \ + arm_block_memory(store, up, up, yes); \ + break; \ + \ + case 0x9F: \ + /* LDMIB rn!, rlist^ */ \ + arm_block_memory(load, up, up, yes); \ + break; \ + \ + case 0xA0 ... 0xAF: \ + { \ + /* B offset */ \ + arm_b(); \ + break; \ + } \ + \ + case 0xB0 ... 0xBF: \ + { \ + /* BL offset */ \ + arm_bl(); \ + break; \ + } \ + \ + case 0xC0 ... 0xEF: \ + /* coprocessor instructions, reserved on GBA */ \ + break; \ + \ + case 0xF0 ... 0xFF: \ + { \ + /* SWI comment */ \ + arm_swi(); \ + break; \ + } \ + } \ + \ + pc += 4 \ + +#define arm_flag_status() \ + +#define translate_thumb_instruction() \ + flag_status = block_data[block_data_position].flag_data; \ + check_pc_region(pc); \ + last_opcode = opcode; \ + opcode = address16(pc_address_block, (pc & 0x7FFF)); \ + \ + switch((opcode >> 8) & 0xFF) \ + { \ + case 0x00 ... 0x07: \ + /* LSL rd, rs, imm */ \ + thumb_shift(shift, lsl, imm); \ + break; \ + \ + case 0x08 ... 0x0F: \ + /* LSR rd, rs, imm */ \ + thumb_shift(shift, lsr, imm); \ + break; \ + \ + case 0x10 ... 0x17: \ + /* ASR rd, rs, imm */ \ + thumb_shift(shift, asr, imm); \ + break; \ + \ + case 0x18 ... 0x19: \ + /* ADD rd, rs, rn */ \ + thumb_data_proc(add_sub, adds, reg, rd, rs, rn); \ + break; \ + \ + case 0x1A ... 0x1B: \ + /* SUB rd, rs, rn */ \ + thumb_data_proc(add_sub, subs, reg, rd, rs, rn); \ + break; \ + \ + case 0x1C ... 0x1D: \ + /* ADD rd, rs, imm */ \ + thumb_data_proc(add_sub_imm, adds, imm, rd, rs, imm); \ + break; \ + \ + case 0x1E ... 0x1F: \ + /* SUB rd, rs, imm */ \ + thumb_data_proc(add_sub_imm, subs, imm, rd, rs, imm); \ + break; \ + \ + case 0x20: \ + /* MOV r0, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 0, imm); \ + break; \ + \ + case 0x21: \ + /* MOV r1, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 1, imm); \ + break; \ + \ + case 0x22: \ + /* MOV r2, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 2, imm); \ + break; \ + \ + case 0x23: \ + /* MOV r3, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 3, imm); \ + break; \ + \ + case 0x24: \ + /* MOV r4, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 4, imm); \ + break; \ + \ + case 0x25: \ + /* MOV r5, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 5, imm); \ + break; \ + \ + case 0x26: \ + /* MOV r6, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 6, imm); \ + break; \ + \ + case 0x27: \ + /* MOV r7, imm */ \ + thumb_data_proc_unary(imm, movs, imm, 7, imm); \ + break; \ + \ + case 0x28: \ + /* CMP r0, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 0, imm); \ + break; \ + \ + case 0x29: \ + /* CMP r1, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 1, imm); \ + break; \ + \ + case 0x2A: \ + /* CMP r2, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 2, imm); \ + break; \ + \ + case 0x2B: \ + /* CMP r3, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 3, imm); \ + break; \ + \ + case 0x2C: \ + /* CMP r4, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 4, imm); \ + break; \ + \ + case 0x2D: \ + /* CMP r5, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 5, imm); \ + break; \ + \ + case 0x2E: \ + /* CMP r6, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 6, imm); \ + break; \ + \ + case 0x2F: \ + /* CMP r7, imm */ \ + thumb_data_proc_test(imm, cmp, imm, 7, imm); \ + break; \ + \ + case 0x30: \ + /* ADD r0, imm */ \ + thumb_data_proc(imm, adds, imm, 0, 0, imm); \ + break; \ + \ + case 0x31: \ + /* ADD r1, imm */ \ + thumb_data_proc(imm, adds, imm, 1, 1, imm); \ + break; \ + \ + case 0x32: \ + /* ADD r2, imm */ \ + thumb_data_proc(imm, adds, imm, 2, 2, imm); \ + break; \ + \ + case 0x33: \ + /* ADD r3, imm */ \ + thumb_data_proc(imm, adds, imm, 3, 3, imm); \ + break; \ + \ + case 0x34: \ + /* ADD r4, imm */ \ + thumb_data_proc(imm, adds, imm, 4, 4, imm); \ + break; \ + \ + case 0x35: \ + /* ADD r5, imm */ \ + thumb_data_proc(imm, adds, imm, 5, 5, imm); \ + break; \ + \ + case 0x36: \ + /* ADD r6, imm */ \ + thumb_data_proc(imm, adds, imm, 6, 6, imm); \ + break; \ + \ + case 0x37: \ + /* ADD r7, imm */ \ + thumb_data_proc(imm, adds, imm, 7, 7, imm); \ + break; \ + \ + case 0x38: \ + /* SUB r0, imm */ \ + thumb_data_proc(imm, subs, imm, 0, 0, imm); \ + break; \ + \ + case 0x39: \ + /* SUB r1, imm */ \ + thumb_data_proc(imm, subs, imm, 1, 1, imm); \ + break; \ + \ + case 0x3A: \ + /* SUB r2, imm */ \ + thumb_data_proc(imm, subs, imm, 2, 2, imm); \ + break; \ + \ + case 0x3B: \ + /* SUB r3, imm */ \ + thumb_data_proc(imm, subs, imm, 3, 3, imm); \ + break; \ + \ + case 0x3C: \ + /* SUB r4, imm */ \ + thumb_data_proc(imm, subs, imm, 4, 4, imm); \ + break; \ + \ + case 0x3D: \ + /* SUB r5, imm */ \ + thumb_data_proc(imm, subs, imm, 5, 5, imm); \ + break; \ + \ + case 0x3E: \ + /* SUB r6, imm */ \ + thumb_data_proc(imm, subs, imm, 6, 6, imm); \ + break; \ + \ + case 0x3F: \ + /* SUB r7, imm */ \ + thumb_data_proc(imm, subs, imm, 7, 7, imm); \ + break; \ + \ + case 0x40: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* AND rd, rs */ \ + thumb_data_proc(alu_op, ands, reg, rd, rd, rs); \ + break; \ + \ + case 0x01: \ + /* EOR rd, rs */ \ + thumb_data_proc(alu_op, eors, reg, rd, rd, rs); \ + break; \ + \ + case 0x02: \ + /* LSL rd, rs */ \ + thumb_shift(alu_op, lsl, reg); \ + break; \ + \ + case 0x03: \ + /* LSR rd, rs */ \ + thumb_shift(alu_op, lsr, reg); \ + break; \ + } \ + break; \ + \ + case 0x41: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* ASR rd, rs */ \ + thumb_shift(alu_op, asr, reg); \ + break; \ + \ + case 0x01: \ + /* ADC rd, rs */ \ + thumb_data_proc(alu_op, adcs, reg, rd, rd, rs); \ + break; \ + \ + case 0x02: \ + /* SBC rd, rs */ \ + thumb_data_proc(alu_op, sbcs, reg, rd, rd, rs); \ + break; \ + \ + case 0x03: \ + /* ROR rd, rs */ \ + thumb_shift(alu_op, ror, reg); \ + break; \ + } \ + break; \ + \ + case 0x42: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* TST rd, rs */ \ + thumb_data_proc_test(alu_op, tst, reg, rd, rs); \ + break; \ + \ + case 0x01: \ + /* NEG rd, rs */ \ + thumb_data_proc_unary(alu_op, neg, reg, rd, rs); \ + break; \ + \ + case 0x02: \ + /* CMP rd, rs */ \ + thumb_data_proc_test(alu_op, cmp, reg, rd, rs); \ + break; \ + \ + case 0x03: \ + /* CMN rd, rs */ \ + thumb_data_proc_test(alu_op, cmn, reg, rd, rs); \ + break; \ + } \ + break; \ + \ + case 0x43: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* ORR rd, rs */ \ + thumb_data_proc(alu_op, orrs, reg, rd, rd, rs); \ + break; \ + \ + case 0x01: \ + /* MUL rd, rs */ \ + thumb_data_proc(alu_op, muls, reg, rd, rd, rs); \ + break; \ + \ + case 0x02: \ + /* BIC rd, rs */ \ + thumb_data_proc(alu_op, bics, reg, rd, rd, rs); \ + break; \ + \ + case 0x03: \ + /* MVN rd, rs */ \ + thumb_data_proc_unary(alu_op, mvns, reg, rd, rs); \ + break; \ + } \ + break; \ + \ + case 0x44: \ + /* ADD rd, rs */ \ + thumb_data_proc_hi(add); \ + break; \ + \ + case 0x45: \ + /* CMP rd, rs */ \ + thumb_data_proc_test_hi(cmp); \ + break; \ + \ + case 0x46: \ + /* MOV rd, rs */ \ + thumb_data_proc_mov_hi(); \ + break; \ + \ + case 0x47: \ + /* BX rs */ \ + thumb_bx(); \ + break; \ + \ + case 0x48: \ + /* LDR r0, [pc + imm] */ \ + thumb_access_memory(load, imm, 0, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x49: \ + /* LDR r1, [pc + imm] */ \ + thumb_access_memory(load, imm, 1, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4A: \ + /* LDR r2, [pc + imm] */ \ + thumb_access_memory(load, imm, 2, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4B: \ + /* LDR r3, [pc + imm] */ \ + thumb_access_memory(load, imm, 3, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4C: \ + /* LDR r4, [pc + imm] */ \ + thumb_access_memory(load, imm, 4, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4D: \ + /* LDR r5, [pc + imm] */ \ + thumb_access_memory(load, imm, 5, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4E: \ + /* LDR r6, [pc + imm] */ \ + thumb_access_memory(load, imm, 6, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x4F: \ + /* LDR r7, [pc + imm] */ \ + thumb_access_memory(load, imm, 7, 0, 0, pc_relative, \ + (pc & ~2) + (imm * 4) + 4, u32); \ + break; \ + \ + case 0x50 ... 0x51: \ + /* STR rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u32); \ + break; \ + \ + case 0x52 ... 0x53: \ + /* STRH rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u16); \ + break; \ + \ + case 0x54 ... 0x55: \ + /* STRB rd, [rb + ro] */ \ + thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u8); \ + break; \ + \ + case 0x56 ... 0x57: \ + /* LDSB rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, s8); \ + break; \ + \ + case 0x58 ... 0x59: \ + /* LDR rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u32); \ + break; \ + \ + case 0x5A ... 0x5B: \ + /* LDRH rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u16); \ + break; \ + \ + case 0x5C ... 0x5D: \ + /* LDRB rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u8); \ + break; \ + \ + case 0x5E ... 0x5F: \ + /* LDSH rd, [rb + ro] */ \ + thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, s16); \ + break; \ + \ + case 0x60 ... 0x67: \ + /* STR rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, (imm * 4), \ + u32); \ + break; \ + \ + case 0x68 ... 0x6F: \ + /* LDR rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, (imm * 4), u32); \ + break; \ + \ + case 0x70 ... 0x77: \ + /* STRB rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, imm, u8); \ + break; \ + \ + case 0x78 ... 0x7F: \ + /* LDRB rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, imm, u8); \ + break; \ + \ + case 0x80 ... 0x87: \ + /* STRH rd, [rb + imm] */ \ + thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, \ + (imm * 2), u16); \ + break; \ + \ + case 0x88 ... 0x8F: \ + /* LDRH rd, [rb + imm] */ \ + thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, (imm * 2), u16); \ + break; \ + \ + case 0x90: \ + /* STR r0, [sp + imm] */ \ + thumb_access_memory(store, imm, 0, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x91: \ + /* STR r1, [sp + imm] */ \ + thumb_access_memory(store, imm, 1, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x92: \ + /* STR r2, [sp + imm] */ \ + thumb_access_memory(store, imm, 2, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x93: \ + /* STR r3, [sp + imm] */ \ + thumb_access_memory(store, imm, 3, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x94: \ + /* STR r4, [sp + imm] */ \ + thumb_access_memory(store, imm, 4, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x95: \ + /* STR r5, [sp + imm] */ \ + thumb_access_memory(store, imm, 5, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x96: \ + /* STR r6, [sp + imm] */ \ + thumb_access_memory(store, imm, 6, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x97: \ + /* STR r7, [sp + imm] */ \ + thumb_access_memory(store, imm, 7, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x98: \ + /* LDR r0, [sp + imm] */ \ + thumb_access_memory(load, imm, 0, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x99: \ + /* LDR r1, [sp + imm] */ \ + thumb_access_memory(load, imm, 1, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9A: \ + /* LDR r2, [sp + imm] */ \ + thumb_access_memory(load, imm, 2, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9B: \ + /* LDR r3, [sp + imm] */ \ + thumb_access_memory(load, imm, 3, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9C: \ + /* LDR r4, [sp + imm] */ \ + thumb_access_memory(load, imm, 4, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9D: \ + /* LDR r5, [sp + imm] */ \ + thumb_access_memory(load, imm, 5, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9E: \ + /* LDR r6, [sp + imm] */ \ + thumb_access_memory(load, imm, 6, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0x9F: \ + /* LDR r7, [sp + imm] */ \ + thumb_access_memory(load, imm, 7, 13, 0, reg_imm_sp, imm, u32); \ + break; \ + \ + case 0xA0: \ + /* ADD r0, pc, +imm */ \ + thumb_load_pc(0); \ + break; \ + \ + case 0xA1: \ + /* ADD r1, pc, +imm */ \ + thumb_load_pc(1); \ + break; \ + \ + case 0xA2: \ + /* ADD r2, pc, +imm */ \ + thumb_load_pc(2); \ + break; \ + \ + case 0xA3: \ + /* ADD r3, pc, +imm */ \ + thumb_load_pc(3); \ + break; \ + \ + case 0xA4: \ + /* ADD r4, pc, +imm */ \ + thumb_load_pc(4); \ + break; \ + \ + case 0xA5: \ + /* ADD r5, pc, +imm */ \ + thumb_load_pc(5); \ + break; \ + \ + case 0xA6: \ + /* ADD r6, pc, +imm */ \ + thumb_load_pc(6); \ + break; \ + \ + case 0xA7: \ + /* ADD r7, pc, +imm */ \ + thumb_load_pc(7); \ + break; \ + \ + case 0xA8: \ + /* ADD r0, sp, +imm */ \ + thumb_load_sp(0); \ + break; \ + \ + case 0xA9: \ + /* ADD r1, sp, +imm */ \ + thumb_load_sp(1); \ + break; \ + \ + case 0xAA: \ + /* ADD r2, sp, +imm */ \ + thumb_load_sp(2); \ + break; \ + \ + case 0xAB: \ + /* ADD r3, sp, +imm */ \ + thumb_load_sp(3); \ + break; \ + \ + case 0xAC: \ + /* ADD r4, sp, +imm */ \ + thumb_load_sp(4); \ + break; \ + \ + case 0xAD: \ + /* ADD r5, sp, +imm */ \ + thumb_load_sp(5); \ + break; \ + \ + case 0xAE: \ + /* ADD r6, sp, +imm */ \ + thumb_load_sp(6); \ + break; \ + \ + case 0xAF: \ + /* ADD r7, sp, +imm */ \ + thumb_load_sp(7); \ + break; \ + \ + case 0xB0 ... 0xB3: \ + if((opcode >> 7) & 0x01) \ + { \ + /* ADD sp, -imm */ \ + thumb_adjust_sp(down); \ + } \ + else \ + { \ + /* ADD sp, +imm */ \ + thumb_adjust_sp(up); \ + } \ + break; \ + \ + case 0xB4: \ + /* PUSH rlist */ \ + thumb_block_memory(store, down, no, 13); \ + break; \ + \ + case 0xB5: \ + /* PUSH rlist, lr */ \ + thumb_block_memory(store, push_lr, push_lr, 13); \ + break; \ + \ + case 0xBC: \ + /* POP rlist */ \ + thumb_block_memory(load, no, up, 13); \ + break; \ + \ + case 0xBD: \ + /* POP rlist, pc */ \ + thumb_block_memory(load, no, pop_pc, 13); \ + break; \ + \ + case 0xC0: \ + /* STMIA r0!, rlist */ \ + thumb_block_memory(store, no, up, 0); \ + break; \ + \ + case 0xC1: \ + /* STMIA r1!, rlist */ \ + thumb_block_memory(store, no, up, 1); \ + break; \ + \ + case 0xC2: \ + /* STMIA r2!, rlist */ \ + thumb_block_memory(store, no, up, 2); \ + break; \ + \ + case 0xC3: \ + /* STMIA r3!, rlist */ \ + thumb_block_memory(store, no, up, 3); \ + break; \ + \ + case 0xC4: \ + /* STMIA r4!, rlist */ \ + thumb_block_memory(store, no, up, 4); \ + break; \ + \ + case 0xC5: \ + /* STMIA r5!, rlist */ \ + thumb_block_memory(store, no, up, 5); \ + break; \ + \ + case 0xC6: \ + /* STMIA r6!, rlist */ \ + thumb_block_memory(store, no, up, 6); \ + break; \ + \ + case 0xC7: \ + /* STMIA r7!, rlist */ \ + thumb_block_memory(store, no, up, 7); \ + break; \ + \ + case 0xC8: \ + /* LDMIA r0!, rlist */ \ + thumb_block_memory(load, no, up, 0); \ + break; \ + \ + case 0xC9: \ + /* LDMIA r1!, rlist */ \ + thumb_block_memory(load, no, up, 1); \ + break; \ + \ + case 0xCA: \ + /* LDMIA r2!, rlist */ \ + thumb_block_memory(load, no, up, 2); \ + break; \ + \ + case 0xCB: \ + /* LDMIA r3!, rlist */ \ + thumb_block_memory(load, no, up, 3); \ + break; \ + \ + case 0xCC: \ + /* LDMIA r4!, rlist */ \ + thumb_block_memory(load, no, up, 4); \ + break; \ + \ + case 0xCD: \ + /* LDMIA r5!, rlist */ \ + thumb_block_memory(load, no, up, 5); \ + break; \ + \ + case 0xCE: \ + /* LDMIA r6!, rlist */ \ + thumb_block_memory(load, no, up, 6); \ + break; \ + \ + case 0xCF: \ + /* LDMIA r7!, rlist */ \ + thumb_block_memory(load, no, up, 7); \ + break; \ + \ + case 0xD0: \ + /* BEQ label */ \ + thumb_conditional_branch(eq); \ + break; \ + \ + case 0xD1: \ + /* BNE label */ \ + thumb_conditional_branch(ne); \ + break; \ + \ + case 0xD2: \ + /* BCS label */ \ + thumb_conditional_branch(cs); \ + break; \ + \ + case 0xD3: \ + /* BCC label */ \ + thumb_conditional_branch(cc); \ + break; \ + \ + case 0xD4: \ + /* BMI label */ \ + thumb_conditional_branch(mi); \ + break; \ + \ + case 0xD5: \ + /* BPL label */ \ + thumb_conditional_branch(pl); \ + break; \ + \ + case 0xD6: \ + /* BVS label */ \ + thumb_conditional_branch(vs); \ + break; \ + \ + case 0xD7: \ + /* BVC label */ \ + thumb_conditional_branch(vc); \ + break; \ + \ + case 0xD8: \ + /* BHI label */ \ + thumb_conditional_branch(hi); \ + break; \ + \ + case 0xD9: \ + /* BLS label */ \ + thumb_conditional_branch(ls); \ + break; \ + \ + case 0xDA: \ + /* BGE label */ \ + thumb_conditional_branch(ge); \ + break; \ + \ + case 0xDB: \ + /* BLT label */ \ + thumb_conditional_branch(lt); \ + break; \ + \ + case 0xDC: \ + /* BGT label */ \ + thumb_conditional_branch(gt); \ + break; \ + \ + case 0xDD: \ + /* BLE label */ \ + thumb_conditional_branch(le); \ + break; \ + \ + case 0xDF: \ + { \ + /* SWI comment */ \ + thumb_swi(); \ + break; \ + } \ + \ + case 0xE0 ... 0xE7: \ + { \ + /* B label */ \ + thumb_b(); \ + break; \ + } \ + \ + case 0xF0 ... 0xF7: \ + { \ + /* (low word) BL label */ \ + /* This should possibly generate code if not in conjunction with a BLH \ + next, but I don't think anyone will do that. */ \ + break; \ + } \ + \ + case 0xF8 ... 0xFF: \ + { \ + /* (high word) BL label */ \ + /* This might not be preceeding a BL low word (Golden Sun 2), if so \ + it must be handled like an indirect branch. */ \ + if((last_opcode >= 0xF000) && (last_opcode < 0xF800)) \ + { \ + thumb_bl(); \ + } \ + else \ + { \ + thumb_blh(); \ + } \ + break; \ + } \ + } \ + \ + pc += 2 \ + +#define thumb_flag_modifies_all() \ + flag_status |= 0xFF \ + +#define thumb_flag_modifies_zn() \ + flag_status |= 0xCC \ + +#define thumb_flag_modifies_znc() \ + flag_status |= 0xEE \ + +#define thumb_flag_modifies_zn_maybe_c() \ + flag_status |= 0xCE \ + +#define thumb_flag_modifies_c() \ + flag_status |= 0x22 \ + +#define thumb_flag_requires_c() \ + flag_status |= 0x200 \ + +#define thumb_flag_requires_all() \ + flag_status |= 0xF00 \ + +#define thumb_flag_status() \ +{ \ + u16 flag_status = 0; \ + switch((opcode >> 8) & 0xFF) \ + { \ + /* left shift by imm */ \ + case 0x00 ... 0x07: \ + thumb_flag_modifies_zn(); \ + if(((opcode >> 6) & 0x1F) != 0) \ + { \ + thumb_flag_modifies_c(); \ + } \ + break; \ + \ + /* right shift by imm */ \ + case 0x08 ... 0x17: \ + thumb_flag_modifies_znc(); \ + break; \ + \ + /* add, subtract */ \ + case 0x18 ... 0x1F: \ + thumb_flag_modifies_all(); \ + break; \ + \ + /* mov reg, imm */ \ + case 0x20 ... 0x27: \ + thumb_flag_modifies_zn(); \ + break; \ + \ + /* cmp reg, imm; add, subtract */ \ + case 0x28 ... 0x3F: \ + thumb_flag_modifies_all(); \ + break; \ + \ + case 0x40: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* AND rd, rs */ \ + thumb_flag_modifies_zn(); \ + break; \ + \ + case 0x01: \ + /* EOR rd, rs */ \ + thumb_flag_modifies_zn(); \ + break; \ + \ + case 0x02: \ + /* LSL rd, rs */ \ + thumb_flag_modifies_zn_maybe_c(); \ + break; \ + \ + case 0x03: \ + /* LSR rd, rs */ \ + thumb_flag_modifies_zn_maybe_c(); \ + break; \ + } \ + break; \ + \ + case 0x41: \ + switch((opcode >> 6) & 0x03) \ + { \ + case 0x00: \ + /* ASR rd, rs */ \ + thumb_flag_modifies_zn_maybe_c(); \ + break; \ + \ + case 0x01: \ + /* ADC rd, rs */ \ + thumb_flag_modifies_all(); \ + thumb_flag_requires_c(); \ + break; \ + \ + case 0x02: \ + /* SBC rd, rs */ \ + thumb_flag_modifies_all(); \ + thumb_flag_requires_c(); \ + break; \ + \ + case 0x03: \ + /* ROR rd, rs */ \ + thumb_flag_modifies_zn_maybe_c(); \ + break; \ + } \ + break; \ + \ + /* TST, NEG, CMP, CMN */ \ + case 0x42: \ + thumb_flag_modifies_all(); \ + break; \ + \ + /* ORR, MUL, BIC, MVN */ \ + case 0x43: \ + thumb_flag_modifies_zn(); \ + break; \ + \ + case 0x45: \ + /* CMP rd, rs */ \ + thumb_flag_modifies_all(); \ + break; \ + \ + /* mov might change PC (fall through if so) */ \ + case 0x46: \ + if((opcode & 0xFF87) != 0x4687) \ + break; \ + \ + /* branches (can change PC) */ \ + case 0x47: \ + case 0xBD: \ + case 0xD0 ... 0xE7: \ + case 0xF0 ... 0xFF: \ + thumb_flag_requires_all(); \ + break; \ + } \ + block_data[block_data_position].flag_data = flag_status; \ +} \ + +u8 *ram_block_ptrs[1024 * 64]; +u32 ram_block_tag_top = 0x0101; + +u8 *bios_block_ptrs[1024 * 8]; +u32 bios_block_tag_top = 0x0101; + +// This function will return a pointer to a translated block of code. If it +// doesn't exist it will translate it, if it does it will pass it back. + +// type should be "arm", "thumb", or "dual." For arm or thumb the PC should +// be a real PC, for dual the least significant bit will determine if it's +// ARM or Thumb mode. + +#define block_lookup_address_pc_arm() \ + pc &= ~0x03 + +#define block_lookup_address_pc_thumb() \ + pc &= ~0x01 \ + +#define block_lookup_address_pc_dual() \ + u32 thumb = pc & 0x01; \ + \ + if(thumb) \ + { \ + pc--; \ + reg[REG_CPSR] |= 0x20; \ + } \ + else \ + { \ + pc = (pc + 2) & ~0x03; \ + reg[REG_CPSR] &= ~0x20; \ + } \ + +#define ram_translation_region TRANSLATION_REGION_RAM +#define rom_translation_region TRANSLATION_REGION_ROM +#define bios_translation_region TRANSLATION_REGION_BIOS + +#define block_lookup_translate_arm(mem_type, smc_enable) \ + translation_result = translate_block_arm(pc, mem_type##_translation_region, \ + smc_enable) \ + +#define block_lookup_translate_thumb(mem_type, smc_enable) \ + translation_result = translate_block_thumb(pc, \ + mem_type##_translation_region, smc_enable) \ + +#define block_lookup_translate_dual(mem_type, smc_enable) \ + if(thumb) \ + { \ + translation_result = translate_block_thumb(pc, \ + mem_type##_translation_region, smc_enable); \ + } \ + else \ + { \ + translation_result = translate_block_arm(pc, \ + mem_type##_translation_region, smc_enable); \ + } \ + +// 0x0101 is the smallest tag that can be used. 0xFFFF is marked +// in the middle of blocks and used for write guarding, it doesn't +// indicate a valid block either (it's okay to compile a new block +// that overlaps the earlier one, although this should be relatively +// uncommon) + +#define fill_tag_arm(mem_type) \ + location[0] = mem_type##_block_tag_top; \ + location[1] = 0xFFFF \ + +#define fill_tag_thumb(mem_type) \ + *location = mem_type##_block_tag_top \ + +#define fill_tag_dual(mem_type) \ + if(thumb) \ + fill_tag_thumb(mem_type); \ + else \ + fill_tag_arm(mem_type) \ + +#define block_lookup_translate(instruction_type, mem_type, smc_enable) \ + block_tag = *location; \ + if((block_tag < 0x0101) || (block_tag == 0xFFFF)) \ + { \ + __label__ redo; \ + s32 translation_result; \ + \ + redo: \ + \ + translation_recursion_level++; \ + block_address = mem_type##_translation_ptr + block_prologue_size; \ + mem_type##_block_ptrs[mem_type##_block_tag_top] = block_address; \ + fill_tag_##instruction_type(mem_type); \ + mem_type##_block_tag_top++; \ + \ + block_lookup_translate_##instruction_type(mem_type, smc_enable); \ + translation_recursion_level--; \ + \ + /* If the translation failed then pass that failure on if we're in \ + a recursive level, or try again if we've hit the bottom. */ \ + if(translation_result == -1) \ + { \ + if(translation_recursion_level) \ + return NULL; \ + \ + goto redo; \ + } \ + \ + if(translation_recursion_level == 0) \ + translate_invalidate_dcache(); \ + } \ + else \ + { \ + block_address = mem_type##_block_ptrs[block_tag]; \ + } \ + +u32 translation_recursion_level = 0; +u32 translation_flush_count = 0; + + +#define block_lookup_address_builder(type) \ +u8 function_cc *block_lookup_address_##type(u32 pc) \ +{ \ + u16 *location; \ + u32 block_tag; \ + u8 *block_address; \ + \ + /* Starting at the beginning, we allow for one translation cache flush. */ \ + if(translation_recursion_level == 0) \ + translation_flush_count = 0; \ + block_lookup_address_pc_##type(); \ + \ + switch(pc >> 24) \ + { \ + case 0x0: \ + bios_region_read_allow(); \ + location = (u16 *)(bios_rom + pc + 0x4000); \ + block_lookup_translate(type, bios, 0); \ + if(translation_recursion_level == 0) \ + bios_region_read_allow(); \ + break; \ + \ + case 0x2: \ + location = (u16 *)(ewram + (pc & 0x7FFF) + ((pc & 0x38000) * 2)); \ + block_lookup_translate(type, ram, 1); \ + if(translation_recursion_level == 0) \ + bios_region_read_protect(); \ + break; \ + \ + case 0x3: \ + location = (u16 *)(iwram + (pc & 0x7FFF)); \ + block_lookup_translate(type, ram, 1); \ + if(translation_recursion_level == 0) \ + bios_region_read_protect(); \ + break; \ + \ + case 0x8 ... 0xD: \ + { \ + u32 hash_target = ((pc * 2654435761U) >> 16) & \ + (ROM_BRANCH_HASH_SIZE - 1); \ + u32 *block_ptr = rom_branch_hash[hash_target]; \ + u32 **block_ptr_address = rom_branch_hash + hash_target; \ + \ + while(block_ptr) \ + { \ + if(block_ptr[0] == pc) \ + { \ + block_address = (u8 *)(block_ptr + 2) + block_prologue_size; \ + break; \ + } \ + \ + block_ptr_address = (u32 **)(block_ptr + 1); \ + block_ptr = (u32 *)block_ptr[1]; \ + } \ + \ + if(block_ptr == NULL) \ + { \ + __label__ redo; \ + s32 translation_result; \ + \ + redo: \ + \ + translation_recursion_level++; \ + ((u32 *)rom_translation_ptr)[0] = pc; \ + ((u32 **)rom_translation_ptr)[1] = NULL; \ + *block_ptr_address = (u32 *)rom_translation_ptr; \ + rom_translation_ptr += 8; \ + block_address = rom_translation_ptr + block_prologue_size; \ + block_lookup_translate_##type(rom, 0); \ + translation_recursion_level--; \ + \ + /* If the translation failed then pass that failure on if we're in \ + a recursive level, or try again if we've hit the bottom. */ \ + if(translation_result == -1) \ + { \ + if(translation_recursion_level) \ + return NULL; \ + \ + goto redo; \ + } \ + \ + if(translation_recursion_level == 0) \ + translate_invalidate_dcache(); \ + } \ + if(translation_recursion_level == 0) \ + bios_region_read_protect(); \ + break; \ + } \ + \ + default: \ + /* If we're at the bottom, it means we're actually trying to jump to an \ + address that we can't handle. Otherwise, it means that code scanned \ + has reached an address that can't be handled, which means that we \ + have most likely hit an area that doesn't contain code yet (for \ + instance, in RAM). If such a thing happens, return -1 and the \ + block translater will naively link it (it'll be okay, since it \ + should never be hit) */ \ + if(translation_recursion_level == 0) \ + { \ + char buffer[256]; \ + sprintf(buffer, "bad jump %x (%x) (%x)\n", pc, reg[REG_PC], \ + last_instruction); \ + printf(buffer); \ + quit(); \ + } \ + block_address = (u8 *)(-1); \ + break; \ + } \ + \ + return block_address; \ +} \ + +block_lookup_address_builder(arm); +block_lookup_address_builder(thumb); +block_lookup_address_builder(dual); + +// Potential exit point: If the rd field is pc for instructions is 0x0F, +// the instruction is b/bl/bx, or the instruction is ldm with PC in the +// register list. +// All instructions with upper 3 bits less than 100b have an rd field +// except bx, where the bits must be 0xF there anyway, multiplies, +// which cannot have 0xF in the corresponding fields, and msr, which +// has 0x0F there but doesn't end things (therefore must be special +// checked against). Because MSR and BX overlap both are checked for. + +#define arm_exit_point \ + (((opcode < 0x8000000) && ((opcode & 0x000F000) == 0x000F000) && \ + ((opcode & 0xDB0F000) != 0x120F000)) || \ + ((opcode & 0x12FFF10) == 0x12FFF10) || \ + ((opcode & 0x8108000) == 0x8108000) || \ + ((opcode >= 0xA000000) && (opcode < 0xF000000)) || \ + ((opcode > 0xF000000) && (!swi_hle_handle[((opcode >> 16) & 0xFF)]))) \ + +#define arm_opcode_branch \ + ((opcode & 0xE000000) == 0xA000000) \ + +#define arm_opcode_swi \ + ((opcode & 0xF000000) == 0xF000000) \ + +#define arm_opcode_unconditional_branch \ + (condition == 0x0E) \ + +#define arm_load_opcode() \ + opcode = address32(pc_address_block, (block_end_pc & 0x7FFF)); \ + condition = opcode >> 28; \ + \ + opcode &= 0xFFFFFFF; \ + \ + block_end_pc += 4 \ + +#define arm_branch_target() \ + branch_target = (block_end_pc + 4 + (((s32)(opcode & 0xFFFFFF) << 8) >> 6)) \ + +// Contiguous conditional block flags modification - it will set 0x20 in the +// condition's bits if this instruction modifies flags. Taken from the CPU +// switch so it'd better be right this time. + +#define arm_set_condition(_condition) \ + block_data[block_data_position].condition = _condition; \ + switch((opcode >> 20) & 0xFF) \ + { \ + case 0x01: \ + case 0x03: \ + case 0x09: \ + case 0x0B: \ + case 0x0D: \ + case 0x0F: \ + if((((opcode >> 5) & 0x03) == 0) || ((opcode & 0x90) != 0x90)) \ + block_data[block_data_position].condition |= 0x20; \ + break; \ + \ + case 0x05: \ + case 0x07: \ + case 0x11: \ + case 0x13: \ + case 0x15 ... 0x17: \ + case 0x19: \ + case 0x1B: \ + case 0x1D: \ + case 0x1F: \ + if((opcode & 0x90) != 0x90) \ + block_data[block_data_position].condition |= 0x20; \ + break; \ + \ + case 0x12: \ + if(((opcode & 0x90) != 0x90) && !(opcode & 0x10)) \ + block_data[block_data_position].condition |= 0x20; \ + break; \ + \ + case 0x21: \ + case 0x23: \ + case 0x25: \ + case 0x27: \ + case 0x29: \ + case 0x2B: \ + case 0x2D: \ + case 0x2F ... 0x37: \ + case 0x39: \ + case 0x3B: \ + case 0x3D: \ + case 0x3F: \ + block_data[block_data_position].condition |= 0x20; \ + break; \ + } \ + +#define arm_link_block() \ + translation_target = block_lookup_address_arm(branch_target) \ + +#define arm_instruction_width 4 + +#define arm_base_cycles() \ + cycle_count += waitstate_cycles_sequential[pc >> 24][2] \ + +// For now this just sets a variable that says flags should always be +// computed. + +#define arm_dead_flag_eliminate() \ + flag_status = 0xF \ + +// The following Thumb instructions can exit: +// b, bl, bx, swi, pop {... pc}, and mov pc, ..., the latter being a hireg +// op only. Rather simpler to identify than the ARM set. + +#define thumb_exit_point \ + (((opcode >= 0xD000) && (opcode < 0xDF00)) || \ + (((opcode & 0xFF00) == 0xDF00) && \ + (!swi_hle_handle[opcode & 0xFF])) || \ + ((opcode >= 0xE000) && (opcode < 0xE800)) || \ + ((opcode & 0xFF00) == 0x4700) || \ + ((opcode & 0xFF00) == 0xBD00) || \ + ((opcode & 0xFF87) == 0x4687) || \ + ((opcode >= 0xF800))) \ + +#define thumb_opcode_branch \ + (((opcode >= 0xD000) && (opcode < 0xDF00)) || \ + ((opcode >= 0xE000) && (opcode < 0xE800)) || \ + (opcode >= 0xF800)) \ + +#define thumb_opcode_swi \ + ((opcode & 0xFF00) == 0xDF00) \ + +#define thumb_opcode_unconditional_branch \ + ((opcode < 0xD000) || (opcode >= 0xDF00)) \ + +#define thumb_load_opcode() \ + last_opcode = opcode; \ + opcode = address16(pc_address_block, (block_end_pc & 0x7FFF)); \ + \ + block_end_pc += 2 \ + +#define thumb_branch_target() \ + if(opcode < 0xE000) \ + { \ + branch_target = block_end_pc + 2 + ((s8)(opcode & 0xFF) * 2); \ + } \ + else \ + \ + if(opcode < 0xF800) \ + { \ + branch_target = block_end_pc + 2 + ((s32)((opcode & 0x7FF) << 21) >> 20); \ + } \ + else \ + { \ + if((last_opcode >= 0xF000) && (last_opcode < 0xF800)) \ + { \ + branch_target = \ + (block_end_pc + ((s32)((last_opcode & 0x07FF) << 21) >> 9) + \ + ((opcode & 0x07FF) * 2)); \ + } \ + else \ + { \ + goto no_direct_branch; \ + } \ + } \ + +#define thumb_set_condition(_condition) \ + +#define thumb_link_block() \ + if(branch_target != 0x00000008) \ + translation_target = block_lookup_address_thumb(branch_target); \ + else \ + translation_target = block_lookup_address_arm(branch_target) \ + +#define thumb_instruction_width 2 + +#define thumb_base_cycles() \ + cycle_count += waitstate_cycles_sequential[pc >> 24][1] \ + +// Here's how this works: each instruction has three different sets of flag +// attributes, each consisiting of a 4bit mask describing how that instruction +// interacts with the 4 main flags (N/Z/C/V). +// The first set, in bits 0:3, is the set of flags the instruction may +// modify. After this pass this is changed to the set of flags the instruction +// should modify - if the bit for the corresponding flag is not set then code +// does not have to be generated to calculate the flag for that instruction. + +// The second set, in bits 7:4, is the set of flags that the instruction must +// modify (ie, for shifts by the register values the instruction may not +// always modify the C flag, and thus the C bit won't be set here). + +// The third set, in bits 11:8, is the set of flags that the instruction uses +// in its computation, or the set of flags that will be needed after the +// instruction is done. For any instructions that change the PC all of the +// bits should be set because it is (for now) unknown what flags will be +// needed after it arrives at its destination. Instructions that use the +// carry flag as input will have it set as well. + +// The algorithm is a simple liveness analysis procedure: It starts at the +// bottom of the instruction stream and sets a "currently needed" mask to +// the flags needed mask of the current instruction. Then it moves down +// an instruction, ANDs that instructions "should generate" mask by the +// "currently needed" mask, then ANDs the "currently needed" mask by +// the 1's complement of the instruction's "must generate" mask, and ORs +// the "currently needed" mask by the instruction's "flags needed" mask. + +#define thumb_dead_flag_eliminate() \ +{ \ + u32 needed_mask; \ + needed_mask = block_data[block_data_position].flag_data >> 8; \ + \ + block_data_position--; \ + while(block_data_position >= 0) \ + { \ + flag_status = block_data[block_data_position].flag_data; \ + block_data[block_data_position].flag_data = \ + (flag_status & needed_mask); \ + needed_mask &= ~((flag_status >> 4) & 0x0F); \ + needed_mask |= flag_status >> 8; \ + block_data_position--; \ + } \ +} \ + +#define MAX_BLOCK_SIZE 8192 +#define MAX_EXITS 256 + +block_data_type block_data[MAX_BLOCK_SIZE]; +block_exit_type block_exits[MAX_EXITS]; + +#define smc_write_arm_yes() \ + if(address32(pc_address_block, (block_end_pc & 0x7FFF) - 0x8000) == 0x0000) \ + { \ + address32(pc_address_block, (block_end_pc & 0x7FFF) - 0x8000) = \ + 0xFFFFFFFF; \ + } \ + +#define smc_write_thumb_yes() \ + if(address16(pc_address_block, (block_end_pc & 0x7FFF) - 0x8000) == 0x0000) \ + { \ + address16(pc_address_block, (block_end_pc & 0x7FFF) - 0x8000) = 0xFFFF; \ + } \ + +#define smc_write_arm_no() \ + +#define smc_write_thumb_no() \ + +#define scan_block(type, smc_write_op) \ +{ \ + __label__ block_end; \ + /* Find the end of the block */ \ + do \ + { \ + check_pc_region(block_end_pc); \ + smc_write_##type##_##smc_write_op(); \ + type##_load_opcode(); \ + type##_flag_status(); \ + \ + if(type##_exit_point) \ + { \ + /* Branch/branch with link */ \ + if(type##_opcode_branch) \ + { \ + __label__ no_direct_branch; \ + type##_branch_target(); \ + block_exits[block_exit_position].branch_target = branch_target; \ + block_exit_position++; \ + \ + /* Give the branch target macro somewhere to bail if it turns out to \ + be an indirect branch (ala malformed Thumb bl) */ \ + no_direct_branch:; \ + } \ + \ + /* SWI branches to the BIOS, this will likely change when \ + some HLE BIOS is implemented. */ \ + if(type##_opcode_swi) \ + { \ + block_exits[block_exit_position].branch_target = 0x00000008; \ + block_exit_position++; \ + } \ + \ + type##_set_condition(condition | 0x10); \ + \ + /* Only unconditional branches can end the block. */ \ + if(type##_opcode_unconditional_branch) \ + { \ + /* Check to see if any prior block exits branch after here, \ + if so don't end the block. Starts from the top and works \ + down because the most recent branch is most likely to \ + join after the end (if/then form) */ \ + for(i = block_exit_position - 2; i >= 0; i--) \ + { \ + if(block_exits[i].branch_target == block_end_pc) \ + break; \ + } \ + \ + if(i < 0) \ + break; \ + } \ + if(block_exit_position == MAX_EXITS) \ + break; \ + } \ + else \ + { \ + type##_set_condition(condition); \ + } \ + \ + for(i = 0; i < translation_gate_targets; i++) \ + { \ + if(block_end_pc == translation_gate_target_pc[i]) \ + goto block_end; \ + } \ + \ + block_data[block_data_position].update_cycles = 0; \ + block_data_position++; \ + if((block_data_position == MAX_BLOCK_SIZE) || \ + (block_end_pc == 0x3007FF0) || (block_end_pc == 0x203FFFF0)) \ + { \ + break; \ + } \ + } while(1); \ + \ + block_end:; \ +} \ + +#define arm_fix_pc() \ + pc &= ~0x03 \ + +#define thumb_fix_pc() \ + pc &= ~0x01 \ + +#define translate_block_builder(type) \ +s32 translate_block_##type(u32 pc, translation_region_type \ + translation_region, u32 smc_enable) \ +{ \ + u32 opcode; \ + u32 last_opcode; \ + u32 condition; \ + u32 last_condition; \ + u32 pc_region = (pc >> 15); \ + u32 new_pc_region; \ + u8 *pc_address_block = memory_map_read[pc_region]; \ + u32 block_start_pc = pc; \ + u32 block_end_pc = pc; \ + u32 block_exit_position = 0; \ + s32 block_data_position = 0; \ + u32 external_block_exit_position = 0; \ + u32 branch_target; \ + u32 cycle_count = 0; \ + u8 *translation_target; \ + u8 *backpatch_address; \ + u8 *translation_ptr; \ + u8 *translation_cache_limit; \ + s32 i; \ + u32 flag_status; \ + block_exit_type external_block_exits[MAX_EXITS]; \ + generate_block_extra_vars_##type(); \ + type##_fix_pc(); \ + \ + if(pc_address_block == NULL) \ + pc_address_block = load_gamepak_page(pc_region & 0x3FF); \ + \ + switch(translation_region) \ + { \ + case TRANSLATION_REGION_RAM: \ + if(pc >= 0x3000000) \ + { \ + if((pc < iwram_code_min) || (iwram_code_min == 0xFFFFFFFF)) \ + iwram_code_min = pc; \ + } \ + else \ + \ + if(pc >= 0x2000000) \ + { \ + if((pc < ewram_code_min) || (ewram_code_min == 0xFFFFFFFF)) \ + ewram_code_min = pc; \ + } \ + \ + translation_ptr = ram_translation_ptr; \ + translation_cache_limit = \ + ram_translation_cache + RAM_TRANSLATION_CACHE_SIZE - \ + TRANSLATION_CACHE_LIMIT_THRESHOLD; \ + break; \ + \ + case TRANSLATION_REGION_ROM: \ + translation_ptr = rom_translation_ptr; \ + translation_cache_limit = \ + rom_translation_cache + ROM_TRANSLATION_CACHE_SIZE - \ + TRANSLATION_CACHE_LIMIT_THRESHOLD; \ + break; \ + \ + case TRANSLATION_REGION_BIOS: \ + translation_ptr = bios_translation_ptr; \ + translation_cache_limit = bios_translation_cache + \ + BIOS_TRANSLATION_CACHE_SIZE; \ + break; \ + } \ + \ + generate_block_prologue(); \ + \ + /* This is a function because it's used a lot more than it might seem (all \ + of the data processing functions can access it), and its expansion was \ + massacreing the compiler. */ \ + \ + if(smc_enable) \ + { \ + scan_block(type, yes); \ + } \ + else \ + { \ + scan_block(type, no); \ + } \ + \ + for(i = 0; i < block_exit_position; i++) \ + { \ + branch_target = block_exits[i].branch_target; \ + \ + if((branch_target > block_start_pc) && \ + (branch_target < block_end_pc)) \ + { \ + block_data[(branch_target - block_start_pc) / \ + type##_instruction_width].update_cycles = 1; \ + } \ + } \ + \ + type##_dead_flag_eliminate(); \ + \ + block_exit_position = 0; \ + block_data_position = 0; \ + \ + last_condition = 0x0E; \ + \ + while(pc != block_end_pc) \ + { \ + block_data[block_data_position].block_offset = translation_ptr; \ + type##_base_cycles(); \ + /*generate_step_debug();*/ \ + \ + translate_##type##_instruction(); \ + block_data_position++; \ + \ + /* If it went too far the cache needs to be flushed and the process \ + restarted. Because we might already be nested several stages in \ + a simple recursive call here won't work, it has to pedal out to \ + the beginning. */ \ + \ + if(translation_ptr > translation_cache_limit) \ + { \ + translation_flush_count++; \ + \ + switch(translation_region) \ + { \ + case TRANSLATION_REGION_RAM: \ + flush_translation_cache_ram(); \ + break; \ + \ + case TRANSLATION_REGION_ROM: \ + flush_translation_cache_rom(); \ + break; \ + \ + case TRANSLATION_REGION_BIOS: \ + flush_translation_cache_bios(); \ + break; \ + } \ + \ + return -1; \ + } \ + \ + /* If the next instruction is a block entry point update the \ + cycle counter and update */ \ + if(block_data[block_data_position].update_cycles == 1) \ + { \ + generate_cycle_update(); \ + } \ + } \ + for(i = 0; i < translation_gate_targets; i++) \ + { \ + if(pc == translation_gate_target_pc[i]) \ + { \ + generate_translation_gate(type); \ + break; \ + } \ + } \ + \ + for(i = 0; i < block_exit_position; i++) \ + { \ + branch_target = block_exits[i].branch_target; \ + \ + if((branch_target >= block_start_pc) && (branch_target < block_end_pc)) \ + { \ + /* Internal branch, patch to recorded address */ \ + translation_target = \ + block_data[(branch_target - block_start_pc) / \ + type##_instruction_width].block_offset; \ + \ + generate_branch_patch_unconditional(block_exits[i].branch_source, \ + translation_target); \ + } \ + else \ + { \ + /* External branch, save for later */ \ + external_block_exits[external_block_exit_position].branch_target = \ + branch_target; \ + external_block_exits[external_block_exit_position].branch_source = \ + block_exits[i].branch_source; \ + external_block_exit_position++; \ + } \ + } \ + \ + switch(translation_region) \ + { \ + case TRANSLATION_REGION_RAM: \ + if(pc >= 0x3000000) \ + { \ + if((pc > iwram_code_max) || (iwram_code_max == 0xFFFFFFFF)) \ + iwram_code_max = pc; \ + } \ + else \ + \ + if(pc >= 0x2000000) \ + { \ + if((pc > ewram_code_max) || (ewram_code_max == 0xFFFFFFFF)) \ + ewram_code_max = pc; \ + } \ + \ + ram_translation_ptr = translation_ptr; \ + break; \ + \ + case TRANSLATION_REGION_ROM: \ + rom_translation_ptr = translation_ptr; \ + break; \ + \ + case TRANSLATION_REGION_BIOS: \ + bios_translation_ptr = translation_ptr; \ + break; \ + } \ + \ + for(i = 0; i < external_block_exit_position; i++) \ + { \ + branch_target = external_block_exits[i].branch_target; \ + type##_link_block(); \ + if(translation_target == NULL) \ + return -1; \ + generate_branch_patch_unconditional( \ + external_block_exits[i].branch_source, translation_target); \ + } \ + \ + return 0; \ +} \ + +translate_block_builder(arm); +translate_block_builder(thumb); + +void flush_translation_cache_ram() +{ + flush_ram_count++; +/* printf("ram flush %d (pc %x), %x to %x, %x to %x\n", + flush_ram_count, reg[REG_PC], iwram_code_min, iwram_code_max, + ewram_code_min, ewram_code_max); */ + +#ifndef PC_BUILD + invalidate_icache_region(ram_translation_cache, + (ram_translation_ptr - ram_translation_cache) + 0x100); +#endif + ram_translation_ptr = ram_translation_cache; + ram_block_tag_top = 0x0101; + if(iwram_code_min != 0xFFFFFFFF) + { + iwram_code_min &= 0x7FFF; + iwram_code_max &= 0x7FFF; + memset(iwram + iwram_code_min, 0, iwram_code_max - iwram_code_min); + } + + if(ewram_code_min != 0xFFFFFFFF) + { + u32 ewram_code_min_page; + u32 ewram_code_max_page; + u32 ewram_code_min_offset; + u32 ewram_code_max_offset; + u32 i; + + ewram_code_min &= 0x3FFFF; + ewram_code_max &= 0x3FFFF; + + ewram_code_min_page = ewram_code_min >> 15; + ewram_code_max_page = ewram_code_max >> 15; + ewram_code_min_offset = ewram_code_min & 0x7FFF; + ewram_code_max_offset = ewram_code_max & 0x7FFF; + + if(ewram_code_min_page == ewram_code_max_page) + { + memset(ewram + (ewram_code_min_page * 0x10000) + + ewram_code_min_offset, 0, + ewram_code_max_offset - ewram_code_min_offset); + } + else + { + for(i = ewram_code_min_page + 1; i < ewram_code_max_page; i++) + { + memset(ewram + (i * 0x10000), 0, 0x8000); + } + + memset(ewram, 0, ewram_code_max_offset); + } + } + + iwram_code_min = 0xFFFFFFFF; + iwram_code_max = 0xFFFFFFFF; + ewram_code_min = 0xFFFFFFFF; + ewram_code_max = 0xFFFFFFFF; +} + +void flush_translation_cache_rom() +{ +#ifndef PC_BUILD + invalidate_icache_region(rom_translation_cache, + rom_translation_ptr - rom_translation_cache + 0x100); +#endif + + rom_translation_ptr = rom_translation_cache; + memset(rom_branch_hash, 0, sizeof(rom_branch_hash)); +} + +void flush_translation_cache_bios() +{ +#ifndef PC_BUILD + invalidate_icache_region(bios_translation_cache, + bios_translation_ptr - bios_translation_cache + 0x100); +#endif + + bios_block_tag_top = 0x0101; + bios_translation_ptr = bios_translation_cache; + memset(bios_rom + 0x4000, 0, 0x4000); +} + +#ifdef GP2X_BUILD + #define cache_dump_prefix "/mnt/nand/" +#else + #define cache_dump_prefix "" +#endif + +void dump_translation_cache() +{ + file_open(ram_cache, cache_dump_prefix "ram_cache.bin", write); + file_write(ram_cache, ram_translation_cache, + ram_translation_ptr - ram_translation_cache); + file_close(ram_cache); + + file_open(rom_cache, cache_dump_prefix "rom_cache.bin", write); + file_write(rom_cache, rom_translation_cache, + rom_translation_ptr - rom_translation_cache); + file_close(rom_cache); + + file_open(bios_cache, cache_dump_prefix "bios_cache.bin", write); + file_write(bios_cache, bios_translation_cache, + bios_translation_ptr - bios_translation_cache); + file_close(bios_cache); +} + diff --git a/disasm.c b/disasm.c new file mode 100644 index 0000000..601584f --- /dev/null +++ b/disasm.c @@ -0,0 +1,184 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#define arm_decode_data_proc_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_data_proc_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm; \ + ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ + +#define arm_decode_psr_reg() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_psr_imm() \ + u32 psr_field = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 imm; \ + ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ + +#define arm_decode_branchx() \ + u32 rn = opcode & 0x0F \ + +#define arm_decode_multiply() \ + u32 rd = (opcode >> 16) & 0x0F; \ + u32 rn = (opcode >> 12) & 0x0F; \ + u32 rs = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_multiply_long() \ + u32 rdhi = (opcode >> 16) & 0x0F; \ + u32 rdlo = (opcode >> 12) & 0x0F; \ + u32 rn = (opcode >> 8) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_swap() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_half_trans_r() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_half_trans_of() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F) \ + +#define arm_decode_data_trans_imm() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 offset = opcode & 0x0FFF \ + +#define arm_decode_data_trans_reg() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 rd = (opcode >> 12) & 0x0F; \ + u32 rm = opcode & 0x0F \ + +#define arm_decode_block_trans() \ + u32 rn = (opcode >> 16) & 0x0F; \ + u32 reg_list = opcode & 0xFFFF \ + +#define arm_decode_branch() \ + s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \ + +#define thumb_decode_shift() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sub() \ + u32 rn = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sub_imm() \ + u32 imm = (opcode >> 6) & 0x07; \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_imm() \ + u32 imm = opcode & 0xFF \ + +#define thumb_decode_alu_op() \ + u32 rs = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_hireg_op() \ + u32 rs = (opcode >> 3) & 0x0F; \ + u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07) \ + +#define thumb_decode_mem_reg() \ + u32 ro = (opcode >> 6) & 0x07; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_mem_imm() \ + u32 imm = (opcode >> 6) & 0x1F; \ + u32 rb = (opcode >> 3) & 0x07; \ + u32 rd = opcode & 0x07 \ + +#define thumb_decode_add_sp() \ + u32 imm = opcode & 0x7F \ + +#define thumb_decode_rlist() \ + u32 reg_list = opcode & 0xFF \ + +#define thumb_decode_branch_cond() \ + s32 offset = (s8)(opcode & 0xFF) \ + +#define thumb_decode_swi() \ + u32 comment = opcode & 0xFF \ + +#define thumb_decode_branch() \ + u32 offset = opcode & 0x07FF \ + +const char *condition_table[] = +{ + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" +}; + +const char *data_proc_opcode_table[] = +{ + "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", + "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" +}; + + +u32 print_disasm_arm_instruction(u32 opcode) +{ + u32 condition = opcode >> 28; + + switch((opcode >> 25) & 0x07) + { + // Data processing reg, multiply, bx, memory transfer half/byte, swap, + // PSR reg + case 0x0: + + // Data processing imm, PSR imm + case 0x1: + + // Memory transfer imm + case 0x2: + + // Memory transfer reg, undefined + case 0x3: + + // Block memory transfer + case 0x4: + + // Branch + case 0x5: + + // Coprocessor + case 0x6: + + // Coprocessor, SWI + case 0x7: + } \ No newline at end of file diff --git a/font.h b/font.h new file mode 100644 index 0000000..27f6200 --- /dev/null +++ b/font.h @@ -0,0 +1,5878 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Generated by convbdf on Fri Aug 18 17:44:10 2006. */ +/* Slightly modified by Exophase. Big thanks to ajs for converting this! */ + +#define FONT_WIDTH 6 +#define FONT_HEIGHT 10 + +/* Font information: + name: 6x10 + facename: -Misc-Fixed-Medium-R-Normal--10-100-75-75-C-60-ISO8859-1 + w x h: 6x10 + size: 256 + ascent: 8 + descent: 2 + first char: 0 (0x00) + last char: 255 (0xff) + default char: 0 (0x00) + proportional: no + Public domain terminal emulator font. Share and enjoy. +*/ + +/* Font character bitmap data. */ +static u16 _font_bits[2230] = +{ +/* Character 0 (0x00): + width 6 + +------+ + | | + |* * * | + | | + |* * | + | | + |* * | + | | + |* * * | + | | + | | + +------+ */ +0x0000, +0xa800, +0x0000, +0x8800, +0x0000, +0x8800, +0x0000, +0xa800, +0x0000, +0x0000, + +/* Character 1 (0x01): + width 6 + +------+ + | | + | | + | * | + | *** | + |***** | + | *** | + | * | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x7000, +0xf800, +0x7000, +0x2000, +0x0000, +0x0000, +0x0000, + +/* Character 2 (0x02): + width 6 + +------+ + |* * * | + | * * *| + |* * * | + | * * *| + |* * * | + | * * *| + |* * * | + | * * *| + |* * * | + | * * *| + +------+ */ +0xa800, +0x5400, +0xa800, +0x5400, +0xa800, +0x5400, +0xa800, +0x5400, +0xa800, +0x5400, + +/* Character 3 (0x03): + width 6 + +------+ + | | + |* * | + |* * | + |**** | + |* * | + |* * | + | **** | + | * | + | * | + | * | + +------+ */ +0x0000, +0x9000, +0x9000, +0xf000, +0x9000, +0x9000, +0x7800, +0x1000, +0x1000, +0x1000, + +/* Character 4 (0x04): + width 6 + +------+ + | | + |*** | + |* | + |** | + |* | + |* *** | + | * | + | ** | + | * | + | * | + +------+ */ +0x0000, +0xe000, +0x8000, +0xc000, +0x8000, +0xb800, +0x2000, +0x3000, +0x2000, +0x2000, + +/* Character 5 (0x05): + width 6 + +------+ + | | + | *** | + |* | + |* | + | *** | + | *** | + | * * | + | *** | + | * * | + | * * | + +------+ */ +0x0000, +0x7000, +0x8000, +0x8000, +0x7000, +0x7000, +0x4800, +0x7000, +0x4800, +0x4800, + +/* Character 6 (0x06): + width 6 + +------+ + | | + |* | + |* | + |* | + |**** | + | **** | + | * | + | *** | + | * | + | * | + +------+ */ +0x0000, +0x8000, +0x8000, +0x8000, +0xf000, +0x7800, +0x4000, +0x7000, +0x4000, +0x4000, + +/* Character 7 (0x07): + width 6 + +------+ + | | + | * | + | * * | + | * | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x2000, +0x5000, +0x2000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 8 (0x08): + width 6 + +------+ + | | + | | + | * | + | * | + |***** | + | * | + | * | + |***** | + | | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x2000, +0xf800, +0x2000, +0x2000, +0xf800, +0x0000, +0x0000, + +/* Character 9 (0x09): + width 6 + +------+ + | | + |* * | + |** * | + |** * | + |* ** | + |* * | + | * | + | * | + | * | + | **** | + +------+ */ +0x0000, +0x9000, +0xd000, +0xd000, +0xb000, +0x9000, +0x4000, +0x4000, +0x4000, +0x7800, + +/* Character 10 (0x0a): + width 6 + +------+ + | | + |* * | + |* * | + | ** | + | * | + | **** | + | * | + | * | + | * | + | * | + +------+ */ +0x0000, +0x9000, +0x9000, +0x6000, +0x4000, +0x7800, +0x1000, +0x1000, +0x1000, +0x1000, + +/* Character 11 (0x0b): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + |*** | + | | + | | + | | + | | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0xe000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 12 (0x0c): + width 6 + +------+ + | | + | | + | | + | | + | | + |*** | + | * | + | * | + | * | + | * | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xe000, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 13 (0x0d): + width 6 + +------+ + | | + | | + | | + | | + | | + | ****| + | * | + | * | + | * | + | * | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x3c00, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 14 (0x0e): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + | ****| + | | + | | + | | + | | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x3c00, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 15 (0x0f): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + |******| + | * | + | * | + | * | + | * | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0xfc00, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 16 (0x10): + width 6 + +------+ + |******| + | | + | | + | | + | | + | | + | | + | | + | | + | | + +------+ */ +0xfc00, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 17 (0x11): + width 6 + +------+ + | | + | | + |******| + | | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0xfc00, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 18 (0x12): + width 6 + +------+ + | | + | | + | | + | | + | | + |******| + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xfc00, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 19 (0x13): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | | + |******| + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xfc00, +0x0000, +0x0000, + +/* Character 20 (0x14): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + |******| + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xfc00, + +/* Character 21 (0x15): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + | ****| + | * | + | * | + | * | + | * | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x3c00, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 22 (0x16): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + |*** | + | * | + | * | + | * | + | * | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0xe000, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 23 (0x17): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + |******| + | | + | | + | | + | | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0xfc00, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 24 (0x18): + width 6 + +------+ + | | + | | + | | + | | + | | + |******| + | * | + | * | + | * | + | * | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xfc00, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 25 (0x19): + width 6 + +------+ + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + +------+ */ +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, + +/* Character 26 (0x1a): + width 6 + +------+ + | | + | ** | + | ** | + |* | + | ** | + | ** | + | | + |***** | + | | + | | + +------+ */ +0x0000, +0x1800, +0x6000, +0x8000, +0x6000, +0x1800, +0x0000, +0xf800, +0x0000, +0x0000, + +/* Character 27 (0x1b): + width 6 + +------+ + | | + |** | + | ** | + | * | + | ** | + |** | + | | + |***** | + | | + | | + +------+ */ +0x0000, +0xc000, +0x3000, +0x0800, +0x3000, +0xc000, +0x0000, +0xf800, +0x0000, +0x0000, + +/* Character 28 (0x1c): + width 6 + +------+ + | | + | | + | | + |***** | + | * * | + | * * | + | * * | + | * * | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0xf800, +0x5000, +0x5000, +0x5000, +0x5000, +0x0000, +0x0000, + +/* Character 29 (0x1d): + width 6 + +------+ + | | + | * | + | * | + |***** | + | * | + |***** | + | * | + |* | + | | + | | + +------+ */ +0x0000, +0x0800, +0x1000, +0xf800, +0x2000, +0xf800, +0x4000, +0x8000, +0x0000, +0x0000, + +/* Character 30 (0x1e): + width 6 + +------+ + | | + | ** | + | * * | + | * | + |*** | + | * | + | * * | + |* ** | + | | + | | + +------+ */ +0x0000, +0x3000, +0x4800, +0x4000, +0xe000, +0x4000, +0x4800, +0xb000, +0x0000, +0x0000, + +/* Character 31 (0x1f): + width 6 + +------+ + | | + | | + | | + | | + | * | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x2000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 32 (0x20): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 33 (0x21): + width 6 + +------+ + | | + | * | + | * | + | * | + | * | + | * | + | | + | * | + | | + | | + +------+ */ +0x0000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x0000, +0x2000, +0x0000, +0x0000, + +/* Character 34 (0x22): + width 6 + +------+ + | | + | * * | + | * * | + | * * | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x5000, +0x5000, +0x5000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 35 (0x23): + width 6 + +------+ + | | + | * * | + | * * | + |***** | + | * * | + |***** | + | * * | + | * * | + | | + | | + +------+ */ +0x0000, +0x5000, +0x5000, +0xf800, +0x5000, +0xf800, +0x5000, +0x5000, +0x0000, +0x0000, + +/* Character 36 (0x24): + width 6 + +------+ + | | + | * | + | *** | + |* * | + | *** | + | * * | + | *** | + | * | + | | + | | + +------+ */ +0x0000, +0x2000, +0x7000, +0xa000, +0x7000, +0x2800, +0x7000, +0x2000, +0x0000, +0x0000, + +/* Character 37 (0x25): + width 6 + +------+ + | | + | * * | + |* * * | + | * * | + | * | + | * * | + |* * * | + |* * | + | | + | | + +------+ */ +0x0000, +0x4800, +0xa800, +0x5000, +0x2000, +0x5000, +0xa800, +0x9000, +0x0000, +0x0000, + +/* Character 38 (0x26): + width 6 + +------+ + | | + | * | + |* * | + |* * | + | * | + |* * * | + |* * | + | ** * | + | | + | | + +------+ */ +0x0000, +0x4000, +0xa000, +0xa000, +0x4000, +0xa800, +0x9000, +0x6800, +0x0000, +0x0000, + +/* Character 39 (0x27): + width 6 + +------+ + | | + | * | + | * | + | * | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x2000, +0x2000, +0x2000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 40 (0x28): + width 6 + +------+ + | | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x1000, +0x2000, +0x4000, +0x4000, +0x4000, +0x2000, +0x1000, +0x0000, +0x0000, + +/* Character 41 (0x29): + width 6 + +------+ + | | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x4000, +0x2000, +0x1000, +0x1000, +0x1000, +0x2000, +0x4000, +0x0000, +0x0000, + +/* Character 42 (0x2a): + width 6 + +------+ + | | + | | + |* * | + | * * | + |***** | + | * * | + |* * | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x8800, +0x5000, +0xf800, +0x5000, +0x8800, +0x0000, +0x0000, +0x0000, + +/* Character 43 (0x2b): + width 6 + +------+ + | | + | | + | * | + | * | + |***** | + | * | + | * | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x2000, +0xf800, +0x2000, +0x2000, +0x0000, +0x0000, +0x0000, + +/* Character 44 (0x2c): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | ** | + | * | + | * | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x3000, +0x2000, +0x4000, +0x0000, + +/* Character 45 (0x2d): + width 6 + +------+ + | | + | | + | | + | | + |***** | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0xf800, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 46 (0x2e): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | * | + | *** | + | * | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x2000, +0x7000, +0x2000, +0x0000, + +/* Character 47 (0x2f): + width 6 + +------+ + | | + | * | + | * | + | * | + | * | + | * | + |* | + |* | + | | + | | + +------+ */ +0x0000, +0x0800, +0x0800, +0x1000, +0x2000, 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* | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x8800, +0x8800, +0x7000, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 57 (0x39): + width 6 + +------+ + | | + | *** | + |* * | + |* ** | + | ** * | + | * | + | * | + | ** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x8800, +0x9800, +0x6800, +0x0800, +0x1000, +0x6000, +0x0000, +0x0000, + +/* Character 58 (0x3a): + width 6 + +------+ + | | + | | + | * | + | *** | + | * | + | | + | * | + | *** | + | * | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x7000, +0x2000, +0x0000, +0x2000, +0x7000, +0x2000, +0x0000, + +/* Character 59 (0x3b): + width 6 + +------+ + | | + | | + | * | + | *** | + | * | + | | + | ** | + | * | + | * | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x7000, +0x2000, +0x0000, +0x3000, +0x2000, +0x4000, +0x0000, + +/* Character 60 (0x3c): + width 6 + +------+ + | | + | * | + | * | + | * | + | * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x0800, +0x1000, +0x2000, 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|* | + |* | + |***** | + | | + | | + +------+ */ +0x0000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0xf800, +0x0000, +0x0000, + +/* Character 70 (0x46): + width 6 + +------+ + | | + |***** | + |* | + |* | + |**** | + |* | + |* | + |* | + | | + | | + +------+ */ +0x0000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0x8000, +0x0000, +0x0000, + +/* Character 71 (0x47): + width 6 + +------+ + | | + | *** | + |* * | + |* | + |* | + |* ** | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x8800, +0x8000, +0x8000, +0x9800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 72 (0x48): + width 6 + +------+ + | | + |* * | + |* * | + |* * | + |***** | + |* * | + |* * | + |* * | + | | + | | + +------+ */ +0x0000, +0x8800, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 73 (0x49): + width 6 + +------+ + | | + | *** | + | * | + | * | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x2000, 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+0x0000, +0x8800, +0x8800, +0x8800, +0x5000, +0x5000, +0x5000, +0x2000, +0x0000, +0x0000, + +/* Character 87 (0x57): + width 6 + +------+ + | | + |* * | + |* * | + |* * | + |* * * | + |* * * | + |** ** | + |* * | + | | + | | + +------+ */ +0x0000, +0x8800, +0x8800, +0x8800, +0xa800, +0xa800, +0xd800, +0x8800, +0x0000, +0x0000, + +/* Character 88 (0x58): + width 6 + +------+ + | | + |* * | + |* * | + | * * | + | * | + | * * | + |* * | + |* * | + | | + | | + +------+ */ +0x0000, +0x8800, +0x8800, +0x5000, +0x2000, +0x5000, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 89 (0x59): + width 6 + +------+ + | | + |* * | + |* * | + | * * | + | * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x8800, +0x8800, +0x5000, +0x2000, +0x2000, +0x2000, +0x2000, +0x0000, +0x0000, + +/* Character 90 (0x5a): + width 6 + +------+ + | | + |***** | + | * | + | * | + | * | + | * | + |* | + |***** | + | | + | | + +------+ */ +0x0000, +0xf800, +0x0800, +0x1000, +0x2000, +0x4000, +0x8000, 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| | + | | + | | + | | + | | + |***** | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0xf800, +0x0000, + +/* Character 96 (0x60): + width 6 + +------+ + | * | + | * | + | | + | | + | | + | | + | | + | | + | | + | | + +------+ */ +0x2000, +0x1000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 97 (0x61): + width 6 + +------+ + | | + | | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 98 (0x62): + width 6 + +------+ + | | + |* | + |* | + |* ** | + |** * | + |* * | + |** * | + |* ** | + | | + | | + +------+ */ +0x0000, +0x8000, +0x8000, +0xb000, +0xc800, +0x8800, +0xc800, +0xb000, +0x0000, +0x0000, + +/* Character 99 (0x63): + width 6 + +------+ + | | + | | + | | + | *** | + |* * | + |* | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, 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*/ +0x0000, +0x6000, +0x1000, +0x2000, +0x1800, +0x2000, +0x1000, +0x6000, +0x0000, +0x0000, + +/* Character 126 (0x7e): + width 6 + +------+ + | | + | * * | + |* * * | + |* * | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x4800, +0xa800, +0x9000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 160 (0xa0): + width 6 + +------+ + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 161 (0xa1): + width 6 + +------+ + | | + | * | + | | + | * | + | * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x2000, +0x0000, +0x2000, +0x2000, +0x2000, +0x2000, +0x2000, +0x0000, +0x0000, + +/* Character 162 (0xa2): + width 6 + +------+ + | | + | | + | * | + | **** | + |* * | + |* * | + |* * | + | **** | + | * | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x7800, +0xa000, +0xa000, +0xa000, +0x7800, +0x2000, +0x0000, + +/* Character 163 (0xa3): + width 6 + +------+ + | | + | ** | + | * * | + | * | + |*** | + | * | + | * * | + |* ** | + | | + | | + +------+ */ +0x0000, +0x3000, +0x4800, +0x4000, +0xe000, +0x4000, +0x4800, +0xb000, +0x0000, +0x0000, + +/* Character 164 (0xa4): + width 6 + +------+ + | | + | | + | | + |* * | + | *** | + | * * | + | *** | + |* * | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x8800, +0x7000, +0x5000, +0x7000, +0x8800, +0x0000, +0x0000, + +/* Character 165 (0xa5): + width 6 + +------+ + | | + |* * | + |* * | + | * * | + | * | + |***** | + | * | + | * | + | * | + | | + +------+ */ +0x0000, +0x8800, +0x8800, +0x5000, +0x2000, +0xf800, +0x2000, +0x2000, +0x2000, +0x0000, + +/* Character 166 (0xa6): + width 6 + +------+ + | | + | * | + | * | + | * | + | | + | * | + | * | + | * | + | | + | | + +------+ */ +0x0000, +0x2000, +0x2000, +0x2000, +0x0000, +0x2000, +0x2000, +0x2000, +0x0000, +0x0000, + +/* Character 167 (0xa7): + width 6 + +------+ + | | + | *** | + |* | + |*** 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(0xb0): + width 6 + +------+ + | | + | * | + | * * | + | * | + | | + | | + | | + | | + | | + | | + +------+ */ +0x0000, +0x2000, +0x5000, +0x2000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 177 (0xb1): + width 6 + +------+ + | | + | | + | * | + | * | + |***** | + | * | + | * | + |***** | + | | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x2000, +0xf800, +0x2000, +0x2000, +0xf800, +0x0000, +0x0000, + +/* Character 178 (0xb2): + width 6 + +------+ + | ** | + | * * | + | * | + | * | + | **** | + | | + | | + | | + | | + | | + +------+ */ +0x3000, +0x4800, +0x1000, +0x2000, +0x7800, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 179 (0xb3): + width 6 + +------+ + | *** | + | * | + | ** | + | * | + | *** | + | | + | | + | | + | | + | | + +------+ */ +0x7000, +0x0800, +0x3000, +0x0800, +0x7000, +0x0000, +0x0000, +0x0000, +0x0000, +0x0000, + +/* Character 180 (0xb4): + width 6 + +------+ + | * | + | * | + | | + | | + | | + | | + | | + | | + | | + | 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|** | + | * | + | * | + |*** * | + | * *| + | *| + | * | + | ***| + | | + +------+ */ +0x4000, +0xc000, +0x4000, +0x4000, +0xe800, +0x1400, +0x0400, +0x0800, +0x1c00, +0x0000, + +/* Character 190 (0xbe): + width 6 + +------+ + |** | + | * | + | * | + | * | + |** * | + | ** | + | * * | + | **** | + | * | + | | + +------+ */ +0xc000, +0x2000, +0x4000, +0x2000, +0xc800, +0x1800, +0x2800, +0x7800, +0x0800, +0x0000, + +/* Character 191 (0xbf): + width 6 + +------+ + | | + | * | + | | + | * | + | * | + | * | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0x2000, +0x0000, +0x2000, +0x2000, +0x4000, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 192 (0xc0): + width 6 + +------+ + | * | + | * | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x4000, +0x2000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 193 (0xc1): + width 6 + +------+ + | * | + | * | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x1000, +0x2000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 194 (0xc2): + width 6 + +------+ + | * | + | * * | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x2000, +0x5000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 195 (0xc3): + width 6 + +------+ + | * * | + |* ** | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x4800, +0xb000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 196 (0xc4): + width 6 + +------+ + | * * | + | | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x5000, +0x0000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 197 (0xc5): + width 6 + +------+ + | * | + | * * | + | *** | + |* * | + |* * | + |***** | + |* * | + |* * | + | | + | | + +------+ */ +0x2000, +0x5000, +0x7000, +0x8800, +0x8800, +0xf800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 198 (0xc6): + width 6 + +------+ + | | + | ****| + | * * | + |* * | + |* ***| + |**** | + |* * | + |* ***| + | | + | | + +------+ */ +0x0000, +0x3c00, +0x5000, +0x9000, +0x9c00, +0xf000, +0x9000, +0x9c00, +0x0000, +0x0000, + +/* Character 199 (0xc7): + width 6 + +------+ + | | + | *** | + |* * | + |* | + |* | + |* | + |* * | + | *** | + | * | + | * | + +------+ */ +0x0000, +0x7000, +0x8800, +0x8000, +0x8000, +0x8000, +0x8800, +0x7000, +0x2000, +0x4000, + +/* Character 200 (0xc8): + width 6 + +------+ + | * | + |***** | + |* | + |* | + |**** | + |* | + |* | + |***** | + | | + | | + +------+ */ +0x4000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0xf800, +0x0000, +0x0000, + +/* Character 201 (0xc9): + width 6 + +------+ + | * | + |***** | + |* | + |* | + |**** | + |* | + |* | + |***** | + | | + | | + +------+ */ +0x1000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0xf800, +0x0000, +0x0000, + +/* Character 202 (0xca): + width 6 + +------+ + | * | + |***** | + |* | + |* | + |**** | + |* | + |* | + |***** | + | | + | | + +------+ */ +0x2000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0xf800, +0x0000, +0x0000, + +/* Character 203 (0xcb): + width 6 + +------+ + | * * | + |***** | + |* | + |* | + |**** | + |* | + |* | + |***** | + | | + | | + +------+ */ +0x5000, +0xf800, +0x8000, +0x8000, +0xf000, +0x8000, +0x8000, +0xf800, +0x0000, +0x0000, + +/* Character 204 (0xcc): + width 6 + +------+ + | * | + | * | + | *** | + | * | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x7000, +0x2000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 205 (0xcd): + width 6 + +------+ + | * | + | * | + | *** | + | * | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x7000, +0x2000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 206 (0xce): + width 6 + +------+ + | * | + | * * | + | *** | + | * | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x7000, +0x2000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 207 (0xcf): + width 6 + +------+ + | * * | + | | + | *** | + | * | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x5000, +0x0000, +0x7000, +0x2000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 208 (0xd0): + width 6 + +------+ + | | + |**** | + | * * | + | * * | + |*** * | + | * * | + | * * | + |**** | + | | + | | + +------+ */ +0x0000, +0xf000, +0x4800, +0x4800, +0xe800, +0x4800, +0x4800, +0xf000, +0x0000, +0x0000, + +/* Character 209 (0xd1): + width 6 + +------+ + | * * | + | * * | + |* * | + |** * | + |* * * | + |* ** | + |* * | + |* * | + | | + | | + +------+ */ +0x2800, +0x5000, +0x8800, +0xc800, +0xa800, +0x9800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 210 (0xd2): + width 6 + +------+ + | * | + | * | + | *** | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x7000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 211 (0xd3): + width 6 + +------+ + | * | + | * | + | *** | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x7000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 212 (0xd4): + width 6 + +------+ + | * | + | * * | + | *** | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x7000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 213 (0xd5): + width 6 + +------+ + | * * | + | * * | + | *** | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x2800, +0x5000, +0x7000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 214 (0xd6): + width 6 + +------+ + | * * | + | | + | *** | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x5000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 215 (0xd7): + width 6 + +------+ + | | + | | + | | + |* * | + | * * | + | * | + | * * | + |* * | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x8800, +0x5000, +0x2000, +0x5000, +0x8800, +0x0000, +0x0000, + +/* Character 216 (0xd8): + width 6 + +------+ + | | + | *** | + |* ** | + |* ** | + |* * * | + |** * | + |** * | + | *** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x9800, +0x9800, +0xa800, +0xc800, +0xc800, +0x7000, +0x0000, +0x0000, + +/* Character 217 (0xd9): + width 6 + +------+ + | * | + | * | + |* * | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x8800, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 218 (0xda): + width 6 + +------+ + | * | + | * | + |* * | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x8800, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 219 (0xdb): + width 6 + +------+ + | * | + | * * | + | | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 220 (0xdc): + width 6 + +------+ + | * * | + | | + |* * | + |* * | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x5000, +0x0000, +0x8800, +0x8800, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 221 (0xdd): + width 6 + +------+ + | * | + | * | + |* * | + |* * | + | * * | + | * | + | * | + | * | + | | + | | + +------+ */ +0x1000, +0x2000, +0x8800, +0x8800, +0x5000, +0x2000, +0x2000, +0x2000, +0x0000, +0x0000, + +/* Character 222 (0xde): + width 6 + +------+ + | | + |* | + |**** | + |* * | + |**** | + |* | + |* | + |* | + | | + | | + +------+ */ +0x0000, +0x8000, +0xf000, +0x8800, +0xf000, +0x8000, +0x8000, +0x8000, +0x0000, +0x0000, + +/* Character 223 (0xdf): + width 6 + +------+ + | | + | *** | + |* * | + |* * | + |* * | + |* * | + |* * | + |* ** | + | | + | | + +------+ */ +0x0000, +0x7000, +0x8800, +0x9000, +0xa000, +0x9000, +0x8800, +0xb000, +0x0000, +0x0000, + +/* Character 224 (0xe0): + width 6 + +------+ + | * | + | * | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 225 (0xe1): + width 6 + +------+ + | * | + | * | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 226 (0xe2): + width 6 + +------+ + | * | + | * * | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 227 (0xe3): + width 6 + +------+ + | * * | + | * * | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x2800, +0x5000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 228 (0xe4): + width 6 + +------+ + | | + | * * | + | | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x0000, +0x5000, +0x0000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 229 (0xe5): + width 6 + +------+ + | * | + | * * | + | * | + | *** | + | * | + | **** | + |* * | + | **** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x2000, +0x7000, +0x0800, +0x7800, +0x8800, +0x7800, +0x0000, +0x0000, + +/* Character 230 (0xe6): + width 6 + +------+ + | | + | | + | | + | **** | + | * *| + | *****| + |* * | + | *****| + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x7800, +0x1400, +0x7c00, +0x9000, +0x7c00, +0x0000, +0x0000, + +/* Character 231 (0xe7): + width 6 + +------+ + | | + | | + | | + | *** | + |* * | + |* | + |* * | + | *** | + | * | + | * | + +------+ */ +0x0000, +0x0000, +0x0000, +0x7000, +0x8800, +0x8000, +0x8800, +0x7000, +0x2000, +0x4000, + +/* Character 232 (0xe8): + width 6 + +------+ + | * | + | * | + | | + | *** | + |* * | + |***** | + |* | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x0000, +0x7000, +0x8800, +0xf800, +0x8000, +0x7000, +0x0000, +0x0000, + +/* Character 233 (0xe9): + width 6 + +------+ + | * | + | * | + | | + | *** | + |* * | + |***** | + |* | + | *** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x0000, +0x7000, +0x8800, +0xf800, +0x8000, +0x7000, +0x0000, +0x0000, + +/* Character 234 (0xea): + width 6 + +------+ + | * | + | * * | + | | + | *** | + |* * | + |***** | + |* | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x7000, +0x8800, +0xf800, +0x8000, +0x7000, +0x0000, +0x0000, + +/* Character 235 (0xeb): + width 6 + +------+ + | | + | * * | + | | + | *** | + |* * | + |***** | + |* | + | *** | + | | + | | + +------+ */ +0x0000, +0x5000, +0x0000, +0x7000, +0x8800, +0xf800, +0x8000, +0x7000, +0x0000, +0x0000, + +/* Character 236 (0xec): + width 6 + +------+ + | * | + | * | + | | + | ** | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x0000, +0x6000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 237 (0xed): + width 6 + +------+ + | * | + | * | + | | + | ** | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x2000, +0x4000, +0x0000, +0x6000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 238 (0xee): + width 6 + +------+ + | * | + | * * | + | | + | ** | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x6000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 239 (0xef): + width 6 + +------+ + | | + | * * | + | | + | ** | + | * | + | * | + | * | + | *** | + | | + | | + +------+ */ +0x0000, +0x5000, +0x0000, +0x6000, +0x2000, +0x2000, +0x2000, +0x7000, +0x0000, +0x0000, + +/* Character 240 (0xf0): + width 6 + +------+ + | | + |** | + | ** | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0xc000, +0x3000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 241 (0xf1): + width 6 + +------+ + | * * | + | * * | + | | + |* ** | + |** * | + |* * | + |* * | + |* * | + | | + | | + +------+ */ +0x2800, +0x5000, +0x0000, +0xb000, +0xc800, +0x8800, +0x8800, +0x8800, +0x0000, +0x0000, + +/* Character 242 (0xf2): + width 6 + +------+ + | * | + | * | + | | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x4000, +0x2000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 243 (0xf3): + width 6 + +------+ + | * | + | * | + | | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x1000, +0x2000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 244 (0xf4): + width 6 + +------+ + | * | + | * * | + | | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 245 (0xf5): + width 6 + +------+ + | * * | + | * * | + | | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x2800, +0x5000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 246 (0xf6): + width 6 + +------+ + | | + | * * | + | | + | *** | + |* * | + |* * | + |* * | + | *** | + | | + | | + +------+ */ +0x0000, +0x5000, +0x0000, +0x7000, +0x8800, +0x8800, +0x8800, +0x7000, +0x0000, +0x0000, + +/* Character 247 (0xf7): + width 6 + +------+ + | | + | | + | * | + | | + |***** | + | | + | * | + | | + | | + | | + +------+ */ +0x0000, +0x0000, +0x2000, +0x0000, +0xf800, +0x0000, +0x2000, +0x0000, +0x0000, +0x0000, + +/* Character 248 (0xf8): + width 6 + +------+ + | | + | | + | | + | **** | + |* ** | + |* * * | + |** * | + |**** | + | | + | | + +------+ */ +0x0000, +0x0000, +0x0000, +0x7800, +0x9800, +0xa800, +0xc800, +0xf000, +0x0000, +0x0000, + +/* Character 249 (0xf9): + width 6 + +------+ + | * | + | * | + | | + |* * | + |* * | + |* * | + |* ** | + | ** * | + | | + | | + +------+ */ +0x4000, +0x2000, +0x0000, +0x8800, +0x8800, +0x8800, +0x9800, +0x6800, +0x0000, +0x0000, + +/* Character 250 (0xfa): + width 6 + +------+ + | * | + | * | + | | + |* * | + |* * | + |* * | + |* ** | + | ** * | + | | + | | + +------+ */ +0x1000, +0x2000, +0x0000, +0x8800, +0x8800, +0x8800, +0x9800, +0x6800, +0x0000, +0x0000, + +/* Character 251 (0xfb): + width 6 + +------+ + | * | + | * * | + | | + |* * | + |* * | + |* * | + |* ** | + | ** * | + | | + | | + +------+ */ +0x2000, +0x5000, +0x0000, +0x8800, +0x8800, +0x8800, +0x9800, +0x6800, +0x0000, +0x0000, + +/* Character 252 (0xfc): + width 6 + +------+ + | | + | * * | + | | + |* * | + |* * | + |* * | + |* ** | + | ** * | + | | + | | + +------+ */ +0x0000, +0x5000, +0x0000, +0x8800, +0x8800, +0x8800, +0x9800, +0x6800, +0x0000, +0x0000, + +/* Character 253 (0xfd): + width 6 + +------+ + | | + | * | + | * | + |* * | + |* * | + |* ** | + | ** * | + | * | + |* * | + | *** | + +------+ */ +0x0000, +0x1000, +0x2000, +0x8800, +0x8800, +0x9800, +0x6800, +0x0800, +0x8800, +0x7000, + +/* Character 254 (0xfe): + width 6 + +------+ + | | + | | + |* | + |**** | + |* * | + |* * | + |* * | + |**** | + |* | + |* | + +------+ */ +0x0000, +0x0000, +0x8000, +0xf000, +0x8800, +0x8800, +0x8800, +0xf000, +0x8000, +0x8000, + +/* Character 255 (0xff): + width 6 + +------+ + | | + | * * | + | | + |* * | + |* * | + |* ** | + | ** * | + | * | + |* * | + | *** | + +------+ */ +0x0000, +0x5000, +0x0000, +0x8800, +0x8800, +0x9800, +0x6800, +0x0800, +0x8800, +0x7000, +}; + +/* Character->glyph mapping. */ +static unsigned long _font_offset[256] = +{ + 0, /* (0x00) */ + 10, /* (0x01) */ + 20, /* (0x02) */ + 30, /* (0x03) */ + 40, /* (0x04) */ + 50, /* (0x05) */ + 60, /* (0x06) */ + 70, /* (0x07) */ + 80, /* (0x08) */ + 90, /* (0x09) */ + 100, /* (0x0a) */ + 110, /* (0x0b) */ + 120, /* (0x0c) */ + 130, /* (0x0d) */ + 140, /* (0x0e) */ + 150, /* (0x0f) */ + 160, /* (0x10) */ + 170, /* (0x11) */ + 180, /* (0x12) */ + 190, /* (0x13) */ + 200, /* (0x14) */ + 210, /* (0x15) */ + 220, /* (0x16) */ + 230, /* (0x17) */ + 240, /* (0x18) */ + 250, /* (0x19) */ + 260, /* (0x1a) */ + 270, /* (0x1b) */ + 280, /* (0x1c) */ + 290, /* (0x1d) */ + 300, /* (0x1e) */ + 310, /* (0x1f) */ + 320, /* (0x20) */ + 330, /* (0x21) */ + 340, /* (0x22) */ + 350, /* (0x23) */ + 360, /* (0x24) */ + 370, /* (0x25) */ + 380, /* (0x26) */ + 390, /* (0x27) */ + 400, /* (0x28) */ + 410, /* (0x29) */ + 420, /* (0x2a) */ + 430, /* (0x2b) */ + 440, /* (0x2c) */ + 450, /* (0x2d) */ + 460, /* (0x2e) */ + 470, /* (0x2f) */ + 480, /* (0x30) */ + 490, /* (0x31) */ + 500, /* (0x32) */ + 510, /* (0x33) */ + 520, /* (0x34) */ + 530, /* (0x35) */ + 540, /* (0x36) */ + 550, /* (0x37) */ + 560, /* (0x38) */ + 570, /* (0x39) */ + 580, /* (0x3a) */ + 590, /* (0x3b) */ + 600, /* (0x3c) */ + 610, /* (0x3d) */ + 620, /* (0x3e) */ + 630, /* (0x3f) */ + 640, /* (0x40) */ + 650, /* (0x41) */ + 660, /* (0x42) */ + 670, /* (0x43) */ + 680, /* (0x44) */ + 690, /* (0x45) */ + 700, /* (0x46) */ + 710, /* (0x47) */ + 720, /* (0x48) */ + 730, /* (0x49) */ + 740, /* (0x4a) */ + 750, /* (0x4b) */ + 760, /* (0x4c) */ + 770, /* (0x4d) */ + 780, /* (0x4e) */ + 790, /* (0x4f) */ + 800, /* (0x50) */ + 810, /* (0x51) */ + 820, /* (0x52) */ + 830, /* (0x53) */ + 840, /* (0x54) */ + 850, /* (0x55) */ + 860, /* (0x56) */ + 870, /* (0x57) */ + 880, /* (0x58) */ + 890, /* (0x59) */ + 900, /* (0x5a) */ + 910, /* (0x5b) */ + 920, /* (0x5c) */ + 930, /* (0x5d) */ + 940, /* (0x5e) */ + 950, /* (0x5f) */ + 960, /* (0x60) */ + 970, /* (0x61) */ + 980, /* (0x62) */ + 990, /* (0x63) */ + 1000, /* (0x64) */ + 1010, /* (0x65) */ + 1020, /* (0x66) */ + 1030, /* (0x67) */ + 1040, /* (0x68) */ + 1050, /* (0x69) */ + 1060, /* (0x6a) */ + 1070, /* (0x6b) */ + 1080, /* (0x6c) */ + 1090, /* (0x6d) */ + 1100, /* (0x6e) */ + 1110, /* (0x6f) */ + 1120, /* (0x70) */ + 1130, /* (0x71) */ + 1140, /* (0x72) */ + 1150, /* (0x73) */ + 1160, /* (0x74) */ + 1170, /* (0x75) */ + 1180, /* (0x76) */ + 1190, /* (0x77) */ + 1200, /* (0x78) */ + 1210, /* (0x79) */ + 1220, /* (0x7a) */ + 1230, /* (0x7b) */ + 1240, /* (0x7c) */ + 1250, /* (0x7d) */ + 1260, /* (0x7e) */ + 0, /* (0x7f) */ + 0, /* (0x80) */ + 0, /* (0x81) */ + 0, /* (0x82) */ + 0, /* (0x83) */ + 0, /* (0x84) */ + 0, /* (0x85) */ + 0, /* (0x86) */ + 0, /* (0x87) */ + 0, /* (0x88) */ + 0, /* (0x89) */ + 0, /* (0x8a) */ + 0, /* (0x8b) */ + 0, /* (0x8c) */ + 0, /* (0x8d) */ + 0, /* (0x8e) */ + 0, /* (0x8f) */ + 0, /* (0x90) */ + 0, /* (0x91) */ + 0, /* (0x92) */ + 0, /* (0x93) */ + 0, /* (0x94) */ + 0, /* (0x95) */ + 0, /* (0x96) */ + 0, /* (0x97) */ + 0, /* (0x98) */ + 0, /* (0x99) */ + 0, /* (0x9a) */ + 0, /* (0x9b) */ + 0, /* (0x9c) */ + 0, /* (0x9d) */ + 0, /* (0x9e) */ + 0, /* (0x9f) */ + 1270, /* (0xa0) */ + 1280, /* (0xa1) */ + 1290, /* (0xa2) */ + 1300, /* (0xa3) */ + 1310, /* (0xa4) */ + 1320, /* (0xa5) */ + 1330, /* (0xa6) */ + 1340, /* (0xa7) */ + 1350, /* (0xa8) */ + 1360, /* (0xa9) */ + 1370, /* (0xaa) */ + 1380, /* (0xab) */ + 1390, /* (0xac) */ + 1400, /* (0xad) */ + 1410, /* (0xae) */ + 1420, /* (0xaf) */ + 1430, /* (0xb0) */ + 1440, /* (0xb1) */ + 1450, /* (0xb2) */ + 1460, /* (0xb3) */ + 1470, /* (0xb4) */ + 1480, /* (0xb5) */ + 1490, /* (0xb6) */ + 1500, /* (0xb7) */ + 1510, /* (0xb8) */ + 1520, /* (0xb9) */ + 1530, /* (0xba) */ + 1540, /* (0xbb) */ + 1550, /* (0xbc) */ + 1560, /* (0xbd) */ + 1570, /* (0xbe) */ + 1580, /* (0xbf) */ + 1590, /* (0xc0) */ + 1600, /* (0xc1) */ + 1610, /* (0xc2) */ + 1620, /* (0xc3) */ + 1630, /* (0xc4) */ + 1640, /* (0xc5) */ + 1650, /* (0xc6) */ + 1660, /* (0xc7) */ + 1670, /* (0xc8) */ + 1680, /* (0xc9) */ + 1690, /* (0xca) */ + 1700, /* (0xcb) */ + 1710, /* (0xcc) */ + 1720, /* (0xcd) */ + 1730, /* (0xce) */ + 1740, /* (0xcf) */ + 1750, /* (0xd0) */ + 1760, /* (0xd1) */ + 1770, /* (0xd2) */ + 1780, /* (0xd3) */ + 1790, /* (0xd4) */ + 1800, /* (0xd5) */ + 1810, /* (0xd6) */ + 1820, /* (0xd7) */ + 1830, /* (0xd8) */ + 1840, /* (0xd9) */ + 1850, /* (0xda) */ + 1860, /* (0xdb) */ + 1870, /* (0xdc) */ + 1880, /* (0xdd) */ + 1890, /* (0xde) */ + 1900, /* (0xdf) */ + 1910, /* (0xe0) */ + 1920, /* (0xe1) */ + 1930, /* (0xe2) */ + 1940, /* (0xe3) */ + 1950, /* (0xe4) */ + 1960, /* (0xe5) */ + 1970, /* (0xe6) */ + 1980, /* (0xe7) */ + 1990, /* (0xe8) */ + 2000, /* (0xe9) */ + 2010, /* (0xea) */ + 2020, /* (0xeb) */ + 2030, /* (0xec) */ + 2040, /* (0xed) */ + 2050, /* (0xee) */ + 2060, /* (0xef) */ + 2070, /* (0xf0) */ + 2080, /* (0xf1) */ + 2090, /* (0xf2) */ + 2100, /* (0xf3) */ + 2110, /* (0xf4) */ + 2120, /* (0xf5) */ + 2130, /* (0xf6) */ + 2140, /* (0xf7) */ + 2150, /* (0xf8) */ + 2160, /* (0xf9) */ + 2170, /* (0xfa) */ + 2180, /* (0xfb) */ + 2190, /* (0xfc) */ + 2200, /* (0xfd) */ + 2210, /* (0xfe) */ + 2220 /* (0xff) */ +}; diff --git a/game_config.txt b/game_config.txt new file mode 100644 index 0000000..bb2ac49 --- /dev/null +++ b/game_config.txt @@ -0,0 +1,932 @@ +# gpSP game settings database + +# What is this file??? game_config.txt is a database of settings on a +# per-game basis. A couple of the settings are required to make games +# work at all, but most of them are there to improve the performance of +# a game. If a game doesn't work then look through the settings here, +# but keep in mind that this file can not be used to fix a majority of +# games, the ones that don't work because of emulator bugs. For those +# you'll have to wait for a new release and hope it someday gets fixed. + +# This file is meant to be edited in plain text, with a normal editor. +# game_name, game_code, and vender_code can be found in the game's header. +# All three must match for the game to be used, and those setting must be +# in that order. Be sure to use [!] ROMs (verified by GoodGBA) when +# building this list. Right now I don't know how much overlap there is +# between different region games, but usually idle loops don't apply to +# them. If you're using a different region than the one in here you can +# try copying the entry, it might improve it. + +# You can also find the three identifying codes on the second line from +# the top in gpSP's main menu. So anyone should be able to add settings +# to this file if they know what to set, but for some options it'll take +# a lot of special knowledge for them to be of any use. Be sure to see if +# your game is already here, but only if the game_name/game_code/ +# vender_code all match. Only the first full match's settings will be used. + +# Everything here is case sensitive. Don't mess with this file unless +# you know what you're doing - if in doubt sooner ask someone who does. + +# I mainly focus on USA versions, so try those first. And, just because +# a game is on here doesn't mean the game actually works in the current +# version. :/ + +# These are the following options: + +# idle_loop_eliminate_target - tells the recompiler that this branch +# is an idle loop and thus a hardware update should follow it every +# time. This is purely a speed improvement and is not meant to improve +# compatibility - if it does it represents a strange timing problem in +# the game. You can only set one of these for now. Don't use this if +# you don't know what you're doing, it can break the game. Some games +# will run miserably slowly without this option. + +# translation_gate_target - tells the recompiler to put an indirect +# branch (gate) at this point, so artificially stop the current block. +# This is useful if the game performs self modifying code from within +# the same block it is currently executing - this can prevent it from +# causing SMC hits far more times than it should. This is also only a +# speed hack; you can have up to 8 of these. Don't use this if you don't +# know what you're doing, they'll just make the game slower and are +# rarely helpful (good for Camelot games). + +# iwram_stack_optimize - set this to "no" to turn it off. By default this +# is set on. It will turn off an optimization that assumes that the stack +# is always in IWRAM, and thus makes ldm/stm relative to the stack much +# faster. Turning it off will degrade game speed slightly, but is +# necessary for a few games that don't follow this convention. + +# flash_rom_type - set this to 128KB if the game has a 128KB flash ROM, +# otherwise leave it alone or you might break game saving. If you get +# a white screen when the game starts try this option. + +# bios_rom_hack_39 - a hack that allows "roll" to work with the correct BIOS +# in Zelda: Minish Cap. + +# bios_rom_hack_2C - like the above but allows Rayman Advance to work. + +# Castlevania: Circle of the Moon (U) +game_name = DRACULA AGB1 +game_code = AAME +vender_code = A4 +idle_loop_eliminate_target = 080003d2 + +# Megaman Battle Network (U) +game_name = MEGAMAN_BN +game_code = AREE +vender_code = 08 +idle_loop_eliminate_target = 08000338 + +# Megaman Battle Network 2 (U) +game_name = MEGAMAN_EXE2 +game_code = AE2E +vender_code = 08 +idle_loop_eliminate_target = 08000358 + +# Megaman Battle Network 3 White (U) +game_name = MEGA_EXE3_WH +game_code = A6BE +vender_code = 08 +idle_loop_eliminate_target = 0800036c + +# Megaman Battle Network 3 Blue (U) +game_name = MEGA_EXE3_BL +game_code = A3XE +vender_code = 08 +idle_loop_eliminate_target = 0800036c + +# Megaman Battle Network 4 Red Sun (U) +game_name = MEGAMANBN4RS +game_code = B4WE +vender_code = 08 +idle_loop_eliminate_target = 080003a6 + +# Megaman Battle Network 4 Blue Moon (U) +game_name = MEGAMANBN4BM +game_code = B4BE +vender_code = 08 +idle_loop_eliminate_target = 080003a6 + +# Megaman Battle Network 5 Team Protoman (U) +game_name = MEGAMAN5_TP_ +game_code = BRBE +vender_code = 08 +idle_loop_eliminate_target = 080003ca + +# Megaman Battle Network 5 Team Colonel (U) +game_name = MEGAMAN5_TC_ +game_code = BRKE +vender_code = 08 +idle_loop_eliminate_target = 080003ca + +# Megaman Battle Network 6 Cybeast Gregar (U) +game_name = MEGAMAN6_GXX +game_code = BR5E +vender_code = 08 +idle_loop_eliminate_target = 080003da + +# Megaman Zero (U/E) +game_name = MEGAMAN ZERO +game_code = AZCE +vender_code = 08 +idle_loop_eliminate_target = 080004ee + +# Megaman Zero 2 (U) +game_name = MEGAMANZERO2 +game_code = A62E +vender_code = 08 +idle_loop_eliminate_target = 08000664 + +# Megaman Zero 3 (U) +game_name = MEGAMANZERO3 +game_code = BZ3E +vender_code = 08 +idle_loop_eliminate_target = 08001a08 + +# Megaman Zero 4 (U) +game_name = MEGAMANZERO4 +game_code = B4ZP +vender_code = 08 +idle_loop_eliminate_target = 0800090c + +# Kirby: Nightmare in Dreamland (U) +game_name = AGB KIRBY DX +game_code = A7KE +vender_code = 01 +idle_loop_eliminate_target = 08000fae +iwram_stack_optimize = no + +# Hoshi no Kirby: Yume no Izumi Deluxe (J) +game_name = AGB KIRBY DX +game_code = A7KJ +vender_code = 01 +idle_loop_eliminate_target = 08000f92 +iwram_stack_optimize = no + +# Kirby: Nightmare in Dreamland (E) +game_name = AGB KIRBY DX +game_code = A7KP +vender_code = 01 +idle_loop_eliminate_target = 08000fae +iwram_stack_optimize = no + +# Super Mario Advance (U) +game_name = SUPER MARIOA +game_code = AMZE +vender_code = 01 +idle_loop_eliminate_target = 08001cf2 + +# Super Mario Advance 2 (U) +game_name = SUPER MARIOB +game_code = AA2E +vender_code = 01 +idle_loop_eliminate_target = 08000534 + +# Super Mario Advance 3 (U) +game_name = SUPER MARIOC +game_code = A3AE +vender_code = 01 +idle_loop_eliminate_target = 08002ba4 + +# Super Mario Advance 4 (U) +game_name = SUPER MARIOD +game_code = AX4E +vender_code = 01 +idle_loop_eliminate_target = 08000732 +flash_rom_type = 128KB + +# Super Mario Advance 4 (J) +game_name = SUPER MARIOD +game_code = AX4J +vender_code = 01 +idle_loop_eliminate_target = 08000732 +flash_rom_type = 128KB + +# Super Mario Advance 4 (E) +game_name = SUPER MARIOD +game_code = AX4P +vender_code = 01 +idle_loop_eliminate_target = 08000732 +flash_rom_type = 128KB + +# Advance Wars (U) +# This one was really annoying to find, I hope it's okay.. there +# might be a better one somewhere. +game_name = ADVANCEWARS +game_code = AWRE +vender_code = 01 +idle_loop_eliminate_target = 0803880a + +# Pokemon Emerald (E/U) +# I don't know why this has an idle loop when Ruby doesn't.... +game_name = POKEMON EMER +game_code = BPEE +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Emerald (J) +game_name = POKEMON EMER +game_code = BPEJ +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Emerald (G) +game_name = POKEMON EMER +game_code = BPED +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Emerald (F) +game_name = POKEMON EMER +game_code = BPEF +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Emerald (S) +game_name = POKEMON EMER +game_code = BPES +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Emerald (I) +game_name = POKEMON EMER +game_code = BPEI +vender_code = 01 +idle_loop_eliminate_target = 080008ce +flash_rom_type = 128KB + +# Pokemon Sapphire (U) +game_name = POKEMON SAPP +game_code = AXPE +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Sapphire (J) +game_name = POKEMON SAPP +game_code = AXPJ +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Sapphire (G) +game_name = POKEMON SAPP +game_code = AXPD +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Sapphire (I) +game_name = POKEMON SAPP +game_code = AXPI +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Sapphire (S) +game_name = POKEMON SAPP +game_code = AXPS +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Sapphire (F) +game_name = POKEMON SAPP +game_code = AXPF +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (U) +game_name = POKEMON RUBY +game_code = AXVE +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (J) +game_name = POKEMON RUBY +game_code = AXVJ +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (G) +game_name = POKEMON RUBY +game_code = AXVD +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (I) +game_name = POKEMON RUBY +game_code = AXVI +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (S) +game_name = POKEMON RUBY +game_code = AXVS +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon Ruby (F) +game_name = POKEMON RUBY +game_code = AXVF +vender_code = 01 +flash_rom_type = 128KB + +# V-Rally 3 (E) +game_name = V-RALLY 3 +game_code = AVRP +vender_code = 70 +idle_loop_eliminate_target = 080aa920 + +# Mario Vs Donkey Kong (U) +game_name = MARIOVSDK +game_code = BM5E +vender_code = 01 +idle_loop_eliminate_target = 08033eec + +# Pokemon: Sapphire (U) +game_name = POKEMON SAPP +game_code = AXPE +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon: Sapphire (G) +game_name = POKEMON SAPP +game_code = AXPD +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon: Fire Red (J) +game_name = POKEMON FIRE +game_code = BPRJ +vender_code = 01 +idle_loop_eliminate_target = 080008b2 +# If you have the European version try this instead. +#idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Fire Red (E/U) +game_name = POKEMON FIRE +game_code = BPRE +vender_code = 01 +idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Fire Red (S) +game_name = POKEMON FIRE +game_code = BPRS +vender_code = 01 +idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Fire Red (G) +game_name = POKEMON FIRE +game_code = BPRD +vender_code = 01 +idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Fire Red (I) +game_name = POKEMON FIRE +game_code = BPRI +vender_code = 01 +idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Fire Red (F) +game_name = POKEMON FIRE +game_code = BPRE +vender_code = 01 +idle_loop_eliminate_target = 080008c6 +flash_rom_type = 128KB + +# Pokemon: Leaf Green (E/U) +# Hey, this one is the same as Fire Red, who'd have thought? :B +game_name = POKEMON LEAF +game_code = BPGE +vender_code = 01 +idle_loop_eliminate_target = 080008b2 +flash_rom_type = 128KB + +# Pokemon: Leaf Green (S) +game_name = POKEMON LEAF +game_code = BPGS +vender_code = 01 +idle_loop_eliminate_target = 080008b6 +flash_rom_type = 128KB + +# Pokemon: Leaf Green (G) +game_name = POKEMON LEAF +game_code = BPGD +vender_code = 01 +idle_loop_eliminate_target = 080008b6 +flash_rom_type = 128KB + +# Pokemon: Leaf Green (I) +game_name = POKEMON LEAF +game_code = BPGI +vender_code = 01 +idle_loop_eliminate_target = 080008b6 +flash_rom_type = 128KB + +# Pokemon: Leaf Green (F) +game_name = POKEMON LEAF +game_code = BPGF +vender_code = 01 +idle_loop_eliminate_target = 080008b6 +flash_rom_type = 128KB + +# Pokemon: Fushigi no Dungeon Aka no Kyuujotai (J) +game_name = POKE DUNGEON +game_code = B24J +vender_code = 01 +flash_rom_type = 128KB + +# Pokemon: Red Rescue Team (E/U) +game_name = POKE DUNGEON +game_code = B24E +vender_code = 01 +flash_rom_type = 128KB + +# F-Zero: Climax (J) +game_name = F-ZEROCLIMAX +game_code = BFTJ +vender_code = 01 +flash_rom_type = 128KB + +# Final Fantasy Tactics Advance (U) +game_name = FFTA_USVER. +game_code = AFXE +vender_code = 01 +idle_loop_eliminate_target = 0800041e + +# Gradius Galaxies (U) +# Badly coded game with several idle loops. This one works for level +# one at least. +game_name = GRADIUSGALAX +game_code = AGAE +vender_code = A4 +idle_loop_eliminate_target = 08013844 + +# Rebelstar: Tactical Command (U) +# Badly coded game with several idle loops. I don't think any are +# even close to dominant, and it jumps around too much when things +# matter.... +game_name = REBELSTAR +game_code = BRLE +vender_code = AF +idle_loop_eliminate_target = 0800041a + +# Golden Sun +game_name = Golden_Sun_A +game_code = AGSE +vender_code = 01 +translation_gate_target = 03000820 +translation_gate_target = 030009ac +translation_gate_target = 03007dac + +# Golden Sun: The Lost Age (U) +# Probably the most horrifically coded GBA game in existence. +game_name = GOLDEN_SUN_B +game_code = AGFE +vender_code = 01 +idle_loop_eliminate_target = 08013542 +translation_gate_target = 030009ac +#translation_gate_target = 03007d70 + +# Nothing to see here :/ +# Mario & Luigi: Superstar Saga (U) +game_name = MARIO&LUIGIU +game_code = A88E +vender_code = 01 + +# Mario Party Advance (U) +game_name = MARIOPARTYUS +game_code = B8ME +vender_code = 01 +iwram_stack_optimize = no + +# Mario Party Advance (J) +game_name = MARIOPARTYJA +game_code = B8MJ +vender_code = 01 +iwram_stack_optimize = no + +# Mario Party Advance (E) +game_name = MARIOPARTYEU +game_code = B8MP +vender_code = 01 +iwram_stack_optimize = no + +# Mario Golf: Advance Tour (U) +game_name = MARIOGOLFGBA +game_code = BMGE +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: GBA Tour (J) +game_name = MARIOGOLFGBA +game_code = BMGJ +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (E) +game_name = MARIOGOLFGBA +game_code = BMGP +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (S) +game_name = MARIOGOLFGBA +game_code = BMGS +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (F) +game_name = MARIOGOLFGBA +game_code = BMGF +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (I) +game_name = MARIOGOLFGBA +game_code = BMGI +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (G) +game_name = MARIOGOLFGBA +game_code = BMGD +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Mario Golf: Advance Tour (A) +game_name = MARIOGOLFGBA +game_code = BMGU +vender_code = 01 +iwram_stack_optimize = no +idle_loop_eliminate_target = 08014e0a +translation_gate_target = 03000d00 +translation_gate_target = 03000a30 + +# Tales of Phantasia (U) +game_name = PHANTASIA +game_code = AN8E +vender_code = 01 +iwram_stack_optimize = no + +# Tales of Phantasia (J) +game_name = PHANTASIA +game_code = AN8J +vender_code = AF +iwram_stack_optimize = no + +# Tales of Phantasia (E) +game_name = PHANTASIA +game_code = AN8P +vender_code = 01 +iwram_stack_optimize = no + +# Advance Wars 2: Black Hole Rising (U) +game_name = ADVANCEWARS2 +game_code = AW2E +vender_code = 01 +idle_loop_eliminate_target = 08036e2a + +# Bomberman Tournament (U) +game_name = BOMSTORYUSA +game_code = ABSE +vender_code = 52 +idle_loop_eliminate_target = 08000526 + +# Broken Sword - The Shadow of the Templars (U) +game_name = BROKENSWORD +game_code = ABJE +vender_code = 6L +idle_loop_eliminate_target = 08000a26 + +# Defender of The Crown (U) +game_name = DOTC +game_code = ADHE +vender_code = 5N +idle_loop_eliminate_target = 080007ec + +# Drill Dozer (U) +game_name = DRILL DOZER +game_code = V49E +vender_code = 01 +idle_loop_eliminate_target = 080006c2 + +# F-Zero - Maximum Velocity (U) +game_name = F-ZERO ADVAN +game_code = AFZE +vender_code = 01 +idle_loop_eliminate_target = 08000c2e + +# Megaman Zero 2 (U) +game_name = MEGAMANZERO2 +game_code = A62E +vender_code = 08 +idle_loop_eliminate_target = 08000664 + +# Megaman Zero 3 (U) +game_name = MEGAMANZERO3 +game_code = BZ3E +vender_code = 08 +idle_loop_eliminate_target = 08001a08 + +# Megaman Zero 4 (U) +game_name = MEGAMANZERO4 +game_code = B4ZE +vender_code = 08 +idle_loop_eliminate_target = 0800090c + +# Metal Slug Advance (U) +game_name = METAL SLUG +game_code = BSME +vender_code = B7 +idle_loop_eliminate_target = 08000298 + +# Magical Quest 2 Starring Mickey & Minnie (U) +game_name = M&M MAGICAL2 +game_code = AQME +vender_code = 08 +idle_loop_eliminate_target = 0801d340 + +# Magical Quest 3 Starring Mickey & Donald (U) +game_name = M&D MAGICAL3 +game_code = BMQE +vender_code = 08 +idle_loop_eliminate_target = 08016064 + +# Pinball Challenge Deluxe (E) +game_name = PINBALL CHAL +game_code = APLP +vender_code = 41 +idle_loop_eliminate_target = 080075a6 + +# Prince of Persia - The Sands of Time (U) +game_name = PRINCEPERSIA +game_code = BPYE +vender_code = 41 +idle_loop_eliminate_target = 0808ff3a + +# Rhythm Tengoku (J) +game_name = RHYTHMTENGOK +game_code = BRIJ +vender_code = 01 +idle_loop_eliminate_target = 080013d4 + +# River City Ransom EX (U) +game_name = RIVERCRANSOM +game_code = BDTE +vender_code = EB +idle_loop_eliminate_target = 0800065a + +# Super Puzzle Fighter II Turbo (U) +game_name = PUZZLEFIGHT2 +game_code = AZ8E +vender_code = 08 +idle_loop_eliminate_target = 08002b5e + +# Yu-Gi-Oh! - Dungeon Dice Monsters (U) +game_name = YU-GI-OH DDM +game_code = AYDE +vender_code = A4 +idle_loop_eliminate_target = 0802cc6a + +# Yu-Gi-Oh! - The Eternal Duelist Soul (U) +game_name = YU-GI-OH!EDS +game_code = AY5E +vender_code = A4 +idle_loop_eliminate_target = 08075d96 + +# Yu-Gi-Oh! - The Sacred Cards (U) +game_name = YUGIOH DM7 +game_code = AY7E +vender_code = A4 +idle_loop_eliminate_target = 08003bd6 + +# Yu-Gi-Oh! - World Championship Tournament 2004 (U) +game_name = YWCT2004USA +game_code = BYWE +vender_code = A4 +idle_loop_eliminate_target = 080831da + +# Yu-Gi-Oh! - Worldwide Edition - Stairway to the Destined Duel (U) +game_name = YUGIOHWWE +game_code = AYWE +vender_code = A4 +idle_loop_eliminate_target = 08089792 + +# Wario Ware, Inc. Mega Microgames (U) +game_name = WARIOWAREINC +game_code = AZWE +vender_code = 01 +idle_loop_eliminate_target = 08000f66 + +# Tom Clancy's Splinter Cell (U) +game_name = SPLINTERCELL +game_code = AO4E +vender_code = 41 +idle_loop_eliminate_target = 0807a0c4 + +# Tom Clancy's Splinter Cell - Pandora Tomorrow (U) +game_name = TOM CLANCY'S +game_code = BSLE +vender_code = 41 +idle_loop_eliminate_target = 0807785e + +# Final Fantasy IV Advance (U) +game_name = FF4ADVANCE +game_code = BZ4E +vender_code = 01 +idle_loop_eliminate_target = 0800fabe +# or try 00000430 + +# Digimon Battle Spirit (U) +game_name = DIGIMON BTSP +game_code = A8SE +vender_code = B2 +idle_loop_eliminate_target = 08011208 + +# Digimon Battle Spirit 2 (U) +game_name = DIGIMON BS2 +game_code = BDSE +vender_code = B2 +idle_loop_eliminate_target = 08010eb0 + +# Donald Duck Advance (U) +game_name = DISNEY'S DON +game_code = ADKE +vender_code = 41 +idle_loop_eliminate_target = 08002f30 + +# Final Fight One (U) +game_name = FINAL FIGHT +game_code = AFFE +vender_code = 08 +idle_loop_eliminate_target = 0800b428 + +# Megaman Battle Chip Challenge (U) +game_name = BATTLECHIPGP +game_code = A89E +vender_code = 08 +idle_loop_eliminate_target = 08000544 + +# Monster Force (U) +game_name = MONSTERFORCE +game_code = AM8E +vender_code = 7D +idle_loop_eliminate_target = 08000b00 + +# Monster Rancher Advance (U) +game_name = MONSRANCHERA +game_code = AMFE +vender_code = 9B +idle_loop_eliminate_target = 0809f394 + +# Monster Rancher Advance 2 (U) +game_name = MONSTERRANC2 +game_code = A2QE +vender_code = 9B +idle_loop_eliminate_target = 081c7290 + +# The Pinball of The Dead +game_name = PINBALL DEAD +game_code = APDE +vender_code = 78 +idle_loop_eliminate_target = 08000300 + +# Tringo (U) +game_name = TRINGO +game_code = BTJE +vender_code = 4Z +idle_loop_eliminate_target = 080009a4 + +# Virtual Kasparov (U) +game_name = VIRTKASPAROV +game_code = AVKE +vender_code = 60 +idle_loop_eliminate_target = 0800093a + +# Advance Wars 2 - Black Hole Rising (E) +game_name = ADVANCEWARS2 +game_code = AW2P +vender_code = 01 +idle_loop_eliminate_target = 080371be + +# Bookworm (U) +game_name = BOOKWORM +game_code = BKWE +vender_code = 5G +idle_loop_eliminate_target = 0800397c + +# 007 - Nightfire (U) +game_name = NIGHTFIRE +game_code = A7OE +vender_code = 69 +idle_loop_eliminate_target = 080031d6 + +# Asterix & Obelix XXL (E) +game_name = ASTERIX +game_code = BLXP +vender_code = 70 +idle_loop_eliminate_target = 0846d060 + +# Was this game released in Japan? What as? +# Ninja Five-0 (U) +game_name = NINJA FIVE 0 +game_code = ANXE +vender_code = A4 +iwram_stack_optimize = no + +# Ninja Cop (E) +game_name = NINJA COP +game_code = ANXP +vender_code = A4 +iwram_stack_optimize = no + +# Sennen Kazoku (J) +game_name = SENNENKAZOKU +game_code = BKAJ +vender_code = 01 +flash_rom_type = 128KB + +# Doom 2 (U) +game_name = DOOM II +game_code = A9DE +vender_code = 52 +translation_gate_target = 030041c8 +translation_gate_target = 03004fa0 + +# Bleach Advance (J) +game_name = BLEACH ADV1 +game_code = BLEJ +vender_code = 8P +iwram_stack_optimize = no + +# Shining Soul (J) +game_name = SHINING SOUL +game_code = AHUJ +vender_code = 8P +iwram_stack_optimize = no + +# Shining Soul (U) +game_name = SHINING SOUL +game_code = AHUE +vender_code = EB +iwram_stack_optimize = no + +# Shining Soul (E) +game_name = SHINING SOUL +game_code = AHUP +vender_code = 8P +iwram_stack_optimize = no + +# Shining Soul 2 (J) +game_name = SHININGSOUL2 +game_code = AU2J +vender_code = 8P +iwram_stack_optimize = no + +# Shining Soul 2 (U) +game_name = SHININGSOUL2 +game_code = AU2E +vender_code = EB +iwram_stack_optimize = no + +# Shining Soul 2 (E) +game_name = SHININGSOUL2 +game_code = AU2P +vender_code = 8P +iwram_stack_optimize = no + +# This is needed to make the game work. +# Another World (Homebrew) +game_name = FoxAnWorld +game_code = Home +vender_code = 00 +translation_gate_target = 03000f1c + diff --git a/gp2x/Makefile b/gp2x/Makefile new file mode 100644 index 0000000..e91ac43 --- /dev/null +++ b/gp2x/Makefile @@ -0,0 +1,51 @@ +# gpSP makefile +# Gilead Kutnick - Exophase +# GP2X port(ion) - Z + +# Global definitions + +PREFIX = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +CC = $(PREFIX)/bin/arm-open2x-linux-gcc +STRIP = $(PREFIX)/bin/arm-open2x-linux-strip + +OBJS = main.o cpu.o memory.u video.o input.o sound.o gp2x.o gui.o \ + cheats.o zip.o cpu_threaded.z cpu_speed.o cpuctrl.o \ + gp2xminilib.o font.o display.o speedtest.o cmdline.o daemon.o \ + arm_stub.o video_blend.o +BIN = gpsp.gpe + +# Platform specific definitions + +VPATH += .. +CFLAGS += -DARM_ARCH -DGP2X_BUILD +# NOTE: -funroll-loops will slow down compiling considerably +CFLAGS += -O3 -std=c99 -msoft-float -funsigned-char -fno-common \ + -fno-builtin \ + +INCLUDES = `$(PREFIX)/bin/arm-open2x-linux-sdl-config --cflags` +LIBS = `$(PREFIX)/bin/arm-open2x-linux-sdl-config --libs` \ + -lm -ldl -lpthread -lz -static + +# Compilation: + +.SUFFIXES: .c + +%.z: %.c + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +%.u: %.c + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +%.o: %.c + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +%.o: %.S + $(CC) $(ASFLAGS) $(INCLUDES) -c -o $@ $< + +all: $(OBJS) + $(CC) $(OBJS) $(LIBS) -o $(BIN) + $(STRIP) $(BIN) + +clean: + rm -f *.o *.u *.z $(BIN) + diff --git a/gp2x/align_test.c b/gp2x/align_test.c new file mode 100644 index 0000000..b7b3512 --- /dev/null +++ b/gp2x/align_test.c @@ -0,0 +1,48 @@ +// Betting on GCC aligning this for efficiency. +#include + +int main() +{ + unsigned short int read_16 = 0xF1F2; + unsigned int read_32 = 0xF1F2F3F4; + + unsigned short int write_16 = 0xF00D; + unsigned int write_32 = 0xF00DFEED; + // 16bit unsigned reads, we expect 0xF1F2 and 0xF20000F1 + fprintf(stderr, "%04x %04x\n", + *((unsigned short int *)((char *)&read_16)), + *((unsigned short int *)((char *)&read_16 + 1))); + + // 16bit signed reads, we expect 0xFFFFF1F2 and 0xFFFFFFF1 + fprintf(stderr, "%04x %04x\n", + *((short int *)((char *)&read_16)), + *((short int *)((char *)&read_16 + 1))); + + // 32bit reads, we expect 0xF1F2F3F4, 0xF4F1F2F3, 0xF3F4F1F2, + // and 0xF2F3F4F1 + + fprintf(stderr, "%08x %08x %08x %08x\n", + *((int *)((char *)&read_32)), + *((int *)((char *)&read_32 + 1)), + *((int *)((char *)&read_32 + 2)), + *((int *)((char *)&read_32 + 3))); + + // 16bit writes, we expect write_16 to remain 0xF00D + + *((short int *)((char *)&write_16)) = 0xF00D; + *((short int *)((char *)&write_16) + 1) = 0xF00D; + + fprintf(stderr, "%04x\n", write_16); + + // 32bit writes, we expect write_32 to remain 0xF00DFEED + + *((int *)((char *)&write_16)) = 0xF00DFEED; + *((int *)((char *)&write_16) + 1) = 0xF00DFEED; + *((int *)((char *)&write_16) + 2) = 0xF00DFEED; + *((int *)((char *)&write_16) + 3) = 0xF00DFEED; + + fprintf(stderr, "%08x\n", write_32); + + return 0; +} + diff --git a/gp2x/arm_codegen.h b/gp2x/arm_codegen.h new file mode 100644 index 0000000..42b8795 --- /dev/null +++ b/gp2x/arm_codegen.h @@ -0,0 +1,1392 @@ +/* + * arm-codegen.h + * + * Copyright (c) 2002 Wild West Software + * Copyright (c) 2001, 2002 Sergey Chaban + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#ifndef ARM_CG_H +#define ARM_CG_H + +typedef unsigned long arminstr_t; +typedef unsigned long armword_t; + +/* Helper functions */ +/*void arm_emit_std_prologue(cg_segment_t * segment, unsigned int local_size); +void arm_emit_std_epilogue(cg_segment_t * segment, unsigned int local_size, int pop_regs); +void arm_emit_lean_prologue(cg_segment_t * segment, unsigned int local_size, int push_regs); +int arm_is_power_of_2(armword_t val); +int calc_arm_mov_const_shift(armword_t val); +int is_arm_const(armword_t val); +int arm_bsf(armword_t val); +void arm_mov_reg_imm32_cond(cg_segment_t * segment, int reg, armword_t imm32, int cond); +void arm_mov_reg_imm32(cg_segment_t * segment, int reg, armword_t imm32);*/ + + +//*** check for correctness *** +//extern u32* x86Ptr; + +void write_to_file(u32 val); + +//#define write32(val) { *(u32 *)translation_ptr = val; write_to_file(*(u32 *)translation_ptr); translation_ptr += 4; } + +//#define write32(val) { if( g_PcWatch.IsReset == RECRESET_OFF ) { *(u32*)pCurPage->pCodeCurrent = val; pCurPage->pCodeCurrent +=4; if( (u32)pCurPage->pCodeCurrent >= (u32)pCurPage->pCodeEnd ) { g_PcWatch.IsReset = RECRESET_START; recResize(); g_PcWatch.IsReset = RECRESET_END; return; } }else{ if( g_PcWatch.IsReset == RECRESET_END ){ g_PcWatch.IsReset = RECRESET_OFF; return; } } } +//#define write32_ret(val) { if( g_PcWatch.IsReset == RECRESET_OFF ) { *(u32*)pCurPage->pCodeCurrent = val; pCurPage->pCodeCurrent +=4; if( (u32)pCurPage->pCodeCurrent >= (u32)pCurPage->pCodeEnd ) { g_PcWatch.IsReset = RECRESET_START; recResize(); g_PcWatch.IsReset = RECRESET_END; return 0; } }else{ if( g_PcWatch.IsReset == RECRESET_END ){ g_PcWatch.IsReset = RECRESET_OFF; return 0; } } } +//#define write32(val) { *(u32*)pCurPage->pCodeCurrent = val; pCurPage->pCodeCurrent +=4; } + +#define ARM_EMIT(p, i) write32(i); +//write32(i); +/*{ *(u32*)translation_ptr = (i); translation_ptr += 4; } */ + +#if defined(GIZMONDO) || defined(POCKETPC) /* Implemented but not working right yet for PPC */ + +// -------------------------------------------------------------------------- +// These declarations for coredll are extracted from platform builder +// source code +// -------------------------------------------------------------------------- + +/* Flags for CacheSync/CacheRangeFlush */ +#define CACHE_SYNC_DISCARD 0x001 /* write back & discard all cached data */ +#define CACHE_SYNC_INSTRUCTIONS 0x002 /* discard all cached instructions */ +#define CACHE_SYNC_WRITEBACK 0x004 /* write back but don't discard data cache*/ +#define CACHE_SYNC_FLUSH_I_TLB 0x008 /* flush I-TLB */ +#define CACHE_SYNC_FLUSH_D_TLB 0x010 /* flush D-TLB */ +#define CACHE_SYNC_FLUSH_TLB (CACHE_SYNC_FLUSH_I_TLB|CACHE_SYNC_FLUSH_D_TLB) /* flush all TLB */ +#define CACHE_SYNC_L2_WRITEBACK 0x020 /* write-back L2 Cache */ +#define CACHE_SYNC_L2_DISCARD 0x040 /* discard L2 Cache */ + +#define CACHE_SYNC_ALL 0x07F /* sync and discard everything in Cache/TLB */ + +extern "C" { + void CacheSync(int flags); +} +#define CLEAR_INSN_CACHE(BEG, END) CacheSync(CACHE_SYNC_INSTRUCTIONS | CACHE_SYNC_WRITEBACK); + +#else + +#if 0 +#define CLEAR_INSN_CACHE(BEG, END) \ +{ \ + register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \ + register unsigned long _end __asm ("a2") = (unsigned long) (END); \ + register unsigned long _flg __asm ("a3") = 0; \ + register unsigned long _scno __asm ("r7") = 0xf0002; \ + __asm __volatile ("swi 0x9f0002 @ sys_cacheflush" \ + : "=r" (_beg) \ + : "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno)); \ +} + +#endif + +#endif + +#if defined(_MSC_VER) && !defined(ARM_NOIASM) +# define ARM_IASM(_expr) __easfdmit (_expr) +#else +# define ARM_IASM(_expr) +#endif + +/* even_scale = rot << 1 */ +#define ARM_SCALE(imm8, even_scale) ( ((imm8) >> (even_scale)) | ((imm8) << (32 - even_scale)) ) + + + +typedef enum { + ARMREG_R0 = 0, + ARMREG_R1, + ARMREG_R2, + ARMREG_R3, + ARMREG_R4, + ARMREG_R5, + ARMREG_R6, + ARMREG_R7, + ARMREG_R8, + ARMREG_R9, + ARMREG_R10, + ARMREG_R11, + ARMREG_R12, + ARMREG_R13, + ARMREG_R14, + ARMREG_R15, + + + /* aliases */ + /* args */ + ARMREG_A1 = ARMREG_R0, + ARMREG_A2 = ARMREG_R1, + ARMREG_A3 = ARMREG_R2, + ARMREG_A4 = ARMREG_R3, + + /* local vars */ + ARMREG_V1 = ARMREG_R4, + ARMREG_V2 = ARMREG_R5, + ARMREG_V3 = ARMREG_R6, + ARMREG_V4 = ARMREG_R7, + ARMREG_V5 = ARMREG_R8, + ARMREG_V6 = ARMREG_R9, + ARMREG_V7 = ARMREG_R10, + + ARMREG_FP = ARMREG_R11, + ARMREG_IP = ARMREG_R12, + ARMREG_SP = ARMREG_R13, + ARMREG_LR = ARMREG_R14, + ARMREG_PC = ARMREG_R15, + + /* FPU */ + ARMREG_F0 = 0, + ARMREG_F1, + ARMREG_F2, + ARMREG_F3, + ARMREG_F4, + ARMREG_F5, + ARMREG_F6, + ARMREG_F7, + + /* co-processor */ + ARMREG_CR0 = 0, + ARMREG_CR1, + ARMREG_CR2, + ARMREG_CR3, + ARMREG_CR4, + ARMREG_CR5, + ARMREG_CR6, + ARMREG_CR7, + ARMREG_CR8, + ARMREG_CR9, + ARMREG_CR10, + ARMREG_CR11, + ARMREG_CR12, + ARMREG_CR13, + ARMREG_CR14, + ARMREG_CR15, + + /* XScale: acc0 on CP0 */ + ARMREG_ACC0 = ARMREG_CR0, + + ARMREG_MAX = ARMREG_R15, + + /* flags */ + ARMREG_CPSR = 0, + ARMREG_SPSR = 1 +} ARMReg; + +typedef enum { + ARM_FCONST_0_0 = 8, + ARM_FCONST_1_0, + ARM_FCONST_2_0, + ARM_FCONST_3_0, + ARM_FCONST_4_0, + ARM_FCONST_5_0, + ARM_FCONST_0_5, + ARM_FCONST_10_0 +} ARMFPUConst; + +/* number of argument registers */ +#define ARM_NUM_ARG_REGS 4 + +/* number of non-argument registers */ +#define ARM_NUM_VARIABLE_REGS 7 + +/* number of global registers */ +#define ARM_NUM_GLOBAL_REGS 5 + +/* bitvector for all argument regs (A1-A4) */ +#define ARM_ALL_ARG_REGS \ + (1 << ARMREG_A1) | (1 << ARMREG_A2) | (1 << ARMREG_A3) | (1 << ARMREG_A4) + + +typedef enum { + ARMCOND_EQ = 0x0, /* Equal; Z = 1 */ + ARMCOND_NE = 0x1, /* Not equal, or unordered; Z = 0 */ + ARMCOND_CS = 0x2, /* Carry set; C = 1 */ + ARMCOND_HS = ARMCOND_CS, /* Unsigned higher or same; */ + ARMCOND_CC = 0x3, /* Carry clear; C = 0 */ + ARMCOND_LO = ARMCOND_CC, /* Unsigned lower */ + ARMCOND_MI = 0x4, /* Negative; N = 1 */ + ARMCOND_PL = 0x5, /* Positive or zero; N = 0 */ + ARMCOND_VS = 0x6, /* Overflow; V = 1 */ + ARMCOND_VC = 0x7, /* No overflow; V = 0 */ + ARMCOND_HI = 0x8, /* Unsigned higher; C = 1 && Z = 0 */ + ARMCOND_LS = 0x9, /* Unsigned lower or same; C = 0 || Z = 1 */ + ARMCOND_GE = 0xA, /* Signed greater than or equal; N = V */ + ARMCOND_LT = 0xB, /* Signed less than; N != V */ + ARMCOND_GT = 0xC, /* Signed greater than; Z = 0 && N = V */ + ARMCOND_LE = 0xD, /* Signed less than or equal; Z = 1 && N != V */ + ARMCOND_AL = 0xE, /* Always */ + ARMCOND_NV = 0xF, /* Never */ + + ARMCOND_SHIFT = 28 +} ARMCond; + +#define ARMCOND_MASK (ARMCOND_NV << ARMCOND_SHIFT) + +#define ARM_DEF_COND(cond) (((cond) & 0xF) << ARMCOND_SHIFT) + + + +typedef enum { + ARMSHIFT_LSL = 0, + ARMSHIFT_LSR = 1, + ARMSHIFT_ASR = 2, + ARMSHIFT_ROR = 3, + + ARMSHIFT_ASL = ARMSHIFT_LSL + /* rrx = (ror, 1) */ +} ARMShiftType; + + +typedef struct { + armword_t PSR_c : 8; + armword_t PSR_x : 8; + armword_t PSR_s : 8; + armword_t PSR_f : 8; +} ARMPSR; + +typedef enum { + ARMOP_AND = 0x0, + ARMOP_EOR = 0x1, + ARMOP_SUB = 0x2, + ARMOP_RSB = 0x3, + ARMOP_ADD = 0x4, + ARMOP_ADC = 0x5, + ARMOP_SBC = 0x6, + ARMOP_RSC = 0x7, + ARMOP_TST = 0x8, + ARMOP_TEQ = 0x9, + ARMOP_CMP = 0xa, + ARMOP_CMN = 0xb, + ARMOP_ORR = 0xc, + ARMOP_MOV = 0xd, + ARMOP_BIC = 0xe, + ARMOP_MVN = 0xf, + + + /* not really opcodes */ + + ARMOP_STR = 0x0, + ARMOP_LDR = 0x1, + + /* ARM2+ */ + ARMOP_MUL = 0x0, /* Rd := Rm*Rs */ + ARMOP_MLA = 0x1, /* Rd := (Rm*Rs)+Rn */ + + /* ARM3M+ */ + ARMOP_UMULL = 0x4, + ARMOP_UMLAL = 0x5, + ARMOP_SMULL = 0x6, + ARMOP_SMLAL = 0x7, + + /* for data transfers with register offset */ + ARM_UP = 1, + ARM_DOWN = 0 +} ARMOpcode; + +typedef enum { + THUMBOP_AND = 0, + THUMBOP_EOR = 1, + THUMBOP_LSL = 2, + THUMBOP_LSR = 3, + THUMBOP_ASR = 4, + THUMBOP_ADC = 5, + THUMBOP_SBC = 6, + THUMBOP_ROR = 7, + THUMBOP_TST = 8, + THUMBOP_NEG = 9, + THUMBOP_CMP = 10, + THUMBOP_CMN = 11, + THUMBOP_ORR = 12, + THUMBOP_MUL = 13, + THUMBOP_BIC = 14, + THUMBOP_MVN = 15, + THUMBOP_MOV = 16, + THUMBOP_CMPI = 17, + THUMBOP_ADD = 18, + THUMBOP_SUB = 19, + THUMBOP_CMPH = 19, + THUMBOP_MOVH = 20 +} ThumbOpcode; + + +/* Generic form - all ARM instructions are conditional. */ +typedef struct { + arminstr_t icode : 28; + arminstr_t cond : 4; +} ARMInstrGeneric; + + + +/* Branch or Branch with Link instructions. */ +typedef struct { + arminstr_t offset : 24; + arminstr_t link : 1; + arminstr_t tag : 3; /* 1 0 1 */ + arminstr_t cond : 4; +} ARMInstrBR; + +#define ARM_BR_ID 5 +#define ARM_BR_MASK 7 << 25 +#define ARM_BR_TAG ARM_BR_ID << 25 + +#define ARM_DEF_BR(offs, l, cond) ((offs) | ((l) << 24) | (ARM_BR_TAG) | (cond << ARMCOND_SHIFT)) + +/* branch */ +#define ARM_B_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 0, cond)) +#define ARM_B(p, offs) ARM_B_COND((p), ARMCOND_AL, (offs)) +/* branch with link */ +#define ARM_BL_COND(p, cond, offset) ARM_EMIT(p, ARM_DEF_BR(offset, 1, cond)) +#define ARM_BL(p, offs) ARM_BL_COND((p), ARMCOND_AL, (offs)) + +/* branch to register and exchange */ +#define ARM_BX_COND(p, cond, reg) ARM_EMIT(p, ((cond << ARMCOND_SHIFT) | (reg) | 0x12FFF10)) +#define ARM_BX(p, reg) ARM_BX_COND((p), ARMCOND_AL, (reg)) + +/* branch to register with link */ +#define ARM_BLX_COND(p, cond, reg) ARM_EMIT(p, ((cond << ARMCOND_SHIFT) | (reg) | 0x12FFF30)) +#define ARM_BLX(p, reg) ARM_BLX_COND((p), ARMCOND_AL, (reg)) + + +/* Data Processing Instructions - there are 3 types. */ + +typedef struct { + arminstr_t imm : 8; + arminstr_t rot : 4; +} ARMDPI_op2_imm; + +typedef struct { + arminstr_t rm : 4; + arminstr_t tag : 1; /* 0 - immediate shift, 1 - reg shift */ + arminstr_t type : 2; /* shift type - logical, arithmetic, rotate */ +} ARMDPI_op2_reg_shift; + + +/* op2 is reg shift by imm */ +typedef union { + ARMDPI_op2_reg_shift r2; + struct { + arminstr_t _dummy_r2 : 7; + arminstr_t shift : 5; + } imm; +} ARMDPI_op2_reg_imm; + +/* op2 is reg shift by reg */ +typedef union { + ARMDPI_op2_reg_shift r2; + struct { + arminstr_t _dummy_r2 : 7; + arminstr_t pad : 1; /* always 0, to differentiate from HXFER etc. */ + arminstr_t rs : 4; + } reg; +} ARMDPI_op2_reg_reg; + +/* Data processing instrs */ +typedef union { + ARMDPI_op2_imm op2_imm; + + ARMDPI_op2_reg_shift op2_reg; + ARMDPI_op2_reg_imm op2_reg_imm; + ARMDPI_op2_reg_reg op2_reg_reg; + + struct { + arminstr_t op2 : 12; /* raw operand 2 */ + arminstr_t rd : 4; /* destination reg */ + arminstr_t rn : 4; /* first operand reg */ + arminstr_t s : 1; /* S-bit controls PSR update */ + arminstr_t opcode : 4; /* arithmetic/logic operation */ + arminstr_t type : 1; /* type of op2, 0 = register, 1 = immediate */ + arminstr_t tag : 2; /* 0 0 */ + arminstr_t cond : 4; + } all; +} ARMInstrDPI; + +#define ARM_DPI_ID 0 +#define ARM_DPI_MASK 3 << 26 +#define ARM_DPI_TAG ARM_DPI_ID << 26 + +#define ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, cond) \ + ((imm8) & 0xFF) | \ + (((rot) & 0xF) << 8) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((s) << 20) | \ + ((op) << 21) | \ + (1 << 25) | \ + (ARM_DPI_TAG) | \ + ARM_DEF_COND(cond) + + +#define ARM_DEF_DPI_IMM(imm8, rot, rd, rn, s, op) \ + ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, ARMCOND_AL) + +/* codegen */ +#define ARM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond)) +#define ARM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond)) + +/* inline */ +#define ARM_IASM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \ + ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond)) +#define ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \ + ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond)) + + + +#define ARM_DEF_DPI_REG_IMMSHIFT_COND(rm, shift_type, imm_shift, rd, rn, s, op, cond) \ + (rm) | \ + ((shift_type & 3) << 5) | \ + (((imm_shift) & 0x1F) << 7) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((s) << 20) | \ + ((op) << 21) | \ + (ARM_DPI_TAG) | \ + ARM_DEF_COND(cond) + +/* codegen */ +#define ARM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_type, imm_shift, (rd), (rn), 0, (op), cond)) + +#define ARM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_type, imm_shift, (rd), (rn), 1, (op), cond)) + +#define ARM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond)) + +#define ARM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond)) + +/* inline */ +#define ARM_IASM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_type, imm_shift, (rd), (rn), 0, (op), cond)) + +#define ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_type, imm_shift, (rd), (rn), 1, (op), cond)) + +#define ARM_IASM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \ + ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond)) + +#define ARM_IASM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \ + ARM_IASM_EMIT(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond)) + + +/* Rd := Rn op (Rm shift_type Rs) */ +#define ARM_DEF_DPI_REG_REGSHIFT_COND(rm, shift_type, rs, rd, rn, s, op, cond) \ + (rm) | \ + (1 << 4) | \ + ((shift_type & 3) << 5) | \ + ((rs) << 8) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((s) << 20) | \ + ((op) << 21) | \ + (ARM_DPI_TAG) | \ + ARM_DEF_COND(cond) + +/* codegen */ +#define ARM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_type, rs, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_type, (rs), (rd), (rn), 0, (op), cond)) + +#define ARM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_type, rs, cond) \ + ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_type, (rs), (rd), (rn), 1, (op), cond)) + +/* inline */ +#define ARM_IASM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_type, (rs), (rd), (rn), 0, (op), cond)) + +#define ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_type, (rs), (rd), (rn), 1, (op), cond)) + + + +/* Multiple register transfer. */ +typedef struct { + arminstr_t reg_list : 16; /* bitfield */ + arminstr_t rn : 4; /* base reg */ + arminstr_t ls : 1; /* load(1)/store(0) */ + arminstr_t wb : 1; /* write-back "!" */ + arminstr_t s : 1; /* restore PSR, force user bit */ + arminstr_t u : 1; /* up/down */ + arminstr_t p : 1; /* pre(1)/post(0) index */ + arminstr_t tag : 3; /* 1 0 0 */ + arminstr_t cond : 4; +} ARMInstrMRT; + +#define ARM_MRT_ID 4 +#define ARM_MRT_MASK 7 << 25 +#define ARM_MRT_TAG ARM_MRT_ID << 25 + +#define ARM_DEF_MRT(regs, rn, l, w, s, u, p, cond) \ + (regs) | \ + (rn << 16) | \ + (l << 20) | \ + (w << 21) | \ + (s << 22) | \ + (u << 23) | \ + (p << 24) | \ + (ARM_MRT_TAG) | \ + ARM_DEF_COND(cond) + +#define ARM_STMDB(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 0, 0, 0, 0, 1, ARMCOND_AL)) +#define ARM_LDMDB(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 1, 0, 0, 0, 1, ARMCOND_AL)) +#define ARM_STMDB_WB(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 0, 1, 0, 0, 1, ARMCOND_AL)) +#define ARM_LDMIA_WB(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 1, 1, 0, 1, 0, ARMCOND_AL)) +#define ARM_LDMIA(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 1, 0, 0, 1, 0, ARMCOND_AL)) +#define ARM_STMIA(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 0, 0, 0, 1, 0, ARMCOND_AL)) +#define ARM_STMIA_WB(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 0, 1, 0, 1, 0, ARMCOND_AL)) + +#define ARM_LDMIA_WB_PC_S(p, rbase, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, rbase, 1, 1, 1, 1, 0, ARMCOND_AL)) + +/* THUMB +#define ARM_POP_OP(p) ARM_EMIT(p, 0xFF01BD17) +#define ARM_PUSH_OP(p) ARM_EMIT(p, 0xFF02B497) +*/ + +/* stmdb sp!, {regs} */ +#define ARM_PUSH(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL)) +#define ARM_IASM_PUSH(regs) ARM_IASM(ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL)) + +/* ldmia sp!, {regs} */ +#define ARM_POP(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL)) +#define ARM_IASM_POP(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL)) + +/* ldmia sp, {regs} ; (no write-back) */ +#define ARM_POP_NWB(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL)) +#define ARM_IASM_POP_NWB(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL)) + +#define ARM_PUSH1(p, r1) ARM_PUSH(p, (1 << r1)) +#define ARM_PUSH2(p, r1, r2) ARM_PUSH(p, (1 << r1) | (1 << r2)) +#define ARM_PUSH3(p, r1, r2, r3) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3)) +#define ARM_PUSH4(p, r1, r2, r3, r4) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4)) +#define ARM_PUSH5(p, r1, r2, r3, r4, r5) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5)) +#define ARM_PUSH6(p, r1, r2, r3, r4, r5, r6) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6)) +#define ARM_PUSH7(p, r1, r2, r3, r4, r5, r6, r7) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7)) +#define ARM_PUSH8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8)) +#define ARM_PUSH9(p, r1, r2, r3, r4, r5, r6, r7, r8, r9) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8) | (1 << r9)) + +#define ARM_POP9(p, r1, r2, r3, r4, r5, r6, r7, r8, r9) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8) | (1 << r9)) +#define ARM_POP8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8)) +#define ARM_POP7(p, r1, r2, r3, r4, r5, r6, r7) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7)) +#define ARM_POP6(p, r1, r2, r3, r4, r5, r6) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6)) +#define ARM_POP5(p, r1, r2, r3, r4, r5) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5)) +#define ARM_POP4(p, r1, r2, r3, r4) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4)) +#define ARM_POP3(p, r1, r2, r3) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3)) +#define ARM_POP2(p, r1, r2) ARM_POP(p, (1 << r1) | (1 << r2)) +#define ARM_POP1(p, r1) ARM_POP(p, (1 << r1)) + + +/* Multiply instructions */ +typedef struct { + arminstr_t rm : 4; + arminstr_t tag2 : 4; /* 9 */ + arminstr_t rs : 4; + arminstr_t rn : 4; + arminstr_t rd : 4; + arminstr_t s : 1; + arminstr_t opcode : 3; + arminstr_t tag : 4; + arminstr_t cond : 4; +} ARMInstrMul; + +#define ARM_MUL_ID 0 +#define ARM_MUL_ID2 9 +#define ARM_MUL_MASK ((0xF << 24) | (0xF << 4)) +#define ARM_MUL_TAG ((ARM_MUL_ID << 24) | (ARM_MUL_ID2 << 4)) + +#define ARM_DEF_MUL_COND(op, rd, rm, rs, rn, s, cond) \ + (rm) | \ + ((rs) << 8) | \ + ((rn) << 12) | \ + ((rd) << 16) | \ + (((s) & 1) << 20) | \ + (((op) & 7) << 21) | \ + ARM_MUL_TAG | \ + ARM_DEF_COND(cond) + +/* Rd := (Rm * Rs)[31:0]; 32 x 32 -> 32 */ +#define ARM_MUL_COND(p, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond)) +#define ARM_MUL(p, rd, rm, rs) \ + ARM_MUL_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_MULS_COND(p, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond)) +#define ARM_MULS(p, rd, rm, rs) \ + ARM_MULS_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_MUL_REG_REG(p, rd, rm, rs) ARM_MUL(p, rd, rm, rs) +#define ARM_MULS_REG_REG(p, rd, rm, rs) ARM_MULS(p, rd, rm, rs) + +/* inline */ +#define ARM_IASM_MUL_COND(rd, rm, rs, cond) \ + ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond)) +#define ARM_IASM_MUL(rd, rm, rs) \ + ARM_IASM_MUL_COND(rd, rm, rs, ARMCOND_AL) +#define ARM_IASM_MULS_COND(rd, rm, rs, cond) \ + ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond)) +#define ARM_IASM_MULS(rd, rm, rs) \ + ARM_IASM_MULS_COND(rd, rm, rs, ARMCOND_AL) + + +/* Rd := (Rm * Rs) + Rn; 32x32+32->32 */ +#define ARM_MLA_COND(p, rd, rm, rs, rn, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond)) +#define ARM_MLA(p, rd, rm, rs, rn) \ + ARM_MLA_COND(p, rd, rm, rs, rn, ARMCOND_AL) +#define ARM_MLAS_COND(p, rd, rm, rs, rn, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond)) +#define ARM_MLAS(p, rd, rm, rs, rn) \ + ARM_MLAS_COND(p, rd, rm, rs, rn, ARMCOND_AL) + +/* inline */ +#define ARM_IASM_MLA_COND(rd, rm, rs, rn, cond) \ + ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond)) +#define ARM_IASM_MLA(rd, rm, rs, rn) \ + ARM_IASM_MLA_COND(rd, rm, rs, rn, ARMCOND_AL) +#define ARM_IASM_MLAS_COND(rd, rm, rs, rn, cond) \ + ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond)) +#define ARM_IASM_MLAS(rd, rm, rs, rn) \ + ARM_IASM_MLAS_COND(rd, rm, rs, rn, ARMCOND_AL) + + +#define ARM_SMULL_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMULL, rd, rm, rs, rn, 0, cond)) +#define ARM_SMULL(p, rn, rd, rm, rs) \ + ARM_SMULL_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_SMLAL_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMLAL, rd, rm, rs, rn, 0, cond)) +#define ARM_SMLAL(p, rn, rd, rm, rs) \ + ARM_SMLAL_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_UMULL_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMULL, rd, rm, rs, rn, 0, cond)) +#define ARM_UMULL(p, rn, rd, rm, rs) \ + ARM_UMULL_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_UMLAL_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMLAL, rd, rm, rs, rn, 0, cond)) +#define ARM_UMLAL(p, rn, rd, rm, rs) \ + ARM_UMLAL_COND(p, rn, rd, rm, rs, ARMCOND_AL) + + +#define ARM_SMULLS_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMULL, rd, rm, rs, rn, 1, cond)) +#define ARM_SMULLS(p, rn, rd, rm, rs) \ + ARM_SMULLS_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_SMLALS_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_SMLAL, rd, rm, rs, rn, 1, cond)) +#define ARM_SMLALS(p, rn, rd, rm, rs) \ + ARM_SMLALS_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_UMULLS_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMULL, rd, rm, rs, rn, 1, cond)) +#define ARM_UMULLS(p, rn, rd, rm, rs) \ + ARM_UMULLS_COND(p, rn, rd, rm, rs, ARMCOND_AL) + +#define ARM_UMLALS_COND(p, rn, rd, rm, rs, cond) \ + ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_UMLAL, rd, rm, rs, rn, 1, cond)) +#define ARM_UMLALS(p, rn, rd, rm, rs) \ + ARM_UMLALS_COND(p, rn, rd, rm, rs, ARMCOND_AL) + + + +/* Word/byte transfer */ +typedef union { + ARMDPI_op2_reg_imm op2_reg_imm; + struct { + arminstr_t op2_imm : 12; + arminstr_t rd : 4; + arminstr_t rn : 4; + arminstr_t ls : 1; + arminstr_t wb : 1; + arminstr_t b : 1; + arminstr_t u : 1; /* down(0) / up(1) */ + arminstr_t p : 1; /* post-index(0) / pre-index(1) */ + arminstr_t type : 1; /* imm(0) / register(1) */ + arminstr_t tag : 2; /* 0 1 */ + arminstr_t cond : 4; + } all; +} ARMInstrWXfer; + +#define ARM_WXFER_ID 1 +#define ARM_WXFER_MASK 3 << 26 +#define ARM_WXFER_TAG ARM_WXFER_ID << 26 + + +/* + * ls : opcode, ARMOP_STR(0)/ARMOP_LDR(1) + * imm12 : immediate offset + * wb : write-back + * p : index mode, post-index (0, automatic write-back) + * or pre-index (1, calc effective address before memory access) + */ +#define ARM_DEF_WXFER_IMM(imm12, rd, rn, ls, wb, b, p, cond) \ + ((((int)(imm12)) < 0) ? -((int)(imm12)) : (imm12)) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((ls) << 20) | \ + ((wb) << 21) | \ + ((b) << 22) | \ + (((int)(imm12) >= 0) << 23) | \ + ((p) << 24) | \ + ARM_WXFER_TAG | \ + ARM_DEF_COND(cond) + +#define ARM_WXFER_MAX_OFFS 0xFFF + +/* this macro checks for imm12 bounds */ +#define ARM_EMIT_WXFER_IMM(ptr, imm12, rd, rn, ls, wb, b, p, cond) \ + do { \ + int _imm12 = (int)(imm12) < -ARM_WXFER_MAX_OFFS \ + ? -ARM_WXFER_MAX_OFFS \ + : (int)(imm12) > ARM_WXFER_MAX_OFFS \ + ? ARM_WXFER_MAX_OFFS \ + : (int)(imm12); \ + ARM_EMIT((ptr), \ + ARM_DEF_WXFER_IMM(_imm12, (rd), (rn), (ls), (wb), (b), (p), (cond))); \ + } while (0) + + +/* LDRx */ +/* immediate offset, post-index */ +#define ARM_LDR_IMM_POST_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 0, cond)) + +#define ARM_LDR_IMM_POST(p, rd, rn, imm) ARM_LDR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL) + +#define ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 0, cond)) + +#define ARM_LDRB_IMM_POST(p, rd, rn, imm) ARM_LDRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL) + +/* immediate offset, pre-index */ +#define ARM_LDR_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 0, 1, cond)) + +#define ARM_LDR_IMM(p, rd, rn, imm) ARM_LDR_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + +#define ARM_LDRB_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_LDR, 0, 1, 1, cond)) + +#define ARM_LDRB_IMM(p, rd, rn, imm) ARM_LDRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + + +/* STRx */ +/* immediate offset, post-index */ +#define ARM_STR_IMM_POST_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 0, cond)) + +#define ARM_STR_IMM_POST(p, rd, rn, imm) ARM_STR_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL) + +#define ARM_STRB_IMM_POST_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 0, cond)) + +#define ARM_STRB_IMM_POST(p, rd, rn, imm) ARM_STRB_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL) + +/* immediate offset, pre-index */ +#define ARM_STR_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 0, 0, 1, cond) +/* ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 1, cond))*/ +/* ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 0, 0, 1, cond) */ +/* ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 0, 1, cond)) */ + +#define ARM_STR_IMM(p, rd, rn, imm) ARM_STR_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + +#define ARM_STRB_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_IMM(imm, rd, rn, ARMOP_STR, 0, 1, 1, cond)) + +#define ARM_STRB_IMM(p, rd, rn, imm) ARM_STRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + +/* write-back */ +#define ARM_STR_IMM_WB_COND(p, rd, rn, imm, cond) \ + ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 1, 0, 1, cond) +#define ARM_STR_IMM_WB(p, rd, rn, imm) ARM_STR_IMM_WB_COND(p, rd, rn, imm, ARMCOND_AL) + + +/* + * wb : write-back + * u : down(0) / up(1) + * p : index mode, post-index (0, automatic write-back) or pre-index (1) + */ +#define ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, u, p, cond) \ + (rm) | \ + ((shift_type) << 5) | \ + ((shift) << 7) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((ls) << 20) | \ + ((wb) << 21) | \ + ((b) << 22) | \ + ((u) << 23) | \ + ((p) << 24) | \ + (1 << 25) | \ + ARM_WXFER_TAG | \ + ARM_DEF_COND(cond) + +#define ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \ + ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_UP, p, cond) +#define ARM_DEF_WXFER_REG_MINUS_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \ + ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_DOWN, p, cond) + + +#define ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 0, 1, cond)) +#define ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \ + ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL) +#define ARM_LDR_REG_REG(p, rd, rn, rm) \ + ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0) + +#define ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 1, 1, cond)) +#define ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \ + ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL) +#define ARM_LDRB_REG_REG(p, rd, rn, rm) \ + ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0) + +#define ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 0, 1, cond)) +#define ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \ + ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL) +#define ARM_STR_REG_REG(p, rd, rn, rm) \ + ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0) + +/* post-index */ +#define ARM_STR_REG_REG_SHIFT_POST_COND(p, rd, rn, rm, shift_type, shift, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 0, 0, cond)) +#define ARM_STR_REG_REG_SHIFT_POST(p, rd, rn, rm, shift_type, shift) \ + ARM_STR_REG_REG_SHIFT_POST_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL) +#define ARM_STR_REG_REG_POST(p, rd, rn, rm) \ + ARM_STR_REG_REG_SHIFT_POST(p, rd, rn, rm, ARMSHIFT_LSL, 0) + +/* zero-extend */ +#define ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \ + ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 1, 1, cond)) +#define ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \ + ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL) +#define ARM_STRB_REG_REG(p, rd, rn, rm) \ + ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0) + + +/* ARMv4+ */ +/* Half-word or byte (signed) transfer. */ +typedef struct { + arminstr_t rm : 4; /* imm_lo */ + arminstr_t tag3 : 1; /* 1 */ + arminstr_t h : 1; /* half-word or byte */ + arminstr_t s : 1; /* sign-extend or zero-extend */ + arminstr_t tag2 : 1; /* 1 */ + arminstr_t imm_hi : 4; + arminstr_t rd : 4; + arminstr_t rn : 4; + arminstr_t ls : 1; + arminstr_t wb : 1; + arminstr_t type : 1; /* imm(1) / reg(0) */ + arminstr_t u : 1; /* +- */ + arminstr_t p : 1; /* pre/post-index */ + arminstr_t tag : 3; + arminstr_t cond : 4; +} ARMInstrHXfer; + +#define ARM_HXFER_ID 0 +#define ARM_HXFER_ID2 1 +#define ARM_HXFER_ID3 1 +#define ARM_HXFER_MASK ((0x7 << 25) | (0x9 << 4)) +#define ARM_HXFER_TAG ((ARM_HXFER_ID << 25) | (ARM_HXFER_ID2 << 7) | (ARM_HXFER_ID3 << 4)) + +#define ARM_DEF_HXFER_IMM_COND(imm, h, s, rd, rn, ls, wb, p, cond) \ + (((int)(imm) >= 0 ? (imm) : -(int)(imm)) & 0xF) | \ + ((h) << 5) | \ + ((s) << 6) | \ + ((((int)(imm) >= 0 ? (imm) : -(int)(imm)) << 4) & (0xF << 8)) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((ls) << 20) | \ + ((wb) << 21) | \ + (1 << 22) | \ + (((int)(imm) >= 0) << 23) | \ + ((p) << 24) | \ + ARM_HXFER_TAG | \ + ARM_DEF_COND(cond) + +#define ARM_LDRH_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRH_IMM(p, rd, rn, imm) \ + ARM_LDRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL) +#define ARM_LDRSH_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRSH_IMM(p, rd, rn, imm) \ + ARM_LDRSH_IMM_COND(p, rd, rn, imm, ARMCOND_AL) +#define ARM_LDRSB_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRSB_IMM(p, rd, rn, imm) \ + ARM_LDRSB_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + + +#define ARM_STRH_IMM_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond)) +#define ARM_STRH_IMM(p, rd, rn, imm) \ + ARM_STRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL) + +#define ARM_STRH_IMM_POST_COND(p, rd, rn, imm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_IMM_COND(imm, 1, 0, rd, rn, ARMOP_STR, 0, 0, cond)) +#define ARM_STRH_IMM_POST(p, rd, rn, imm) \ + ARM_STRH_IMM_POST_COND(p, rd, rn, imm, ARMCOND_AL) + + +#define ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, u, p, cond) \ + ((rm) & 0xF) | \ + ((h) << 5) | \ + ((s) << 6) | \ + ((rd) << 12) | \ + ((rn) << 16) | \ + ((ls) << 20) | \ + ((wb) << 21) | \ + (0 << 22) | \ + ((u) << 23) | \ + ((p) << 24) | \ + ARM_HXFER_TAG | \ + ARM_DEF_COND(cond) + +#define ARM_DEF_HXFER_REG_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \ + ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_UP, p, cond) +#define ARM_DEF_HXFER_REG_MINUS_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \ + ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_DOWN, p, cond) + +#define ARM_LDRH_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRH_REG_REG(p, rd, rn, rm) \ + ARM_LDRH_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_LDRSH_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRSH_REG_REG(p, rd, rn, rm) \ + ARM_LDRSH_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_LDRSB_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond)) +#define ARM_LDRSB_REG_REG(p, rd, rn, rm) ARM_LDRSB_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#define ARM_STRH_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond)) +#define ARM_STRH_REG_REG(p, rd, rn, rm) \ + ARM_STRH_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#define ARM_STRH_REG_REG_POST_COND(p, rd, rn, rm, cond) \ + ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_STR, 0, 0, cond)) +#define ARM_STRH_REG_REG_POST(p, rd, rn, rm) \ + ARM_STRH_REG_REG_POST_COND(p, rd, rn, rm, ARMCOND_AL) + + + +/* Swap */ +typedef struct { + arminstr_t rm : 4; + arminstr_t tag3 : 8; /* 0x9 */ + arminstr_t rd : 4; + arminstr_t rn : 4; + arminstr_t tag2 : 2; + arminstr_t b : 1; + arminstr_t tag : 5; /* 0x2 */ + arminstr_t cond : 4; +} ARMInstrSwap; + +#define ARM_SWP_ID 2 +#define ARM_SWP_ID2 9 +#define ARM_SWP_MASK ((0x1F << 23) | (3 << 20) | (0xFF << 4)) +#define ARM_SWP_TAG ((ARM_SWP_ID << 23) | (ARM_SWP_ID2 << 4)) + + + +/* Software interrupt */ +typedef struct { + arminstr_t num : 24; + arminstr_t tag : 4; + arminstr_t cond : 4; +} ARMInstrSWI; + +#define ARM_SWI_ID 0xF +#define ARM_SWI_MASK (0xF << 24) +#define ARM_SWI_TAG (ARM_SWI_ID << 24) + + + +/* Co-processor Data Processing */ +typedef struct { + arminstr_t crm : 4; + arminstr_t tag2 : 1; /* 0 */ + arminstr_t op2 : 3; + arminstr_t cpn : 4; /* CP number */ + arminstr_t crd : 4; + arminstr_t crn : 4; + arminstr_t op : 4; + arminstr_t tag : 4; /* 0xE */ + arminstr_t cond : 4; +} ARMInstrCDP; + +#define ARM_CDP_ID 0xE +#define ARM_CDP_ID2 0 +#define ARM_CDP_MASK ((0xF << 24) | (1 << 4)) +#define ARM_CDP_TAG ((ARM_CDP_ID << 24) | (ARM_CDP_ID2 << 4)) + + +/* Co-processor Data Transfer (ldc/stc) */ +typedef struct { + arminstr_t offs : 8; + arminstr_t cpn : 4; + arminstr_t crd : 4; + arminstr_t rn : 4; + arminstr_t ls : 1; + arminstr_t wb : 1; + arminstr_t n : 1; + arminstr_t u : 1; + arminstr_t p : 1; + arminstr_t tag : 3; + arminstr_t cond : 4; +} ARMInstrCDT; + +#define ARM_CDT_ID 6 +#define ARM_CDT_MASK (7 << 25) +#define ARM_CDT_TAG (ARM_CDT_ID << 25) + + +/* Co-processor Register Transfer (mcr/mrc) */ +typedef struct { + arminstr_t crm : 4; + arminstr_t tag2 : 1; + arminstr_t op2 : 3; + arminstr_t cpn : 4; + arminstr_t rd : 4; + arminstr_t crn : 4; + arminstr_t ls : 1; + arminstr_t op1 : 3; + arminstr_t tag : 4; + arminstr_t cond : 4; +} ARMInstrCRT; + +#define ARM_CRT_ID 0xE +#define ARM_CRT_ID2 0x1 +#define ARM_CRT_MASK ((0xF << 24) | (1 << 4)) +#define ARM_CRT_TAG ((ARM_CRT_ID << 24) | (ARM_CRT_ID2 << 4)) + +/* + * Move from co-processor register to CPU register + * Rd := cRn {cRm} + * op{condition} CP#,CPOp,Rd,CRn,CRm{,CPOp2} + */ +#define ARM_DEF_MRC_COND(cpn, cpop, rd, crn, crm, cpop2, cond) \ + ((crm) & 0xF) |\ + ((cpop2) << 5) |\ + ((cpn) << 8) |\ + ((rd) << 12) |\ + ((crn) << 16) |\ + ((ARMOP_LDR) << 20) |\ + ((cpop) << 21) |\ + ARM_CRT_TAG |\ + ARM_DEF_COND(cond) + +#define ARM_MRC_COND(p, cpn, cpop, rd, crn, crm, cpop2, cond) \ + ARM_EMIT(p, ARM_DEF_MRC_COND(cpn, cpop, rd, crn, crm, cpop2, cond)) +#define ARM_MRC(p, cpn, cpop, rd, crn, crm, cpop2) \ + ARM_MRC_COND(p, cpn, cpop, rd, crn, crm, cpop2, ARMCOND_AL) + + + +/* Move register to PSR. */ +typedef union { + ARMDPI_op2_imm op2_imm; + struct { + arminstr_t rm : 4; + arminstr_t pad : 8; /* 0 */ + arminstr_t tag4 : 4; /* 0xF */ + arminstr_t fld : 4; + arminstr_t tag3 : 2; /* 0x2 */ + arminstr_t sel : 1; + arminstr_t tag2 : 2; /* 0x2 */ + arminstr_t type : 1; + arminstr_t tag : 2; /* 0 */ + arminstr_t cond : 4; + } all; +} ARMInstrMSR; + +#define ARM_MSR_ID 0 +#define ARM_MSR_ID2 2 +#define ARM_MSR_ID3 2 +#define ARM_MSR_ID4 0xF +#define ARM_MSR_MASK ((3 << 26) | \ + (3 << 23) | \ + (3 << 20) | \ + (0xF << 12)) +#define ARM_MSR_TAG ((ARM_MSR_ID << 26) | \ + (ARM_MSR_ID2 << 23) | \ + (ARM_MSR_ID3 << 20) | \ + (ARM_MSR_ID4 << 12)) + +#define ARM_DEF_MSR_REG_COND(mask, rm, r, cond) \ + ARM_MSR_TAG | \ + ARM_DEF_COND(cond) | \ + ((rm) & 0xf) | \ + (((r) & 1) << 22) | \ + (((mask) & 0xf) << 16) + +#define ARM_MSR_REG_COND(p, mask, rm, r, cond) \ + ARM_EMIT(p, ARM_DEF_MSR_REG_COND(mask, rm, r, cond)) + +#define ARM_MSR_REG(p, mask, rm, r) \ + ARM_MSR_REG_COND(p, mask, rm, r, ARMCOND_AL) + +#define ARM_PSR_C 1 +#define ARM_PSR_X 2 +#define ARM_PSR_S 4 +#define ARM_PSR_F 8 + +#define ARM_CPSR 0 +#define ARM_SPSR 1 + +/* Move PSR to register. */ +typedef struct { + arminstr_t tag3 : 12; + arminstr_t rd : 4; + arminstr_t tag2 : 6; + arminstr_t sel : 1; /* CPSR | SPSR */ + arminstr_t tag : 5; + arminstr_t cond : 4; +} ARMInstrMRS; + +#define ARM_MRS_ID 2 +#define ARM_MRS_ID2 0xF +#define ARM_MRS_ID3 0 +#define ARM_MRS_MASK ((0x1F << 23) | (0x3F << 16) | 0xFFF) +#define ARM_MRS_TAG ((ARM_MRS_ID << 23) | (ARM_MRS_ID2 << 16) | ARM_MRS_ID3) + +#define ARM_DEF_MRS_COND(rd, r, cond) \ + ARM_MRS_TAG | \ + ARM_DEF_COND(cond) | \ + (((r) & 1) << 22) | \ + ((rd)& 0xf) << 12 + +#define ARM_MRS_COND(p, rd, r, cond) \ + ARM_EMIT(p, ARM_DEF_MRS_COND(rd, r, cond)) + +#define ARM_MRS_CPSR_COND(p, rd, cond) \ + ARM_MRS_COND(p, rd, ARM_CPSR, cond) + +#define ARM_MRS_CPSR(p, rd) \ + ARM_MRS_CPSR_COND(p, rd, ARMCOND_AL) + +#define ARM_MRS_SPSR_COND(p, rd, cond) \ + ARM_MRS_COND(p, rd, ARM_SPSR, cond) + +#define ARM_MRS_SPSR(p, rd) \ + ARM_MRS_SPSR_COND(p, rd, ARMCOND_AL) + + +#include "arm_dpimacros.h" + +#define ARM_NOP(p) ARM_MOV_REG_REG(p, ARMREG_R0, ARMREG_R0) + + +#define ARM_SHL_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond) +#define ARM_SHL_IMM(p, rd, rm, imm) \ + ARM_SHL_IMM_COND(p, rd, rm, imm, ARMCOND_AL) +#define ARM_SHLS_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond) +#define ARM_SHLS_IMM(p, rd, rm, imm) \ + ARM_SHLS_IMM_COND(p, rd, rm, imm, ARMCOND_AL) + +#define ARM_SHR_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond) +#define ARM_SHR_IMM(p, rd, rm, imm) \ + ARM_SHR_IMM_COND(p, rd, rm, imm, ARMCOND_AL) +#define ARM_SHRS_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond) +#define ARM_SHRS_IMM(p, rd, rm, imm) \ + ARM_SHRS_IMM_COND(p, rd, rm, imm, ARMCOND_AL) + +#define ARM_SAR_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond) +#define ARM_SAR_IMM(p, rd, rm, imm) \ + ARM_SAR_IMM_COND(p, rd, rm, imm, ARMCOND_AL) +#define ARM_SARS_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond) +#define ARM_SARS_IMM(p, rd, rm, imm) \ + ARM_SARS_IMM_COND(p, rd, rm, imm, ARMCOND_AL) + +#define ARM_ROR_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond) +#define ARM_ROR_IMM(p, rd, rm, imm) \ + ARM_ROR_IMM_COND(p, rd, rm, imm, ARMCOND_AL) +#define ARM_RORS_IMM_COND(p, rd, rm, imm, cond) \ + ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond) +#define ARM_RORS_IMM(p, rd, rm, imm) \ + ARM_RORS_IMM_COND(p, rd, rm, imm, ARMCOND_AL) + +#define ARM_SHL_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond) +#define ARM_SHL_REG(p, rd, rm, rs) \ + ARM_SHL_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SHLS_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond) +#define ARM_SHLS_REG(p, rd, rm, rs) \ + ARM_SHLS_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SHLS_REG_REG(p, rd, rm, rs) ARM_SHLS_REG(p, rd, rm, rs) + +#define ARM_SHR_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond) +#define ARM_SHR_REG(p, rd, rm, rs) \ + ARM_SHR_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SHRS_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond) +#define ARM_SHRS_REG(p, rd, rm, rs) \ + ARM_SHRS_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SHRS_REG_REG(p, rd, rm, rs) ARM_SHRS_REG(p, rd, rm, rs) + +#define ARM_SAR_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond) +#define ARM_SAR_REG(p, rd, rm, rs) \ + ARM_SAR_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SARS_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond) +#define ARM_SARS_REG(p, rd, rm, rs) \ + ARM_SARS_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_SARS_REG_REG(p, rd, rm, rs) ARM_SARS_REG(p, rd, rm, rs) + +#define ARM_ROR_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond) +#define ARM_ROR_REG(p, rd, rm, rs) \ + ARM_ROR_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_RORS_REG_COND(p, rd, rm, rs, cond) \ + ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond) +#define ARM_RORS_REG(p, rd, rm, rs) \ + ARM_RORS_REG_COND(p, rd, rm, rs, ARMCOND_AL) +#define ARM_RORS_REG_REG(p, rd, rm, rs) ARM_RORS_REG(p, rd, rm, rs) + +#define ARM_DBRK(p) ARM_EMIT(p, 0xE6000010) +#define ARM_IASM_DBRK() ARM_IASM_EMIT(0xE6000010) + +#define ARM_INC(p, reg) ARM_ADD_REG_IMM8(p, reg, reg, 1) +#define ARM_DEC(p, reg) ARM_SUB_REG_IMM8(p, reg, reg, 1) + + +/* ARM V5 */ + +/* Count leading zeros, CLZ{cond} Rd, Rm */ +typedef struct { + arminstr_t rm : 4; + arminstr_t tag2 : 8; + arminstr_t rd : 4; + arminstr_t tag : 12; + arminstr_t cond : 4; +} ARMInstrCLZ; + +#define ARM_CLZ_ID 0x16F +#define ARM_CLZ_ID2 0xF1 +#define ARM_CLZ_MASK ((0xFFF << 16) | (0xFF < 4)) +#define ARM_CLZ_TAG ((ARM_CLZ_ID << 16) | (ARM_CLZ_ID2 << 4)) + +#define ARM_DEF_CLZ_COND(rd, rm, cond) \ + ARM_CLZ_TAG | \ + ARM_DEF_COND(cond) | \ + (((rm) & 0xf)) | \ + ((rd) & 0xf) << 12 + +#define ARM_CLZ_COND(p, rd, rm, cond) \ + ARM_EMIT(p, ARM_DEF_CLZ_COND(rd, rm, cond)) + +#define ARM_CLZ(p, rd, rm) \ + ARM_EMIT(p, ARM_DEF_CLZ_COND(rd, rm, ARMCOND_AL)) + +/* + * TAG p b wb ls + * ARMCOND_NV | 0-1-0 | 0 | +/- | 1 | 0 | 1 | rn -|- 0xF | imm12 + */ +#define ARM_PLD_ID 0xF45 +#define ARM_PLD_ID2 0xF /* rd */ +#define ARM_PLD_MASK ((0xFC7 << 20) | (0xF << 12)) +#define ARM_PLD_TAG ((ARM_PLD_ID << 20) | (ARM_PLD_ID2 << 12)) +#define ARM_DEF_PLD_IMM(imm12, rn) \ + ((((int)imm12) < 0) ? -(int)(imm12) : (imm12)) | \ + ((0xF) << 12) | \ + ((rn) << 16) | \ + ((1) << 20) /* ls = load(1) */ | \ + ((0) << 21) /* wb = 0 */ | \ + ((1) << 22) /* b = 1 */ | \ + (((int)(imm12) >= 0) << 23) | \ + ((1) << 24) /* pre/post = pre(1) */ | \ + ((2) << 25) /* tag */ | \ + ARM_DEF_COND(ARMCOND_NV) + +#define ARM_PLD_IMM(p, rn, imm12) ARM_EMIT(p, ARM_DEF_PLD_IMM(imm12, rn)) + +#define ARM_DEF_PLD_REG_REG_UPDOWN_SHIFT(rn, shift_type, shift, rm, u) \ + (rm) | \ + ((shift_type) << 5) | \ + ((shift) << 7) | \ + (0xF << 12) /* rd = 0xF */ | \ + ((rn) << 16) | \ + (1 << 20) /* ls = load(1) */ | \ + (0 << 21) /* wb = 0 */ | \ + (1 << 22) /* b = 1 */ | \ + ((u) << 23) | \ + (1 << 24) /* pre(1) */ | \ + (3 << 25) | \ + ARM_DEF_COND(ARMCOND_NV) + +#define ARM_PLD_REG_REG_UPDOWN_SHIFT(p, rm, rn, u, shift_type, shift) \ + ARM_EMIT(p, ARM_DEF_PLD_REG_REG_UPDOWN_SHIFT(rm, shift_type, shift, rn, u)) + +#define ARM_PLD_REG_PLUS_REG(p, rm, rn) \ + ARM_PLD_REG_REG_UPDOWN_SHIFT(p, rm, rn, ARM_UP, ARMSHIFT_LSL, 0) + +#define ARM_PLD_REG_MINUS_REG(p, rm, rn) \ + ARM_PLD_REG_REG_UPDOWN_SHIFT(p, rm, rn, ARM_DOWN, ARMSHIFT_LSL, 0) + + +#define ARM_DEF_STF_IMM_COND(p, prec, freg_const, rd, imm8, rot, cond) \ + ((imm8) & 0xFF) | \ + (((rot) & 0xF) << 8) | \ + ((freg_const) << 12) | \ + (1 << 25) | \ + ARM_DEF_COND(cond) + + +typedef union { + ARMInstrBR br; + ARMInstrDPI dpi; + ARMInstrMRT mrt; + ARMInstrMul mul; + ARMInstrWXfer wxfer; + ARMInstrHXfer hxfer; + ARMInstrSwap swp; + ARMInstrCDP cdp; + ARMInstrCDT cdt; + ARMInstrCRT crt; + ARMInstrSWI swi; + ARMInstrMSR msr; + ARMInstrMRS mrs; + ARMInstrCLZ clz; + + ARMInstrGeneric generic; + arminstr_t raw; +} ARMInstr; + +#endif /* ARM_CG_H */ + diff --git a/gp2x/arm_dpimacros.h b/gp2x/arm_dpimacros.h new file mode 100644 index 0000000..743d5a5 --- /dev/null +++ b/gp2x/arm_dpimacros.h @@ -0,0 +1,1661 @@ +/* Macros for DPI ops, auto-generated from template + * + * Copyright (c) 2002 Wild West Software + * Copyright (c) 2001, 2002 Sergey Chaban + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +/* mov/mvn */ + +/* Rd := imm8 ROR rot */ +#define ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond) +#define ARM_MOV_REG_IMM(p, reg, imm8, rot) \ + ARM_MOV_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL) +/* S */ +#define ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, rot, cond) +#define ARM_MOVS_REG_IMM(p, reg, imm8, rot) \ + ARM_MOVS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MOV_REG_IMM_COND(reg, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond) +#define _MOV_REG_IMM(reg, imm8, rot) \ + _MOV_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL) +/* S */ +#define _MOVS_REG_IMM_COND(reg, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, rot, cond) +#define _MOVS_REG_IMM(reg, imm8, rot) \ + _MOVS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := imm8 */ +#define ARM_MOV_REG_IMM8_COND(p, reg, imm8, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond) +#define ARM_MOV_REG_IMM8(p, reg, imm8) \ + ARM_MOV_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL) +/* S */ +#define ARM_MOVS_REG_IMM8_COND(p, reg, imm8, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MOV, reg, 0, imm8, 0, cond) +#define ARM_MOVS_REG_IMM8(p, reg, imm8) \ + ARM_MOVS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MOV_REG_IMM8_COND(reg, imm8, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond) +#define _MOV_REG_IMM8(reg, imm8) \ + _MOV_REG_IMM8_COND(reg, imm8, ARMCOND_AL) +/* S */ +#define _MOVS_REG_IMM8_COND(reg, imm8, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MOV, reg, 0, imm8, 0, cond) +#define _MOVS_REG_IMM8(reg, imm8) \ + _MOVS_REG_IMM8_COND(reg, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rm */ +#define ARM_MOV_REG_REG_COND(p, rd, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond) +#define ARM_MOV_REG_REG(p, rd, rm) \ + ARM_MOV_REG_REG_COND(p, rd, rm, ARMCOND_AL) +/* S */ +#define ARM_MOVS_REG_REG_COND(p, rd, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MOV, rd, 0, rm, cond) +#define ARM_MOVS_REG_REG(p, rd, rm) \ + ARM_MOVS_REG_REG_COND(p, rd, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MOV_REG_REG_COND(rd, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond) +#define _MOV_REG_REG(rd, rm) \ + _MOV_REG_REG_COND(rd, rm, ARMCOND_AL) +/* S */ +#define _MOVS_REG_REG_COND(rd, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MOV, rd, 0, rm, cond) +#define _MOVS_REG_REG(rd, rm) \ + _MOVS_REG_REG_COND(rd, rm, ARMCOND_AL) +#endif + + +/* Rd := Rm imm_shift */ +#define ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond) +#define ARM_MOV_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \ + ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL) +/* S */ +#define ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond) +#define ARM_MOVS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \ + ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond) +#define _MOV_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \ + _MOV_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL) +/* S */ +#define _MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, imm_shift, cond) +#define _MOVS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \ + _MOVS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + + +/* Rd := (Rm Rs) */ +#define ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond) +#define ARM_MOV_REG_REGSHIFT(p, rd, rm, shift_type, rs) \ + ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL) +/* S */ +#define ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MOV, rd, 0, rm, shift_type, rs, cond) +#define ARM_MOVS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \ + ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond) +#define _MOV_REG_REGSHIFT(rd, rm, shift_type, rs) \ + _MOV_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL) +/* S */ +#define _MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MOV, rd, 0, rm, shift_type, rs, cond) +#define _MOVS_REG_REGSHIFT(rd, rm, shift_type, rs) \ + _MOVS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* Rd := imm8 ROR rot */ +#define ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond) +#define ARM_MVN_REG_IMM(p, reg, imm8, rot) \ + ARM_MVN_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL) +/* S */ +#define ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, rot, cond) +#define ARM_MVNS_REG_IMM(p, reg, imm8, rot) \ + ARM_MVNS_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MVN_REG_IMM_COND(reg, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond) +#define _MVN_REG_IMM(reg, imm8, rot) \ + _MVN_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL) +/* S */ +#define _MVNS_REG_IMM_COND(reg, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, rot, cond) +#define _MVNS_REG_IMM(reg, imm8, rot) \ + _MVNS_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := imm8 */ +#define ARM_MVN_REG_IMM8_COND(p, reg, imm8, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond) +#define ARM_MVN_REG_IMM8(p, reg, imm8) \ + ARM_MVN_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL) +/* S */ +#define ARM_MVNS_REG_IMM8_COND(p, reg, imm8, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_MVN, reg, 0, imm8, 0, cond) +#define ARM_MVNS_REG_IMM8(p, reg, imm8) \ + ARM_MVNS_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MVN_REG_IMM8_COND(reg, imm8, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond) +#define _MVN_REG_IMM8(reg, imm8) \ + _MVN_REG_IMM8_COND(reg, imm8, ARMCOND_AL) +/* S */ +#define _MVNS_REG_IMM8_COND(reg, imm8, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_MVN, reg, 0, imm8, 0, cond) +#define _MVNS_REG_IMM8(reg, imm8) \ + _MVNS_REG_IMM8_COND(reg, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rm */ +#define ARM_MVN_REG_REG_COND(p, rd, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond) +#define ARM_MVN_REG_REG(p, rd, rm) \ + ARM_MVN_REG_REG_COND(p, rd, rm, ARMCOND_AL) +/* S */ +#define ARM_MVNS_REG_REG_COND(p, rd, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_MVN, rd, 0, rm, cond) +#define ARM_MVNS_REG_REG(p, rd, rm) \ + ARM_MVNS_REG_REG_COND(p, rd, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MVN_REG_REG_COND(rd, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond) +#define _MVN_REG_REG(rd, rm) \ + _MVN_REG_REG_COND(rd, rm, ARMCOND_AL) +/* S */ +#define _MVNS_REG_REG_COND(rd, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_MVN, rd, 0, rm, cond) +#define _MVNS_REG_REG(rd, rm) \ + _MVNS_REG_REG_COND(rd, rm, ARMCOND_AL) +#endif + + +/* Rd := Rm imm_shift */ +#define ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond) +#define ARM_MVN_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \ + ARM_MVN_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL) +/* S */ +#define ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond) +#define ARM_MVNS_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \ + ARM_MVNS_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond) +#define _MVN_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \ + _MVN_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL) +/* S */ +#define _MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, imm_shift, cond) +#define _MVNS_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \ + _MVNS_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + + +/* Rd := (Rm Rs) */ +#define ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond) +#define ARM_MVN_REG_REGSHIFT(p, rd, rm, shift_type, rs) \ + ARM_MVN_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL) +/* S */ +#define ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_MVN, rd, 0, rm, shift_type, rs, cond) +#define ARM_MVNS_REG_REGSHIFT(p, rd, rm, shift_type, rs) \ + ARM_MVNS_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond) +#define _MVN_REG_REGSHIFT(rd, rm, shift_type, rs) \ + _MVN_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL) +/* S */ +#define _MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_MVN, rd, 0, rm, shift_type, rs, cond) +#define _MVNS_REG_REGSHIFT(rd, rm, shift_type, rs) \ + _MVNS_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL) +#endif + + + +/* DPIs, arithmetic and logical */ + +/* -- AND -- */ + +/* Rd := Rn AND (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond) +#define ARM_AND_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_AND_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_AND, rd, rn, imm8, rot, cond) +#define ARM_ANDS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _AND_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond) +#define _AND_REG_IMM(rd, rn, imm8, rot) \ + _AND_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _ANDS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_AND, rd, rn, imm8, rot, cond) +#define _ANDS_REG_IMM(rd, rn, imm8, rot) \ + _ANDS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn AND imm8 */ +#define ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_AND_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_AND_REG_IMM8(p, rd, rn, imm8) \ + ARM_AND_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ANDS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ANDS_REG_IMM8(p, rd, rn, imm8) \ + ARM_ANDS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _AND_REG_IMM8_COND(rd, rn, imm8, cond) \ + _AND_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _AND_REG_IMM8(rd, rn, imm8) \ + _AND_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _ANDS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ANDS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ANDS_REG_IMM8(rd, rn, imm8) \ + _ANDS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn AND Rm */ +#define ARM_AND_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_AND, rd, rn, rm, cond) +#define ARM_AND_REG_REG(p, rd, rn, rm) \ + ARM_AND_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_ANDS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_AND, rd, rn, rm, cond) +#define ARM_ANDS_REG_REG(p, rd, rn, rm) \ + ARM_ANDS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _AND_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_AND, rd, rn, rm, cond) +#define _AND_REG_REG(rd, rn, rm) \ + _AND_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _ANDS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_AND, rd, rn, rm, cond) +#define _ANDS_REG_REG(rd, rn, rm) \ + _ANDS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn AND (Rm imm_shift) */ +#define ARM_AND_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_AND_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_AND_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_ANDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ANDS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ANDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _AND_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond) +#define _AND_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _AND_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _ANDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, imm_shift, cond) +#define _ANDS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ANDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn AND (Rm Rs) */ +#define ARM_AND_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, rs, cond) +#define ARM_AND_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_AND_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_ANDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_AND, rd, rn, rm, shift_type, rs, cond) +#define ARM_ANDS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ANDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _AND_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, rs, cond) +#define _AND_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _AND_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _ANDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_AND, rd, rn, rm, shift_type, rs, cond) +#define _ANDS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ANDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- EOR -- */ + +/* Rd := Rn EOR (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_EOR, rd, rn, imm8, rot, cond) +#define ARM_EOR_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_EOR, rd, rn, imm8, rot, cond) +#define ARM_EORS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _EOR_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_EOR, rd, rn, imm8, rot, cond) +#define _EOR_REG_IMM(rd, rn, imm8, rot) \ + _EOR_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _EORS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_EOR, rd, rn, imm8, rot, cond) +#define _EORS_REG_IMM(rd, rn, imm8, rot) \ + _EORS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn EOR imm8 */ +#define ARM_EOR_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_EOR_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_EOR_REG_IMM8(p, rd, rn, imm8) \ + ARM_EOR_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_EORS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_EORS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_EORS_REG_IMM8(p, rd, rn, imm8) \ + ARM_EORS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _EOR_REG_IMM8_COND(rd, rn, imm8, cond) \ + _EOR_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _EOR_REG_IMM8(rd, rn, imm8) \ + _EOR_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _EORS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _EORS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _EORS_REG_IMM8(rd, rn, imm8) \ + _EORS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn EOR Rm */ +#define ARM_EOR_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_EOR, rd, rn, rm, cond) +#define ARM_EOR_REG_REG(p, rd, rn, rm) \ + ARM_EOR_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_EORS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_EOR, rd, rn, rm, cond) +#define ARM_EORS_REG_REG(p, rd, rn, rm) \ + ARM_EORS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _EOR_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_EOR, rd, rn, rm, cond) +#define _EOR_REG_REG(rd, rn, rm) \ + _EOR_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _EORS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_EOR, rd, rn, rm, cond) +#define _EORS_REG_REG(rd, rn, rm) \ + _EORS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn EOR (Rm imm_shift) */ +#define ARM_EOR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_EOR_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_EOR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_EORS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_EORS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_EORS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _EOR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond) +#define _EOR_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _EOR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _EORS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, imm_shift, cond) +#define _EORS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _EORS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn EOR (Rm Rs) */ +#define ARM_EOR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, rs, cond) +#define ARM_EOR_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_EOR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_EORS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_EOR, rd, rn, rm, shift_type, rs, cond) +#define ARM_EORS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_EORS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _EOR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, rs, cond) +#define _EOR_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _EOR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _EORS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_EOR, rd, rn, rm, shift_type, rs, cond) +#define _EORS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _EORS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- SUB -- */ + +/* Rd := Rn SUB (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_SUB, rd, rn, imm8, rot, cond) +#define ARM_SUB_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_SUB, rd, rn, imm8, rot, cond) +#define ARM_SUBS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SUB_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_SUB, rd, rn, imm8, rot, cond) +#define _SUB_REG_IMM(rd, rn, imm8, rot) \ + _SUB_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _SUBS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_SUB, rd, rn, imm8, rot, cond) +#define _SUBS_REG_IMM(rd, rn, imm8, rot) \ + _SUBS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn SUB imm8 */ +#define ARM_SUB_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_SUB_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_SUB_REG_IMM8(p, rd, rn, imm8) \ + ARM_SUB_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_SUBS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_SUBS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_SUBS_REG_IMM8(p, rd, rn, imm8) \ + ARM_SUBS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SUB_REG_IMM8_COND(rd, rn, imm8, cond) \ + _SUB_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _SUB_REG_IMM8(rd, rn, imm8) \ + _SUB_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _SUBS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _SUBS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _SUBS_REG_IMM8(rd, rn, imm8) \ + _SUBS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn SUB Rm */ +#define ARM_SUB_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_SUB, rd, rn, rm, cond) +#define ARM_SUB_REG_REG(p, rd, rn, rm) \ + ARM_SUB_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_SUBS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_SUB, rd, rn, rm, cond) +#define ARM_SUBS_REG_REG(p, rd, rn, rm) \ + ARM_SUBS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SUB_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_SUB, rd, rn, rm, cond) +#define _SUB_REG_REG(rd, rn, rm) \ + _SUB_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _SUBS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_SUB, rd, rn, rm, cond) +#define _SUBS_REG_REG(rd, rn, rm) \ + _SUBS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn SUB (Rm imm_shift) */ +#define ARM_SUB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_SUB_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_SUB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_SUBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_SUBS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_SUBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SUB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond) +#define _SUB_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _SUB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _SUBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, imm_shift, cond) +#define _SUBS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _SUBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn SUB (Rm Rs) */ +#define ARM_SUB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, rs, cond) +#define ARM_SUB_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_SUB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_SUBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_SUB, rd, rn, rm, shift_type, rs, cond) +#define ARM_SUBS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_SUBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SUB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, rs, cond) +#define _SUB_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _SUB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _SUBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_SUB, rd, rn, rm, shift_type, rs, cond) +#define _SUBS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _SUBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- RSB -- */ + +/* Rd := Rn RSB (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_RSB, rd, rn, imm8, rot, cond) +#define ARM_RSB_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_RSB, rd, rn, imm8, rot, cond) +#define ARM_RSBS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSB_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_RSB, rd, rn, imm8, rot, cond) +#define _RSB_REG_IMM(rd, rn, imm8, rot) \ + _RSB_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _RSBS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_RSB, rd, rn, imm8, rot, cond) +#define _RSBS_REG_IMM(rd, rn, imm8, rot) \ + _RSBS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn RSB imm8 */ +#define ARM_RSB_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_RSB_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_RSB_REG_IMM8(p, rd, rn, imm8) \ + ARM_RSB_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_RSBS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_RSBS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_RSBS_REG_IMM8(p, rd, rn, imm8) \ + ARM_RSBS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSB_REG_IMM8_COND(rd, rn, imm8, cond) \ + _RSB_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _RSB_REG_IMM8(rd, rn, imm8) \ + _RSB_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _RSBS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _RSBS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _RSBS_REG_IMM8(rd, rn, imm8) \ + _RSBS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn RSB Rm */ +#define ARM_RSB_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_RSB, rd, rn, rm, cond) +#define ARM_RSB_REG_REG(p, rd, rn, rm) \ + ARM_RSB_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_RSBS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_RSB, rd, rn, rm, cond) +#define ARM_RSBS_REG_REG(p, rd, rn, rm) \ + ARM_RSBS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSB_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_RSB, rd, rn, rm, cond) +#define _RSB_REG_REG(rd, rn, rm) \ + _RSB_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _RSBS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_RSB, rd, rn, rm, cond) +#define _RSBS_REG_REG(rd, rn, rm) \ + _RSBS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn RSB (Rm imm_shift) */ +#define ARM_RSB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_RSB_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_RSB_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_RSBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_RSBS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_RSBS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond) +#define _RSB_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _RSB_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _RSBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, imm_shift, cond) +#define _RSBS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _RSBS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn RSB (Rm Rs) */ +#define ARM_RSB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, rs, cond) +#define ARM_RSB_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_RSB_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_RSBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_RSB, rd, rn, rm, shift_type, rs, cond) +#define ARM_RSBS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_RSBS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, rs, cond) +#define _RSB_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _RSB_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _RSBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_RSB, rd, rn, rm, shift_type, rs, cond) +#define _RSBS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _RSBS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- ADD -- */ + +/* Rd := Rn ADD (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ADD, rd, rn, imm8, rot, cond) +#define ARM_ADD_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ADD, rd, rn, imm8, rot, cond) +#define ARM_ADDS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADD_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ADD, rd, rn, imm8, rot, cond) +#define _ADD_REG_IMM(rd, rn, imm8, rot) \ + _ADD_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _ADDS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ADD, rd, rn, imm8, rot, cond) +#define _ADDS_REG_IMM(rd, rn, imm8, rot) \ + _ADDS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn ADD imm8 */ +#define ARM_ADD_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ADD_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ADD_REG_IMM8(p, rd, rn, imm8) \ + ARM_ADD_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_ADDS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ADDS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ADDS_REG_IMM8(p, rd, rn, imm8) \ + ARM_ADDS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADD_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ADD_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ADD_REG_IMM8(rd, rn, imm8) \ + _ADD_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _ADDS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ADDS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ADDS_REG_IMM8(rd, rn, imm8) \ + _ADDS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn ADD Rm */ +#define ARM_ADD_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_ADD, rd, rn, rm, cond) +#define ARM_ADD_REG_REG(p, rd, rn, rm) \ + ARM_ADD_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_ADDS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ADD, rd, rn, rm, cond) +#define ARM_ADDS_REG_REG(p, rd, rn, rm) \ + ARM_ADDS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADD_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ADD, rd, rn, rm, cond) +#define _ADD_REG_REG(rd, rn, rm) \ + _ADD_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _ADDS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ADD, rd, rn, rm, cond) +#define _ADDS_REG_REG(rd, rn, rm) \ + _ADDS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn ADD (Rm imm_shift) */ +#define ARM_ADD_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ADD_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ADD_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_ADDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ADDS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ADDS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADD_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond) +#define _ADD_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ADD_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _ADDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, imm_shift, cond) +#define _ADDS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ADDS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn ADD (Rm Rs) */ +#define ARM_ADD_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, rs, cond) +#define ARM_ADD_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ADD_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_ADDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ADD, rd, rn, rm, shift_type, rs, cond) +#define ARM_ADDS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ADDS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADD_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, rs, cond) +#define _ADD_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ADD_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _ADDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ADD, rd, rn, rm, shift_type, rs, cond) +#define _ADDS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ADDS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- ADC -- */ + +/* Rd := Rn ADC (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ADC, rd, rn, imm8, rot, cond) +#define ARM_ADC_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ADC, rd, rn, imm8, rot, cond) +#define ARM_ADCS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADC_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ADC, rd, rn, imm8, rot, cond) +#define _ADC_REG_IMM(rd, rn, imm8, rot) \ + _ADC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _ADCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ADC, rd, rn, imm8, rot, cond) +#define _ADCS_REG_IMM(rd, rn, imm8, rot) \ + _ADCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn ADC imm8 */ +#define ARM_ADC_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ADC_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ADC_REG_IMM8(p, rd, rn, imm8) \ + ARM_ADC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_ADCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ADCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ADCS_REG_IMM8(p, rd, rn, imm8) \ + ARM_ADCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADC_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ADC_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ADC_REG_IMM8(rd, rn, imm8) \ + _ADC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _ADCS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ADCS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ADCS_REG_IMM8(rd, rn, imm8) \ + _ADCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn ADC Rm */ +#define ARM_ADC_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_ADC, rd, rn, rm, cond) +#define ARM_ADC_REG_REG(p, rd, rn, rm) \ + ARM_ADC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_ADCS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ADC, rd, rn, rm, cond) +#define ARM_ADCS_REG_REG(p, rd, rn, rm) \ + ARM_ADCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADC_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ADC, rd, rn, rm, cond) +#define _ADC_REG_REG(rd, rn, rm) \ + _ADC_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _ADCS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ADC, rd, rn, rm, cond) +#define _ADCS_REG_REG(rd, rn, rm) \ + _ADCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn ADC (Rm imm_shift) */ +#define ARM_ADC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ADC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ADC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_ADCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ADCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ADCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond) +#define _ADC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ADC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _ADCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, imm_shift, cond) +#define _ADCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ADCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn ADC (Rm Rs) */ +#define ARM_ADC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, rs, cond) +#define ARM_ADC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ADC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_ADCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ADC, rd, rn, rm, shift_type, rs, cond) +#define ARM_ADCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ADCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ADC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, rs, cond) +#define _ADC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ADC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _ADCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ADC, rd, rn, rm, shift_type, rs, cond) +#define _ADCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ADCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- SBC -- */ + +/* Rd := Rn SBC (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_SBC, rd, rn, imm8, rot, cond) +#define ARM_SBC_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_SBC, rd, rn, imm8, rot, cond) +#define ARM_SBCS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SBC_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_SBC, rd, rn, imm8, rot, cond) +#define _SBC_REG_IMM(rd, rn, imm8, rot) \ + _SBC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _SBCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_SBC, rd, rn, imm8, rot, cond) +#define _SBCS_REG_IMM(rd, rn, imm8, rot) \ + _SBCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn SBC imm8 */ +#define ARM_SBC_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_SBC_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_SBC_REG_IMM8(p, rd, rn, imm8) \ + ARM_SBC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_SBCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_SBCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_SBCS_REG_IMM8(p, rd, rn, imm8) \ + ARM_SBCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SBC_REG_IMM8_COND(rd, rn, imm8, cond) \ + _SBC_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _SBC_REG_IMM8(rd, rn, imm8) \ + _SBC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _SBCS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _SBCS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _SBCS_REG_IMM8(rd, rn, imm8) \ + _SBCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn SBC Rm */ +#define ARM_SBC_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_SBC, rd, rn, rm, cond) +#define ARM_SBC_REG_REG(p, rd, rn, rm) \ + ARM_SBC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_SBCS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_SBC, rd, rn, rm, cond) +#define ARM_SBCS_REG_REG(p, rd, rn, rm) \ + ARM_SBCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SBC_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_SBC, rd, rn, rm, cond) +#define _SBC_REG_REG(rd, rn, rm) \ + _SBC_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _SBCS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_SBC, rd, rn, rm, cond) +#define _SBCS_REG_REG(rd, rn, rm) \ + _SBCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn SBC (Rm imm_shift) */ +#define ARM_SBC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_SBC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_SBC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_SBCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_SBCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_SBCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SBC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond) +#define _SBC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _SBC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _SBCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, imm_shift, cond) +#define _SBCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _SBCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn SBC (Rm Rs) */ +#define ARM_SBC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, rs, cond) +#define ARM_SBC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_SBC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_SBCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_SBC, rd, rn, rm, shift_type, rs, cond) +#define ARM_SBCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_SBCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _SBC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, rs, cond) +#define _SBC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _SBC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _SBCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_SBC, rd, rn, rm, shift_type, rs, cond) +#define _SBCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _SBCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- RSC -- */ + +/* Rd := Rn RSC (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_RSC, rd, rn, imm8, rot, cond) +#define ARM_RSC_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_RSC, rd, rn, imm8, rot, cond) +#define ARM_RSCS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSC_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_RSC, rd, rn, imm8, rot, cond) +#define _RSC_REG_IMM(rd, rn, imm8, rot) \ + _RSC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _RSCS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_RSC, rd, rn, imm8, rot, cond) +#define _RSCS_REG_IMM(rd, rn, imm8, rot) \ + _RSCS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn RSC imm8 */ +#define ARM_RSC_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_RSC_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_RSC_REG_IMM8(p, rd, rn, imm8) \ + ARM_RSC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_RSCS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_RSCS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_RSCS_REG_IMM8(p, rd, rn, imm8) \ + ARM_RSCS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSC_REG_IMM8_COND(rd, rn, imm8, cond) \ + _RSC_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _RSC_REG_IMM8(rd, rn, imm8) \ + _RSC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _RSCS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _RSCS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _RSCS_REG_IMM8(rd, rn, imm8) \ + _RSCS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn RSC Rm */ +#define ARM_RSC_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_RSC, rd, rn, rm, cond) +#define ARM_RSC_REG_REG(p, rd, rn, rm) \ + ARM_RSC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_RSCS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_RSC, rd, rn, rm, cond) +#define ARM_RSCS_REG_REG(p, rd, rn, rm) \ + ARM_RSCS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSC_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_RSC, rd, rn, rm, cond) +#define _RSC_REG_REG(rd, rn, rm) \ + _RSC_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _RSCS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_RSC, rd, rn, rm, cond) +#define _RSCS_REG_REG(rd, rn, rm) \ + _RSCS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn RSC (Rm imm_shift) */ +#define ARM_RSC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_RSC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_RSC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_RSCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_RSCS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_RSCS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond) +#define _RSC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _RSC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _RSCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, imm_shift, cond) +#define _RSCS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _RSCS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn RSC (Rm Rs) */ +#define ARM_RSC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, rs, cond) +#define ARM_RSC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_RSC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_RSCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_RSC, rd, rn, rm, shift_type, rs, cond) +#define ARM_RSCS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_RSCS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _RSC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, rs, cond) +#define _RSC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _RSC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _RSCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_RSC, rd, rn, rm, shift_type, rs, cond) +#define _RSCS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _RSCS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- ORR -- */ + +/* Rd := Rn ORR (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_ORR, rd, rn, imm8, rot, cond) +#define ARM_ORR_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_ORR, rd, rn, imm8, rot, cond) +#define ARM_ORRS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ORR_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_ORR, rd, rn, imm8, rot, cond) +#define _ORR_REG_IMM(rd, rn, imm8, rot) \ + _ORR_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _ORRS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_ORR, rd, rn, imm8, rot, cond) +#define _ORRS_REG_IMM(rd, rn, imm8, rot) \ + _ORRS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn ORR imm8 */ +#define ARM_ORR_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ORR_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ORR_REG_IMM8(p, rd, rn, imm8) \ + ARM_ORR_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_ORRS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_ORRS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_ORRS_REG_IMM8(p, rd, rn, imm8) \ + ARM_ORRS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ORR_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ORR_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ORR_REG_IMM8(rd, rn, imm8) \ + _ORR_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _ORRS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _ORRS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _ORRS_REG_IMM8(rd, rn, imm8) \ + _ORRS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn ORR Rm */ +#define ARM_ORR_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_ORR, rd, rn, rm, cond) +#define ARM_ORR_REG_REG(p, rd, rn, rm) \ + ARM_ORR_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_ORRS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_ORR, rd, rn, rm, cond) +#define ARM_ORRS_REG_REG(p, rd, rn, rm) \ + ARM_ORRS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ORR_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_ORR, rd, rn, rm, cond) +#define _ORR_REG_REG(rd, rn, rm) \ + _ORR_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _ORRS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_ORR, rd, rn, rm, cond) +#define _ORRS_REG_REG(rd, rn, rm) \ + _ORRS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn ORR (Rm imm_shift) */ +#define ARM_ORR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ORR_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ORR_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_ORRS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_ORRS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_ORRS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ORR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond) +#define _ORR_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ORR_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _ORRS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, imm_shift, cond) +#define _ORRS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _ORRS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn ORR (Rm Rs) */ +#define ARM_ORR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, rs, cond) +#define ARM_ORR_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ORR_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_ORRS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_ORR, rd, rn, rm, shift_type, rs, cond) +#define ARM_ORRS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_ORRS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _ORR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, rs, cond) +#define _ORR_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ORR_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _ORRS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_ORR, rd, rn, rm, shift_type, rs, cond) +#define _ORRS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _ORRS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* -- BIC -- */ + +/* Rd := Rn BIC (imm8 ROR rot) ; rot is power of 2 */ +#define ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_BIC, rd, rn, imm8, rot, cond) +#define ARM_BIC_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) +#define ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_BIC, rd, rn, imm8, rot, cond) +#define ARM_BICS_REG_IMM(p, rd, rn, imm8, rot) \ + ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _BIC_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_BIC, rd, rn, imm8, rot, cond) +#define _BIC_REG_IMM(rd, rn, imm8, rot) \ + _BIC_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#define _BICS_REG_IMM_COND(rd, rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_BIC, rd, rn, imm8, rot, cond) +#define _BICS_REG_IMM(rd, rn, imm8, rot) \ + _BICS_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL) +#endif + + +/* Rd := Rn BIC imm8 */ +#define ARM_BIC_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_BIC_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_BIC_REG_IMM8(p, rd, rn, imm8) \ + ARM_BIC_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) +#define ARM_BICS_REG_IMM8_COND(p, rd, rn, imm8, cond) \ + ARM_BICS_REG_IMM_COND(p, rd, rn, imm8, 0, cond) +#define ARM_BICS_REG_IMM8(p, rd, rn, imm8) \ + ARM_BICS_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _BIC_REG_IMM8_COND(rd, rn, imm8, cond) \ + _BIC_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _BIC_REG_IMM8(rd, rn, imm8) \ + _BIC_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#define _BICS_REG_IMM8_COND(rd, rn, imm8, cond) \ + _BICS_REG_IMM_COND(rd, rn, imm8, 0, cond) +#define _BICS_REG_IMM8(rd, rn, imm8) \ + _BICS_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL) +#endif + + +/* Rd := Rn BIC Rm */ +#define ARM_BIC_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_REG_REG_COND(p, ARMOP_BIC, rd, rn, rm, cond) +#define ARM_BIC_REG_REG(p, rd, rn, rm) \ + ARM_BIC_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) +#define ARM_BICS_REG_REG_COND(p, rd, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_BIC, rd, rn, rm, cond) +#define ARM_BICS_REG_REG(p, rd, rn, rm) \ + ARM_BICS_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _BIC_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_REG_REG_COND(ARMOP_BIC, rd, rn, rm, cond) +#define _BIC_REG_REG(rd, rn, rm) \ + _BIC_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#define _BICS_REG_REG_COND(rd, rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_BIC, rd, rn, rm, cond) +#define _BICS_REG_REG(rd, rn, rm) \ + _BICS_REG_REG_COND(rd, rn, rm, ARMCOND_AL) +#endif + + +/* Rd := Rn BIC (Rm imm_shift) */ +#define ARM_BIC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_BIC_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_BIC_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define ARM_BICS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond) +#define ARM_BICS_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \ + ARM_BICS_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _BIC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond) +#define _BIC_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _BIC_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#define _BICS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, imm_shift, cond) +#define _BICS_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \ + _BICS_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* Rd := Rn BIC (Rm Rs) */ +#define ARM_BIC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, rs, cond) +#define ARM_BIC_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_BIC_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define ARM_BICS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \ + ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_BIC, rd, rn, rm, shift_type, rs, cond) +#define ARM_BICS_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \ + ARM_BICS_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _BIC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, rs, cond) +#define _BIC_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _BIC_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#define _BICS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ + ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_BIC, rd, rn, rm, shift_type, rs, cond) +#define _BICS_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ + _BICS_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + + + + + +/* DPIs, comparison */ + +/* PSR := TST Rn, (imm8 ROR 2*rot) */ +#define ARM_TST_REG_IMM_COND(p, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_TST, 0, rn, imm8, rot, cond) +#define ARM_TST_REG_IMM(p, rn, imm8, rot) \ + ARM_TST_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TST_REG_IMM_COND(rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_TST, 0, rn, imm8, rot, cond) +#define _TST_REG_IMM(rn, imm8, rot) \ + _TST_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL) +#endif + + +/* PSR := TST Rn, imm8 */ +#define ARM_TST_REG_IMM8_COND(p, rn, imm8, cond) \ + ARM_TST_REG_IMM_COND(p, rn, imm8, 0, cond) +#define ARM_TST_REG_IMM8(p, rn, imm8) \ + ARM_TST_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TST_REG_IMM8_COND(rn, imm8, cond) \ + _TST_REG_IMM_COND(rn, imm8, 0, cond) +#define _TST_REG_IMM8(rn, imm8) \ + _TST_REG_IMM8_COND(rn, imm8, ARMCOND_AL) +#endif + + +/* PSR := TST Rn, Rm */ +#define ARM_TST_REG_REG_COND(p, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_TST, 0, rn, rm, cond) +#define ARM_TST_REG_REG(p, rn, rm) \ + ARM_TST_REG_REG_COND(p, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TST_REG_REG_COND(rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_TST, 0, rn, rm, cond) +#define _TST_REG_REG(rn, rm) \ + _TST_REG_REG_COND(rn, rm, ARMCOND_AL) +#endif + + +/* PSR := TST Rn, (Rm imm8) */ +#define ARM_TST_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_TST, 0, rn, rm, shift_type, imm_shift, cond) +#define ARM_TST_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \ + ARM_TST_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TST_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_TST, 0, rn, rm, shift_type, imm_shift, cond) +#define _TST_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \ + _TST_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* PSR := TEQ Rn, (imm8 ROR 2*rot) */ +#define ARM_TEQ_REG_IMM_COND(p, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_TEQ, 0, rn, imm8, rot, cond) +#define ARM_TEQ_REG_IMM(p, rn, imm8, rot) \ + ARM_TEQ_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TEQ_REG_IMM_COND(rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_TEQ, 0, rn, imm8, rot, cond) +#define _TEQ_REG_IMM(rn, imm8, rot) \ + _TEQ_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL) +#endif + + +/* PSR := TEQ Rn, imm8 */ +#define ARM_TEQ_REG_IMM8_COND(p, rn, imm8, cond) \ + ARM_TEQ_REG_IMM_COND(p, rn, imm8, 0, cond) +#define ARM_TEQ_REG_IMM8(p, rn, imm8) \ + ARM_TEQ_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TEQ_REG_IMM8_COND(rn, imm8, cond) \ + _TEQ_REG_IMM_COND(rn, imm8, 0, cond) +#define _TEQ_REG_IMM8(rn, imm8) \ + _TEQ_REG_IMM8_COND(rn, imm8, ARMCOND_AL) +#endif + + +/* PSR := TEQ Rn, Rm */ +#define ARM_TEQ_REG_REG_COND(p, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_TEQ, 0, rn, rm, cond) +#define ARM_TEQ_REG_REG(p, rn, rm) \ + ARM_TEQ_REG_REG_COND(p, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TEQ_REG_REG_COND(rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_TEQ, 0, rn, rm, cond) +#define _TEQ_REG_REG(rn, rm) \ + _TEQ_REG_REG_COND(rn, rm, ARMCOND_AL) +#endif + + +/* PSR := TEQ Rn, (Rm imm8) */ +#define ARM_TEQ_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_TEQ, 0, rn, rm, shift_type, imm_shift, cond) +#define ARM_TEQ_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \ + ARM_TEQ_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _TEQ_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_TEQ, 0, rn, rm, shift_type, imm_shift, cond) +#define _TEQ_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \ + _TEQ_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* PSR := CMP Rn, (imm8 ROR 2*rot) */ +#define ARM_CMP_REG_IMM_COND(p, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_CMP, 0, rn, imm8, rot, cond) +#define ARM_CMP_REG_IMM(p, rn, imm8, rot) \ + ARM_CMP_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMP_REG_IMM_COND(rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_CMP, 0, rn, imm8, rot, cond) +#define _CMP_REG_IMM(rn, imm8, rot) \ + _CMP_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL) +#endif + + +/* PSR := CMP Rn, imm8 */ +#define ARM_CMP_REG_IMM8_COND(p, rn, imm8, cond) \ + ARM_CMP_REG_IMM_COND(p, rn, imm8, 0, cond) +#define ARM_CMP_REG_IMM8(p, rn, imm8) \ + ARM_CMP_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMP_REG_IMM8_COND(rn, imm8, cond) \ + _CMP_REG_IMM_COND(rn, imm8, 0, cond) +#define _CMP_REG_IMM8(rn, imm8) \ + _CMP_REG_IMM8_COND(rn, imm8, ARMCOND_AL) +#endif + + +/* PSR := CMP Rn, Rm */ +#define ARM_CMP_REG_REG_COND(p, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_CMP, 0, rn, rm, cond) +#define ARM_CMP_REG_REG(p, rn, rm) \ + ARM_CMP_REG_REG_COND(p, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMP_REG_REG_COND(rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_CMP, 0, rn, rm, cond) +#define _CMP_REG_REG(rn, rm) \ + _CMP_REG_REG_COND(rn, rm, ARMCOND_AL) +#endif + + +/* PSR := CMP Rn, (Rm imm8) */ +#define ARM_CMP_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_CMP, 0, rn, rm, shift_type, imm_shift, cond) +#define ARM_CMP_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \ + ARM_CMP_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMP_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_CMP, 0, rn, rm, shift_type, imm_shift, cond) +#define _CMP_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \ + _CMP_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + +/* PSR := CMP Rn, (Rm Rs) */ +#define ARM_CMP_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, cond) \ +ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_CMP, 0, rn, rm, shift_type, rs, cond) +#define ARM_CMP_REG_REGSHIFT(p, rn, rm, shift_type, rs) \ +ARM_CMP_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, ARMCOND_AL) + +/* PSR := CMN Rn, (Rm Rs) */ +#define ARM_CMN_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, cond) \ +ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_CMN, 0, rn, rm, shift_type, rs, cond) +#define ARM_CMN_REG_REGSHIFT(p, rn, rm, shift_type, rs) \ +ARM_CMN_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, ARMCOND_AL) + +/* PSR := TST Rn, (Rm Rs) */ +#define ARM_TST_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, cond) \ +ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_TST, 0, rn, rm, shift_type, rs, cond) +#define ARM_TST_REG_REGSHIFT(p, rn, rm, shift_type, rs) \ +ARM_CMN_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, ARMCOND_AL) + +/* PSR := TEQ Rn, (Rm Rs) */ +#define ARM_TEQ_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, cond) \ +ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_TEQ, 0, rn, rm, shift_type, rs, cond) +#define ARM_TEQ_REG_REGSHIFT(p, rn, rm, shift_type, rs) \ +ARM_CMN_REG_REGSHIFT_COND(p, rn, rm, shift_type, rs, ARMCOND_AL) + + + +#ifndef ARM_NOIASM +#define _CMP_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \ +ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_CMP, rd, rn, rm, shift_type, rs, cond) +#define _CMP_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \ +_CMP_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL) +#endif + + +/* PSR := CMN Rn, (imm8 ROR 2*rot) */ +#define ARM_CMN_REG_IMM_COND(p, rn, imm8, rot, cond) \ + ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_CMN, 0, rn, imm8, rot, cond) +#define ARM_CMN_REG_IMM(p, rn, imm8, rot) \ + ARM_CMN_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMN_REG_IMM_COND(rn, imm8, rot, cond) \ + ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_CMN, 0, rn, imm8, rot, cond) +#define _CMN_REG_IMM(rn, imm8, rot) \ + _CMN_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL) +#endif + + +/* PSR := CMN Rn, imm8 */ +#define ARM_CMN_REG_IMM8_COND(p, rn, imm8, cond) \ + ARM_CMN_REG_IMM_COND(p, rn, imm8, 0, cond) +#define ARM_CMN_REG_IMM8(p, rn, imm8) \ + ARM_CMN_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMN_REG_IMM8_COND(rn, imm8, cond) \ + _CMN_REG_IMM_COND(rn, imm8, 0, cond) +#define _CMN_REG_IMM8(rn, imm8) \ + _CMN_REG_IMM8_COND(rn, imm8, ARMCOND_AL) +#endif + + +/* PSR := CMN Rn, Rm */ +#define ARM_CMN_REG_REG_COND(p, rn, rm, cond) \ + ARM_DPIOP_S_REG_REG_COND(p, ARMOP_CMN, 0, rn, rm, cond) +#define ARM_CMN_REG_REG(p, rn, rm) \ + ARM_CMN_REG_REG_COND(p, rn, rm, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMN_REG_REG_COND(rn, rm, cond) \ + ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_CMN, 0, rn, rm, cond) +#define _CMN_REG_REG(rn, rm) \ + _CMN_REG_REG_COND(rn, rm, ARMCOND_AL) +#endif + + +/* PSR := CMN Rn, (Rm imm8) */ +#define ARM_CMN_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \ + ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_CMN, 0, rn, rm, shift_type, imm_shift, cond) +#define ARM_CMN_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \ + ARM_CMN_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL) + +#ifndef ARM_NOIASM +#define _CMN_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \ + ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_CMN, 0, rn, rm, shift_type, imm_shift, cond) +#define _CMN_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \ + _CMN_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL) +#endif + + + +/* end generated */ + diff --git a/gp2x/arm_emit.h b/gp2x/arm_emit.h new file mode 100644 index 0000000..1d8040f --- /dev/null +++ b/gp2x/arm_emit.h @@ -0,0 +1,1952 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ARM_EMIT_H +#define ARM_EMIT_H + +#include "arm_codegen.h" + +u32 arm_update_gba_arm(u32 pc); +u32 arm_update_gba_thumb(u32 pc); +u32 arm_update_gba_idle_arm(u32 pc); +u32 arm_update_gba_idle_thumb(u32 pc); + +// Although these are defined as a function, don't call them as +// such (jump to it instead) +void arm_indirect_branch_arm(u32 address); +void arm_indirect_branch_thumb(u32 address); +void arm_indirect_branch_dual_arm(u32 address); +void arm_indirect_branch_dual_thumb(u32 address); + +void execute_store_cpsr(u32 new_cpsr, u32 store_mask, u32 address); +u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address); +void execute_store_spsr(u32 new_cpsr, u32 store_mask); +u32 execute_read_spsr(); +u32 execute_spsr_restore(u32 address); + +void execute_swi_arm(u32 pc); +void execute_swi_thumb(u32 pc); + +void function_cc execute_store_u32_safe(u32 address, u32 source); + +void step_debug_arm(u32 pc); + + +#define write32(value) \ + *((u32 *)translation_ptr) = value; \ + translation_ptr += 4 \ + +#define arm_relative_offset(source, offset) \ + (((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF) \ + + +// reg_base_offset is the amount of bytes after reg_base where the registers +// actually begin. + +#define reg_base_offset 1024 + + +#define reg_a0 ARMREG_R0 +#define reg_a1 ARMREG_R1 +#define reg_a2 ARMREG_R2 + +#define reg_s0 ARMREG_R9 +#define reg_base ARMREG_SP +#define reg_flags ARMREG_R11 + +#define reg_cycles ARMREG_R12 + +#define reg_rv ARMREG_R0 + +#define reg_rm ARMREG_R0 +#define reg_rn ARMREG_R1 +#define reg_rs ARMREG_R14 +#define reg_rd ARMREG_R0 + + +// Register allocation layout for ARM and Thumb: +// Map from a GBA register to a host ARM register. -1 means load it +// from memory into one of the temp registers. + +// The following registers are chosen based on statistical analysis +// of a few games (see below), but might not be the best ones. Results +// vary tremendously between ARM and Thumb (for obvious reasons), so +// two sets are used. Take care to not call any function which can +// overwrite any of these registers from the dynarec - only call +// trusted functions in arm_stub.S which know how to save/restore +// them and know how to transfer them to the C functions it calls +// if necessary. + +// The following define the actual registers available for allocation. +// As registers are freed up add them to this list. + +// Note that r15 is linked to the a0 temp reg - this register will +// be preloaded with a constant upon read, and used to link to +// indirect branch functions upon write. + +#define reg_x0 ARMREG_R3 +#define reg_x1 ARMREG_R4 +#define reg_x2 ARMREG_R5 +#define reg_x3 ARMREG_R6 +#define reg_x4 ARMREG_R7 +#define reg_x5 ARMREG_R8 + +#define mem_reg -1 + +/* + +ARM register usage (38.775138% ARM instructions): +r00: 18.263814% (-- 18.263814%) +r12: 11.531477% (-- 29.795291%) +r09: 11.500162% (-- 41.295453%) +r14: 9.063440% (-- 50.358893%) +r06: 7.837682% (-- 58.196574%) +r01: 7.401049% (-- 65.597623%) +r07: 6.778340% (-- 72.375963%) +r05: 5.445009% (-- 77.820973%) +r02: 5.427288% (-- 83.248260%) +r03: 5.293743% (-- 88.542003%) +r04: 3.601103% (-- 92.143106%) +r11: 3.207311% (-- 95.350417%) +r10: 2.334864% (-- 97.685281%) +r08: 1.708207% (-- 99.393488%) +r15: 0.311270% (-- 99.704757%) +r13: 0.295243% (-- 100.000000%) + +Thumb register usage (61.224862% Thumb instructions): +r00: 34.788858% (-- 34.788858%) +r01: 26.564083% (-- 61.352941%) +r03: 10.983500% (-- 72.336441%) +r02: 8.303127% (-- 80.639567%) +r04: 4.900381% (-- 85.539948%) +r05: 3.941292% (-- 89.481240%) +r06: 3.257582% (-- 92.738822%) +r07: 2.644851% (-- 95.383673%) +r13: 1.408824% (-- 96.792497%) +r08: 0.906433% (-- 97.698930%) +r09: 0.679693% (-- 98.378623%) +r10: 0.656446% (-- 99.035069%) +r12: 0.453668% (-- 99.488737%) +r14: 0.248909% (-- 99.737646%) +r11: 0.171066% (-- 99.908713%) +r15: 0.091287% (-- 100.000000%) + +*/ + +s32 arm_register_allocation[] = +{ + reg_x0, // GBA r0 + reg_x1, // GBA r1 + mem_reg, // GBA r2 + mem_reg, // GBA r3 + mem_reg, // GBA r4 + mem_reg, // GBA r5 + reg_x2, // GBA r6 + mem_reg, // GBA r7 + mem_reg, // GBA r8 + reg_x3, // GBA r9 + mem_reg, // GBA r10 + mem_reg, // GBA r11 + reg_x4, // GBA r12 + mem_reg, // GBA r13 + reg_x5, // GBA r14 + reg_a0 // GBA r15 + + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, +}; + +s32 thumb_register_allocation[] = +{ + reg_x0, // GBA r0 + reg_x1, // GBA r1 + reg_x2, // GBA r2 + reg_x3, // GBA r3 + reg_x4, // GBA r4 + reg_x5, // GBA r5 + mem_reg, // GBA r6 + mem_reg, // GBA r7 + mem_reg, // GBA r8 + mem_reg, // GBA r9 + mem_reg, // GBA r10 + mem_reg, // GBA r11 + mem_reg, // GBA r12 + mem_reg, // GBA r13 + mem_reg, // GBA r14 + reg_a0 // GBA r15 + + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, + mem_reg, +}; + + + +#define arm_imm_lsl_to_rot(value) \ + (32 - value) \ + + +u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) +{ + u32 store_count = 0; + u32 left_shift = 0; + u32 i; + + // Otherwise it'll return 0 things to store because it'll never + // find anything. + if(imm == 0) + { + rotations[0] = 0; + stores[0] = 0; + return 1; + } + + // Find chunks of non-zero data at 2 bit alignments. + while(1) + { + for(; left_shift < 32; left_shift += 2) + { + if((imm >> left_shift) & 0x03) + break; + } + + if(left_shift == 32) + { + // We've hit the end of the useful data. + return store_count; + } + + // Hit the end, it might wrap back around to the beginning. + if(left_shift >= 24) + { + // Make a mask for the residual bits. IE, if we have + // 5 bits of data at the end we can wrap around to 3 + // bits of data in the beginning. Thus the first + // thing, after being shifted left, has to be less + // than 111b, 0x7, or (1 << 3) - 1. + u32 top_bits = 32 - left_shift; + u32 residual_bits = 8 - top_bits; + u32 residual_mask = (1 << residual_bits) - 1; + + if((store_count > 1) && (left_shift > 24) && + ((stores[0] << ((32 - rotations[0]) & 0x1F)) < residual_mask)) + { + // Then we can throw out the last bit and tack it on + // to the first bit. + u32 initial_bits = rotations[0]; + stores[0] = + (stores[0] << ((top_bits + (32 - rotations[0])) & 0x1F)) | + ((imm >> left_shift) & 0xFF); + rotations[0] = top_bits; + + return store_count; + } + else + { + // There's nothing to wrap over to in the beginning + stores[store_count] = (imm >> left_shift) & 0xFF; + rotations[store_count] = (32 - left_shift) & 0x1F; + return store_count + 1; + } + break; + } + + stores[store_count] = (imm >> left_shift) & 0xFF; + rotations[store_count] = (32 - left_shift) & 0x1F; + + store_count++; + left_shift += 8; + } +} + +#define arm_load_imm_32bit(ireg, imm) \ +{ \ + u32 stores[4]; \ + u32 rotations[4]; \ + u32 store_count = arm_disect_imm_32bit(imm, stores, rotations); \ + u32 i; \ + \ + ARM_MOV_REG_IMM(0, ireg, stores[0], rotations[0]); \ + \ + for(i = 1; i < store_count; i++) \ + { \ + ARM_ORR_REG_IMM(0, ireg, ireg, stores[i], rotations[i]); \ + } \ +} \ + + +#define generate_load_pc(ireg, new_pc) \ + arm_load_imm_32bit(ireg, new_pc) \ + +#define generate_load_imm(ireg, imm, imm_ror) \ + ARM_MOV_REG_IMM(0, ireg, imm, imm_ror) \ + + + +#define generate_shift_left(ireg, imm) \ + ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSL, imm) \ + +#define generate_shift_right(ireg, imm) \ + ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSR, imm) \ + +#define generate_shift_right_arithmetic(ireg, imm) \ + ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ASR, imm) \ + +#define generate_rotate_right(ireg, imm) \ + ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ROR, imm) \ + +#define generate_add(ireg_dest, ireg_src) \ + ARM_ADD_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \ + +#define generate_sub(ireg_dest, ireg_src) \ + ARM_SUB_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \ + +#define generate_or(ireg_dest, ireg_src) \ + ARM_ORR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \ + +#define generate_xor(ireg_dest, ireg_src) \ + ARM_EOR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \ + +#define generate_add_imm(ireg, imm, imm_ror) \ + ARM_ADD_REG_IMM(0, ireg, ireg, imm, imm_ror) \ + +#define generate_sub_imm(ireg, imm, imm_ror) \ + ARM_SUB_REG_IMM(0, ireg, ireg, imm, imm_ror) \ + +#define generate_xor_imm(ireg, imm, imm_ror) \ + ARM_EOR_REG_IMM(0, ireg, ireg, imm, imm_ror) \ + +#define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm, imm_ror) \ + ARM_ADD_REG_IMM(0, ireg_dest, ireg_src, imm, imm_ror) \ + +#define generate_and_imm(ireg, imm, imm_ror) \ + ARM_AND_REG_IMM(0, ireg, ireg, imm, imm_ror) \ + +#define generate_mov(ireg_dest, ireg_src) \ + if(ireg_dest != ireg_src) \ + { \ + ARM_MOV_REG_REG(0, ireg_dest, ireg_src); \ + } \ + +#define generate_function_call(function_location) \ + ARM_BL(0, arm_relative_offset(translation_ptr, function_location)) \ + +#define generate_exit_block() \ + ARM_BX(0, ARMREG_LR) \ + +// The branch target is to be filled in later (thus a 0 for now) + +#define generate_branch_filler(condition_code, writeback_location) \ + (writeback_location) = translation_ptr; \ + ARM_B_COND(0, condition_code, 0) \ + +#define generate_update_pc(new_pc) \ + generate_load_pc(reg_a0, new_pc) \ + +#define generate_cycle_update() \ + if(cycle_count) \ + { \ + if(cycle_count >> 8) \ + { \ + ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \ + arm_imm_lsl_to_rot(8)); \ + } \ + ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \ + cycle_count = 0; \ + } \ + +#define generate_cycle_update_flag_set() \ + if(cycle_count >> 8) \ + { \ + ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \ + arm_imm_lsl_to_rot(8)); \ + } \ + generate_save_flags(); \ + ARM_ADDS_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \ + cycle_count = 0 \ + +#define generate_branch_patch_conditional(dest, offset) \ + *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \ + arm_relative_offset(dest, offset) \ + +#define generate_branch_patch_unconditional(dest, offset) \ + *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \ + arm_relative_offset(dest, offset) \ + +// A different function is called for idle updates because of the relative +// location of the embedded PC. The idle version could be optimized to put +// the CPU into halt mode too, however. + +#define generate_branch_idle_eliminate(writeback_location, new_pc, mode) \ + generate_function_call(arm_update_gba_idle_##mode); \ + write32(new_pc); \ + generate_branch_filler(ARMCOND_AL, writeback_location) \ + +#define generate_branch_update(writeback_location, new_pc, mode) \ + ARM_MOV_REG_IMMSHIFT(0, reg_a0, reg_cycles, ARMSHIFT_LSR, 31); \ + ARM_ADD_REG_IMMSHIFT(0, ARMREG_PC, ARMREG_PC, reg_a0, ARMSHIFT_LSL, 2); \ + write32(new_pc); \ + generate_function_call(arm_update_gba_##mode); \ + generate_branch_filler(ARMCOND_AL, writeback_location) \ + + +#define generate_branch_no_cycle_update(writeback_location, new_pc, mode) \ + if(pc == idle_loop_target_pc) \ + { \ + generate_branch_idle_eliminate(writeback_location, new_pc, mode); \ + } \ + else \ + { \ + generate_branch_update(writeback_location, new_pc, mode); \ + } \ + +#define generate_branch_cycle_update(writeback_location, new_pc, mode) \ + generate_cycle_update(); \ + generate_branch_no_cycle_update(writeback_location, new_pc, mode) \ + +// a0 holds the destination + +#define generate_indirect_branch_no_cycle_update(type) \ + ARM_B(0, arm_relative_offset(translation_ptr, arm_indirect_branch_##type)) \ + +#define generate_indirect_branch_cycle_update(type) \ + generate_cycle_update(); \ + generate_indirect_branch_no_cycle_update(type) \ + +#define generate_block_prologue() \ + +#define generate_block_extra_vars_arm() \ + void generate_indirect_branch_arm() \ + { \ + if(condition == 0x0E) \ + { \ + generate_cycle_update(); \ + } \ + generate_indirect_branch_no_cycle_update(arm); \ + } \ + \ + void generate_indirect_branch_dual() \ + { \ + if(condition == 0x0E) \ + { \ + generate_cycle_update(); \ + } \ + generate_indirect_branch_no_cycle_update(dual_arm); \ + } \ + \ + u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \ + { \ + u32 reg_use = arm_register_allocation[reg_index]; \ + if(reg_use == mem_reg) \ + { \ + ARM_LDR_IMM(0, scratch_reg, reg_base, \ + (reg_base_offset + (reg_index * 4))); \ + return scratch_reg; \ + } \ + \ + return reg_use; \ + } \ + \ + u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \ + { \ + if(reg_index == 15) \ + { \ + generate_load_pc(scratch_reg, pc + pc_offset); \ + return scratch_reg; \ + } \ + return prepare_load_reg(scratch_reg, reg_index); \ + } \ + \ + u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \ + { \ + u32 reg_use = arm_register_allocation[reg_index]; \ + if(reg_use == mem_reg) \ + return scratch_reg; \ + \ + return reg_use; \ + } \ + \ + void complete_store_reg(u32 scratch_reg, u32 reg_index) \ + { \ + if(arm_register_allocation[reg_index] == mem_reg) \ + { \ + ARM_STR_IMM(0, scratch_reg, reg_base, \ + (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + \ + void complete_store_reg_pc_no_flags(u32 scratch_reg, u32 reg_index) \ + { \ + if(reg_index == 15) \ + { \ + generate_indirect_branch_arm(); \ + } \ + else \ + { \ + complete_store_reg(scratch_reg, reg_index); \ + } \ + } \ + \ + void complete_store_reg_pc_flags(u32 scratch_reg, u32 reg_index) \ + { \ + if(reg_index == 15) \ + { \ + if(condition == 0x0E) \ + { \ + generate_cycle_update(); \ + } \ + generate_function_call(execute_spsr_restore); \ + } \ + else \ + { \ + complete_store_reg(scratch_reg, reg_index); \ + } \ + } \ + \ + void generate_load_reg(u32 ireg, u32 reg_index) \ + { \ + s32 load_src = arm_register_allocation[reg_index]; \ + if(load_src != mem_reg) \ + { \ + ARM_MOV_REG_REG(0, ireg, load_src); \ + } \ + else \ + { \ + ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + \ + void generate_store_reg(u32 ireg, u32 reg_index) \ + { \ + s32 store_dest = arm_register_allocation[reg_index]; \ + if(store_dest != mem_reg) \ + { \ + ARM_MOV_REG_REG(0, store_dest, ireg); \ + } \ + else \ + { \ + ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + + +#define generate_block_extra_vars_thumb() \ + u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \ + { \ + u32 reg_use = thumb_register_allocation[reg_index]; \ + if(reg_use == mem_reg) \ + { \ + ARM_LDR_IMM(0, scratch_reg, reg_base, \ + (reg_base_offset + (reg_index * 4))); \ + return scratch_reg; \ + } \ + \ + return reg_use; \ + } \ + \ + u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \ + { \ + if(reg_index == 15) \ + { \ + generate_load_pc(scratch_reg, pc + pc_offset); \ + return scratch_reg; \ + } \ + return prepare_load_reg(scratch_reg, reg_index); \ + } \ + \ + u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \ + { \ + u32 reg_use = thumb_register_allocation[reg_index]; \ + if(reg_use == mem_reg) \ + return scratch_reg; \ + \ + return reg_use; \ + } \ + \ + void complete_store_reg(u32 scratch_reg, u32 reg_index) \ + { \ + if(thumb_register_allocation[reg_index] == mem_reg) \ + { \ + ARM_STR_IMM(0, scratch_reg, reg_base, \ + (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + \ + void generate_load_reg(u32 ireg, u32 reg_index) \ + { \ + s32 load_src = thumb_register_allocation[reg_index]; \ + if(load_src != mem_reg) \ + { \ + ARM_MOV_REG_REG(0, ireg, load_src); \ + } \ + else \ + { \ + ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + \ + void generate_store_reg(u32 ireg, u32 reg_index) \ + { \ + s32 store_dest = thumb_register_allocation[reg_index]; \ + if(store_dest != mem_reg) \ + { \ + ARM_MOV_REG_REG(0, store_dest, ireg); \ + } \ + else \ + { \ + ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + } \ + } \ + +#define translate_invalidate_dcache() \ +{ \ + invalidate_cache_region(rom_translation_cache, \ + rom_translation_cache + ROM_TRANSLATION_CACHE_SIZE); \ + invalidate_cache_region(ram_translation_cache, \ + ram_translation_cache + RAM_TRANSLATION_CACHE_SIZE); \ + invalidate_cache_region(bios_translation_cache, \ + bios_translation_cache + BIOS_TRANSLATION_CACHE_SIZE); \ +} \ + +#define block_prologue_size 0 + + +// It should be okay to still generate result flags, spsr will overwrite them. +// This is pretty infrequent (returning from interrupt handlers, et al) so +// probably not worth optimizing for. + +#define check_for_interrupts() \ + if((io_registers[REG_IE] & io_registers[REG_IF]) && \ + io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \ + { \ + reg_mode[MODE_IRQ][6] = pc + 4; \ + spsr[MODE_IRQ] = reg[REG_CPSR]; \ + reg[REG_CPSR] = 0xD2; \ + pc = 0x00000018; \ + set_cpu_mode(MODE_IRQ); \ + } \ + +#define generate_load_reg_pc(ireg, reg_index, pc_offset) \ + if(reg_index == 15) \ + { \ + generate_load_pc(ireg, pc + pc_offset); \ + } \ + else \ + { \ + generate_load_reg(ireg, reg_index); \ + } \ + +#define generate_store_reg_pc_no_flags(ireg, reg_index) \ + generate_store_reg(ireg, reg_index); \ + if(reg_index == 15) \ + { \ + generate_indirect_branch_arm(); \ + } \ + + +u32 function_cc execute_spsr_restore_body(u32 pc) +{ + set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); + check_for_interrupts(); + + return pc; +} + + +#define generate_store_reg_pc_flags(ireg, reg_index) \ + generate_store_reg(ireg, reg_index); \ + if(reg_index == 15) \ + { \ + if(condition == 0x0E) \ + { \ + generate_cycle_update(); \ + } \ + generate_function_call(execute_spsr_restore); \ + } \ + + +#define generate_load_flags() \ +/* ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) */ \ + +#define generate_store_flags() \ +/* ARM_MRS_CPSR(0, reg_flags) */ \ + +#define generate_save_flags() \ + ARM_MRS_CPSR(0, reg_flags) \ + +#define generate_restore_flags() \ + ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) \ + + +#define condition_opposite_eq ARMCOND_NE +#define condition_opposite_ne ARMCOND_EQ +#define condition_opposite_cs ARMCOND_CC +#define condition_opposite_cc ARMCOND_CS +#define condition_opposite_mi ARMCOND_PL +#define condition_opposite_pl ARMCOND_MI +#define condition_opposite_vs ARMCOND_VC +#define condition_opposite_vc ARMCOND_VS +#define condition_opposite_hi ARMCOND_LS +#define condition_opposite_ls ARMCOND_HI +#define condition_opposite_ge ARMCOND_LT +#define condition_opposite_lt ARMCOND_GE +#define condition_opposite_gt ARMCOND_LE +#define condition_opposite_le ARMCOND_GT +#define condition_opposite_al ARMCOND_NV +#define condition_opposite_nv ARMCOND_AL + +#define generate_branch(mode) \ +{ \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target, mode); \ + block_exit_position++; \ +} \ + + +#define generate_op_and_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_AND_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_orr_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_ORR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_eor_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_EOR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_bic_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_BIC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_sub_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_SUB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_rsb_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_RSB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_sbc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_SBC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_rsc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_RSC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_add_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_ADD_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_adc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_ADC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_mov_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_MOV_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \ + +#define generate_op_mvn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + ARM_MVN_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \ + + +#define generate_op_and_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_AND_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_orr_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_ORR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_eor_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_EOR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_bic_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_BIC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_sub_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_SUB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_rsb_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_RSB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_sbc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_SBC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_rsc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_RSC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_add_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_ADD_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_adc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_ADC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_mov_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_MOV_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \ + +#define generate_op_mvn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + ARM_MVN_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \ + + +#define generate_op_and_imm(_rd, _rn) \ + ARM_AND_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_orr_imm(_rd, _rn) \ + ARM_ORR_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_eor_imm(_rd, _rn) \ + ARM_EOR_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_bic_imm(_rd, _rn) \ + ARM_BIC_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_sub_imm(_rd, _rn) \ + ARM_SUB_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_rsb_imm(_rd, _rn) \ + ARM_RSB_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_sbc_imm(_rd, _rn) \ + ARM_SBC_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_rsc_imm(_rd, _rn) \ + ARM_RSC_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_add_imm(_rd, _rn) \ + ARM_ADD_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_adc_imm(_rd, _rn) \ + ARM_ADC_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_mov_imm(_rd, _rn) \ + ARM_MOV_REG_IMM(0, _rd, imm, imm_ror) \ + +#define generate_op_mvn_imm(_rd, _rn) \ + ARM_MVN_REG_IMM(0, _rd, imm, imm_ror) \ + + +#define generate_op_reg_immshift_lflags(name, _rd, _rn, _rm, st, shift) \ + ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \ + +#define generate_op_reg_immshift_aflags(name, _rd, _rn, _rm, st, shift) \ + ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \ + +#define generate_op_reg_immshift_aflags_load_c(name, _rd, _rn, _rm, st, sh) \ + ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, sh) \ + +#define generate_op_reg_immshift_uflags(name, _rd, _rm, shift_type, shift) \ + ARM_##name##_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \ + +#define generate_op_reg_immshift_tflags(name, _rn, _rm, shift_type, shift) \ + ARM_##name##_REG_IMMSHIFT(0, _rn, _rm, shift_type, shift) \ + + +#define generate_op_reg_regshift_lflags(name, _rd, _rn, _rm, shift_type, _rs) \ + ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_reg_regshift_aflags(name, _rd, _rn, _rm, st, _rs) \ + ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \ + +#define generate_op_reg_regshift_aflags_load_c(name, _rd, _rn, _rm, st, _rs) \ + ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \ + +#define generate_op_reg_regshift_uflags(name, _rd, _rm, shift_type, _rs) \ + ARM_##name##_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \ + +#define generate_op_reg_regshift_tflags(name, _rn, _rm, shift_type, _rs) \ + ARM_##name##_REG_REGSHIFT(0, _rn, _rm, shift_type, _rs) \ + + +#define generate_op_imm_lflags(name, _rd, _rn) \ + ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_imm_aflags(name, _rd, _rn) \ + ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_imm_aflags_load_c(name, _rd, _rn) \ + ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \ + +#define generate_op_imm_uflags(name, _rd) \ + ARM_##name##_REG_IMM(0, _rd, imm, imm_ror) \ + +#define generate_op_imm_tflags(name, _rn) \ + ARM_##name##_REG_IMM(0, _rn, imm, imm_ror) \ + + +#define generate_op_ands_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_lflags(ANDS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_orrs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_lflags(ORRS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_eors_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_lflags(EORS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_bics_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_lflags(BICS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_subs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_aflags(SUBS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_rsbs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_aflags(RSBS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_sbcs_reg_immshift(_rd, _rn, _rm, st, shift) \ + generate_op_reg_immshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, shift) \ + +#define generate_op_rscs_reg_immshift(_rd, _rn, _rm, st, shift) \ + generate_op_reg_immshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, shift) \ + +#define generate_op_adds_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_aflags(ADDS, _rd, _rn, _rm, shift_type, shift) \ + +#define generate_op_adcs_reg_immshift(_rd, _rn, _rm, st, shift) \ + generate_op_reg_immshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, shift) \ + +#define generate_op_movs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_uflags(MOVS, _rd, _rm, shift_type, shift) \ + +#define generate_op_mvns_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_uflags(MVNS, _rd, _rm, shift_type, shift) \ + +// The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't +// being used here. When rsbs is fully inlined it can be used with the +// apropriate operands. + +#define generate_op_neg_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ +{ \ + generate_load_imm(reg_rn, 0, 0); \ + generate_op_subs_reg_immshift(_rd, reg_rn, _rm, ARMSHIFT_LSL, 0); \ +} \ + +#define generate_op_muls_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_load_flags(); \ + ARM_MULS(0, _rd, _rn, _rm); \ + generate_store_flags() \ + +#define generate_op_cmp_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_tflags(CMP, _rn, _rm, shift_type, shift) \ + +#define generate_op_cmn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_tflags(CMN, _rn, _rm, shift_type, shift) \ + +#define generate_op_tst_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_tflags(TST, _rn, _rm, shift_type, shift) \ + +#define generate_op_teq_reg_immshift(_rd, _rn, _rm, shift_type, shift) \ + generate_op_reg_immshift_tflags(TEQ, _rn, _rm, shift_type, shift) \ + + +#define generate_op_ands_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_lflags(ANDS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_orrs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_lflags(ORRS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_eors_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_lflags(EORS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_bics_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_lflags(BICS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_subs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_aflags(SUBS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_rsbs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_aflags(RSBS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_sbcs_reg_regshift(_rd, _rn, _rm, st, _rs) \ + generate_op_reg_regshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, _rs) \ + +#define generate_op_rscs_reg_regshift(_rd, _rn, _rm, st, _rs) \ + generate_op_reg_regshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, _rs) \ + +#define generate_op_adds_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_aflags(ADDS, _rd, _rn, _rm, shift_type, _rs) \ + +#define generate_op_adcs_reg_regshift(_rd, _rn, _rm, st, _rs) \ + generate_op_reg_regshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, _rs) \ + +#define generate_op_movs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_uflags(MOVS, _rd, _rm, shift_type, _rs) \ + +#define generate_op_mvns_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_uflags(MVNS, _rd, _rm, shift_type, _rs) \ + +#define generate_op_cmp_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_tflags(CMP, _rn, _rm, shift_type, _rs) \ + +#define generate_op_cmn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_tflags(CMN, _rn, _rm, shift_type, _rs) \ + +#define generate_op_tst_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_tflags(TST, _rn, _rm, shift_type, _rs) \ + +#define generate_op_teq_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \ + generate_op_reg_regshift_tflags(TEQ, _rn, _rm, shift_type, _rs) \ + + +#define generate_op_ands_imm(_rd, _rn) \ + generate_op_imm_lflags(ANDS, _rd, _rn) \ + +#define generate_op_orrs_imm(_rd, _rn) \ + generate_op_imm_lflags(ORRS, _rd, _rn) \ + +#define generate_op_eors_imm(_rd, _rn) \ + generate_op_imm_lflags(EORS, _rd, _rn) \ + +#define generate_op_bics_imm(_rd, _rn) \ + generate_op_imm_lflags(BICS, _rd, _rn) \ + +#define generate_op_subs_imm(_rd, _rn) \ + generate_op_imm_aflags(SUBS, _rd, _rn) \ + +#define generate_op_rsbs_imm(_rd, _rn) \ + generate_op_imm_aflags(RSBS, _rd, _rn) \ + +#define generate_op_sbcs_imm(_rd, _rn) \ + generate_op_imm_aflags_load_c(SBCS, _rd, _rn) \ + +#define generate_op_rscs_imm(_rd, _rn) \ + generate_op_imm_aflags_load_c(RSCS, _rd, _rn) \ + +#define generate_op_adds_imm(_rd, _rn) \ + generate_op_imm_aflags(ADDS, _rd, _rn) \ + +#define generate_op_adcs_imm(_rd, _rn) \ + generate_op_imm_aflags_load_c(ADCS, _rd, _rn) \ + +#define generate_op_movs_imm(_rd, _rn) \ + generate_op_imm_uflags(MOVS, _rd) \ + +#define generate_op_mvns_imm(_rd, _rn) \ + generate_op_imm_uflags(MVNS, _rd) \ + +#define generate_op_cmp_imm(_rd, _rn) \ + generate_op_imm_tflags(CMP, _rn) \ + +#define generate_op_cmn_imm(_rd, _rn) \ + generate_op_imm_tflags(CMN, _rn) \ + +#define generate_op_tst_imm(_rd, _rn) \ + generate_op_imm_tflags(TST, _rn) \ + +#define generate_op_teq_imm(_rd, _rn) \ + generate_op_imm_tflags(TEQ, _rn) \ + + +#define prepare_load_rn_yes() \ + u32 _rn = prepare_load_reg_pc(reg_rn, rn, 8) \ + +#define prepare_load_rn_no() \ + +#define prepare_store_rd_yes() \ + u32 _rd = prepare_store_reg(reg_rd, rd) \ + +#define prepare_store_rd_no() \ + +#define complete_store_rd_yes(flags_op) \ + complete_store_reg_pc_##flags_op(_rd, rd) \ + +#define complete_store_rd_no(flags_op) \ + +#define arm_generate_op_reg(name, load_op, store_op, flags_op) \ + u32 shift_type = (opcode >> 5) & 0x03; \ + arm_decode_data_proc_reg(); \ + prepare_load_rn_##load_op(); \ + prepare_store_rd_##store_op(); \ + \ + if((opcode >> 4) & 0x01) \ + { \ + u32 rs = ((opcode >> 8) & 0x0F); \ + u32 _rs = prepare_load_reg(reg_rs, rs); \ + u32 _rm = prepare_load_reg_pc(reg_rm, rm, 12); \ + generate_op_##name##_reg_regshift(_rd, _rn, _rm, shift_type, _rs); \ + } \ + else \ + { \ + u32 shift_imm = ((opcode >> 7) & 0x1F); \ + u32 _rm = prepare_load_reg_pc(reg_rm, rm, 8); \ + generate_op_##name##_reg_immshift(_rd, _rn, _rm, shift_type, shift_imm); \ + } \ + complete_store_rd_##store_op(flags_op) \ + +#define arm_generate_op_reg_flags(name, load_op, store_op, flags_op) \ + arm_generate_op_reg(name, load_op, store_op, flags_op) \ + +// imm will be loaded by the called function if necessary. + +#define arm_generate_op_imm(name, load_op, store_op, flags_op) \ + arm_decode_data_proc_imm(); \ + prepare_load_rn_##load_op(); \ + prepare_store_rd_##store_op(); \ + generate_op_##name##_imm(_rd, _rn); \ + complete_store_rd_##store_op(flags_op) \ + +#define arm_generate_op_imm_flags(name, load_op, store_op, flags_op) \ + arm_generate_op_imm(name, load_op, store_op, flags_op) \ + +#define arm_data_proc(name, type, flags_op) \ +{ \ + arm_generate_op_##type(name, yes, yes, flags_op); \ +} \ + +#define arm_data_proc_test(name, type) \ +{ \ + arm_generate_op_##type(name, yes, no, no); \ +} \ + +#define arm_data_proc_unary(name, type, flags_op) \ +{ \ + arm_generate_op_##type(name, no, yes, flags_op); \ +} \ + + +#define arm_multiply_add_no_flags_no() \ + ARM_MUL(0, _rd, _rm, _rs) \ + +#define arm_multiply_add_yes_flags_no() \ + u32 _rn = prepare_load_reg(reg_a2, rn); \ + ARM_MLA(0, _rd, _rm, _rs, _rn) \ + +#define arm_multiply_add_no_flags_yes() \ + generate_load_flags(); \ + ARM_MULS(0, reg_a0, reg_a0, reg_a1) \ + generate_store_flags() \ + +#define arm_multiply_add_yes_flags_yes() \ + u32 _rn = prepare_load_reg(reg_a2, rn); \ + generate_load_flags(); \ + ARM_MLAS(0, _rd, _rm, _rs, _rn); \ + generate_store_flags() + + +#define arm_multiply(add_op, flags) \ +{ \ + arm_decode_multiply(); \ + u32 _rm = prepare_load_reg(reg_a0, rm); \ + u32 _rs = prepare_load_reg(reg_a1, rs); \ + u32 _rd = prepare_store_reg(reg_a0, rd); \ + arm_multiply_add_##add_op##_flags_##flags(); \ + complete_store_reg(_rd, rd); \ +} \ + + +#define arm_multiply_long_name_s64 SMULL +#define arm_multiply_long_name_u64 UMULL +#define arm_multiply_long_name_s64_add SMLAL +#define arm_multiply_long_name_u64_add UMLAL + + +#define arm_multiply_long_flags_no(name) \ + ARM_##name(0, _rdlo, _rdhi, _rm, _rs) \ + +#define arm_multiply_long_flags_yes(name) \ + generate_load_flags(); \ + ARM_##name##S(0, _rdlo, _rdhi, _rm, _rs); \ + generate_store_flags() \ + + +#define arm_multiply_long_add_no(name) \ + +#define arm_multiply_long_add_yes(name) \ + prepare_load_reg(reg_a0, rdlo); \ + prepare_load_reg(reg_a1, rdhi) \ + + +#define arm_multiply_long_op(flags, name) \ + arm_multiply_long_flags_##flags(name) \ + +#define arm_multiply_long(name, add_op, flags) \ +{ \ + arm_decode_multiply_long(); \ + u32 _rm = prepare_load_reg(reg_a2, rm); \ + u32 _rs = prepare_load_reg(reg_rs, rs); \ + u32 _rdlo = prepare_store_reg(reg_a0, rdlo); \ + u32 _rdhi = prepare_store_reg(reg_a1, rdhi); \ + arm_multiply_long_add_##add_op(name); \ + arm_multiply_long_op(flags, arm_multiply_long_name_##name); \ + complete_store_reg(_rdlo, rdlo); \ + complete_store_reg(_rdhi, rdhi); \ +} \ + +#define arm_psr_read_cpsr() \ + u32 _rd = prepare_store_reg(reg_a0, rd); \ + generate_load_reg(_rd, REG_CPSR); \ + ARM_BIC_REG_IMM(0, _rd, _rd, 0xF0, arm_imm_lsl_to_rot(24)); \ + ARM_AND_REG_IMM(0, reg_flags, reg_flags, 0xF0, arm_imm_lsl_to_rot(24)); \ + ARM_ORR_REG_REG(0, _rd, _rd, reg_flags); \ + complete_store_reg(_rd, rd) \ + +#define arm_psr_read_spsr() \ + generate_function_call(execute_read_spsr) \ + generate_store_reg(reg_a0, rd) \ + +#define arm_psr_read(op_type, psr_reg) \ + arm_psr_read_##psr_reg() \ + +// This function's okay because it's called from an ASM function that can +// wrap it correctly. + +u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) +{ + reg[REG_CPSR] = _cpsr; + if(store_mask & 0xFF) + { + set_cpu_mode(cpu_modes[_cpsr & 0x1F]); + if((io_registers[REG_IE] & io_registers[REG_IF]) && + io_registers[REG_IME] && ((_cpsr & 0x80) == 0)) + { + reg_mode[MODE_IRQ][6] = address + 4; + spsr[MODE_IRQ] = _cpsr; + reg[REG_CPSR] = 0xD2; + set_cpu_mode(MODE_IRQ); + return 0x00000018; + } + } + + return 0; +} + +#define arm_psr_load_new_reg() \ + generate_load_reg(reg_a0, rm) \ + +#define arm_psr_load_new_imm() \ + generate_load_imm(reg_a0, imm, imm_ror) \ + +#define arm_psr_store_cpsr() \ + arm_load_imm_32bit(reg_a1, psr_masks[psr_field]); \ + generate_function_call(execute_store_cpsr); \ + write32(pc) \ + +#define arm_psr_store_spsr() \ + generate_function_call(execute_store_spsr) \ + +#define arm_psr_store(op_type, psr_reg) \ + arm_psr_load_new_##op_type(); \ + arm_psr_store_##psr_reg() \ + + +#define arm_psr(op_type, transfer_type, psr_reg) \ +{ \ + arm_decode_psr_##op_type(); \ + arm_psr_##transfer_type(op_type, psr_reg); \ +} \ + +// TODO: loads will need the PC passed as well for open address, however can +// eventually be rectified with a hash table on the memory accesses +// (same with the stores) + +#define arm_access_memory_load(mem_type) \ + cycle_count += 2; \ + generate_function_call(execute_load_##mem_type); \ + write32((pc + 8)); \ + generate_store_reg_pc_no_flags(reg_rv, rd) \ + +#define arm_access_memory_store(mem_type) \ + cycle_count++; \ + generate_load_reg_pc(reg_a1, rd, 12); \ + generate_function_call(execute_store_##mem_type); \ + write32((pc + 4)) \ + +// Calculate the address into a0 from _rn, _rm + +#define arm_access_memory_adjust_reg_sh_up(ireg) \ + ARM_ADD_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \ + ((opcode >> 7) & 0x1F)) \ + +#define arm_access_memory_adjust_reg_sh_down(ireg) \ + ARM_SUB_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \ + ((opcode >> 7) & 0x1F)) \ + +#define arm_access_memory_adjust_reg_up(ireg) \ + ARM_ADD_REG_REG(0, ireg, _rn, _rm) \ + +#define arm_access_memory_adjust_reg_down(ireg) \ + ARM_SUB_REG_REG(0, ireg, _rn, _rm) \ + +#define arm_access_memory_adjust_imm(op, ireg) \ +{ \ + u32 stores[4]; \ + u32 rotations[4]; \ + u32 store_count = arm_disect_imm_32bit(offset, stores, rotations); \ + \ + if(store_count > 1) \ + { \ + ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \ + ARM_##op##_REG_IMM(0, ireg, ireg, stores[1], rotations[1]); \ + } \ + else \ + { \ + ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \ + } \ +} \ + +#define arm_access_memory_adjust_imm_up(ireg) \ + arm_access_memory_adjust_imm(ADD, ireg) \ + +#define arm_access_memory_adjust_imm_down(ireg) \ + arm_access_memory_adjust_imm(SUB, ireg) \ + + +#define arm_access_memory_pre(type, direction) \ + arm_access_memory_adjust_##type##_##direction(reg_a0) \ + +#define arm_access_memory_pre_wb(type, direction) \ + arm_access_memory_adjust_##type##_##direction(reg_a0); \ + generate_store_reg(reg_a0, rn) \ + +#define arm_access_memory_post(type, direction) \ + u32 _rn_dest = prepare_store_reg(reg_a1, rn); \ + if(_rn != reg_a0) \ + { \ + generate_load_reg(reg_a0, rn); \ + } \ + arm_access_memory_adjust_##type##_##direction(_rn_dest); \ + complete_store_reg(_rn_dest, rn) \ + + +#define arm_data_trans_reg(adjust_op, direction) \ + arm_decode_data_trans_reg(); \ + u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \ + u32 _rm = prepare_load_reg(reg_a1, rm); \ + arm_access_memory_##adjust_op(reg_sh, direction) \ + +#define arm_data_trans_imm(adjust_op, direction) \ + arm_decode_data_trans_imm(); \ + u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \ + arm_access_memory_##adjust_op(imm, direction) \ + + +#define arm_data_trans_half_reg(adjust_op, direction) \ + arm_decode_half_trans_r(); \ + u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \ + u32 _rm = prepare_load_reg(reg_a1, rm); \ + arm_access_memory_##adjust_op(reg, direction) \ + +#define arm_data_trans_half_imm(adjust_op, direction) \ + arm_decode_half_trans_of(); \ + u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \ + arm_access_memory_##adjust_op(imm, direction) \ + + +#define arm_access_memory(access_type, direction, adjust_op, mem_type, \ + offset_type) \ +{ \ + arm_data_trans_##offset_type(adjust_op, direction); \ + arm_access_memory_##access_type(mem_type); \ +} \ + + +#define word_bit_count(word) \ + (bit_count[word >> 8] + bit_count[word & 0xFF]) \ + +#define sprint_no(access_type, pre_op, post_op, wb) \ + +#define sprint_yes(access_type, pre_op, post_op, wb) \ + printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \ + + +// TODO: Make these use cached registers. Implement iwram_stack_optimize. + +#define arm_block_memory_load() \ + generate_function_call(execute_load_u32); \ + write32((pc + 8)); \ + generate_store_reg(reg_rv, i) \ + +#define arm_block_memory_store() \ + generate_load_reg_pc(reg_a1, i, 8); \ + generate_function_call(execute_store_u32_safe) \ + +#define arm_block_memory_final_load() \ + arm_block_memory_load() \ + +#define arm_block_memory_final_store() \ + generate_load_reg_pc(reg_a1, i, 12); \ + generate_function_call(execute_store_u32); \ + write32((pc + 4)) \ + +#define arm_block_memory_adjust_pc_store() \ + +#define arm_block_memory_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_mov(reg_a0, reg_rv); \ + generate_indirect_branch_arm(); \ + } \ + +#define arm_block_memory_offset_down_a() \ + generate_sub_imm(reg_s0, ((word_bit_count(reg_list) * 4) - 4), 0) \ + +#define arm_block_memory_offset_down_b() \ + generate_sub_imm(reg_s0, (word_bit_count(reg_list) * 4), 0) \ + +#define arm_block_memory_offset_no() \ + +#define arm_block_memory_offset_up() \ + generate_add_imm(reg_s0, 4, 0) \ + +#define arm_block_memory_writeback_down() \ + generate_load_reg(reg_a0, rn); \ + generate_sub_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \ + generate_store_reg(reg_a0, rn) \ + +#define arm_block_memory_writeback_up() \ + generate_load_reg(reg_a0, rn); \ + generate_add_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \ + generate_store_reg(reg_a0, rn) \ + +#define arm_block_memory_writeback_no() + +// Only emit writeback if the register is not in the list + +#define arm_block_memory_writeback_load(writeback_type) \ + if(!((reg_list >> rn) & 0x01)) \ + { \ + arm_block_memory_writeback_##writeback_type(); \ + } \ + +#define arm_block_memory_writeback_store(writeback_type) \ + arm_block_memory_writeback_##writeback_type() \ + +#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \ +{ \ + arm_decode_block_trans(); \ + u32 offset = 0; \ + u32 i; \ + \ + generate_load_reg(reg_s0, rn); \ + arm_block_memory_offset_##offset_type(); \ + arm_block_memory_writeback_##access_type(writeback_type); \ + ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + arm_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + arm_block_memory_final_##access_type(); \ + break; \ + } \ + } \ + } \ + \ + arm_block_memory_adjust_pc_##access_type(); \ +} \ + +#define arm_swap(type) \ +{ \ + arm_decode_swap(); \ + cycle_count += 3; \ + generate_load_reg(reg_a0, rn); \ + generate_function_call(execute_load_##type); \ + write32((pc + 8)); \ + generate_mov(reg_s0, reg_rv); \ + generate_load_reg(reg_a0, rn); \ + generate_load_reg(reg_a1, rm); \ + generate_function_call(execute_store_##type); \ + write32((pc + 4)); \ + generate_store_reg(reg_s0, rd); \ +} \ + + +#define thumb_generate_op_reg(name, _rd, _rs, _rn) \ + u32 __rm = prepare_load_reg(reg_rm, _rn); \ + generate_op_##name##_reg_immshift(__rd, __rn, __rm, ARMSHIFT_LSL, 0) \ + +#define thumb_generate_op_imm(name, _rd, _rs, imm_) \ +{ \ + u32 imm_ror = 0; \ + generate_op_##name##_imm(__rd, __rn); \ +} \ + + +#define thumb_data_proc(type, name, op_type, _rd, _rs, _rn) \ +{ \ + thumb_decode_##type(); \ + u32 __rn = prepare_load_reg(reg_rn, _rs); \ + u32 __rd = prepare_store_reg(reg_rd, _rd); \ + generate_load_reg(reg_rn, _rs); \ + thumb_generate_op_##op_type(name, _rd, _rs, _rn); \ + complete_store_reg(__rd, _rd); \ +} \ + +#define thumb_data_proc_test(type, name, op_type, _rd, _rs) \ +{ \ + thumb_decode_##type(); \ + u32 __rn = prepare_load_reg(reg_rn, _rd); \ + thumb_generate_op_##op_type(name, 0, _rd, _rs); \ +} \ + +#define thumb_data_proc_unary(type, name, op_type, _rd, _rs) \ +{ \ + thumb_decode_##type(); \ + u32 __rd = prepare_store_reg(reg_rd, _rd); \ + thumb_generate_op_##op_type(name, _rd, 0, _rs); \ + complete_store_reg(__rd, _rd); \ +} \ + + +#define complete_store_reg_pc_thumb() \ + if(rd == 15) \ + { \ + generate_indirect_branch_cycle_update(thumb); \ + } \ + else \ + { \ + complete_store_reg(_rd, rd); \ + } \ + +#define thumb_data_proc_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \ + u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \ + generate_op_##name##_reg_immshift(_rd, _rd, _rs, ARMSHIFT_LSL, 0); \ + complete_store_reg_pc_thumb(); \ +} \ + +#define thumb_data_proc_test_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \ + u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \ + generate_op_##name##_reg_immshift(0, _rd, _rs, ARMSHIFT_LSL, 0); \ +} \ + +#define thumb_data_proc_mov_hi() \ +{ \ + thumb_decode_hireg_op(); \ + u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \ + u32 _rd = prepare_store_reg(reg_rd, rd); \ + ARM_MOV_REG_REG(0, _rd, _rs); \ + complete_store_reg_pc_thumb(); \ +} \ + + + +#define thumb_load_pc(_rd) \ +{ \ + thumb_decode_imm(); \ + u32 __rd = prepare_store_reg(reg_rd, _rd); \ + generate_load_pc(__rd, (((pc & ~2) + 4) + (imm * 4))); \ + complete_store_reg(__rd, _rd); \ +} \ + +#define thumb_load_sp(_rd) \ +{ \ + thumb_decode_imm(); \ + u32 __sp = prepare_load_reg(reg_a0, REG_SP); \ + u32 __rd = prepare_store_reg(reg_a0, _rd); \ + ARM_ADD_REG_IMM(0, __rd, __sp, imm, arm_imm_lsl_to_rot(2)); \ + complete_store_reg(__rd, _rd); \ +} \ + +#define thumb_adjust_sp_up() \ + ARM_ADD_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \ + +#define thumb_adjust_sp_down() \ + ARM_SUB_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \ + +#define thumb_adjust_sp(direction) \ +{ \ + thumb_decode_add_sp(); \ + u32 _sp = prepare_load_reg(reg_a0, REG_SP); \ + thumb_adjust_sp_##direction(); \ + complete_store_reg(_sp, REG_SP); \ +} \ + +#define generate_op_lsl_reg(_rd, _rm, _rs) \ + generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSL, _rs) \ + +#define generate_op_lsr_reg(_rd, _rm, _rs) \ + generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSR, _rs) \ + +#define generate_op_asr_reg(_rd, _rm, _rs) \ + generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ASR, _rs) \ + +#define generate_op_ror_reg(_rd, _rm, _rs) \ + generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ROR, _rs) \ + + +#define generate_op_lsl_imm(_rd, _rm) \ + generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSL, imm) \ + +#define generate_op_lsr_imm(_rd, _rm) \ + generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSR, imm) \ + +#define generate_op_asr_imm(_rd, _rm) \ + generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ASR, imm) \ + +#define generate_op_ror_imm(_rd, _rm) \ + generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ROR, imm) \ + + +#define generate_shift_reg(op_type) \ + u32 __rm = prepare_load_reg(reg_rd, rd); \ + u32 __rs = prepare_load_reg(reg_rs, rs); \ + generate_op_##op_type##_reg(__rd, __rm, __rs) \ + +#define generate_shift_imm(op_type) \ + u32 __rs = prepare_load_reg(reg_rs, rs); \ + generate_op_##op_type##_imm(__rd, __rs) \ + + +#define thumb_shift(decode_type, op_type, value_type) \ +{ \ + thumb_decode_##decode_type(); \ + u32 __rd = prepare_store_reg(reg_rd, rd); \ + generate_shift_##value_type(op_type); \ + complete_store_reg(__rd, rd); \ +} \ + +// Operation types: imm, mem_reg, mem_imm + +#define thumb_access_memory_load(mem_type, _rd) \ + cycle_count += 2; \ + generate_function_call(execute_load_##mem_type); \ + write32((pc + 4)); \ + generate_store_reg(reg_rv, _rd) \ + +#define thumb_access_memory_store(mem_type, _rd) \ + cycle_count++; \ + generate_load_reg(reg_a1, _rd); \ + generate_function_call(execute_store_##mem_type); \ + write32((pc + 2)) \ + +#define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro) \ + generate_load_pc(reg_a0, (offset)) \ + +#define thumb_access_memory_generate_address_reg_imm(offset, _rb, _ro) \ + u32 __rb = prepare_load_reg(reg_a0, _rb); \ + ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, 0) \ + +#define thumb_access_memory_generate_address_reg_imm_sp(offset, _rb, _ro) \ + u32 __rb = prepare_load_reg(reg_a0, _rb); \ + ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, arm_imm_lsl_to_rot(2)) \ + +#define thumb_access_memory_generate_address_reg_reg(offset, _rb, _ro) \ + u32 __rb = prepare_load_reg(reg_a0, _rb); \ + u32 __ro = prepare_load_reg(reg_a1, _ro); \ + ARM_ADD_REG_REG(0, reg_a0, __rb, __ro) \ + +#define thumb_access_memory(access_type, op_type, _rd, _rb, _ro, \ + address_type, offset, mem_type) \ +{ \ + thumb_decode_##op_type(); \ + thumb_access_memory_generate_address_##address_type(offset, _rb, _ro); \ + thumb_access_memory_##access_type(mem_type, _rd); \ +} \ + +// TODO: Make these use cached registers. Implement iwram_stack_optimize. + +#define thumb_block_address_preadjust_up() \ + generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0) \ + +#define thumb_block_address_preadjust_down() \ + generate_sub_imm(reg_s0, (bit_count[reg_list] * 4), 0) \ + +#define thumb_block_address_preadjust_push_lr() \ + generate_sub_imm(reg_s0, ((bit_count[reg_list] + 1) * 4), 0) \ + +#define thumb_block_address_preadjust_no() \ + +#define thumb_block_address_postadjust_no(base_reg) \ + generate_store_reg(reg_s0, base_reg) \ + +#define thumb_block_address_postadjust_up(base_reg) \ + generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \ + generate_store_reg(reg_a0, base_reg) \ + +#define thumb_block_address_postadjust_down(base_reg) \ + generate_mov(reg_a0, reg_s0); \ + generate_sub_imm(reg_a0, (bit_count[reg_list] * 4), 0); \ + generate_store_reg(reg_a0, base_reg) \ + +#define thumb_block_address_postadjust_pop_pc(base_reg) \ + generate_add_reg_reg_imm(reg_a0, reg_s0, \ + ((bit_count[reg_list] + 1) * 4), 0); \ + generate_store_reg(reg_a0, base_reg) \ + +#define thumb_block_address_postadjust_push_lr(base_reg) \ + generate_store_reg(reg_s0, base_reg) \ + +#define thumb_block_memory_extra_no() \ + +#define thumb_block_memory_extra_up() \ + +#define thumb_block_memory_extra_down() \ + +#define thumb_block_memory_extra_pop_pc() \ + generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \ + generate_function_call(execute_load_u32); \ + write32((pc + 4)); \ + generate_mov(reg_a0, reg_rv); \ + generate_indirect_branch_cycle_update(thumb) \ + +#define thumb_block_memory_extra_push_lr(base_reg) \ + generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \ + generate_load_reg(reg_a1, REG_LR); \ + generate_function_call(execute_store_u32_safe) \ + +#define thumb_block_memory_load() \ + generate_function_call(execute_load_u32); \ + write32((pc + 4)); \ + generate_store_reg(reg_rv, i) \ + +#define thumb_block_memory_store() \ + generate_load_reg(reg_a1, i); \ + generate_function_call(execute_store_u32_safe) \ + +#define thumb_block_memory_final_load() \ + thumb_block_memory_load() \ + +#define thumb_block_memory_final_store() \ + generate_load_reg(reg_a1, i); \ + generate_function_call(execute_store_u32); \ + write32((pc + 2)) \ + +#define thumb_block_memory_final_no(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_up(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_down(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_push_lr(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory_final_pop_pc(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory(access_type, pre_op, post_op, base_reg) \ +{ \ + thumb_decode_rlist(); \ + u32 i; \ + u32 offset = 0; \ + \ + generate_load_reg(reg_s0, base_reg); \ + ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \ + thumb_block_address_preadjust_##pre_op(); \ + thumb_block_address_postadjust_##post_op(base_reg); \ + \ + for(i = 0; i < 8; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + thumb_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + thumb_block_memory_final_##post_op(access_type); \ + break; \ + } \ + } \ + } \ + \ + thumb_block_memory_extra_##post_op(); \ +} \ + +#define thumb_conditional_branch(condition) \ +{ \ + generate_cycle_update(); \ + generate_load_flags(); \ + generate_branch_filler(condition_opposite_##condition, backpatch_address); \ + generate_branch_no_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target, thumb); \ + generate_branch_patch_conditional(backpatch_address, translation_ptr); \ + block_exit_position++; \ +} \ + + +#define arm_conditional_block_header() \ + generate_cycle_update(); \ + generate_load_flags(); \ + /* This will choose the opposite condition */ \ + condition ^= 0x01; \ + generate_branch_filler(condition, backpatch_address) \ + +#define arm_b() \ + generate_branch(arm) \ + +#define arm_bl() \ + generate_update_pc((pc + 4)); \ + generate_store_reg(reg_a0, REG_LR); \ + generate_branch(arm) \ + +#define arm_bx() \ + arm_decode_branchx(); \ + generate_load_reg(reg_a0, rn); \ + generate_indirect_branch_dual(); \ + +#define arm_swi() \ + generate_swi_hle_handler((opcode >> 16) & 0xFF, arm); \ + generate_function_call(execute_swi_arm); \ + write32((pc + 4)); \ + generate_branch(arm) \ + +#define thumb_b() \ + generate_branch(thumb) \ + +#define thumb_bl() \ + generate_update_pc(((pc + 2) | 0x01)); \ + generate_store_reg(reg_a0, REG_LR); \ + generate_branch(thumb) \ + +#define thumb_blh() \ +{ \ + thumb_decode_branch(); \ + generate_update_pc(((pc + 2) | 0x01)); \ + generate_load_reg(reg_a1, REG_LR); \ + generate_store_reg(reg_a0, REG_LR); \ + generate_mov(reg_a0, reg_a1); \ + generate_add_imm(reg_a0, (offset * 2), 0); \ + generate_indirect_branch_cycle_update(thumb); \ +} \ + +#define thumb_bx() \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(reg_a0, rs, 4); \ + generate_indirect_branch_cycle_update(dual_thumb); \ +} \ + +#define thumb_swi() \ + generate_swi_hle_handler(opcode & 0xFF, thumb); \ + generate_function_call(execute_swi_thumb); \ + write32((pc + 2)); \ + /* We're in ARM mode now */ \ + generate_branch(arm) \ + +u8 swi_hle_handle[256] = +{ + 0x0, // SWI 0: SoftReset + 0x0, // SWI 1: RegisterRAMReset + 0x0, // SWI 2: Halt + 0x0, // SWI 3: Stop/Sleep + 0x0, // SWI 4: IntrWait + 0x0, // SWI 5: VBlankIntrWait + 0x1, // SWI 6: Div + 0x0, // SWI 7: DivArm + 0x0, // SWI 8: Sqrt + 0x0, // SWI 9: ArcTan + 0x0, // SWI A: ArcTan2 + 0x0, // SWI B: CpuSet + 0x0, // SWI C: CpuFastSet + 0x0, // SWI D: GetBIOSCheckSum + 0x0, // SWI E: BgAffineSet + 0x0, // SWI F: ObjAffineSet + 0x0, // SWI 10: BitUnpack + 0x0, // SWI 11: LZ77UnCompWram + 0x0, // SWI 12: LZ77UnCompVram + 0x0, // SWI 13: HuffUnComp + 0x0, // SWI 14: RLUnCompWram + 0x0, // SWI 15: RLUnCompVram + 0x0, // SWI 16: Diff8bitUnFilterWram + 0x0, // SWI 17: Diff8bitUnFilterVram + 0x0, // SWI 18: Diff16bitUnFilter + 0x0, // SWI 19: SoundBias + 0x0, // SWI 1A: SoundDriverInit + 0x0, // SWI 1B: SoundDriverMode + 0x0, // SWI 1C: SoundDriverMain + 0x0, // SWI 1D: SoundDriverVSync + 0x0, // SWI 1E: SoundChannelClear + 0x0, // SWI 1F: MidiKey2Freq + 0x0, // SWI 20: SoundWhatever0 + 0x0, // SWI 21: SoundWhatever1 + 0x0, // SWI 22: SoundWhatever2 + 0x0, // SWI 23: SoundWhatever3 + 0x0, // SWI 24: SoundWhatever4 + 0x0, // SWI 25: MultiBoot + 0x0, // SWI 26: HardReset + 0x0, // SWI 27: CustomHalt + 0x0, // SWI 28: SoundDriverVSyncOff + 0x0, // SWI 29: SoundDriverVSyncOn + 0x0 // SWI 2A: SoundGetJumpList +}; + +void execute_swi_hle_div_arm(); +void execute_swi_hle_div_thumb(); + +void execute_swi_hle_div_c() +{ + s32 result = (s32)reg[0] / (s32)reg[1]; + reg[1] = (s32)reg[0] % (s32)reg[1]; + reg[0] = result; + + reg[3] = (result ^ (result >> 31)) - (result >> 31); +} + +#define generate_swi_hle_handler(_swi_number, mode) \ +{ \ + u32 swi_number = _swi_number; \ + if(swi_hle_handle[swi_number]) \ + { \ + /* Div */ \ + if(swi_number == 0x06) \ + { \ + generate_function_call(execute_swi_hle_div_##mode); \ + } \ + break; \ + } \ +} \ + +#define generate_translation_gate(type) \ + generate_update_pc(pc); \ + generate_indirect_branch_no_cycle_update(type) \ + +#define generate_step_debug() \ + generate_function_call(step_debug_arm); \ + write32(pc) \ + +#endif + diff --git a/gp2x/arm_stub.S b/gp2x/arm_stub.S new file mode 100644 index 0000000..17512ba --- /dev/null +++ b/gp2x/arm_stub.S @@ -0,0 +1,1016 @@ +.align 2 + +.global arm_update_gba_arm +.global arm_update_gba_thumb +.global arm_update_gba_idle_arm +.global arm_update_gba_idle_thumb + +.global arm_indirect_branch_arm +.global arm_indirect_branch_thumb +.global arm_indirect_branch_dual_arm +.global arm_indirect_branch_dual_thumb + +.global execute_arm_translate + +.global execute_store_u8 +.global execute_store_u16 +.global execute_store_u32 +.global execute_store_u32_safe + +.global execute_load_u8 +.global execute_load_s8 +.global execute_load_u16 +.global execute_load_s16 +.global execute_load_u32 + +.global execute_store_cpsr +.global execute_read_spsr +.global execute_store_spsr +.global execute_spsr_restore + +.global execute_swi_arm +.global execute_swi_thumb + +.global execute_patch_bios_read +.global execute_patch_bios_protect + +.global execute_bios_ptr_protected +.global execute_bios_rom_ptr + + +.global step_debug_arm + +.global invalidate_icache_region +.global invalidate_cache_region + +.global memory_map_read +.global memory_map_write +.global reg + +#define REG_BASE_OFFSET 1024 + +#define REG_R0 (REG_BASE_OFFSET + (0 * 4)) +#define REG_R1 (REG_BASE_OFFSET + (1 * 4)) +#define REG_R2 (REG_BASE_OFFSET + (2 * 4)) +#define REG_R3 (REG_BASE_OFFSET + (3 * 4)) +#define REG_R4 (REG_BASE_OFFSET + (4 * 4)) +#define REG_R5 (REG_BASE_OFFSET + (5 * 4)) +#define REG_R6 (REG_BASE_OFFSET + (6 * 4)) +#define REG_R7 (REG_BASE_OFFSET + (7 * 4)) +#define REG_R8 (REG_BASE_OFFSET + (8 * 4)) +#define REG_R9 (REG_BASE_OFFSET + (9 * 4)) +#define REG_R10 (REG_BASE_OFFSET + (10 * 4)) +#define REG_R11 (REG_BASE_OFFSET + (11 * 4)) +#define REG_R12 (REG_BASE_OFFSET + (12 * 4)) +#define REG_R13 (REG_BASE_OFFSET + (13 * 4)) +#define REG_R14 (REG_BASE_OFFSET + (14 * 4)) +#define REG_SP (REG_BASE_OFFSET + (13 * 4)) +#define REG_LR (REG_BASE_OFFSET + (14 * 4)) +#define REG_PC (REG_BASE_OFFSET + (15 * 4)) + +#define REG_N_FLAG (REG_BASE_OFFSET + (16 * 4)) +#define REG_Z_FLAG (REG_BASE_OFFSET + (17 * 4)) +#define REG_C_FLAG (REG_BASE_OFFSET + (18 * 4)) +#define REG_V_FLAG (REG_BASE_OFFSET + (19 * 4)) +#define REG_CPSR (REG_BASE_OFFSET + (20 * 4)) + +#define REG_SAVE (REG_BASE_OFFSET + (21 * 4)) +#define REG_SAVE2 (REG_BASE_OFFSET + (22 * 4)) +#define REG_SAVE3 (REG_BASE_OFFSET + (23 * 4)) + +#define CPU_MODE (REG_BASE_OFFSET + (29 * 4)) +#define CPU_HALT_STATE (REG_BASE_OFFSET + (30 * 4)) +#define CHANGED_PC_STATUS (REG_BASE_OFFSET + (31 * 4)) + + +#define reg_a0 r0 +#define reg_a1 r1 +#define reg_a2 r2 + +#define reg_s0 r9 +#define reg_base sp +#define reg_flags r11 + +#define reg_cycles r12 + +#define reg_x0 r3 +#define reg_x1 r4 +#define reg_x2 r5 +#define reg_x3 r6 +#define reg_x4 r7 +#define reg_x5 r8 + + +#define MODE_SUPERVISOR 3 + + +@ Will load the register set from memory into the appropriate cached registers. +@ See arm_emit.h for listing explanation. + +#define load_registers_arm() ;\ + ldr reg_x0, [reg_base, #REG_R0] ;\ + ldr reg_x1, [reg_base, #REG_R1] ;\ + ldr reg_x2, [reg_base, #REG_R6] ;\ + ldr reg_x3, [reg_base, #REG_R9] ;\ + ldr reg_x4, [reg_base, #REG_R12] ;\ + ldr reg_x5, [reg_base, #REG_R14] ;\ + +#define load_registers_thumb() ;\ + ldr reg_x0, [reg_base, #REG_R0] ;\ + ldr reg_x1, [reg_base, #REG_R1] ;\ + ldr reg_x2, [reg_base, #REG_R2] ;\ + ldr reg_x3, [reg_base, #REG_R3] ;\ + ldr reg_x4, [reg_base, #REG_R4] ;\ + ldr reg_x5, [reg_base, #REG_R5] ;\ + + +@ Will store the register set from cached registers back to memory. + +#define store_registers_arm() ;\ + str reg_x0, [reg_base, #REG_R0] ;\ + str reg_x1, [reg_base, #REG_R1] ;\ + str reg_x2, [reg_base, #REG_R6] ;\ + str reg_x3, [reg_base, #REG_R9] ;\ + str reg_x4, [reg_base, #REG_R12] ;\ + str reg_x5, [reg_base, #REG_R14] ;\ + +#define store_registers_thumb() ;\ + str reg_x0, [reg_base, #REG_R0] ;\ + str reg_x1, [reg_base, #REG_R1] ;\ + str reg_x2, [reg_base, #REG_R2] ;\ + str reg_x3, [reg_base, #REG_R3] ;\ + str reg_x4, [reg_base, #REG_R4] ;\ + str reg_x5, [reg_base, #REG_R5] ;\ + + +@ Returns an updated persistent cpsr with the cached flags register. +@ Uses reg as a temporary register and returns the CPSR here. + +#define collapse_flags_no_update(reg) ;\ + ldr reg, [reg_base, #REG_CPSR] /* reg = cpsr */;\ + bic reg, reg, #0xF0000000 /* clear ALU flags in cpsr */;\ + and reg_flags, reg_flags, #0xF0000000 /* clear non-ALU flags */;\ + orr reg, reg, reg_flags /* update cpsr with ALU flags */;\ + +@ Updates cpsr using the above macro. + +#define collapse_flags(reg) ;\ + collapse_flags_no_update(reg) ;\ + str reg, [reg_base, #REG_CPSR] ;\ + +@ Loads the saved flags register from the persistent cpsr. + +#define extract_flags() ;\ + ldr reg_flags, [reg_base, #REG_CPSR] ;\ + msr cpsr_f, reg_flags ;\ + + +#define save_flags() ;\ + mrs reg_flags, cpsr ;\ + +#define restore_flags() ;\ + msr cpsr_f, reg_flags ;\ + +@ Calls a C function - all caller save registers which are important to the +@ dynarec and to returning from this function are saved. + +#define call_c_function(function) ;\ + stmdb sp!, { r3, r12, lr } ;\ + bl function ;\ + ldmia sp!, { r3, r12, lr } ;\ + + +@ Update the GBA hardware (video, sound, input, etc) + +@ Input: +@ r0: current PC + +#define return_straight() ;\ + bx lr ;\ + +#define return_add() ;\ + add pc, lr, #4 ;\ + +#define load_pc_straight() ;\ + ldr r0, [lr, #-8] ;\ + +#define load_pc_add() ;\ + ldr r0, [lr] ;\ + + +#define arm_update_gba_builder(name, mode, return_op) ;\ + ;\ +arm_update_gba_##name: ;\ + load_pc_##return_op() ;\ + str r0, [reg_base, #REG_PC] /* write out the PC */;\ + ;\ + save_flags() ;\ + collapse_flags(r0) /* update the flags */;\ + ;\ + store_registers_##mode() /* save out registers */;\ + call_c_function(update_gba) /* update GBA state */;\ + ;\ + mvn reg_cycles, r0 /* load new cycle count */;\ + ;\ + ldr r0, [reg_base, #CHANGED_PC_STATUS] /* load PC changed status */;\ + cmp r0, #0 /* see if PC has changed */;\ + beq 1f /* if not return */;\ + ;\ + ldr r0, [reg_base, #REG_PC] /* load new PC */;\ + ldr r1, [reg_base, #REG_CPSR] /* r1 = flags */;\ + tst r1, #0x20 /* see if Thumb bit is set */;\ + bne 2f /* if so load Thumb PC */;\ + ;\ + load_registers_arm() /* load ARM regs */;\ + call_c_function(block_lookup_address_arm) ;\ + restore_flags() ;\ + bx r0 /* jump to new ARM block */;\ + ;\ +1: ;\ + load_registers_##mode() /* reload registers */;\ + restore_flags() ;\ + return_##return_op() ;\ + ;\ +2: ;\ + load_registers_thumb() /* load Thumb regs */;\ + call_c_function(block_lookup_address_thumb) ;\ + restore_flags() ;\ + bx r0 /* jump to new ARM block */;\ + + +arm_update_gba_builder(arm, arm, straight) +arm_update_gba_builder(thumb, thumb, straight) + +arm_update_gba_builder(idle_arm, arm, add) +arm_update_gba_builder(idle_thumb, thumb, add) + + + +@ These are b stubs for performing indirect branches. They are not +@ linked to and don't return, instead they link elsewhere. + +@ Input: +@ r0: PC to branch to + +arm_indirect_branch_arm: + save_flags() + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 + +arm_indirect_branch_thumb: + save_flags() + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 + +arm_indirect_branch_dual_arm: + save_flags() + tst r0, #0x01 @ check lower bit + bne 1f @ if set going to Thumb mode + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 @ return + +1: + bic r0, r0, #0x01 + store_registers_arm() @ save out ARM registers + load_registers_thumb() @ load in Thumb registers + ldr r1, [reg_base, #REG_CPSR] @ load cpsr + orr r1, r1, #0x20 @ set Thumb mode + str r1, [reg_base, #REG_CPSR] @ store flags + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 @ return + +arm_indirect_branch_dual_thumb: + save_flags() + tst r0, #0x01 @ check lower bit + beq 1f @ if set going to ARM mode + bic r0, r0, #0x01 + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 @ return + +1: + store_registers_thumb() @ save out Thumb registers + load_registers_arm() @ load in ARM registers + ldr r1, [reg_base, #REG_CPSR] @ load cpsr + bic r1, r1, #0x20 @ clear Thumb mode + str r1, [reg_base, #REG_CPSR] @ store flags + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 @ return + + +@ Update the cpsr. + +@ Input: +@ r0: new cpsr value +@ r1: bitmask of which bits in cpsr to update +@ r2: current PC + +execute_store_cpsr: + save_flags() + and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask + ldr r0, [reg_base, #REG_CPSR] @ r0 = cpsr + bic r0, r0, r1 @ r0 = cpsr & ~store_mask + orr reg_flags, reg_flags, r0 @ reg_flags = new_cpsr | cpsr + + mov r0, reg_flags @ also put new cpsr in r0 + + store_registers_arm() @ save ARM registers + ldr r2, [lr] @ r2 = pc + call_c_function(execute_store_cpsr_body) + load_registers_arm() @ restore ARM registers + + cmp r0, #0 @ check new PC + beq 1f @ if it's zero, return + + call_c_function(block_lookup_address_arm) + + restore_flags() + bx r0 @ return to new ARM address + +1: + restore_flags() + add pc, lr, #4 @ return + + +@ Update the current spsr. + +@ Input: +@ r0: new cpsr value +@ r1: bitmask of which bits in spsr to update + +execute_store_spsr: + ldr r1, 1f @ r1 = spsr + ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE + str r0, [r1, r2, lsl #2] @ spsr[CPU_MODE] = new_spsr + bx lr + +1: + .word spsr + +@ Read the current spsr. + +@ Output: +@ r0: spsr + +execute_read_spsr: + ldr r0, 1b @ r0 = spsr + ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE + ldr r0, [r0, r1, lsl #2] @ r0 = spsr[CPU_MODE] + bx lr @ return + + +@ Restore the cpsr from the mode spsr and mode shift. + +@ Input: +@ r0: current pc + +execute_spsr_restore: + save_flags() + ldr r1, 1f @ r1 = spsr + ldr r2, [reg_base, #CPU_MODE] @ r2 = cpu_mode + ldr r1, [r1, r2, lsl #2] @ r1 = spsr[cpu_mode] (new cpsr) + str r1, [reg_base, #REG_CPSR] @ update cpsr + mov reg_flags, r1 @ also, update shadow flags + + @ This function call will pass r0 (address) and return it. + store_registers_arm() @ save ARM registers + call_c_function(execute_spsr_restore_body) + + ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr + tst r1, #0x20 @ see if Thumb mode is set + bne 2f @ if so handle it + + load_registers_arm() @ restore ARM registers + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 + + @ This will service execute_spsr_restore and execute_swi +1: + .word spsr + +2: + load_registers_thumb() @ load Thumb registers + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 + + + +@ Setup the mode transition work for calling an SWI. + +@ Input: +@ r0: current pc + +#define execute_swi_builder(mode) ;\ + ;\ +execute_swi_##mode: ;\ + save_flags() ;\ + ldr r1, 1f /* r1 = reg_mode */;\ + /* reg_mode[MODE_SUPERVISOR][6] = pc */;\ + ldr r0, [lr] /* load PC */;\ + str r0, [r1, #((MODE_SUPERVISOR * (7 * 4)) + (6 * 4))] ;\ + collapse_flags_no_update(r0) /* r0 = cpsr */;\ + ldr r1, 2f /* r1 = spsr */;\ + str r0, [r1, #(MODE_SUPERVISOR * 4)] /* spsr[MODE_SUPERVISOR] = cpsr */;\ + bic r0, r0, #0x3F /* clear mode flag in r0 */;\ + orr r0, r0, #0x13 /* set to supervisor mode */;\ + str r0, [reg_base, #REG_CPSR] /* update cpsr */;\ + ;\ + call_c_function(bios_region_read_allow) ;\ + ;\ + mov r0, #MODE_SUPERVISOR ;\ + ;\ + store_registers_##mode() /* store regs for mode */;\ + call_c_function(set_cpu_mode) /* set the CPU mode to svsr */;\ + load_registers_arm() /* load ARM regs */;\ + ;\ + restore_flags() ;\ + add pc, lr, #4 /* return */;\ + ;\ +1: ;\ + .word reg_mode ;\ + ;\ +2: ;\ + .word spsr ;\ + ;\ +3: ;\ + .word execute_bios_rom_ptr ;\ + +execute_swi_builder(arm) +execute_swi_builder(thumb) + + +@ Wrapper for calling SWI functions in C (or can implement some in ASM if +@ desired) + +#define execute_swi_function_builder(swi_function, mode) ;\ + ;\ + .global execute_swi_hle_##swi_function##_##mode ;\ +execute_swi_hle_##swi_function##_##mode: ;\ + save_flags() ;\ + store_registers_##mode() ;\ + call_c_function(execute_swi_hle_##swi_function##_c) ;\ + load_registers_##mode() ;\ + restore_flags() ;\ + bx lr ;\ + +execute_swi_function_builder(div, arm) +execute_swi_function_builder(div, thumb) + + +@ Start program execution. Normally the mode should be Thumb and the +@ PC should be 0x8000000, however if a save state is preloaded this +@ will be different. + +@ Input: +@ r0: initial value for cycle counter + +@ Uses sp as reg_base; must hold consistently true. + +execute_arm_translate: + sub sp, sp, #0x100 @ allocate room for register data + + mvn reg_cycles, r0 @ load cycle counter + + mov r0, reg_base @ load reg_base into first param + call_c_function(move_reg) @ make reg_base the new reg ptr + + sub sp, sp, #REG_BASE_OFFSET @ allocate room for ptr table + bl load_ptr_read_function_table @ load read function ptr table + + ldr r0, [reg_base, #REG_PC] @ r0 = current pc + ldr r1, [reg_base, #REG_CPSR] @ r1 = flags + tst r1, #0x20 @ see if Thumb bit is set + + bne 1f @ if so lookup thumb + + load_registers_arm() @ load ARM registers + call_c_function(block_lookup_address_arm) + extract_flags() @ load flags + bx r0 @ jump to first ARM block + +1: + load_registers_thumb() @ load Thumb registers + call_c_function(block_lookup_address_thumb) + extract_flags() @ load flags + bx r0 @ jump to first Thumb block + + +@ Write out to memory. + +@ Input: +@ r0: address +@ r1: value +@ r2: current pc + +#define execute_store_body(store_type, store_op) ;\ + save_flags() ;\ + stmdb sp!, { lr } /* save lr */;\ + tst r0, #0xF0000000 /* make sure address is in range */;\ + bne ext_store_u##store_type /* if not do ext store */;\ + ;\ + ldr r2, 1f /* r2 = memory_map_write */;\ + mov lr, r0, lsr #15 /* lr = page index of address */;\ + ldr r2, [r2, lr, lsl #2] /* r2 = memory page */;\ + ;\ + cmp r2, #0 /* see if map is ext */;\ + beq ext_store_u##store_type /* if so do ext store */;\ + ;\ + mov r0, r0, lsl #17 /* isolate bottom 15 bits in top */;\ + mov r0, r0, lsr #17 /* like performing and 0x7FFF */;\ + store_op r1, [r2, r0] /* store result */;\ + + +#define store_align_8() ;\ + +#define store_align_16() ;\ + bic r0, r0, #0x01 ;\ + +#define store_align_32() ;\ + bic r0, r0, #0x03 ;\ + + +#define execute_store_builder(store_type, store_op, load_op) ;\ + ;\ +execute_store_u##store_type: ;\ + execute_store_body(store_type, store_op) ;\ + sub r2, r2, #0x8000 /* Pointer to code status data */;\ + load_op r0, [r2, r0] /* check code flag */;\ + ;\ + cmp r0, #0 /* see if it's not 0 */;\ + bne 2f /* if so perform smc write */;\ + ldmia sp!, { lr } /* restore lr */;\ + restore_flags() ;\ + add pc, lr, #4 /* return */;\ + ;\ +2: ;\ + ldmia sp!, { lr } /* restore lr */;\ + ldr r0, [lr] /* load PC */;\ + str r0, [reg_base, #REG_PC] /* write out PC */;\ + b smc_write /* perform smc write */;\ +1: ;\ + .word memory_map_write ;\ + ;\ +ext_store_u##store_type: ;\ + ldmia sp!, { lr } /* pop lr off of stack */;\ + ldr r2, [lr] /* load PC */;\ + str r2, [reg_base, #REG_PC] /* write out PC */;\ + store_align_##store_type() ;\ + call_c_function(write_memory##store_type) ;\ + b write_epilogue /* handle additional write stuff */;\ + +execute_store_builder(8, strb, ldrb) +execute_store_builder(16, strh, ldrh) +execute_store_builder(32, str, ldr) + + +execute_store_u32_safe: + execute_store_body(32_safe, str) + restore_flags() + ldmia sp!, { pc } @ return + +1: + .word memory_map_write + +ext_store_u32_safe: + ldmia sp!, { lr } @ Restore lr + call_c_function(write_memory32) @ Perform 32bit store + restore_flags() + bx lr @ Return + + +write_epilogue: + cmp r0, #0 @ check if the write rose an alert + beq 4f @ if not we can exit + + collapse_flags(r1) @ interrupt needs current flags + + cmp r0, #2 @ see if the alert is due to SMC + beq smc_write @ if so, goto SMC handler + + ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr + tst r1, #0x20 @ see if Thumb bit is set + bne 1f @ if so do Thumb update + + store_registers_arm() @ save ARM registers + +3: + bl update_gba @ update GBA until CPU isn't halted + + mvn reg_cycles, r0 @ load new cycle count + ldr r0, [reg_base, #REG_PC] @ load new PC + ldr r1, [reg_base, #REG_CPSR] @ r1 = flags + tst r1, #0x20 @ see if Thumb bit is set + bne 2f + + load_registers_arm() + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 @ jump to new ARM block + +1: + store_registers_thumb() @ save Thumb registers + b 3b + +2: + load_registers_thumb() + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 @ jump to new Thumb block + +4: + restore_flags() + add pc, lr, #4 @ return + + +smc_write: + call_c_function(flush_translation_cache_ram) + +lookup_pc: + ldr r0, [reg_base, #REG_PC] @ r0 = new pc + ldr r1, [reg_base, #REG_CPSR] @ r1 = flags + tst r1, #0x20 @ see if Thumb bit is set + beq lookup_pc_arm @ if not lookup ARM + +lookup_pc_thumb: + call_c_function(block_lookup_address_thumb) + restore_flags() + bx r0 @ jump to new Thumb block + +lookup_pc_arm: + call_c_function(block_lookup_address_arm) + restore_flags() + bx r0 @ jump to new ARM block + + +#define sign_extend_u8(reg) +#define sign_extend_u16(reg) +#define sign_extend_u32(reg) + +#define sign_extend_s8(reg) ;\ + mov reg, reg, lsl #24 /* shift reg into upper 8bits */;\ + mov reg, reg, asr #24 /* shift down, sign extending */;\ + +#define sign_extend_s16(reg) ;\ + mov reg, reg, lsl #16 /* shift reg into upper 16bits */;\ + mov reg, reg, asr #16 /* shift down, sign extending */;\ + +#define execute_load_op_u8(load_op) ;\ + mov r0, r0, lsl #17 ;\ + load_op r0, [r2, r0, lsr #17] ;\ + +#define execute_load_op_s8(load_op) ;\ + mov r0, r0, lsl #17 ;\ + mov r0, r0, lsr #17 ;\ + load_op r0, [r2, r0] ;\ + +#define execute_load_op_u16(load_op) ;\ + execute_load_op_s8(load_op) ;\ + +#define execute_load_op_s16(load_op) ;\ + execute_load_op_s8(load_op) ;\ + +#define execute_load_op_u16(load_op) ;\ + execute_load_op_s8(load_op) ;\ + +#define execute_load_op_u32(load_op) ;\ + execute_load_op_u8(load_op) ;\ + + +#define execute_load_builder(load_type, load_function, load_op, mask) ;\ + ;\ +execute_load_##load_type: ;\ + save_flags() ;\ + tst r0, mask /* make sure address is in range */;\ + bne ext_load_##load_type /* if not do ext load */;\ + ;\ + ldr r2, 1f /* r2 = memory_map_read */;\ + mov r1, r0, lsr #15 /* r1 = page index of address */;\ + ldr r2, [r2, r1, lsl #2] /* r2 = memory page */;\ + ;\ + cmp r2, #0 /* see if map is ext */;\ + beq ext_load_##load_type /* if so do ext load */;\ + ;\ + execute_load_op_##load_type(load_op) ;\ + restore_flags() ;\ + add pc, lr, #4 /* return */;\ + ;\ +ext_load_##load_type: ;\ + ldr r1, [lr] /* r1 = PC */;\ + str r1, [reg_base, #REG_PC] /* update PC */;\ + call_c_function(read_memory##load_function) ;\ + sign_extend_##load_type(r0) /* sign extend result */;\ + restore_flags() ;\ + add pc, lr, #4 /* return */;\ + ;\ +1: ;\ + .word memory_map_read ;\ + + +execute_load_builder(u8, 8, ldrneb, #0xF0000000) +execute_load_builder(s8, 8, ldrnesb, #0xF0000000) +execute_load_builder(u16, 16, ldrneh, #0xF0000001) +execute_load_builder(s16, 16_signed, ldrnesh, #0xF0000001) +execute_load_builder(u32, 32, ldrne, #0xF0000000) + + +#define execute_ptr_builder(region, ptr, bits) ;\ + ;\ +execute_##region##_ptr: ;\ + ldr r1, 1f /* load region ptr */;\ + mov r0, r0, lsl #(32 - bits) /* isolate bottom bits */;\ + mov r0, r0, lsr #(32 - bits) ;\ + bx lr /* return */;\ + ;\ +1: ;\ + .word (ptr) ;\ + + +execute_bios_ptr_protected: + ldr r1, 1f @ load bios read ptr + and r0, r0, #0x03 @ only want bottom 2 bits + bx lr @ return + +1: + .word bios_read_protect + + +@ address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; + +execute_ewram_ptr: + ldr r1, 1f @ load ewram read ptr + mov r2, r0, lsl #17 @ isolate bottom 15 bits + mov r2, r2, lsr #17 + and r0, r0, #0x38000 @ isolate top 2 bits + add r0, r2, r0, lsl #1 @ add top 2 bits * 2 to bottom 15 + bx lr @ return + +1: + .word (ewram + 0x8000) + + +@ u32 gamepak_index = address >> 15; +@ u8 *map = memory_map_read[gamepak_index]; + +@ if(map == NULL) +@ map = load_gamepak_page(gamepak_index & 0x3FF); + +@ value = address##type(map, address & 0x7FFF) + +execute_gamepak_ptr: + ldr r1, 1f @ load memory_map_read + mov r2, r0, lsr #15 @ isolate top 17 bits + ldr r1, [r1, r2, lsl #2] @ load memory map read ptr + + save_flags() + cmp r1, #0 @ see if map entry is NULL + bne 2f @ if not resume + + stmdb sp!, { r0 } @ save r0 on stack + mov r2, r2, lsl #20 @ isolate page index + mov r0, r2, lsr #20 + call_c_function(load_gamepak_page) @ read new page into r0 + + mov r1, r0 @ new map = return + ldmia sp!, { r0 } @ restore r0 + +2: + mov r0, r0, lsl #17 @ isolate bottom 15 bits + mov r0, r0, lsr #17 + restore_flags() + bx lr @ return + +1: + .word memory_map_read + + +@ These will store the result in a pointer, then pass that pointer. + +execute_eeprom_ptr: + save_flags() + + call_c_function(read_eeprom) @ load EEPROM result + add r1, reg_base, #(REG_SAVE & 0xFF00) + add r1, r1, #(REG_SAVE & 0xFF) + strh r0, [r1] @ write result out + mov r0, #0 @ zero out address + + restore_flags() + bx lr @ return + + +execute_backup_ptr: + save_flags() + + mov r0, r0, lsl #16 @ only want top 16 bits + mov r0, r0, lsr #16 + call_c_function(read_backup) @ load backup result + add r1, reg_base, #(REG_SAVE & 0xFF00) + add r1, r1, #(REG_SAVE & 0xFF) + strb r0, [r1] @ write result out + mov r0, #0 @ zero out address + + restore_flags() + bx lr @ return + + +execute_open_ptr: + ldr r1, [reg_base, #REG_CPSR] @ r1 = cpsr + save_flags() + + stmdb sp!, { r0 } @ save r0 + + ldr r0, [lr, #-4] @ r0 = current PC + + tst r1, #0x20 @ see if Thumb bit is set + bne 1f @ if so load Thumb op + + call_c_function(read_memory32) @ read open address + + add r1, reg_base, #((REG_SAVE + 4) & 0xFF00) + add r1, r1, #((REG_SAVE + 4) & 0xFF) + add r1, r1, reg_base + str r0, [r1] @ write out + + ldmia sp!, { r0 } @ restore r0 + and r0, r0, #0x03 @ isolate bottom 2 bits + + restore_flags() + bx lr + +1: + call_c_function(read_memory16) @ read open address + + orr r0, r0, r0, lsl #16 @ duplicate opcode over halves + add r1, reg_base, #((REG_SAVE + 4) & 0xFF00) + add r1, r1, #((REG_SAVE + 4) & 0xFF) + + add r1, r1, reg_base + str r0, [r1] @ write out + + ldmia sp!, { r0 } @ restore r0 + and r0, r0, #0x03 @ isolate bottom 2 bits + + restore_flags(); + bx lr + + +execute_ptr_builder(bios_rom, bios_rom, 14) +execute_ptr_builder(iwram, iwram + 0x8000, 15) +execute_ptr_builder(vram, vram, 17) +execute_ptr_builder(oam_ram, oam_ram, 10) +execute_ptr_builder(io_registers, io_registers, 10) +execute_ptr_builder(palette_ram, palette_ram, 10) + +ptr_read_function_table: + .word execute_bios_ptr_protected @ 0x00: BIOS + .word execute_open_ptr @ 0x01: open + .word execute_ewram_ptr @ 0x02: ewram + .word execute_iwram_ptr @ 0x03: iwram + .word execute_io_registers_ptr @ 0x04: I/O registers + .word execute_palette_ram_ptr @ 0x05: palette RAM + .word execute_vram_ptr @ 0x06: vram + .word execute_oam_ram_ptr @ 0x07: oam RAM + .word execute_gamepak_ptr @ 0x08: gamepak + .word execute_gamepak_ptr @ 0x09: gamepak + .word execute_gamepak_ptr @ 0x0A: gamepak + .word execute_gamepak_ptr @ 0x0B: gamepak + .word execute_gamepak_ptr @ 0x0C: gamepak + .word execute_eeprom_ptr @ 0x0D: EEPROM + .word execute_backup_ptr @ 0x0E: backup + +.rept (256 - 15) @ 0x0F - 0xFF: open + .word execute_open_ptr +.endr + + +@ Setup the read function table. +@ Load this onto the the stack; assume we're free to use r3 + +load_ptr_read_function_table: + mov r0, #256 @ 256 elements + ldr r1, 1f @ r0 = ptr_read_function_table + mov r2, sp @ load here + +2: + ldr r3, [r1], #4 @ read pointer + str r3, [r2], #4 @ write pointer + + subs r0, r0, #1 @ goto next iteration + bne 2b + + bx lr + +1: + .word ptr_read_function_table + + +@ Patch the read function table to allow for BIOS reads. + +execute_patch_bios_read: + ldr r0, 1f @ r0 = patch function + ldr r1, 2f @ r1 = reg + ldr r1, [r1] + str r0, [r1, #-REG_BASE_OFFSET] + bx lr + +1: + .word execute_bios_rom_ptr + +2: + .word reg + + +@ Patch the read function table to allow for BIOS reads. + +execute_patch_bios_protect: + ldr r0, 1f @ r0 = patch function + ldr r1, 2f @ r1 = reg + ldr r1, [r1] + str r0, [r1, #-REG_BASE_OFFSET] + bx lr + +1: + .word execute_bios_ptr_protected + +2: + .word reg + + +#define save_reg_scratch(reg) ;\ + ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\ + str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\ + +#define restore_reg_scratch(reg) ;\ + ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\ + str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\ + +#define scratch_regs_thumb(type) ;\ + type##_reg_scratch(0) ;\ + type##_reg_scratch(1) ;\ + type##_reg_scratch(2) ;\ + type##_reg_scratch(3) ;\ + type##_reg_scratch(4) ;\ + type##_reg_scratch(5) ;\ + +#define scratch_regs_arm(type) ;\ + type##_reg_scratch(0) ;\ + type##_reg_scratch(1) ;\ + type##_reg_scratch(6) ;\ + type##_reg_scratch(9) ;\ + type##_reg_scratch(12) ;\ + type##_reg_scratch(14) ;\ + + +step_debug_arm: + save_flags() + collapse_flags(r0) + + ldr r0, [reg_base, #REG_CPSR] @ r1 = cpsr + tst r0, #0x20 @ see if Thumb bit is set + + ldr r0, [lr] @ load PC + mvn r1, reg_cycles @ load cycle counter + + beq 1f @ if not goto ARM mode + + scratch_regs_thumb(save) + + store_registers_thumb() @ write back Thumb regs + call_c_function(step_debug) @ call debug step + scratch_regs_thumb(restore) + restore_flags() + add pc, lr, #4 @ return + +1: + scratch_regs_arm(save) + store_registers_arm() @ write back ARM regs + call_c_function(step_debug) @ call debug step + scratch_regs_arm(restore) + restore_flags() + add pc, lr, #4 @ return, skipping PC + +invalidate_icache_region: + mov r2, #0x0 + swi 0x9f0002 + + bx lr + +invalidate_cache_region: + mov r2, #0x1 + swi 0x9f0002 + + bx lr + + +.comm memory_map_read 0x8000 +.comm memory_map_write 0x8000 + + + diff --git a/gp2x/bios_cache.S b/gp2x/bios_cache.S new file mode 100644 index 0000000..7383a83 --- /dev/null +++ b/gp2x/bios_cache.S @@ -0,0 +1,478 @@ + +//Gp2x/gp2x/mnt/nand/bios_cache.bin: file format binary + +Disassembly of section .data: + +00000000 <.data>: + 0: e3a00f02 mov r0, #8 ; 0x8 + 4: ebcb1afd bl step_debug + 8: e25cc001 subs ip, ip, #1 ; 0x1 + c: 5a000001 bpl 0x18 + 10: e3a00d05 mov r0, #320 ; 0x140 + 14: ebcb18d0 bl 0xff2c635c + 18: eaffffff b 0x1c + 1c: e3a00d05 mov r0, #320 ; 0x140 + 20: ebcb1af6 bl step_debug + 24: e59a9034 ldr r9, [sl, #52] + 28: e249900c sub r9, r9, #12 ; 0xc + 2c: e59a0034 ldr r0, [sl, #52] + 30: e240000c sub r0, r0, #12 ; 0xc + 34: e58a0034 str r0, [sl, #52] + 38: e3c99003 bic r9, r9, #3 ; 0x3 + 3c: e2890000 add r0, r9, #0 ; 0x0 + 40: e59a102c ldr r1, [sl, #44] + 44: ebcb1a8e bl 0xff2c6a84 + 48: e2890004 add r0, r9, #4 ; 0x4 + 4c: e1a01007 mov r1, r7 + 50: ebcb1a8b bl 0xff2c6a84 + 54: e2890008 add r0, r9, #8 ; 0x8 + 58: e1a01008 mov r1, r8 + 5c: e3a02f51 mov r2, #324 ; 0x144 + 60: ebcb1a6f bl 0xff2c6a24 + 64: e3a00f51 mov r0, #324 ; 0x144 + 68: ebcb1ae4 bl step_debug + 6c: e2480002 sub r0, r8, #2 ; 0x2 + 70: ebcb1a95 bl 0xff2c6acc + 74: e1a07000 mov r7, r0 + 78: e3a00f52 mov r0, #328 ; 0x148 + 7c: ebcb1adf bl step_debug + 80: e3a01e15 mov r1, #336 ; 0x150 + 84: e2810078 add r0, r1, #120 ; 0x78 + 88: e58a002c str r0, [sl, #44] + 8c: e3a00f53 mov r0, #332 ; 0x14c + 90: ebcb1ada bl step_debug + 94: e59a002c ldr r0, [sl, #44] + 98: e0800107 add r0, r0, r7, lsl #2 + 9c: ebcb1ac9 bl 0xff2c6bc8 + a0: e1a07000 mov r7, r0 + a4: e3a00e15 mov r0, #336 ; 0x150 + a8: ebcb1ad4 bl step_debug + ac: ebcb194d bl 0xff2c65e8 + b0: e58a002c str r0, [sl, #44] + b4: e3a00f55 mov r0, #340 ; 0x154 + b8: ebcb1ad0 bl step_debug + bc: e59a9034 ldr r9, [sl, #52] + c0: e2499004 sub r9, r9, #4 ; 0x4 + c4: e59a0034 ldr r0, [sl, #52] + c8: e2400004 sub r0, r0, #4 ; 0x4 + cc: e58a0034 str r0, [sl, #52] + d0: e3c99003 bic r9, r9, #3 ; 0x3 + d4: e2890000 add r0, r9, #0 ; 0x0 + d8: e59a102c ldr r1, [sl, #44] + dc: e3a02f56 mov r2, #344 ; 0x158 + e0: ebcb1a4f bl 0xff2c6a24 + e4: e3a00f56 mov r0, #344 ; 0x158 + e8: ebcb1ac4 bl step_debug + ec: e59a102c ldr r1, [sl, #44] + f0: e2010080 and r0, r1, #128 ; 0x80 + f4: e58a002c str r0, [sl, #44] + f8: e3a00f57 mov r0, #348 ; 0x15c + fc: ebcb1abf bl step_debug + 100: e59a102c ldr r1, [sl, #44] + 104: e381001f orr r0, r1, #31 ; 0x1f + 108: e58a002c str r0, [sl, #44] + 10c: e3a00e16 mov r0, #352 ; 0x160 + 110: ebcb1aba bl step_debug + 114: e59a002c ldr r0, [sl, #44] + 118: e3a02e16 mov r2, #352 ; 0x160 + 11c: e3a010ff mov r1, #255 ; 0xff + 120: e38114ff orr r1, r1, #-16777216 ; 0xff000000 + 124: ebcb190a bl 0xff2c6554 + 128: e3a00f59 mov r0, #356 ; 0x164 + 12c: ebcb1ab3 bl step_debug + 130: e59a9034 ldr r9, [sl, #52] + 134: e2499008 sub r9, r9, #8 ; 0x8 + 138: e59a0034 ldr r0, [sl, #52] + 13c: e2400008 sub r0, r0, #8 ; 0x8 + 140: e58a0034 str r0, [sl, #52] + 144: e3c99003 bic r9, r9, #3 ; 0x3 + 148: e2890000 add r0, r9, #0 ; 0x0 + 14c: e59a1008 ldr r1, [sl, #8] + 150: ebcb1a4b bl 0xff2c6a84 + 154: e2890004 add r0, r9, #4 ; 0x4 + 158: e1a01008 mov r1, r8 + 15c: e3a02f5a mov r2, #360 ; 0x168 + 160: ebcb1a2f bl 0xff2c6a24 + 164: e3a00f5a mov r0, #360 ; 0x168 + 168: ebcb1aa4 bl step_debug + 16c: e3a01e17 mov r1, #368 ; 0x170 + 170: e2818000 add r8, r1, #0 ; 0x0 + 174: e3a00f5b mov r0, #364 ; 0x16c + 178: ebcb1aa0 bl step_debug + 17c: e1a00007 mov r0, r7 + 180: e24cc016 sub ip, ip, #22 ; 0x16 + 184: eacb18be b 0xff2c6484 + 188: e3a00ff1 mov r0, #964 ; 0x3c4 + 18c: e3800b02 orr r0, r0, #2048 ; 0x800 + 190: ebcb1a9a bl step_debug + 194: e59a9034 ldr r9, [sl, #52] + 198: e2499020 sub r9, r9, #32 ; 0x20 + 19c: e59a0034 ldr r0, [sl, #52] + 1a0: e2400020 sub r0, r0, #32 ; 0x20 + 1a4: e58a0034 str r0, [sl, #52] + 1a8: e3c99003 bic r9, r9, #3 ; 0x3 + 1ac: e2890000 add r0, r9, #0 ; 0x0 + 1b0: e59a1010 ldr r1, [sl, #16] + 1b4: ebcb1a32 bl 0xff2c6a84 + 1b8: e2890004 add r0, r9, #4 ; 0x4 + 1bc: e59a1014 ldr r1, [sl, #20] + 1c0: ebcb1a2f bl 0xff2c6a84 + 1c4: e2890008 add r0, r9, #8 ; 0x8 + 1c8: e1a01005 mov r1, r5 + 1cc: ebcb1a2c bl 0xff2c6a84 + 1d0: e289000c add r0, r9, #12 ; 0xc + 1d4: e59a101c ldr r1, [sl, #28] + 1d8: ebcb1a29 bl 0xff2c6a84 + 1dc: e2890010 add r0, r9, #16 ; 0x10 + 1e0: e59a1020 ldr r1, [sl, #32] + 1e4: ebcb1a26 bl 0xff2c6a84 + 1e8: e2890014 add r0, r9, #20 ; 0x14 + 1ec: e1a01006 mov r1, r6 + 1f0: ebcb1a23 bl 0xff2c6a84 + 1f4: e2890018 add r0, r9, #24 ; 0x18 + 1f8: e59a1028 ldr r1, [sl, #40] + 1fc: ebcb1a20 bl 0xff2c6a84 + 200: e289001c add r0, r9, #28 ; 0x1c + 204: e1a01008 mov r1, r8 + 208: e3a02ff2 mov r2, #968 ; 0x3c8 + 20c: e3822b02 orr r2, r2, #2048 ; 0x800 + 210: ebcb1a03 bl 0xff2c6a24 + 214: e3a00ff2 mov r0, #968 ; 0x3c8 + 218: e3800b02 orr r0, r0, #2048 ; 0x800 + 21c: ebcb1a77 bl step_debug + 220: e59a0008 ldr r0, [sl, #8] + 224: e1a00580 mov r0, r0, lsl #11 + 228: e58a0028 str r0, [sl, #40] + 22c: e3a00ff3 mov r0, #972 ; 0x3cc + 230: e3800b02 orr r0, r0, #2048 ; 0x800 + 234: ebcb1a71 bl step_debug + 238: e59a0028 ldr r0, [sl, #40] + 23c: e128f00b msr CPSR_f, fp + 240: e1b074a0 movs r7, r0, lsr #9 + 244: e10fb000 mrs fp, CPSR + 248: e3a00ebd mov r0, #3024 ; 0xbd0 + 24c: ebcb1a6b bl step_debug + 250: e3a00ff5 mov r0, #980 ; 0x3d4 + 254: e3800b02 orr r0, r0, #2048 ; 0x800 + 258: e1a08000 mov r8, r0 + 25c: e25cc00c subs ip, ip, #12 ; 0xc + 260: 5a000002 bpl 0x270 + 264: e3a00fe9 mov r0, #932 ; 0x3a4 + 268: e3800b02 orr r0, r0, #2048 ; 0x800 + 26c: ebcb183a bl 0xff2c635c + 270: eaffffff b 0x274 + 274: e3a00fe9 mov r0, #932 ; 0x3a4 + 278: e3800b02 orr r0, r0, #2048 ; 0x800 + 27c: ebcb1a5f bl step_debug + 280: e3570000 cmp r7, #0 ; 0x0 + 284: e10fb000 mrs fp, CPSR + 288: e3a00fea mov r0, #936 ; 0x3a8 + 28c: e3800b02 orr r0, r0, #2048 ; 0x800 + 290: ebcb1a5a bl step_debug + 294: e24cc002 sub ip, ip, #2 ; 0x2 + 298: e128f00b msr CPSR_f, fp + 29c: 1a000007 bne 0x2c0 + 2a0: 5a000002 bpl 0x2b0 + 2a4: e3a00fef mov r0, #956 ; 0x3bc + 2a8: e3800b02 orr r0, r0, #2048 ; 0x800 + 2ac: ebcb182a bl 0xff2c635c + 2b0: ea000013 b 0x304 + 2b4: e3a00feb mov r0, #940 ; 0x3ac + 2b8: e3800b02 orr r0, r0, #2048 ; 0x800 + 2bc: ebcb1a4f bl step_debug + 2c0: e3c774fe bic r7, r7, #-33554432 ; 0xfe000000 + 2c4: e3a00ebb mov r0, #2992 ; 0xbb0 + 2c8: ebcb1a4c bl step_debug + 2cc: e0837007 add r7, r3, r7 + 2d0: e3a00fed mov r0, #948 ; 0x3b4 + 2d4: e3800b02 orr r0, r0, #2048 ; 0x800 + 2d8: ebcb1a48 bl step_debug + 2dc: e313040e tst r3, #234881024 ; 0xe000000 + 2e0: e10fb000 mrs fp, CPSR + 2e4: e3a00fee mov r0, #952 ; 0x3b8 + 2e8: e3800b02 orr r0, r0, #2048 ; 0x800 + 2ec: ebcb1a43 bl step_debug + 2f0: e24cc004 sub ip, ip, #4 ; 0x4 + 2f4: e128f00b msr CPSR_f, fp + 2f8: 0a000004 beq 0x310 + 2fc: e317040e tst r7, #234881024 ; 0xe000000 + 300: e10fb000 mrs fp, CPSR + 304: e3a00fef mov r0, #956 ; 0x3bc + 308: e3800b02 orr r0, r0, #2048 ; 0x800 + 30c: ebcb1a3b bl step_debug + 310: e1a00008 mov r0, r8 + 314: e24cc001 sub ip, ip, #1 ; 0x1 + 318: eacb1859 b 0xff2c6484 + 31c: e3a00ff5 mov r0, #980 ; 0x3d4 + 320: e3800b02 orr r0, r0, #2048 ; 0x800 + 324: ebcb1a35 bl step_debug + 328: e24cc001 sub ip, ip, #1 ; 0x1 + 32c: e128f00b msr CPSR_f, fp + 330: 1a000007 bne 0x354 + 334: 5a000002 bpl 0x344 + 338: e3a00f09 mov r0, #36 ; 0x24 + 33c: e3800b03 orr r0, r0, #3072 ; 0xc00 + 340: ebcb1805 bl 0xff2c635c + 344: ea0000d6 b 0x6a4 + 348: e3a00ff6 mov r0, #984 ; 0x3d8 + 34c: e3800b02 orr r0, r0, #2048 ; 0x800 + 350: ebcb1a2a bl step_debug + 354: e59a0028 ldr r0, [sl, #40] + 358: e08404a0 add r0, r4, r0, lsr #9 + 35c: e58a0028 str r0, [sl, #40] + 360: e3a00ff7 mov r0, #988 ; 0x3dc + 364: e3800b02 orr r0, r0, #2048 ; 0x800 + 368: ebcb1a24 bl step_debug + 36c: e59a0008 ldr r0, [sl, #8] + 370: e128f00b msr CPSR_f, fp + 374: e1b00ca0 movs r0, r0, lsr #25 + 378: e10fb000 mrs fp, CPSR + 37c: e58a0008 str r0, [sl, #8] + 380: e3a00ebe mov r0, #3040 ; 0xbe0 + 384: ebcb1a1d bl step_debug + 388: e24cc003 sub ip, ip, #3 ; 0x3 + 38c: e128f00b msr CPSR_f, fp + 390: 2a000007 bcs 0x3b4 + 394: 5a000002 bpl 0x3a4 + 398: e3a00f05 mov r0, #20 ; 0x14 + 39c: e3800b03 orr r0, r0, #3072 ; 0xc00 + 3a0: ebcb17ed bl 0xff2c635c + 3a4: ea00006a b 0x554 + 3a8: e3a00ff9 mov r0, #996 ; 0x3e4 + 3ac: e3800b02 orr r0, r0, #2048 ; 0x800 + 3b0: ebcb1a12 bl step_debug + 3b4: e2830000 add r0, r3, #0 ; 0x0 + 3b8: ebcb1a02 bl 0xff2c6bc8 + 3bc: e58a0008 str r0, [sl, #8] + 3c0: e3a00ffa mov r0, #1000 ; 0x3e8 + 3c4: e3800b02 orr r0, r0, #2048 ; 0x800 + 3c8: ebcb1a0c bl step_debug + 3cc: e59a0008 ldr r0, [sl, #8] + 3d0: e1a00000 nop (mov r0,r0) + 3d4: e58a000c str r0, [sl, #12] + 3d8: e3a00ffb mov r0, #1004 ; 0x3ec + 3dc: e3800b02 orr r0, r0, #2048 ; 0x800 + 3e0: ebcb1a06 bl step_debug + 3e4: e59a0008 ldr r0, [sl, #8] + 3e8: e1a00000 nop (mov r0,r0) + 3ec: e58a0010 str r0, [sl, #16] + 3f0: e3a00ebf mov r0, #3056 ; 0xbf0 + 3f4: ebcb1a01 bl step_debug + 3f8: e59a0008 ldr r0, [sl, #8] + 3fc: e1a00000 nop (mov r0,r0) + 400: e58a0014 str r0, [sl, #20] + 404: e3a00ffd mov r0, #1012 ; 0x3f4 + 408: e3800b02 orr r0, r0, #2048 ; 0x800 + 40c: ebcb19fb bl step_debug + 410: e59a0008 ldr r0, [sl, #8] + 414: e1a05000 mov r5, r0 + 418: e3a00ffe mov r0, #1016 ; 0x3f8 + 41c: e3800b02 orr r0, r0, #2048 ; 0x800 + 420: ebcb19f6 bl step_debug + 424: e59a0008 ldr r0, [sl, #8] + 428: e1a00000 nop (mov r0,r0) + 42c: e58a001c str r0, [sl, #28] + 430: e3a00fff mov r0, #1020 ; 0x3fc + 434: e3800b02 orr r0, r0, #2048 ; 0x800 + 438: ebcb19f0 bl step_debug + 43c: e59a0008 ldr r0, [sl, #8] + 440: e1a00000 nop (mov r0,r0) + 444: e58a0020 str r0, [sl, #32] + 448: e3a00b03 mov r0, #3072 ; 0xc00 + 44c: ebcb19eb bl step_debug + 450: e59a0008 ldr r0, [sl, #8] + 454: e1a06000 mov r6, r0 + 458: e24cc00a sub ip, ip, #10 ; 0xa + + 45c: e3a00f01 mov r0, #4 ; 0x4 + 460: e3800b03 orr r0, r0, #3072 ; 0xc00 + 464: ebcb19e5 bl step_debug + + 468: e59a0028 ldr r0, [sl, #40] + 46c: e1540000 cmp r4, r0 + 470: e10fb000 mrs fp, CPSR + + 474: e3a00f02 mov r0, #8 ; 0x8 + 478: e3800b03 orr r0, r0, #3072 ; 0xc00 + + 47c: ebcb19df bl step_debug + 480: e24cc002 sub ip, ip, #2 ; 0x2 + 484: e128f00b msr CPSR_f, fp + + 488: aa000021 bge 0x514 + 48c: e1a09004 mov r9, r4 + + 490: e1a00004 mov r0, r4 + 494: e2800020 add r0, r0, #32 ; 0x20 + 498: e1a04000 mov r4, r0 + 49c: e3c99003 bic r9, r9, #3 ; 0x3 + 4a0: e2890000 add r0, r9, #0 ; 0x0 + 4a4: e59a1008 ldr r1, [sl, #8] + 4a8: ebcb1975 bl 0xff2c6a84 + 4ac: e2890004 add r0, r9, #4 ; 0x4 + 4b0: e59a100c ldr r1, [sl, #12] + 4b4: ebcb1972 bl 0xff2c6a84 + 4b8: e2890008 add r0, r9, #8 ; 0x8 + 4bc: e59a1010 ldr r1, [sl, #16] + 4c0: ebcb196f bl 0xff2c6a84 + 4c4: e289000c add r0, r9, #12 ; 0xc + 4c8: e59a1014 ldr r1, [sl, #20] + 4cc: ebcb196c bl 0xff2c6a84 + 4d0: e2890010 add r0, r9, #16 ; 0x10 + 4d4: e1a01005 mov r1, r5 + 4d8: ebcb1969 bl 0xff2c6a84 + 4dc: e2890014 add r0, r9, #20 ; 0x14 + 4e0: e59a101c ldr r1, [sl, #28] + 4e4: ebcb1966 bl 0xff2c6a84 + 4e8: e2890018 add r0, r9, #24 ; 0x18 + 4ec: e59a1020 ldr r1, [sl, #32] + 4f0: ebcb1963 bl 0xff2c6a84 + 4f4: e289001c add r0, r9, #28 ; 0x1c + 4f8: e1a01006 mov r1, r6 + 4fc: e3a02f03 mov r2, #12 ; 0xc + 500: e3822b03 orr r2, r2, #3072 ; 0xc00 + 504: ebcb1946 bl 0xff2c6a24 + 508: e3a00f03 mov r0, #12 ; 0xc + 50c: e3800b03 orr r0, r0, #3072 ; 0xc00 + 510: ebcb19ba bl step_debug + 514: e24cc009 sub ip, ip, #9 ; 0x9 + 518: e128f00b msr CPSR_f, fp + 51c: aa000006 bge 0x53c + 520: 5a000002 bpl 0x530 + 524: e3a00f01 mov r0, #4 ; 0x4 + 528: e3800b03 orr r0, r0, #3072 ; 0xc00 + 52c: ebcb178a bl 0xff2c635c + 530: eaffffc9 b 0x45c + 534: e3a00ec1 mov r0, #3088 ; 0xc10 + 538: ebcb19b0 bl step_debug + 53c: e25cc001 subs ip, ip, #1 ; 0x1 + 540: 5a000002 bpl 0x550 + 544: e3a00f09 mov r0, #36 ; 0x24 + 548: e3800b03 orr r0, r0, #3072 ; 0xc00 + 54c: ebcb1782 bl 0xff2c635c + 550: ea000053 b 0x6a4 + 554: e3a00f05 mov r0, #20 ; 0x14 + 558: e3800b03 orr r0, r0, #3072 ; 0xc00 + 55c: ebcb19a7 bl step_debug + 560: e59a0028 ldr r0, [sl, #40] + 564: e1540000 cmp r4, r0 + 568: e10fb000 mrs fp, CPSR + 56c: e3a00f06 mov r0, #24 ; 0x18 + 570: e3800b03 orr r0, r0, #3072 ; 0xc00 + 574: ebcb19a1 bl step_debug + 578: e24cc002 sub ip, ip, #2 ; 0x2 + 57c: e128f00b msr CPSR_f, fp + 580: aa00003f bge 0x684 + 584: e1a09003 mov r9, r3 + 588: e1a00003 mov r0, r3 + 58c: e2800020 add r0, r0, #32 ; 0x20 + 590: e1a03000 mov r3, r0 + 594: e3c99003 bic r9, r9, #3 ; 0x3 + 598: e2890000 add r0, r9, #0 ; 0x0 + 59c: ebcb1989 bl 0xff2c6bc8 + 5a0: e58a0008 str r0, [sl, #8] + 5a4: e2890004 add r0, r9, #4 ; 0x4 + 5a8: ebcb1986 bl 0xff2c6bc8 + 5ac: e58a000c str r0, [sl, #12] + 5b0: e2890008 add r0, r9, #8 ; 0x8 + 5b4: ebcb1983 bl 0xff2c6bc8 + 5b8: e58a0010 str r0, [sl, #16] + 5bc: e289000c add r0, r9, #12 ; 0xc + 5c0: ebcb1980 bl 0xff2c6bc8 + 5c4: e58a0014 str r0, [sl, #20] + 5c8: e2890010 add r0, r9, #16 ; 0x10 + 5cc: ebcb197d bl 0xff2c6bc8 + 5d0: e1a05000 mov r5, r0 + 5d4: e2890014 add r0, r9, #20 ; 0x14 + 5d8: ebcb197a bl 0xff2c6bc8 + 5dc: e58a001c str r0, [sl, #28] + 5e0: e2890018 add r0, r9, #24 ; 0x18 + 5e4: ebcb1977 bl 0xff2c6bc8 + 5e8: e58a0020 str r0, [sl, #32] + 5ec: e289001c add r0, r9, #28 ; 0x1c + 5f0: ebcb1974 bl 0xff2c6bc8 + 5f4: e1a06000 mov r6, r0 + 5f8: e3a00f07 mov r0, #28 ; 0x1c + 5fc: e3800b03 orr r0, r0, #3072 ; 0xc00 + 600: ebcb197e bl step_debug + 604: e1a09004 mov r9, r4 + 608: e1a00004 mov r0, r4 + 60c: e2800020 add r0, r0, #32 ; 0x20 + 610: e1a04000 mov r4, r0 + 614: e3c99003 bic r9, r9, #3 ; 0x3 + 618: e2890000 add r0, r9, #0 ; 0x0 + 61c: e59a1008 ldr r1, [sl, #8] + 620: ebcb1917 bl 0xff2c6a84 + 624: e2890004 add r0, r9, #4 ; 0x4 + 628: e59a100c ldr r1, [sl, #12] + 62c: ebcb1914 bl 0xff2c6a84 + 630: e2890008 add r0, r9, #8 ; 0x8 + 634: e59a1010 ldr r1, [sl, #16] + 638: ebcb1911 bl 0xff2c6a84 + 63c: e289000c add r0, r9, #12 ; 0xc + 640: e59a1014 ldr r1, [sl, #20] + 644: ebcb190e bl 0xff2c6a84 + 648: e2890010 add r0, r9, #16 ; 0x10 + 64c: e1a01005 mov r1, r5 + 650: ebcb190b bl 0xff2c6a84 + 654: e2890014 add r0, r9, #20 ; 0x14 + 658: e59a101c ldr r1, [sl, #28] + 65c: ebcb1908 bl 0xff2c6a84 + 660: e2890018 add r0, r9, #24 ; 0x18 + 664: e59a1020 ldr r1, [sl, #32] + 668: ebcb1905 bl 0xff2c6a84 + 66c: e289001c add r0, r9, #28 ; 0x1c + 670: e1a01006 mov r1, r6 + 674: e3a02ec2 mov r2, #3104 ; 0xc20 + 678: ebcb18e9 bl 0xff2c6a24 + + 67c: e3a00ec2 mov r0, #3104 ; 0xc20 + 680: ebcb195e bl step_debug + 684: e24cc012 sub ip, ip, #18 ; 0x12 + 688: e128f00b msr CPSR_f, fp + 68c: aa000007 bge 0x6b0 + 690: 5a000002 bpl 0x6a0 + 694: e3a00f05 mov r0, #20 ; 0x14 + 698: e3800b03 orr r0, r0, #3072 ; 0xc00 + 69c: ebcb172e bl 0xff2c635c + 6a0: eaffffab b 0x554 + +6a4: e3a00f09 mov r0, #36 ; 0x24 + 6a8: e3800b03 orr r0, r0, #3072 ; 0xc00 + 6ac: ebcb1953 bl step_debug + 6b0: e59a9034 ldr r9, [sl, #52] + 6b4: e59a0034 ldr r0, [sl, #52] + 6b8: e2800020 add r0, r0, #32 ; 0x20 + 6bc: e58a0034 str r0, [sl, #52] + 6c0: e3c99003 bic r9, r9, #3 ; 0x3 + 6c4: e2890000 add r0, r9, #0 ; 0x0 + 6c8: ebcb193e bl 0xff2c6bc8 + 6cc: e58a0010 str r0, [sl, #16] + 6d0: e2890004 add r0, r9, #4 ; 0x4 + 6d4: ebcb193b bl 0xff2c6bc8 + 6d8: e58a0014 str r0, [sl, #20] + 6dc: e2890008 add r0, r9, #8 ; 0x8 + 6e0: ebcb1938 bl 0xff2c6bc8 + 6e4: e1a05000 mov r5, r0 + 6e8: e289000c add r0, r9, #12 ; 0xc + 6ec: ebcb1935 bl 0xff2c6bc8 + 6f0: e58a001c str r0, [sl, #28] + 6f4: e2890010 add r0, r9, #16 ; 0x10 + 6f8: ebcb1932 bl 0xff2c6bc8 + 6fc: e58a0020 str r0, [sl, #32] + 700: e2890014 add r0, r9, #20 ; 0x14 + 704: ebcb192f bl 0xff2c6bc8 + 708: e1a06000 mov r6, r0 + 70c: e2890018 add r0, r9, #24 ; 0x18 + 710: ebcb192c bl 0xff2c6bc8 + 714: e58a0028 str r0, [sl, #40] + 718: e289001c add r0, r9, #28 ; 0x1c + 71c: ebcb1929 bl 0xff2c6bc8 + 720: e1a08000 mov r8, r0 + +724: e3a00f0a mov r0, #40 ; 0x28 + 728: e3800b03 orr r0, r0, #3072 ; 0xc00 + 72c: ebcb1933 bl step_debug + 730: e1a00008 mov r0, r8 + 734: e24cc00a sub ip, ip, #10 ; 0xa + 738: eacb1751 b 0xff2c6484 diff --git a/gp2x/cmdline.c b/gp2x/cmdline.c new file mode 100644 index 0000000..6b50e17 --- /dev/null +++ b/gp2x/cmdline.c @@ -0,0 +1,256 @@ + +/* commandline.c for GP2X Version 2.0 + Copyright (C) 2006 god_at_hell + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include +#include +#include +#include "cpuctrl.h" +#include "gp2xminilib.h" +#include "cpuctrl.h" + + +void fallback(int argc, char *argv[]) +{ + //beginning commandline-utilizing + if (argc == 3) + { + if (atoi(argv[1]) == 0) + { + if(atoi(argv[2]) > 36){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -20){gp2x_deinit();exit(1);} + set_add_FLCDCLK(atoi(argv[2])); + } + else + { + if(atoi(argv[2]) > 10){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -5){gp2x_deinit();exit(1);} + set_add_ULCDCLK(atoi(argv[2])); + } + } + + if (argc == 4) + { + if(atoi(argv[3]) > 320){gp2x_deinit();exit(1);} + if(atoi(argv[3]) < 33){gp2x_deinit();exit(1);} + if (atoi(argv[1]) == 0) + { + if(atoi(argv[2]) > 36){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -20){gp2x_deinit();exit(1);} + set_add_FLCDCLK(atoi(argv[2])); + } + else + { + if(atoi(argv[2]) > 10){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -5){gp2x_deinit();exit(1);} + set_add_ULCDCLK(atoi(argv[2])); + } + set_FCLK(atoi(argv[3])); + } + + if (argc == 5) + { + if(atoi(argv[3]) > 320){gp2x_deinit();exit(1);} + if(atoi(argv[3]) < 33){gp2x_deinit();exit(1);} + if(atof(argv[4]) > 10){gp2x_deinit();exit(1);} + if(atof(argv[4]) < 0.02){gp2x_deinit();exit(1);} + if (atoi(argv[1]) == 0) + { + if(atoi(argv[2]) > 36){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -20){gp2x_deinit();exit(1);} + set_add_FLCDCLK(atoi(argv[2])); + } + else + { + if(atoi(argv[2]) > 10){gp2x_deinit();exit(1);} + if(atoi(argv[2]) < -5){gp2x_deinit();exit(1);} + set_add_ULCDCLK(atoi(argv[2])); + } + set_FCLK(atoi(argv[3])); + set_gamma(atof(argv[4])); + } +} + +void cmdhelp() +{ + printf ("\ngpSP2X v0.9003 Beta by Exophase/ZodTTD\r\n"); + printf ("cpu_speed by god_at_hell\r\n"); + printf ("Usage: cpu_speed.gpe [option1] [value1] [option2]...\r\n"); + printf ("Options:\r\n"); + printf (" RAM-Options\r\n"); + printf (" -----------\r\n"); + printf (" --cas CAS Latency. Delay in clock cycles between the registration \n\t\tof a READ command and the first bit of output data. \n\t\tValid values are 2 and 3 cycles.\r\n"); + printf (" --trc ACTIVE to ACTIVE /AUTOREFRESH command delay. Defines ACTIVE \n\t\tto ACTIVE/auto refresh command period delay. \n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --tras ACTIVE to PRECHARGE delay. Defines the delay between the ACTIVE \n\t\tand PRECHARGE commands. \n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --twr Write recovery time in cycles.\n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --tmrd LOAD MODE REGISTER command cycle time.\n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --trfc AUTO REFRESH command period in cycles.\n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --trp PRECHARGE command period in cycles.\n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --trcd RAS to CAS Delay in cycles.\n\t\tValid values are from 1 to 16 cycles.\r\n"); + printf (" --refperd Refresh Period. Defines maximum time period between \n\t\tAUTOREFRESH commands.\n\t\tValid values are from 1 to 65535 (default ~ 250) cycles.\r\n"); + printf (" --ramdiv Divider for the Memory-Clock which is 1/2 of the CPU-Clock. \n\t\tValid values are from 1 to 8.\r\n"); + printf ("\n CPU-Options\r\n"); + printf (" -----------\r\n"); + printf (" --cpuclk Sets the CPU-Frequency in Mhz. \n\t\tValid values are from 33 to 340.\r\n"); + printf (" --cpudiv Divider for the CPU-Clock. \n\t\tValid values are from 1 to 8.\r\n"); + printf ("\n Display-Options\r\n"); + printf ("----------------\r\n"); + printf (" --fpll Sets clockgenerator to fpll (for firmware 1.0 - 1.0.1).\r\n"); + printf (" --upll Sets clockgenerator to upll (for the rest).\r\n"); + printf (" --timing Timing Prescaler to eliminate flickering. \n\t\tValid values are: -20 to 36 with fpll.\n\t\t\t\t -6 to 10 with upll.\r\n"); + printf (" --gamma Regulates the gamma. \n\t\tValid values are from 0.0001 to 15.0000.\r\n"); + printf ("\n Daemon-Mode \r\n"); + printf ("----------------\r\n"); + printf ("Usage: cpu_speed.gpe --daemon [option1] [value1] [option2]...\r\n"); + printf ("Shutdown: cpu_speed.gpe --kill[-daemon]\r\n"); + printf ("Options:\r\n"); + printf (" --min Sets the minimum CPU-Frequency in Mhz. \n\t\tValid values are from 33 to 340.\r\n"); + printf (" --max Sets the maximum CPU-Frequency in Mhz. \n\t\tValid values are from 33 to 340.\r\n"); + printf (" --start Sets the CPU-Frequency in Mhz. \n\t\tValid values are from 33 to 340.\r\n"); + printf (" --step Sets the CPU-Frequency step in Mhz. \n\t\tValid values are from 1 to 340.\r\n"); + printf (" --hotkey Sets the hotkey. (Default: LR) \n\t\tValid values are a combination of LRXYZAB+-S/@ or ``None''\n\t\t (+- are volume, S is Start, / is Select, @ is Stick).\r\n"); + printf (" --incr Sets the increment key. (Default: +) \n\t\tValid values are a combination of LRXYZAB+-S/@ or ``None''\n\t\t (+- are volume, S is Start, / is Select, @ is Stick).\r\n"); + printf (" --decr Sets the decrement key. (Default: -) \n\t\tValid values are a combination of LRXYZAB+-S/@ or ``None''\n\t\t (+- are volume, S is Start, / is Select, @ is Stick).\r\n"); + printf (" --no-hotkey Alias for --hotkey None.\r\n"); + printf (" --no-incr Alias for --incr None.\r\n"); + printf (" --no-decr Alias for --decr None.\r\n"); + printf (" --foreground Do not switch to daemon mode. (Useful for debugging)\r\n"); + printf (" --background Switch to daemon mode. (Default)\r\n"); + printf (" --display Enable on screen display. COMING SOON!\r\n"); + printf (" --no-display Disable on screen display.\r\n"); + printf ("\nNOTE:\nThe old commandline-settings are working ... read more about this in the readme\n\n"); +} + +void cmdline(int argc, char *argv[]) +{ + short i,n; + short varis = 11; + char clockgen = get_Clkgen(); + char var[11][9]={"--cas","--trc","--tras","--twr","--tmrd","--trfc","--trp","--trcd","--ramdiv","--cpuclk","--cpudiv"}; + + short val[varis]; + for(n=0;n -21) + { + if(timing < 37) set_add_FLCDCLK(timing); + } + else set_add_FLCDCLK(get_LCDClk(clockgen)); + } + if(clockgen == 1) + { + if(timing > -7) + { + if(timing < 11) set_add_ULCDCLK(timing); + } + else set_add_ULCDCLK(get_LCDClk(clockgen)); + } + if(refperd-1 > -1) + { + if(refperd-1 < 0xffff) set_REFPERD(refperd-1); + } + if(gamma > 0.) + { + if(gamma < 15.) set_gamma(gamma); + } + if(val[0]-2 > -1) + { + if(val[0]-2 < 2) set_CAS(val[0]-2); + } + if(val[1]-1 > -1) + { + if(val[1]-1 < 16) set_tRC(val[1]-1); + } + if(val[2]-1 > -1) + { + if(val[2]-1 < 16) set_tRAS(val[2]-1); + } + if(val[3]-1 > -1) + { + if(val[3]-1 < 16) set_tWR(val[3]-1); + } + if(val[4]-1 > -1) + { + if(val[4]-1 < 16) set_tMRD(val[4]-1); + } + if(val[5]-1 > -1) + { + if(val[5]-1 < 16) set_tRFC(val[5]-1); + } + if(val[6]-1 > -1) + { + if(val[6] < 16) set_tRP(val[6]-1); + } + if(val[7]-1 > -1) + { + if(val[7]-1 < 16) set_tRCD(val[7]-1); + } + if(val[8]-1 > -1) + { + if(val[8]-1 < 8) set_DCLK_Div(val[8]-1); + } + if(val[9] > 32) + { + if(val[9] < 341) set_FCLK(val[9]); + } + if(val[10]-1 > -1) + { + if(val[10]-1 < 8) set_920_Div(val[10]-1); + } +} diff --git a/gp2x/cmdline.h b/gp2x/cmdline.h new file mode 100644 index 0000000..e80b968 --- /dev/null +++ b/gp2x/cmdline.h @@ -0,0 +1,3 @@ +void fallback(int argc, char *argv[]); +void cmdhelp(); +void cmdline(int argc, char *argv[]); diff --git a/gp2x/cpu_speed.c b/gp2x/cpu_speed.c new file mode 100644 index 0000000..519a2f6 --- /dev/null +++ b/gp2x/cpu_speed.c @@ -0,0 +1,1276 @@ + +/* CPU/LCD/RAM-Tuner for GP2X Version 2.0 + Copyright (C) 2006 god_at_hell + original CPU-Overclocker (c) by Hermes/PS2Reality + the gamma-routine was provided by theoddbot + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "display.h" +#include "cpuctrl.h" +#include "gp2xminilib.h" +#include "speedtest.h" +#include "cmdline.h" +#include "daemon.h" + +int cpuspeed_exit = 0; + +unsigned COLORFONDO=0xB00000; // background-color +unsigned WHITE=0xFFFFFF; +unsigned TEXTBACK=0x0000B0; + +unsigned gp2x_nKeys=0; +int oldtime=0; +char pageshift; +short menupoint; +unsigned char cad[256]; +short cpusettings[2],dispsettings[3],ramsettings[10]; +extern int daemonsettings[8]; +extern unsigned MDIV,PDIV,SCALE; + +void cleardisp() +{ + ClearScreen(COLORFONDO); + sprintf(cad,"gpSP2X v0.9008 with CPU_SPEED"); + v_putcad(1,1,WHITE,COLORFONDO,cad); + v_putcad(28,5,WHITE,COLORFONDO,"Item Help"); + v_putcad(2,26,WHITE,COLORFONDO,"Start:Quit Stick:UP/DOWN"); + + DrawBox(WHITE); +} + +void itemhelp(char item[]) +{ + if(strcmp(item, "menu") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Enter submenu"); + v_putcad(26,9,0xffffff,COLORFONDO,"with B."); + } + if(strcmp(item, "cpuclk") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"clockspeed"); + v_putcad(26,10,0xffffff,COLORFONDO,"with R/L or"); + v_putcad(26,11,0xffffff,COLORFONDO,"Vol UP/Down."); + v_putcad(26,13,0xffffff,COLORFONDO,"Valid speeds"); + v_putcad(26,14,0xffffff,COLORFONDO,"are:"); + v_putcad(26,15,0xffffff,COLORFONDO,"33 to 340Mhz"); + } + if(strcmp(item, "cpudiv") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"The CPU-clock"); + v_putcad(26,12,0xffffff,COLORFONDO,"will be"); + v_putcad(26,13,0xffffff,COLORFONDO,"divided by"); + v_putcad(26,14,0xffffff,COLORFONDO,"this value."); + v_putcad(26,16,0xffffff,COLORFONDO,"Valid values"); + v_putcad(26,17,0xffffff,COLORFONDO,"are from"); + v_putcad(26,18,0xffffff,COLORFONDO,"1 to 8"); + } + if(strcmp(item, "test") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"The test"); + v_putcad(26,12,0xffffff,COLORFONDO,"checks how"); + v_putcad(26,13,0xffffff,COLORFONDO,"high you can"); + v_putcad(26,14,0xffffff,COLORFONDO,"clock the"); + v_putcad(26,15,0xffffff,COLORFONDO,"CPU."); + v_putcad(26,17,0xffffff,COLORFONDO,"Check the"); + v_putcad(26,18,0xffffff,COLORFONDO,"Readme for"); + v_putcad(26,19,0xffffff,COLORFONDO,"more infos."); + } + if(strcmp(item, "gotest") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Start the"); + v_putcad(26,9,0xffffff,COLORFONDO,"test with B."); + } + if(strcmp(item, "clockgen") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change the"); + v_putcad(26,9,0xffffff,COLORFONDO,"clockgen with"); + v_putcad(26,10,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,12,0xffffff,COLORFONDO,"FPLL is for"); + v_putcad(26,13,0xffffff,COLORFONDO,"FW 1.0"); + v_putcad(26,14,0xffffff,COLORFONDO,"UPLL for the"); + v_putcad(26,15,0xffffff,COLORFONDO,"rest."); + } + if(strcmp(item, "timing") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose the"); + v_putcad(26,9,0xffffff,COLORFONDO,"LCD-Timing"); + v_putcad(26,10,0xffffff,COLORFONDO,"with R/L."); + v_putcad(26,12,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,13,0xffffff,COLORFONDO,"values from"); + v_putcad(26,14,0xffffff,COLORFONDO,"-20 to 36"); + v_putcad(26,15,0xffffff,COLORFONDO,"for FPLL"); + v_putcad(26,16,0xffffff,COLORFONDO,"and -6 to 10"); + v_putcad(26,17,0xffffff,COLORFONDO,"for UPLL"); + } + if(strcmp(item, "gamma") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change gamma"); + v_putcad(26,9,0xffffff,COLORFONDO,"with R/L or"); + v_putcad(26,10,0xffffff,COLORFONDO,"Vol UP/DOWN"); + v_putcad(26,12,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,13,0xffffff,COLORFONDO,"values from"); + v_putcad(26,14,0xffffff,COLORFONDO,"0.01 to 10.00"); + } + if(strcmp(item, "CAS") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose the"); + v_putcad(26,9,0xffffff,COLORFONDO,"CAS Latency"); + v_putcad(26,10,0xffffff,COLORFONDO,"with R/L"); + v_putcad(26,12,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,13,0xffffff,COLORFONDO,"2 or 3 cycles"); + v_putcad(26,15,0xffffff,COLORFONDO,"Delay between"); + v_putcad(26,16,0xffffff,COLORFONDO,"registration"); + v_putcad(26,17,0xffffff,COLORFONDO,"of a READ"); + v_putcad(26,18,0xffffff,COLORFONDO,"command and"); + v_putcad(26,19,0xffffff,COLORFONDO,"outputdata."); + v_putcad(27,21,0x0000DD,COLORFONDO,"!INSTABLE!"); + } + if(strcmp(item, "tRC") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"ACTIVE to"); + v_putcad(26,16,0xffffff,COLORFONDO,"ACTIVE/"); + v_putcad(26,17,0xffffff,COLORFONDO,"AUTOREFRESH"); + v_putcad(26,18,0xffffff,COLORFONDO,"command"); + v_putcad(26,19,0xffffff,COLORFONDO,"period delay."); + } + if(strcmp(item, "tRAS") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"Delay between"); + v_putcad(26,16,0xffffff,COLORFONDO,"the ACTIVE"); + v_putcad(26,17,0xffffff,COLORFONDO,"and PRECHARGE"); + v_putcad(26,18,0xffffff,COLORFONDO,"commands."); + } + if(strcmp(item, "tWR") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"Write"); + v_putcad(26,16,0xffffff,COLORFONDO,"recovery time"); + v_putcad(26,17,0xffffff,COLORFONDO,"in cycles."); + } + if(strcmp(item, "tMRD") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"LOAD MODE"); + v_putcad(26,16,0xffffff,COLORFONDO,"REGISTER"); + v_putcad(26,17,0xffffff,COLORFONDO,"command cycle"); + v_putcad(26,18,0xffffff,COLORFONDO,"time."); + } + if(strcmp(item, "tRFC") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"AUTOREFRESH"); + v_putcad(26,16,0xffffff,COLORFONDO,"command"); + v_putcad(26,17,0xffffff,COLORFONDO,"period."); + } + if(strcmp(item, "tRP") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"PRECHARGE"); + v_putcad(26,16,0xffffff,COLORFONDO,"command"); + v_putcad(26,17,0xffffff,COLORFONDO,"period."); + } + if(strcmp(item, "tRCD") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Change with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,12,0xffffff,COLORFONDO,"1 to 16"); + v_putcad(26,13,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,15,0xffffff,COLORFONDO,"RAS to CAS"); + v_putcad(26,16,0xffffff,COLORFONDO,"Delay in"); + v_putcad(26,17,0xffffff,COLORFONDO,"cycles."); + } + if(strcmp(item, "REFPERD") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose the"); + v_putcad(26,9,0xffffff,COLORFONDO,"RAM Refresh"); + v_putcad(26,9,0xffffff,COLORFONDO,"Period"); + v_putcad(26,10,0xffffff,COLORFONDO,"with R/L"); + v_putcad(26,12,0xffffff,COLORFONDO,"Valid are"); + v_putcad(26,13,0xffffff,COLORFONDO,"1 to 65535 "); + v_putcad(26,14,0xffffff,COLORFONDO,"cycles."); + v_putcad(26,16,0xffffff,COLORFONDO,"Max. cycles"); + v_putcad(26,17,0xffffff,COLORFONDO,"between"); + v_putcad(26,18,0xffffff,COLORFONDO,"AUTOREFRESH"); + v_putcad(26,19,0xffffff,COLORFONDO,"commands."); + v_putcad(26,21,0xFFFF,COLORFONDO,"Default ~250"); + } + if(strcmp(item, "DCLK_Div") == 0) + { + v_putcad(26,8,0xffffff,COLORFONDO,"Choose with"); + v_putcad(26,9,0xffffff,COLORFONDO,"R/L."); + v_putcad(26,11,0xffffff,COLORFONDO,"The CPU-clock"); + v_putcad(26,12,0xffffff,COLORFONDO,"will be"); + v_putcad(26,13,0xffffff,COLORFONDO,"divided by"); + v_putcad(26,14,0xffffff,COLORFONDO,"this value."); + v_putcad(26,15,0xffffff,COLORFONDO,"Valid values"); + v_putcad(26,17,0xffffff,COLORFONDO,"are from"); + v_putcad(26,18,0xffffff,COLORFONDO,"1 to 8"); + v_putcad(26,20,0xffffff,COLORFONDO,"RAM-Clock ="); + v_putcad(26,21,0xffffff,COLORFONDO,"CPU-Clock / 2"); + } +} + +short cpumenu() +{ + unsigned sysfreq=0, cpufreq, cpu_div; + + short test = 1; + + if(cpusettings[0] == -1) + { + //get the setted values from system + cpu_div = get_920_Div(); + sysfreq=get_freq_920_CLK(); + sysfreq*=cpu_div+1; + cpufreq=sysfreq/1000000; + } + else + { + //use old settings + cpufreq = cpusettings[0]; + cpu_div = cpusettings[1]; + } + + menupoint = 0; + + do + { + cleardisp(); + + //cpu menu + v_putcad(12,2,WHITE,COLORFONDO,"CPU Clock Setup"); + sprintf(cad,"CPU Frequency = %uMhz",cpufreq); + if(menupoint==0){v_putcad(2,5,0xffffff,TEXTBACK,cad);itemhelp("cpuclk");} + else v_putcad(2,5,0xffff,COLORFONDO,cad); + sprintf(cad,"CPU Divider: %u",cpu_div+1); + if(menupoint==1){v_putcad(2,7,0xffffff,TEXTBACK,cad);itemhelp("cpudiv");} + else v_putcad(2,7,0xffff,COLORFONDO,cad); + v_putcad(2,12,0xffff00,COLORFONDO,"CPU Speedtest"); + if(test==0) sprintf(cad,"Test 2: Primnumber"); + if(test==1) sprintf(cad,"Test 1: Walking Ant"); + if(menupoint==2){v_putcad(2,15,0xffffff,TEXTBACK,cad);itemhelp("test");} + else v_putcad(2,15,0xffff,COLORFONDO,cad); + if(menupoint==3){v_putcad(8,17,0xffffff,TEXTBACK,"GO!!!");itemhelp("gotest");} + else v_putcad(8,17,0xffff,COLORFONDO,"GO!!!"); + + gp2x_video_flip(); + + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + + if((gp2x_nKeys & GP2X_START)) + { + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + cpusettings[0] = cpufreq; + cpusettings[1] = cpu_div; + return 0; + } + + if((gp2x_nKeys & GP2X_DOWN)) + { + menupoint++; + if(menupoint>3) menupoint=0; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_UP)) + { + menupoint--; + if(menupoint<0) menupoint=3; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_R)) + { + if (menupoint == 0) + { + cpufreq+=10; + if (cpufreq > 340) cpufreq = 33; + } + if (menupoint == 1) + { + cpu_div++; + if (cpu_div == 8) cpu_div = 0; + } + if (menupoint == 2) + { + test++; + if (test == 2) test = 0; + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_L)) + { + if (menupoint == 0) + { + cpufreq-=10; + if (cpufreq < 33) cpufreq = 340; + } + if (menupoint == 1) + { + cpu_div--; + if (cpu_div == -1) cpu_div = 7; + } + if (menupoint == 2) + { + cpu_div--; + if (cpu_div == -1) cpu_div = 1; + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_VOL_DOWN)) + { + if (menupoint == 0) + { + cpufreq++; + if (cpufreq == 340) cpufreq = 33; + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_VOL_UP)) + { + if (menupoint == 0) + { + cpufreq--; + if (cpufreq == 32) cpufreq = 340; + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_B)) + { + if (menupoint == 3) speedtest(test); + delay_us(200000); + break; + } + } + } + while(1); +} + +short lcdmenu() +{ + short clockgen, LCDClk; + float gamma; + + if(dispsettings[0] == -1) + { + //get the setted values from system + clockgen = get_Clkgen(); + LCDClk = get_LCDClk(clockgen); + gamma = 1.0; + } + else + { + //use old settings + clockgen = dispsettings[0]; + LCDClk = dispsettings[1]; + gamma = dispsettings[2]/100; + } + + menupoint = 0; + + do + { + cleardisp(); + + //display menu + v_putcad(9,2,WHITE,COLORFONDO,"Display Setting Setup"); + if (clockgen == 0) + { + sprintf(cad,"Clockgen = FPLL"); + if(menupoint==0){v_putcad(2,5,0xffffff,TEXTBACK,cad);itemhelp("clockgen");} + else v_putcad(2,5,0xffff,COLORFONDO,cad); + } + else + { + sprintf(cad,"Clockgen = UPLL"); + if(menupoint==0){v_putcad(2,5,0xffffff,TEXTBACK,cad);itemhelp("clockgen");} + else v_putcad(2,5,0xffff,COLORFONDO,cad); + } + sprintf(cad,"Timing: %i",LCDClk); + if(menupoint==1){v_putcad(2,7,0xffffff,TEXTBACK,cad);itemhelp("timing");} + else v_putcad(2,7,0xffff,COLORFONDO,cad); + sprintf(cad,"Gamma: %.2f",gamma); + if(menupoint==2){v_putcad(2,9,0xffffff,TEXTBACK,cad);itemhelp("gamma");} + else v_putcad(2,9,0xffff,COLORFONDO,cad); + + gp2x_video_flip(); + + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + + if((gp2x_nKeys & GP2X_START)) + { + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + dispsettings[0] = clockgen; + dispsettings[1] = LCDClk; + dispsettings[2] = (int)(gamma*100); + return 0; + } + + if((gp2x_nKeys & GP2X_DOWN)) + { + menupoint++; + if(menupoint>2) menupoint=0; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_UP)) + { + menupoint--; + if(menupoint<0) menupoint=2; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_R)) + { + if (menupoint == 0) + { + clockgen++; + if (clockgen == 2) clockgen = 0; + } + if (menupoint == 1) + { + LCDClk++; + if (clockgen == 0) + { + if (LCDClk == 37) LCDClk = -20; + set_add_FLCDCLK(LCDClk); + } + else + { + if (LCDClk == 11) LCDClk = -6; + set_add_ULCDCLK(LCDClk); + } + } + if (menupoint == 2) + { + gamma += 0.2; + if (gamma > 10) gamma = 0.2; + set_gamma(gamma); + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_L)) + { + if (menupoint == 0) + { + clockgen--; + if (clockgen == -1) clockgen = 1; + } + if (menupoint == 1) + { + LCDClk--; + if(clockgen == 0) + { + if (LCDClk == -21) LCDClk = 36; + set_add_FLCDCLK(LCDClk); + } + else + { + if (LCDClk == -7) LCDClk = 10; + set_add_ULCDCLK(LCDClk); + } + } + if (menupoint == 2) + { + gamma -= 0.2; + if (gamma < 0.01) gamma = 10; + set_gamma(gamma); + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_VOL_DOWN)) + { + if (menupoint == 2) + { + gamma += 0.01; + if (gamma > 10) gamma = 0.01; + set_gamma(gamma); + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_VOL_UP)) + { + if (menupoint == 2) + { + gamma -= 0.01; + if (gamma < 0.01) gamma = 10; + set_gamma(gamma); + } + delay_us(200000); + break; + } + } + } + while(1); +} + +short rammenu() +{ + short CAS,tRC,tRAS,tWR,tMRD,tRFC,tRP,tRCD,DCLK_Div; + int REFPERD; + + if(ramsettings[0] == -1) + { + //get the setted values from system + CAS = get_CAS(); + tRC = get_tRC(); + tRAS = get_tRAS(); + tWR = get_tWR(); + tMRD = get_tMRD(); + tRFC = get_tRFC(); + tRP = get_tRP(); + tRCD = get_tRCD(); + REFPERD = get_REFPERD(); + DCLK_Div = get_DCLK_Div(); + } + else + { + //use old settings + CAS = ramsettings[0]; + tRC = ramsettings[1]; + tRAS = ramsettings[2]; + tWR = ramsettings[3]; + tMRD = ramsettings[4]; + tRFC = ramsettings[5]; + tRP = ramsettings[6]; + tRCD = ramsettings[7]; + REFPERD = ramsettings[8]; + DCLK_Div = ramsettings[9]; + } + + pageshift = 0; + menupoint = 0; + + do + { + cleardisp(); + + //ram menu + v_putcad(11,2,WHITE,COLORFONDO,"RAM Setting Setup"); + if(pageshift == 0) + { + sprintf(cad,"CAS: %u",CAS+2); + if(menupoint==0){v_putcad(2,5,0xffffff,TEXTBACK,cad);itemhelp("CAS");} + else v_putcad(2,5,0xffff,COLORFONDO,cad); + } + else v_putcad(13,5,0xffff,COLORFONDO,"^"); + sprintf(cad,"tRC: %u",tRC+1); + if(menupoint==1){v_putcad(2,7-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tRC");} + else v_putcad(2,7-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tRAS: %u",tRAS+1); + if(menupoint==2){v_putcad(2,9-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tRAS");} + else v_putcad(2,9-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tWR: %u",tWR+1); + if(menupoint==3){v_putcad(2,11-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tWR");} + else v_putcad(2,11-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tMRD: %u",tMRD+1); + if(menupoint==4){v_putcad(2,13-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tMRD");} + else v_putcad(2,13-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tRFC: %u",tRFC+1); + if(menupoint==5){v_putcad(2,15-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tRFC");} + else v_putcad(2,15-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tRP: %u",tRP+1); + if(menupoint==6){v_putcad(2,17-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tRP");} + else v_putcad(2,17-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"tRCD: %u",tRCD+1); + if(menupoint==7){v_putcad(2,19-pageshift,0xffffff,TEXTBACK,cad);itemhelp("tRCD");} + else v_putcad(2,19-pageshift,0xffff,COLORFONDO,cad); + sprintf(cad,"Refresh Period: %u",REFPERD+1); + if(menupoint==8){v_putcad(2,21-pageshift,0xffffff,TEXTBACK,cad);itemhelp("REFPERD");} + else v_putcad(2,21-pageshift,0xffff,COLORFONDO,cad); + if(pageshift == 1) + { + sprintf(cad,"RAM Divider: %u",DCLK_Div+1); + if(menupoint==9){v_putcad(2,23,0xffffff,TEXTBACK,cad);itemhelp("DCLK_Div");} + else v_putcad(2,23,0xffff,COLORFONDO,cad); + } + else v_putcad(13,23,0xffff,COLORFONDO,"v"); + + + gp2x_video_flip(); + + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + + if((gp2x_nKeys & GP2X_START)) + { + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + ramsettings[0] = CAS; + ramsettings[1] = tRC; + ramsettings[2] = tRAS; + ramsettings[3] = tWR; + ramsettings[4] = tMRD; + ramsettings[5] = tRFC; + ramsettings[6] = tRP; + ramsettings[7] = tRCD; + ramsettings[8] = REFPERD; + ramsettings[9] = DCLK_Div; + return 0; + } + + if((gp2x_nKeys & GP2X_DOWN)) + { + menupoint++; + if(menupoint==9) pageshift = 1; + if(menupoint>9) {menupoint=0; pageshift = 0;} + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_UP)) + { + menupoint--; + if(menupoint==0) pageshift = 0; + if(menupoint<0) { menupoint=9; pageshift = 1;} + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_R)) + { + if (menupoint == 0) + { + CAS++; + if (CAS == 2) CAS = 0; + } + if (menupoint == 1) + { + tRC++; + if (tRC == 16) tRC = 0; + } + if (menupoint == 2) + { + tRAS++; + if (tRAS == 16) tRAS = 0; + } + if (menupoint == 3) + { + tWR++; + if (tWR == 16) tWR = 0; + } + if (menupoint == 4) + { + tMRD++; + if (tMRD == 16) tMRD = 0; + } + if (menupoint == 5) + { + tRFC++; + if (tRFC == 16) tRFC = 0; + } + if (menupoint == 6) + { + tRP++; + if (tRP == 16) tRP = 0; + } + if (menupoint == 7) + { + tRCD++; + if (tRCD == 16) tRCD = 0; + } + if (menupoint == 8) + { + REFPERD += 10; + if (REFPERD == 0xffff) REFPERD = 0; + } + if (menupoint == 9) + { + DCLK_Div++; + if (DCLK_Div == 8) DCLK_Div = 0; + } + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_L)) + { + if (menupoint == 0) + { + CAS--; + if (CAS == -1) CAS = 1; + } + if (menupoint == 1) + { + tRC--; + if (tRC == -1) tRC = 15; + } + if (menupoint == 2) + { + tRAS--; + if (tRAS == -1) tRAS = 15; + } + if (menupoint == 3) + { + tWR--; + if (tWR == -1) tWR = 15; + } + if (menupoint == 4) + { + tMRD--; + if (tMRD == -1) tMRD = 15; + } + if (menupoint == 5) + { + tRFC--; + if (tRFC == -1) tRFC = 15; + } + if (menupoint == 6) + { + tRP--; + if (tRP == -1) tRP = 15; + } + if (menupoint == 7) + { + tRCD--; + if (tRCD == -1) tRCD = 15; + } + if (menupoint == 8) + { + REFPERD -= 10; + if (REFPERD == -1) REFPERD = 0xfffe; + } + if (menupoint == 9) + { + DCLK_Div--; + if (DCLK_Div == -1) DCLK_Div = 7; + } + delay_us(200000); + break; + } + } + } + while(1); +} + +int exit_cpu_speed(char* runfile) +{ + gp2x_deinit(); + cpuspeed_exit = 1; +#if 0 + system("sync"); + if(strcmp(runfile, "gp2xmenu") == 0) chdir("/usr/gp2x"); + execl(runfile,NULL); + exit(0); +#endif +} + +/****************************************************************************************************************************************/ +// MAIN +/****************************************************************************************************************************************/ + +int main_cpuspeed(int argc, char *argv[]) +{ + unsigned sysfreq=0; + int cpufreq, n; + short run = 0; + int start_daemon = 0; + short mainmenupoint = 0; + ramsettings[0] = -1; + ramsettings[1] = -1; + ramsettings[2] = -1; + ramsettings[3] = -1; + ramsettings[4] = -1; + ramsettings[5] = -1; + ramsettings[6] = -1; + ramsettings[7] = -1; + ramsettings[8] = -1; + ramsettings[9] = -1; + dispsettings[0] = -1; + dispsettings[1] = -100; + dispsettings[2] = -1; + cpusettings[0] = -1; + cpusettings[1] = -1; + daemonsettings[0] = -1; + daemonsettings[1] = 260; + daemonsettings[2] = 5; + daemonsettings[3] = 5; + daemonsettings[4] = GP2X_L | GP2X_R; + daemonsettings[5] = GP2X_VOL_DOWN; + daemonsettings[6] = GP2X_VOL_UP; + daemonsettings[7] = 1; + + char *runfile; + + FILE *settings; + char sets[41][40]; + char* comps[25] = { + "CPU-Clock\n","CPU-Div\n","FPLL\n","UPLL\n","Gamma\n","CAS\n","tRC\n", + "tRAS\n","tWR\n","tMRD\n","tRFC\n","tRP\n","tRCD\n","Refresh-Period\n","RAM-Div\n","Run\n", + "Daemon-Min\n","Daemon-Max\n","Daemon-Step\n","Daemon-Delay\n","Daemon-Hotkey\n","Daemon-Incr-Key\n","Daemon-Decr-Key\n", + "Daemon-OSD\n","Daemon-Run\n" + }; + + gp2x_init(16,44100,16,1,50); + cpuctrl_init(); // ATENCION: si no se hace esto, cuelgue seguro (aprovecho la definicion de rlyeh y debe ir despues de gp2x_init) + + settings = fopen ("./cpu_speed.cfg", "r"); + + if (settings == NULL) + { + printf("No file found\n"); + } + else + { + char *ReturnCode; + for(n=0; n<40; n++) + { + ReturnCode = fgets(sets[n],40,settings); + if (ReturnCode == NULL) + { + sets[40][0] = (char)n; + break; + } + } + + for(n=0; n<(int)sets[40][0]; n=n+2) + { + if(strcmp(sets[n],comps[0]) == 0) + { + if(atoi(sets[n+1]) > 33) + if(atoi(sets[n+1]) < 341) + cpusettings[0] = atoi(sets[n+1]); + } + if(strcmp(sets[n],comps[1]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 9) + cpusettings[1] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[2]) == 0) + { + if(atoi(sets[n+1]) > -21) + if(atoi(sets[n+1]) < 37) + dispsettings[0] = 0; + dispsettings[1] = atoi(sets[n+1]); + + } + if(strcmp(sets[n],comps[3]) == 0) + { + if(atoi(sets[n+1]) > -7) + if(atoi(sets[n+1]) < 11) + dispsettings[0] = 1; + dispsettings[1] = atoi(sets[n+1]); + } + if(strcmp(sets[n],comps[4]) == 0) + { + if(atof(sets[n+1]) > 0) + if(atof(sets[n+1]) <= 10) + dispsettings[2] = (int)(atof(sets[n+1])*100); + } + if(strcmp(sets[n],comps[5]) == 0) + { + if(atoi(sets[n+1]) > 1) + if(atoi(sets[n+1]) < 4) + ramsettings[0] = atoi(sets[n+1])-2; + } + if(strcmp(sets[n],comps[6]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[1] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[7]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[2] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[8]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[3] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[9]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[4] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[10]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[5] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[11]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[6] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[12]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 17) + ramsettings[7] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[13]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 65536) + ramsettings[8] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[14]) == 0) + { + if(atoi(sets[n+1]) > 0) + if(atoi(sets[n+1]) < 9) + ramsettings[9] = atoi(sets[n+1])-1; + } + if(strcmp(sets[n],comps[15]) == 0) + { + run = 1; + runfile = sets[n+1]; + } + if(strcmp(sets[n],comps[16]) == 0) + { + if(atoi(sets[n+1]) >= 33) + if(atoi(sets[n+1]) <= 340) + daemonsettings[0] = atoi(sets[n+1]); + } + if(strcmp(sets[n],comps[17]) == 0) + { + if(atoi(sets[n+1]) >= 33) + if(atoi(sets[n+1]) <= 340) + daemonsettings[1] = atoi(sets[n+1]); + } + if(strcmp(sets[n],comps[18]) == 0) + { + if(atoi(sets[n+1]) >= daemonsettings[1]) + if(atoi(sets[n+1]) <= 340) + daemonsettings[2] = atoi(sets[n+1]); + } + if(strcmp(sets[n],comps[19]) == 0) + { + daemonsettings[3] = (int)(atof(sets[n+1])*10+0.5); + if(daemonsettings[3] < 1) + daemonsettings[3] = 5; + } + if(strcmp(sets[n],comps[20]) == 0) + { + daemonsettings[4] = parse_key_sequence(sets[n+1]); + } + if(strcmp(sets[n],comps[21]) == 0) + { + daemonsettings[5] = parse_key_sequence(sets[n+1]); + } + if(strcmp(sets[n],comps[22]) == 0) + { + daemonsettings[6] = parse_key_sequence(sets[n+1]); + } + if(strcmp(sets[n],comps[23]) == 0) + { + daemonsettings[7] = (sets[n+1][1] == 'n' ? 1 : 0); + } + if(strcmp(sets[n],comps[24]) == 0) + { + start_daemon = 1; + } + } + } + + if(run == 1) + { + if (cpusettings[0] > -1) set_FCLK(cpusettings[0]); + if (cpusettings[1] > -1) set_920_Div(cpusettings[1]); + if (dispsettings[0] == 0) + if (dispsettings[1] > -100) set_add_FLCDCLK(dispsettings[1]); + if (dispsettings[0] == 1) + if (dispsettings[1] > -100) set_add_ULCDCLK(dispsettings[1]); + if (dispsettings[2] > -1) set_gamma((float)(dispsettings[2]/100)); + if (ramsettings[0] > -1) set_CAS(ramsettings[0]); + if (ramsettings[1] > -1) set_tRC(ramsettings[1]); + if (ramsettings[2] > -1) set_tRAS(ramsettings[2]); + if (ramsettings[3] > -1) set_tWR(ramsettings[3]); + if (ramsettings[4] > -1) set_tMRD(ramsettings[4]); + if (ramsettings[5] > -1) set_tRFC(ramsettings[5]); + if (ramsettings[6] > -1) set_tRP(ramsettings[6]); + if (ramsettings[7] > -1) set_tRCD(ramsettings[7]); + if (ramsettings[8] > -1) set_REFPERD(ramsettings[8]); + if (ramsettings[9] > -1) set_DCLK_Div(ramsettings[9]); + exit_cpu_speed(runfile); + return 0; + } + + sysfreq=get_freq_920_CLK(); + sysfreq*=get_920_Div()+1; + cpufreq=sysfreq/1000000; + +#if 0 + if(argc > 1) + { + if(strcmp(argv[1], "0") == 0) fallback(argc, argv); + else if(strcmp(argv[1], "1") == 0) fallback(argc, argv); + else if(strcmp(argv[1], "--help") == 0) cmdhelp(); + else if(strcmp(argv[1], "--daemon") == 0) cmd_daemon(argc, argv); + else if(strcmp(argv[1], "--kill-daemon") == 0) kill_running_daemon() || printf("no daemon running\r\n"); + else if(strcmp(argv[1], "--kill") == 0) kill_running_daemon() || printf("no daemon running\r\n"); + else cmdline(argc, argv); + gp2x_deinit(); + return 0; + } +#endif + + if(start_daemon) + start_daemon_by_settings(); + + set_gamma(1.0); + + do + { + cleardisp(); + + //main menu + v_putcad(27,26,WHITE,COLORFONDO,"Y:Save to SD"); + v_putcad(2,27,WHITE,COLORFONDO,"Select: Set setting and quit"); + itemhelp("menu"); + if(mainmenupoint==0) v_putcad(2,6,0xffffff,TEXTBACK,"> CPU Clock"); + else v_putcad(2,6,0xffff,COLORFONDO,"> CPU Clock"); + if(mainmenupoint==1) v_putcad(2,8,0xffffff,TEXTBACK,"> Display Settings"); + else v_putcad(2,8,0xffff,COLORFONDO,"> Display Settings"); + if(mainmenupoint==2) v_putcad(2,10,0xffffff,TEXTBACK,"> RAM Settings"); + else v_putcad(2,10,0xffff,COLORFONDO,"> RAM Settings"); + if(mainmenupoint==3) v_putcad(2,12,0xffffff,TEXTBACK,"> Daemon"); + else v_putcad(2,12,0xffff,COLORFONDO,"> Daemon"); + v_putcad(2,17,0xffff00,COLORFONDO,"Information:"); + sprintf(cad,"Sys.-Frq: %u Hz",sysfreq); + v_putcad(2,19,0xffffff,COLORFONDO,cad); + sprintf(cad,"UCLK-Frq: %u Hz",get_freq_UCLK()); + v_putcad(2,20,0xffffff,COLORFONDO,cad); + sprintf(cad,"ACLK-Frq: %u Hz",get_freq_ACLK()); + v_putcad(2,21,0xffffff,COLORFONDO,cad); + gp2x_video_flip(); + + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + + if((gp2x_nKeys & GP2X_START)) + { + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + exit_cpu_speed("gp2xmenu"); + return 0; + } + + if((gp2x_nKeys & GP2X_SELECT)) + { + if (cpusettings[0] > -1) + { + set_FCLK(cpusettings[0]); + set_920_Div(cpusettings[1]); + } + if (ramsettings[0] > -1) + { + set_CAS(ramsettings[0]); + set_tRC(ramsettings[1]); + set_tRAS(ramsettings[2]); + set_tWR(ramsettings[3]); + set_tMRD(ramsettings[4]); + set_tRFC(ramsettings[5]); + set_tRP(ramsettings[6]); + set_tRCD(ramsettings[7]); + set_REFPERD(ramsettings[8]); + set_DCLK_Div(ramsettings[9]); + } + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + exit_cpu_speed("gp2xmenu"); + return 0; + } + + if((gp2x_nKeys & GP2X_DOWN)) + { + mainmenupoint=mainmenupoint+1; + if(mainmenupoint>3) mainmenupoint=0; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_UP)) + { + mainmenupoint=mainmenupoint-1; + if(mainmenupoint<0) mainmenupoint=3; + delay_us(200000); + break; + } + + if((gp2x_nKeys & GP2X_Y)) + { + settings = fopen("./cpu_speed.cfg", "w"); + if(cpusettings[0] > -1) + { + fprintf(settings,"CPU-Clock\n%u\n", cpusettings[0]); + fprintf(settings,"CPU-Div\n%i\n", cpusettings[1]+1); + } + if(dispsettings[0] > -1) + { + if(dispsettings[0] == 0) fprintf(settings,"FPLL\n%i\n", dispsettings[1]); + if(dispsettings[0] == 1) fprintf(settings,"UPLL\n%i\n", dispsettings[1]); + fprintf(settings,"Gamma\n%.2f\n", (float)(dispsettings[2]/100)); + } + if(ramsettings[0] > -1) + { + fprintf(settings,"CAS\n%i\n", ramsettings[0]+2); + fprintf(settings,"tRC\n%i\n", ramsettings[1]+1); + fprintf(settings,"tRAS\n%i\n", ramsettings[2]+1); + fprintf(settings,"tWR\n%i\n", ramsettings[3]+1); + fprintf(settings,"tMRD\n%i\n", ramsettings[4]+1); + fprintf(settings,"tRFC\n%i\n", ramsettings[5]+1); + fprintf(settings,"tRP\n%i\n", ramsettings[6]+1); + fprintf(settings,"tRCD\n%i\n", ramsettings[7]+1); + fprintf(settings,"Refresh-Period\n%i\n", ramsettings[8]+1); + fprintf(settings,"RAM-Div\n%i\n", ramsettings[9]+1); + } + if(daemonsettings[0] > -1) + { + fprintf(settings,"Daemon-Min\n%i\n", daemonsettings[0]); + fprintf(settings,"Daemon-Max\n%i\n", daemonsettings[1]); + fprintf(settings,"Daemon-Step\n%i\n", daemonsettings[2]); + fprintf(settings,"Daemon-Delay\n%.1f\n", daemonsettings[3]/10.f); + + char test[256]; + sprintf(test,""); + formatkey(test,daemonsettings[4]); + fprintf(settings,"Daemon-Hotkey\n%s\n",test); + sprintf(test,""); + formatkey(test,daemonsettings[5]); + fprintf(settings,"Daemon-Incr-Key\n%s\n",test); + sprintf(test,""); + formatkey(test,daemonsettings[6]); + fprintf(settings,"Daemon-Decr-Key\n%s\n",test); + + fprintf(settings,"Daemon-OSD\n%s\n",(daemonsettings[7]?"On":"Off")); + if(!access("/tmp/cpu_daemon.pid",R_OK)) + fprintf(settings,"Daemon-Run\nOn\n"); + + } + + + fclose(settings); + system("sync"); + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_Y)) break; + } + break; + } + + + if((gp2x_nKeys & GP2X_B)) + { + if(mainmenupoint==0) cpumenu(); + if(mainmenupoint==1) lcdmenu(); + if(mainmenupoint==2) rammenu(); + if(mainmenupoint==3) daemonmenu(); + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_B)) break; + } + break; + } + } + } + while(cpuspeed_exit == 0); +} diff --git a/gp2x/cpuctrl.c b/gp2x/cpuctrl.c new file mode 100644 index 0000000..ab165fc --- /dev/null +++ b/gp2x/cpuctrl.c @@ -0,0 +1,484 @@ +/* cpuctrl.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0) + Copyright (C) 2006 god_at_hell + original CPU-Overclocker (c) by Hermes/PS2Reality + the gamma-routine was provided by theoddbot + parts (c) Rlyehs Work + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + + +/****************************************************************************************************************************************/ +// CPU CONTROL +/****************************************************************************************************************************************/ + +#include +#include +#include +#include "gp2xminilib.h" + +#define SYS_CLK_FREQ 7372800 + +//from minimal library rlyeh + +extern unsigned long gp2x_dev[4]; +extern unsigned short *gp2x_memregs; + +// system registers +static struct +{ + unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,DISPCSETREG,MEMTIMEX0; + unsigned short MEMTIMEX1,MEMREFX,MLC_GAMM_BYPATH,MLC_GAMMA_A,MLC_GAMMA_D,YBNKLVL; +} +system_reg; + +volatile unsigned short *MEM_REG; +unsigned MDIV,PDIV,SCALE; +volatile unsigned *arm940code; + +void cpuctrl_init() +{ + MEM_REG=&gp2x_memregs[0]; +} + +void save_system_regs() +{ + system_reg.SYSCSETREG=MEM_REG[0x91c>>1]; + system_reg.FPLLVSETREG=MEM_REG[0x912>>1]; + system_reg.SYSCLKENREG=MEM_REG[0x904>>1]; + system_reg.DUALINT920=MEM_REG[0x3B40>>1]; + system_reg.DUALINT940=MEM_REG[0x3B42>>1]; + system_reg.DUALCTRL940=MEM_REG[0x3B48>>1]; + system_reg.DISPCSETREG=MEM_REG[0x924>>1]; + system_reg.MEMTIMEX0=MEM_REG[0x3802>>1]; + system_reg.MEMTIMEX1=MEM_REG[0x3804>>1]; + system_reg.MEMREFX=MEM_REG[0x3808>>1]; + system_reg.MLC_GAMM_BYPATH=MEM_REG[0x2880>>1]; + system_reg.MLC_GAMMA_A=MEM_REG[0x295C>>1]; + system_reg.MLC_GAMMA_D=MEM_REG[0x295E>>1]; + system_reg.YBNKLVL=MEM_REG[0x283A>>1]; +} + +void load_system_regs() +{ + MEM_REG[0x91c>>1]=system_reg.SYSCSETREG; + MEM_REG[0x910>>1]=system_reg.FPLLVSETREG; + MEM_REG[0x3B40>>1]=system_reg.DUALINT920; + MEM_REG[0x3B42>>1]=system_reg.DUALINT940; + MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940; + MEM_REG[0x904>>1]=system_reg.SYSCLKENREG; + /* Set UPLLSETVREG to 0x4F02, which gives 80MHz */ + MEM_REG[0x0914>>1] = 0x4F02; + /* Wait for clock change to start */ + while (MEM_REG[0x0902>>1] & 2); + /* Wait for clock change to be verified */ + while (MEM_REG[0x0916>>1] != 0x4F02); + MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0; + MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1; + MEM_REG[0x3808>>1]=system_reg.MEMREFX; + MEM_REG[0x2880>>1]=system_reg.MLC_GAMM_BYPATH; + MEM_REG[0x295C>>1]=system_reg.MLC_GAMMA_A; + MEM_REG[0x295E>>1]=system_reg.MLC_GAMMA_D; + MEM_REG[0x283A>>1]=system_reg.YBNKLVL; +} + + +void set_FCLK(unsigned MHZ) +{ + printf ("set CPU-Frequency = %uMHz\r\n",MHZ); + unsigned v; + unsigned mdiv,pdiv=3,scale=0; + MHZ*=1000000; + mdiv=(MHZ*pdiv)/SYS_CLK_FREQ; + //printf ("Old value = %04X\r",MEM_REG[0x924>>1]," "); + //printf ("APLL = %04X\r",MEM_REG[0x91A>>1]," "); + mdiv=((mdiv-8)<<8) & 0xff00; + pdiv=((pdiv-2)<<2) & 0xfc; + scale&=3; + v=mdiv | pdiv | scale; + MEM_REG[0x910>>1]=v; +} + +unsigned get_FCLK() +{ + return MEM_REG[0x910>>1]; +} + +void set_add_FLCDCLK(int addclock) +{ + //Set LCD controller to use FPLL + printf ("...set to FPLL-Clockgen...\r\n"); + printf ("set Timing-Prescaler = %i\r\n",addclock); + MEM_REG[0x924>>1]= 0x5A00 + ((addclock)<<8); + //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c" +} + +void set_add_ULCDCLK(int addclock) +{ + //Set LCD controller to use UPLL + printf ("...set to UPLL-Clockgen...\r\n"); + printf ("set Timing-Prescaler = %i\r\n",addclock); + MEM_REG[0x0924>>1] = 0x8900 + ((addclock)<<8); + //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c" +} + +unsigned get_LCDClk() +{ + if (MEM_REG[0x0924>>1] < 0x7A01) return((MEM_REG[0x0924>>1] - 0x5A00)>>8); + else return((MEM_REG[0x0924>>1] - 0x8900)>>8); +} + +char get_Clkgen() +{ + if (MEM_REG[0x0924>>1] < 0x7A01) return(0); + else return(1); +} + +unsigned get_freq_UCLK() +{ + unsigned i; + unsigned reg,mdiv,pdiv,scale; + i = MEM_REG[0x900>>1]; + i = ((i >> 7) & 1) ; + if(i) return 0; + reg=MEM_REG[0x916>>1]; + mdiv = ((reg & 0xff00) >> 8) + 8; + pdiv = ((reg & 0xfc) >> 2) + 2; + scale = reg & 3; + return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale)); +} + +unsigned get_freq_ACLK() +{ + unsigned i; + unsigned reg,mdiv,pdiv,scale; + i = MEM_REG[0x900>>1]; + i = ((i >> 8) & 1) ; + if(i) return 0; + reg=MEM_REG[0x918>>1]; + mdiv = ((reg & 0xff00) >> 8) + 8; + pdiv = ((reg & 0xfc) >> 2) + 2; + scale = reg & 3; + return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale)); +} + +unsigned get_freq_920_CLK() +{ + unsigned i; + unsigned reg,mdiv,pdiv,scale; + reg=MEM_REG[0x912>>1]; + mdiv = ((reg & 0xff00) >> 8) + 8; + pdiv = ((reg & 0xfc) >> 2) + 2; + scale = reg & 3; + MDIV=mdiv; + PDIV=pdiv; + SCALE=scale; + i = (MEM_REG[0x91c>>1] & 7)+1; + return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale))/i; +} + +unsigned get_freq_940_CLK() +{ + unsigned i; + unsigned reg,mdiv,pdiv,scale; + reg=MEM_REG[0x912>>1]; + mdiv = ((reg & 0xff00) >> 8) + 8; + pdiv = ((reg & 0xfc) >> 2) + 2; + scale = reg & 3; + i = ((MEM_REG[0x91c>>1]>>3) & 7)+1; + return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i; +} + +unsigned get_freq_DCLK() +{ + unsigned i; + unsigned reg,mdiv,pdiv,scale; + reg=MEM_REG[0x912>>1]; + mdiv = ((reg & 0xff00) >> 8) + 8; + pdiv = ((reg & 0xfc) >> 2) + 2; + scale = reg & 3; + i = ((MEM_REG[0x91c>>1]>>6) & 7)+1; + return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i; +} + +void set_920_Div(unsigned short div) +{ + printf ("set divider for CPU-Clock = %u\r\n",div+1); + unsigned short v; + v = MEM_REG[0x91c>>1] & (~0x3); + MEM_REG[0x91c>>1] = (div & 0x7) | v; +} + +unsigned short get_920_Div() +{ + return (MEM_REG[0x91c>>1] & 0x7); +} + +void set_940_Div(unsigned short div) +{ + unsigned short v; + v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 3))); + MEM_REG[0x91c>>1] = ((div & 0x7) << 3) | v; +} + +unsigned short get_940_Div() +{ + return ((MEM_REG[0x91c>>1] >> 3) & 0x7); +} + +void set_DCLK_Div( unsigned short div ) +{ + printf ("set divider for RAM-Clock = %u\r\n",div+1); + unsigned short v; + v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6))); + MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v; +} + +unsigned short get_DCLK_Div() +{ + return ((MEM_REG[0x91c>>1] >> 6) & 0x7); +} + +unsigned short Disable_Int_920() +{ + unsigned short ret; + ret=MEM_REG[0x3B40>>1]; + MEM_REG[0x3B40>>1]=0; + MEM_REG[0x3B44>>1]=0xffff; + return ret; +} + +unsigned short Disable_Int_940() +{ + unsigned short ret; + ret=MEM_REG[0x3B42>>1]; + MEM_REG[0x3B42>>1]=0; + MEM_REG[0x3B46>>1]=0xffff; + return ret; +} + +unsigned get_state940() +{ + return MEM_REG[0x904>>1]; +} + + +void Enable_Int_920(unsigned short flag) +{ + MEM_REG[0x3B40>>1]=flag; +} + +void Enable_Int_940(unsigned short flag) +{ + MEM_REG[0x3B42>>1]=flag; +} + +void Disable_940() +{ + Disable_Int_940(); + MEM_REG[0x3B48>>1]|= (1 << 7); + MEM_REG[0x904>>1]&=0xfffe; +} + +void Load_940_code(unsigned *code,int size) +{ + unsigned *cp; + int i; + arm940code=(unsigned short *)mmap(0, 0x100000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0x03000000); + Disable_940(); + cp=(unsigned *) code; + for (i = 0; i < size/4; i ++) + { + arm940code[i] = cp[i]; + } + for (i = 0; i < 64; i ++) + { + arm940code[0x3FC0+i] = 0; + } + MEM_REG[0x3B48>>1]=(MEM_REG[0x3B48>>1] & 0xFF00) | 0x03; // allow 940 +} + +void clock_940_off() +{ + MEM_REG[0x904>>1]&=0xfffe; +} + +void clock_940_on() +{ + MEM_REG[0x904>>1]|=1; +} + + +//-------------- +//Memory Timings +//-------------- + +//get + +unsigned get_CAS() +{ + return ((MEM_REG[0x3804>>1] >> 12) & 0x1); +} + +unsigned get_tRC() +{ + return ((MEM_REG[0x3804>>1] >> 8) & 0xF); +} + +unsigned get_tRAS() +{ + return ((MEM_REG[0x3804>>1] >> 4) & 0xF); +} + +unsigned get_tWR() +{ + return (MEM_REG[0x3804>>1] & 0xF); +} + +unsigned get_tMRD() +{ + return ((MEM_REG[0x3802>>1] >> 12) & 0xF); +} + +unsigned get_tRFC() +{ + return ((MEM_REG[0x3802>>1] >> 8) & 0xF); +} + +unsigned get_tRP() +{ + return ((MEM_REG[0x3802>>1] >> 4) & 0xF); +} + +unsigned get_tRCD() +{ + return (MEM_REG[0x3802>>1] & 0xF); +} + +unsigned get_REFPERD() +{ + return MEM_REG[0x3808>>1]; +} + + +//set + +void set_CAS(unsigned short timing) +{ + printf ("set CAS = %u\r\n",timing+2); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0x1 << 12))); + MEM_REG[0x3804>>1] = ((timing & 0x1) << 12) | v; +} + +void set_tRC(unsigned short timing) +{ + printf ("set tRC = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 8))); + MEM_REG[0x3804>>1] = ((timing & 0xF) << 8) | v; +} + +void set_tRAS(unsigned short timing) +{ + printf ("set tRAS = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 4))); + MEM_REG[0x3804>>1] = ((timing & 0xF) << 4) | v; +} + +void set_tWR(unsigned short timing) +{ + printf ("set tWR = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF))); + MEM_REG[0x3804>>1] = (timing & 0xF) | v; +} + +void set_tMRD(unsigned short timing) +{ + printf ("set tMRD = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 12))); + MEM_REG[0x3802>>1] = ((timing & 0xF) << 12) | v; +} + +void set_tRFC(unsigned short timing) +{ + printf ("set tRFC = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 8))); + MEM_REG[0x3802>>1] = ((timing & 0xF) << 8) | v; +} + +void set_tRP(unsigned short timing) +{ + printf ("set tRP = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 4))); + MEM_REG[0x3802>>1] = ((timing & 0xF) << 4) | v; +} + +void set_tRCD(unsigned short timing) +{ + printf ("set tRCD = %u\r\n",timing+1); + unsigned short v; + v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF))); + MEM_REG[0x3802>>1] = (timing & 0xF) | v; +} + +void set_REFPERD(unsigned short timing) +{ + printf ("set Refresh Period = %u\r\n",timing+1); + MEM_REG[0x3808>>1] = timing; +} + + +//----- +//Gamma +//----- + +void set_gamma(float gamma) +{ + printf ("set gamma = %f\r\n",gamma); + int i; + gamma = 1/gamma; + + //enable gamma + MEM_REG[0x2880>>1]&=~(1<<12); + + MEM_REG[0x295C>>1]=0; + for(i=0; i<256; i++) + { + unsigned char g; + unsigned short s; + g =(unsigned char)(255.0*pow(i/255.0,gamma)); + s = (g<<8) | g; + MEM_REG[0x295E>>1]= s; + MEM_REG[0x295E>>1]= g; + } +} + +unsigned get_YBNKLVL() +{ + return (MEM_REG[0x283A>>1] & 0x3FF); +} + +void set_YBNKLVL(unsigned short val) +{ + unsigned short temp = (unsigned short)(MEM_REG[0x3808>>1] & (~(0x3FF))); + MEM_REG[0x3808>>1] = (val & 0x3FF) | temp; +} diff --git a/gp2x/cpuctrl.h b/gp2x/cpuctrl.h new file mode 100644 index 0000000..13ffa26 --- /dev/null +++ b/gp2x/cpuctrl.h @@ -0,0 +1,72 @@ +#if !defined(_CPUCTRL_) +#define _CPUCTRL_ + +void cpuctrl_init(); // call this at first + +void save_system_regs(); // save some registers +void load_system_regs(); + +void set_FCLK(unsigned MHZ); // adjust the clock frequency (in Mhz units) +void set_add_ULCDCLK(int addclock); +void set_add_FLCDCLK(int addclock); + +unsigned get_FCLK(); +unsigned get_freq_UCLK(); +unsigned get_freq_ACLK(); +unsigned get_freq_920_CLK(); +unsigned get_freq_940_CLK(); +unsigned get_freq_DCLK(); +unsigned get_LCDClk(); +char get_Clkgen(); +unsigned get_state940(); + +void set_920_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */ +unsigned short get_920_Div(); + +void set_940_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */ +unsigned short get_940_Div(); + +void set_DCLK_Div(unsigned short div); /* 0 to 7 divider (freq=FCLK/(1+div)) */ +unsigned short get_DCLK_Div(); + +unsigned short Disable_Int_920(); +unsigned short Disable_Int_940(); + +void Enable_Int_920(unsigned short flag); +void Enable_Int_940(unsigned short flag); + +void Disable_940(); // 940t down + +extern volatile unsigned *arm940code; // memory address of 940t code + +void Load_940_code(unsigned *code,int size); // enable 940t, load 940t code and clock 940t off + +void clock_940_off(); // 940t stops +void clock_940_on(); // 940t running + +//Memory Timings +unsigned get_CAS(); //CAS Latency +unsigned get_tRC(); //ACTIVE to ACTIVE /AUTOREFRESH command delay +unsigned get_tRAS(); //ACTIVE to PRECHARGE delay +unsigned get_tWR(); //Write recovery time +unsigned get_tMRD(); //LOAD MODE REGISTER command cycle time +unsigned get_tRFC(); //AUTO REFRESH command period +unsigned get_tRP(); //PRECHARGE command period +unsigned get_tRCD(); //RAS to CAS Delay +unsigned get_REFPERD();//Refresh Period + +void set_CAS(); +void set_tRC(); +void set_tRAS(); +void set_tWR(); +void set_tMRD(); +void set_tRFC(); +void set_tRP(); +void set_tRCD(); +void set_REFPERD(); + +void set_gamma(float gamma); + +unsigned get_YBNKLVL(); +void set_YBNKLVL(unsigned short val); +#endif diff --git a/gp2x/daemon.c b/gp2x/daemon.c new file mode 100644 index 0000000..11b42b4 --- /dev/null +++ b/gp2x/daemon.c @@ -0,0 +1,671 @@ +/* daemon.c for GP2X Version 2.0 + Copyright (C) 2006 jannis harder + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gp2xminilib.h" +#include "cpuctrl.h" +#include "display.h" + +#include "daemon.h" + + +extern unsigned COLORFONDO; // background-color +extern unsigned WHITE; +extern unsigned TEXTBACK; + +extern unsigned char cad[256]; + +extern unsigned short *gp2x_memregs; +extern pthread_t gp2x_sound_thread; + +int start_daemon( + unsigned int minimal_cpu_speed, unsigned int maximal_cpu_speed, unsigned int start_cpu_speed, int cpu_speed_step, + unsigned long hotkey, unsigned long incrementkey, unsigned long decrementkey, + int speed_display, int foreground, + unsigned long delay) +{ + pid_t pid, sid; + + if(!foreground) { + kill_running_daemon(); + + + FILE * pidfile = fopen("/tmp/cpu_daemon.pid","w"); + + if(!pidfile) { + printf("couldn't write pidfile\r\n"); + exit(-2); + } + + pid = fork(); + + if(pid > 0) { + fprintf(pidfile,"%i\n",pid); + fclose(pidfile); + } + if(pid != 0) + return pid; + + + fclose(pidfile); + + umask(0); + sid = setsid(); + + + close(STDIN_FILENO); + close(STDOUT_FILENO); + close(STDERR_FILENO); + } + + if(foreground) + printf("daemon ready\r\n"); + + nano_setup(); // loading the full minilib would be overkill and i guess some games/emus wouldn't like it + + + unsigned int current_cpu_speed = start_cpu_speed; + + while(1) { + usleep(delay); + unsigned long keystate = gp2x_joystick_read(); + + unsigned int last_cpu_speed = 0; + + while( + (hotkey && (keystate & hotkey) == hotkey) || + ((!hotkey) && ( + (incrementkey && (keystate & incrementkey) == incrementkey) || + (decrementkey && (keystate & decrementkey) == decrementkey) + )) + ) { + if(foreground && !last_cpu_speed) + printf("cpu daemon activated!\r\n"); + + if(incrementkey && (keystate & incrementkey) == incrementkey) { + current_cpu_speed += cpu_speed_step; + while((keystate & incrementkey) == incrementkey) usleep(100000),keystate = gp2x_joystick_read(); + } + else if(decrementkey && (keystate & decrementkey) == decrementkey) { + current_cpu_speed -= cpu_speed_step; + while((keystate & decrementkey) == decrementkey) usleep(100000),keystate = gp2x_joystick_read(); + } + + if(current_cpu_speed < minimal_cpu_speed) + current_cpu_speed = minimal_cpu_speed; + if(current_cpu_speed > maximal_cpu_speed) + current_cpu_speed = maximal_cpu_speed; + + + + if(last_cpu_speed != current_cpu_speed) { + set_FCLK(current_cpu_speed); + } + last_cpu_speed = current_cpu_speed; + keystate = gp2x_joystick_read(); + } + + } + +} + +int kill_running_daemon() { + + FILE * pidfile = fopen("/tmp/cpu_daemon.pid","r"); + char pid_buffer[14]; + pid_buffer[0] = 'k'; + pid_buffer[1] = 'i'; + pid_buffer[2] = 'l'; + pid_buffer[3] = 'l'; + pid_buffer[4] = ' '; + pid_buffer[5] = 0; + if(pidfile) { + printf("found pidfile\r\n"); + fgets(&(pid_buffer[5]),10,pidfile); + fclose(pidfile); + int return_code = system(pid_buffer); + if(return_code) + printf("daemon wasn't running\r\n"); + else + printf("killed old daemon\r\n"); + unlink("/tmp/cpu_daemon.pid"); + return 1; + } + return 0; +} + + +void nano_setup() { + if(!gp2x_sound_thread) { + gp2x_memregs=(unsigned short *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, open("/dev/mem", O_RDWR), 0xc0000000); + cpuctrl_init(); + } +} + +void cmd_daemon(int argc, char *argv[]) { + + int cpu_div = get_920_Div(); + int sysfreq=get_freq_920_CLK(); + sysfreq*=cpu_div+1; + int cpufreq=sysfreq/1000000; + + unsigned int minimal_value = 33; + unsigned int maximal_value = 260; + unsigned int start_value = cpufreq; + unsigned int step = 10; + unsigned long hotkey = GP2X_L | GP2X_R; + unsigned long downkey = GP2X_VOL_UP; + unsigned long upkey = GP2X_VOL_DOWN; + int foreground = 0; + int display = 1; + float delay = 1; + + int i; + for( i = 2; i < argc; i++) { + if(!strcmp(argv[i],"--min")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + minimal_value = atoi(argv[i+1]); + if(minimal_value < 33) + minimal_value = 33; + } + else if(!strcmp(argv[i],"--max")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + maximal_value = atoi(argv[i+1]); + if(maximal_value > 340) + maximal_value = 340; + } + else if(!strcmp(argv[i],"--start")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + start_value = atoi(argv[i+1]); + } + else if(!strcmp(argv[i],"--step")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + step = atoi(argv[i+1]); + } + else if(!strcmp(argv[i],"--hotkey")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + hotkey = parse_key_sequence(argv[i+1]); + } + else if(!strcmp(argv[i],"--incr")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + upkey = parse_key_sequence(argv[i+1]); + } + else if(!strcmp(argv[i],"--decr")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + downkey = parse_key_sequence(argv[i+1]); + } + else if(!strcmp(argv[i],"--delay")) { + if(i+1 == argc){printf ("%s is missing it's parameter\r\n",argv[i]);gp2x_deinit();exit(1);} + delay = atof(argv[i+1]); + } + else if(!strcmp(argv[i],"--no-incr")) { + upkey = 0; + } + else if(!strcmp(argv[i],"--no-decr")) { + downkey = 0; + } + else if(!strcmp(argv[i],"--no-hotkey")) { + hotkey = 0; + } + else if(!strcmp(argv[i],"--foreground")) { + foreground = 1; + } + else if(!strcmp(argv[i],"--background")) { + foreground = 0; + } + else if(!strcmp(argv[i],"--display")) { + display = 1; + } + else if(!strcmp(argv[i],"--no-display")) { + display = 0; + } + } + + if((hotkey & downkey) == downkey) + printf("warning: hotkey includes decrement keypress!\r\n"); + if((hotkey & upkey) == upkey) + printf("warning: hotkey includes increment keypress!\r\n"); + + int pid = start_daemon(minimal_value, maximal_value, start_value, step, hotkey, upkey, downkey, display, foreground, delay* 1000000); + + if(pid < 0) { + printf("couldn't start daemon\r\n"); + exit(1); + } + else if(pid > 0) { + printf("daemon started\r\n"); + exit(0); + } +} + +unsigned long parse_key_sequence(char *key_sequence) { + unsigned long hotkey = 0; + if(!strcmp(key_sequence,"None")) + return 0; + char *mask = key_sequence; + while(*mask) { + switch(*mask) { + case 'l': + case 'L': + hotkey |= GP2X_L; + break; + case 'r': + case 'R': + hotkey |= GP2X_R; + break; + case 'a': + case 'A': + hotkey |= GP2X_A; + break; + case 'b': + case 'B': + hotkey |= GP2X_B; + break; + case 'x': + case 'X': + hotkey |= GP2X_X; + break; + case 'y': + case 'Y': + hotkey |= GP2X_Y; + break; + case '+': + hotkey |= GP2X_VOL_DOWN; + break; + case '-': + hotkey |= GP2X_VOL_UP; + break; + case 'S': + case 's': + hotkey |= GP2X_START; + break; + case '/': + hotkey |= GP2X_SELECT; + break; + case '@': + hotkey |= GP2X_PUSH; + break; + case '\n': + break; + default: + printf("unknown key %c\r\n",*mask); + } + mask++; + } + return hotkey; +} + +int daemonsettings[8]; + + +void cleardisp(); + + +void formatkey(char * base, unsigned long keyseq) { + + if(!keyseq) + strcat(base,"None"); + + if(keyseq & GP2X_L) + strcat(base,"L"); + if(keyseq & GP2X_R) + strcat(base,"R"); + if(keyseq & GP2X_A) + strcat(base,"A"); + if(keyseq & GP2X_B) + strcat(base,"B"); + if(keyseq & GP2X_X) + strcat(base,"X"); + if(keyseq & GP2X_Y) + strcat(base,"Y"); + if(keyseq & GP2X_VOL_DOWN) + strcat(base,"+"); + if(keyseq & GP2X_VOL_UP) + strcat(base,"-"); + if(keyseq & GP2X_START) + strcat(base,"S"); + if(keyseq & GP2X_SELECT) + strcat(base,"/"); + if(keyseq & GP2X_PUSH) + strcat(base,"@"); +} + + + +#define VALID_KEYS ((GP2X_L) | (GP2X_R) | (GP2X_X) | (GP2X_Y) | (GP2X_A) | (GP2X_B) | (GP2X_START) | (GP2X_SELECT) | (GP2X_VOL_UP) | (GP2X_VOL_DOWN) | (GP2X_PUSH) ) + +int running; + +void daemon_itemhelp(int menuitem) +{ + switch(menuitem) { + case 0: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"minimal"); + v_putcad(26,10,0xffffff,COLORFONDO,"clockspeed"); + v_putcad(26,11,0xffffff,COLORFONDO,"with R/L or"); + v_putcad(26,12,0xffffff,COLORFONDO,"Vol UP/Down."); + v_putcad(26,14,0xffffff,COLORFONDO,"Valid speeds"); + v_putcad(26,15,0xffffff,COLORFONDO,"are:"); + v_putcad(26,16,0xffffff,COLORFONDO,"33 to 340Mhz"); + break; + case 1: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"maximal"); + v_putcad(26,10,0xffffff,COLORFONDO,"clockspeed"); + v_putcad(26,11,0xffffff,COLORFONDO,"with R/L or"); + v_putcad(26,12,0xffffff,COLORFONDO,"Vol UP/Down."); + v_putcad(26,14,0xffffff,COLORFONDO,"Valid speeds"); + v_putcad(26,15,0xffffff,COLORFONDO,"are:"); + v_putcad(26,16,0xffffff,COLORFONDO,"33 to 340Mhz"); + break; + case 2: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a step"); + v_putcad(26,9,0xffffff,COLORFONDO,"width for"); + v_putcad(26,10,0xffffff,COLORFONDO,"changing the"); + v_putcad(26,11,0xffffff,COLORFONDO,"clockspeed."); + v_putcad(26,13,0xffffff,COLORFONDO,"Use R/L or"); + v_putcad(26,14,0xffffff,COLORFONDO,"Vol UP/Down."); + break; + case 3: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"delay between"); + v_putcad(26,10,0xffffff,COLORFONDO,"each hotkey"); + v_putcad(26,11,0xffffff,COLORFONDO,"check"); + v_putcad(26,13,0xffffff,COLORFONDO,"Use R/L or"); + v_putcad(26,14,0xffffff,COLORFONDO,"Vol UP/Down."); + break; + case 4: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"hotkey."); + v_putcad(26,10,0xffffff,COLORFONDO,"Add or delete"); + v_putcad(26,11,0xffffff,COLORFONDO,"a button by"); + v_putcad(26,12,0xffffff,COLORFONDO,"pressing it."); + v_putcad(26,14,0x0000DD,COLORFONDO,"Joystick is"); + v_putcad(26,15,0x0000DD,COLORFONDO,"not allowed."); + break; + case 5: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"key for"); + v_putcad(26,10,0xffffff,COLORFONDO,"incrementing"); + v_putcad(26,11,0xffffff,COLORFONDO,"the clkspeed."); + v_putcad(26,12,0xffffff,COLORFONDO,"Add or delete"); + v_putcad(26,13,0xffffff,COLORFONDO,"a button by"); + v_putcad(26,14,0xffffff,COLORFONDO,"pressing it."); + v_putcad(26,16,0x0000DD,COLORFONDO,"Joystick is"); + v_putcad(26,17,0x0000DD,COLORFONDO,"not allowed."); + break; + case 6: + v_putcad(26,8,0xffffff,COLORFONDO,"Choose a"); + v_putcad(26,9,0xffffff,COLORFONDO,"key for"); + v_putcad(26,10,0xffffff,COLORFONDO,"decrementing"); + v_putcad(26,11,0xffffff,COLORFONDO,"the clkspeed."); + v_putcad(26,12,0xffffff,COLORFONDO,"Add or delete"); + v_putcad(26,13,0xffffff,COLORFONDO,"a button by"); + v_putcad(26,14,0xffffff,COLORFONDO,"pressing it."); + v_putcad(26,16,0x0000DD,COLORFONDO,"Joystick is"); + v_putcad(26,17,0x0000DD,COLORFONDO,"not allowed."); + break; + case 7: + /* v_putcad(26,8,0xffffff,COLORFONDO,"Enable or"); + v_putcad(26,9,0xffffff,COLORFONDO,"disable"); + v_putcad(26,10,0xffffff,COLORFONDO,"on screen"); + v_putcad(26,11,0xffffff,COLORFONDO,"display."); + v_putcad(26,13,0x0000DD,COLORFONDO,"May cause"); + v_putcad(26,14,0x0000DD,COLORFONDO,"conflicts"); + v_putcad(26,15,0x0000DD,COLORFONDO,"with"); + v_putcad(26,16,0x0000DD,COLORFONDO,"some apps!");*/ + v_putcad(26,8,0x0000DD,COLORFONDO,"COMING SOON"); + break; + case 8: + if(running) { + v_putcad(26,8,0xffffff,COLORFONDO,"Press B to"); + v_putcad(26,9,0xffffff,COLORFONDO,"kill the"); + v_putcad(26,10,0xffffff,COLORFONDO,"running"); + v_putcad(26,11,0xffffff,COLORFONDO,"daemon"); + v_putcad(26,12,0xffffff,COLORFONDO,"process."); + } + else { + v_putcad(26,8,0xffffff,COLORFONDO,"Press B to"); + v_putcad(26,9,0xffffff,COLORFONDO,"start the "); + v_putcad(26,10,0xffffff,COLORFONDO,"daemon in the"); + v_putcad(26,11,0xffffff,COLORFONDO, "background."); + } + break; + } +} + +void daemonmenu() { + + int menupoint = 0; + running = !access("/tmp/cpu_daemon.pid",R_OK); + + + unsigned long gp2x_nKeys; + while(1) { + + if(daemonsettings[0] < 33) + daemonsettings[0] = 33; + if(daemonsettings[1] > 340) + daemonsettings[1] = 340; + if(daemonsettings[1] < daemonsettings[0]) + daemonsettings[1] = daemonsettings[0]; + if(daemonsettings[0] > daemonsettings[1]) + daemonsettings[0] = daemonsettings[1]; + if(daemonsettings[2] < 1) + daemonsettings[2] = 1; + if(daemonsettings[3] < 1) + daemonsettings[3] = 1; + //if(daemonsettings[7] == 10 || daemonsettings[7] == -10) + // daemonsettings[7] = 1; + //if(daemonsettings[7] == 11 || daemonsettings[7] == -9) + daemonsettings[7] = 0; + + + + cleardisp(); + v_putcad(13,2,WHITE,COLORFONDO,"Daemon Setup"); + + v_putcad(2,5,0xffff00,COLORFONDO,"CPU Clockspeed:"); + + sprintf(cad,"From: %huMhz",daemonsettings[0]); + + v_putcad(2,7,0xffff,COLORFONDO,cad); + if(menupoint == 0) + v_putcad(2,7,0xffff,TEXTBACK,cad); + + sprintf(cad,"To: %huMhz",daemonsettings[1]); + + v_putcad(2,8,0xffff,COLORFONDO,cad); + if(menupoint == 1) + v_putcad(2,8,0xffff,TEXTBACK,cad); + + sprintf(cad,"Step: %huMhz",daemonsettings[2]); + + v_putcad(2,9,0xffff,COLORFONDO,cad); + if(menupoint == 2) + v_putcad(2,9,0xffff,TEXTBACK,cad); + + + v_putcad(2,11,0xffff00,COLORFONDO,"Buttons:"); + + sprintf(cad,"Delay: %0.1fsec",daemonsettings[3]/10.0f); + + v_putcad(2,13,0xffff,COLORFONDO,cad); + if(menupoint == 3) + v_putcad(2,13,0xffff,TEXTBACK,cad); + + sprintf(cad,"Hotkey: "); + + formatkey(cad,daemonsettings[4]); + + v_putcad(2,15,0xffff,COLORFONDO,cad); + if(menupoint == 4) + v_putcad(2,15,0xffff,TEXTBACK,cad); + + + sprintf(cad,"IncrKey: "); + + formatkey(cad,daemonsettings[5]); + + v_putcad(2,16,0xffff,COLORFONDO,cad); + if(menupoint == 5) + v_putcad(2,16,0xffff,TEXTBACK,cad); + + sprintf(cad,"DecrKey: "); + + formatkey(cad,daemonsettings[6]); + + v_putcad(2,17,0xffff,COLORFONDO,cad); + if(menupoint == 6) + v_putcad(2,17,0xffff,TEXTBACK,cad); + + if(menupoint >= 4 && menupoint <=6) + v_putcad(2,26,WHITE,COLORFONDO,"---------- Stick:UP/DOWN"); + + v_putcad(2,19,0xffff00,COLORFONDO,"Misc:"); + + + v_putcad(2,21,0xffff,COLORFONDO,(daemonsettings[7] ? "On Screen Display: On" : "On Screen Display: Off")); + if(menupoint == 7) + v_putcad(2,21,0xffff,TEXTBACK,(daemonsettings[7] ? "On Screen Display: On" : "On Screen Display: Off")); + + + v_putcad(2,23,0xffff,COLORFONDO,(running ? "Kill Running Daemon" : "Start Daemon")); + if(menupoint == 8) + v_putcad(2,23,0xffff,TEXTBACK,(running ? "Kill Running Daemon" : "Start Daemon")); + + + + daemon_itemhelp(menupoint); + + gp2x_video_flip(); + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + + + + if((gp2x_nKeys & GP2X_DOWN)) + { + menupoint++; + if(menupoint>8) menupoint=0; + usleep(200000); + break; + } + + if((gp2x_nKeys & GP2X_UP)) + { + menupoint--; + if(menupoint<0) menupoint=8; + usleep(200000); + break; + } + + if((menupoint >= 4) && (menupoint <= 6) && (gp2x_nKeys & VALID_KEYS)) + { + daemonsettings[menupoint] ^= (gp2x_nKeys & VALID_KEYS); + usleep(200000); + break; + } + + if(menupoint < 8 &&(gp2x_nKeys & GP2X_R)) + { + daemonsettings[menupoint] += 10; + usleep(200000); + break; + } + + if(menupoint < 4 && (gp2x_nKeys & GP2X_VOL_UP)) + { + daemonsettings[menupoint] -= 1; + usleep(200000); + break; + } + + if(menupoint < 4 && (gp2x_nKeys & GP2X_VOL_DOWN)) + { + daemonsettings[menupoint] += 1; + usleep(200000); + break; + } + + if(menupoint < 8 && (gp2x_nKeys & GP2X_L)) + { + daemonsettings[menupoint] -= 10; + usleep(200000); + break; + } + if(menupoint == 8 && (gp2x_nKeys & GP2X_B)) + { + if(running) + kill_running_daemon(); + else { + int cpu_div = get_920_Div(); + int sysfreq=get_freq_920_CLK(); + sysfreq*=cpu_div+1; + int cpufreq=sysfreq/1000000; + + start_daemon_by_settings(); + } + usleep(200000); + running = !access("/tmp/cpu_daemon.pid",R_OK); + break; + } + + + if((gp2x_nKeys & GP2X_START)) + { + while(1) + { + gp2x_nKeys=gp2x_joystick_read(); + if(!(gp2x_nKeys & GP2X_START)) break; + } + + if(running) { // update values! + start_daemon_by_settings(); + } + + + return; + } + + } + } +} + +void start_daemon_by_settings() { + int cpu_div = get_920_Div(); + int sysfreq=get_freq_920_CLK(); + sysfreq*=cpu_div+1; + int cpufreq=sysfreq/1000000; + + start_daemon(daemonsettings[0], daemonsettings[1], cpufreq, daemonsettings[2], daemonsettings[4], daemonsettings[5], + daemonsettings[6], daemonsettings[7], 0, daemonsettings[3] * 100000); +} diff --git a/gp2x/daemon.h b/gp2x/daemon.h new file mode 100644 index 0000000..18fbf4e --- /dev/null +++ b/gp2x/daemon.h @@ -0,0 +1,18 @@ +int start_daemon( + unsigned int minimal_cpu_speed, unsigned int maximal_cpu_speed, unsigned int start_cpu_speed, int cpu_speed_step, + unsigned long hotkey, unsigned long incrementkey, unsigned long decrmentkey, + int speed_display, int foreground, + unsigned long delay); + +int kill_running_daemon(); + +void nano_setup(); +void cmd_daemon(int argc, char *argv[]); + +unsigned long parse_key_sequence(char *key_sequence); + +void daemonmenu(); + +void formatkey(char * base, unsigned long keyseq); + +void start_daemon_by_settings(); diff --git a/gp2x/display.c b/gp2x/display.c new file mode 100644 index 0000000..82eb31c --- /dev/null +++ b/gp2x/display.c @@ -0,0 +1,139 @@ +/* display.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0) + Copyright (C) 2006 god_at_hell + original CPU-Overclocker (c) by Hermes/PS2Reality + parts (c) Rlyehs Work + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include +#include +#include +#include +#include + +#include "gp2xminilib.h" +#include "cpuctrl.h" +#define WIDTH 320 +#define HEIGHT 240 + +//unsigned TEXTBACK=0x900000; // text-background-color + +extern unsigned char msx[]; // define la fuente externa usada para dibujar letras y numeros + +void ClearScreen(unsigned val) // se usa para 'borrar' la pantalla virtual con un color +{ + int n; + unsigned char *c; + unsigned short col; + c=&val; + col=gp2x_video_color15(c[0],c[1],c[2],0); + for(n=0;n<320*240;n++) + { + gp2x_screen15[n]=col; + } +} + +void DrawBox(unsigned val) +{ + int n; + unsigned char *c; + unsigned short col; + c=&val; + col=gp2x_video_color15(c[0],c[1],c[2],0); + + for(n=320*27+2;n<320*28-1;n++) + { + gp2x_screen15[n]=col; + gp2x_screen15[n+320*209]=col; + } + + for(n=320*29+4;n<320*30-3;n++) + { + gp2x_screen15[n]=col; + gp2x_screen15[n+320*169]=col; + gp2x_screen15[n+320*205]=col; + } + + for(n=320*28;n<320*237;n=n+320) + { + gp2x_screen15[n+2]=col; + gp2x_screen15[n-2]=col; + } + + for(n=320*30;n<320*235;n=n+320) + { + gp2x_screen15[n+4]=col; + gp2x_screen15[n-4]=col; + } + + for(n=320*30;n<320*199;n=n+320) + { + gp2x_screen15[n-120]=col; + } + + for(n=320*55-120;n<320*55-4;n++) + { + gp2x_screen15[n]=col; + } + +} + +void v_putchar( unsigned x, unsigned y, unsigned color, unsigned textback, unsigned char ch) // rutina usada para dibujar caracteres (coordenadas de 8x8) +{ + int i,j,v; + unsigned char *font; + unsigned char *c; + unsigned short col,col2; + if(x>=WIDTH || y>=HEIGHT) return; + c=&color; + col=gp2x_video_color15(c[0],c[1],c[2],0); + c=&textback; + col2=gp2x_video_color15(c[0],c[1],c[2],0); + v=(y*320*8); + font = &msx[ (int)ch * 8]; + for (i=0; i < 8; i++, font++) + { + for (j=0; j < 8; j++) + { + if ((*font & (128 >> j))) + { + gp2x_screen15[v+(((x<<3)+j))]=col; + } + else gp2x_screen15[v+(((x<<3)+j))]=col2; + } + v+=WIDTH; + } +} + +// display array of chars + +void v_putcad(int x,int y,unsigned color,unsigned textback,char *cad) // dibuja una cadena de texto +{ + while(cad[0]!=0) {v_putchar(x,y,color,textback,cad[0]);cad++;x++;} +} + + +void gp2x_sound_frame(void *unused, unsigned char *stream, int samples) +{ + int n; + short *pu; + pu=stream; + for(n=0;n<(samples);n++) + { + *pu++=0;*pu++=0; + } +} diff --git a/gp2x/display.h b/gp2x/display.h new file mode 100644 index 0000000..c037480 --- /dev/null +++ b/gp2x/display.h @@ -0,0 +1,5 @@ +void ClearScreen(unsigned val); +void DrawBox(unsigned val); +void v_putchar( unsigned x, unsigned y, unsigned color, unsigned textback, unsigned char ch); +void v_putcad(int x,int y,unsigned color,unsigned textback,char *cad); +void gp2x_sound_frame(void *unused, unsigned char *stream, int samples); diff --git a/gp2x/font.c b/gp2x/font.c new file mode 100644 index 0000000..e0d776b --- /dev/null +++ b/gp2x/font.c @@ -0,0 +1,143 @@ +/* + _____ ___ ____ + ____| | ____| PSX2 OpenSource Project + | ___| |____ (C)2001, Gustavo Scotti (gustavo@scotti.com) + ------------------------------------------------------------------------ + font.c + EE UGLY DEBUG ON SCREEN - FONT BASE + This is mostly based on Duke's work +*/ +//#include + +unsigned char msx[]= +"\x00\x00\x00\x00\x00\x00\x00\x00\x3c\x42\xa5\x81\xa5\x99\x42\x3c" +"\x3c\x7e\xdb\xff\xff\xdb\x66\x3c\x6c\xfe\xfe\xfe\x7c\x38\x10\x00" +"\x10\x38\x7c\xfe\x7c\x38\x10\x00\x10\x38\x54\xfe\x54\x10\x38\x00" +"\x10\x38\x7c\xfe\xfe\x10\x38\x00\x00\x00\x00\x30\x30\x00\x00\x00" +"\xff\xff\xff\xe7\xe7\xff\xff\xff\x38\x44\x82\x82\x82\x44\x38\x00" +"\xc7\xbb\x7d\x7d\x7d\xbb\xc7\xff\x0f\x03\x05\x79\x88\x88\x88\x70" +"\x38\x44\x44\x44\x38\x10\x7c\x10\x30\x28\x24\x24\x28\x20\xe0\xc0" +"\x3c\x24\x3c\x24\x24\xe4\xdc\x18\x10\x54\x38\xee\x38\x54\x10\x00" +"\x10\x10\x10\x7c\x10\x10\x10\x10\x10\x10\x10\xff\x00\x00\x00\x00" +"\x00\x00\x00\xff\x10\x10\x10\x10\x10\x10\x10\xf0\x10\x10\x10\x10" +"\x10\x10\x10\x1f\x10\x10\x10\x10\x10\x10\x10\xff\x10\x10\x10\x10" +"\x10\x10\x10\x10\x10\x10\x10\x10\x00\x00\x00\xff\x00\x00\x00\x00" +"\x00\x00\x00\x1f\x10\x10\x10\x10\x00\x00\x00\xf0\x10\x10\x10\x10" +"\x10\x10\x10\x1f\x00\x00\x00\x00\x10\x10\x10\xf0\x00\x00\x00\x00" +"\x81\x42\x24\x18\x18\x24\x42\x81\x01\x02\x04\x08\x10\x20\x40\x80" +"\x80\x40\x20\x10\x08\x04\x02\x01\x00\x10\x10\xff\x10\x10\x00\x00" +"\x00\x00\x00\x00\x00\x00\x00\x00\x20\x20\x20\x20\x00\x00\x20\x00" +"\x50\x50\x50\x00\x00\x00\x00\x00\x50\x50\xf8\x50\xf8\x50\x50\x00" +"\x20\x78\xa0\x70\x28\xf0\x20\x00\xc0\xc8\x10\x20\x40\x98\x18\x00" +"\x40\xa0\x40\xa8\x90\x98\x60\x00\x10\x20\x40\x00\x00\x00\x00\x00" +"\x10\x20\x40\x40\x40\x20\x10\x00\x40\x20\x10\x10\x10\x20\x40\x00" +"\x20\xa8\x70\x20\x70\xa8\x20\x00\x00\x20\x20\xf8\x20\x20\x00\x00" +"\x00\x00\x00\x00\x00\x20\x20\x40\x00\x00\x00\x78\x00\x00\x00\x00" +"\x00\x00\x00\x00\x00\x60\x60\x00\x00\x00\x08\x10\x20\x40\x80\x00" +"\x70\x88\x98\xa8\xc8\x88\x70\x00\x20\x60\xa0\x20\x20\x20\xf8\x00" +"\x70\x88\x08\x10\x60\x80\xf8\x00\x70\x88\x08\x30\x08\x88\x70\x00" +"\x10\x30\x50\x90\xf8\x10\x10\x00\xf8\x80\xe0\x10\x08\x10\xe0\x00" +"\x30\x40\x80\xf0\x88\x88\x70\x00\xf8\x88\x10\x20\x20\x20\x20\x00" +"\x70\x88\x88\x70\x88\x88\x70\x00\x70\x88\x88\x78\x08\x10\x60\x00" +"\x00\x00\x20\x00\x00\x20\x00\x00\x00\x00\x20\x00\x00\x20\x20\x40" +"\x18\x30\x60\xc0\x60\x30\x18\x00\x00\x00\xf8\x00\xf8\x00\x00\x00" +"\xc0\x60\x30\x18\x30\x60\xc0\x00\x70\x88\x08\x10\x20\x00\x20\x00" +"\x70\x88\x08\x68\xa8\xa8\x70\x00\x20\x50\x88\x88\xf8\x88\x88\x00" +"\xf0\x48\x48\x70\x48\x48\xf0\x00\x30\x48\x80\x80\x80\x48\x30\x00" +"\xe0\x50\x48\x48\x48\x50\xe0\x00\xf8\x80\x80\xf0\x80\x80\xf8\x00" +"\xf8\x80\x80\xf0\x80\x80\x80\x00\x70\x88\x80\xb8\x88\x88\x70\x00" +"\x88\x88\x88\xf8\x88\x88\x88\x00\x70\x20\x20\x20\x20\x20\x70\x00" +"\x38\x10\x10\x10\x90\x90\x60\x00\x88\x90\xa0\xc0\xa0\x90\x88\x00" +"\x80\x80\x80\x80\x80\x80\xf8\x00\x88\xd8\xa8\xa8\x88\x88\x88\x00" +"\x88\xc8\xc8\xa8\x98\x98\x88\x00\x70\x88\x88\x88\x88\x88\x70\x00" +"\xf0\x88\x88\xf0\x80\x80\x80\x00\x70\x88\x88\x88\xa8\x90\x68\x00" +"\xf0\x88\x88\xf0\xa0\x90\x88\x00\x70\x88\x80\x70\x08\x88\x70\x00" +"\xf8\x20\x20\x20\x20\x20\x20\x00\x88\x88\x88\x88\x88\x88\x70\x00" +"\x88\x88\x88\x88\x50\x50\x20\x00\x88\x88\x88\xa8\xa8\xd8\x88\x00" +"\x88\x88\x50\x20\x50\x88\x88\x00\x88\x88\x88\x70\x20\x20\x20\x00" +"\xf8\x08\x10\x20\x40\x80\xf8\x00\x70\x40\x40\x40\x40\x40\x70\x00" +"\x00\x00\x80\x40\x20\x10\x08\x00\x70\x10\x10\x10\x10\x10\x70\x00" +"\x20\x50\x88\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xf8\x00" +"\x40\x20\x10\x00\x00\x00\x00\x00\x00\x00\x70\x08\x78\x88\x78\x00" +"\x80\x80\xb0\xc8\x88\xc8\xb0\x00\x00\x00\x70\x88\x80\x88\x70\x00" +"\x08\x08\x68\x98\x88\x98\x68\x00\x00\x00\x70\x88\xf8\x80\x70\x00" +"\x10\x28\x20\xf8\x20\x20\x20\x00\x00\x00\x68\x98\x98\x68\x08\x70" +"\x80\x80\xf0\x88\x88\x88\x88\x00\x20\x00\x60\x20\x20\x20\x70\x00" +"\x10\x00\x30\x10\x10\x10\x90\x60\x40\x40\x48\x50\x60\x50\x48\x00" +"\x60\x20\x20\x20\x20\x20\x70\x00\x00\x00\xd0\xa8\xa8\xa8\xa8\x00" +"\x00\x00\xb0\xc8\x88\x88\x88\x00\x00\x00\x70\x88\x88\x88\x70\x00" +"\x00\x00\xb0\xc8\xc8\xb0\x80\x80\x00\x00\x68\x98\x98\x68\x08\x08" +"\x00\x00\xb0\xc8\x80\x80\x80\x00\x00\x00\x78\x80\xf0\x08\xf0\x00" +"\x40\x40\xf0\x40\x40\x48\x30\x00\x00\x00\x90\x90\x90\x90\x68\x00" +"\x00\x00\x88\x88\x88\x50\x20\x00\x00\x00\x88\xa8\xa8\xa8\x50\x00" +"\x00\x00\x88\x50\x20\x50\x88\x00\x00\x00\x88\x88\x98\x68\x08\x70" +"\x00\x00\xf8\x10\x20\x40\xf8\x00\x18\x20\x20\x40\x20\x20\x18\x00" +"\x20\x20\x20\x00\x20\x20\x20\x00\xc0\x20\x20\x10\x20\x20\xc0\x00" +"\x40\xa8\x10\x00\x00\x00\x00\x00\x00\x00\x20\x50\xf8\x00\x00\x00" +"\x70\x88\x80\x80\x88\x70\x20\x60\x90\x00\x00\x90\x90\x90\x68\x00" +"\x10\x20\x70\x88\xf8\x80\x70\x00\x20\x50\x70\x08\x78\x88\x78\x00" +"\x48\x00\x70\x08\x78\x88\x78\x00\x20\x10\x70\x08\x78\x88\x78\x00" +"\x20\x00\x70\x08\x78\x88\x78\x00\x00\x70\x80\x80\x80\x70\x10\x60" +"\x20\x50\x70\x88\xf8\x80\x70\x00\x50\x00\x70\x88\xf8\x80\x70\x00" +"\x20\x10\x70\x88\xf8\x80\x70\x00\x50\x00\x00\x60\x20\x20\x70\x00" +"\x20\x50\x00\x60\x20\x20\x70\x00\x40\x20\x00\x60\x20\x20\x70\x00" +"\x50\x00\x20\x50\x88\xf8\x88\x00\x20\x00\x20\x50\x88\xf8\x88\x00" +"\x10\x20\xf8\x80\xf0\x80\xf8\x00\x00\x00\x6c\x12\x7e\x90\x6e\x00" +"\x3e\x50\x90\x9c\xf0\x90\x9e\x00\x60\x90\x00\x60\x90\x90\x60\x00" +"\x90\x00\x00\x60\x90\x90\x60\x00\x40\x20\x00\x60\x90\x90\x60\x00" +"\x40\xa0\x00\xa0\xa0\xa0\x50\x00\x40\x20\x00\xa0\xa0\xa0\x50\x00" +"\x90\x00\x90\x90\xb0\x50\x10\xe0\x50\x00\x70\x88\x88\x88\x70\x00" +"\x50\x00\x88\x88\x88\x88\x70\x00\x20\x20\x78\x80\x80\x78\x20\x20" +"\x18\x24\x20\xf8\x20\xe2\x5c\x00\x88\x50\x20\xf8\x20\xf8\x20\x00" +"\xc0\xa0\xa0\xc8\x9c\x88\x88\x8c\x18\x20\x20\xf8\x20\x20\x20\x40" +"\x10\x20\x70\x08\x78\x88\x78\x00\x10\x20\x00\x60\x20\x20\x70\x00" +"\x20\x40\x00\x60\x90\x90\x60\x00\x20\x40\x00\x90\x90\x90\x68\x00" +"\x50\xa0\x00\xa0\xd0\x90\x90\x00\x28\x50\x00\xc8\xa8\x98\x88\x00" +"\x00\x70\x08\x78\x88\x78\x00\xf8\x00\x60\x90\x90\x90\x60\x00\xf0" +"\x20\x00\x20\x40\x80\x88\x70\x00\x00\x00\x00\xf8\x80\x80\x00\x00" +"\x00\x00\x00\xf8\x08\x08\x00\x00\x84\x88\x90\xa8\x54\x84\x08\x1c" +"\x84\x88\x90\xa8\x58\xa8\x3c\x08\x20\x00\x00\x20\x20\x20\x20\x00" +"\x00\x00\x24\x48\x90\x48\x24\x00\x00\x00\x90\x48\x24\x48\x90\x00" +"\x28\x50\x20\x50\x88\xf8\x88\x00\x28\x50\x70\x08\x78\x88\x78\x00" +"\x28\x50\x00\x70\x20\x20\x70\x00\x28\x50\x00\x20\x20\x20\x70\x00" +"\x28\x50\x00\x70\x88\x88\x70\x00\x50\xa0\x00\x60\x90\x90\x60\x00" +"\x28\x50\x00\x88\x88\x88\x70\x00\x50\xa0\x00\xa0\xa0\xa0\x50\x00" +"\xfc\x48\x48\x48\xe8\x08\x50\x20\x00\x50\x00\x50\x50\x50\x10\x20" +"\xc0\x44\xc8\x54\xec\x54\x9e\x04\x10\xa8\x40\x00\x00\x00\x00\x00" +"\x00\x20\x50\x88\x50\x20\x00\x00\x88\x10\x20\x40\x80\x28\x00\x00" +"\x7c\xa8\xa8\x68\x28\x28\x28\x00\x38\x40\x30\x48\x48\x30\x08\x70" +"\x00\x00\x00\x00\x00\x00\xff\xff\xf0\xf0\xf0\xf0\x0f\x0f\x0f\x0f" +"\x00\x00\xff\xff\xff\xff\xff\xff\xff\xff\x00\x00\x00\x00\x00\x00" +"\x00\x00\x00\x3c\x3c\x00\x00\x00\xff\xff\xff\xff\xff\xff\x00\x00" +"\xc0\xc0\xc0\xc0\xc0\xc0\xc0\xc0\x0f\x0f\x0f\x0f\xf0\xf0\xf0\xf0" +"\xfc\xfc\xfc\xfc\xfc\xfc\xfc\xfc\x03\x03\x03\x03\x03\x03\x03\x03" +"\x3f\x3f\x3f\x3f\x3f\x3f\x3f\x3f\x11\x22\x44\x88\x11\x22\x44\x88" +"\x88\x44\x22\x11\x88\x44\x22\x11\xfe\x7c\x38\x10\x00\x00\x00\x00" +"\x00\x00\x00\x00\x10\x38\x7c\xfe\x80\xc0\xe0\xf0\xe0\xc0\x80\x00" +"\x01\x03\x07\x0f\x07\x03\x01\x00\xff\x7e\x3c\x18\x18\x3c\x7e\xff" +"\x81\xc3\xe7\xff\xff\xe7\xc3\x81\xf0\xf0\xf0\xf0\x00\x00\x00\x00" +"\x00\x00\x00\x00\x0f\x0f\x0f\x0f\x0f\x0f\x0f\x0f\x00\x00\x00\x00" +"\x00\x00\x00\x00\xf0\xf0\xf0\xf0\x33\x33\xcc\xcc\x33\x33\xcc\xcc" +"\x00\x20\x20\x50\x50\x88\xf8\x00\x20\x20\x70\x20\x70\x20\x20\x00" +"\x00\x00\x00\x50\x88\xa8\x50\x00\xff\xff\xff\xff\xff\xff\xff\xff" +"\x00\x00\x00\x00\xff\xff\xff\xff\xf0\xf0\xf0\xf0\xf0\xf0\xf0\xf0" +"\x0f\x0f\x0f\x0f\x0f\x0f\x0f\x0f\xff\xff\xff\xff\x00\x00\x00\x00" +"\x00\x00\x68\x90\x90\x90\x68\x00\x30\x48\x48\x70\x48\x48\x70\xc0" +"\xf8\x88\x80\x80\x80\x80\x80\x00\xf8\x50\x50\x50\x50\x50\x98\x00" +"\xf8\x88\x40\x20\x40\x88\xf8\x00\x00\x00\x78\x90\x90\x90\x60\x00" +"\x00\x50\x50\x50\x50\x68\x80\x80\x00\x50\xa0\x20\x20\x20\x20\x00" +"\xf8\x20\x70\xa8\xa8\x70\x20\xf8\x20\x50\x88\xf8\x88\x50\x20\x00" +"\x70\x88\x88\x88\x50\x50\xd8\x00\x30\x40\x40\x20\x50\x50\x50\x20" +"\x00\x00\x00\x50\xa8\xa8\x50\x00\x08\x70\xa8\xa8\xa8\x70\x80\x00" +"\x38\x40\x80\xf8\x80\x40\x38\x00\x70\x88\x88\x88\x88\x88\x88\x00" +"\x00\xf8\x00\xf8\x00\xf8\x00\x00\x20\x20\xf8\x20\x20\x00\xf8\x00" +"\xc0\x30\x08\x30\xc0\x00\xf8\x00\x18\x60\x80\x60\x18\x00\xf8\x00" +"\x10\x28\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\x20\xa0\x40" +"\x00\x20\x00\xf8\x00\x20\x00\x00\x00\x50\xa0\x00\x50\xa0\x00\x00" +"\x00\x18\x24\x24\x18\x00\x00\x00\x00\x30\x78\x78\x30\x00\x00\x00" +"\x00\x00\x00\x00\x30\x00\x00\x00\x3e\x20\x20\x20\xa0\x60\x20\x00" +"\xa0\x50\x50\x50\x00\x00\x00\x00\x40\xa0\x20\x40\xe0\x00\x00\x00" +"\x00\x38\x38\x38\x38\x38\x38\x00\x00\x00\x00\x00\x00\x00\x00"; + + + diff --git a/gp2x/gp2x.c b/gp2x/gp2x.c new file mode 100644 index 0000000..29ee5f4 --- /dev/null +++ b/gp2x/gp2x.c @@ -0,0 +1,93 @@ +/* Parts used from cpuctrl */ +/* cpuctrl for GP2X + Copyright (C) 2005 Hermes/PS2Reality + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + + +#include +#include +#include +#include "../common.h" +#include "gp2x.h" + +extern int main_cpuspeed(int argc, char *argv[]); +extern SDL_Surface* screen; + +u32 gp2x_audio_volume = 74; +u32 gpsp_gp2x_dev_audio = 0; +u32 gpsp_gp2x_dev = 0; + +volatile u16 *gpsp_gp2x_memregs; +volatile u32 *gpsp_gp2x_memregl; + +static volatile u16 *MEM_REG; + +s32 gp2x_load_mmuhack() +{ + s32 mmufd = open("/dev/mmuhack", O_RDWR); + + if(mmufd < 0) + { + system("/sbin/insmod mmuhack.o"); + mmufd = open("/dev/mmuhack", O_RDWR); + } + + if(mmufd < 0) + return -1; + + close(mmufd); + return 0; +} + +void gp2x_overclock() +{ + gpsp_gp2x_dev = open("/dev/mem", O_RDWR); + gpsp_gp2x_dev_audio = open("/dev/mixer", O_RDWR); + gpsp_gp2x_memregl = + (unsigned long *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, + gpsp_gp2x_dev, 0xc0000000); + gpsp_gp2x_memregs = (unsigned short *)gpsp_gp2x_memregl; + + clear_screen(0); + main_cpuspeed(0, NULL); + gp2x_sound_volume(1); +} + +void gp2x_quit() +{ + munmap((void *)gpsp_gp2x_memregl, 0x10000); + close(gpsp_gp2x_dev_audio); + close(gpsp_gp2x_dev); + chdir("/usr/gp2x"); + execl("gp2xmenu", "gp2xmenu", NULL); +} + +void gp2x_sound_volume(u32 volume_up) +{ + u32 volume; + if((volume_up == 0) && (gp2x_audio_volume > 0)) + gp2x_audio_volume--; + + if((volume_up != 0) && (gp2x_audio_volume < 100)) + gp2x_audio_volume++; + + volume = (gp2x_audio_volume * 0x50) / 100; + volume = (gp2x_audio_volume << 8) | gp2x_audio_volume; + ioctl(gpsp_gp2x_dev_audio, SOUND_MIXER_WRITE_PCM, &volume); +} + diff --git a/gp2x/gp2x.h b/gp2x/gp2x.h new file mode 100644 index 0000000..f0b2914 --- /dev/null +++ b/gp2x/gp2x.h @@ -0,0 +1,50 @@ +#ifndef GP2X_H +#define GP2X_H + +enum +{ + GP2X_UP = 1 << 0, + GP2X_LEFT = 1 << 2, + GP2X_DOWN = 1 << 4, + GP2X_RIGHT = 1 << 6, + GP2X_START = 1 << 8, + GP2X_SELECT = 1 << 9, + GP2X_L = 1 << 10, + GP2X_R = 1 << 11, + GP2X_A = 1 << 12, + GP2X_B = 1 << 13, + GP2X_X = 1 << 14, + GP2X_Y = 1 << 15, + GP2X_VOL_DOWN = 1 << 22, + GP2X_VOL_UP = 1 << 23, + GP2X_PUSH = 1 << 27 +}; + + +extern u32 gpsp_gp2x_dev_audio; +extern u32 gpsp_gp2x_dev; +extern volatile u16 *gpsp_gp2x_memregs; +extern volatile u32 *gpsp_gp2x_memregl; + +void gp2x_sound_volume(u32 volume_up); +void gp2x_quit(); + +// call this at first +void cpuctrl_init(void); +void save_system_regs(void); +void cpuctrl_deinit(void); +void set_display_clock_div(unsigned div); + +void set_FCLK(u32 MHZ); +// 0 to 7 divider (freq = FCLK / (1 + div)) +void set_920_Div(u16 div); +void set_DCLK_Div(u16 div); + +void Disable_940(void); +void gp2x_video_wait_vsync(void); +unsigned short get_920_Div(); +void set_940_Div(u16 div); + +s32 gp2x_load_mmuhack(); + +#endif diff --git a/gp2x/gp2xminilib.c b/gp2x/gp2xminilib.c new file mode 100644 index 0000000..098da6b --- /dev/null +++ b/gp2x/gp2xminilib.c @@ -0,0 +1,242 @@ + +/* + GP2X minimal library v0.5 by rlyeh, 2005. + + + GP2X video library with double buffering. + + GP2X soundring buffer library with double buffering. + + GP2X joystick library. + + Thanks to Squidge, Robster, snaff and NK, for the help & previous work! :-) + + + What's new + ========== + + 0.5: patched sound for real stereo (using NK's solution); better init code. + + 0.4: lots of cleanups; sound is threaded now, double buffered too; 8 bpp video support; better exiting code. + + 0.3: shorter library; improved joystick diagonal detection. + + 0.2: better code layout; public release. + + 0.1: beta release +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gp2xminilib.h" + +extern void gp2x_sound_frame(void *blah, void *bufferg, int samples); + + + + unsigned long gp2x_dev[4]={0,0,0,0}, gp2x_physvram[4]; + unsigned short *gp2x_memregs, *gp2x_screen15, *gp2x_logvram15[2], gp2x_sound_buffer[4+(44100*2)*4]; //*2=stereo, *4=max buffers +volatile unsigned short gp2x_palette[512][2]; + unsigned char *gp2x_screen8, *gp2x_logvram8[2]; + pthread_t gp2x_sound_thread=0, gp2x_sound_thread_exit=0; + +void gp2x_video_flip(void) +{ + unsigned long address=gp2x_physvram[gp2x_physvram[3]]; + + gp2x_screen15=gp2x_logvram15[gp2x_physvram[3]^=1]; + gp2x_screen8 =gp2x_logvram8 [gp2x_physvram[3] ]; + + gp2x_memregs[0x290E>>1]=(unsigned short)(address & 0xffff); + gp2x_memregs[0x2910>>1]=(unsigned short)(address >> 16); + gp2x_memregs[0x2912>>1]=(unsigned short)(address & 0xffff); + gp2x_memregs[0x2914>>1]=(unsigned short)(address >> 16); +} + +void gp2x_video_setpalette(void) +{int i; + gp2x_memregs[0x2958>>1]=0; + for(i=0; i<512; i++) gp2x_memregs[0x295A>>1]=gp2x_palette[i][0], gp2x_memregs[0x295A>>1]=gp2x_palette[i][1]; +} + +unsigned long gp2x_joystick_read(void) +{ + unsigned long value=(gp2x_memregs[0x1198>>1] & 0x00FF); + + if(value==0xFD) value=0xFA; + if(value==0xF7) value=0xEB; + if(value==0xDF) value=0xAF; + if(value==0x7F) value=0xBE; + + return ~((gp2x_memregs[0x1184>>1] & 0xFF00) | value | (gp2x_memregs[0x1186>>1] << 16)); +} + +#if 0 +void *gp2x_sound_play(void *blah) +{ + struct timespec ts; + int flip=0; + + ts.tv_sec=0, ts.tv_nsec=gp2x_sound_buffer[2]; + + while(! gp2x_sound_thread_exit) + { + gp2x_sound_frame(blah, (void *)(&gp2x_sound_buffer[4+flip]), gp2x_sound_buffer[0]); + write(gp2x_dev[3], (void *)(&gp2x_sound_buffer[4+flip]), gp2x_sound_buffer[1]); + + flip^=gp2x_sound_buffer[1]; + + //nanosleep(&ts, NULL); + } + + return NULL; +} +#endif + +void gp2x_deinit(void) +{int i; + if(gp2x_sound_thread) { gp2x_sound_thread_exit=1; for(i=0;i<1000000;i++); } + + gp2x_memregs[0x28DA>>1]=0x4AB; + gp2x_memregs[0x290C>>1]=640; + + close(gp2x_dev[0]); + close(gp2x_dev[1]); + close(gp2x_dev[2]); + //close(gp2x_dev[3]); + //fcloseall(); +} + +void gp2x_init(int bpp, int rate, int bits, int stereo, int Hz) +{ + struct fb_fix_screeninfo fixed_info; + + if(!gp2x_dev[0]) gp2x_dev[0] = open("/dev/fb0", O_RDWR); + if(!gp2x_dev[1]) gp2x_dev[1] = open("/dev/fb1", O_RDWR); + if(!gp2x_dev[2]) gp2x_dev[2] = open("/dev/mem", O_RDWR); + //if(!gp2x_dev[3]) gp2x_dev[3] = open("/dev/dsp", O_WRONLY); + + gp2x_memregs=(unsigned short *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0xc0000000); + + if(!gp2x_sound_thread) { gp2x_memregs[0x0F16>>1] = 0x830a; sleep(1); + gp2x_memregs[0x0F58>>1] = 0x100c; sleep(1); } + + ioctl (gp2x_dev[0], FBIOGET_FSCREENINFO, &fixed_info); + gp2x_screen15=gp2x_logvram15[0]=(unsigned short *)mmap(0, 320*240*2, PROT_WRITE, MAP_SHARED, gp2x_dev[0], 0); + gp2x_screen8=gp2x_logvram8[0]=(unsigned char *)gp2x_logvram15[0]; + gp2x_physvram[0]=fixed_info.smem_start; + + ioctl (gp2x_dev[1], FBIOGET_FSCREENINFO, &fixed_info); + gp2x_logvram15[1]=(unsigned short *)mmap(0, 320*240*2, PROT_WRITE, MAP_SHARED, gp2x_dev[1], 0); + gp2x_logvram8[1]=(unsigned char *)gp2x_logvram15[1]; + gp2x_physvram[1]=fixed_info.smem_start; + + gp2x_memregs[0x28DA>>1]=(((bpp+1)/8)<<9)|0xAB; /*8/15/16/24bpp...*/ + gp2x_memregs[0x290C>>1]=320*((bpp+1)/8); /*line width in bytes*/ + + ioctl(gp2x_dev[3], SNDCTL_DSP_SPEED, &rate); + ioctl(gp2x_dev[3], SNDCTL_DSP_SETFMT, &bits); + ioctl(gp2x_dev[3], SNDCTL_DSP_STEREO, &stereo); + + gp2x_sound_buffer[1]=(gp2x_sound_buffer[0]=(rate/Hz)) << (stereo + (bits==16)); + gp2x_sound_buffer[2]=(1000000/Hz); + + if(!gp2x_sound_thread) { gp2x_sound_thread = 1; //pthread_create( &gp2x_sound_thread, NULL, gp2x_sound_play, NULL); + atexit(gp2x_deinit); } +} + + + +/* + +EXAMPLE +======= + + now supply your own function for 16 bits, stereo: + + void gp2x_sound_frame(void *blah, void *bufferg, int samples) + { + signed short *buffer=(signed short *)bufferg; + while(samples--) + { + *buffer++=0; //Left channel + *buffer++=0; //Right channel + } + } + + or 16 bits mono: + + void gp2x_sound_frame(void *blah, void *bufferg, int samples) + { + signed short *buffer=(signed short *)bufferg; + while(samples--) + { + *buffer++=0; //Central channel + } + } + + now the main program... + + hicolor example: + + int main(int argc, char *argv[]) + { + //this sets video to hicolor (16 bpp) + //it also sets sound to 44100,16bits,stereo and syncs audio to 50 Hz (PAL timing) + + //Warning: GP2X does not support 8bit sound sampling! (at least within Linux) + + gp2x_init(16,44100,16,1,50); + + while(1) + { + unsigned long pad=gp2x_joystick_read(); + unsigned short color=gp2x_video_color15(255,255,255,0); + + if(pad & GP2X_L) if(pad & GP2X_R) exit(); + + if(pad & GP2X_A) color=gp2x_color15(255,255,255,0); //white + else color=gp2x_color15(255,0,0,0); //red + + gp2x_screen15[160+120*320]=color; //x=160, y=120 + gp2x_video_flip(); + } + } + + palettized example: + + int main(int argc, char *argv[]) + { + //this sets video to palette mode (8 bpp) + //it also sets sound to 11025,16bits,stereo and syncs audio to 60 Hz (NSTC timing) + + //Warning: GP2X does not support 8bit sound sampling! (at least within Linux) + + gp2x_init(8,11025,16,1,60); + + gp2x_video_color8(0,0,0,0); //color #0 is black for us + gp2x_video_color8(1,255,255,255); //color #1 is white for us + gp2x_video_color8(2,255,0,0); //color #2 is red for us + gp2x_video_setpalette(); + + while(1) + { + unsigned long pad=gp2x_joystick_read(); + unsigned char color; + + if(pad & GP2X_L) if(pad & GP2X_R) exit(); + + if(pad & GP2X_A) color=1; //white + else color=2; //red + + gp2x_screen8[160+120*320]=color; //x=160, y=120 + gp2x_video_flip(); + } + } + +*/ + diff --git a/gp2x/gp2xminilib.h b/gp2x/gp2xminilib.h new file mode 100644 index 0000000..cf3c00b --- /dev/null +++ b/gp2x/gp2xminilib.h @@ -0,0 +1,58 @@ +/* + GP2X minimal library v0.5 by rlyeh, 2005. + + + GP2X video library with double buffering. + + GP2X soundring buffer library with double buffering. + + GP2X joystick library. + + Thanks to Squidge, Robster, snaff and NK, for the help & previous work! :-) + + + What's new + ========== + + 0.5: patched sound for real stereo (using NK's solution); better init code. + + 0.4: lots of cleanups; sound is threaded now, double buffered too; 8 bpp video support; better exiting code. + + 0.3: shorter library; improved joystick diagonal detection. + + 0.2: better code layout; public release. + + 0.1: beta release +*/ + +/* .h by Hermes/PS2Reality*/ + +#if !defined(GP2XMINILIB) +#define GP2XMINILIB + +enum { GP2X_UP=0x1, GP2X_LEFT=0x4, GP2X_DOWN=0x10, GP2X_RIGHT=0x40, + GP2X_START=1<<8, GP2X_SELECT=1<<9, GP2X_L=1<<10, GP2X_R=1<<11, + GP2X_A=1<<12, GP2X_B=1<<13, GP2X_X=1<<14, GP2X_Y=1<<15, + GP2X_VOL_UP=1<<22, GP2X_VOL_DOWN=1<<23, GP2X_PUSH=1<<27, }; + +#define gp2x_video_color15(R,G,B,A) (((R&0xF8)<<8)|((G&0xF8)<<3)|((B&0xF8)>>3)|(A<<5)) +#define gp2x_video_color8 (C,R,G,B) gp2x_palette[C][0]=(G<<8)|B,gp2x_palette[C][1]=R; + + + + + +extern unsigned short *gp2x_memregs, *gp2x_screen15, *gp2x_logvram15[2], gp2x_sound_buffer[4+(44100*2)*4]; //*2=stereo, *4=max buffers + + + +extern unsigned long gp2x_dev[4]; + + +void gp2x_video_flip(void); +void gp2x_video_setpalette(void); +unsigned long gp2x_joystick_read(void); +void *gp2x_sound_play(void *blah); +void gp2x_deinit(void); +void gp2x_init(int bpp, int rate, int bits, int stereo, int Hz); + + + +#endif diff --git a/gp2x/load_imm_test.c b/gp2x/load_imm_test.c new file mode 100644 index 0000000..b850d56 --- /dev/null +++ b/gp2x/load_imm_test.c @@ -0,0 +1,135 @@ +#include + +typedef unsigned int u32; + +u32 arm_imm_find_nonzero(u32 imm, u32 start_bit) +{ + u32 i; + + for(i = start_bit; i < 32; i += 2) + { + if((imm >> i) & 0x03) + break; + } + + return i; +} + +u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) +{ + u32 store_count = 0; + u32 left_shift = 0; + + // Otherwise it'll return 0 things to store because it'll never + // find anything. + if(imm == 0) + { + rotations[0] = 0; + stores[0] = 0; + return 1; + } + + // Find chunks of non-zero data at 2 bit alignments. + while(1) + { + left_shift = arm_imm_find_nonzero(imm, left_shift); + + if(left_shift == 32) + { + // We've hit the end of the useful data. + return store_count; + } + + // Hit the end, it might wrap back around to the beginning. + if(left_shift >= 24) + { + // Make a mask for the residual bits. IE, if we have + // 5 bits of data at the end we can wrap around to 3 + // bits of data in the beginning. Thus the first + // thing, after being shifted left, has to be less + // than 111b, 0x7, or (1 << 3) - 1. + u32 top_bits = 32 - left_shift; + u32 residual_bits = 8 - top_bits; + u32 residual_mask = (1 << residual_bits) - 1; + + if((store_count > 1) && (left_shift > 24) && + ((stores[0] << (32 - rotations[0])) < residual_mask)) + { + // Then we can throw out the last bit and tack it on + // to the first bit. + u32 initial_bits = rotations[0]; + stores[0] = (stores[0] << (top_bits + (32 - rotations[0]))) | + ((imm >> left_shift) & 0xFF); + rotations[0] = top_bits; + + return store_count; + } + else + { + // There's nothing to wrap over to in the beginning + stores[store_count] = (imm >> left_shift) & 0xFF; + rotations[store_count] = (32 - left_shift) & 0x1F; + return store_count + 1; + } + break; + } + + stores[store_count] = (imm >> left_shift) & 0xFF; + rotations[store_count] = (32 - left_shift) & 0x1F; + + store_count++; + left_shift += 8; + } +} + +#define ror(value, shift) \ + ((value) >> shift) | ((value) << (32 - shift)) \ + +u32 arm_assemble_imm_32bit(u32 *stores, u32 *rotations, u32 store_count) +{ + u32 n = ror(stores[0], rotations[0]); + u32 i; + printf("%x : %x\n", stores[0], rotations[0]); + + for(i = 1; i < store_count; i++) + { + printf("%x : %x\n", stores[i], rotations[i]); + n |= ror(stores[i], rotations[i]); + } + + return n; +} + + +int main(int argc, char *argv[]) +{ + u32 n = 0; + u32 stores[4]; + u32 rotations[4]; + u32 store_count; + u32 n2; + + if(argc != 1) + { + n = strtoul(argv[1], NULL, 16); + store_count = arm_disect_imm_32bit(n, stores, rotations); + n2 = arm_assemble_imm_32bit(stores, rotations, store_count); + printf("%08x -> %08x (%d stores)\n", n, n2, store_count); + return 0; + } + + do + { + store_count = arm_disect_imm_32bit(n, stores, rotations); + n2 = arm_assemble_imm_32bit(stores, rotations, store_count); + if(n != n2) + { + printf("Failure: %08x -/-> %08x\n", n, n2); + return -1; + } + n++; + } while(n != 0); + + printf("Done!\n"); + return 0; +} diff --git a/gp2x/readme_gp2x.txt b/gp2x/readme_gp2x.txt new file mode 100644 index 0000000..434250a --- /dev/null +++ b/gp2x/readme_gp2x.txt @@ -0,0 +1,262 @@ +-- gameplaySP2X Gameboy Advance emulator for GP2X -- + +gpSP2X is a version of my (Exophase)'s emulator originally for Sony PSP. +A large amount of effort has been done to make it more optimized for the +ARM CPU present in the GP2X, however it is still very much a work in +progress. + +See readme.txt for the PSP version readme, which contains a lot of +information relevant to the GP2X version (note that some of it does +not apply however). + + +Changelog: + +0.9-2xb: +-- IMPORTANT-- If you're overwriting an old version, be sure to delete the + gpsp.cfg file first, or be prepared to have a bunch of weird button + settings that would require fixing. + +- Fixed some bugs stunting compatability. +- Optimized alpha blends in renderer. +- Some more optimizations to dynarec output. +- Savestates should work better now. +- Cheat/misc menu won't crash the emulator. +- Main button config window works (not all buttons are in yet) + +0.9-2Xa: (Exophase release) +- Redid autoframeskip. Should work more reliably. +- Rewrote dynamic recompiler from x86 source (arm_emit.h, arm_stub.S). + Has some more sophisticated behavior than the last version, more is + still to come... Should notice a slight speed improvement over the + last version. +- Tweaked GUI to be a little more useable. Buttons are now mirroring the + PSP version's. +- Code unification + cleanup amongst versions. + + +v9008: (zodttd release) +- Updated the way autoframeskip works. Should be better now. Still has a max + frameskip value. +- Added a slight performance increase to the dynarec. +- Added sync() to make sure files such as savestates and in-game saves are + saved properly to the GP2X. + +v9006: (zodttd release) +- Initial public release + + +Installation: + +1. Place the "gpsp.gpe" and "game_config.txt" file in a directory on your SD + card used with the GP2X. + +2. Place your GBA BIOS in the directory from step 1. This file must be named + "gba_bios.bin" in all lowercase as shown, so rename it if needed. + + -- NOTE -- + + There are two commonly available BIOSes - one is the correct one used in + production GBA's worldwide and the other is a prototype BIOS. The latter + will not cause some games to not work correctly or crash. If you attempt + to use this BIOS you will be presented with a warning before being + allowed to continue. This screen will give you a checksum of the real + BIOS image (see readme.txt for further information). + +3. Place your GBA games in the directory from step 1. These files should have + a ".gba" or ".bin" file extension. Zip compressed games should be supported + and are recognized with the ".zip" file extension. Note that 32MB ROMs will + probably not run if zipped. 16MB and smaller should be OK. + +4. Done. Run gpsp.gpe. + + +Controls: + +How to use gpSP on the GP2X: +Buttons are mapped as follows (GBA/ingame buttons can be changed in the menu): + +GP2X--------------------GBA +X -> A +B -> B +L TRIG -> L TRIG +R TRIG -> R TRIG +START -> START +SELECT -> SELECT + +GP2X--------------------------------gpSP + +-- IN-GAME -- + +VOL MIDDLE (UP + DOWN) -> menu +PUSH STICK -> fps display toggle (second number is + frames actually drawn) + +-- IN-MENU -- +B -> select option +X -> cancel/exit menu +A -> escape (up one director level in the + file selector) + +When gpSP is started, you are presented with the option to overclock your +GP2X. Use the L/R TRIG to change the CPU clockspeed and press START to +continue. You may also change RAM timings here - experiment with what +works well. Note that going too high on overclocking or low on RAM +timings can cause the game to crash or the GP2X to outright freeze up. + +If you do not want to overclock, press START without using L/R. +You will now be presented with a menu to choose a game. Press the IN-MENU +"SELECT" button shown above to pick a game to load. + +If you would like to test gpSP for the GP2X with a homebrew (free public +domain) game, a game by Russ Prince works very well with gpSP. It is called +Bust-A-Move and is a remake of the classic game it's named after. + + +How to build from source: + +The makefile included in the source is geared towards the Open2x toolchain. +If you use Open2x and installed it in the way recommended then it should +work okay, assuming you also have up to date HW-SDL (and have +arm-linux-sdl-config installed in the right place). The makefile is in the +gp2x directory, so go there first then just type make to build gpsp.gpe. +Might need a little tweaking if your setup is different. If you need help +you can ask me, but I'll probably nag you about why you want to build it in +the first place. + + +GP2X version FAQ: + +Q) Help! This game doesn't work. Am I using a bad version of the ROM? + +A) First, make sure you're using the correct BIOS version. If you aren't + gpSP should tell you. Other than that, there are some games that are + known to not work now (and will probably work later), and perhaps + many more games that I don't know about that don't work. I haven't + launched a full scale compatability test at this version, so it might + take a while before the compatability levels are high. + + +Q) Why is this version slower than the PSP version? + +A) gpSP is still a work in progress. It might be possible to obtain more + speed from both this version and the PSP one too (and others in the + future). With that in mind, know that even a very agressively overclocked + GP2X is still less powerful than a PSP, generally speaking. Still, I + have a lot of ideas. It's unlikely that the GP2X version will ever be as + fast/faster than the PSP version for anyone but anything's possible. + + +Q) How high does my GP2X have to overclock to enjoy gpSP? + +A) That depends on you. Higher overclocking will mean less frames skipped + on autoframeskip, or less frameskip needed if on manual. Or it can + make the difference between whether or not virtual 60fps can be reached. + For some games no GP2X in the world will be able to run them fullspeed, + with any amount of frameskip. A few might run well with no overclocking + and a generous level of frameskip (probably manual). If you don't care + about battery life (or you're plugged into an outlet) you should push + it as high as you can while still maintaining stability, because + chances are high that whatever you play will benefit from it. Right now + you'll probably want 260MHz if you can achieve it, but with a lot of + luck this number will lower slightly in the future (and is just a vague + ballpark figure anyway). I don't want to scare anyone off from using the + emulator, you should give it a try and see how it plays for you + regardless of how high you can overclock. Just note that this is far + from a locked smooth experience for everyone on every game. + + +Q) GBA has an ARM processor, GP2X has an ARM processor. GP2X is more + powerful than GBA. This emulator should run great without overclocking, + so therefore you're doing it wrong. + +A) That's not a question, but I'll field it anyway. Two things: first, + "virtualization", or running the GBA code "natively" on the GP2X is + probably not possible, at least not with the way I want to do things. + For reasons why go read my blog (see below). So yes, you actually + do need more than 16.7MHz of ARM9 power to emulate the GBA's CPU. + Second: there is a whole lot of work behind emulating the pretty 2D + graphics on the GBA, something it can do in hardware a lot better than + this platform can. + End result: GBA emulation on GP2X isn't as easy as you think it is. + + +Q) What are you working on now? When will you release the next version? + +A) See the gpSP development blog: + + http://gpsp-dev.blogspot.com/ + + Note that I don't give release dates, ever, unless I'm right on the verge + of releasing. Be grateful that I've decided to be much more open about + the development of the emulator now. + + +Q) Thanks to your blog I heard that you made some improvement. Can I have + a copy of the new code? + +A) No. Builds in transition often have a lot of problems, and I like for + releases to be relatively substantial. I can probably be bribed out of + them with donations though. :P + + +Q) Why do the menu suck so much? Why do half the options not work or not + make any sense? + +A) Sorry, the menu still hasn't been modified very much to fit the GP2X + version instead of the PSP version.. hopefully this will improve in the + future. + + +Q) Who's in charge of the GP2X version anyway? + +A) Originally, zodttd was. I, Exophase, have basically usurped control of it + now to encourage zodttd to work more on his PS1 emulator (that and I'm + possessive of gpSP and get nervous when people work on it too heavily). + zodttd will most likely still be around to work on things though. + + +Q) I'm a super nice person and would like to donate some of my hard earned + money to this one-off GBA emulator. Where do I send my money to? + +A) Exophase: exophase@gmail.com on PayPal + zodttd: https://www.paypal.com/cgi-bin/webscr?cmd=_xclick&business=heirloomer + %40pobox%2ecom&item_number=1&no_shipping=1&no_note=1&tax=0&cy_code=USD&bn= + PP%2dDonationsBF&charset=UTF%2d8 + ^ Click there for donating on PayPal (remove whitespace/linebreaks). + + GP2X people have already donated a lot more to me than PSP people have, + even though there's an order of magnitude or two less users. And they've + donated far more to zodttd than they have to me. So I'm not going to ask + people to donate.. + + However I won't lie: donating ups the chances of me actually working on the + next version (for which I have a lot of ideas, but not necessarily time to + dedicate to.. that time might need more incentive to be allotted from other + things). This could change depending on my employment situation, but right + now I feel guilty doing anything that doesn't help guarantee that I'll be + able to buy food a year from now. + + +Q) Tell me all of your personal information. + +A) Again not a question, but why not. I'm Exophase, real name: Gilead Kutnick, + male, 23 years old, current residence Bloomington, IN; straight/single/not + actively looking, almost have an MS in Computer Science (do have a BS + underneath it), likes PSP more than GP2X, will not write a Nintendo DS + emulator for either, am currently looking for a job for after I graduate. + + +Q) You said you're looking for a job. + +A) Yes. If you have one or know someone who needs a low level oriented + programmer then I'm up for grabs. And this is my resume: + http://exophase.devzero.co.uk/resume.pdf + + +Credits: + +Original codebase: Exophase (exophase@gmail.com) +Foundation gp2x code: zodttd +GP2X dynarec/stubs + current code maintainance: Exophase + diff --git a/gp2x/rom_cache.S b/gp2x/rom_cache.S new file mode 100644 index 0000000..1824bc2 --- /dev/null +++ b/gp2x/rom_cache.S @@ -0,0 +1,37007 @@ + +//Gp2x/gp2x/mnt/nand/rom_cache.bin: file format binary + +Disassembly of section .data: + +00000000 <.data>: + 0: 08000000 stmeqda r0, {} + 4: 00000000 andeq r0, r0, r0 + 8: ebf60fdc bl 0xffd83f80 + c: 08000000 stmeqda r0, {} + 10: e28cc006 add ip, ip, #6 ; 0x6 + 14: e1a00fac mov r0, ip, lsr #31 + 18: e08ff100 add pc, pc, r0, lsl #2 + 1c: 080000c0 stmeqda r0, {r6, r7} + 20: ebf60b95 bl 0xffd82e7c + 24: ea000001 b 0x30 + 28: 080000c0 stmeqda r0, {r6, r7} + 2c: 00000000 andeq r0, r0, r0 + 30: ebf60fd2 bl 0xffd83f80 + 34: 080000c0 stmeqda r0, {r6, r7} + 38: e3a03012 mov r3, #18 ; 0x12 + 3c: ebf60fcf bl 0xffd83f80 + 40: 080000c4 stmeqda r0, {r2, r6, r7} + 44: e1a00003 mov r0, r3 + 48: e3a010ff mov r1, #255 ; 0xff + 4c: e38114ff orr r1, r1, #-16777216 ; 0xff000000 + 50: ebf60c3b bl 0xffd83144 + 54: 080000c4 stmeqda r0, {r2, r6, r7} + 58: ebf60fc8 bl 0xffd83f80 + 5c: 080000c8 stmeqda r0, {r3, r6, r7} + 60: e3a00e0d mov r0, #208 ; 0xd0 + 64: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 68: e2800f0a add r0, r0, #40 ; 0x28 + 6c: ebf60e29 bl 0xffd83918 + 70: 080000d0 stmeqda r0, {r4, r6, r7} + 74: e58d0434 str r0, [sp, #1076] + 78: ebf60fc0 bl 0xffd83f80 + 7c: 080000cc stmeqda r0, {r2, r3, r6, r7} + 80: e3a0301f mov r3, #31 ; 0x1f + 84: ebf60fbd bl 0xffd83f80 + 88: 080000d0 stmeqda r0, {r4, r6, r7} + 8c: e1a00003 mov r0, r3 + 90: e3a010ff mov r1, #255 ; 0xff + 94: e38114ff orr r1, r1, #-16777216 ; 0xff000000 + 98: ebf60c29 bl 0xffd83144 + 9c: 080000d0 stmeqda r0, {r4, r6, r7} + a0: ebf60fb6 bl 0xffd83f80 + a4: 080000d4 stmeqda r0, {r2, r4, r6, r7} + a8: e3a00f37 mov r0, #220 ; 0xdc + ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b0: e2800f06 add r0, r0, #24 ; 0x18 + b4: ebf60e17 bl 0xffd83918 + b8: 080000dc stmeqda r0, {r2, r3, r4, r6, r7} + bc: e58d0434 str r0, [sp, #1076] + c0: ebf60fae bl 0xffd83f80 + c4: 080000d8 stmeqda r0, {r3, r4, r6, r7} + c8: e3a00e0e mov r0, #224 ; 0xe0 + cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d0: e2800f4f add r0, r0, #316 ; 0x13c + d4: ebf60e0f bl 0xffd83918 + d8: 080000e0 stmeqda r0, {r5, r6, r7} + dc: e1a04000 mov r4, r0 + e0: ebf60fa6 bl 0xffd83f80 + e4: 080000dc stmeqda r0, {r2, r3, r4, r6, r7} + e8: e3a01f39 mov r1, #228 ; 0xe4 + ec: e3811302 orr r1, r1, #134217728 ; 0x8000000 + f0: e2813018 add r3, r1, #24 ; 0x18 + f4: ebf60fa1 bl 0xffd83f80 + f8: 080000e0 stmeqda r0, {r5, r6, r7} + fc: e2840000 add r0, r4, #0 ; 0x0 + 100: e1a01003 mov r1, r3 + 104: ebf60d30 bl 0xffd835cc + 108: 080000e4 stmeqda r0, {r2, r5, r6, r7} + 10c: ebf60f9b bl 0xffd83f80 + 110: 080000e4 stmeqda r0, {r2, r5, r6, r7} + 114: e3a00f3b mov r0, #236 ; 0xec + 118: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11c: e2800f4d add r0, r0, #308 ; 0x134 + 120: ebf60dfc bl 0xffd83918 + 124: 080000ec stmeqda r0, {r2, r3, r5, r6, r7} + 128: e1a04000 mov r4, r0 + 12c: ebf60f93 bl 0xffd83f80 + 130: 080000e8 stmeqda r0, {r3, r5, r6, r7} + 134: e3a00e0f mov r0, #240 ; 0xf0 + 138: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13c: e1a08000 mov r8, r0 + 140: ebf60f8e bl 0xffd83f80 + 144: 080000ec stmeqda r0, {r2, r3, r5, r6, r7} + 148: e1a00004 mov r0, r4 + 14c: e28cc051 add ip, ip, #81 ; 0x51 + 150: eaf60bc1 b 0xffd8305c + 154: 0800022c stmeqda r0, {r2, r3, r5, r9} + 158: 00000000 andeq r0, r0, r0 + 15c: ebf60f87 bl 0xffd83f80 + 160: 0800022c stmeqda r0, {r2, r3, r5, r9} + 164: e59d9434 ldr r9, [sp, #1076] + 168: e3c99003 bic r9, r9, #3 ; 0x3 + 16c: e2499014 sub r9, r9, #20 ; 0x14 + 170: e58d9434 str r9, [sp, #1076] + 174: e2890000 add r0, r9, #0 ; 0x0 + 178: e1a01007 mov r1, r7 + 17c: ebf60d32 bl 0xffd8364c + 180: e2890004 add r0, r9, #4 ; 0x4 + 184: e1a01008 mov r1, r8 + 188: ebf60d2f bl 0xffd8364c + 18c: e2890008 add r0, r9, #8 ; 0x8 + 190: e59d1418 ldr r1, [sp, #1048] + 194: ebf60d2c bl 0xffd8364c + 198: e289000c add r0, r9, #12 ; 0xc + 19c: e59d141c ldr r1, [sp, #1052] + 1a0: ebf60d29 bl 0xffd8364c + 1a4: e2890010 add r0, r9, #16 ; 0x10 + 1a8: e59d1438 ldr r1, [sp, #1080] + 1ac: ebf60d26 bl 0xffd8364c + 1b0: ebf60f72 bl 0xffd83f80 + 1b4: 0800022e stmeqda r0, {r1, r2, r3, r5, r9} + 1b8: e59d1420 ldr r1, [sp, #1056] + 1bc: e1a00001 mov r0, r1 + 1c0: e58d041c str r0, [sp, #1052] + 1c4: ebf60f6d bl 0xffd83f80 + 1c8: 08000230 stmeqda r0, {r4, r5, r9} + 1cc: e59d9434 ldr r9, [sp, #1076] + 1d0: e3c99003 bic r9, r9, #3 ; 0x3 + 1d4: e2499004 sub r9, r9, #4 ; 0x4 + 1d8: e58d9434 str r9, [sp, #1076] + 1dc: e2890000 add r0, r9, #0 ; 0x0 + 1e0: e59d141c ldr r1, [sp, #1052] + 1e4: ebf60cf8 bl 0xffd835cc + 1e8: 08000232 stmeqda r0, {r1, r4, r5, r9} + 1ec: ebf60f63 bl 0xffd83f80 + 1f0: 08000232 stmeqda r0, {r1, r4, r5, r9} + 1f4: e59d0434 ldr r0, [sp, #1076] + 1f8: e2400f02 sub r0, r0, #8 ; 0x8 + 1fc: e58d0434 str r0, [sp, #1076] + 200: ebf60f5e bl 0xffd83f80 + 204: 08000234 stmeqda r0, {r2, r4, r5, r9} + 208: e3a00ffe mov r0, #1016 ; 0x3f8 + 20c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 210: ebf60dc0 bl 0xffd83918 + 214: 08000238 stmeqda r0, {r3, r4, r5, r9} + 218: e1a05000 mov r5, r0 + 21c: ebf60f57 bl 0xffd83f80 + 220: 08000236 stmeqda r0, {r1, r2, r4, r5, r9} + 224: e2850000 add r0, r5, #0 ; 0x0 + 228: ebf60d8e bl 0xffd83868 + 22c: 0800023a stmeqda r0, {r1, r3, r4, r5, r9} + 230: e1a03000 mov r3, r0 + 234: ebf60f51 bl 0xffd83f80 + 238: 08000238 stmeqda r0, {r3, r4, r5, r9} + 23c: e3b06080 movs r6, #128 ; 0x80 + 240: ebf60f4e bl 0xffd83f80 + 244: 0800023a stmeqda r0, {r1, r3, r4, r5, r9} + 248: e1b06386 movs r6, r6, lsl #7 + 24c: ebf60f4b bl 0xffd83f80 + 250: 0800023c stmeqda r0, {r2, r3, r4, r5, r9} + 254: e1a01006 mov r1, r6 + 258: e2964000 adds r4, r6, #0 ; 0x0 + 25c: ebf60f47 bl 0xffd83f80 + 260: 0800023e stmeqda r0, {r1, r2, r3, r4, r5, r9} + 264: e1a01003 mov r1, r3 + 268: e1933004 orrs r3, r3, r4 + 26c: ebf60f43 bl 0xffd83f80 + 270: 08000240 stmeqda r0, {r6, r9} + 274: e2850000 add r0, r5, #0 ; 0x0 + 278: e1a01003 mov r1, r3 + 27c: ebf60cb2 bl 0xffd8354c + 280: 08000242 stmeqda r0, {r1, r6, r9} + 284: ebf60f3d bl 0xffd83f80 + 288: 08000242 stmeqda r0, {r1, r6, r9} + 28c: e2850000 add r0, r5, #0 ; 0x0 + 290: ebf60d74 bl 0xffd83868 + 294: 08000246 stmeqda r0, {r1, r2, r6, r9} + 298: e1a03000 mov r3, r0 + 29c: ebf60f37 bl 0xffd83f80 + 2a0: 08000244 stmeqda r0, {r2, r6, r9} + 2a4: e3b04014 movs r4, #20 ; 0x14 + 2a8: ebf60f34 bl 0xffd83f80 + 2ac: 08000246 stmeqda r0, {r1, r2, r6, r9} + 2b0: e1a01003 mov r1, r3 + 2b4: e1933004 orrs r3, r3, r4 + 2b8: ebf60f30 bl 0xffd83f80 + 2bc: 08000248 stmeqda r0, {r3, r6, r9} + 2c0: e2850000 add r0, r5, #0 ; 0x0 + 2c4: e1a01003 mov r1, r3 + 2c8: ebf60c9f bl 0xffd8354c + 2cc: 0800024a stmeqda r0, {r1, r3, r6, r9} + 2d0: ebf60f2a bl 0xffd83f80 + 2d4: 0800024a stmeqda r0, {r1, r3, r6, r9} + 2d8: e2850000 add r0, r5, #0 ; 0x0 + 2dc: ebf60d61 bl 0xffd83868 + 2e0: 0800024e stmeqda r0, {r1, r2, r3, r6, r9} + 2e4: e1a03000 mov r3, r0 + 2e8: ebf60f24 bl 0xffd83f80 + 2ec: 0800024c stmeqda r0, {r2, r3, r6, r9} + 2f0: e3b040a0 movs r4, #160 ; 0xa0 + 2f4: ebf60f21 bl 0xffd83f80 + 2f8: 0800024e stmeqda r0, {r1, r2, r3, r6, r9} + 2fc: e1a01003 mov r1, r3 + 300: e1933004 orrs r3, r3, r4 + 304: ebf60f1d bl 0xffd83f80 + 308: 08000250 stmeqda r0, {r4, r6, r9} + 30c: e2850000 add r0, r5, #0 ; 0x0 + 310: e1a01003 mov r1, r3 + 314: ebf60c8c bl 0xffd8354c + 318: 08000252 stmeqda r0, {r1, r4, r6, r9} + 31c: ebf60f17 bl 0xffd83f80 + 320: 08000252 stmeqda r0, {r1, r4, r6, r9} + 324: e2850000 add r0, r5, #0 ; 0x0 + 328: ebf60d4e bl 0xffd83868 + 32c: 08000256 stmeqda r0, {r1, r2, r4, r6, r9} + 330: e1a03000 mov r3, r0 + 334: ebf60f11 bl 0xffd83f80 + 338: 08000254 stmeqda r0, {r2, r4, r6, r9} + 33c: e3b060a0 movs r6, #160 ; 0xa0 + 340: ebf60f0e bl 0xffd83f80 + 344: 08000256 stmeqda r0, {r1, r2, r4, r6, r9} + 348: e1b06186 movs r6, r6, lsl #3 + 34c: ebf60f0b bl 0xffd83f80 + 350: 08000258 stmeqda r0, {r3, r4, r6, r9} + 354: e1a01006 mov r1, r6 + 358: e2964000 adds r4, r6, #0 ; 0x0 + 35c: ebf60f07 bl 0xffd83f80 + 360: 0800025a stmeqda r0, {r1, r3, r4, r6, r9} + 364: e1a01003 mov r1, r3 + 368: e1933004 orrs r3, r3, r4 + 36c: ebf60f03 bl 0xffd83f80 + 370: 0800025c stmeqda r0, {r2, r3, r4, r6, r9} + 374: e2850000 add r0, r5, #0 ; 0x0 + 378: e1a01003 mov r1, r3 + 37c: ebf60c72 bl 0xffd8354c + 380: 0800025e stmeqda r0, {r1, r2, r3, r4, r6, r9} + 384: ebf60efd bl 0xffd83f80 + 388: 0800025e stmeqda r0, {r1, r2, r3, r4, r6, r9} + 38c: ebf60efb bl 0xffd83f80 + 390: 08000260 stmeqda r0, {r5, r6, r9} + 394: e3a00063 mov r0, #99 ; 0x63 + 398: e3800c02 orr r0, r0, #512 ; 0x200 + 39c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3a0: e58d0438 str r0, [sp, #1080] + 3a4: e28cc064 add ip, ip, #100 ; 0x64 + 3a8: e1a00fac mov r0, ip, lsr #31 + 3ac: e08ff100 add pc, pc, r0, lsl #2 + 3b0: 08000520 stmeqda r0, {r5, r8, sl} + 3b4: ebf60ae6 bl 0xffd82f54 + 3b8: ea000001 b 0x3c4 + 3bc: 08000520 stmeqda r0, {r5, r8, sl} + 3c0: 00000000 andeq r0, r0, r0 + 3c4: ebf60eed bl 0xffd83f80 + 3c8: 08000520 stmeqda r0, {r5, r8, sl} + 3cc: e3a00f8b mov r0, #556 ; 0x22c + 3d0: e3800b01 orr r0, r0, #1024 ; 0x400 + 3d4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3d8: ebf60d4e bl 0xffd83918 + 3dc: 08000524 stmeqda r0, {r2, r5, r8, sl} + 3e0: e1a05000 mov r5, r0 + 3e4: ebf60ee5 bl 0xffd83f80 + 3e8: 08000522 stmeqda r0, {r1, r5, r8, sl} + 3ec: e3b03080 movs r3, #128 ; 0x80 + 3f0: ebf60ee2 bl 0xffd83f80 + 3f4: 08000524 stmeqda r0, {r2, r5, r8, sl} + 3f8: e1b03983 movs r3, r3, lsl #19 + 3fc: ebf60edf bl 0xffd83f80 + 400: 08000526 stmeqda r0, {r1, r2, r5, r8, sl} + 404: e2830000 add r0, r3, #0 ; 0x0 + 408: ebf60d16 bl 0xffd83868 + 40c: 0800052a stmeqda r0, {r1, r3, r5, r8, sl} + 410: e1a03000 mov r3, r0 + 414: ebf60ed9 bl 0xffd83f80 + 418: 08000528 stmeqda r0, {r3, r5, r8, sl} + 41c: e2850000 add r0, r5, #0 ; 0x0 + 420: e1a01003 mov r1, r3 + 424: ebf60c48 bl 0xffd8354c + 428: 0800052a stmeqda r0, {r1, r3, r5, r8, sl} + 42c: ebf60ed3 bl 0xffd83f80 + 430: 0800052a stmeqda r0, {r1, r3, r5, r8, sl} + 434: e3a00e63 mov r0, #1584 ; 0x630 + 438: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 43c: ebf60d35 bl 0xffd83918 + 440: 0800052e stmeqda r0, {r1, r2, r3, r5, r8, sl} + 444: e1a03000 mov r3, r0 + 448: ebf60ecc bl 0xffd83f80 + 44c: 0800052c stmeqda r0, {r2, r3, r5, r8, sl} + 450: e2830000 add r0, r3, #0 ; 0x0 + 454: ebf60d03 bl 0xffd83868 + 458: 08000530 stmeqda r0, {r4, r5, r8, sl} + 45c: e1a03000 mov r3, r0 + 460: ebf60ec6 bl 0xffd83f80 + 464: 0800052e stmeqda r0, {r1, r2, r3, r5, r8, sl} + 468: e2850002 add r0, r5, #2 ; 0x2 + 46c: e1a01003 mov r1, r3 + 470: ebf60c35 bl 0xffd8354c + 474: 08000530 stmeqda r0, {r4, r5, r8, sl} + 478: ebf60ec0 bl 0xffd83f80 + 47c: 08000530 stmeqda r0, {r4, r5, r8, sl} + 480: e3a00f8d mov r0, #564 ; 0x234 + 484: e3800b01 orr r0, r0, #1024 ; 0x400 + 488: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 48c: ebf60d21 bl 0xffd83918 + 490: 08000534 stmeqda r0, {r2, r4, r5, r8, sl} + 494: e1a03000 mov r3, r0 + 498: ebf60eb8 bl 0xffd83f80 + 49c: 08000532 stmeqda r0, {r1, r4, r5, r8, sl} + 4a0: e2830000 add r0, r3, #0 ; 0x0 + 4a4: ebf60cef bl 0xffd83868 + 4a8: 08000536 stmeqda r0, {r1, r2, r4, r5, r8, sl} + 4ac: e1a03000 mov r3, r0 + 4b0: ebf60eb2 bl 0xffd83f80 + 4b4: 08000534 stmeqda r0, {r2, r4, r5, r8, sl} + 4b8: e2850004 add r0, r5, #4 ; 0x4 + 4bc: e1a01003 mov r1, r3 + 4c0: ebf60c21 bl 0xffd8354c + 4c4: 08000536 stmeqda r0, {r1, r2, r4, r5, r8, sl} + 4c8: ebf60eac bl 0xffd83f80 + 4cc: 08000536 stmeqda r0, {r1, r2, r4, r5, r8, sl} + 4d0: e3a00f8e mov r0, #568 ; 0x238 + 4d4: e3800b01 orr r0, r0, #1024 ; 0x400 + 4d8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4dc: ebf60d0d bl 0xffd83918 + 4e0: 0800053a stmeqda r0, {r1, r3, r4, r5, r8, sl} + 4e4: e1a03000 mov r3, r0 + 4e8: ebf60ea4 bl 0xffd83f80 + 4ec: 08000538 stmeqda r0, {r3, r4, r5, r8, sl} + 4f0: e2830000 add r0, r3, #0 ; 0x0 + 4f4: ebf60cdb bl 0xffd83868 + 4f8: 0800053c stmeqda r0, {r2, r3, r4, r5, r8, sl} + 4fc: e1a03000 mov r3, r0 + 500: ebf60e9e bl 0xffd83f80 + 504: 0800053a stmeqda r0, {r1, r3, r4, r5, r8, sl} + 508: e2850006 add r0, r5, #6 ; 0x6 + 50c: e1a01003 mov r1, r3 + 510: ebf60c0d bl 0xffd8354c + 514: 0800053c stmeqda r0, {r2, r3, r4, r5, r8, sl} + 518: ebf60e98 bl 0xffd83f80 + 51c: 0800053c stmeqda r0, {r2, r3, r4, r5, r8, sl} + 520: e3a00f8f mov r0, #572 ; 0x23c + 524: e3800b01 orr r0, r0, #1024 ; 0x400 + 528: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 52c: ebf60cf9 bl 0xffd83918 + 530: 08000540 stmeqda r0, {r6, r8, sl} + 534: e1a03000 mov r3, r0 + 538: ebf60e90 bl 0xffd83f80 + 53c: 0800053e stmeqda r0, {r1, r2, r3, r4, r5, r8, sl} + 540: e2830000 add r0, r3, #0 ; 0x0 + 544: ebf60cc7 bl 0xffd83868 + 548: 08000542 stmeqda r0, {r1, r6, r8, sl} + 54c: e1a03000 mov r3, r0 + 550: ebf60e8a bl 0xffd83f80 + 554: 08000540 stmeqda r0, {r6, r8, sl} + 558: e2850008 add r0, r5, #8 ; 0x8 + 55c: e1a01003 mov r1, r3 + 560: ebf60bf9 bl 0xffd8354c + 564: 08000542 stmeqda r0, {r1, r6, r8, sl} + 568: ebf60e84 bl 0xffd83f80 + 56c: 08000542 stmeqda r0, {r1, r6, r8, sl} + 570: e3a00d19 mov r0, #1600 ; 0x640 + 574: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 578: ebf60ce6 bl 0xffd83918 + 57c: 08000546 stmeqda r0, {r1, r2, r6, r8, sl} + 580: e1a03000 mov r3, r0 + 584: ebf60e7d bl 0xffd83f80 + 588: 08000544 stmeqda r0, {r2, r6, r8, sl} + 58c: e2830000 add r0, r3, #0 ; 0x0 + 590: ebf60cb4 bl 0xffd83868 + 594: 08000548 stmeqda r0, {r3, r6, r8, sl} + 598: e1a03000 mov r3, r0 + 59c: ebf60e77 bl 0xffd83f80 + 5a0: 08000546 stmeqda r0, {r1, r2, r6, r8, sl} + 5a4: e285000a add r0, r5, #10 ; 0xa + 5a8: e1a01003 mov r1, r3 + 5ac: ebf60be6 bl 0xffd8354c + 5b0: 08000548 stmeqda r0, {r3, r6, r8, sl} + 5b4: ebf60e71 bl 0xffd83f80 + 5b8: 08000548 stmeqda r0, {r3, r6, r8, sl} + 5bc: e3a00f91 mov r0, #580 ; 0x244 + 5c0: e3800b01 orr r0, r0, #1024 ; 0x400 + 5c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5c8: ebf60cd2 bl 0xffd83918 + 5cc: 0800054c stmeqda r0, {r2, r3, r6, r8, sl} + 5d0: e1a03000 mov r3, r0 + 5d4: ebf60e69 bl 0xffd83f80 + 5d8: 0800054a stmeqda r0, {r1, r3, r6, r8, sl} + 5dc: e2830000 add r0, r3, #0 ; 0x0 + 5e0: ebf60ca0 bl 0xffd83868 + 5e4: 0800054e stmeqda r0, {r1, r2, r3, r6, r8, sl} + 5e8: e1a03000 mov r3, r0 + 5ec: ebf60e63 bl 0xffd83f80 + 5f0: 0800054c stmeqda r0, {r2, r3, r6, r8, sl} + 5f4: e285000c add r0, r5, #12 ; 0xc + 5f8: e1a01003 mov r1, r3 + 5fc: ebf60bd2 bl 0xffd8354c + 600: 0800054e stmeqda r0, {r1, r2, r3, r6, r8, sl} + 604: ebf60e5d bl 0xffd83f80 + 608: 0800054e stmeqda r0, {r1, r2, r3, r6, r8, sl} + 60c: e3a00f92 mov r0, #584 ; 0x248 + 610: e3800b01 orr r0, r0, #1024 ; 0x400 + 614: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 618: ebf60cbe bl 0xffd83918 + 61c: 08000552 stmeqda r0, {r1, r4, r6, r8, sl} + 620: e1a03000 mov r3, r0 + 624: ebf60e55 bl 0xffd83f80 + 628: 08000550 stmeqda r0, {r4, r6, r8, sl} + 62c: e2830000 add r0, r3, #0 ; 0x0 + 630: ebf60c8c bl 0xffd83868 + 634: 08000554 stmeqda r0, {r2, r4, r6, r8, sl} + 638: e1a03000 mov r3, r0 + 63c: ebf60e4f bl 0xffd83f80 + 640: 08000552 stmeqda r0, {r1, r4, r6, r8, sl} + 644: e285000e add r0, r5, #14 ; 0xe + 648: e1a01003 mov r1, r3 + 64c: ebf60bbe bl 0xffd8354c + 650: 08000554 stmeqda r0, {r2, r4, r6, r8, sl} + 654: ebf60e49 bl 0xffd83f80 + 658: 08000554 stmeqda r0, {r2, r4, r6, r8, sl} + 65c: e3a00f93 mov r0, #588 ; 0x24c + 660: e3800b01 orr r0, r0, #1024 ; 0x400 + 664: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 668: ebf60caa bl 0xffd83918 + 66c: 08000558 stmeqda r0, {r3, r4, r6, r8, sl} + 670: e1a03000 mov r3, r0 + 674: ebf60e41 bl 0xffd83f80 + 678: 08000556 stmeqda r0, {r1, r2, r4, r6, r8, sl} + 67c: e2830000 add r0, r3, #0 ; 0x0 + 680: ebf60c78 bl 0xffd83868 + 684: 0800055a stmeqda r0, {r1, r3, r4, r6, r8, sl} + 688: e1a03000 mov r3, r0 + 68c: ebf60e3b bl 0xffd83f80 + 690: 08000558 stmeqda r0, {r3, r4, r6, r8, sl} + 694: e2850010 add r0, r5, #16 ; 0x10 + 698: e1a01003 mov r1, r3 + 69c: ebf60baa bl 0xffd8354c + 6a0: 0800055a stmeqda r0, {r1, r3, r4, r6, r8, sl} + 6a4: ebf60e35 bl 0xffd83f80 + 6a8: 0800055a stmeqda r0, {r1, r3, r4, r6, r8, sl} + 6ac: e3a00e65 mov r0, #1616 ; 0x650 + 6b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6b4: ebf60c97 bl 0xffd83918 + 6b8: 0800055e stmeqda r0, {r1, r2, r3, r4, r6, r8, sl} + 6bc: e1a03000 mov r3, r0 + 6c0: ebf60e2e bl 0xffd83f80 + 6c4: 0800055c stmeqda r0, {r2, r3, r4, r6, r8, sl} + 6c8: e2830000 add r0, r3, #0 ; 0x0 + 6cc: ebf60c65 bl 0xffd83868 + 6d0: 08000560 stmeqda r0, {r5, r6, r8, sl} + 6d4: e1a03000 mov r3, r0 + 6d8: ebf60e28 bl 0xffd83f80 + 6dc: 0800055e stmeqda r0, {r1, r2, r3, r4, r6, r8, sl} + 6e0: e2850012 add r0, r5, #18 ; 0x12 + 6e4: e1a01003 mov r1, r3 + 6e8: ebf60b97 bl 0xffd8354c + 6ec: 08000560 stmeqda r0, {r5, r6, r8, sl} + 6f0: ebf60e22 bl 0xffd83f80 + 6f4: 08000560 stmeqda r0, {r5, r6, r8, sl} + 6f8: e3a00f95 mov r0, #596 ; 0x254 + 6fc: e3800b01 orr r0, r0, #1024 ; 0x400 + 700: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 704: ebf60c83 bl 0xffd83918 + 708: 08000564 stmeqda r0, {r2, r5, r6, r8, sl} + 70c: e1a03000 mov r3, r0 + 710: ebf60e1a bl 0xffd83f80 + 714: 08000562 stmeqda r0, {r1, r5, r6, r8, sl} + 718: e2830000 add r0, r3, #0 ; 0x0 + 71c: ebf60c51 bl 0xffd83868 + 720: 08000566 stmeqda r0, {r1, r2, r5, r6, r8, sl} + 724: e1a03000 mov r3, r0 + 728: ebf60e14 bl 0xffd83f80 + 72c: 08000564 stmeqda r0, {r2, r5, r6, r8, sl} + 730: e2850014 add r0, r5, #20 ; 0x14 + 734: e1a01003 mov r1, r3 + 738: ebf60b83 bl 0xffd8354c + 73c: 08000566 stmeqda r0, {r1, r2, r5, r6, r8, sl} + 740: ebf60e0e bl 0xffd83f80 + 744: 08000566 stmeqda r0, {r1, r2, r5, r6, r8, sl} + 748: e3a00f96 mov r0, #600 ; 0x258 + 74c: e3800b01 orr r0, r0, #1024 ; 0x400 + 750: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 754: ebf60c6f bl 0xffd83918 + 758: 0800056a stmeqda r0, {r1, r3, r5, r6, r8, sl} + 75c: e1a03000 mov r3, r0 + 760: ebf60e06 bl 0xffd83f80 + 764: 08000568 stmeqda r0, {r3, r5, r6, r8, sl} + 768: e2830000 add r0, r3, #0 ; 0x0 + 76c: ebf60c3d bl 0xffd83868 + 770: 0800056c stmeqda r0, {r2, r3, r5, r6, r8, sl} + 774: e1a03000 mov r3, r0 + 778: ebf60e00 bl 0xffd83f80 + 77c: 0800056a stmeqda r0, {r1, r3, r5, r6, r8, sl} + 780: e2850016 add r0, r5, #22 ; 0x16 + 784: e1a01003 mov r1, r3 + 788: ebf60b6f bl 0xffd8354c + 78c: 0800056c stmeqda r0, {r2, r3, r5, r6, r8, sl} + 790: ebf60dfa bl 0xffd83f80 + 794: 0800056c stmeqda r0, {r2, r3, r5, r6, r8, sl} + 798: e3a00f97 mov r0, #604 ; 0x25c + 79c: e3800b01 orr r0, r0, #1024 ; 0x400 + 7a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7a4: ebf60c5b bl 0xffd83918 + 7a8: 08000570 stmeqda r0, {r4, r5, r6, r8, sl} + 7ac: e1a03000 mov r3, r0 + 7b0: ebf60df2 bl 0xffd83f80 + 7b4: 0800056e stmeqda r0, {r1, r2, r3, r5, r6, r8, sl} + 7b8: e2830000 add r0, r3, #0 ; 0x0 + 7bc: ebf60c29 bl 0xffd83868 + 7c0: 08000572 stmeqda r0, {r1, r4, r5, r6, r8, sl} + 7c4: e1a03000 mov r3, r0 + 7c8: ebf60dec bl 0xffd83f80 + 7cc: 08000570 stmeqda r0, {r4, r5, r6, r8, sl} + 7d0: e2850018 add r0, r5, #24 ; 0x18 + 7d4: e1a01003 mov r1, r3 + 7d8: ebf60b5b bl 0xffd8354c + 7dc: 08000572 stmeqda r0, {r1, r4, r5, r6, r8, sl} + 7e0: ebf60de6 bl 0xffd83f80 + 7e4: 08000572 stmeqda r0, {r1, r4, r5, r6, r8, sl} + 7e8: e3a00e66 mov r0, #1632 ; 0x660 + 7ec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7f0: ebf60c48 bl 0xffd83918 + 7f4: 08000576 stmeqda r0, {r1, r2, r4, r5, r6, r8, sl} + 7f8: e1a03000 mov r3, r0 + 7fc: ebf60ddf bl 0xffd83f80 + 800: 08000574 stmeqda r0, {r2, r4, r5, r6, r8, sl} + 804: e2830000 add r0, r3, #0 ; 0x0 + 808: ebf60c16 bl 0xffd83868 + 80c: 08000578 stmeqda r0, {r3, r4, r5, r6, r8, sl} + 810: e1a03000 mov r3, r0 + 814: ebf60dd9 bl 0xffd83f80 + 818: 08000576 stmeqda r0, {r1, r2, r4, r5, r6, r8, sl} + 81c: e285001a add r0, r5, #26 ; 0x1a + 820: e1a01003 mov r1, r3 + 824: ebf60b48 bl 0xffd8354c + 828: 08000578 stmeqda r0, {r3, r4, r5, r6, r8, sl} + 82c: ebf60dd3 bl 0xffd83f80 + 830: 08000578 stmeqda r0, {r3, r4, r5, r6, r8, sl} + 834: e3a00f99 mov r0, #612 ; 0x264 + 838: e3800b01 orr r0, r0, #1024 ; 0x400 + 83c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 840: ebf60c34 bl 0xffd83918 + 844: 0800057c stmeqda r0, {r2, r3, r4, r5, r6, r8, sl} + 848: e1a03000 mov r3, r0 + 84c: ebf60dcb bl 0xffd83f80 + 850: 0800057a stmeqda r0, {r1, r3, r4, r5, r6, r8, sl} + 854: e2830000 add r0, r3, #0 ; 0x0 + 858: ebf60c02 bl 0xffd83868 + 85c: 0800057e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, sl} + 860: e1a03000 mov r3, r0 + 864: ebf60dc5 bl 0xffd83f80 + 868: 0800057c stmeqda r0, {r2, r3, r4, r5, r6, r8, sl} + 86c: e285001c add r0, r5, #28 ; 0x1c + 870: e1a01003 mov r1, r3 + 874: ebf60b34 bl 0xffd8354c + 878: 0800057e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, sl} + 87c: ebf60dbf bl 0xffd83f80 + 880: 0800057e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, sl} + 884: e3a00f9a mov r0, #616 ; 0x268 + 888: e3800b01 orr r0, r0, #1024 ; 0x400 + 88c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 890: ebf60c20 bl 0xffd83918 + 894: 08000582 stmeqda r0, {r1, r7, r8, sl} + 898: e1a03000 mov r3, r0 + 89c: ebf60db7 bl 0xffd83f80 + 8a0: 08000580 stmeqda r0, {r7, r8, sl} + 8a4: e2830000 add r0, r3, #0 ; 0x0 + 8a8: ebf60bee bl 0xffd83868 + 8ac: 08000584 stmeqda r0, {r2, r7, r8, sl} + 8b0: e1a03000 mov r3, r0 + 8b4: ebf60db1 bl 0xffd83f80 + 8b8: 08000582 stmeqda r0, {r1, r7, r8, sl} + 8bc: e285001e add r0, r5, #30 ; 0x1e + 8c0: e1a01003 mov r1, r3 + 8c4: ebf60b20 bl 0xffd8354c + 8c8: 08000584 stmeqda r0, {r2, r7, r8, sl} + 8cc: ebf60dab bl 0xffd83f80 + 8d0: 08000584 stmeqda r0, {r2, r7, r8, sl} + 8d4: e3a00f9b mov r0, #620 ; 0x26c + 8d8: e3800b01 orr r0, r0, #1024 ; 0x400 + 8dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8e0: ebf60c0c bl 0xffd83918 + 8e4: 08000588 stmeqda r0, {r3, r7, r8, sl} + 8e8: e1a03000 mov r3, r0 + 8ec: ebf60da3 bl 0xffd83f80 + 8f0: 08000586 stmeqda r0, {r1, r2, r7, r8, sl} + 8f4: e2830000 add r0, r3, #0 ; 0x0 + 8f8: ebf60bda bl 0xffd83868 + 8fc: 0800058a stmeqda r0, {r1, r3, r7, r8, sl} + 900: e1a03000 mov r3, r0 + 904: ebf60d9d bl 0xffd83f80 + 908: 08000588 stmeqda r0, {r3, r7, r8, sl} + 90c: e2850020 add r0, r5, #32 ; 0x20 + 910: e1a01003 mov r1, r3 + 914: ebf60b0c bl 0xffd8354c + 918: 0800058a stmeqda r0, {r1, r3, r7, r8, sl} + 91c: ebf60d97 bl 0xffd83f80 + 920: 0800058a stmeqda r0, {r1, r3, r7, r8, sl} + 924: e3a00e67 mov r0, #1648 ; 0x670 + 928: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 92c: ebf60bf9 bl 0xffd83918 + 930: 0800058e stmeqda r0, {r1, r2, r3, r7, r8, sl} + 934: e1a03000 mov r3, r0 + 938: ebf60d90 bl 0xffd83f80 + 93c: 0800058c stmeqda r0, {r2, r3, r7, r8, sl} + 940: e2830000 add r0, r3, #0 ; 0x0 + 944: ebf60bc7 bl 0xffd83868 + 948: 08000590 stmeqda r0, {r4, r7, r8, sl} + 94c: e1a03000 mov r3, r0 + 950: ebf60d8a bl 0xffd83f80 + 954: 0800058e stmeqda r0, {r1, r2, r3, r7, r8, sl} + 958: e2850022 add r0, r5, #34 ; 0x22 + 95c: e1a01003 mov r1, r3 + 960: ebf60af9 bl 0xffd8354c + 964: 08000590 stmeqda r0, {r4, r7, r8, sl} + 968: ebf60d84 bl 0xffd83f80 + 96c: 08000590 stmeqda r0, {r4, r7, r8, sl} + 970: e3a00f9d mov r0, #628 ; 0x274 + 974: e3800b01 orr r0, r0, #1024 ; 0x400 + 978: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 97c: ebf60be5 bl 0xffd83918 + 980: 08000594 stmeqda r0, {r2, r4, r7, r8, sl} + 984: e1a03000 mov r3, r0 + 988: ebf60d7c bl 0xffd83f80 + 98c: 08000592 stmeqda r0, {r1, r4, r7, r8, sl} + 990: e2830000 add r0, r3, #0 ; 0x0 + 994: ebf60bb3 bl 0xffd83868 + 998: 08000596 stmeqda r0, {r1, r2, r4, r7, r8, sl} + 99c: e1a03000 mov r3, r0 + 9a0: ebf60d76 bl 0xffd83f80 + 9a4: 08000594 stmeqda r0, {r2, r4, r7, r8, sl} + 9a8: e2850024 add r0, r5, #36 ; 0x24 + 9ac: e1a01003 mov r1, r3 + 9b0: ebf60ae5 bl 0xffd8354c + 9b4: 08000596 stmeqda r0, {r1, r2, r4, r7, r8, sl} + 9b8: ebf60d70 bl 0xffd83f80 + 9bc: 08000596 stmeqda r0, {r1, r2, r4, r7, r8, sl} + 9c0: e3a00f9e mov r0, #632 ; 0x278 + 9c4: e3800b01 orr r0, r0, #1024 ; 0x400 + 9c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9cc: ebf60bd1 bl 0xffd83918 + 9d0: 0800059a stmeqda r0, {r1, r3, r4, r7, r8, sl} + 9d4: e1a03000 mov r3, r0 + 9d8: ebf60d68 bl 0xffd83f80 + 9dc: 08000598 stmeqda r0, {r3, r4, r7, r8, sl} + 9e0: e2830000 add r0, r3, #0 ; 0x0 + 9e4: ebf60b9f bl 0xffd83868 + 9e8: 0800059c stmeqda r0, {r2, r3, r4, r7, r8, sl} + 9ec: e1a03000 mov r3, r0 + 9f0: ebf60d62 bl 0xffd83f80 + 9f4: 0800059a stmeqda r0, {r1, r3, r4, r7, r8, sl} + 9f8: e2850026 add r0, r5, #38 ; 0x26 + 9fc: e1a01003 mov r1, r3 + a00: ebf60ad1 bl 0xffd8354c + a04: 0800059c stmeqda r0, {r2, r3, r4, r7, r8, sl} + a08: ebf60d5c bl 0xffd83f80 + a0c: 0800059c stmeqda r0, {r2, r3, r4, r7, r8, sl} + a10: e3a00f9f mov r0, #636 ; 0x27c + a14: e3800b01 orr r0, r0, #1024 ; 0x400 + a18: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a1c: ebf60bbd bl 0xffd83918 + a20: 080005a0 stmeqda r0, {r5, r7, r8, sl} + a24: e1a03000 mov r3, r0 + a28: ebf60d54 bl 0xffd83f80 + a2c: 0800059e stmeqda r0, {r1, r2, r3, r4, r7, r8, sl} + a30: e2830000 add r0, r3, #0 ; 0x0 + a34: ebf60b8b bl 0xffd83868 + a38: 080005a2 stmeqda r0, {r1, r5, r7, r8, sl} + a3c: e1a03000 mov r3, r0 + a40: ebf60d4e bl 0xffd83f80 + a44: 080005a0 stmeqda r0, {r5, r7, r8, sl} + a48: e2850028 add r0, r5, #40 ; 0x28 + a4c: e1a01003 mov r1, r3 + a50: ebf60abd bl 0xffd8354c + a54: 080005a2 stmeqda r0, {r1, r5, r7, r8, sl} + a58: ebf60d48 bl 0xffd83f80 + a5c: 080005a2 stmeqda r0, {r1, r5, r7, r8, sl} + a60: e3a00d1a mov r0, #1664 ; 0x680 + a64: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a68: ebf60baa bl 0xffd83918 + a6c: 080005a6 stmeqda r0, {r1, r2, r5, r7, r8, sl} + a70: e1a03000 mov r3, r0 + a74: ebf60d41 bl 0xffd83f80 + a78: 080005a4 stmeqda r0, {r2, r5, r7, r8, sl} + a7c: e2830000 add r0, r3, #0 ; 0x0 + a80: ebf60b78 bl 0xffd83868 + a84: 080005a8 stmeqda r0, {r3, r5, r7, r8, sl} + a88: e1a03000 mov r3, r0 + a8c: ebf60d3b bl 0xffd83f80 + a90: 080005a6 stmeqda r0, {r1, r2, r5, r7, r8, sl} + a94: e285002a add r0, r5, #42 ; 0x2a + a98: e1a01003 mov r1, r3 + a9c: ebf60aaa bl 0xffd8354c + aa0: 080005a8 stmeqda r0, {r3, r5, r7, r8, sl} + aa4: ebf60d35 bl 0xffd83f80 + aa8: 080005a8 stmeqda r0, {r3, r5, r7, r8, sl} + aac: e3a00fa1 mov r0, #644 ; 0x284 + ab0: e3800b01 orr r0, r0, #1024 ; 0x400 + ab4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ab8: ebf60b96 bl 0xffd83918 + abc: 080005ac stmeqda r0, {r2, r3, r5, r7, r8, sl} + ac0: e1a03000 mov r3, r0 + ac4: ebf60d2d bl 0xffd83f80 + ac8: 080005aa stmeqda r0, {r1, r3, r5, r7, r8, sl} + acc: e2830000 add r0, r3, #0 ; 0x0 + ad0: ebf60b64 bl 0xffd83868 + ad4: 080005ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl} + ad8: e1a03000 mov r3, r0 + adc: ebf60d27 bl 0xffd83f80 + ae0: 080005ac stmeqda r0, {r2, r3, r5, r7, r8, sl} + ae4: e285002c add r0, r5, #44 ; 0x2c + ae8: e1a01003 mov r1, r3 + aec: ebf60a96 bl 0xffd8354c + af0: 080005ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl} + af4: ebf60d21 bl 0xffd83f80 + af8: 080005ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl} + afc: e3a00fa2 mov r0, #648 ; 0x288 + b00: e3800b01 orr r0, r0, #1024 ; 0x400 + b04: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b08: ebf60b82 bl 0xffd83918 + b0c: 080005b2 stmeqda r0, {r1, r4, r5, r7, r8, sl} + b10: e1a03000 mov r3, r0 + b14: ebf60d19 bl 0xffd83f80 + b18: 080005b0 stmeqda r0, {r4, r5, r7, r8, sl} + b1c: e2830000 add r0, r3, #0 ; 0x0 + b20: ebf60b50 bl 0xffd83868 + b24: 080005b4 stmeqda r0, {r2, r4, r5, r7, r8, sl} + b28: e1a03000 mov r3, r0 + b2c: ebf60d13 bl 0xffd83f80 + b30: 080005b2 stmeqda r0, {r1, r4, r5, r7, r8, sl} + b34: e285002e add r0, r5, #46 ; 0x2e + b38: e1a01003 mov r1, r3 + b3c: ebf60a82 bl 0xffd8354c + b40: 080005b4 stmeqda r0, {r2, r4, r5, r7, r8, sl} + b44: ebf60d0d bl 0xffd83f80 + b48: 080005b4 stmeqda r0, {r2, r4, r5, r7, r8, sl} + b4c: e3a00fa3 mov r0, #652 ; 0x28c + b50: e3800b01 orr r0, r0, #1024 ; 0x400 + b54: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b58: ebf60b6e bl 0xffd83918 + b5c: 080005b8 stmeqda r0, {r3, r4, r5, r7, r8, sl} + b60: e1a03000 mov r3, r0 + b64: ebf60d05 bl 0xffd83f80 + b68: 080005b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl} + b6c: e2830000 add r0, r3, #0 ; 0x0 + b70: ebf60b3c bl 0xffd83868 + b74: 080005ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl} + b78: e1a03000 mov r3, r0 + b7c: ebf60cff bl 0xffd83f80 + b80: 080005b8 stmeqda r0, {r3, r4, r5, r7, r8, sl} + b84: e2850030 add r0, r5, #48 ; 0x30 + b88: e1a01003 mov r1, r3 + b8c: ebf60a6e bl 0xffd8354c + b90: 080005ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl} + b94: ebf60cf9 bl 0xffd83f80 + b98: 080005ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl} + b9c: e3a00e69 mov r0, #1680 ; 0x690 + ba0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ba4: ebf60b5b bl 0xffd83918 + ba8: 080005be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl} + bac: e1a03000 mov r3, r0 + bb0: ebf60cf2 bl 0xffd83f80 + bb4: 080005bc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl} + bb8: e2830000 add r0, r3, #0 ; 0x0 + bbc: ebf60b29 bl 0xffd83868 + bc0: 080005c0 stmeqda r0, {r6, r7, r8, sl} + bc4: e1a03000 mov r3, r0 + bc8: ebf60cec bl 0xffd83f80 + bcc: 080005be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl} + bd0: e2850032 add r0, r5, #50 ; 0x32 + bd4: e1a01003 mov r1, r3 + bd8: ebf60a5b bl 0xffd8354c + bdc: 080005c0 stmeqda r0, {r6, r7, r8, sl} + be0: ebf60ce6 bl 0xffd83f80 + be4: 080005c0 stmeqda r0, {r6, r7, r8, sl} + be8: e3a00fa5 mov r0, #660 ; 0x294 + bec: e3800b01 orr r0, r0, #1024 ; 0x400 + bf0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + bf4: ebf60b47 bl 0xffd83918 + bf8: 080005c4 stmeqda r0, {r2, r6, r7, r8, sl} + bfc: e1a03000 mov r3, r0 + c00: ebf60cde bl 0xffd83f80 + c04: 080005c2 stmeqda r0, {r1, r6, r7, r8, sl} + c08: e2830000 add r0, r3, #0 ; 0x0 + c0c: ebf60b15 bl 0xffd83868 + c10: 080005c6 stmeqda r0, {r1, r2, r6, r7, r8, sl} + c14: e1a03000 mov r3, r0 + c18: ebf60cd8 bl 0xffd83f80 + c1c: 080005c4 stmeqda r0, {r2, r6, r7, r8, sl} + c20: e2850034 add r0, r5, #52 ; 0x34 + c24: e1a01003 mov r1, r3 + c28: ebf60a47 bl 0xffd8354c + c2c: 080005c6 stmeqda r0, {r1, r2, r6, r7, r8, sl} + c30: ebf60cd2 bl 0xffd83f80 + c34: 080005c6 stmeqda r0, {r1, r2, r6, r7, r8, sl} + c38: e3a00fa6 mov r0, #664 ; 0x298 + c3c: e3800b01 orr r0, r0, #1024 ; 0x400 + c40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c44: ebf60b33 bl 0xffd83918 + c48: 080005ca stmeqda r0, {r1, r3, r6, r7, r8, sl} + c4c: e1a03000 mov r3, r0 + c50: ebf60cca bl 0xffd83f80 + c54: 080005c8 stmeqda r0, {r3, r6, r7, r8, sl} + c58: e2830000 add r0, r3, #0 ; 0x0 + c5c: ebf60b01 bl 0xffd83868 + c60: 080005cc stmeqda r0, {r2, r3, r6, r7, r8, sl} + c64: e1a03000 mov r3, r0 + c68: ebf60cc4 bl 0xffd83f80 + c6c: 080005ca stmeqda r0, {r1, r3, r6, r7, r8, sl} + c70: e2850036 add r0, r5, #54 ; 0x36 + c74: e1a01003 mov r1, r3 + c78: ebf60a33 bl 0xffd8354c + c7c: 080005cc stmeqda r0, {r2, r3, r6, r7, r8, sl} + c80: ebf60cbe bl 0xffd83f80 + c84: 080005cc stmeqda r0, {r2, r3, r6, r7, r8, sl} + c88: e3a00fa7 mov r0, #668 ; 0x29c + c8c: e3800b01 orr r0, r0, #1024 ; 0x400 + c90: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c94: ebf60b1f bl 0xffd83918 + c98: 080005d0 stmeqda r0, {r4, r6, r7, r8, sl} + c9c: e1a03000 mov r3, r0 + ca0: ebf60cb6 bl 0xffd83f80 + ca4: 080005ce stmeqda r0, {r1, r2, r3, r6, r7, r8, sl} + ca8: e2830000 add r0, r3, #0 ; 0x0 + cac: ebf60aed bl 0xffd83868 + cb0: 080005d2 stmeqda r0, {r1, r4, r6, r7, r8, sl} + cb4: e1a03000 mov r3, r0 + cb8: ebf60cb0 bl 0xffd83f80 + cbc: 080005d0 stmeqda r0, {r4, r6, r7, r8, sl} + cc0: e2850038 add r0, r5, #56 ; 0x38 + cc4: e1a01003 mov r1, r3 + cc8: ebf60a1f bl 0xffd8354c + ccc: 080005d2 stmeqda r0, {r1, r4, r6, r7, r8, sl} + cd0: ebf60caa bl 0xffd83f80 + cd4: 080005d2 stmeqda r0, {r1, r4, r6, r7, r8, sl} + cd8: e3a00e6a mov r0, #1696 ; 0x6a0 + cdc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ce0: ebf60b0c bl 0xffd83918 + ce4: 080005d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, sl} + ce8: e1a03000 mov r3, r0 + cec: ebf60ca3 bl 0xffd83f80 + cf0: 080005d4 stmeqda r0, {r2, r4, r6, r7, r8, sl} + cf4: e2830000 add r0, r3, #0 ; 0x0 + cf8: ebf60ada bl 0xffd83868 + cfc: 080005d8 stmeqda r0, {r3, r4, r6, r7, r8, sl} + d00: e1a03000 mov r3, r0 + d04: ebf60c9d bl 0xffd83f80 + d08: 080005d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, sl} + d0c: e285003a add r0, r5, #58 ; 0x3a + d10: e1a01003 mov r1, r3 + d14: ebf60a0c bl 0xffd8354c + d18: 080005d8 stmeqda r0, {r3, r4, r6, r7, r8, sl} + d1c: ebf60c97 bl 0xffd83f80 + d20: 080005d8 stmeqda r0, {r3, r4, r6, r7, r8, sl} + d24: e3a00fa9 mov r0, #676 ; 0x2a4 + d28: e3800b01 orr r0, r0, #1024 ; 0x400 + d2c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d30: ebf60af8 bl 0xffd83918 + d34: 080005dc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl} + d38: e1a03000 mov r3, r0 + d3c: ebf60c8f bl 0xffd83f80 + d40: 080005da stmeqda r0, {r1, r3, r4, r6, r7, r8, sl} + d44: e2830000 add r0, r3, #0 ; 0x0 + d48: ebf60ac6 bl 0xffd83868 + d4c: 080005de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl} + d50: e1a03000 mov r3, r0 + d54: ebf60c89 bl 0xffd83f80 + d58: 080005dc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl} + d5c: e285003c add r0, r5, #60 ; 0x3c + d60: e1a01003 mov r1, r3 + d64: ebf609f8 bl 0xffd8354c + d68: 080005de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl} + d6c: ebf60c83 bl 0xffd83f80 + d70: 080005de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl} + d74: e3a00faa mov r0, #680 ; 0x2a8 + d78: e3800b01 orr r0, r0, #1024 ; 0x400 + d7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d80: ebf60ae4 bl 0xffd83918 + d84: 080005e2 stmeqda r0, {r1, r5, r6, r7, r8, sl} + d88: e1a03000 mov r3, r0 + d8c: ebf60c7b bl 0xffd83f80 + d90: 080005e0 stmeqda r0, {r5, r6, r7, r8, sl} + d94: e2830000 add r0, r3, #0 ; 0x0 + d98: ebf60ab2 bl 0xffd83868 + d9c: 080005e4 stmeqda r0, {r2, r5, r6, r7, r8, sl} + da0: e1a03000 mov r3, r0 + da4: ebf60c75 bl 0xffd83f80 + da8: 080005e2 stmeqda r0, {r1, r5, r6, r7, r8, sl} + dac: e285003e add r0, r5, #62 ; 0x3e + db0: e1a01003 mov r1, r3 + db4: ebf609e4 bl 0xffd8354c + db8: 080005e4 stmeqda r0, {r2, r5, r6, r7, r8, sl} + dbc: ebf60c6f bl 0xffd83f80 + dc0: 080005e4 stmeqda r0, {r2, r5, r6, r7, r8, sl} + dc4: e3a00fab mov r0, #684 ; 0x2ac + dc8: e3800b01 orr r0, r0, #1024 ; 0x400 + dcc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + dd0: ebf60ad0 bl 0xffd83918 + dd4: 080005e8 stmeqda r0, {r3, r5, r6, r7, r8, sl} + dd8: e1a03000 mov r3, r0 + ddc: ebf60c67 bl 0xffd83f80 + de0: 080005e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, sl} + de4: e2830000 add r0, r3, #0 ; 0x0 + de8: ebf60a9e bl 0xffd83868 + dec: 080005ea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl} + df0: e1a04000 mov r4, r0 + df4: ebf60c61 bl 0xffd83f80 + df8: 080005e8 stmeqda r0, {r3, r5, r6, r7, r8, sl} + dfc: e1a01005 mov r1, r5 + e00: e2953000 adds r3, r5, #0 ; 0x0 + e04: ebf60c5d bl 0xffd83f80 + e08: 080005ea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl} + e0c: e1a01003 mov r1, r3 + e10: e2933040 adds r3, r3, #64 ; 0x40 + e14: ebf60c59 bl 0xffd83f80 + e18: 080005ec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl} + e1c: e2830000 add r0, r3, #0 ; 0x0 + e20: e1a01004 mov r1, r4 + e24: ebf609c8 bl 0xffd8354c + e28: 080005ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl} + e2c: ebf60c53 bl 0xffd83f80 + e30: 080005ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl} + e34: e3a00e6b mov r0, #1712 ; 0x6b0 + e38: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e3c: ebf60ab5 bl 0xffd83918 + e40: 080005f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl} + e44: e1a03000 mov r3, r0 + e48: ebf60c4c bl 0xffd83f80 + e4c: 080005f0 stmeqda r0, {r4, r5, r6, r7, r8, sl} + e50: e2830000 add r0, r3, #0 ; 0x0 + e54: ebf60a83 bl 0xffd83868 + e58: 080005f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl} + e5c: e1a03000 mov r3, r0 + e60: ebf60c46 bl 0xffd83f80 + e64: 080005f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl} + e68: e1a01005 mov r1, r5 + e6c: e2954000 adds r4, r5, #0 ; 0x0 + e70: ebf60c42 bl 0xffd83f80 + e74: 080005f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl} + e78: e1a01004 mov r1, r4 + e7c: e2944042 adds r4, r4, #66 ; 0x42 + e80: ebf60c3e bl 0xffd83f80 + e84: 080005f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl} + e88: e2840000 add r0, r4, #0 ; 0x0 + e8c: e1a01003 mov r1, r3 + e90: ebf609ad bl 0xffd8354c + e94: 080005f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl} + e98: ebf60c38 bl 0xffd83f80 + e9c: 080005f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl} + ea0: e3a00fad mov r0, #692 ; 0x2b4 + ea4: e3800b01 orr r0, r0, #1024 ; 0x400 + ea8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + eac: ebf60a99 bl 0xffd83918 + eb0: 080005fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl} + eb4: e1a03000 mov r3, r0 + eb8: ebf60c30 bl 0xffd83f80 + ebc: 080005fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, sl} + ec0: e2830000 add r0, r3, #0 ; 0x0 + ec4: ebf60a67 bl 0xffd83868 + ec8: 080005fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl} + ecc: e1a04000 mov r4, r0 + ed0: ebf60c2a bl 0xffd83f80 + ed4: 080005fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl} + ed8: e1a01005 mov r1, r5 + edc: e2953000 adds r3, r5, #0 ; 0x0 + ee0: ebf60c26 bl 0xffd83f80 + ee4: 080005fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl} + ee8: e1a01003 mov r1, r3 + eec: e2933044 adds r3, r3, #68 ; 0x44 + ef0: ebf60c22 bl 0xffd83f80 + ef4: 08000600 stmeqda r0, {r9, sl} + ef8: e2830000 add r0, r3, #0 ; 0x0 + efc: e1a01004 mov r1, r4 + f00: ebf60991 bl 0xffd8354c + f04: 08000602 stmeqda r0, {r1, r9, sl} + f08: ebf60c1c bl 0xffd83f80 + f0c: 08000602 stmeqda r0, {r1, r9, sl} + f10: e3a00fae mov r0, #696 ; 0x2b8 + f14: e3800b01 orr r0, r0, #1024 ; 0x400 + f18: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f1c: ebf60a7d bl 0xffd83918 + f20: 08000606 stmeqda r0, {r1, r2, r9, sl} + f24: e1a03000 mov r3, r0 + f28: ebf60c14 bl 0xffd83f80 + f2c: 08000604 stmeqda r0, {r2, r9, sl} + f30: e2830000 add r0, r3, #0 ; 0x0 + f34: ebf60a4b bl 0xffd83868 + f38: 08000608 stmeqda r0, {r3, r9, sl} + f3c: e1a03000 mov r3, r0 + f40: ebf60c0e bl 0xffd83f80 + f44: 08000606 stmeqda r0, {r1, r2, r9, sl} + f48: e1a01005 mov r1, r5 + f4c: e2954000 adds r4, r5, #0 ; 0x0 + f50: ebf60c0a bl 0xffd83f80 + f54: 08000608 stmeqda r0, {r3, r9, sl} + f58: e1a01004 mov r1, r4 + f5c: e2944046 adds r4, r4, #70 ; 0x46 + f60: ebf60c06 bl 0xffd83f80 + f64: 0800060a stmeqda r0, {r1, r3, r9, sl} + f68: e2840000 add r0, r4, #0 ; 0x0 + f6c: e1a01003 mov r1, r3 + f70: ebf60975 bl 0xffd8354c + f74: 0800060c stmeqda r0, {r2, r3, r9, sl} + f78: ebf60c00 bl 0xffd83f80 + f7c: 0800060c stmeqda r0, {r2, r3, r9, sl} + f80: e3a00faf mov r0, #700 ; 0x2bc + f84: e3800b01 orr r0, r0, #1024 ; 0x400 + f88: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f8c: ebf60a61 bl 0xffd83918 + f90: 08000610 stmeqda r0, {r4, r9, sl} + f94: e1a03000 mov r3, r0 + f98: ebf60bf8 bl 0xffd83f80 + f9c: 0800060e stmeqda r0, {r1, r2, r3, r9, sl} + fa0: e2830000 add r0, r3, #0 ; 0x0 + fa4: ebf60a2f bl 0xffd83868 + fa8: 08000612 stmeqda r0, {r1, r4, r9, sl} + fac: e1a04000 mov r4, r0 + fb0: ebf60bf2 bl 0xffd83f80 + fb4: 08000610 stmeqda r0, {r4, r9, sl} + fb8: e1a01005 mov r1, r5 + fbc: e2953000 adds r3, r5, #0 ; 0x0 + fc0: ebf60bee bl 0xffd83f80 + fc4: 08000612 stmeqda r0, {r1, r4, r9, sl} + fc8: e1a01003 mov r1, r3 + fcc: e2933048 adds r3, r3, #72 ; 0x48 + fd0: ebf60bea bl 0xffd83f80 + fd4: 08000614 stmeqda r0, {r2, r4, r9, sl} + fd8: e2830000 add r0, r3, #0 ; 0x0 + fdc: e1a01004 mov r1, r4 + fe0: ebf60959 bl 0xffd8354c + fe4: 08000616 stmeqda r0, {r1, r2, r4, r9, sl} + fe8: ebf60be4 bl 0xffd83f80 + fec: 08000616 stmeqda r0, {r1, r2, r4, r9, sl} + ff0: e3a00d1b mov r0, #1728 ; 0x6c0 + ff4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ff8: ebf60a46 bl 0xffd83918 + ffc: 0800061a stmeqda r0, {r1, r3, r4, r9, sl} + 1000: e1a03000 mov r3, r0 + 1004: ebf60bdd bl 0xffd83f80 + 1008: 08000618 stmeqda r0, {r3, r4, r9, sl} + 100c: e2830000 add r0, r3, #0 ; 0x0 + 1010: ebf60a14 bl 0xffd83868 + 1014: 0800061c stmeqda r0, {r2, r3, r4, r9, sl} + 1018: e1a03000 mov r3, r0 + 101c: ebf60bd7 bl 0xffd83f80 + 1020: 0800061a stmeqda r0, {r1, r3, r4, r9, sl} + 1024: e1a01005 mov r1, r5 + 1028: e2954000 adds r4, r5, #0 ; 0x0 + 102c: ebf60bd3 bl 0xffd83f80 + 1030: 0800061c stmeqda r0, {r2, r3, r4, r9, sl} + 1034: e1a01004 mov r1, r4 + 1038: e294404a adds r4, r4, #74 ; 0x4a + 103c: ebf60bcf bl 0xffd83f80 + 1040: 0800061e stmeqda r0, {r1, r2, r3, r4, r9, sl} + 1044: e2840000 add r0, r4, #0 ; 0x0 + 1048: e1a01003 mov r1, r3 + 104c: ebf6093e bl 0xffd8354c + 1050: 08000620 stmeqda r0, {r5, r9, sl} + 1054: ebf60bc9 bl 0xffd83f80 + 1058: 08000620 stmeqda r0, {r5, r9, sl} + 105c: e3a00fb1 mov r0, #708 ; 0x2c4 + 1060: e3800b01 orr r0, r0, #1024 ; 0x400 + 1064: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1068: ebf60a2a bl 0xffd83918 + 106c: 08000624 stmeqda r0, {r2, r5, r9, sl} + 1070: e1a03000 mov r3, r0 + 1074: ebf60bc1 bl 0xffd83f80 + 1078: 08000622 stmeqda r0, {r1, r5, r9, sl} + 107c: e2830000 add r0, r3, #0 ; 0x0 + 1080: ebf609f8 bl 0xffd83868 + 1084: 08000626 stmeqda r0, {r1, r2, r5, r9, sl} + 1088: e1a04000 mov r4, r0 + 108c: ebf60bbb bl 0xffd83f80 + 1090: 08000624 stmeqda r0, {r2, r5, r9, sl} + 1094: e1a01005 mov r1, r5 + 1098: e2953000 adds r3, r5, #0 ; 0x0 + 109c: ebf60bb7 bl 0xffd83f80 + 10a0: 08000626 stmeqda r0, {r1, r2, r5, r9, sl} + 10a4: e1a01003 mov r1, r3 + 10a8: e293304c adds r3, r3, #76 ; 0x4c + 10ac: ebf60bb3 bl 0xffd83f80 + 10b0: 08000628 stmeqda r0, {r3, r5, r9, sl} + 10b4: e2830000 add r0, r3, #0 ; 0x0 + 10b8: e1a01004 mov r1, r4 + 10bc: ebf60922 bl 0xffd8354c + 10c0: 0800062a stmeqda r0, {r1, r3, r5, r9, sl} + 10c4: ebf60bad bl 0xffd83f80 + 10c8: 0800062a stmeqda r0, {r1, r3, r5, r9, sl} + 10cc: e59d0438 ldr r0, [sp, #1080] + 10d0: e28ccc02 add ip, ip, #512 ; 0x200 + 10d4: e28cc055 add ip, ip, #85 ; 0x55 + 10d8: eaf607fc b 0xffd830d0 + 10dc: 08000262 stmeqda r0, {r1, r5, r6, r9} + 10e0: 00000000 andeq r0, r0, r0 + 10e4: ebf60ba5 bl 0xffd83f80 + 10e8: 08000262 stmeqda r0, {r1, r5, r6, r9} + 10ec: e3b08000 movs r8, #0 ; 0x0 + 10f0: ebf60ba2 bl 0xffd83f80 + 10f4: 08000264 stmeqda r0, {r2, r5, r6, r9} + 10f8: e59d0434 ldr r0, [sp, #1076] + 10fc: e2800f00 add r0, r0, #0 ; 0x0 + 1100: e1a01008 mov r1, r8 + 1104: ebf60930 bl 0xffd835cc + 1108: 08000266 stmeqda r0, {r1, r2, r5, r6, r9} + 110c: ebf60b9b bl 0xffd83f80 + 1110: 08000266 stmeqda r0, {r1, r2, r5, r6, r9} + 1114: e3a00fff mov r0, #1020 ; 0x3fc + 1118: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 111c: ebf609fd bl 0xffd83918 + 1120: 0800026a stmeqda r0, {r1, r3, r5, r6, r9} + 1124: e1a07000 mov r7, r0 + 1128: ebf60b94 bl 0xffd83f80 + 112c: 08000268 stmeqda r0, {r3, r5, r6, r9} + 1130: e59d1434 ldr r1, [sp, #1076] + 1134: e1a03001 mov r3, r1 + 1138: ebf60b90 bl 0xffd83f80 + 113c: 0800026a stmeqda r0, {r1, r3, r5, r6, r9} + 1140: e2870000 add r0, r7, #0 ; 0x0 + 1144: e1a01003 mov r1, r3 + 1148: ebf6091f bl 0xffd835cc + 114c: 0800026c stmeqda r0, {r2, r3, r5, r6, r9} + 1150: ebf60b8a bl 0xffd83f80 + 1154: 0800026c stmeqda r0, {r2, r3, r5, r6, r9} + 1158: e3b000c0 movs r0, #192 ; 0xc0 + 115c: e58d041c str r0, [sp, #1052] + 1160: ebf60b86 bl 0xffd83f80 + 1164: 0800026e stmeqda r0, {r1, r2, r3, r5, r6, r9} + 1168: e59de41c ldr lr, [sp, #1052] + 116c: e1b0090e movs r0, lr, lsl #18 + 1170: e58d041c str r0, [sp, #1052] + 1174: ebf60b81 bl 0xffd83f80 + 1178: 08000270 stmeqda r0, {r4, r5, r6, r9} + 117c: e2870004 add r0, r7, #4 ; 0x4 + 1180: e59d141c ldr r1, [sp, #1052] + 1184: ebf60910 bl 0xffd835cc + 1188: 08000272 stmeqda r0, {r1, r4, r5, r6, r9} + 118c: ebf60b7b bl 0xffd83f80 + 1190: 08000272 stmeqda r0, {r1, r4, r5, r6, r9} + 1194: e3a00b01 mov r0, #1024 ; 0x400 + 1198: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 119c: ebf609dd bl 0xffd83918 + 11a0: 08000276 stmeqda r0, {r1, r2, r4, r5, r6, r9} + 11a4: e1a03000 mov r3, r0 + 11a8: ebf60b74 bl 0xffd83f80 + 11ac: 08000274 stmeqda r0, {r2, r4, r5, r6, r9} + 11b0: e2870008 add r0, r7, #8 ; 0x8 + 11b4: e1a01003 mov r1, r3 + 11b8: ebf60903 bl 0xffd835cc + 11bc: 08000276 stmeqda r0, {r1, r2, r4, r5, r6, r9} + 11c0: ebf60b6e bl 0xffd83f80 + 11c4: 08000276 stmeqda r0, {r1, r2, r4, r5, r6, r9} + 11c8: e2870008 add r0, r7, #8 ; 0x8 + 11cc: ebf609d1 bl 0xffd83918 + 11d0: 0800027a stmeqda r0, {r1, r3, r4, r5, r6, r9} + 11d4: e1a03000 mov r3, r0 + 11d8: ebf60b68 bl 0xffd83f80 + 11dc: 08000278 stmeqda r0, {r3, r4, r5, r6, r9} + 11e0: e59d0434 ldr r0, [sp, #1076] + 11e4: e2800f00 add r0, r0, #0 ; 0x0 + 11e8: e1a01008 mov r1, r8 + 11ec: ebf608f6 bl 0xffd835cc + 11f0: 0800027a stmeqda r0, {r1, r3, r4, r5, r6, r9} + 11f4: ebf60b61 bl 0xffd83f80 + 11f8: 0800027a stmeqda r0, {r1, r3, r4, r5, r6, r9} + 11fc: e59d1434 ldr r1, [sp, #1076] + 1200: e1a04001 mov r4, r1 + 1204: ebf60b5d bl 0xffd83f80 + 1208: 0800027c stmeqda r0, {r2, r3, r4, r5, r6, r9} + 120c: e2870000 add r0, r7, #0 ; 0x0 + 1210: e1a01004 mov r1, r4 + 1214: ebf608ec bl 0xffd835cc + 1218: 0800027e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9} + 121c: ebf60b57 bl 0xffd83f80 + 1220: 0800027e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9} + 1224: e3b03080 movs r3, #128 ; 0x80 + 1228: ebf60b54 bl 0xffd83f80 + 122c: 08000280 stmeqda r0, {r7, r9} + 1230: e1b03903 movs r3, r3, lsl #18 + 1234: ebf60b51 bl 0xffd83f80 + 1238: 08000282 stmeqda r0, {r1, r7, r9} + 123c: e2870004 add r0, r7, #4 ; 0x4 + 1240: e1a01003 mov r1, r3 + 1244: ebf608e0 bl 0xffd835cc + 1248: 08000284 stmeqda r0, {r2, r7, r9} + 124c: ebf60b4b bl 0xffd83f80 + 1250: 08000284 stmeqda r0, {r2, r7, r9} + 1254: e3a00f01 mov r0, #4 ; 0x4 + 1258: e3800b01 orr r0, r0, #1024 ; 0x400 + 125c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1260: ebf609ac bl 0xffd83918 + 1264: 08000288 stmeqda r0, {r3, r7, r9} + 1268: e1a03000 mov r3, r0 + 126c: ebf60b43 bl 0xffd83f80 + 1270: 08000286 stmeqda r0, {r1, r2, r7, r9} + 1274: e2870008 add r0, r7, #8 ; 0x8 + 1278: e1a01003 mov r1, r3 + 127c: ebf608d2 bl 0xffd835cc + 1280: 08000288 stmeqda r0, {r3, r7, r9} + 1284: ebf60b3d bl 0xffd83f80 + 1288: 08000288 stmeqda r0, {r3, r7, r9} + 128c: e2870008 add r0, r7, #8 ; 0x8 + 1290: ebf609a0 bl 0xffd83918 + 1294: 0800028c stmeqda r0, {r2, r3, r7, r9} + 1298: e1a03000 mov r3, r0 + 129c: ebf60b37 bl 0xffd83f80 + 12a0: 0800028a stmeqda r0, {r1, r3, r7, r9} + 12a4: e59d0434 ldr r0, [sp, #1076] + 12a8: e2804f01 add r4, r0, #4 ; 0x4 + 12ac: ebf60b33 bl 0xffd83f80 + 12b0: 0800028c stmeqda r0, {r2, r3, r7, r9} + 12b4: e2840000 add r0, r4, #0 ; 0x0 + 12b8: e1a01008 mov r1, r8 + 12bc: ebf608a2 bl 0xffd8354c + 12c0: 0800028e stmeqda r0, {r1, r2, r3, r7, r9} + 12c4: ebf60b2d bl 0xffd83f80 + 12c8: 0800028e stmeqda r0, {r1, r2, r3, r7, r9} + 12cc: e2870000 add r0, r7, #0 ; 0x0 + 12d0: e1a01004 mov r1, r4 + 12d4: ebf608bc bl 0xffd835cc + 12d8: 08000290 stmeqda r0, {r4, r7, r9} + 12dc: ebf60b27 bl 0xffd83f80 + 12e0: 08000290 stmeqda r0, {r4, r7, r9} + 12e4: e3b030c0 movs r3, #192 ; 0xc0 + 12e8: ebf60b24 bl 0xffd83f80 + 12ec: 08000292 stmeqda r0, {r1, r4, r7, r9} + 12f0: e1b03983 movs r3, r3, lsl #19 + 12f4: ebf60b21 bl 0xffd83f80 + 12f8: 08000294 stmeqda r0, {r2, r4, r7, r9} + 12fc: e2870004 add r0, r7, #4 ; 0x4 + 1300: e1a01003 mov r1, r3 + 1304: ebf608b0 bl 0xffd835cc + 1308: 08000296 stmeqda r0, {r1, r2, r4, r7, r9} + 130c: ebf60b1b bl 0xffd83f80 + 1310: 08000296 stmeqda r0, {r1, r2, r4, r7, r9} + 1314: e3a00f02 mov r0, #8 ; 0x8 + 1318: e3800b01 orr r0, r0, #1024 ; 0x400 + 131c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1320: ebf6097c bl 0xffd83918 + 1324: 0800029a stmeqda r0, {r1, r3, r4, r7, r9} + 1328: e1a03000 mov r3, r0 + 132c: ebf60b13 bl 0xffd83f80 + 1330: 08000298 stmeqda r0, {r3, r4, r7, r9} + 1334: e2870008 add r0, r7, #8 ; 0x8 + 1338: e1a01003 mov r1, r3 + 133c: ebf608a2 bl 0xffd835cc + 1340: 0800029a stmeqda r0, {r1, r3, r4, r7, r9} + 1344: ebf60b0d bl 0xffd83f80 + 1348: 0800029a stmeqda r0, {r1, r3, r4, r7, r9} + 134c: e2870008 add r0, r7, #8 ; 0x8 + 1350: ebf60970 bl 0xffd83918 + 1354: 0800029e stmeqda r0, {r1, r2, r3, r4, r7, r9} + 1358: e1a03000 mov r3, r0 + 135c: ebf60b07 bl 0xffd83f80 + 1360: 0800029c stmeqda r0, {r2, r3, r4, r7, r9} + 1364: e59d0434 ldr r0, [sp, #1076] + 1368: e2800f00 add r0, r0, #0 ; 0x0 + 136c: e1a01008 mov r1, r8 + 1370: ebf60895 bl 0xffd835cc + 1374: 0800029e stmeqda r0, {r1, r2, r3, r4, r7, r9} + 1378: ebf60b00 bl 0xffd83f80 + 137c: 0800029e stmeqda r0, {r1, r2, r3, r4, r7, r9} + 1380: e59d1434 ldr r1, [sp, #1076] + 1384: e1a06001 mov r6, r1 + 1388: ebf60afc bl 0xffd83f80 + 138c: 080002a0 stmeqda r0, {r5, r7, r9} + 1390: e2870000 add r0, r7, #0 ; 0x0 + 1394: e1a01006 mov r1, r6 + 1398: ebf6088b bl 0xffd835cc + 139c: 080002a2 stmeqda r0, {r1, r5, r7, r9} + 13a0: ebf60af6 bl 0xffd83f80 + 13a4: 080002a2 stmeqda r0, {r1, r5, r7, r9} + 13a8: e3b030e0 movs r3, #224 ; 0xe0 + 13ac: ebf60af3 bl 0xffd83f80 + 13b0: 080002a4 stmeqda r0, {r2, r5, r7, r9} + 13b4: e1b03983 movs r3, r3, lsl #19 + 13b8: ebf60af0 bl 0xffd83f80 + 13bc: 080002a6 stmeqda r0, {r1, r2, r5, r7, r9} + 13c0: e2870004 add r0, r7, #4 ; 0x4 + 13c4: e1a01003 mov r1, r3 + 13c8: ebf6087f bl 0xffd835cc + 13cc: 080002a8 stmeqda r0, {r3, r5, r7, r9} + 13d0: ebf60aea bl 0xffd83f80 + 13d4: 080002a8 stmeqda r0, {r3, r5, r7, r9} + 13d8: e3a00f03 mov r0, #12 ; 0xc + 13dc: e3800b01 orr r0, r0, #1024 ; 0x400 + 13e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13e4: ebf6094b bl 0xffd83918 + 13e8: 080002ac stmeqda r0, {r2, r3, r5, r7, r9} + 13ec: e1a03000 mov r3, r0 + 13f0: ebf60ae2 bl 0xffd83f80 + 13f4: 080002aa stmeqda r0, {r1, r3, r5, r7, r9} + 13f8: e2870008 add r0, r7, #8 ; 0x8 + 13fc: e1a01003 mov r1, r3 + 1400: ebf60871 bl 0xffd835cc + 1404: 080002ac stmeqda r0, {r2, r3, r5, r7, r9} + 1408: ebf60adc bl 0xffd83f80 + 140c: 080002ac stmeqda r0, {r2, r3, r5, r7, r9} + 1410: e2870008 add r0, r7, #8 ; 0x8 + 1414: ebf6093f bl 0xffd83918 + 1418: 080002b0 stmeqda r0, {r4, r5, r7, r9} + 141c: e1a03000 mov r3, r0 + 1420: ebf60ad6 bl 0xffd83f80 + 1424: 080002ae stmeqda r0, {r1, r2, r3, r5, r7, r9} + 1428: e3a00e41 mov r0, #1040 ; 0x410 + 142c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1430: ebf60938 bl 0xffd83918 + 1434: 080002b2 stmeqda r0, {r1, r4, r5, r7, r9} + 1438: e1a03000 mov r3, r0 + 143c: ebf60acf bl 0xffd83f80 + 1440: 080002b0 stmeqda r0, {r4, r5, r7, r9} + 1444: e1a01003 mov r1, r3 + 1448: e2930000 adds r0, r3, #0 ; 0x0 + 144c: e58d0418 str r0, [sp, #1048] + 1450: ebf60aca bl 0xffd83f80 + 1454: 080002b2 stmeqda r0, {r1, r4, r5, r7, r9} + 1458: e2840000 add r0, r4, #0 ; 0x0 + 145c: e59d1418 ldr r1, [sp, #1048] + 1460: ebf60839 bl 0xffd8354c + 1464: 080002b4 stmeqda r0, {r2, r4, r5, r7, r9} + 1468: ebf60ac4 bl 0xffd83f80 + 146c: 080002b4 stmeqda r0, {r2, r4, r5, r7, r9} + 1470: e2870000 add r0, r7, #0 ; 0x0 + 1474: e1a01004 mov r1, r4 + 1478: ebf60853 bl 0xffd835cc + 147c: 080002b6 stmeqda r0, {r1, r2, r4, r5, r7, r9} + 1480: ebf60abe bl 0xffd83f80 + 1484: 080002b6 stmeqda r0, {r1, r2, r4, r5, r7, r9} + 1488: e3b030a0 movs r3, #160 ; 0xa0 + 148c: ebf60abb bl 0xffd83f80 + 1490: 080002b8 stmeqda r0, {r3, r4, r5, r7, r9} + 1494: e1b03983 movs r3, r3, lsl #19 + 1498: ebf60ab8 bl 0xffd83f80 + 149c: 080002ba stmeqda r0, {r1, r3, r4, r5, r7, r9} + 14a0: e2870004 add r0, r7, #4 ; 0x4 + 14a4: e1a01003 mov r1, r3 + 14a8: ebf60847 bl 0xffd835cc + 14ac: 080002bc stmeqda r0, {r2, r3, r4, r5, r7, r9} + 14b0: ebf60ab2 bl 0xffd83f80 + 14b4: 080002bc stmeqda r0, {r2, r3, r4, r5, r7, r9} + 14b8: e3a00f05 mov r0, #20 ; 0x14 + 14bc: e3800b01 orr r0, r0, #1024 ; 0x400 + 14c0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14c4: ebf60913 bl 0xffd83918 + 14c8: 080002c0 stmeqda r0, {r6, r7, r9} + 14cc: e1a03000 mov r3, r0 + 14d0: ebf60aaa bl 0xffd83f80 + 14d4: 080002be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9} + 14d8: e2870008 add r0, r7, #8 ; 0x8 + 14dc: e1a01003 mov r1, r3 + 14e0: ebf60839 bl 0xffd835cc + 14e4: 080002c0 stmeqda r0, {r6, r7, r9} + 14e8: ebf60aa4 bl 0xffd83f80 + 14ec: 080002c0 stmeqda r0, {r6, r7, r9} + 14f0: e2870008 add r0, r7, #8 ; 0x8 + 14f4: ebf60907 bl 0xffd83918 + 14f8: 080002c4 stmeqda r0, {r2, r6, r7, r9} + 14fc: e1a03000 mov r3, r0 + 1500: ebf60a9e bl 0xffd83f80 + 1504: 080002c2 stmeqda r0, {r1, r6, r7, r9} + 1508: e3a00f06 mov r0, #24 ; 0x18 + 150c: e3800b01 orr r0, r0, #1024 ; 0x400 + 1510: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1514: ebf608ff bl 0xffd83918 + 1518: 080002c6 stmeqda r0, {r1, r2, r6, r7, r9} + 151c: e1a04000 mov r4, r0 + 1520: ebf60a96 bl 0xffd83f80 + 1524: 080002c4 stmeqda r0, {r2, r6, r7, r9} + 1528: e1a00004 mov r0, r4 + 152c: e58d0420 str r0, [sp, #1056] + 1530: ebf60a92 bl 0xffd83f80 + 1534: 080002c6 stmeqda r0, {r1, r2, r6, r7, r9} + 1538: e3a00f07 mov r0, #28 ; 0x1c + 153c: e3800b01 orr r0, r0, #1024 ; 0x400 + 1540: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1544: ebf608f3 bl 0xffd83918 + 1548: 080002ca stmeqda r0, {r1, r3, r6, r7, r9} + 154c: e1a04000 mov r4, r0 + 1550: ebf60a8a bl 0xffd83f80 + 1554: 080002c8 stmeqda r0, {r3, r6, r7, r9} + 1558: e59d1420 ldr r1, [sp, #1056] + 155c: e0844001 add r4, r4, r1 + 1560: ebf60a86 bl 0xffd83f80 + 1564: 080002ca stmeqda r0, {r1, r3, r6, r7, r9} + 1568: e3b03001 movs r3, #1 ; 0x1 + 156c: ebf60a83 bl 0xffd83f80 + 1570: 080002cc stmeqda r0, {r2, r3, r6, r7, r9} + 1574: e2840000 add r0, r4, #0 ; 0x0 + 1578: e1a01003 mov r1, r3 + 157c: ebf607f2 bl 0xffd8354c + 1580: 080002ce stmeqda r0, {r1, r2, r3, r6, r7, r9} + 1584: ebf60a7d bl 0xffd83f80 + 1588: 080002ce stmeqda r0, {r1, r2, r3, r6, r7, r9} + 158c: ebf60a7b bl 0xffd83f80 + 1590: 080002d0 stmeqda r0, {r4, r6, r7, r9} + 1594: e3a000d3 mov r0, #211 ; 0xd3 + 1598: e3800c02 orr r0, r0, #512 ; 0x200 + 159c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15a0: e58d0438 str r0, [sp, #1080] + 15a4: e28cc0d9 add ip, ip, #217 ; 0xd9 + 15a8: e1a00fac mov r0, ip, lsr #31 + 15ac: e08ff100 add pc, pc, r0, lsl #2 + 15b0: 08000d6c stmeqda r0, {r2, r3, r5, r6, r8, sl, fp} + 15b4: ebf60666 bl 0xffd82f54 + 15b8: ea000001 b 0x15c4 + 15bc: 08000d6c stmeqda r0, {r2, r3, r5, r6, r8, sl, fp} + 15c0: 00000000 andeq r0, r0, r0 + 15c4: ebf60a6d bl 0xffd83f80 + 15c8: 08000d6c stmeqda r0, {r2, r3, r5, r6, r8, sl, fp} + 15cc: e59d9434 ldr r9, [sp, #1076] + 15d0: e3c99003 bic r9, r9, #3 ; 0x3 + 15d4: e249900c sub r9, r9, #12 ; 0xc + 15d8: e58d9434 str r9, [sp, #1076] + 15dc: e2890000 add r0, r9, #0 ; 0x0 + 15e0: e1a01007 mov r1, r7 + 15e4: ebf60818 bl 0xffd8364c + 15e8: e2890004 add r0, r9, #4 ; 0x4 + 15ec: e1a01008 mov r1, r8 + 15f0: ebf60815 bl 0xffd8364c + 15f4: e2890008 add r0, r9, #8 ; 0x8 + 15f8: e59d1438 ldr r1, [sp, #1080] + 15fc: ebf60812 bl 0xffd8364c + 1600: ebf60a5e bl 0xffd83f80 + 1604: 08000d6e stmeqda r0, {r1, r2, r3, r5, r6, r8, sl, fp} + 1608: e59d0434 ldr r0, [sp, #1076] + 160c: e2400f01 sub r0, r0, #4 ; 0x4 + 1610: e58d0434 str r0, [sp, #1076] + 1614: ebf60a59 bl 0xffd83f80 + 1618: 08000d70 stmeqda r0, {r4, r5, r6, r8, sl, fp} + 161c: e3b06000 movs r6, #0 ; 0x0 + 1620: ebf60a56 bl 0xffd83f80 + 1624: 08000d72 stmeqda r0, {r1, r4, r5, r6, r8, sl, fp} + 1628: e3a00f6e mov r0, #440 ; 0x1b8 + 162c: e3800b03 orr r0, r0, #3072 ; 0xc00 + 1630: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1634: ebf608b7 bl 0xffd83918 + 1638: 08000d76 stmeqda r0, {r1, r2, r4, r5, r6, r8, sl, fp} + 163c: e1a03000 mov r3, r0 + 1640: ebf60a4e bl 0xffd83f80 + 1644: 08000d74 stmeqda r0, {r2, r4, r5, r6, r8, sl, fp} + 1648: e3b050a5 movs r5, #165 ; 0xa5 + 164c: ebf60a4b bl 0xffd83f80 + 1650: 08000d76 stmeqda r0, {r1, r2, r4, r5, r6, r8, sl, fp} + 1654: e1b05185 movs r5, r5, lsl #3 + 1658: ebf60a48 bl 0xffd83f80 + 165c: 08000d78 stmeqda r0, {r3, r4, r5, r6, r8, sl, fp} + 1660: e1a01003 mov r1, r3 + 1664: e0934005 adds r4, r3, r5 + 1668: ebf60a44 bl 0xffd83f80 + 166c: 08000d7a stmeqda r0, {r1, r3, r4, r5, r6, r8, sl, fp} + 1670: e3b07094 movs r7, #148 ; 0x94 + 1674: ebf60a41 bl 0xffd83f80 + 1678: 08000d7c stmeqda r0, {r2, r3, r4, r5, r6, r8, sl, fp} + 167c: e1b07087 movs r7, r7, lsl #1 + 1680: ebf60a3e bl 0xffd83f80 + 1684: 08000d7e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, sl, fp} + 1688: e1a01003 mov r1, r3 + 168c: e0935007 adds r5, r3, r7 + 1690: ebf60a3a bl 0xffd83f80 + 1694: 08000d80 stmeqda r0, {r7, r8, sl, fp} + 1698: e2840000 add r0, r4, #0 ; 0x0 + 169c: e1a01005 mov r1, r5 + 16a0: ebf607c9 bl 0xffd835cc + 16a4: 08000d82 stmeqda r0, {r1, r7, r8, sl, fp} + 16a8: ebf60a34 bl 0xffd83f80 + 16ac: 08000d82 stmeqda r0, {r1, r7, r8, sl, fp} + 16b0: e3b080a3 movs r8, #163 ; 0xa3 + 16b4: ebf60a31 bl 0xffd83f80 + 16b8: 08000d84 stmeqda r0, {r2, r7, r8, sl, fp} + 16bc: e1b08188 movs r8, r8, lsl #3 + 16c0: ebf60a2e bl 0xffd83f80 + 16c4: 08000d86 stmeqda r0, {r1, r2, r7, r8, sl, fp} + 16c8: e1a01003 mov r1, r3 + 16cc: e0934008 adds r4, r3, r8 + 16d0: ebf60a2a bl 0xffd83f80 + 16d4: 08000d88 stmeqda r0, {r3, r7, r8, sl, fp} + 16d8: e1a01008 mov r1, r8 + 16dc: e2988014 adds r8, r8, #20 ; 0x14 + 16e0: ebf60a26 bl 0xffd83f80 + 16e4: 08000d8a stmeqda r0, {r1, r3, r7, r8, sl, fp} + 16e8: e1a01003 mov r1, r3 + 16ec: e0937008 adds r7, r3, r8 + 16f0: ebf60a22 bl 0xffd83f80 + 16f4: 08000d8c stmeqda r0, {r2, r3, r7, r8, sl, fp} + 16f8: e1540005 cmp r4, r5 + 16fc: ebf60a1f bl 0xffd83f80 + 1700: 08000d8e stmeqda r0, {r1, r2, r3, r7, r8, sl, fp} + 1704: e28cc03b add ip, ip, #59 ; 0x3b + 1708: 2a000004 bcs 0x1720 + 170c: e1a00fac mov r0, ip, lsr #31 + 1710: e08ff100 add pc, pc, r0, lsl #2 + 1714: 08000d9c stmeqda r0, {r2, r3, r4, r7, r8, sl, fp} + 1718: ebf6060d bl 0xffd82f54 + 171c: ea00001e b 0x179c + 1720: ebf60a16 bl 0xffd83f80 + 1724: 08000d90 stmeqda r0, {r4, r7, r8, sl, fp} + 1728: e1a01005 mov r1, r5 + 172c: e2953000 adds r3, r5, #0 ; 0x0 + 1730: e28cc003 add ip, ip, #3 ; 0x3 + 1734: ebf60a11 bl 0xffd83f80 + 1738: 08000d92 stmeqda r0, {r1, r4, r7, r8, sl, fp} + 173c: e284000c add r0, r4, #12 ; 0xc + 1740: e1a01006 mov r1, r6 + 1744: ebf607a0 bl 0xffd835cc + 1748: 08000d94 stmeqda r0, {r2, r4, r7, r8, sl, fp} + 174c: ebf60a0b bl 0xffd83f80 + 1750: 08000d94 stmeqda r0, {r2, r4, r7, r8, sl, fp} + 1754: e1a01004 mov r1, r4 + 1758: e2946000 adds r6, r4, #0 ; 0x0 + 175c: ebf60a07 bl 0xffd83f80 + 1760: 08000d96 stmeqda r0, {r1, r2, r4, r7, r8, sl, fp} + 1764: e1a01004 mov r1, r4 + 1768: e2544010 subs r4, r4, #16 ; 0x10 + 176c: ebf60a03 bl 0xffd83f80 + 1770: 08000d98 stmeqda r0, {r3, r4, r7, r8, sl, fp} + 1774: e1540003 cmp r4, r3 + 1778: ebf60a00 bl 0xffd83f80 + 177c: 08000d9a stmeqda r0, {r1, r3, r4, r7, r8, sl, fp} + 1780: e28cc010 add ip, ip, #16 ; 0x10 + 1784: 3a000004 bcc 0x179c + 1788: e1a00fac mov r0, ip, lsr #31 + 178c: e08ff100 add pc, pc, r0, lsl #2 + 1790: 08000d92 stmeqda r0, {r1, r4, r7, r8, sl, fp} + 1794: ebf605ee bl 0xffd82f54 + 1798: eaffffe5 b 0x1734 + 179c: ebf609f7 bl 0xffd83f80 + 17a0: 08000d9c stmeqda r0, {r2, r3, r4, r7, r8, sl, fp} + 17a4: e3b03000 movs r3, #0 ; 0x0 + 17a8: ebf609f4 bl 0xffd83f80 + 17ac: 08000d9e stmeqda r0, {r1, r2, r3, r4, r7, r8, sl, fp} + 17b0: e59d0434 ldr r0, [sp, #1076] + 17b4: e2800f00 add r0, r0, #0 ; 0x0 + 17b8: e1a01003 mov r1, r3 + 17bc: ebf60782 bl 0xffd835cc + 17c0: 08000da0 stmeqda r0, {r5, r7, r8, sl, fp} + 17c4: ebf609ed bl 0xffd83f80 + 17c8: 08000da0 stmeqda r0, {r5, r7, r8, sl, fp} + 17cc: e3a00f6f mov r0, #444 ; 0x1bc + 17d0: e3800b03 orr r0, r0, #3072 ; 0xc00 + 17d4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 17d8: ebf6084e bl 0xffd83918 + 17dc: 08000da4 stmeqda r0, {r2, r5, r7, r8, sl, fp} + 17e0: e1a03000 mov r3, r0 + 17e4: ebf609e5 bl 0xffd83f80 + 17e8: 08000da2 stmeqda r0, {r1, r5, r7, r8, sl, fp} + 17ec: e59d1434 ldr r1, [sp, #1076] + 17f0: e1a04001 mov r4, r1 + 17f4: ebf609e1 bl 0xffd83f80 + 17f8: 08000da4 stmeqda r0, {r2, r5, r7, r8, sl, fp} + 17fc: e2830000 add r0, r3, #0 ; 0x0 + 1800: e1a01004 mov r1, r4 + 1804: ebf60770 bl 0xffd835cc + 1808: 08000da6 stmeqda r0, {r1, r2, r5, r7, r8, sl, fp} + 180c: ebf609db bl 0xffd83f80 + 1810: 08000da6 stmeqda r0, {r1, r2, r5, r7, r8, sl, fp} + 1814: e2830004 add r0, r3, #4 ; 0x4 + 1818: e1a01007 mov r1, r7 + 181c: ebf6076a bl 0xffd835cc + 1820: 08000da8 stmeqda r0, {r3, r5, r7, r8, sl, fp} + 1824: ebf609d5 bl 0xffd83f80 + 1828: 08000da8 stmeqda r0, {r3, r5, r7, r8, sl, fp} + 182c: e3a00d37 mov r0, #3520 ; 0xdc0 + 1830: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1834: ebf60837 bl 0xffd83918 + 1838: 08000dac stmeqda r0, {r2, r3, r5, r7, r8, sl, fp} + 183c: e1a04000 mov r4, r0 + 1840: ebf609ce bl 0xffd83f80 + 1844: 08000daa stmeqda r0, {r1, r3, r5, r7, r8, sl, fp} + 1848: e2830008 add r0, r3, #8 ; 0x8 + 184c: e1a01004 mov r1, r4 + 1850: ebf6075d bl 0xffd835cc + 1854: 08000dac stmeqda r0, {r2, r3, r5, r7, r8, sl, fp} + 1858: ebf609c8 bl 0xffd83f80 + 185c: 08000dac stmeqda r0, {r2, r3, r5, r7, r8, sl, fp} + 1860: e2830008 add r0, r3, #8 ; 0x8 + 1864: ebf6082b bl 0xffd83918 + 1868: 08000db0 stmeqda r0, {r4, r5, r7, r8, sl, fp} + 186c: e1a03000 mov r3, r0 + 1870: ebf609c2 bl 0xffd83f80 + 1874: 08000dae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, fp} + 1878: e59d0434 ldr r0, [sp, #1076] + 187c: e2800f01 add r0, r0, #4 ; 0x4 + 1880: e58d0434 str r0, [sp, #1076] + 1884: ebf609bd bl 0xffd83f80 + 1888: 08000db0 stmeqda r0, {r4, r5, r7, r8, sl, fp} + 188c: e59d9434 ldr r9, [sp, #1076] + 1890: e3c99003 bic r9, r9, #3 ; 0x3 + 1894: e2890008 add r0, r9, #8 ; 0x8 + 1898: e58d0434 str r0, [sp, #1076] + 189c: e2890000 add r0, r9, #0 ; 0x0 + 18a0: ebf6081c bl 0xffd83918 + 18a4: 08000db4 stmeqda r0, {r2, r4, r5, r7, r8, sl, fp} + 18a8: e1a07000 mov r7, r0 + 18ac: e2890004 add r0, r9, #4 ; 0x4 + 18b0: ebf60818 bl 0xffd83918 + 18b4: 08000db4 stmeqda r0, {r2, r4, r5, r7, r8, sl, fp} + 18b8: e1a08000 mov r8, r0 + 18bc: ebf609af bl 0xffd83f80 + 18c0: 08000db2 stmeqda r0, {r1, r4, r5, r7, r8, sl, fp} + 18c4: e59d9434 ldr r9, [sp, #1076] + 18c8: e3c99003 bic r9, r9, #3 ; 0x3 + 18cc: e2890004 add r0, r9, #4 ; 0x4 + 18d0: e58d0434 str r0, [sp, #1076] + 18d4: e2890000 add r0, r9, #0 ; 0x0 + 18d8: ebf6080e bl 0xffd83918 + 18dc: 08000db6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl, fp} + 18e0: e1a03000 mov r3, r0 + 18e4: ebf609a5 bl 0xffd83f80 + 18e8: 08000db4 stmeqda r0, {r2, r4, r5, r7, r8, sl, fp} + 18ec: e1a00003 mov r0, r3 + 18f0: e28cc034 add ip, ip, #52 ; 0x34 + 18f4: eaf605f5 b 0xffd830d0 + 18f8: 080002d2 stmeqda r0, {r1, r4, r6, r7, r9} + 18fc: 00000000 andeq r0, r0, r0 + 1900: ebf6099e bl 0xffd83f80 + 1904: 080002d2 stmeqda r0, {r1, r4, r6, r7, r9} + 1908: ebf6099c bl 0xffd83f80 + 190c: 080002d4 stmeqda r0, {r2, r4, r6, r7, r9} + 1910: e3a000d7 mov r0, #215 ; 0xd7 + 1914: e3800c02 orr r0, r0, #512 ; 0x200 + 1918: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 191c: e58d0438 str r0, [sp, #1080] + 1920: e28cc006 add ip, ip, #6 ; 0x6 + 1924: e1a00fac mov r0, ip, lsr #31 + 1928: e08ff100 add pc, pc, r0, lsl #2 + 192c: 080c03a4 stmeqda ip, {r2, r5, r7, r8, r9} + 1930: ebf60587 bl 0xffd82f54 + 1934: ea000001 b 0x1940 + 1938: 080c03a4 stmeqda ip, {r2, r5, r7, r8, r9} + 193c: 00000000 andeq r0, r0, r0 + 1940: ebf6098e bl 0xffd83f80 + 1944: 080c03a4 stmeqda ip, {r2, r5, r7, r8, r9} + 1948: e59d9434 ldr r9, [sp, #1076] + 194c: e3c99003 bic r9, r9, #3 ; 0x3 + 1950: e2499014 sub r9, r9, #20 ; 0x14 + 1954: e58d9434 str r9, [sp, #1076] + 1958: e2890000 add r0, r9, #0 ; 0x0 + 195c: e1a01007 mov r1, r7 + 1960: ebf60739 bl 0xffd8364c + 1964: e2890004 add r0, r9, #4 ; 0x4 + 1968: e1a01008 mov r1, r8 + 196c: ebf60736 bl 0xffd8364c + 1970: e2890008 add r0, r9, #8 ; 0x8 + 1974: e59d1418 ldr r1, [sp, #1048] + 1978: ebf60733 bl 0xffd8364c + 197c: e289000c add r0, r9, #12 ; 0xc + 1980: e59d141c ldr r1, [sp, #1052] + 1984: ebf60730 bl 0xffd8364c + 1988: e2890010 add r0, r9, #16 ; 0x10 + 198c: e59d1438 ldr r1, [sp, #1080] + 1990: ebf6072d bl 0xffd8364c + 1994: ebf60979 bl 0xffd83f80 + 1998: 080c03a6 stmeqda ip, {r1, r2, r5, r7, r8, r9} + 199c: e59d1420 ldr r1, [sp, #1056] + 19a0: e1a00001 mov r0, r1 + 19a4: e58d041c str r0, [sp, #1052] + 19a8: ebf60974 bl 0xffd83f80 + 19ac: 080c03a8 stmeqda ip, {r3, r5, r7, r8, r9} + 19b0: e59d9434 ldr r9, [sp, #1076] + 19b4: e3c99003 bic r9, r9, #3 ; 0x3 + 19b8: e2499004 sub r9, r9, #4 ; 0x4 + 19bc: e58d9434 str r9, [sp, #1076] + 19c0: e2890000 add r0, r9, #0 ; 0x0 + 19c4: e59d141c ldr r1, [sp, #1052] + 19c8: ebf606ff bl 0xffd835cc + 19cc: 080c03aa stmeqda ip, {r1, r3, r5, r7, r8, r9} + 19d0: ebf6096a bl 0xffd83f80 + 19d4: 080c03aa stmeqda ip, {r1, r3, r5, r7, r8, r9} + 19d8: e3a00f03 mov r0, #12 ; 0xc + 19dc: e3800b01 orr r0, r0, #1024 ; 0x400 + 19e0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 19e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 19e8: ebf607ca bl 0xffd83918 + 19ec: 080c03ae stmeqda ip, {r1, r2, r3, r5, r7, r8, r9} + 19f0: e1a03000 mov r3, r0 + 19f4: ebf60961 bl 0xffd83f80 + 19f8: 080c03ac stmeqda ip, {r2, r3, r5, r7, r8, r9} + 19fc: e3b04002 movs r4, #2 ; 0x2 + 1a00: ebf6095e bl 0xffd83f80 + 1a04: 080c03ae stmeqda ip, {r1, r2, r3, r5, r7, r8, r9} + 1a08: e3a01000 mov r1, #0 ; 0x0 + 1a0c: e0514004 subs r4, r1, r4 + 1a10: ebf6095a bl 0xffd83f80 + 1a14: 080c03b0 stmeqda ip, {r4, r5, r7, r8, r9} + 1a18: e1a01003 mov r1, r3 + 1a1c: e0133004 ands r3, r3, r4 + 1a20: ebf60956 bl 0xffd83f80 + 1a24: 080c03b2 stmeqda ip, {r1, r4, r5, r7, r8, r9} + 1a28: e3a00e41 mov r0, #1040 ; 0x410 + 1a2c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1a30: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1a34: ebf607b7 bl 0xffd83918 + 1a38: 080c03b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9} + 1a3c: e1a04000 mov r4, r0 + 1a40: ebf6094e bl 0xffd83f80 + 1a44: 080c03b4 stmeqda ip, {r2, r4, r5, r7, r8, r9} + 1a48: e3a00f05 mov r0, #20 ; 0x14 + 1a4c: e3800b01 orr r0, r0, #1024 ; 0x400 + 1a50: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1a54: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1a58: ebf607ae bl 0xffd83918 + 1a5c: 080c03b8 stmeqda ip, {r3, r4, r5, r7, r8, r9} + 1a60: e1a05000 mov r5, r0 + 1a64: ebf60945 bl 0xffd83f80 + 1a68: 080c03b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9} + 1a6c: ebf60943 bl 0xffd83f80 + 1a70: 080c03b8 stmeqda ip, {r3, r4, r5, r7, r8, r9} + 1a74: e3a000bb mov r0, #187 ; 0xbb + 1a78: e3800c03 orr r0, r0, #768 ; 0x300 + 1a7c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1a80: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1a84: e58d0438 str r0, [sp, #1080] + 1a88: e28cc02c add ip, ip, #44 ; 0x2c + 1a8c: e1a00fac mov r0, ip, lsr #31 + 1a90: e08ff100 add pc, pc, r0, lsl #2 + 1a94: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 1a98: ebf6052d bl 0xffd82f54 + 1a9c: ea000001 b 0x1aa8 + 1aa0: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 1aa4: 00000000 andeq r0, r0, r0 + 1aa8: ebf60934 bl 0xffd83f80 + 1aac: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 1ab0: ebf60619 bl 0xffd8331c + 1ab4: 080c2f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp, sp} + 1ab8: e28cc003 add ip, ip, #3 ; 0x3 + 1abc: e1a00fac mov r0, ip, lsr #31 + 1ac0: e08ff100 add pc, pc, r0, lsl #2 + 1ac4: 00000008 andeq r0, r0, r8 + 1ac8: ebf604eb bl 0xffd82e7c + 1acc: ea2af94b b 0xac0000 + 1ad0: 080c2f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp, sp} + 1ad4: 00000000 andeq r0, r0, r0 + 1ad8: ebf60928 bl 0xffd83f80 + 1adc: 080c2f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp, sp} + 1ae0: e59d0438 ldr r0, [sp, #1080] + 1ae4: e28cc003 add ip, ip, #3 ; 0x3 + 1ae8: eaf60578 b 0xffd830d0 + 1aec: 080c03ba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9} + 1af0: 00000000 andeq r0, r0, r0 + 1af4: ebf60921 bl 0xffd83f80 + 1af8: 080c03ba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9} + 1afc: e3a00f06 mov r0, #24 ; 0x18 + 1b00: e3800b01 orr r0, r0, #1024 ; 0x400 + 1b04: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1b08: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1b0c: ebf60781 bl 0xffd83918 + 1b10: 080c03be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9} + 1b14: e1a03000 mov r3, r0 + 1b18: ebf60918 bl 0xffd83f80 + 1b1c: 080c03bc stmeqda ip, {r2, r3, r4, r5, r7, r8, r9} + 1b20: ebf60916 bl 0xffd83f80 + 1b24: 080c03be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9} + 1b28: e3a000c1 mov r0, #193 ; 0xc1 + 1b2c: e3800c03 orr r0, r0, #768 ; 0x300 + 1b30: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1b34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1b38: e58d0438 str r0, [sp, #1080] + 1b3c: e28cc00b add ip, ip, #11 ; 0xb + 1b40: e1a00fac mov r0, ip, lsr #31 + 1b44: e08ff100 add pc, pc, r0, lsl #2 + 1b48: 080c076c stmeqda ip, {r2, r3, r5, r6, r8, r9, sl} + 1b4c: ebf60500 bl 0xffd82f54 + 1b50: ea000001 b 0x1b5c + 1b54: 080c076c stmeqda ip, {r2, r3, r5, r6, r8, r9, sl} + 1b58: 00000000 andeq r0, r0, r0 + 1b5c: ebf60907 bl 0xffd83f80 + 1b60: 080c076c stmeqda ip, {r2, r3, r5, r6, r8, r9, sl} + 1b64: e59d9434 ldr r9, [sp, #1076] + 1b68: e3c99003 bic r9, r9, #3 ; 0x3 + 1b6c: e2499008 sub r9, r9, #8 ; 0x8 + 1b70: e58d9434 str r9, [sp, #1076] + 1b74: e2890000 add r0, r9, #0 ; 0x0 + 1b78: e1a01007 mov r1, r7 + 1b7c: ebf606b2 bl 0xffd8364c + 1b80: e2890004 add r0, r9, #4 ; 0x4 + 1b84: e59d1438 ldr r1, [sp, #1080] + 1b88: ebf606af bl 0xffd8364c + 1b8c: ebf608fb bl 0xffd83f80 + 1b90: 080c076e stmeqda ip, {r1, r2, r3, r5, r6, r8, r9, sl} + 1b94: e59d0434 ldr r0, [sp, #1076] + 1b98: e2400f01 sub r0, r0, #4 ; 0x4 + 1b9c: e58d0434 str r0, [sp, #1076] + 1ba0: ebf608f6 bl 0xffd83f80 + 1ba4: 080c0770 stmeqda ip, {r4, r5, r6, r8, r9, sl} + 1ba8: e1a01003 mov r1, r3 + 1bac: e2937000 adds r7, r3, #0 ; 0x0 + 1bb0: ebf608f2 bl 0xffd83f80 + 1bb4: 080c0772 stmeqda ip, {r1, r4, r5, r6, r8, r9, sl} + 1bb8: e3b06000 movs r6, #0 ; 0x0 + 1bbc: ebf608ef bl 0xffd83f80 + 1bc0: 080c0774 stmeqda ip, {r2, r4, r5, r6, r8, r9, sl} + 1bc4: e2870000 add r0, r7, #0 ; 0x0 + 1bc8: e1a01006 mov r1, r6 + 1bcc: ebf6067e bl 0xffd835cc + 1bd0: 080c0776 stmeqda ip, {r1, r2, r4, r5, r6, r8, r9, sl} + 1bd4: ebf608e9 bl 0xffd83f80 + 1bd8: 080c0776 stmeqda ip, {r1, r2, r4, r5, r6, r8, r9, sl} + 1bdc: e3a00ffe mov r0, #1016 ; 0x3f8 + 1be0: e3800b01 orr r0, r0, #1024 ; 0x400 + 1be4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1be8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1bec: ebf60749 bl 0xffd83918 + 1bf0: 080c077a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, sl} + 1bf4: e1a03000 mov r3, r0 + 1bf8: ebf608e0 bl 0xffd83f80 + 1bfc: 080c0778 stmeqda ip, {r3, r4, r5, r6, r8, r9, sl} + 1c00: e2830000 add r0, r3, #0 ; 0x0 + 1c04: e1a01006 mov r1, r6 + 1c08: ebf6064f bl 0xffd8354c + 1c0c: 080c077a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, sl} + 1c10: ebf608da bl 0xffd83f80 + 1c14: 080c077a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, sl} + 1c18: e1a01003 mov r1, r3 + 1c1c: e293300c adds r3, r3, #12 ; 0xc + 1c20: ebf608d6 bl 0xffd83f80 + 1c24: 080c077c stmeqda ip, {r2, r3, r4, r5, r6, r8, r9, sl} + 1c28: e2830000 add r0, r3, #0 ; 0x0 + 1c2c: e1a01006 mov r1, r6 + 1c30: ebf60645 bl 0xffd8354c + 1c34: 080c077e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, r9, sl} + 1c38: ebf608d0 bl 0xffd83f80 + 1c3c: 080c077e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, r9, sl} + 1c40: e3a00fff mov r0, #1020 ; 0x3fc + 1c44: e3800b01 orr r0, r0, #1024 ; 0x400 + 1c48: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1c4c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1c50: ebf60730 bl 0xffd83918 + 1c54: 080c0782 stmeqda ip, {r1, r7, r8, r9, sl} + 1c58: e1a04000 mov r4, r0 + 1c5c: ebf608c7 bl 0xffd83f80 + 1c60: 080c0780 stmeqda ip, {r7, r8, r9, sl} + 1c64: e3b0308f movs r3, #143 ; 0x8f + 1c68: ebf608c4 bl 0xffd83f80 + 1c6c: 080c0782 stmeqda ip, {r1, r7, r8, r9, sl} + 1c70: e2840000 add r0, r4, #0 ; 0x0 + 1c74: e1a01003 mov r1, r3 + 1c78: ebf60633 bl 0xffd8354c + 1c7c: 080c0784 stmeqda ip, {r2, r7, r8, r9, sl} + 1c80: ebf608be bl 0xffd83f80 + 1c84: 080c0784 stmeqda ip, {r2, r7, r8, r9, sl} + 1c88: e1a01004 mov r1, r4 + 1c8c: e2544002 subs r4, r4, #2 ; 0x2 + 1c90: ebf608ba bl 0xffd83f80 + 1c94: 080c0786 stmeqda ip, {r1, r2, r7, r8, r9, sl} + 1c98: e3a00b02 mov r0, #2048 ; 0x800 + 1c9c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1ca0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ca4: ebf6071b bl 0xffd83918 + 1ca8: 080c078a stmeqda ip, {r1, r3, r7, r8, r9, sl} + 1cac: e1a05000 mov r5, r0 + 1cb0: ebf608b2 bl 0xffd83f80 + 1cb4: 080c0788 stmeqda ip, {r3, r7, r8, r9, sl} + 1cb8: e1a01005 mov r1, r5 + 1cbc: e2953000 adds r3, r5, #0 ; 0x0 + 1cc0: ebf608ae bl 0xffd83f80 + 1cc4: 080c078a stmeqda ip, {r1, r3, r7, r8, r9, sl} + 1cc8: e2840000 add r0, r4, #0 ; 0x0 + 1ccc: e1a01003 mov r1, r3 + 1cd0: ebf6061d bl 0xffd8354c + 1cd4: 080c078c stmeqda ip, {r2, r3, r7, r8, r9, sl} + 1cd8: ebf608a8 bl 0xffd83f80 + 1cdc: 080c078c stmeqda ip, {r2, r3, r7, r8, r9, sl} + 1ce0: e3a00f01 mov r0, #4 ; 0x4 + 1ce4: e3800b02 orr r0, r0, #2048 ; 0x800 + 1ce8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1cec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1cf0: ebf60708 bl 0xffd83918 + 1cf4: 080c0790 stmeqda ip, {r4, r7, r8, r9, sl} + 1cf8: e1a05000 mov r5, r0 + 1cfc: ebf6089f bl 0xffd83f80 + 1d00: 080c078e stmeqda ip, {r1, r2, r3, r7, r8, r9, sl} + 1d04: e2850000 add r0, r5, #0 ; 0x0 + 1d08: ebf606ab bl 0xffd837bc + 1d0c: 080c0792 stmeqda ip, {r1, r4, r7, r8, r9, sl} + 1d10: e1a04000 mov r4, r0 + 1d14: ebf60899 bl 0xffd83f80 + 1d18: 080c0790 stmeqda ip, {r4, r7, r8, r9, sl} + 1d1c: e3b0303f movs r3, #63 ; 0x3f + 1d20: ebf60896 bl 0xffd83f80 + 1d24: 080c0792 stmeqda ip, {r1, r4, r7, r8, r9, sl} + 1d28: e1a01003 mov r1, r3 + 1d2c: e0133004 ands r3, r3, r4 + 1d30: ebf60892 bl 0xffd83f80 + 1d34: 080c0794 stmeqda ip, {r2, r4, r7, r8, r9, sl} + 1d38: e3b04040 movs r4, #64 ; 0x40 + 1d3c: ebf6088f bl 0xffd83f80 + 1d40: 080c0796 stmeqda ip, {r1, r2, r4, r7, r8, r9, sl} + 1d44: e1a01003 mov r1, r3 + 1d48: e1933004 orrs r3, r3, r4 + 1d4c: ebf6088b bl 0xffd83f80 + 1d50: 080c0798 stmeqda ip, {r3, r4, r7, r8, r9, sl} + 1d54: e2850000 add r0, r5, #0 ; 0x0 + 1d58: e1a01003 mov r1, r3 + 1d5c: ebf605db bl 0xffd834d0 + 1d60: 080c079a stmeqda ip, {r1, r3, r4, r7, r8, r9, sl} + 1d64: ebf60885 bl 0xffd83f80 + 1d68: 080c079a stmeqda ip, {r1, r3, r4, r7, r8, r9, sl} + 1d6c: e3a00f02 mov r0, #8 ; 0x8 + 1d70: e3800b02 orr r0, r0, #2048 ; 0x800 + 1d74: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1d78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1d7c: ebf606e5 bl 0xffd83918 + 1d80: 080c079e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, sl} + 1d84: e1a04000 mov r4, r0 + 1d88: ebf6087c bl 0xffd83f80 + 1d8c: 080c079c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl} + 1d90: e3b050d4 movs r5, #212 ; 0xd4 + 1d94: ebf60879 bl 0xffd83f80 + 1d98: 080c079e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, sl} + 1d9c: e1b05105 movs r5, r5, lsl #2 + 1da0: ebf60876 bl 0xffd83f80 + 1da4: 080c07a0 stmeqda ip, {r5, r7, r8, r9, sl} + 1da8: e1a01007 mov r1, r7 + 1dac: e0973005 adds r3, r7, r5 + 1db0: ebf60872 bl 0xffd83f80 + 1db4: 080c07a2 stmeqda ip, {r1, r5, r7, r8, r9, sl} + 1db8: e2840000 add r0, r4, #0 ; 0x0 + 1dbc: e1a01003 mov r1, r3 + 1dc0: ebf60601 bl 0xffd835cc + 1dc4: 080c07a4 stmeqda ip, {r2, r5, r7, r8, r9, sl} + 1dc8: ebf6086c bl 0xffd83f80 + 1dcc: 080c07a4 stmeqda ip, {r2, r5, r7, r8, r9, sl} + 1dd0: e1a01004 mov r1, r4 + 1dd4: e2944004 adds r4, r4, #4 ; 0x4 + 1dd8: ebf60868 bl 0xffd83f80 + 1ddc: 080c07a6 stmeqda ip, {r1, r2, r5, r7, r8, r9, sl} + 1de0: e3a00f03 mov r0, #12 ; 0xc + 1de4: e3800b02 orr r0, r0, #2048 ; 0x800 + 1de8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1dec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1df0: ebf606c8 bl 0xffd83918 + 1df4: 080c07aa stmeqda ip, {r1, r3, r5, r7, r8, r9, sl} + 1df8: e1a03000 mov r3, r0 + 1dfc: ebf6085f bl 0xffd83f80 + 1e00: 080c07a8 stmeqda ip, {r3, r5, r7, r8, r9, sl} + 1e04: e2840000 add r0, r4, #0 ; 0x0 + 1e08: e1a01003 mov r1, r3 + 1e0c: ebf605ee bl 0xffd835cc + 1e10: 080c07aa stmeqda ip, {r1, r3, r5, r7, r8, r9, sl} + 1e14: ebf60859 bl 0xffd83f80 + 1e18: 080c07aa stmeqda ip, {r1, r3, r5, r7, r8, r9, sl} + 1e1c: e1a01004 mov r1, r4 + 1e20: e2944008 adds r4, r4, #8 ; 0x8 + 1e24: ebf60855 bl 0xffd83f80 + 1e28: 080c07ac stmeqda ip, {r2, r3, r5, r7, r8, r9, sl} + 1e2c: e3b05098 movs r5, #152 ; 0x98 + 1e30: ebf60852 bl 0xffd83f80 + 1e34: 080c07ae stmeqda ip, {r1, r2, r3, r5, r7, r8, r9, sl} + 1e38: e1b05205 movs r5, r5, lsl #4 + 1e3c: ebf6084f bl 0xffd83f80 + 1e40: 080c07b0 stmeqda ip, {r4, r5, r7, r8, r9, sl} + 1e44: e1a01007 mov r1, r7 + 1e48: e0973005 adds r3, r7, r5 + 1e4c: ebf6084b bl 0xffd83f80 + 1e50: 080c07b2 stmeqda ip, {r1, r4, r5, r7, r8, r9, sl} + 1e54: e2840000 add r0, r4, #0 ; 0x0 + 1e58: e1a01003 mov r1, r3 + 1e5c: ebf605da bl 0xffd835cc + 1e60: 080c07b4 stmeqda ip, {r2, r4, r5, r7, r8, r9, sl} + 1e64: ebf60845 bl 0xffd83f80 + 1e68: 080c07b4 stmeqda ip, {r2, r4, r5, r7, r8, r9, sl} + 1e6c: e1a01004 mov r1, r4 + 1e70: e2944004 adds r4, r4, #4 ; 0x4 + 1e74: ebf60841 bl 0xffd83f80 + 1e78: 080c07b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9, sl} + 1e7c: e3a00e81 mov r0, #2064 ; 0x810 + 1e80: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1e84: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1e88: ebf606a2 bl 0xffd83918 + 1e8c: 080c07ba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9, sl} + 1e90: e1a03000 mov r3, r0 + 1e94: ebf60839 bl 0xffd83f80 + 1e98: 080c07b8 stmeqda ip, {r3, r4, r5, r7, r8, r9, sl} + 1e9c: e2840000 add r0, r4, #0 ; 0x0 + 1ea0: e1a01003 mov r1, r3 + 1ea4: ebf605c8 bl 0xffd835cc + 1ea8: 080c07ba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9, sl} + 1eac: ebf60833 bl 0xffd83f80 + 1eb0: 080c07ba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9, sl} + 1eb4: e3a00f05 mov r0, #20 ; 0x14 + 1eb8: e3800b02 orr r0, r0, #2048 ; 0x800 + 1ebc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1ec0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ec4: ebf60693 bl 0xffd83918 + 1ec8: 080c07be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 1ecc: e1a03000 mov r3, r0 + 1ed0: ebf6082a bl 0xffd83f80 + 1ed4: 080c07bc stmeqda ip, {r2, r3, r4, r5, r7, r8, r9, sl} + 1ed8: e2830000 add r0, r3, #0 ; 0x0 + 1edc: e1a01007 mov r1, r7 + 1ee0: ebf605b9 bl 0xffd835cc + 1ee4: 080c07be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 1ee8: ebf60824 bl 0xffd83f80 + 1eec: 080c07be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 1ef0: e59d0434 ldr r0, [sp, #1076] + 1ef4: e2800f00 add r0, r0, #0 ; 0x0 + 1ef8: e1a01006 mov r1, r6 + 1efc: ebf605b2 bl 0xffd835cc + 1f00: 080c07c0 stmeqda ip, {r6, r7, r8, r9, sl} + 1f04: ebf6081d bl 0xffd83f80 + 1f08: 080c07c0 stmeqda ip, {r6, r7, r8, r9, sl} + 1f0c: e3a00f06 mov r0, #24 ; 0x18 + 1f10: e3800b02 orr r0, r0, #2048 ; 0x800 + 1f14: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1f18: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f1c: ebf6067d bl 0xffd83918 + 1f20: 080c07c4 stmeqda ip, {r2, r6, r7, r8, r9, sl} + 1f24: e1a05000 mov r5, r0 + 1f28: ebf60814 bl 0xffd83f80 + 1f2c: 080c07c2 stmeqda ip, {r1, r6, r7, r8, r9, sl} + 1f30: e59d1434 ldr r1, [sp, #1076] + 1f34: e1a03001 mov r3, r1 + 1f38: ebf60810 bl 0xffd83f80 + 1f3c: 080c07c4 stmeqda ip, {r2, r6, r7, r8, r9, sl} + 1f40: e1a01007 mov r1, r7 + 1f44: e2974000 adds r4, r7, #0 ; 0x0 + 1f48: ebf6080c bl 0xffd83f80 + 1f4c: 080c07c6 stmeqda ip, {r1, r2, r6, r7, r8, r9, sl} + 1f50: ebf6080a bl 0xffd83f80 + 1f54: 080c07c8 stmeqda ip, {r3, r6, r7, r8, r9, sl} + 1f58: e3a000cb mov r0, #203 ; 0xcb + 1f5c: e3800c07 orr r0, r0, #1792 ; 0x700 + 1f60: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1f64: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f68: e58d0438 str r0, [sp, #1080] + 1f6c: e28cc0ae add ip, ip, #174 ; 0xae + 1f70: e1a00fac mov r0, ip, lsr #31 + 1f74: e08ff100 add pc, pc, r0, lsl #2 + 1f78: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 1f7c: ebf603f4 bl 0xffd82f54 + 1f80: eafffec8 b 0x1aa8 + 1f84: 080c07ca stmeqda ip, {r1, r3, r6, r7, r8, r9, sl} + 1f88: 00000000 andeq r0, r0, r0 + 1f8c: ebf607fb bl 0xffd83f80 + 1f90: 080c07ca stmeqda ip, {r1, r3, r6, r7, r8, r9, sl} + 1f94: e3b03008 movs r3, #8 ; 0x8 + 1f98: ebf607f8 bl 0xffd83f80 + 1f9c: 080c07cc stmeqda ip, {r2, r3, r6, r7, r8, r9, sl} + 1fa0: e2870006 add r0, r7, #6 ; 0x6 + 1fa4: e1a01003 mov r1, r3 + 1fa8: ebf60548 bl 0xffd834d0 + 1fac: 080c07ce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9, sl} + 1fb0: ebf607f2 bl 0xffd83f80 + 1fb4: 080c07ce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9, sl} + 1fb8: e3b0300f movs r3, #15 ; 0xf + 1fbc: ebf607ef bl 0xffd83f80 + 1fc0: 080c07d0 stmeqda ip, {r4, r6, r7, r8, r9, sl} + 1fc4: e2870007 add r0, r7, #7 ; 0x7 + 1fc8: e1a01003 mov r1, r3 + 1fcc: ebf6053f bl 0xffd834d0 + 1fd0: 080c07d2 stmeqda ip, {r1, r4, r6, r7, r8, r9, sl} + 1fd4: ebf607e9 bl 0xffd83f80 + 1fd8: 080c07d2 stmeqda ip, {r1, r4, r6, r7, r8, r9, sl} + 1fdc: e3a00f07 mov r0, #28 ; 0x1c + 1fe0: e3800b02 orr r0, r0, #2048 ; 0x800 + 1fe4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1fe8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fec: ebf60649 bl 0xffd83918 + 1ff0: 080c07d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, sl} + 1ff4: e1a03000 mov r3, r0 + 1ff8: ebf607e0 bl 0xffd83f80 + 1ffc: 080c07d4 stmeqda ip, {r2, r4, r6, r7, r8, r9, sl} + 2000: e2870038 add r0, r7, #56 ; 0x38 + 2004: e1a01003 mov r1, r3 + 2008: ebf6056f bl 0xffd835cc + 200c: 080c07d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, sl} + 2010: ebf607da bl 0xffd83f80 + 2014: 080c07d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, sl} + 2018: e3a00e82 mov r0, #2080 ; 0x820 + 201c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2020: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2024: ebf6063b bl 0xffd83918 + 2028: 080c07da stmeqda ip, {r1, r3, r4, r6, r7, r8, r9, sl} + 202c: e1a03000 mov r3, r0 + 2030: ebf607d2 bl 0xffd83f80 + 2034: 080c07d8 stmeqda ip, {r3, r4, r6, r7, r8, r9, sl} + 2038: e2870028 add r0, r7, #40 ; 0x28 + 203c: e1a01003 mov r1, r3 + 2040: ebf60561 bl 0xffd835cc + 2044: 080c07da stmeqda ip, {r1, r3, r4, r6, r7, r8, r9, sl} + 2048: ebf607cc bl 0xffd83f80 + 204c: 080c07da stmeqda ip, {r1, r3, r4, r6, r7, r8, r9, sl} + 2050: e287002c add r0, r7, #44 ; 0x2c + 2054: e1a01003 mov r1, r3 + 2058: ebf6055b bl 0xffd835cc + 205c: 080c07dc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9, sl} + 2060: ebf607c6 bl 0xffd83f80 + 2064: 080c07dc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9, sl} + 2068: e2870030 add r0, r7, #48 ; 0x30 + 206c: e1a01003 mov r1, r3 + 2070: ebf60555 bl 0xffd835cc + 2074: 080c07de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, sl} + 2078: ebf607c0 bl 0xffd83f80 + 207c: 080c07de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, sl} + 2080: e287003c add r0, r7, #60 ; 0x3c + 2084: e1a01003 mov r1, r3 + 2088: ebf6054f bl 0xffd835cc + 208c: 080c07e0 stmeqda ip, {r5, r6, r7, r8, r9, sl} + 2090: ebf607ba bl 0xffd83f80 + 2094: 080c07e0 stmeqda ip, {r5, r6, r7, r8, r9, sl} + 2098: e3a00f09 mov r0, #36 ; 0x24 + 209c: e3800b02 orr r0, r0, #2048 ; 0x800 + 20a0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 20a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20a8: ebf6061a bl 0xffd83918 + 20ac: 080c07e4 stmeqda ip, {r2, r5, r6, r7, r8, r9, sl} + 20b0: e1a03000 mov r3, r0 + 20b4: ebf607b1 bl 0xffd83f80 + 20b8: 080c07e2 stmeqda ip, {r1, r5, r6, r7, r8, r9, sl} + 20bc: e2870034 add r0, r7, #52 ; 0x34 + 20c0: e1a01003 mov r1, r3 + 20c4: ebf60540 bl 0xffd835cc + 20c8: 080c07e4 stmeqda ip, {r2, r5, r6, r7, r8, r9, sl} + 20cc: ebf607ab bl 0xffd83f80 + 20d0: 080c07e4 stmeqda ip, {r2, r5, r6, r7, r8, r9, sl} + 20d4: e3b03080 movs r3, #128 ; 0x80 + 20d8: ebf607a8 bl 0xffd83f80 + 20dc: 080c07e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl} + 20e0: e1b03583 movs r3, r3, lsl #11 + 20e4: ebf607a5 bl 0xffd83f80 + 20e8: 080c07e8 stmeqda ip, {r3, r5, r6, r7, r8, r9, sl} + 20ec: ebf607a3 bl 0xffd83f80 + 20f0: 080c07ea stmeqda ip, {r1, r3, r5, r6, r7, r8, r9, sl} + 20f4: e3a000ed mov r0, #237 ; 0xed + 20f8: e3800c07 orr r0, r0, #1792 ; 0x700 + 20fc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2100: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2104: e58d0438 str r0, [sp, #1080] + 2108: e28cc041 add ip, ip, #65 ; 0x41 + 210c: e1a00fac mov r0, ip, lsr #31 + 2110: e08ff100 add pc, pc, r0, lsl #2 + 2114: 080c082c stmeqda ip, {r2, r3, r5, fp} + 2118: ebf6038d bl 0xffd82f54 + 211c: ea000001 b 0x2128 + 2120: 080c082c stmeqda ip, {r2, r3, r5, fp} + 2124: 00000000 andeq r0, r0, r0 + 2128: ebf60794 bl 0xffd83f80 + 212c: 080c082c stmeqda ip, {r2, r3, r5, fp} + 2130: e59d9434 ldr r9, [sp, #1076] + 2134: e3c99003 bic r9, r9, #3 ; 0x3 + 2138: e2499010 sub r9, r9, #16 ; 0x10 + 213c: e58d9434 str r9, [sp, #1076] + 2140: e2890000 add r0, r9, #0 ; 0x0 + 2144: e1a01007 mov r1, r7 + 2148: ebf6053f bl 0xffd8364c + 214c: e2890004 add r0, r9, #4 ; 0x4 + 2150: e1a01008 mov r1, r8 + 2154: ebf6053c bl 0xffd8364c + 2158: e2890008 add r0, r9, #8 ; 0x8 + 215c: e59d1418 ldr r1, [sp, #1048] + 2160: ebf60539 bl 0xffd8364c + 2164: e289000c add r0, r9, #12 ; 0xc + 2168: e59d1438 ldr r1, [sp, #1080] + 216c: ebf60536 bl 0xffd8364c + 2170: ebf60782 bl 0xffd83f80 + 2174: 080c082e stmeqda ip, {r1, r2, r3, r5, fp} + 2178: e1a01003 mov r1, r3 + 217c: e2935000 adds r5, r3, #0 ; 0x0 + 2180: ebf6077e bl 0xffd83f80 + 2184: 080c0830 stmeqda ip, {r4, r5, fp} + 2188: e3a00f2b mov r0, #172 ; 0xac + 218c: e3800b02 orr r0, r0, #2048 ; 0x800 + 2190: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2194: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2198: ebf605de bl 0xffd83918 + 219c: 080c0834 stmeqda ip, {r2, r4, r5, fp} + 21a0: e1a03000 mov r3, r0 + 21a4: ebf60775 bl 0xffd83f80 + 21a8: 080c0832 stmeqda ip, {r1, r4, r5, fp} + 21ac: e2830000 add r0, r3, #0 ; 0x0 + 21b0: ebf605d8 bl 0xffd83918 + 21b4: 080c0836 stmeqda ip, {r1, r2, r4, r5, fp} + 21b8: e1a07000 mov r7, r0 + 21bc: ebf6076f bl 0xffd83f80 + 21c0: 080c0834 stmeqda ip, {r2, r4, r5, fp} + 21c4: e3b030f0 movs r3, #240 ; 0xf0 + 21c8: ebf6076c bl 0xffd83f80 + 21cc: 080c0836 stmeqda ip, {r1, r2, r4, r5, fp} + 21d0: e1b03603 movs r3, r3, lsl #12 + 21d4: ebf60769 bl 0xffd83f80 + 21d8: 080c0838 stmeqda ip, {r3, r4, r5, fp} + 21dc: e1a01003 mov r1, r3 + 21e0: e0133005 ands r3, r3, r5 + 21e4: ebf60765 bl 0xffd83f80 + 21e8: 080c083a stmeqda ip, {r1, r3, r4, r5, fp} + 21ec: e1b05823 movs r5, r3, lsr #16 + 21f0: ebf60762 bl 0xffd83f80 + 21f4: 080c083c stmeqda ip, {r2, r3, r4, r5, fp} + 21f8: e3b00000 movs r0, #0 ; 0x0 + 21fc: e58d0418 str r0, [sp, #1048] + 2200: ebf6075e bl 0xffd83f80 + 2204: 080c083e stmeqda ip, {r1, r2, r3, r4, r5, fp} + 2208: e2870008 add r0, r7, #8 ; 0x8 + 220c: e1a01005 mov r1, r5 + 2210: ebf604ae bl 0xffd834d0 + 2214: 080c0840 stmeqda ip, {r6, fp} + 2218: ebf60758 bl 0xffd83f80 + 221c: 080c0840 stmeqda ip, {r6, fp} + 2220: e3a00e8b mov r0, #2224 ; 0x8b0 + 2224: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2228: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 222c: ebf605b9 bl 0xffd83918 + 2230: 080c0844 stmeqda ip, {r2, r6, fp} + 2234: e1a04000 mov r4, r0 + 2238: ebf60750 bl 0xffd83f80 + 223c: 080c0842 stmeqda ip, {r1, r6, fp} + 2240: e1a01005 mov r1, r5 + 2244: e2553001 subs r3, r5, #1 ; 0x1 + 2248: ebf6074c bl 0xffd83f80 + 224c: 080c0844 stmeqda ip, {r2, r6, fp} + 2250: e1b03083 movs r3, r3, lsl #1 + 2254: ebf60749 bl 0xffd83f80 + 2258: 080c0846 stmeqda ip, {r1, r2, r6, fp} + 225c: e1a01003 mov r1, r3 + 2260: e0933004 adds r3, r3, r4 + 2264: ebf60745 bl 0xffd83f80 + 2268: 080c0848 stmeqda ip, {r3, r6, fp} + 226c: e2830000 add r0, r3, #0 ; 0x0 + 2270: ebf6057c bl 0xffd83868 + 2274: 080c084c stmeqda ip, {r2, r3, r6, fp} + 2278: e1a08000 mov r8, r0 + 227c: ebf6073f bl 0xffd83f80 + 2280: 080c084a stmeqda ip, {r1, r3, r6, fp} + 2284: e2870010 add r0, r7, #16 ; 0x10 + 2288: e1a01008 mov r1, r8 + 228c: ebf604ce bl 0xffd835cc + 2290: 080c084c stmeqda ip, {r2, r3, r6, fp} + 2294: ebf60739 bl 0xffd83f80 + 2298: 080c084c stmeqda ip, {r2, r3, r6, fp} + 229c: e3b030c6 movs r3, #198 ; 0xc6 + 22a0: ebf60736 bl 0xffd83f80 + 22a4: 080c084e stmeqda ip, {r1, r2, r3, r6, fp} + 22a8: e1b03183 movs r3, r3, lsl #3 + 22ac: ebf60733 bl 0xffd83f80 + 22b0: 080c0850 stmeqda ip, {r4, r6, fp} + 22b4: e1a01008 mov r1, r8 + 22b8: e2984000 adds r4, r8, #0 ; 0x0 + 22bc: ebf6072f bl 0xffd83f80 + 22c0: 080c0852 stmeqda ip, {r1, r4, r6, fp} + 22c4: ebf6072d bl 0xffd83f80 + 22c8: 080c0854 stmeqda ip, {r2, r4, r6, fp} + 22cc: e3a00057 mov r0, #87 ; 0x57 + 22d0: e3800b02 orr r0, r0, #2048 ; 0x800 + 22d4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 22d8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22dc: e58d0438 str r0, [sp, #1080] + 22e0: e28cc04c add ip, ip, #76 ; 0x4c + 22e4: e1a00fac mov r0, ip, lsr #31 + 22e8: e08ff100 add pc, pc, r0, lsl #2 + 22ec: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 22f0: ebf60317 bl 0xffd82f54 + 22f4: ea000001 b 0x2300 + 22f8: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 22fc: 00000000 andeq r0, r0, r0 + 2300: ebf6071e bl 0xffd83f80 + 2304: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 2308: e3540000 cmp r4, #0 ; 0x0 + 230c: ebf6071b bl 0xffd83f80 + 2310: 080c364e stmeqda ip, {r1, r2, r3, r6, r9, sl, ip, sp} + 2314: e28cc006 add ip, ip, #6 ; 0x6 + 2318: 1a000004 bne 0x2330 + 231c: e1a00fac mov r0, ip, lsr #31 + 2320: e08ff100 add pc, pc, r0, lsl #2 + 2324: 080c36d4 stmeqda ip, {r2, r4, r6, r7, r9, sl, ip, sp} + 2328: ebf60309 bl 0xffd82f54 + 232c: ea000152 b 0x287c + 2330: ebf60712 bl 0xffd83f80 + 2334: 080c3650 stmeqda ip, {r4, r6, r9, sl, ip, sp} + 2338: e59d9434 ldr r9, [sp, #1076] + 233c: e3c99003 bic r9, r9, #3 ; 0x3 + 2340: e2499004 sub r9, r9, #4 ; 0x4 + 2344: e58d9434 str r9, [sp, #1076] + 2348: e2890000 add r0, r9, #0 ; 0x0 + 234c: e1a01007 mov r1, r7 + 2350: ebf6049d bl 0xffd835cc + 2354: 080c3652 stmeqda ip, {r1, r4, r6, r9, sl, ip, sp} + 2358: ebf60708 bl 0xffd83f80 + 235c: 080c3652 stmeqda ip, {r1, r4, r6, r9, sl, ip, sp} + 2360: e1a01003 mov r1, r3 + 2364: e2937000 adds r7, r3, #0 ; 0x0 + 2368: ebf60704 bl 0xffd83f80 + 236c: 080c3654 stmeqda ip, {r2, r4, r6, r9, sl, ip, sp} + 2370: e1a01007 mov r1, r7 + 2374: e0377004 eors r7, r7, r4 + 2378: ebf60700 bl 0xffd83f80 + 237c: 080c3656 stmeqda ip, {r1, r2, r4, r6, r9, sl, ip, sp} + 2380: e1a00007 mov r0, r7 + 2384: e58d0430 str r0, [sp, #1072] + 2388: ebf606fc bl 0xffd83f80 + 238c: 080c3658 stmeqda ip, {r3, r4, r6, r9, sl, ip, sp} + 2390: e3b06001 movs r6, #1 ; 0x1 + 2394: ebf606f9 bl 0xffd83f80 + 2398: 080c365a stmeqda ip, {r1, r3, r4, r6, r9, sl, ip, sp} + 239c: e3b05000 movs r5, #0 ; 0x0 + 23a0: ebf606f6 bl 0xffd83f80 + 23a4: 080c365c stmeqda ip, {r2, r3, r4, r6, r9, sl, ip, sp} + 23a8: e3540000 cmp r4, #0 ; 0x0 + 23ac: ebf606f3 bl 0xffd83f80 + 23b0: 080c365e stmeqda ip, {r1, r2, r3, r4, r6, r9, sl, ip, sp} + 23b4: e28cc019 add ip, ip, #25 ; 0x19 + 23b8: 4a000004 bmi 0x23d0 + 23bc: e1a00fac mov r0, ip, lsr #31 + 23c0: e08ff100 add pc, pc, r0, lsl #2 + 23c4: 080c3662 stmeqda ip, {r1, r5, r6, r9, sl, ip, sp} + 23c8: ebf602e1 bl 0xffd82f54 + 23cc: ea000004 b 0x23e4 + 23d0: ebf606ea bl 0xffd83f80 + 23d4: 080c3660 stmeqda ip, {r5, r6, r9, sl, ip, sp} + 23d8: e3a01000 mov r1, #0 ; 0x0 + 23dc: e0514004 subs r4, r1, r4 + 23e0: e28cc003 add ip, ip, #3 ; 0x3 + 23e4: ebf606e5 bl 0xffd83f80 + 23e8: 080c3662 stmeqda ip, {r1, r5, r6, r9, sl, ip, sp} + 23ec: e3530000 cmp r3, #0 ; 0x0 + 23f0: ebf606e2 bl 0xffd83f80 + 23f4: 080c3664 stmeqda ip, {r2, r5, r6, r9, sl, ip, sp} + 23f8: e28cc006 add ip, ip, #6 ; 0x6 + 23fc: 4a000004 bmi 0x2414 + 2400: e1a00fac mov r0, ip, lsr #31 + 2404: e08ff100 add pc, pc, r0, lsl #2 + 2408: 080c3668 stmeqda ip, {r3, r5, r6, r9, sl, ip, sp} + 240c: ebf602d0 bl 0xffd82f54 + 2410: ea000004 b 0x2428 + 2414: ebf606d9 bl 0xffd83f80 + 2418: 080c3666 stmeqda ip, {r1, r2, r5, r6, r9, sl, ip, sp} + 241c: e3a01000 mov r1, #0 ; 0x0 + 2420: e0513003 subs r3, r1, r3 + 2424: e28cc003 add ip, ip, #3 ; 0x3 + 2428: ebf606d4 bl 0xffd83f80 + 242c: 080c3668 stmeqda ip, {r3, r5, r6, r9, sl, ip, sp} + 2430: e1530004 cmp r3, r4 + 2434: ebf606d1 bl 0xffd83f80 + 2438: 080c366a stmeqda ip, {r1, r3, r5, r6, r9, sl, ip, sp} + 243c: e28cc006 add ip, ip, #6 ; 0x6 + 2440: 2a000004 bcs 0x2458 + 2444: e1a00fac mov r0, ip, lsr #31 + 2448: e08ff100 add pc, pc, r0, lsl #2 + 244c: 080c36c6 stmeqda ip, {r1, r2, r6, r7, r9, sl, ip, sp} + 2450: ebf602bf bl 0xffd82f54 + 2454: ea0000df b 0x27d8 + 2458: ebf606c8 bl 0xffd83f80 + 245c: 080c366c stmeqda ip, {r2, r3, r5, r6, r9, sl, ip, sp} + 2460: e3b07001 movs r7, #1 ; 0x1 + 2464: ebf606c5 bl 0xffd83f80 + 2468: 080c366e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl, ip, sp} + 246c: e1b07e07 movs r7, r7, lsl #28 + 2470: e28cc006 add ip, ip, #6 ; 0x6 + 2474: ebf606c1 bl 0xffd83f80 + 2478: 080c3670 stmeqda ip, {r4, r5, r6, r9, sl, ip, sp} + 247c: e1540007 cmp r4, r7 + 2480: ebf606be bl 0xffd83f80 + 2484: 080c3672 stmeqda ip, {r1, r4, r5, r6, r9, sl, ip, sp} + 2488: e28cc006 add ip, ip, #6 ; 0x6 + 248c: 3a000004 bcc 0x24a4 + 2490: e1a00fac mov r0, ip, lsr #31 + 2494: e08ff100 add pc, pc, r0, lsl #2 + 2498: 080c367e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl, ip, sp} + 249c: ebf602ac bl 0xffd82f54 + 24a0: ea000019 b 0x250c + 24a4: ebf606b5 bl 0xffd83f80 + 24a8: 080c3674 stmeqda ip, {r2, r4, r5, r6, r9, sl, ip, sp} + 24ac: e1540003 cmp r4, r3 + 24b0: ebf606b2 bl 0xffd83f80 + 24b4: 080c3676 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl, ip, sp} + 24b8: e28cc006 add ip, ip, #6 ; 0x6 + 24bc: 3a000004 bcc 0x24d4 + 24c0: e1a00fac mov r0, ip, lsr #31 + 24c4: e08ff100 add pc, pc, r0, lsl #2 + 24c8: 080c367e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl, ip, sp} + 24cc: ebf602a0 bl 0xffd82f54 + 24d0: ea00000d b 0x250c + 24d4: ebf606a9 bl 0xffd83f80 + 24d8: 080c3678 stmeqda ip, {r3, r4, r5, r6, r9, sl, ip, sp} + 24dc: e1b04204 movs r4, r4, lsl #4 + 24e0: ebf606a6 bl 0xffd83f80 + 24e4: 080c367a stmeqda ip, {r1, r3, r4, r5, r6, r9, sl, ip, sp} + 24e8: e1b06206 movs r6, r6, lsl #4 + 24ec: ebf606a3 bl 0xffd83f80 + 24f0: 080c367c stmeqda ip, {r2, r3, r4, r5, r6, r9, sl, ip, sp} + 24f4: e28cc009 add ip, ip, #9 ; 0x9 + 24f8: e1a00fac mov r0, ip, lsr #31 + 24fc: e08ff100 add pc, pc, r0, lsl #2 + 2500: 080c3670 stmeqda ip, {r4, r5, r6, r9, sl, ip, sp} + 2504: ebf60292 bl 0xffd82f54 + 2508: eaffffd9 b 0x2474 + 250c: ebf6069b bl 0xffd83f80 + 2510: 080c367e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl, ip, sp} + 2514: e1b07187 movs r7, r7, lsl #3 + 2518: e28cc003 add ip, ip, #3 ; 0x3 + 251c: ebf60697 bl 0xffd83f80 + 2520: 080c3680 stmeqda ip, {r7, r9, sl, ip, sp} + 2524: e1540007 cmp r4, r7 + 2528: ebf60694 bl 0xffd83f80 + 252c: 080c3682 stmeqda ip, {r1, r7, r9, sl, ip, sp} + 2530: e28cc006 add ip, ip, #6 ; 0x6 + 2534: 3a000004 bcc 0x254c + 2538: e1a00fac mov r0, ip, lsr #31 + 253c: e08ff100 add pc, pc, r0, lsl #2 + 2540: 080c368e stmeqda ip, {r1, r2, r3, r7, r9, sl, ip, sp} + 2544: ebf60282 bl 0xffd82f54 + 2548: ea000019 b 0x25b4 + 254c: ebf6068b bl 0xffd83f80 + 2550: 080c3684 stmeqda ip, {r2, r7, r9, sl, ip, sp} + 2554: e1540003 cmp r4, r3 + 2558: ebf60688 bl 0xffd83f80 + 255c: 080c3686 stmeqda ip, {r1, r2, r7, r9, sl, ip, sp} + 2560: e28cc006 add ip, ip, #6 ; 0x6 + 2564: 3a000004 bcc 0x257c + 2568: e1a00fac mov r0, ip, lsr #31 + 256c: e08ff100 add pc, pc, r0, lsl #2 + 2570: 080c368e stmeqda ip, {r1, r2, r3, r7, r9, sl, ip, sp} + 2574: ebf60276 bl 0xffd82f54 + 2578: ea00000d b 0x25b4 + 257c: ebf6067f bl 0xffd83f80 + 2580: 080c3688 stmeqda ip, {r3, r7, r9, sl, ip, sp} + 2584: e1b04084 movs r4, r4, lsl #1 + 2588: ebf6067c bl 0xffd83f80 + 258c: 080c368a stmeqda ip, {r1, r3, r7, r9, sl, ip, sp} + 2590: e1b06086 movs r6, r6, lsl #1 + 2594: ebf60679 bl 0xffd83f80 + 2598: 080c368c stmeqda ip, {r2, r3, r7, r9, sl, ip, sp} + 259c: e28cc009 add ip, ip, #9 ; 0x9 + 25a0: e1a00fac mov r0, ip, lsr #31 + 25a4: e08ff100 add pc, pc, r0, lsl #2 + 25a8: 080c3680 stmeqda ip, {r7, r9, sl, ip, sp} + 25ac: ebf60268 bl 0xffd82f54 + 25b0: eaffffd9 b 0x251c + 25b4: ebf60671 bl 0xffd83f80 + 25b8: 080c368e stmeqda ip, {r1, r2, r3, r7, r9, sl, ip, sp} + 25bc: e1530004 cmp r3, r4 + 25c0: ebf6066e bl 0xffd83f80 + 25c4: 080c3690 stmeqda ip, {r4, r7, r9, sl, ip, sp} + 25c8: e28cc006 add ip, ip, #6 ; 0x6 + 25cc: 2a000004 bcs 0x25e4 + 25d0: e1a00fac mov r0, ip, lsr #31 + 25d4: e08ff100 add pc, pc, r0, lsl #2 + 25d8: 080c3696 stmeqda ip, {r1, r2, r4, r7, r9, sl, ip, sp} + 25dc: ebf6025c bl 0xffd82f54 + 25e0: ea000008 b 0x2608 + 25e4: ebf60665 bl 0xffd83f80 + 25e8: 080c3692 stmeqda ip, {r1, r4, r7, r9, sl, ip, sp} + 25ec: e1a01003 mov r1, r3 + 25f0: e0533004 subs r3, r3, r4 + 25f4: ebf60661 bl 0xffd83f80 + 25f8: 080c3694 stmeqda ip, {r2, r4, r7, r9, sl, ip, sp} + 25fc: e1a01005 mov r1, r5 + 2600: e1955006 orrs r5, r5, r6 + 2604: e28cc006 add ip, ip, #6 ; 0x6 + 2608: ebf6065c bl 0xffd83f80 + 260c: 080c3696 stmeqda ip, {r1, r2, r4, r7, r9, sl, ip, sp} + 2610: e1b070a4 movs r7, r4, lsr #1 + 2614: ebf60659 bl 0xffd83f80 + 2618: 080c3698 stmeqda ip, {r3, r4, r7, r9, sl, ip, sp} + 261c: e1530007 cmp r3, r7 + 2620: ebf60656 bl 0xffd83f80 + 2624: 080c369a stmeqda ip, {r1, r3, r4, r7, r9, sl, ip, sp} + 2628: e28cc009 add ip, ip, #9 ; 0x9 + 262c: 2a000004 bcs 0x2644 + 2630: e1a00fac mov r0, ip, lsr #31 + 2634: e08ff100 add pc, pc, r0, lsl #2 + 2638: 080c36a2 stmeqda ip, {r1, r5, r7, r9, sl, ip, sp} + 263c: ebf60244 bl 0xffd82f54 + 2640: ea00000b b 0x2674 + 2644: ebf6064d bl 0xffd83f80 + 2648: 080c369c stmeqda ip, {r2, r3, r4, r7, r9, sl, ip, sp} + 264c: e1a01003 mov r1, r3 + 2650: e0533007 subs r3, r3, r7 + 2654: ebf60649 bl 0xffd83f80 + 2658: 080c369e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, ip, sp} + 265c: e1b070a6 movs r7, r6, lsr #1 + 2660: ebf60646 bl 0xffd83f80 + 2664: 080c36a0 stmeqda ip, {r5, r7, r9, sl, ip, sp} + 2668: e1a01005 mov r1, r5 + 266c: e1955007 orrs r5, r5, r7 + 2670: e28cc009 add ip, ip, #9 ; 0x9 + 2674: ebf60641 bl 0xffd83f80 + 2678: 080c36a2 stmeqda ip, {r1, r5, r7, r9, sl, ip, sp} + 267c: e1b07124 movs r7, r4, lsr #2 + 2680: ebf6063e bl 0xffd83f80 + 2684: 080c36a4 stmeqda ip, {r2, r5, r7, r9, sl, ip, sp} + 2688: e1530007 cmp r3, r7 + 268c: ebf6063b bl 0xffd83f80 + 2690: 080c36a6 stmeqda ip, {r1, r2, r5, r7, r9, sl, ip, sp} + 2694: e28cc009 add ip, ip, #9 ; 0x9 + 2698: 2a000004 bcs 0x26b0 + 269c: e1a00fac mov r0, ip, lsr #31 + 26a0: e08ff100 add pc, pc, r0, lsl #2 + 26a4: 080c36ae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl, ip, sp} + 26a8: ebf60229 bl 0xffd82f54 + 26ac: ea00000b b 0x26e0 + 26b0: ebf60632 bl 0xffd83f80 + 26b4: 080c36a8 stmeqda ip, {r3, r5, r7, r9, sl, ip, sp} + 26b8: e1a01003 mov r1, r3 + 26bc: e0533007 subs r3, r3, r7 + 26c0: ebf6062e bl 0xffd83f80 + 26c4: 080c36aa stmeqda ip, {r1, r3, r5, r7, r9, sl, ip, sp} + 26c8: e1b07126 movs r7, r6, lsr #2 + 26cc: ebf6062b bl 0xffd83f80 + 26d0: 080c36ac stmeqda ip, {r2, r3, r5, r7, r9, sl, ip, sp} + 26d4: e1a01005 mov r1, r5 + 26d8: e1955007 orrs r5, r5, r7 + 26dc: e28cc009 add ip, ip, #9 ; 0x9 + 26e0: ebf60626 bl 0xffd83f80 + 26e4: 080c36ae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl, ip, sp} + 26e8: e1b071a4 movs r7, r4, lsr #3 + 26ec: ebf60623 bl 0xffd83f80 + 26f0: 080c36b0 stmeqda ip, {r4, r5, r7, r9, sl, ip, sp} + 26f4: e1530007 cmp r3, r7 + 26f8: ebf60620 bl 0xffd83f80 + 26fc: 080c36b2 stmeqda ip, {r1, r4, r5, r7, r9, sl, ip, sp} + 2700: e28cc009 add ip, ip, #9 ; 0x9 + 2704: 2a000004 bcs 0x271c + 2708: e1a00fac mov r0, ip, lsr #31 + 270c: e08ff100 add pc, pc, r0, lsl #2 + 2710: 080c36ba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, ip, sp} + 2714: ebf6020e bl 0xffd82f54 + 2718: ea00000b b 0x274c + 271c: ebf60617 bl 0xffd83f80 + 2720: 080c36b4 stmeqda ip, {r2, r4, r5, r7, r9, sl, ip, sp} + 2724: e1a01003 mov r1, r3 + 2728: e0533007 subs r3, r3, r7 + 272c: ebf60613 bl 0xffd83f80 + 2730: 080c36b6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, ip, sp} + 2734: e1b071a6 movs r7, r6, lsr #3 + 2738: ebf60610 bl 0xffd83f80 + 273c: 080c36b8 stmeqda ip, {r3, r4, r5, r7, r9, sl, ip, sp} + 2740: e1a01005 mov r1, r5 + 2744: e1955007 orrs r5, r5, r7 + 2748: e28cc009 add ip, ip, #9 ; 0x9 + 274c: ebf6060b bl 0xffd83f80 + 2750: 080c36ba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, ip, sp} + 2754: e3530000 cmp r3, #0 ; 0x0 + 2758: ebf60608 bl 0xffd83f80 + 275c: 080c36bc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, ip, sp} + 2760: e28cc006 add ip, ip, #6 ; 0x6 + 2764: 1a000004 bne 0x277c + 2768: e1a00fac mov r0, ip, lsr #31 + 276c: e08ff100 add pc, pc, r0, lsl #2 + 2770: 080c36c6 stmeqda ip, {r1, r2, r6, r7, r9, sl, ip, sp} + 2774: ebf601f6 bl 0xffd82f54 + 2778: ea000016 b 0x27d8 + 277c: ebf605ff bl 0xffd83f80 + 2780: 080c36be stmeqda ip, {r1, r2, r3, r4, r5, r7, r9, sl, ip, sp} + 2784: e1b06226 movs r6, r6, lsr #4 + 2788: ebf605fc bl 0xffd83f80 + 278c: 080c36c0 stmeqda ip, {r6, r7, r9, sl, ip, sp} + 2790: e28cc006 add ip, ip, #6 ; 0x6 + 2794: 1a000004 bne 0x27ac + 2798: e1a00fac mov r0, ip, lsr #31 + 279c: e08ff100 add pc, pc, r0, lsl #2 + 27a0: 080c36c6 stmeqda ip, {r1, r2, r6, r7, r9, sl, ip, sp} + 27a4: ebf601ea bl 0xffd82f54 + 27a8: ea00000a b 0x27d8 + 27ac: ebf605f3 bl 0xffd83f80 + 27b0: 080c36c2 stmeqda ip, {r1, r6, r7, r9, sl, ip, sp} + 27b4: e1b04224 movs r4, r4, lsr #4 + 27b8: ebf605f0 bl 0xffd83f80 + 27bc: 080c36c4 stmeqda ip, {r2, r6, r7, r9, sl, ip, sp} + 27c0: e28cc006 add ip, ip, #6 ; 0x6 + 27c4: e1a00fac mov r0, ip, lsr #31 + 27c8: e08ff100 add pc, pc, r0, lsl #2 + 27cc: 080c368e stmeqda ip, {r1, r2, r3, r7, r9, sl, ip, sp} + 27d0: ebf601df bl 0xffd82f54 + 27d4: eaffff76 b 0x25b4 + 27d8: ebf605e8 bl 0xffd83f80 + 27dc: 080c36c6 stmeqda ip, {r1, r2, r6, r7, r9, sl, ip, sp} + 27e0: e1a01005 mov r1, r5 + 27e4: e2953000 adds r3, r5, #0 ; 0x0 + 27e8: ebf605e4 bl 0xffd83f80 + 27ec: 080c36c8 stmeqda ip, {r3, r6, r7, r9, sl, ip, sp} + 27f0: e59d1430 ldr r1, [sp, #1072] + 27f4: e1a07001 mov r7, r1 + 27f8: ebf605e0 bl 0xffd83f80 + 27fc: 080c36ca stmeqda ip, {r1, r3, r6, r7, r9, sl, ip, sp} + 2800: e3570000 cmp r7, #0 ; 0x0 + 2804: ebf605dd bl 0xffd83f80 + 2808: 080c36cc stmeqda ip, {r2, r3, r6, r7, r9, sl, ip, sp} + 280c: e28cc00c add ip, ip, #12 ; 0xc + 2810: 4a000004 bmi 0x2828 + 2814: e1a00fac mov r0, ip, lsr #31 + 2818: e08ff100 add pc, pc, r0, lsl #2 + 281c: 080c36d0 stmeqda ip, {r4, r6, r7, r9, sl, ip, sp} + 2820: ebf601cb bl 0xffd82f54 + 2824: ea000004 b 0x283c + 2828: ebf605d4 bl 0xffd83f80 + 282c: 080c36ce stmeqda ip, {r1, r2, r3, r6, r7, r9, sl, ip, sp} + 2830: e3a01000 mov r1, #0 ; 0x0 + 2834: e0513003 subs r3, r1, r3 + 2838: e28cc003 add ip, ip, #3 ; 0x3 + 283c: ebf605cf bl 0xffd83f80 + 2840: 080c36d0 stmeqda ip, {r4, r6, r7, r9, sl, ip, sp} + 2844: e59d9434 ldr r9, [sp, #1076] + 2848: e3c99003 bic r9, r9, #3 ; 0x3 + 284c: e2890004 add r0, r9, #4 ; 0x4 + 2850: e58d0434 str r0, [sp, #1076] + 2854: e2890000 add r0, r9, #0 ; 0x0 + 2858: ebf6042e bl 0xffd83918 + 285c: 080c36d4 stmeqda ip, {r2, r4, r6, r7, r9, sl, ip, sp} + 2860: e1a07000 mov r7, r0 + 2864: ebf605c5 bl 0xffd83f80 + 2868: 080c36d2 stmeqda ip, {r1, r4, r6, r7, r9, sl, ip, sp} + 286c: e59d1438 ldr r1, [sp, #1080] + 2870: e1a00001 mov r0, r1 + 2874: e28cc007 add ip, ip, #7 ; 0x7 + 2878: eaf601f1 b 0xffd83044 + 287c: ebf605bf bl 0xffd83f80 + 2880: 080c36d4 stmeqda ip, {r2, r4, r6, r7, r9, sl, ip, sp} + 2884: e59d9434 ldr r9, [sp, #1076] + 2888: e3c99003 bic r9, r9, #3 ; 0x3 + 288c: e2499004 sub r9, r9, #4 ; 0x4 + 2890: e58d9434 str r9, [sp, #1076] + 2894: e2890000 add r0, r9, #0 ; 0x0 + 2898: e59d1438 ldr r1, [sp, #1080] + 289c: ebf6036a bl 0xffd8364c + 28a0: ebf605b6 bl 0xffd83f80 + 28a4: 080c36d6 stmeqda ip, {r1, r2, r4, r6, r7, r9, sl, ip, sp} + 28a8: ebf605b4 bl 0xffd83f80 + 28ac: 080c36d8 stmeqda ip, {r3, r4, r6, r7, r9, sl, ip, sp} + 28b0: e3a000db mov r0, #219 ; 0xdb + 28b4: e3800c36 orr r0, r0, #13824 ; 0x3600 + 28b8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 28bc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 28c0: e58d0438 str r0, [sp, #1080] + 28c4: e28cc009 add ip, ip, #9 ; 0x9 + 28c8: e1a00fac mov r0, ip, lsr #31 + 28cc: e08ff100 add pc, pc, r0, lsl #2 + 28d0: 080c36e0 stmeqda ip, {r5, r6, r7, r9, sl, ip, sp} + 28d4: ebf6019e bl 0xffd82f54 + 28d8: ea000001 b 0x28e4 + 28dc: 080c36e0 stmeqda ip, {r5, r6, r7, r9, sl, ip, sp} + 28e0: 00000000 andeq r0, r0, r0 + 28e4: ebf605a5 bl 0xffd83f80 + 28e8: 080c36e0 stmeqda ip, {r5, r6, r7, r9, sl, ip, sp} + 28ec: e59d1438 ldr r1, [sp, #1080] + 28f0: e1a00001 mov r0, r1 + 28f4: e28cc003 add ip, ip, #3 ; 0x3 + 28f8: eaf601d1 b 0xffd83044 + 28fc: 080c0856 stmeqda ip, {r1, r2, r4, r6, fp} + 2900: 00000000 andeq r0, r0, r0 + 2904: ebf6059d bl 0xffd83f80 + 2908: 080c0856 stmeqda ip, {r1, r2, r4, r6, fp} + 290c: e287000b add r0, r7, #11 ; 0xb + 2910: e1a01003 mov r1, r3 + 2914: ebf602ed bl 0xffd834d0 + 2918: 080c0858 stmeqda ip, {r3, r4, r6, fp} + 291c: ebf60597 bl 0xffd83f80 + 2920: 080c0858 stmeqda ip, {r3, r4, r6, fp} + 2924: e3a00f2d mov r0, #180 ; 0xb4 + 2928: e3800b02 orr r0, r0, #2048 ; 0x800 + 292c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2930: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2934: ebf603f7 bl 0xffd83918 + 2938: 080c085c stmeqda ip, {r2, r3, r4, r6, fp} + 293c: e1a03000 mov r3, r0 + 2940: ebf6058e bl 0xffd83f80 + 2944: 080c085a stmeqda ip, {r1, r3, r4, r6, fp} + 2948: e1a01003 mov r1, r3 + 294c: e0130893 muls r3, r3, r8 + 2950: ebf6058a bl 0xffd83f80 + 2954: 080c085c stmeqda ip, {r2, r3, r4, r6, fp} + 2958: e3a00f2e mov r0, #184 ; 0xb8 + 295c: e3800b02 orr r0, r0, #2048 ; 0x800 + 2960: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2964: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2968: ebf603ea bl 0xffd83918 + 296c: 080c0860 stmeqda ip, {r5, r6, fp} + 2970: e1a04000 mov r4, r0 + 2974: ebf60581 bl 0xffd83f80 + 2978: 080c085e stmeqda ip, {r1, r2, r3, r4, r6, fp} + 297c: e1a01003 mov r1, r3 + 2980: e0933004 adds r3, r3, r4 + 2984: ebf6057d bl 0xffd83f80 + 2988: 080c0860 stmeqda ip, {r5, r6, fp} + 298c: e3a00f2f mov r0, #188 ; 0xbc + 2990: e3800b02 orr r0, r0, #2048 ; 0x800 + 2994: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2998: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 299c: ebf603dd bl 0xffd83918 + 29a0: 080c0864 stmeqda ip, {r2, r5, r6, fp} + 29a4: e1a04000 mov r4, r0 + 29a8: ebf60574 bl 0xffd83f80 + 29ac: 080c0862 stmeqda ip, {r1, r5, r6, fp} + 29b0: ebf60572 bl 0xffd83f80 + 29b4: 080c0864 stmeqda ip, {r2, r5, r6, fp} + 29b8: e3a00067 mov r0, #103 ; 0x67 + 29bc: e3800b02 orr r0, r0, #2048 ; 0x800 + 29c0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 29c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 29c8: e58d0438 str r0, [sp, #1080] + 29cc: e28cc01f add ip, ip, #31 ; 0x1f + 29d0: e1a00fac mov r0, ip, lsr #31 + 29d4: e08ff100 add pc, pc, r0, lsl #2 + 29d8: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 29dc: ebf6015c bl 0xffd82f54 + 29e0: eafffe46 b 0x2300 + 29e4: 080c0866 stmeqda ip, {r1, r2, r5, r6, fp} + 29e8: 00000000 andeq r0, r0, r0 + 29ec: ebf60563 bl 0xffd83f80 + 29f0: 080c0866 stmeqda ip, {r1, r2, r5, r6, fp} + 29f4: e1a01003 mov r1, r3 + 29f8: e2934000 adds r4, r3, #0 ; 0x0 + 29fc: ebf6055f bl 0xffd83f80 + 2a00: 080c0868 stmeqda ip, {r3, r5, r6, fp} + 2a04: e2870014 add r0, r7, #20 ; 0x14 + 2a08: e1a01004 mov r1, r4 + 2a0c: ebf602ee bl 0xffd835cc + 2a10: 080c086a stmeqda ip, {r1, r3, r5, r6, fp} + 2a14: ebf60559 bl 0xffd83f80 + 2a18: 080c086a stmeqda ip, {r1, r3, r5, r6, fp} + 2a1c: e3b03080 movs r3, #128 ; 0x80 + 2a20: ebf60556 bl 0xffd83f80 + 2a24: 080c086c stmeqda ip, {r2, r3, r5, r6, fp} + 2a28: e1b03883 movs r3, r3, lsl #17 + 2a2c: ebf60553 bl 0xffd83f80 + 2a30: 080c086e stmeqda ip, {r1, r2, r3, r5, r6, fp} + 2a34: ebf60551 bl 0xffd83f80 + 2a38: 080c0870 stmeqda ip, {r4, r5, r6, fp} + 2a3c: e3a00073 mov r0, #115 ; 0x73 + 2a40: e3800b02 orr r0, r0, #2048 ; 0x800 + 2a44: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2a48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2a4c: e58d0438 str r0, [sp, #1080] + 2a50: e28cc013 add ip, ip, #19 ; 0x13 + 2a54: e1a00fac mov r0, ip, lsr #31 + 2a58: e08ff100 add pc, pc, r0, lsl #2 + 2a5c: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 2a60: ebf6013b bl 0xffd82f54 + 2a64: eafffe25 b 0x2300 + 2a68: 080c0872 stmeqda ip, {r1, r4, r5, r6, fp} + 2a6c: 00000000 andeq r0, r0, r0 + 2a70: ebf60542 bl 0xffd83f80 + 2a74: 080c0872 stmeqda ip, {r1, r4, r5, r6, fp} + 2a78: e1a01003 mov r1, r3 + 2a7c: e2933001 adds r3, r3, #1 ; 0x1 + 2a80: ebf6053e bl 0xffd83f80 + 2a84: 080c0874 stmeqda ip, {r2, r4, r5, r6, fp} + 2a88: e1b030c3 movs r3, r3, asr #1 + 2a8c: ebf6053b bl 0xffd83f80 + 2a90: 080c0876 stmeqda ip, {r1, r2, r4, r5, r6, fp} + 2a94: e2870018 add r0, r7, #24 ; 0x18 + 2a98: e1a01003 mov r1, r3 + 2a9c: ebf602ca bl 0xffd835cc + 2aa0: 080c0878 stmeqda ip, {r3, r4, r5, r6, fp} + 2aa4: ebf60535 bl 0xffd83f80 + 2aa8: 080c0878 stmeqda ip, {r3, r4, r5, r6, fp} + 2aac: e3a00d23 mov r0, #2240 ; 0x8c0 + 2ab0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2ab4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2ab8: ebf60396 bl 0xffd83918 + 2abc: 080c087c stmeqda ip, {r2, r3, r4, r5, r6, fp} + 2ac0: e1a03000 mov r3, r0 + 2ac4: ebf6052d bl 0xffd83f80 + 2ac8: 080c087a stmeqda ip, {r1, r3, r4, r5, r6, fp} + 2acc: e2830000 add r0, r3, #0 ; 0x0 + 2ad0: e59d1418 ldr r1, [sp, #1048] + 2ad4: ebf6029c bl 0xffd8354c + 2ad8: 080c087c stmeqda ip, {r2, r3, r4, r5, r6, fp} + 2adc: ebf60527 bl 0xffd83f80 + 2ae0: 080c087c stmeqda ip, {r2, r3, r4, r5, r6, fp} + 2ae4: e3a00f31 mov r0, #196 ; 0xc4 + 2ae8: e3800b02 orr r0, r0, #2048 ; 0x800 + 2aec: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2af0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2af4: ebf60387 bl 0xffd83918 + 2af8: 080c0880 stmeqda ip, {r7, fp} + 2afc: e1a07000 mov r7, r0 + 2b00: ebf6051e bl 0xffd83f80 + 2b04: 080c087e stmeqda ip, {r1, r2, r3, r4, r5, r6, fp} + 2b08: e3a00f32 mov r0, #200 ; 0xc8 + 2b0c: e3800b02 orr r0, r0, #2048 ; 0x800 + 2b10: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2b14: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2b18: ebf6037e bl 0xffd83918 + 2b1c: 080c0882 stmeqda ip, {r1, r7, fp} + 2b20: e1a03000 mov r3, r0 + 2b24: ebf60515 bl 0xffd83f80 + 2b28: 080c0880 stmeqda ip, {r7, fp} + 2b2c: e1a01008 mov r1, r8 + 2b30: e2984000 adds r4, r8, #0 ; 0x0 + 2b34: ebf60511 bl 0xffd83f80 + 2b38: 080c0882 stmeqda ip, {r1, r7, fp} + 2b3c: ebf6050f bl 0xffd83f80 + 2b40: 080c0884 stmeqda ip, {r2, r7, fp} + 2b44: e3a00087 mov r0, #135 ; 0x87 + 2b48: e3800b02 orr r0, r0, #2048 ; 0x800 + 2b4c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2b50: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2b54: e58d0438 str r0, [sp, #1080] + 2b58: e28cc026 add ip, ip, #38 ; 0x26 + 2b5c: e1a00fac mov r0, ip, lsr #31 + 2b60: e08ff100 add pc, pc, r0, lsl #2 + 2b64: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 2b68: ebf600f9 bl 0xffd82f54 + 2b6c: eafffde3 b 0x2300 + 2b70: 080c0886 stmeqda ip, {r1, r2, r7, fp} + 2b74: 00000000 andeq r0, r0, r0 + 2b78: ebf60500 bl 0xffd83f80 + 2b7c: 080c0886 stmeqda ip, {r1, r2, r7, fp} + 2b80: e3a01000 mov r1, #0 ; 0x0 + 2b84: e0513003 subs r3, r1, r3 + 2b88: ebf604fc bl 0xffd83f80 + 2b8c: 080c0888 stmeqda ip, {r3, r7, fp} + 2b90: e2870000 add r0, r7, #0 ; 0x0 + 2b94: e1a01003 mov r1, r3 + 2b98: ebf6026b bl 0xffd8354c + 2b9c: 080c088a stmeqda ip, {r1, r3, r7, fp} + 2ba0: ebf604f6 bl 0xffd83f80 + 2ba4: 080c088a stmeqda ip, {r1, r3, r7, fp} + 2ba8: ebf604f4 bl 0xffd83f80 + 2bac: 080c088c stmeqda ip, {r2, r3, r7, fp} + 2bb0: e3a0008f mov r0, #143 ; 0x8f + 2bb4: e3800b02 orr r0, r0, #2048 ; 0x800 + 2bb8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2bbc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2bc0: e58d0438 str r0, [sp, #1080] + 2bc4: e28cc00d add ip, ip, #13 ; 0xd + 2bc8: e1a00fac mov r0, ip, lsr #31 + 2bcc: e08ff100 add pc, pc, r0, lsl #2 + 2bd0: 080c0a08 stmeqda ip, {r3, r9, fp} + 2bd4: ebf600de bl 0xffd82f54 + 2bd8: ea000001 b 0x2be4 + 2bdc: 080c0a08 stmeqda ip, {r3, r9, fp} + 2be0: 00000000 andeq r0, r0, r0 + 2be4: ebf604e5 bl 0xffd83f80 + 2be8: 080c0a08 stmeqda ip, {r3, r9, fp} + 2bec: e59d9434 ldr r9, [sp, #1076] + 2bf0: e3c99003 bic r9, r9, #3 ; 0x3 + 2bf4: e2499008 sub r9, r9, #8 ; 0x8 + 2bf8: e58d9434 str r9, [sp, #1076] + 2bfc: e2890000 add r0, r9, #0 ; 0x0 + 2c00: e1a01007 mov r1, r7 + 2c04: ebf60290 bl 0xffd8364c + 2c08: e2890004 add r0, r9, #4 ; 0x4 + 2c0c: e59d1438 ldr r1, [sp, #1080] + 2c10: ebf6028d bl 0xffd8364c + 2c14: ebf604d9 bl 0xffd83f80 + 2c18: 080c0a0a stmeqda ip, {r1, r3, r9, fp} + 2c1c: e3a00f8e mov r0, #568 ; 0x238 + 2c20: e3800b02 orr r0, r0, #2048 ; 0x800 + 2c24: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2c28: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2c2c: ebf60339 bl 0xffd83918 + 2c30: 080c0a0e stmeqda ip, {r1, r2, r3, r9, fp} + 2c34: e1a03000 mov r3, r0 + 2c38: ebf604d0 bl 0xffd83f80 + 2c3c: 080c0a0c stmeqda ip, {r2, r3, r9, fp} + 2c40: e2830000 add r0, r3, #0 ; 0x0 + 2c44: ebf60333 bl 0xffd83918 + 2c48: 080c0a10 stmeqda ip, {r4, r9, fp} + 2c4c: e1a05000 mov r5, r0 + 2c50: ebf604ca bl 0xffd83f80 + 2c54: 080c0a0e stmeqda ip, {r1, r2, r3, r9, fp} + 2c58: e2850000 add r0, r5, #0 ; 0x0 + 2c5c: ebf6032d bl 0xffd83918 + 2c60: 080c0a12 stmeqda ip, {r1, r4, r9, fp} + 2c64: e1a06000 mov r6, r0 + 2c68: ebf604c4 bl 0xffd83f80 + 2c6c: 080c0a10 stmeqda ip, {r4, r9, fp} + 2c70: e3a00f8f mov r0, #572 ; 0x23c + 2c74: e3800b02 orr r0, r0, #2048 ; 0x800 + 2c78: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2c7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2c80: ebf60324 bl 0xffd83918 + 2c84: 080c0a14 stmeqda ip, {r2, r4, r9, fp} + 2c88: e1a03000 mov r3, r0 + 2c8c: ebf604bb bl 0xffd83f80 + 2c90: 080c0a12 stmeqda ip, {r1, r4, r9, fp} + 2c94: e1560003 cmp r6, r3 + 2c98: ebf604b8 bl 0xffd83f80 + 2c9c: 080c0a14 stmeqda ip, {r2, r4, r9, fp} + 2ca0: e28cc01e add ip, ip, #30 ; 0x1e + 2ca4: 1a000004 bne 0x2cbc + 2ca8: e1a00fac mov r0, ip, lsr #31 + 2cac: e08ff100 add pc, pc, r0, lsl #2 + 2cb0: 080c0a30 stmeqda ip, {r4, r5, r9, fp} + 2cb4: ebf600a6 bl 0xffd82f54 + 2cb8: ea00003f b 0x2dbc + 2cbc: ebf604af bl 0xffd83f80 + 2cc0: 080c0a16 stmeqda ip, {r1, r2, r4, r9, fp} + 2cc4: e3a00d29 mov r0, #2624 ; 0xa40 + 2cc8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2ccc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2cd0: ebf60310 bl 0xffd83918 + 2cd4: 080c0a1a stmeqda ip, {r1, r3, r4, r9, fp} + 2cd8: e1a03000 mov r3, r0 + 2cdc: ebf604a7 bl 0xffd83f80 + 2ce0: 080c0a18 stmeqda ip, {r3, r4, r9, fp} + 2ce4: e3b070b6 movs r7, #182 ; 0xb6 + 2ce8: ebf604a4 bl 0xffd83f80 + 2cec: 080c0a1a stmeqda ip, {r1, r3, r4, r9, fp} + 2cf0: e1b07407 movs r7, r7, lsl #8 + 2cf4: ebf604a1 bl 0xffd83f80 + 2cf8: 080c0a1c stmeqda ip, {r2, r3, r4, r9, fp} + 2cfc: e1a01007 mov r1, r7 + 2d00: e2974000 adds r4, r7, #0 ; 0x0 + 2d04: ebf6049d bl 0xffd83f80 + 2d08: 080c0a1e stmeqda ip, {r1, r2, r3, r4, r9, fp} + 2d0c: e2830000 add r0, r3, #0 ; 0x0 + 2d10: e1a01004 mov r1, r4 + 2d14: ebf6020c bl 0xffd8354c + 2d18: 080c0a20 stmeqda ip, {r5, r9, fp} + 2d1c: ebf60497 bl 0xffd83f80 + 2d20: 080c0a20 stmeqda ip, {r5, r9, fp} + 2d24: e1a01003 mov r1, r3 + 2d28: e293300c adds r3, r3, #12 ; 0xc + 2d2c: ebf60493 bl 0xffd83f80 + 2d30: 080c0a22 stmeqda ip, {r1, r5, r9, fp} + 2d34: e2830000 add r0, r3, #0 ; 0x0 + 2d38: e1a01004 mov r1, r4 + 2d3c: ebf60202 bl 0xffd8354c + 2d40: 080c0a24 stmeqda ip, {r2, r5, r9, fp} + 2d44: ebf6048d bl 0xffd83f80 + 2d48: 080c0a24 stmeqda ip, {r2, r5, r9, fp} + 2d4c: e2850004 add r0, r5, #4 ; 0x4 + 2d50: ebf60299 bl 0xffd837bc + 2d54: 080c0a28 stmeqda ip, {r3, r5, r9, fp} + 2d58: e1a03000 mov r3, r0 + 2d5c: ebf60487 bl 0xffd83f80 + 2d60: 080c0a26 stmeqda ip, {r1, r2, r5, r9, fp} + 2d64: e3b03000 movs r3, #0 ; 0x0 + 2d68: ebf60484 bl 0xffd83f80 + 2d6c: 080c0a28 stmeqda ip, {r3, r5, r9, fp} + 2d70: e2850004 add r0, r5, #4 ; 0x4 + 2d74: e1a01003 mov r1, r3 + 2d78: ebf601d4 bl 0xffd834d0 + 2d7c: 080c0a2a stmeqda ip, {r1, r3, r5, r9, fp} + 2d80: ebf6047e bl 0xffd83f80 + 2d84: 080c0a2a stmeqda ip, {r1, r3, r5, r9, fp} + 2d88: e1a01006 mov r1, r6 + 2d8c: e2963000 adds r3, r6, #0 ; 0x0 + 2d90: ebf6047a bl 0xffd83f80 + 2d94: 080c0a2c stmeqda ip, {r2, r3, r5, r9, fp} + 2d98: e1a01003 mov r1, r3 + 2d9c: e253300a subs r3, r3, #10 ; 0xa + 2da0: ebf60476 bl 0xffd83f80 + 2da4: 080c0a2e stmeqda ip, {r1, r2, r3, r5, r9, fp} + 2da8: e2850000 add r0, r5, #0 ; 0x0 + 2dac: e1a01003 mov r1, r3 + 2db0: ebf60205 bl 0xffd835cc + 2db4: 080c0a30 stmeqda ip, {r4, r5, r9, fp} + 2db8: e28cc02f add ip, ip, #47 ; 0x2f + 2dbc: ebf6046f bl 0xffd83f80 + 2dc0: 080c0a30 stmeqda ip, {r4, r5, r9, fp} + 2dc4: e59d9434 ldr r9, [sp, #1076] + 2dc8: e3c99003 bic r9, r9, #3 ; 0x3 + 2dcc: e2890004 add r0, r9, #4 ; 0x4 + 2dd0: e58d0434 str r0, [sp, #1076] + 2dd4: e2890000 add r0, r9, #0 ; 0x0 + 2dd8: ebf602ce bl 0xffd83918 + 2ddc: 080c0a34 stmeqda ip, {r2, r4, r5, r9, fp} + 2de0: e1a07000 mov r7, r0 + 2de4: ebf60465 bl 0xffd83f80 + 2de8: 080c0a32 stmeqda ip, {r1, r4, r5, r9, fp} + 2dec: e59d9434 ldr r9, [sp, #1076] + 2df0: e3c99003 bic r9, r9, #3 ; 0x3 + 2df4: e2890004 add r0, r9, #4 ; 0x4 + 2df8: e58d0434 str r0, [sp, #1076] + 2dfc: e2890000 add r0, r9, #0 ; 0x0 + 2e00: ebf602c4 bl 0xffd83918 + 2e04: 080c0a36 stmeqda ip, {r1, r2, r4, r5, r9, fp} + 2e08: e1a03000 mov r3, r0 + 2e0c: ebf6045b bl 0xffd83f80 + 2e10: 080c0a34 stmeqda ip, {r2, r4, r5, r9, fp} + 2e14: e1a00003 mov r0, r3 + 2e18: e28cc00b add ip, ip, #11 ; 0xb + 2e1c: eaf600ab b 0xffd830d0 + 2e20: 080c088e stmeqda ip, {r1, r2, r3, r7, fp} + 2e24: 00000000 andeq r0, r0, r0 + 2e28: ebf60454 bl 0xffd83f80 + 2e2c: 080c088e stmeqda ip, {r1, r2, r3, r7, fp} + 2e30: e3a00f33 mov r0, #204 ; 0xcc + 2e34: e3800b02 orr r0, r0, #2048 ; 0x800 + 2e38: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2e3c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2e40: ebf602b4 bl 0xffd83918 + 2e44: 080c0892 stmeqda ip, {r1, r4, r7, fp} + 2e48: e1a04000 mov r4, r0 + 2e4c: e28cc005 add ip, ip, #5 ; 0x5 + 2e50: ebf6044a bl 0xffd83f80 + 2e54: 080c0890 stmeqda ip, {r4, r7, fp} + 2e58: e2840000 add r0, r4, #0 ; 0x0 + 2e5c: ebf60256 bl 0xffd837bc + 2e60: 080c0894 stmeqda ip, {r2, r4, r7, fp} + 2e64: e1a03000 mov r3, r0 + 2e68: ebf60444 bl 0xffd83f80 + 2e6c: 080c0892 stmeqda ip, {r1, r4, r7, fp} + 2e70: e353009f cmp r3, #159 ; 0x9f + 2e74: ebf60441 bl 0xffd83f80 + 2e78: 080c0894 stmeqda ip, {r2, r4, r7, fp} + 2e7c: e28cc00b add ip, ip, #11 ; 0xb + 2e80: 1a000004 bne 0x2e98 + 2e84: e1a00fac mov r0, ip, lsr #31 + 2e88: e08ff100 add pc, pc, r0, lsl #2 + 2e8c: 080c0890 stmeqda ip, {r4, r7, fp} + 2e90: ebf6002f bl 0xffd82f54 + 2e94: eaffffed b 0x2e50 + 2e98: ebf60438 bl 0xffd83f80 + 2e9c: 080c0896 stmeqda ip, {r1, r2, r4, r7, fp} + 2ea0: e3a00f33 mov r0, #204 ; 0xcc + 2ea4: e3800b02 orr r0, r0, #2048 ; 0x800 + 2ea8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2eac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2eb0: ebf60298 bl 0xffd83918 + 2eb4: 080c089a stmeqda ip, {r1, r3, r4, r7, fp} + 2eb8: e1a04000 mov r4, r0 + 2ebc: e28cc005 add ip, ip, #5 ; 0x5 + 2ec0: ebf6042e bl 0xffd83f80 + 2ec4: 080c0898 stmeqda ip, {r3, r4, r7, fp} + 2ec8: e2840000 add r0, r4, #0 ; 0x0 + 2ecc: ebf6023a bl 0xffd837bc + 2ed0: 080c089c stmeqda ip, {r2, r3, r4, r7, fp} + 2ed4: e1a03000 mov r3, r0 + 2ed8: ebf60428 bl 0xffd83f80 + 2edc: 080c089a stmeqda ip, {r1, r3, r4, r7, fp} + 2ee0: e353009f cmp r3, #159 ; 0x9f + 2ee4: ebf60425 bl 0xffd83f80 + 2ee8: 080c089c stmeqda ip, {r2, r3, r4, r7, fp} + 2eec: e28cc00b add ip, ip, #11 ; 0xb + 2ef0: 0a000004 beq 0x2f08 + 2ef4: e1a00fac mov r0, ip, lsr #31 + 2ef8: e08ff100 add pc, pc, r0, lsl #2 + 2efc: 080c0898 stmeqda ip, {r3, r4, r7, fp} + 2f00: ebf60013 bl 0xffd82f54 + 2f04: eaffffed b 0x2ec0 + 2f08: ebf6041c bl 0xffd83f80 + 2f0c: 080c089e stmeqda ip, {r1, r2, r3, r4, r7, fp} + 2f10: e3a00d23 mov r0, #2240 ; 0x8c0 + 2f14: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2f18: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2f1c: ebf6027d bl 0xffd83918 + 2f20: 080c08a2 stmeqda ip, {r1, r5, r7, fp} + 2f24: e1a04000 mov r4, r0 + 2f28: ebf60414 bl 0xffd83f80 + 2f2c: 080c08a0 stmeqda ip, {r5, r7, fp} + 2f30: e3b03080 movs r3, #128 ; 0x80 + 2f34: ebf60411 bl 0xffd83f80 + 2f38: 080c08a2 stmeqda ip, {r1, r5, r7, fp} + 2f3c: e2840000 add r0, r4, #0 ; 0x0 + 2f40: e1a01003 mov r1, r3 + 2f44: ebf60180 bl 0xffd8354c + 2f48: 080c08a4 stmeqda ip, {r2, r5, r7, fp} + 2f4c: ebf6040b bl 0xffd83f80 + 2f50: 080c08a4 stmeqda ip, {r2, r5, r7, fp} + 2f54: e59d9434 ldr r9, [sp, #1076] + 2f58: e3c99003 bic r9, r9, #3 ; 0x3 + 2f5c: e289000c add r0, r9, #12 ; 0xc + 2f60: e58d0434 str r0, [sp, #1076] + 2f64: e2890000 add r0, r9, #0 ; 0x0 + 2f68: ebf6026a bl 0xffd83918 + 2f6c: 080c08a8 stmeqda ip, {r3, r5, r7, fp} + 2f70: e1a07000 mov r7, r0 + 2f74: e2890004 add r0, r9, #4 ; 0x4 + 2f78: ebf60266 bl 0xffd83918 + 2f7c: 080c08a8 stmeqda ip, {r3, r5, r7, fp} + 2f80: e1a08000 mov r8, r0 + 2f84: e2890008 add r0, r9, #8 ; 0x8 + 2f88: ebf60262 bl 0xffd83918 + 2f8c: 080c08a8 stmeqda ip, {r3, r5, r7, fp} + 2f90: e58d0418 str r0, [sp, #1048] + 2f94: ebf603f9 bl 0xffd83f80 + 2f98: 080c08a6 stmeqda ip, {r1, r2, r5, r7, fp} + 2f9c: e59d9434 ldr r9, [sp, #1076] + 2fa0: e3c99003 bic r9, r9, #3 ; 0x3 + 2fa4: e2890004 add r0, r9, #4 ; 0x4 + 2fa8: e58d0434 str r0, [sp, #1076] + 2fac: e2890000 add r0, r9, #0 ; 0x0 + 2fb0: ebf60258 bl 0xffd83918 + 2fb4: 080c08aa stmeqda ip, {r1, r3, r5, r7, fp} + 2fb8: e1a03000 mov r3, r0 + 2fbc: ebf603ef bl 0xffd83f80 + 2fc0: 080c08a8 stmeqda ip, {r3, r5, r7, fp} + 2fc4: e1a00003 mov r0, r3 + 2fc8: e28cc019 add ip, ip, #25 ; 0x19 + 2fcc: eaf6003f b 0xffd830d0 + 2fd0: 080c07ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9, sl} + 2fd4: 00000000 andeq r0, r0, r0 + 2fd8: ebf603e8 bl 0xffd83f80 + 2fdc: 080c07ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9, sl} + 2fe0: e3a00f0a mov r0, #40 ; 0x28 + 2fe4: e3800b02 orr r0, r0, #2048 ; 0x800 + 2fe8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 2fec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2ff0: ebf60248 bl 0xffd83918 + 2ff4: 080c07f0 stmeqda ip, {r4, r5, r6, r7, r8, r9, sl} + 2ff8: e1a03000 mov r3, r0 + 2ffc: ebf603df bl 0xffd83f80 + 3000: 080c07ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9, sl} + 3004: e2870000 add r0, r7, #0 ; 0x0 + 3008: e1a01003 mov r1, r3 + 300c: ebf6016e bl 0xffd835cc + 3010: 080c07f0 stmeqda ip, {r4, r5, r6, r7, r8, r9, sl} + 3014: ebf603d9 bl 0xffd83f80 + 3018: 080c07f0 stmeqda ip, {r4, r5, r6, r7, r8, r9, sl} + 301c: e59d0434 ldr r0, [sp, #1076] + 3020: e2800f01 add r0, r0, #4 ; 0x4 + 3024: e58d0434 str r0, [sp, #1076] + 3028: ebf603d4 bl 0xffd83f80 + 302c: 080c07f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, r9, sl} + 3030: e59d9434 ldr r9, [sp, #1076] + 3034: e3c99003 bic r9, r9, #3 ; 0x3 + 3038: e2890004 add r0, r9, #4 ; 0x4 + 303c: e58d0434 str r0, [sp, #1076] + 3040: e2890000 add r0, r9, #0 ; 0x0 + 3044: ebf60233 bl 0xffd83918 + 3048: 080c07f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, r9, sl} + 304c: e1a07000 mov r7, r0 + 3050: ebf603ca bl 0xffd83f80 + 3054: 080c07f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, r9, sl} + 3058: e59d9434 ldr r9, [sp, #1076] + 305c: e3c99003 bic r9, r9, #3 ; 0x3 + 3060: e2890004 add r0, r9, #4 ; 0x4 + 3064: e58d0434 str r0, [sp, #1076] + 3068: e2890000 add r0, r9, #0 ; 0x0 + 306c: ebf60229 bl 0xffd83918 + 3070: 080c07f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, r9, sl} + 3074: e1a03000 mov r3, r0 + 3078: e28cc014 add ip, ip, #20 ; 0x14 + 307c: ebf603bf bl 0xffd83f80 + 3080: 080c07f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, r9, sl} + 3084: e1a00003 mov r0, r3 + 3088: e28cc003 add ip, ip, #3 ; 0x3 + 308c: eaf6000f b 0xffd830d0 + 3090: 080c03c0 stmeqda ip, {r6, r7, r8, r9} + 3094: 00000000 andeq r0, r0, r0 + 3098: ebf603b8 bl 0xffd83f80 + 309c: 080c03c0 stmeqda ip, {r6, r7, r8, r9} + 30a0: e3a00f07 mov r0, #28 ; 0x1c + 30a4: e3800b01 orr r0, r0, #1024 ; 0x400 + 30a8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 30ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 30b0: ebf60218 bl 0xffd83918 + 30b4: 080c03c4 stmeqda ip, {r2, r6, r7, r8, r9} + 30b8: e1a03000 mov r3, r0 + 30bc: ebf603af bl 0xffd83f80 + 30c0: 080c03c2 stmeqda ip, {r1, r6, r7, r8, r9} + 30c4: ebf603ad bl 0xffd83f80 + 30c8: 080c03c4 stmeqda ip, {r2, r6, r7, r8, r9} + 30cc: e3a000c7 mov r0, #199 ; 0xc7 + 30d0: e3800c03 orr r0, r0, #768 ; 0x300 + 30d4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 30d8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 30dc: e58d0438 str r0, [sp, #1080] + 30e0: e28cc00b add ip, ip, #11 ; 0xb + 30e4: e1a00fac mov r0, ip, lsr #31 + 30e8: e08ff100 add pc, pc, r0, lsl #2 + 30ec: 080c0614 stmeqda ip, {r2, r4, r9, sl} + 30f0: ebf5ff97 bl 0xffd82f54 + 30f4: ea000001 b 0x3100 + 30f8: 080c0614 stmeqda ip, {r2, r4, r9, sl} + 30fc: 00000000 andeq r0, r0, r0 + 3100: ebf6039e bl 0xffd83f80 + 3104: 080c0614 stmeqda ip, {r2, r4, r9, sl} + 3108: e59d9434 ldr r9, [sp, #1076] + 310c: e3c99003 bic r9, r9, #3 ; 0x3 + 3110: e2499014 sub r9, r9, #20 ; 0x14 + 3114: e58d9434 str r9, [sp, #1076] + 3118: e2890000 add r0, r9, #0 ; 0x0 + 311c: e1a01007 mov r1, r7 + 3120: ebf60149 bl 0xffd8364c + 3124: e2890004 add r0, r9, #4 ; 0x4 + 3128: e1a01008 mov r1, r8 + 312c: ebf60146 bl 0xffd8364c + 3130: e2890008 add r0, r9, #8 ; 0x8 + 3134: e59d1418 ldr r1, [sp, #1048] + 3138: ebf60143 bl 0xffd8364c + 313c: e289000c add r0, r9, #12 ; 0xc + 3140: e59d141c ldr r1, [sp, #1052] + 3144: ebf60140 bl 0xffd8364c + 3148: e2890010 add r0, r9, #16 ; 0x10 + 314c: e59d1438 ldr r1, [sp, #1080] + 3150: ebf6013d bl 0xffd8364c + 3154: ebf60389 bl 0xffd83f80 + 3158: 080c0616 stmeqda ip, {r1, r2, r4, r9, sl} + 315c: e59d0434 ldr r0, [sp, #1076] + 3160: e2400f01 sub r0, r0, #4 ; 0x4 + 3164: e58d0434 str r0, [sp, #1076] + 3168: ebf60384 bl 0xffd83f80 + 316c: 080c0618 stmeqda ip, {r3, r4, r9, sl} + 3170: e1a01003 mov r1, r3 + 3174: e2930000 adds r0, r3, #0 ; 0x0 + 3178: e58d0418 str r0, [sp, #1048] + 317c: ebf6037f bl 0xffd83f80 + 3180: 080c061a stmeqda ip, {r1, r3, r4, r9, sl} + 3184: e3a00fba mov r0, #744 ; 0x2e8 + 3188: e3800b01 orr r0, r0, #1024 ; 0x400 + 318c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3190: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3194: ebf601df bl 0xffd83918 + 3198: 080c061e stmeqda ip, {r1, r2, r3, r4, r9, sl} + 319c: e1a04000 mov r4, r0 + 31a0: ebf60376 bl 0xffd83f80 + 31a4: 080c061c stmeqda ip, {r2, r3, r4, r9, sl} + 31a8: e3b0308f movs r3, #143 ; 0x8f + 31ac: ebf60373 bl 0xffd83f80 + 31b0: 080c061e stmeqda ip, {r1, r2, r3, r4, r9, sl} + 31b4: e2840000 add r0, r4, #0 ; 0x0 + 31b8: e1a01003 mov r1, r3 + 31bc: ebf600e2 bl 0xffd8354c + 31c0: 080c0620 stmeqda ip, {r5, r9, sl} + 31c4: ebf6036d bl 0xffd83f80 + 31c8: 080c0620 stmeqda ip, {r5, r9, sl} + 31cc: e3a00fbb mov r0, #748 ; 0x2ec + 31d0: e3800b01 orr r0, r0, #1024 ; 0x400 + 31d4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 31d8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 31dc: ebf601cd bl 0xffd83918 + 31e0: 080c0624 stmeqda ip, {r2, r5, r9, sl} + 31e4: e1a05000 mov r5, r0 + 31e8: ebf60364 bl 0xffd83f80 + 31ec: 080c0622 stmeqda ip, {r1, r5, r9, sl} + 31f0: e3b03077 movs r3, #119 ; 0x77 + 31f4: ebf60361 bl 0xffd83f80 + 31f8: 080c0624 stmeqda ip, {r2, r5, r9, sl} + 31fc: e2850000 add r0, r5, #0 ; 0x0 + 3200: e1a01003 mov r1, r3 + 3204: ebf600d0 bl 0xffd8354c + 3208: 080c0626 stmeqda ip, {r1, r2, r5, r9, sl} + 320c: ebf6035b bl 0xffd83f80 + 3210: 080c0626 stmeqda ip, {r1, r2, r5, r9, sl} + 3214: e3a00e6f mov r0, #1776 ; 0x6f0 + 3218: e3800703 orr r0, r0, #786432 ; 0xc0000 + 321c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3220: ebf601bc bl 0xffd83918 + 3224: 080c062a stmeqda ip, {r1, r3, r5, r9, sl} + 3228: e1a03000 mov r3, r0 + 322c: ebf60353 bl 0xffd83f80 + 3230: 080c0628 stmeqda ip, {r3, r5, r9, sl} + 3234: e3b04008 movs r4, #8 ; 0x8 + 3238: ebf60350 bl 0xffd83f80 + 323c: 080c062a stmeqda ip, {r1, r3, r5, r9, sl} + 3240: e2830000 add r0, r3, #0 ; 0x0 + 3244: e1a01004 mov r1, r4 + 3248: ebf600a0 bl 0xffd834d0 + 324c: 080c062c stmeqda ip, {r2, r3, r5, r9, sl} + 3250: ebf6034a bl 0xffd83f80 + 3254: 080c062c stmeqda ip, {r2, r3, r5, r9, sl} + 3258: e1a01003 mov r1, r3 + 325c: e2933006 adds r3, r3, #6 ; 0x6 + 3260: ebf60346 bl 0xffd83f80 + 3264: 080c062e stmeqda ip, {r1, r2, r3, r5, r9, sl} + 3268: e2830000 add r0, r3, #0 ; 0x0 + 326c: e1a01004 mov r1, r4 + 3270: ebf60096 bl 0xffd834d0 + 3274: 080c0630 stmeqda ip, {r4, r5, r9, sl} + 3278: ebf60340 bl 0xffd83f80 + 327c: 080c0630 stmeqda ip, {r4, r5, r9, sl} + 3280: e1a01003 mov r1, r3 + 3284: e2933010 adds r3, r3, #16 ; 0x10 + 3288: ebf6033c bl 0xffd83f80 + 328c: 080c0632 stmeqda ip, {r1, r4, r5, r9, sl} + 3290: e2830000 add r0, r3, #0 ; 0x0 + 3294: e1a01004 mov r1, r4 + 3298: ebf6008c bl 0xffd834d0 + 329c: 080c0634 stmeqda ip, {r2, r4, r5, r9, sl} + 32a0: ebf60336 bl 0xffd83f80 + 32a4: 080c0634 stmeqda ip, {r2, r4, r5, r9, sl} + 32a8: e1a01003 mov r1, r3 + 32ac: e2533014 subs r3, r3, #20 ; 0x14 + 32b0: ebf60332 bl 0xffd83f80 + 32b4: 080c0636 stmeqda ip, {r1, r2, r4, r5, r9, sl} + 32b8: e3b04080 movs r4, #128 ; 0x80 + 32bc: ebf6032f bl 0xffd83f80 + 32c0: 080c0638 stmeqda ip, {r3, r4, r5, r9, sl} + 32c4: e2830000 add r0, r3, #0 ; 0x0 + 32c8: e1a01004 mov r1, r4 + 32cc: ebf6007f bl 0xffd834d0 + 32d0: 080c063a stmeqda ip, {r1, r3, r4, r5, r9, sl} + 32d4: ebf60329 bl 0xffd83f80 + 32d8: 080c063a stmeqda ip, {r1, r3, r4, r5, r9, sl} + 32dc: e1a01003 mov r1, r3 + 32e0: e2933008 adds r3, r3, #8 ; 0x8 + 32e4: ebf60325 bl 0xffd83f80 + 32e8: 080c063c stmeqda ip, {r2, r3, r4, r5, r9, sl} + 32ec: e2830000 add r0, r3, #0 ; 0x0 + 32f0: e1a01004 mov r1, r4 + 32f4: ebf60075 bl 0xffd834d0 + 32f8: 080c063e stmeqda ip, {r1, r2, r3, r4, r5, r9, sl} + 32fc: ebf6031f bl 0xffd83f80 + 3300: 080c063e stmeqda ip, {r1, r2, r3, r4, r5, r9, sl} + 3304: e1a01003 mov r1, r3 + 3308: e2933010 adds r3, r3, #16 ; 0x10 + 330c: ebf6031b bl 0xffd83f80 + 3310: 080c0640 stmeqda ip, {r6, r9, sl} + 3314: e2830000 add r0, r3, #0 ; 0x0 + 3318: e1a01004 mov r1, r4 + 331c: ebf6006b bl 0xffd834d0 + 3320: 080c0642 stmeqda ip, {r1, r6, r9, sl} + 3324: ebf60315 bl 0xffd83f80 + 3328: 080c0642 stmeqda ip, {r1, r6, r9, sl} + 332c: e3a00fbd mov r0, #756 ; 0x2f4 + 3330: e3800b01 orr r0, r0, #1024 ; 0x400 + 3334: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3338: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 333c: ebf60175 bl 0xffd83918 + 3340: 080c0646 stmeqda ip, {r1, r2, r6, r9, sl} + 3344: e1a04000 mov r4, r0 + 3348: ebf6030c bl 0xffd83f80 + 334c: 080c0644 stmeqda ip, {r2, r6, r9, sl} + 3350: e3b03000 movs r3, #0 ; 0x0 + 3354: ebf60309 bl 0xffd83f80 + 3358: 080c0646 stmeqda ip, {r1, r2, r6, r9, sl} + 335c: e2840000 add r0, r4, #0 ; 0x0 + 3360: e1a01003 mov r1, r3 + 3364: ebf60059 bl 0xffd834d0 + 3368: 080c0648 stmeqda ip, {r3, r6, r9, sl} + 336c: ebf60303 bl 0xffd83f80 + 3370: 080c0648 stmeqda ip, {r3, r6, r9, sl} + 3374: e3a00fbe mov r0, #760 ; 0x2f8 + 3378: e3800b01 orr r0, r0, #1024 ; 0x400 + 337c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3380: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3384: ebf60163 bl 0xffd83918 + 3388: 080c064c stmeqda ip, {r2, r3, r6, r9, sl} + 338c: e1a04000 mov r4, r0 + 3390: ebf602fa bl 0xffd83f80 + 3394: 080c064a stmeqda ip, {r1, r3, r6, r9, sl} + 3398: e1a01004 mov r1, r4 + 339c: e2943000 adds r3, r4, #0 ; 0x0 + 33a0: ebf602f6 bl 0xffd83f80 + 33a4: 080c064c stmeqda ip, {r2, r3, r6, r9, sl} + 33a8: e2850000 add r0, r5, #0 ; 0x0 + 33ac: e1a01003 mov r1, r3 + 33b0: ebf60065 bl 0xffd8354c + 33b4: 080c064e stmeqda ip, {r1, r2, r3, r6, r9, sl} + 33b8: ebf602f0 bl 0xffd83f80 + 33bc: 080c064e stmeqda ip, {r1, r2, r3, r6, r9, sl} + 33c0: e3a00fbf mov r0, #764 ; 0x2fc + 33c4: e3800b01 orr r0, r0, #1024 ; 0x400 + 33c8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 33cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 33d0: ebf60150 bl 0xffd83918 + 33d4: 080c0652 stmeqda ip, {r1, r4, r6, r9, sl} + 33d8: e1a03000 mov r3, r0 + 33dc: ebf602e7 bl 0xffd83f80 + 33e0: 080c0650 stmeqda ip, {r4, r6, r9, sl} + 33e4: e2830000 add r0, r3, #0 ; 0x0 + 33e8: ebf6014a bl 0xffd83918 + 33ec: 080c0654 stmeqda ip, {r2, r4, r6, r9, sl} + 33f0: e1a08000 mov r8, r0 + 33f4: ebf602e1 bl 0xffd83f80 + 33f8: 080c0652 stmeqda ip, {r1, r4, r6, r9, sl} + 33fc: e2880000 add r0, r8, #0 ; 0x0 + 3400: ebf60144 bl 0xffd83918 + 3404: 080c0656 stmeqda ip, {r1, r2, r4, r6, r9, sl} + 3408: e58d041c str r0, [sp, #1052] + 340c: ebf602db bl 0xffd83f80 + 3410: 080c0654 stmeqda ip, {r2, r4, r6, r9, sl} + 3414: e3a00c07 mov r0, #1792 ; 0x700 + 3418: e3800703 orr r0, r0, #786432 ; 0xc0000 + 341c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3420: ebf6013c bl 0xffd83918 + 3424: 080c0658 stmeqda ip, {r3, r4, r6, r9, sl} + 3428: e1a03000 mov r3, r0 + 342c: ebf602d3 bl 0xffd83f80 + 3430: 080c0656 stmeqda ip, {r1, r2, r4, r6, r9, sl} + 3434: e59d141c ldr r1, [sp, #1052] + 3438: e1510003 cmp r1, r3 + 343c: ebf602cf bl 0xffd83f80 + 3440: 080c0658 stmeqda ip, {r3, r4, r6, r9, sl} + 3444: e28cc089 add ip, ip, #137 ; 0x89 + 3448: 0a000004 beq 0x3460 + 344c: e1a00fac mov r0, ip, lsr #31 + 3450: e08ff100 add pc, pc, r0, lsl #2 + 3454: 080c06e0 stmeqda ip, {r5, r6, r7, r9, sl} + 3458: ebf5febd bl 0xffd82f54 + 345c: ea000028 b 0x3504 + 3460: ebf602c6 bl 0xffd83f80 + 3464: 080c065a stmeqda ip, {r1, r3, r4, r6, r9, sl} + 3468: e59d141c ldr r1, [sp, #1052] + 346c: e59d141c ldr r1, [sp, #1052] + 3470: e2913001 adds r3, r1, #1 ; 0x1 + 3474: ebf602c1 bl 0xffd83f80 + 3478: 080c065c stmeqda ip, {r2, r3, r4, r6, r9, sl} + 347c: e2880000 add r0, r8, #0 ; 0x0 + 3480: e1a01003 mov r1, r3 + 3484: ebf60050 bl 0xffd835cc + 3488: 080c065e stmeqda ip, {r1, r2, r3, r4, r6, r9, sl} + 348c: ebf602bb bl 0xffd83f80 + 3490: 080c065e stmeqda ip, {r1, r2, r3, r4, r6, r9, sl} + 3494: e3a00fc1 mov r0, #772 ; 0x304 + 3498: e3800b01 orr r0, r0, #1024 ; 0x400 + 349c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 34a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 34a4: ebf6011b bl 0xffd83918 + 34a8: 080c0662 stmeqda ip, {r1, r5, r6, r9, sl} + 34ac: e1a07000 mov r7, r0 + 34b0: ebf602b2 bl 0xffd83f80 + 34b4: 080c0660 stmeqda ip, {r5, r6, r9, sl} + 34b8: e1a01007 mov r1, r7 + 34bc: e2973000 adds r3, r7, #0 ; 0x0 + 34c0: ebf602ae bl 0xffd83f80 + 34c4: 080c0662 stmeqda ip, {r1, r5, r6, r9, sl} + 34c8: ebf602ac bl 0xffd83f80 + 34cc: 080c0664 stmeqda ip, {r2, r5, r6, r9, sl} + 34d0: e3a00067 mov r0, #103 ; 0x67 + 34d4: e3800c06 orr r0, r0, #1536 ; 0x600 + 34d8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 34dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 34e0: e58d0438 str r0, [sp, #1080] + 34e4: e28cc015 add ip, ip, #21 ; 0x15 + 34e8: e1a00fac mov r0, ip, lsr #31 + 34ec: e08ff100 add pc, pc, r0, lsl #2 + 34f0: 080bfbb8 stmeqda fp, {r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 34f4: ebf5fe96 bl 0xffd82f54 + 34f8: ea00002d b 0x35b4 + 34fc: 080c06e0 stmeqda ip, {r5, r6, r7, r9, sl} + 3500: 00000000 andeq r0, r0, r0 + 3504: ebf6029d bl 0xffd83f80 + 3508: 080c06e0 stmeqda ip, {r5, r6, r7, r9, sl} + 350c: e59d0434 ldr r0, [sp, #1076] + 3510: e2800f01 add r0, r0, #4 ; 0x4 + 3514: e58d0434 str r0, [sp, #1076] + 3518: ebf60298 bl 0xffd83f80 + 351c: 080c06e2 stmeqda ip, {r1, r5, r6, r7, r9, sl} + 3520: e59d9434 ldr r9, [sp, #1076] + 3524: e3c99003 bic r9, r9, #3 ; 0x3 + 3528: e2890010 add r0, r9, #16 ; 0x10 + 352c: e58d0434 str r0, [sp, #1076] + 3530: e2890000 add r0, r9, #0 ; 0x0 + 3534: ebf600f7 bl 0xffd83918 + 3538: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 353c: e1a07000 mov r7, r0 + 3540: e2890004 add r0, r9, #4 ; 0x4 + 3544: ebf600f3 bl 0xffd83918 + 3548: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 354c: e1a08000 mov r8, r0 + 3550: e2890008 add r0, r9, #8 ; 0x8 + 3554: ebf600ef bl 0xffd83918 + 3558: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 355c: e58d0418 str r0, [sp, #1048] + 3560: e289000c add r0, r9, #12 ; 0xc + 3564: ebf600eb bl 0xffd83918 + 3568: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 356c: e58d041c str r0, [sp, #1052] + 3570: ebf60282 bl 0xffd83f80 + 3574: 080c06e4 stmeqda ip, {r2, r5, r6, r7, r9, sl} + 3578: e59d9434 ldr r9, [sp, #1076] + 357c: e3c99003 bic r9, r9, #3 ; 0x3 + 3580: e2890004 add r0, r9, #4 ; 0x4 + 3584: e58d0434 str r0, [sp, #1076] + 3588: e2890000 add r0, r9, #0 ; 0x0 + 358c: ebf600e1 bl 0xffd83918 + 3590: 080c06e8 stmeqda ip, {r3, r5, r6, r7, r9, sl} + 3594: e1a03000 mov r3, r0 + 3598: ebf60278 bl 0xffd83f80 + 359c: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 35a0: e1a00003 mov r0, r3 + 35a4: e28cc011 add ip, ip, #17 ; 0x11 + 35a8: eaf5fec8 b 0xffd830d0 + 35ac: 080bfbb8 stmeqda fp, {r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 35b0: 00000000 andeq r0, r0, r0 + 35b4: ebf60271 bl 0xffd83f80 + 35b8: 080bfbb8 stmeqda fp, {r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 35bc: e59d1438 ldr r1, [sp, #1080] + 35c0: e1a00001 mov r0, r1 + 35c4: e58d0430 str r0, [sp, #1072] + 35c8: ebf6026c bl 0xffd83f80 + 35cc: 080bfbba stmeqda fp, {r1, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 35d0: e3b04024 movs r4, #36 ; 0x24 + 35d4: ebf60269 bl 0xffd83f80 + 35d8: 080bfbbc stmeqda fp, {r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 35dc: e3a00ffa mov r0, #1000 ; 0x3e8 + 35e0: e3800bfe orr r0, r0, #260096 ; 0x3f800 + 35e4: e3800702 orr r0, r0, #524288 ; 0x80000 + 35e8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 35ec: ebf600c9 bl 0xffd83918 + 35f0: 080bfbc0 stmeqda fp, {r6, r7, r8, r9, fp, ip, sp, lr, pc} + 35f4: e1a05000 mov r5, r0 + 35f8: ebf60260 bl 0xffd83f80 + 35fc: 080bfbbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 3600: e2850000 add r0, r5, #0 ; 0x0 + 3604: ebf600c3 bl 0xffd83918 + 3608: 080bfbc2 stmeqda fp, {r1, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 360c: e1a06000 mov r6, r0 + 3610: ebf6025a bl 0xffd83f80 + 3614: 080bfbc0 stmeqda fp, {r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3618: ebf60258 bl 0xffd83f80 + 361c: 080bfbc2 stmeqda fp, {r1, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3620: e3a000c5 mov r0, #197 ; 0xc5 + 3624: e3800cfb orr r0, r0, #64256 ; 0xfb00 + 3628: e380080b orr r0, r0, #720896 ; 0xb0000 + 362c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3630: e58d0438 str r0, [sp, #1080] + 3634: e28cc016 add ip, ip, #22 ; 0x16 + 3638: e1a00fac mov r0, ip, lsr #31 + 363c: e08ff100 add pc, pc, r0, lsl #2 + 3640: 080bfbd2 stmeqda fp, {r1, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3644: ebf5fe42 bl 0xffd82f54 + 3648: ea000001 b 0x3654 + 364c: 080bfbd2 stmeqda fp, {r1, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3650: 00000000 andeq r0, r0, r0 + 3654: ebf60249 bl 0xffd83f80 + 3658: 080bfbd2 stmeqda fp, {r1, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 365c: e59d9434 ldr r9, [sp, #1076] + 3660: e3c99003 bic r9, r9, #3 ; 0x3 + 3664: e2499004 sub r9, r9, #4 ; 0x4 + 3668: e58d9434 str r9, [sp, #1076] + 366c: e2890000 add r0, r9, #0 ; 0x0 + 3670: e1a01003 mov r1, r3 + 3674: ebf5ffd4 bl 0xffd835cc + 3678: 080bfbd4 stmeqda fp, {r2, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 367c: ebf6023f bl 0xffd83f80 + 3680: 080bfbd4 stmeqda fp, {r2, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3684: e1b03ca5 movs r3, r5, lsr #25 + 3688: ebf6023c bl 0xffd83f80 + 368c: 080bfbd6 stmeqda fp, {r1, r2, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3690: e28cc00a add ip, ip, #10 ; 0xa + 3694: 0a000004 beq 0x36ac + 3698: e1a00fac mov r0, ip, lsr #31 + 369c: e08ff100 add pc, pc, r0, lsl #2 + 36a0: 080bfbe4 stmeqda fp, {r2, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36a4: ebf5fe2a bl 0xffd82f54 + 36a8: ea000024 b 0x3740 + 36ac: ebf60233 bl 0xffd83f80 + 36b0: 080bfbd8 stmeqda fp, {r3, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36b4: e3a00ffa mov r0, #1000 ; 0x3e8 + 36b8: e3800bfe orr r0, r0, #260096 ; 0x3f800 + 36bc: e3800702 orr r0, r0, #524288 ; 0x80000 + 36c0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 36c4: ebf60093 bl 0xffd83918 + 36c8: 080bfbdc stmeqda fp, {r2, r3, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36cc: e1a03000 mov r3, r0 + 36d0: ebf6022a bl 0xffd83f80 + 36d4: 080bfbda stmeqda fp, {r1, r3, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36d8: e1550003 cmp r5, r3 + 36dc: ebf60227 bl 0xffd83f80 + 36e0: 080bfbdc stmeqda fp, {r2, r3, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36e4: e28cc00b add ip, ip, #11 ; 0xb + 36e8: 2a000004 bcs 0x3700 + 36ec: e1a00fac mov r0, ip, lsr #31 + 36f0: e08ff100 add pc, pc, r0, lsl #2 + 36f4: 080bfbe2 stmeqda fp, {r1, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 36f8: ebf5fe15 bl 0xffd82f54 + 36fc: ea00000b b 0x3730 + 3700: ebf6021e bl 0xffd83f80 + 3704: 080bfbde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3708: e1b03725 movs r3, r5, lsr #14 + 370c: ebf6021b bl 0xffd83f80 + 3710: 080bfbe0 stmeqda fp, {r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3714: e28cc006 add ip, ip, #6 ; 0x6 + 3718: 1a000004 bne 0x3730 + 371c: e1a00fac mov r0, ip, lsr #31 + 3720: e08ff100 add pc, pc, r0, lsl #2 + 3724: 080bfbe4 stmeqda fp, {r2, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3728: ebf5fe09 bl 0xffd82f54 + 372c: ea000003 b 0x3740 + 3730: ebf60212 bl 0xffd83f80 + 3734: 080bfbe2 stmeqda fp, {r1, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3738: e3b06000 movs r6, #0 ; 0x0 + 373c: e28cc003 add ip, ip, #3 ; 0x3 + 3740: ebf6020e bl 0xffd83f80 + 3744: 080bfbe4 stmeqda fp, {r2, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3748: e59d9434 ldr r9, [sp, #1076] + 374c: e3c99003 bic r9, r9, #3 ; 0x3 + 3750: e2890004 add r0, r9, #4 ; 0x4 + 3754: e58d0434 str r0, [sp, #1076] + 3758: e2890000 add r0, r9, #0 ; 0x0 + 375c: ebf6006d bl 0xffd83918 + 3760: 080bfbe8 stmeqda fp, {r3, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3764: e1a03000 mov r3, r0 + 3768: ebf60204 bl 0xffd83f80 + 376c: 080bfbe6 stmeqda fp, {r1, r2, r5, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3770: e59d0438 ldr r0, [sp, #1080] + 3774: e28cc007 add ip, ip, #7 ; 0x7 + 3778: eaf5fe54 b 0xffd830d0 + 377c: 080bfbc4 stmeqda fp, {r2, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3780: 00000000 andeq r0, r0, r0 + 3784: ebf601fd bl 0xffd83f80 + 3788: 080bfbc4 stmeqda fp, {r2, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 378c: e1a09003 mov r9, r3 + 3790: e3c99003 bic r9, r9, #3 ; 0x3 + 3794: e2890004 add r0, r9, #4 ; 0x4 + 3798: e1a03000 mov r3, r0 + 379c: e2890000 add r0, r9, #0 ; 0x0 + 37a0: e1a01006 mov r1, r6 + 37a4: ebf5ff88 bl 0xffd835cc + 37a8: 080bfbc6 stmeqda fp, {r1, r2, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 37ac: ebf601f3 bl 0xffd83f80 + 37b0: 080bfbc6 stmeqda fp, {r1, r2, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 37b4: e1a01005 mov r1, r5 + 37b8: e2955004 adds r5, r5, #4 ; 0x4 + 37bc: ebf601ef bl 0xffd83f80 + 37c0: 080bfbc8 stmeqda fp, {r3, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 37c4: e1a01004 mov r1, r4 + 37c8: e2544001 subs r4, r4, #1 ; 0x1 + 37cc: ebf601eb bl 0xffd83f80 + 37d0: 080bfbca stmeqda fp, {r1, r3, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 37d4: e28cc00d add ip, ip, #13 ; 0xd + 37d8: da000004 ble 0x37f0 + 37dc: e1a00fac mov r0, ip, lsr #31 + 37e0: e08ff100 add pc, pc, r0, lsl #2 + 37e4: 080bfbbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 37e8: ebf5fdd9 bl 0xffd82f54 + 37ec: ea000006 b 0x380c + 37f0: ebf601e2 bl 0xffd83f80 + 37f4: 080bfbcc stmeqda fp, {r2, r3, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 37f8: e59d0430 ldr r0, [sp, #1072] + 37fc: e28cc003 add ip, ip, #3 ; 0x3 + 3800: eaf5fe32 b 0xffd830d0 + 3804: 080bfbbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 3808: 00000000 andeq r0, r0, r0 + 380c: ebf601db bl 0xffd83f80 + 3810: 080bfbbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp, lr, pc} + 3814: e2850000 add r0, r5, #0 ; 0x0 + 3818: ebf6003e bl 0xffd83918 + 381c: 080bfbc2 stmeqda fp, {r1, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3820: e1a06000 mov r6, r0 + 3824: ebf601d5 bl 0xffd83f80 + 3828: 080bfbc0 stmeqda fp, {r6, r7, r8, r9, fp, ip, sp, lr, pc} + 382c: ebf601d3 bl 0xffd83f80 + 3830: 080bfbc2 stmeqda fp, {r1, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3834: e3a000c5 mov r0, #197 ; 0xc5 + 3838: e3800cfb orr r0, r0, #64256 ; 0xfb00 + 383c: e380080b orr r0, r0, #720896 ; 0xb0000 + 3840: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3844: e58d0438 str r0, [sp, #1080] + 3848: e28cc00b add ip, ip, #11 ; 0xb + 384c: e1a00fac mov r0, ip, lsr #31 + 3850: e08ff100 add pc, pc, r0, lsl #2 + 3854: 080bfbd2 stmeqda fp, {r1, r4, r6, r7, r8, r9, fp, ip, sp, lr, pc} + 3858: ebf5fdbd bl 0xffd82f54 + 385c: eaffff7c b 0x3654 + 3860: 080c0666 stmeqda ip, {r1, r2, r5, r6, r9, sl} + 3864: 00000000 andeq r0, r0, r0 + 3868: ebf601c4 bl 0xffd83f80 + 386c: 080c0666 stmeqda ip, {r1, r2, r5, r6, r9, sl} + 3870: e3a00fc2 mov r0, #776 ; 0x308 + 3874: e3800b01 orr r0, r0, #1024 ; 0x400 + 3878: e3800703 orr r0, r0, #786432 ; 0xc0000 + 387c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3880: ebf60024 bl 0xffd83918 + 3884: 080c066a stmeqda ip, {r1, r3, r5, r6, r9, sl} + 3888: e1a03000 mov r3, r0 + 388c: ebf601bb bl 0xffd83f80 + 3890: 080c0668 stmeqda ip, {r3, r5, r6, r9, sl} + 3894: e2870020 add r0, r7, #32 ; 0x20 + 3898: e1a01003 mov r1, r3 + 389c: ebf5ff4a bl 0xffd835cc + 38a0: 080c066a stmeqda ip, {r1, r3, r5, r6, r9, sl} + 38a4: ebf601b5 bl 0xffd83f80 + 38a8: 080c066a stmeqda ip, {r1, r3, r5, r6, r9, sl} + 38ac: e3a00fc3 mov r0, #780 ; 0x30c + 38b0: e3800b01 orr r0, r0, #1024 ; 0x400 + 38b4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 38b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 38bc: ebf60015 bl 0xffd83918 + 38c0: 080c066e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl} + 38c4: e1a03000 mov r3, r0 + 38c8: ebf601ac bl 0xffd83f80 + 38cc: 080c066c stmeqda ip, {r2, r3, r5, r6, r9, sl} + 38d0: e2870044 add r0, r7, #68 ; 0x44 + 38d4: e1a01003 mov r1, r3 + 38d8: ebf5ff3b bl 0xffd835cc + 38dc: 080c066e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl} + 38e0: ebf601a6 bl 0xffd83f80 + 38e4: 080c066e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl} + 38e8: e3a00e71 mov r0, #1808 ; 0x710 + 38ec: e3800703 orr r0, r0, #786432 ; 0xc0000 + 38f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 38f4: ebf60007 bl 0xffd83918 + 38f8: 080c0672 stmeqda ip, {r1, r4, r5, r6, r9, sl} + 38fc: e1a03000 mov r3, r0 + 3900: ebf6019e bl 0xffd83f80 + 3904: 080c0670 stmeqda ip, {r4, r5, r6, r9, sl} + 3908: e287004c add r0, r7, #76 ; 0x4c + 390c: e1a01003 mov r1, r3 + 3910: ebf5ff2d bl 0xffd835cc + 3914: 080c0672 stmeqda ip, {r1, r4, r5, r6, r9, sl} + 3918: ebf60198 bl 0xffd83f80 + 391c: 080c0672 stmeqda ip, {r1, r4, r5, r6, r9, sl} + 3920: e3a00fc5 mov r0, #788 ; 0x314 + 3924: e3800b01 orr r0, r0, #1024 ; 0x400 + 3928: e3800703 orr r0, r0, #786432 ; 0xc0000 + 392c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3930: ebf5fff8 bl 0xffd83918 + 3934: 080c0676 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl} + 3938: e1a03000 mov r3, r0 + 393c: ebf6018f bl 0xffd83f80 + 3940: 080c0674 stmeqda ip, {r2, r4, r5, r6, r9, sl} + 3944: e2870070 add r0, r7, #112 ; 0x70 + 3948: e1a01003 mov r1, r3 + 394c: ebf5ff1e bl 0xffd835cc + 3950: 080c0676 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl} + 3954: ebf60189 bl 0xffd83f80 + 3958: 080c0676 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl} + 395c: e3a00fc6 mov r0, #792 ; 0x318 + 3960: e3800b01 orr r0, r0, #1024 ; 0x400 + 3964: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3968: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 396c: ebf5ffe9 bl 0xffd83918 + 3970: 080c067a stmeqda ip, {r1, r3, r4, r5, r6, r9, sl} + 3974: e1a03000 mov r3, r0 + 3978: ebf60180 bl 0xffd83f80 + 397c: 080c0678 stmeqda ip, {r3, r4, r5, r6, r9, sl} + 3980: e2870074 add r0, r7, #116 ; 0x74 + 3984: e1a01003 mov r1, r3 + 3988: ebf5ff0f bl 0xffd835cc + 398c: 080c067a stmeqda ip, {r1, r3, r4, r5, r6, r9, sl} + 3990: ebf6017a bl 0xffd83f80 + 3994: 080c067a stmeqda ip, {r1, r3, r4, r5, r6, r9, sl} + 3998: e3a00fc7 mov r0, #796 ; 0x31c + 399c: e3800b01 orr r0, r0, #1024 ; 0x400 + 39a0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 39a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 39a8: ebf5ffda bl 0xffd83918 + 39ac: 080c067e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl} + 39b0: e1a03000 mov r3, r0 + 39b4: ebf60171 bl 0xffd83f80 + 39b8: 080c067c stmeqda ip, {r2, r3, r4, r5, r6, r9, sl} + 39bc: e2870078 add r0, r7, #120 ; 0x78 + 39c0: e1a01003 mov r1, r3 + 39c4: ebf5ff00 bl 0xffd835cc + 39c8: 080c067e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl} + 39cc: ebf6016b bl 0xffd83f80 + 39d0: 080c067e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl} + 39d4: e3a00e72 mov r0, #1824 ; 0x720 + 39d8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 39dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 39e0: ebf5ffcc bl 0xffd83918 + 39e4: 080c0682 stmeqda ip, {r1, r7, r9, sl} + 39e8: e1a03000 mov r3, r0 + 39ec: ebf60163 bl 0xffd83f80 + 39f0: 080c0680 stmeqda ip, {r7, r9, sl} + 39f4: e287007c add r0, r7, #124 ; 0x7c + 39f8: e1a01003 mov r1, r3 + 39fc: ebf5fef2 bl 0xffd835cc + 3a00: 080c0682 stmeqda ip, {r1, r7, r9, sl} + 3a04: ebf6015d bl 0xffd83f80 + 3a08: 080c0682 stmeqda ip, {r1, r7, r9, sl} + 3a0c: e1a01007 mov r1, r7 + 3a10: e2974000 adds r4, r7, #0 ; 0x0 + 3a14: ebf60159 bl 0xffd83f80 + 3a18: 080c0684 stmeqda ip, {r2, r7, r9, sl} + 3a1c: e1a01004 mov r1, r4 + 3a20: e2944080 adds r4, r4, #128 ; 0x80 + 3a24: ebf60155 bl 0xffd83f80 + 3a28: 080c0686 stmeqda ip, {r1, r2, r7, r9, sl} + 3a2c: e3a00fc9 mov r0, #804 ; 0x324 + 3a30: e3800b01 orr r0, r0, #1024 ; 0x400 + 3a34: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3a38: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3a3c: ebf5ffb5 bl 0xffd83918 + 3a40: 080c068a stmeqda ip, {r1, r3, r7, r9, sl} + 3a44: e1a03000 mov r3, r0 + 3a48: ebf6014c bl 0xffd83f80 + 3a4c: 080c0688 stmeqda ip, {r3, r7, r9, sl} + 3a50: e2840000 add r0, r4, #0 ; 0x0 + 3a54: e1a01003 mov r1, r3 + 3a58: ebf5fedb bl 0xffd835cc + 3a5c: 080c068a stmeqda ip, {r1, r3, r7, r9, sl} + 3a60: ebf60146 bl 0xffd83f80 + 3a64: 080c068a stmeqda ip, {r1, r3, r7, r9, sl} + 3a68: e1a01004 mov r1, r4 + 3a6c: e2944004 adds r4, r4, #4 ; 0x4 + 3a70: ebf60142 bl 0xffd83f80 + 3a74: 080c068c stmeqda ip, {r2, r3, r7, r9, sl} + 3a78: e3a00fca mov r0, #808 ; 0x328 + 3a7c: e3800b01 orr r0, r0, #1024 ; 0x400 + 3a80: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3a84: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3a88: ebf5ffa2 bl 0xffd83918 + 3a8c: 080c0690 stmeqda ip, {r4, r7, r9, sl} + 3a90: e1a03000 mov r3, r0 + 3a94: ebf60139 bl 0xffd83f80 + 3a98: 080c068e stmeqda ip, {r1, r2, r3, r7, r9, sl} + 3a9c: e2840000 add r0, r4, #0 ; 0x0 + 3aa0: e1a01003 mov r1, r3 + 3aa4: ebf5fec8 bl 0xffd835cc + 3aa8: 080c0690 stmeqda ip, {r4, r7, r9, sl} + 3aac: ebf60133 bl 0xffd83f80 + 3ab0: 080c0690 stmeqda ip, {r4, r7, r9, sl} + 3ab4: e288001c add r0, r8, #28 ; 0x1c + 3ab8: e59d1418 ldr r1, [sp, #1048] + 3abc: ebf5fec2 bl 0xffd835cc + 3ac0: 080c0692 stmeqda ip, {r1, r4, r7, r9, sl} + 3ac4: ebf6012d bl 0xffd83f80 + 3ac8: 080c0692 stmeqda ip, {r1, r4, r7, r9, sl} + 3acc: e3a00fcb mov r0, #812 ; 0x32c + 3ad0: e3800b01 orr r0, r0, #1024 ; 0x400 + 3ad4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3ad8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3adc: ebf5ff8d bl 0xffd83918 + 3ae0: 080c0696 stmeqda ip, {r1, r2, r4, r7, r9, sl} + 3ae4: e1a03000 mov r3, r0 + 3ae8: ebf60124 bl 0xffd83f80 + 3aec: 080c0694 stmeqda ip, {r2, r4, r7, r9, sl} + 3af0: e2880028 add r0, r8, #40 ; 0x28 + 3af4: e1a01003 mov r1, r3 + 3af8: ebf5feb3 bl 0xffd835cc + 3afc: 080c0696 stmeqda ip, {r1, r2, r4, r7, r9, sl} + 3b00: ebf6011e bl 0xffd83f80 + 3b04: 080c0696 stmeqda ip, {r1, r2, r4, r7, r9, sl} + 3b08: e3a00e73 mov r0, #1840 ; 0x730 + 3b0c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3b10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3b14: ebf5ff7f bl 0xffd83918 + 3b18: 080c069a stmeqda ip, {r1, r3, r4, r7, r9, sl} + 3b1c: e1a03000 mov r3, r0 + 3b20: ebf60116 bl 0xffd83f80 + 3b24: 080c0698 stmeqda ip, {r3, r4, r7, r9, sl} + 3b28: e288002c add r0, r8, #44 ; 0x2c + 3b2c: e1a01003 mov r1, r3 + 3b30: ebf5fea5 bl 0xffd835cc + 3b34: 080c069a stmeqda ip, {r1, r3, r4, r7, r9, sl} + 3b38: ebf60110 bl 0xffd83f80 + 3b3c: 080c069a stmeqda ip, {r1, r3, r4, r7, r9, sl} + 3b40: e3a00fcd mov r0, #820 ; 0x334 + 3b44: e3800b01 orr r0, r0, #1024 ; 0x400 + 3b48: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3b4c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3b50: ebf5ff70 bl 0xffd83918 + 3b54: 080c069e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl} + 3b58: e1a03000 mov r3, r0 + 3b5c: ebf60107 bl 0xffd83f80 + 3b60: 080c069c stmeqda ip, {r2, r3, r4, r7, r9, sl} + 3b64: e2880030 add r0, r8, #48 ; 0x30 + 3b68: e1a01003 mov r1, r3 + 3b6c: ebf5fe96 bl 0xffd835cc + 3b70: 080c069e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl} + 3b74: ebf60101 bl 0xffd83f80 + 3b78: 080c069e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl} + 3b7c: e2880034 add r0, r8, #52 ; 0x34 + 3b80: e1a01007 mov r1, r7 + 3b84: ebf5fe90 bl 0xffd835cc + 3b88: 080c06a0 stmeqda ip, {r5, r7, r9, sl} + 3b8c: ebf600fb bl 0xffd83f80 + 3b90: 080c06a0 stmeqda ip, {r5, r7, r9, sl} + 3b94: e3a00fce mov r0, #824 ; 0x338 + 3b98: e3800b01 orr r0, r0, #1024 ; 0x400 + 3b9c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3ba0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3ba4: ebf5ff5b bl 0xffd83918 + 3ba8: 080c06a4 stmeqda ip, {r2, r5, r7, r9, sl} + 3bac: e1a03000 mov r3, r0 + 3bb0: ebf600f2 bl 0xffd83f80 + 3bb4: 080c06a2 stmeqda ip, {r1, r5, r7, r9, sl} + 3bb8: e3b04000 movs r4, #0 ; 0x0 + 3bbc: ebf600ef bl 0xffd83f80 + 3bc0: 080c06a4 stmeqda ip, {r2, r5, r7, r9, sl} + 3bc4: e288000c add r0, r8, #12 ; 0xc + 3bc8: e1a01003 mov r1, r3 + 3bcc: ebf5fe3f bl 0xffd834d0 + 3bd0: 080c06a6 stmeqda ip, {r1, r2, r5, r7, r9, sl} + 3bd4: ebf600e9 bl 0xffd83f80 + 3bd8: 080c06a6 stmeqda ip, {r1, r2, r5, r7, r9, sl} + 3bdc: e59d0434 ldr r0, [sp, #1076] + 3be0: e2800f00 add r0, r0, #0 ; 0x0 + 3be4: e1a01004 mov r1, r4 + 3be8: ebf5fe77 bl 0xffd835cc + 3bec: 080c06a8 stmeqda ip, {r3, r5, r7, r9, sl} + 3bf0: ebf600e2 bl 0xffd83f80 + 3bf4: 080c06a8 stmeqda ip, {r3, r5, r7, r9, sl} + 3bf8: e3a00fcf mov r0, #828 ; 0x33c + 3bfc: e3800b01 orr r0, r0, #1024 ; 0x400 + 3c00: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3c04: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3c08: ebf5ff42 bl 0xffd83918 + 3c0c: 080c06ac stmeqda ip, {r2, r3, r5, r7, r9, sl} + 3c10: e1a05000 mov r5, r0 + 3c14: ebf600d9 bl 0xffd83f80 + 3c18: 080c06aa stmeqda ip, {r1, r3, r5, r7, r9, sl} + 3c1c: e59d1434 ldr r1, [sp, #1076] + 3c20: e1a03001 mov r3, r1 + 3c24: ebf600d5 bl 0xffd83f80 + 3c28: 080c06ac stmeqda ip, {r2, r3, r5, r7, r9, sl} + 3c2c: e59d1418 ldr r1, [sp, #1048] + 3c30: e59d1418 ldr r1, [sp, #1048] + 3c34: e2914000 adds r4, r1, #0 ; 0x0 + 3c38: ebf600d0 bl 0xffd83f80 + 3c3c: 080c06ae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl} + 3c40: ebf600ce bl 0xffd83f80 + 3c44: 080c06b0 stmeqda ip, {r4, r5, r7, r9, sl} + 3c48: e3a000b3 mov r0, #179 ; 0xb3 + 3c4c: e3800c06 orr r0, r0, #1536 ; 0x600 + 3c50: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3c54: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3c58: e58d0438 str r0, [sp, #1080] + 3c5c: e28cc09e add ip, ip, #158 ; 0x9e + 3c60: e1a00fac mov r0, ip, lsr #31 + 3c64: e08ff100 add pc, pc, r0, lsl #2 + 3c68: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 3c6c: ebf5fcb8 bl 0xffd82f54 + 3c70: eafff78c b 0x1aa8 + 3c74: 080c06b2 stmeqda ip, {r1, r4, r5, r7, r9, sl} + 3c78: 00000000 andeq r0, r0, r0 + 3c7c: ebf600bf bl 0xffd83f80 + 3c80: 080c06b2 stmeqda ip, {r1, r4, r5, r7, r9, sl} + 3c84: e3b03001 movs r3, #1 ; 0x1 + 3c88: ebf600bc bl 0xffd83f80 + 3c8c: 080c06b4 stmeqda ip, {r2, r4, r5, r7, r9, sl} + 3c90: e59d0418 ldr r0, [sp, #1048] + 3c94: e2800001 add r0, r0, #1 ; 0x1 + 3c98: e1a01003 mov r1, r3 + 3c9c: ebf5fe0b bl 0xffd834d0 + 3ca0: 080c06b6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl} + 3ca4: ebf600b5 bl 0xffd83f80 + 3ca8: 080c06b6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl} + 3cac: e3b03011 movs r3, #17 ; 0x11 + 3cb0: ebf600b2 bl 0xffd83f80 + 3cb4: 080c06b8 stmeqda ip, {r3, r4, r5, r7, r9, sl} + 3cb8: e59d0418 ldr r0, [sp, #1048] + 3cbc: e280001c add r0, r0, #28 ; 0x1c + 3cc0: e1a01003 mov r1, r3 + 3cc4: ebf5fe01 bl 0xffd834d0 + 3cc8: 080c06ba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl} + 3ccc: ebf600ab bl 0xffd83f80 + 3cd0: 080c06ba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl} + 3cd4: e59d1418 ldr r1, [sp, #1048] + 3cd8: e59d1418 ldr r1, [sp, #1048] + 3cdc: e2914000 adds r4, r1, #0 ; 0x0 + 3ce0: ebf600a6 bl 0xffd83f80 + 3ce4: 080c06bc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl} + 3ce8: e1a01004 mov r1, r4 + 3cec: e2944041 adds r4, r4, #65 ; 0x41 + 3cf0: ebf600a2 bl 0xffd83f80 + 3cf4: 080c06be stmeqda ip, {r1, r2, r3, r4, r5, r7, r9, sl} + 3cf8: e3b03002 movs r3, #2 ; 0x2 + 3cfc: ebf6009f bl 0xffd83f80 + 3d00: 080c06c0 stmeqda ip, {r6, r7, r9, sl} + 3d04: e2840000 add r0, r4, #0 ; 0x0 + 3d08: e1a01003 mov r1, r3 + 3d0c: ebf5fdef bl 0xffd834d0 + 3d10: 080c06c2 stmeqda ip, {r1, r6, r7, r9, sl} + 3d14: ebf60099 bl 0xffd83f80 + 3d18: 080c06c2 stmeqda ip, {r1, r6, r7, r9, sl} + 3d1c: e1a01004 mov r1, r4 + 3d20: e294401b adds r4, r4, #27 ; 0x1b + 3d24: ebf60095 bl 0xffd83f80 + 3d28: 080c06c4 stmeqda ip, {r2, r6, r7, r9, sl} + 3d2c: e3b03022 movs r3, #34 ; 0x22 + 3d30: ebf60092 bl 0xffd83f80 + 3d34: 080c06c6 stmeqda ip, {r1, r2, r6, r7, r9, sl} + 3d38: e2840000 add r0, r4, #0 ; 0x0 + 3d3c: e1a01003 mov r1, r3 + 3d40: ebf5fde2 bl 0xffd834d0 + 3d44: 080c06c8 stmeqda ip, {r3, r6, r7, r9, sl} + 3d48: ebf6008c bl 0xffd83f80 + 3d4c: 080c06c8 stmeqda ip, {r3, r6, r7, r9, sl} + 3d50: e1a01004 mov r1, r4 + 3d54: e2944025 adds r4, r4, #37 ; 0x25 + 3d58: ebf60088 bl 0xffd83f80 + 3d5c: 080c06ca stmeqda ip, {r1, r3, r6, r7, r9, sl} + 3d60: e3b03003 movs r3, #3 ; 0x3 + 3d64: ebf60085 bl 0xffd83f80 + 3d68: 080c06cc stmeqda ip, {r2, r3, r6, r7, r9, sl} + 3d6c: e2840000 add r0, r4, #0 ; 0x0 + 3d70: e1a01003 mov r1, r3 + 3d74: ebf5fdd5 bl 0xffd834d0 + 3d78: 080c06ce stmeqda ip, {r1, r2, r3, r6, r7, r9, sl} + 3d7c: ebf6007f bl 0xffd83f80 + 3d80: 080c06ce stmeqda ip, {r1, r2, r3, r6, r7, r9, sl} + 3d84: e1a01004 mov r1, r4 + 3d88: e294401b adds r4, r4, #27 ; 0x1b + 3d8c: ebf6007b bl 0xffd83f80 + 3d90: 080c06d0 stmeqda ip, {r4, r6, r7, r9, sl} + 3d94: e3b03044 movs r3, #68 ; 0x44 + 3d98: ebf60078 bl 0xffd83f80 + 3d9c: 080c06d2 stmeqda ip, {r1, r4, r6, r7, r9, sl} + 3da0: e2840000 add r0, r4, #0 ; 0x0 + 3da4: e1a01003 mov r1, r3 + 3da8: ebf5fdc8 bl 0xffd834d0 + 3dac: 080c06d4 stmeqda ip, {r2, r4, r6, r7, r9, sl} + 3db0: ebf60072 bl 0xffd83f80 + 3db4: 080c06d4 stmeqda ip, {r2, r4, r6, r7, r9, sl} + 3db8: e1a01004 mov r1, r4 + 3dbc: e2944024 adds r4, r4, #36 ; 0x24 + 3dc0: ebf6006e bl 0xffd83f80 + 3dc4: 080c06d6 stmeqda ip, {r1, r2, r4, r6, r7, r9, sl} + 3dc8: e3b03004 movs r3, #4 ; 0x4 + 3dcc: ebf6006b bl 0xffd83f80 + 3dd0: 080c06d8 stmeqda ip, {r3, r4, r6, r7, r9, sl} + 3dd4: e2840001 add r0, r4, #1 ; 0x1 + 3dd8: e1a01003 mov r1, r3 + 3ddc: ebf5fdbb bl 0xffd834d0 + 3de0: 080c06da stmeqda ip, {r1, r3, r4, r6, r7, r9, sl} + 3de4: ebf60065 bl 0xffd83f80 + 3de8: 080c06da stmeqda ip, {r1, r3, r4, r6, r7, r9, sl} + 3dec: e3b03088 movs r3, #136 ; 0x88 + 3df0: ebf60062 bl 0xffd83f80 + 3df4: 080c06dc stmeqda ip, {r2, r3, r4, r6, r7, r9, sl} + 3df8: e284001c add r0, r4, #28 ; 0x1c + 3dfc: e1a01003 mov r1, r3 + 3e00: ebf5fdb2 bl 0xffd834d0 + 3e04: 080c06de stmeqda ip, {r1, r2, r3, r4, r6, r7, r9, sl} + 3e08: ebf6005c bl 0xffd83f80 + 3e0c: 080c06de stmeqda ip, {r1, r2, r3, r4, r6, r7, r9, sl} + 3e10: e2880000 add r0, r8, #0 ; 0x0 + 3e14: e59d141c ldr r1, [sp, #1052] + 3e18: ebf5fdeb bl 0xffd835cc + 3e1c: 080c06e0 stmeqda ip, {r5, r6, r7, r9, sl} + 3e20: ebf60056 bl 0xffd83f80 + 3e24: 080c06e0 stmeqda ip, {r5, r6, r7, r9, sl} + 3e28: e59d0434 ldr r0, [sp, #1076] + 3e2c: e2800f01 add r0, r0, #4 ; 0x4 + 3e30: e58d0434 str r0, [sp, #1076] + 3e34: ebf60051 bl 0xffd83f80 + 3e38: 080c06e2 stmeqda ip, {r1, r5, r6, r7, r9, sl} + 3e3c: e59d9434 ldr r9, [sp, #1076] + 3e40: e3c99003 bic r9, r9, #3 ; 0x3 + 3e44: e2890010 add r0, r9, #16 ; 0x10 + 3e48: e58d0434 str r0, [sp, #1076] + 3e4c: e2890000 add r0, r9, #0 ; 0x0 + 3e50: ebf5feb0 bl 0xffd83918 + 3e54: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 3e58: e1a07000 mov r7, r0 + 3e5c: e2890004 add r0, r9, #4 ; 0x4 + 3e60: ebf5feac bl 0xffd83918 + 3e64: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 3e68: e1a08000 mov r8, r0 + 3e6c: e2890008 add r0, r9, #8 ; 0x8 + 3e70: ebf5fea8 bl 0xffd83918 + 3e74: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 3e78: e58d0418 str r0, [sp, #1048] + 3e7c: e289000c add r0, r9, #12 ; 0xc + 3e80: ebf5fea4 bl 0xffd83918 + 3e84: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 3e88: e58d041c str r0, [sp, #1052] + 3e8c: ebf6003b bl 0xffd83f80 + 3e90: 080c06e4 stmeqda ip, {r2, r5, r6, r7, r9, sl} + 3e94: e59d9434 ldr r9, [sp, #1076] + 3e98: e3c99003 bic r9, r9, #3 ; 0x3 + 3e9c: e2890004 add r0, r9, #4 ; 0x4 + 3ea0: e58d0434 str r0, [sp, #1076] + 3ea4: e2890000 add r0, r9, #0 ; 0x0 + 3ea8: ebf5fe9a bl 0xffd83918 + 3eac: 080c06e8 stmeqda ip, {r3, r5, r6, r7, r9, sl} + 3eb0: e1a03000 mov r3, r0 + 3eb4: ebf60031 bl 0xffd83f80 + 3eb8: 080c06e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl} + 3ebc: e1a00003 mov r0, r3 + 3ec0: e28cc05f add ip, ip, #95 ; 0x5f + 3ec4: eaf5fc81 b 0xffd830d0 + 3ec8: 080c03c6 stmeqda ip, {r1, r2, r6, r7, r8, r9} + 3ecc: 00000000 andeq r0, r0, r0 + 3ed0: ebf6002a bl 0xffd83f80 + 3ed4: 080c03c6 stmeqda ip, {r1, r2, r6, r7, r8, r9} + 3ed8: e3a00e42 mov r0, #1056 ; 0x420 + 3edc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3ee0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3ee4: ebf5fe8b bl 0xffd83918 + 3ee8: 080c03ca stmeqda ip, {r1, r3, r6, r7, r8, r9} + 3eec: e1a03000 mov r3, r0 + 3ef0: ebf60022 bl 0xffd83f80 + 3ef4: 080c03c8 stmeqda ip, {r3, r6, r7, r8, r9} + 3ef8: ebf60020 bl 0xffd83f80 + 3efc: 080c03ca stmeqda ip, {r1, r3, r6, r7, r8, r9} + 3f00: e3a000cd mov r0, #205 ; 0xcd + 3f04: e3800c03 orr r0, r0, #768 ; 0x300 + 3f08: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3f0c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3f10: e58d0438 str r0, [sp, #1080] + 3f14: e28cc00b add ip, ip, #11 ; 0xb + 3f18: e1a00fac mov r0, ip, lsr #31 + 3f1c: e08ff100 add pc, pc, r0, lsl #2 + 3f20: 080c08d0 stmeqda ip, {r4, r6, r7, fp} + 3f24: ebf5fc0a bl 0xffd82f54 + 3f28: ea000001 b 0x3f34 + 3f2c: 080c08d0 stmeqda ip, {r4, r6, r7, fp} + 3f30: 00000000 andeq r0, r0, r0 + 3f34: ebf60011 bl 0xffd83f80 + 3f38: 080c08d0 stmeqda ip, {r4, r6, r7, fp} + 3f3c: e59d9434 ldr r9, [sp, #1076] + 3f40: e3c99003 bic r9, r9, #3 ; 0x3 + 3f44: e249900c sub r9, r9, #12 ; 0xc + 3f48: e58d9434 str r9, [sp, #1076] + 3f4c: e2890000 add r0, r9, #0 ; 0x0 + 3f50: e1a01007 mov r1, r7 + 3f54: ebf5fdbc bl 0xffd8364c + 3f58: e2890004 add r0, r9, #4 ; 0x4 + 3f5c: e1a01008 mov r1, r8 + 3f60: ebf5fdb9 bl 0xffd8364c + 3f64: e2890008 add r0, r9, #8 ; 0x8 + 3f68: e59d1438 ldr r1, [sp, #1080] + 3f6c: ebf5fdb6 bl 0xffd8364c + 3f70: ebf60002 bl 0xffd83f80 + 3f74: 080c08d2 stmeqda ip, {r1, r4, r6, r7, fp} + 3f78: e1a01003 mov r1, r3 + 3f7c: e2936000 adds r6, r3, #0 ; 0x0 + 3f80: ebf5fffe bl 0xffd83f80 + 3f84: 080c08d4 stmeqda ip, {r2, r4, r6, r7, fp} + 3f88: e3a00f57 mov r0, #348 ; 0x15c + 3f8c: e3800b02 orr r0, r0, #2048 ; 0x800 + 3f90: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3f94: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3f98: ebf5fe5e bl 0xffd83918 + 3f9c: 080c08d8 stmeqda ip, {r3, r4, r6, r7, fp} + 3fa0: e1a03000 mov r3, r0 + 3fa4: ebf5fff5 bl 0xffd83f80 + 3fa8: 080c08d6 stmeqda ip, {r1, r2, r4, r6, r7, fp} + 3fac: e2830000 add r0, r3, #0 ; 0x0 + 3fb0: ebf5fe58 bl 0xffd83918 + 3fb4: 080c08da stmeqda ip, {r1, r3, r4, r6, r7, fp} + 3fb8: e1a08000 mov r8, r0 + 3fbc: ebf5ffef bl 0xffd83f80 + 3fc0: 080c08d8 stmeqda ip, {r3, r4, r6, r7, fp} + 3fc4: e2880000 add r0, r8, #0 ; 0x0 + 3fc8: ebf5fe52 bl 0xffd83918 + 3fcc: 080c08dc stmeqda ip, {r2, r3, r4, r6, r7, fp} + 3fd0: e1a04000 mov r4, r0 + 3fd4: ebf5ffe9 bl 0xffd83f80 + 3fd8: 080c08da stmeqda ip, {r1, r3, r4, r6, r7, fp} + 3fdc: e3a00e96 mov r0, #2400 ; 0x960 + 3fe0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 3fe4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 3fe8: ebf5fe4a bl 0xffd83918 + 3fec: 080c08de stmeqda ip, {r1, r2, r3, r4, r6, r7, fp} + 3ff0: e1a03000 mov r3, r0 + 3ff4: ebf5ffe1 bl 0xffd83f80 + 3ff8: 080c08dc stmeqda ip, {r2, r3, r4, r6, r7, fp} + 3ffc: e1540003 cmp r4, r3 + 4000: ebf5ffde bl 0xffd83f80 + 4004: 080c08de stmeqda ip, {r1, r2, r3, r4, r6, r7, fp} + 4008: e28cc022 add ip, ip, #34 ; 0x22 + 400c: 0a000004 beq 0x4024 + 4010: e1a00fac mov r0, ip, lsr #31 + 4014: e08ff100 add pc, pc, r0, lsl #2 + 4018: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 401c: ebf5fbcc bl 0xffd82f54 + 4020: ea0000fe b 0x4420 + 4024: ebf5ffd5 bl 0xffd83f80 + 4028: 080c08e0 stmeqda ip, {r5, r6, r7, fp} + 402c: e1a01004 mov r1, r4 + 4030: e2943001 adds r3, r4, #1 ; 0x1 + 4034: ebf5ffd1 bl 0xffd83f80 + 4038: 080c08e2 stmeqda ip, {r1, r5, r6, r7, fp} + 403c: e2880000 add r0, r8, #0 ; 0x0 + 4040: e1a01003 mov r1, r3 + 4044: ebf5fd60 bl 0xffd835cc + 4048: 080c08e4 stmeqda ip, {r2, r5, r6, r7, fp} + 404c: ebf5ffcb bl 0xffd83f80 + 4050: 080c08e4 stmeqda ip, {r2, r5, r6, r7, fp} + 4054: e3b070ff movs r7, #255 ; 0xff + 4058: ebf5ffc8 bl 0xffd83f80 + 405c: 080c08e6 stmeqda ip, {r1, r2, r5, r6, r7, fp} + 4060: e1a01007 mov r1, r7 + 4064: e0177006 ands r7, r7, r6 + 4068: ebf5ffc4 bl 0xffd83f80 + 406c: 080c08e8 stmeqda ip, {r3, r5, r6, r7, fp} + 4070: e3570000 cmp r7, #0 ; 0x0 + 4074: ebf5ffc1 bl 0xffd83f80 + 4078: 080c08ea stmeqda ip, {r1, r3, r5, r6, r7, fp} + 407c: e28cc013 add ip, ip, #19 ; 0x13 + 4080: 1a000004 bne 0x4098 + 4084: e1a00fac mov r0, ip, lsr #31 + 4088: e08ff100 add pc, pc, r0, lsl #2 + 408c: 080c08f2 stmeqda ip, {r1, r4, r5, r6, r7, fp} + 4090: ebf5fbaf bl 0xffd82f54 + 4094: ea00000d b 0x40d0 + 4098: ebf5ffb8 bl 0xffd83f80 + 409c: 080c08ec stmeqda ip, {r2, r3, r5, r6, r7, fp} + 40a0: e3b0307f movs r3, #127 ; 0x7f + 40a4: ebf5ffb5 bl 0xffd83f80 + 40a8: 080c08ee stmeqda ip, {r1, r2, r3, r5, r6, r7, fp} + 40ac: e1a01007 mov r1, r7 + 40b0: e0177003 ands r7, r7, r3 + 40b4: ebf5ffb1 bl 0xffd83f80 + 40b8: 080c08f0 stmeqda ip, {r4, r5, r6, r7, fp} + 40bc: e2880005 add r0, r8, #5 ; 0x5 + 40c0: e1a01007 mov r1, r7 + 40c4: ebf5fd01 bl 0xffd834d0 + 40c8: 080c08f2 stmeqda ip, {r1, r4, r5, r6, r7, fp} + 40cc: e28cc00a add ip, ip, #10 ; 0xa + 40d0: ebf5ffaa bl 0xffd83f80 + 40d4: 080c08f2 stmeqda ip, {r1, r4, r5, r6, r7, fp} + 40d8: e3b070f0 movs r7, #240 ; 0xf0 + 40dc: ebf5ffa7 bl 0xffd83f80 + 40e0: 080c08f4 stmeqda ip, {r2, r4, r5, r6, r7, fp} + 40e4: e1b07207 movs r7, r7, lsl #4 + 40e8: ebf5ffa4 bl 0xffd83f80 + 40ec: 080c08f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, fp} + 40f0: e1a01007 mov r1, r7 + 40f4: e0177006 ands r7, r7, r6 + 40f8: ebf5ffa0 bl 0xffd83f80 + 40fc: 080c08f8 stmeqda ip, {r3, r4, r5, r6, r7, fp} + 4100: e3570000 cmp r7, #0 ; 0x0 + 4104: ebf5ff9d bl 0xffd83f80 + 4108: 080c08fa stmeqda ip, {r1, r3, r4, r5, r6, r7, fp} + 410c: e28cc00f add ip, ip, #15 ; 0xf + 4110: 1a000004 bne 0x4128 + 4114: e1a00fac mov r0, ip, lsr #31 + 4118: e08ff100 add pc, pc, r0, lsl #2 + 411c: 080c0912 stmeqda ip, {r1, r4, r8, fp} + 4120: ebf5fb8b bl 0xffd82f54 + 4124: ea000031 b 0x41f0 + 4128: ebf5ff94 bl 0xffd83f80 + 412c: 080c08fc stmeqda ip, {r2, r3, r4, r5, r6, r7, fp} + 4130: e1b03427 movs r3, r7, lsr #8 + 4134: ebf5ff91 bl 0xffd83f80 + 4138: 080c08fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, fp} + 413c: e2880006 add r0, r8, #6 ; 0x6 + 4140: e1a01003 mov r1, r3 + 4144: ebf5fce1 bl 0xffd834d0 + 4148: 080c0900 stmeqda ip, {r8, fp} + 414c: ebf5ff8b bl 0xffd83f80 + 4150: 080c0900 stmeqda ip, {r8, fp} + 4154: e3b0700c movs r7, #12 ; 0xc + 4158: ebf5ff88 bl 0xffd83f80 + 415c: 080c0902 stmeqda ip, {r1, r8, fp} + 4160: e1a01008 mov r1, r8 + 4164: e2983000 adds r3, r8, #0 ; 0x0 + 4168: ebf5ff84 bl 0xffd83f80 + 416c: 080c0904 stmeqda ip, {r2, r8, fp} + 4170: e1a01003 mov r1, r3 + 4174: e2933050 adds r3, r3, #80 ; 0x50 + 4178: ebf5ff80 bl 0xffd83f80 + 417c: 080c0906 stmeqda ip, {r1, r2, r8, fp} + 4180: e3b04000 movs r4, #0 ; 0x0 + 4184: e28cc013 add ip, ip, #19 ; 0x13 + 4188: ebf5ff7c bl 0xffd83f80 + 418c: 080c0908 stmeqda ip, {r3, r8, fp} + 4190: e2830000 add r0, r3, #0 ; 0x0 + 4194: e1a01004 mov r1, r4 + 4198: ebf5fccc bl 0xffd834d0 + 419c: 080c090a stmeqda ip, {r1, r3, r8, fp} + 41a0: ebf5ff76 bl 0xffd83f80 + 41a4: 080c090a stmeqda ip, {r1, r3, r8, fp} + 41a8: e1a01007 mov r1, r7 + 41ac: e2577001 subs r7, r7, #1 ; 0x1 + 41b0: ebf5ff72 bl 0xffd83f80 + 41b4: 080c090c stmeqda ip, {r2, r3, r8, fp} + 41b8: e1a01003 mov r1, r3 + 41bc: e2933040 adds r3, r3, #64 ; 0x40 + 41c0: ebf5ff6e bl 0xffd83f80 + 41c4: 080c090e stmeqda ip, {r1, r2, r3, r8, fp} + 41c8: e3570000 cmp r7, #0 ; 0x0 + 41cc: ebf5ff6b bl 0xffd83f80 + 41d0: 080c0910 stmeqda ip, {r4, r8, fp} + 41d4: e28cc010 add ip, ip, #16 ; 0x10 + 41d8: 0a000004 beq 0x41f0 + 41dc: e1a00fac mov r0, ip, lsr #31 + 41e0: e08ff100 add pc, pc, r0, lsl #2 + 41e4: 080c0908 stmeqda ip, {r3, r8, fp} + 41e8: ebf5fb59 bl 0xffd82f54 + 41ec: eaffffe5 b 0x4188 + 41f0: ebf5ff62 bl 0xffd83f80 + 41f4: 080c0912 stmeqda ip, {r1, r4, r8, fp} + 41f8: e3b070f0 movs r7, #240 ; 0xf0 + 41fc: ebf5ff5f bl 0xffd83f80 + 4200: 080c0914 stmeqda ip, {r2, r4, r8, fp} + 4204: e1b07407 movs r7, r7, lsl #8 + 4208: ebf5ff5c bl 0xffd83f80 + 420c: 080c0916 stmeqda ip, {r1, r2, r4, r8, fp} + 4210: e1a01007 mov r1, r7 + 4214: e0177006 ands r7, r7, r6 + 4218: ebf5ff58 bl 0xffd83f80 + 421c: 080c0918 stmeqda ip, {r3, r4, r8, fp} + 4220: e3570000 cmp r7, #0 ; 0x0 + 4224: ebf5ff55 bl 0xffd83f80 + 4228: 080c091a stmeqda ip, {r1, r3, r4, r8, fp} + 422c: e28cc00f add ip, ip, #15 ; 0xf + 4230: 1a000004 bne 0x4248 + 4234: e1a00fac mov r0, ip, lsr #31 + 4238: e08ff100 add pc, pc, r0, lsl #2 + 423c: 080c0920 stmeqda ip, {r5, r8, fp} + 4240: ebf5fb43 bl 0xffd82f54 + 4244: ea000009 b 0x4270 + 4248: ebf5ff4c bl 0xffd83f80 + 424c: 080c091c stmeqda ip, {r2, r3, r4, r8, fp} + 4250: e1b03627 movs r3, r7, lsr #12 + 4254: ebf5ff49 bl 0xffd83f80 + 4258: 080c091e stmeqda ip, {r1, r2, r3, r4, r8, fp} + 425c: e2880007 add r0, r8, #7 ; 0x7 + 4260: e1a01003 mov r1, r3 + 4264: ebf5fc99 bl 0xffd834d0 + 4268: 080c0920 stmeqda ip, {r5, r8, fp} + 426c: e28cc007 add ip, ip, #7 ; 0x7 + 4270: ebf5ff42 bl 0xffd83f80 + 4274: 080c0920 stmeqda ip, {r5, r8, fp} + 4278: e3b070b0 movs r7, #176 ; 0xb0 + 427c: ebf5ff3f bl 0xffd83f80 + 4280: 080c0922 stmeqda ip, {r1, r5, r8, fp} + 4284: e1b07807 movs r7, r7, lsl #16 + 4288: ebf5ff3c bl 0xffd83f80 + 428c: 080c0924 stmeqda ip, {r2, r5, r8, fp} + 4290: e1a01007 mov r1, r7 + 4294: e0177006 ands r7, r7, r6 + 4298: ebf5ff38 bl 0xffd83f80 + 429c: 080c0926 stmeqda ip, {r1, r2, r5, r8, fp} + 42a0: e3570000 cmp r7, #0 ; 0x0 + 42a4: ebf5ff35 bl 0xffd83f80 + 42a8: 080c0928 stmeqda ip, {r3, r5, r8, fp} + 42ac: e28cc00f add ip, ip, #15 ; 0xf + 42b0: 1a000004 bne 0x42c8 + 42b4: e1a00fac mov r0, ip, lsr #31 + 42b8: e08ff100 add pc, pc, r0, lsl #2 + 42bc: 080c093e stmeqda ip, {r1, r2, r3, r4, r5, r8, fp} + 42c0: ebf5fb23 bl 0xffd82f54 + 42c4: ea00002d b 0x4380 + 42c8: ebf5ff2c bl 0xffd83f80 + 42cc: 080c092a stmeqda ip, {r1, r3, r5, r8, fp} + 42d0: e3b030c0 movs r3, #192 ; 0xc0 + 42d4: ebf5ff29 bl 0xffd83f80 + 42d8: 080c092c stmeqda ip, {r2, r3, r5, r8, fp} + 42dc: e1b03703 movs r3, r3, lsl #14 + 42e0: ebf5ff26 bl 0xffd83f80 + 42e4: 080c092e stmeqda ip, {r1, r2, r3, r5, r8, fp} + 42e8: e1a01003 mov r1, r3 + 42ec: e0133007 ands r3, r3, r7 + 42f0: ebf5ff22 bl 0xffd83f80 + 42f4: 080c0930 stmeqda ip, {r4, r5, r8, fp} + 42f8: e1b07723 movs r7, r3, lsr #14 + 42fc: ebf5ff1f bl 0xffd83f80 + 4300: 080c0932 stmeqda ip, {r1, r4, r5, r8, fp} + 4304: e3a00f59 mov r0, #356 ; 0x164 + 4308: e3800b02 orr r0, r0, #2048 ; 0x800 + 430c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4310: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4314: ebf5fd7f bl 0xffd83918 + 4318: 080c0936 stmeqda ip, {r1, r2, r4, r5, r8, fp} + 431c: e1a05000 mov r5, r0 + 4320: ebf5ff16 bl 0xffd83f80 + 4324: 080c0934 stmeqda ip, {r2, r4, r5, r8, fp} + 4328: e2850000 add r0, r5, #0 ; 0x0 + 432c: ebf5fd22 bl 0xffd837bc + 4330: 080c0938 stmeqda ip, {r3, r4, r5, r8, fp} + 4334: e1a04000 mov r4, r0 + 4338: ebf5ff10 bl 0xffd83f80 + 433c: 080c0936 stmeqda ip, {r1, r2, r4, r5, r8, fp} + 4340: e3b0303f movs r3, #63 ; 0x3f + 4344: ebf5ff0d bl 0xffd83f80 + 4348: 080c0938 stmeqda ip, {r3, r4, r5, r8, fp} + 434c: e1a01003 mov r1, r3 + 4350: e0133004 ands r3, r3, r4 + 4354: ebf5ff09 bl 0xffd83f80 + 4358: 080c093a stmeqda ip, {r1, r3, r4, r5, r8, fp} + 435c: e1a01003 mov r1, r3 + 4360: e1933007 orrs r3, r3, r7 + 4364: ebf5ff05 bl 0xffd83f80 + 4368: 080c093c stmeqda ip, {r2, r3, r4, r5, r8, fp} + 436c: e2850000 add r0, r5, #0 ; 0x0 + 4370: e1a01003 mov r1, r3 + 4374: ebf5fc55 bl 0xffd834d0 + 4378: 080c093e stmeqda ip, {r1, r2, r3, r4, r5, r8, fp} + 437c: e28cc023 add ip, ip, #35 ; 0x23 + 4380: ebf5fefe bl 0xffd83f80 + 4384: 080c093e stmeqda ip, {r1, r2, r3, r4, r5, r8, fp} + 4388: e3b070f0 movs r7, #240 ; 0xf0 + 438c: ebf5fefb bl 0xffd83f80 + 4390: 080c0940 stmeqda ip, {r6, r8, fp} + 4394: e1b07607 movs r7, r7, lsl #12 + 4398: ebf5fef8 bl 0xffd83f80 + 439c: 080c0942 stmeqda ip, {r1, r6, r8, fp} + 43a0: e1a01007 mov r1, r7 + 43a4: e0177006 ands r7, r7, r6 + 43a8: ebf5fef4 bl 0xffd83f80 + 43ac: 080c0944 stmeqda ip, {r2, r6, r8, fp} + 43b0: e3570000 cmp r7, #0 ; 0x0 + 43b4: ebf5fef1 bl 0xffd83f80 + 43b8: 080c0946 stmeqda ip, {r1, r2, r6, r8, fp} + 43bc: e28cc00f add ip, ip, #15 ; 0xf + 43c0: 1a000004 bne 0x43d8 + 43c4: e1a00fac mov r0, ip, lsr #31 + 43c8: e08ff100 add pc, pc, r0, lsl #2 + 43cc: 080c0952 stmeqda ip, {r1, r4, r6, r8, fp} + 43d0: ebf5fadf bl 0xffd82f54 + 43d4: ea000030 b 0x449c + 43d8: ebf5fee8 bl 0xffd83f80 + 43dc: 080c0948 stmeqda ip, {r3, r6, r8, fp} + 43e0: e28cc003 add ip, ip, #3 ; 0x3 + 43e4: ebf5fee5 bl 0xffd83f80 + 43e8: 080c094a stmeqda ip, {r1, r3, r6, r8, fp} + 43ec: e3a0004d mov r0, #77 ; 0x4d + 43f0: e3800c09 orr r0, r0, #2304 ; 0x900 + 43f4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 43f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 43fc: e58d0438 str r0, [sp, #1080] + 4400: e28cc003 add ip, ip, #3 ; 0x3 + 4404: e1a00fac mov r0, ip, lsr #31 + 4408: e08ff100 add pc, pc, r0, lsl #2 + 440c: 080c09bc stmeqda ip, {r2, r3, r4, r5, r7, r8, fp} + 4410: ebf5facf bl 0xffd82f54 + 4414: ea00004d b 0x4550 + 4418: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 441c: 00000000 andeq r0, r0, r0 + 4420: ebf5fed6 bl 0xffd83f80 + 4424: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 4428: e59d9434 ldr r9, [sp, #1076] + 442c: e3c99003 bic r9, r9, #3 ; 0x3 + 4430: e2890008 add r0, r9, #8 ; 0x8 + 4434: e58d0434 str r0, [sp, #1076] + 4438: e2890000 add r0, r9, #0 ; 0x0 + 443c: ebf5fd35 bl 0xffd83918 + 4440: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 4444: e1a07000 mov r7, r0 + 4448: e2890004 add r0, r9, #4 ; 0x4 + 444c: ebf5fd31 bl 0xffd83918 + 4450: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 4454: e1a08000 mov r8, r0 + 4458: ebf5fec8 bl 0xffd83f80 + 445c: 080c0958 stmeqda ip, {r3, r4, r6, r8, fp} + 4460: e59d9434 ldr r9, [sp, #1076] + 4464: e3c99003 bic r9, r9, #3 ; 0x3 + 4468: e2890004 add r0, r9, #4 ; 0x4 + 446c: e58d0434 str r0, [sp, #1076] + 4470: e2890000 add r0, r9, #0 ; 0x0 + 4474: ebf5fd27 bl 0xffd83918 + 4478: 080c095c stmeqda ip, {r2, r3, r4, r6, r8, fp} + 447c: e1a03000 mov r3, r0 + 4480: ebf5febe bl 0xffd83f80 + 4484: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 4488: e1a00003 mov r0, r3 + 448c: e28cc00c add ip, ip, #12 ; 0xc + 4490: eaf5fb0e b 0xffd830d0 + 4494: 080c0952 stmeqda ip, {r1, r4, r6, r8, fp} + 4498: 00000000 andeq r0, r0, r0 + 449c: ebf5feb7 bl 0xffd83f80 + 44a0: 080c0952 stmeqda ip, {r1, r4, r6, r8, fp} + 44a4: e3a00e96 mov r0, #2400 ; 0x960 + 44a8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 44ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 44b0: ebf5fd18 bl 0xffd83918 + 44b4: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 44b8: e1a03000 mov r3, r0 + 44bc: ebf5feaf bl 0xffd83f80 + 44c0: 080c0954 stmeqda ip, {r2, r4, r6, r8, fp} + 44c4: e2880000 add r0, r8, #0 ; 0x0 + 44c8: e1a01003 mov r1, r3 + 44cc: ebf5fc3e bl 0xffd835cc + 44d0: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 44d4: ebf5fea9 bl 0xffd83f80 + 44d8: 080c0956 stmeqda ip, {r1, r2, r4, r6, r8, fp} + 44dc: e59d9434 ldr r9, [sp, #1076] + 44e0: e3c99003 bic r9, r9, #3 ; 0x3 + 44e4: e2890008 add r0, r9, #8 ; 0x8 + 44e8: e58d0434 str r0, [sp, #1076] + 44ec: e2890000 add r0, r9, #0 ; 0x0 + 44f0: ebf5fd08 bl 0xffd83918 + 44f4: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 44f8: e1a07000 mov r7, r0 + 44fc: e2890004 add r0, r9, #4 ; 0x4 + 4500: ebf5fd04 bl 0xffd83918 + 4504: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 4508: e1a08000 mov r8, r0 + 450c: ebf5fe9b bl 0xffd83f80 + 4510: 080c0958 stmeqda ip, {r3, r4, r6, r8, fp} + 4514: e59d9434 ldr r9, [sp, #1076] + 4518: e3c99003 bic r9, r9, #3 ; 0x3 + 451c: e2890004 add r0, r9, #4 ; 0x4 + 4520: e58d0434 str r0, [sp, #1076] + 4524: e2890000 add r0, r9, #0 ; 0x0 + 4528: ebf5fcfa bl 0xffd83918 + 452c: 080c095c stmeqda ip, {r2, r3, r4, r6, r8, fp} + 4530: e1a03000 mov r3, r0 + 4534: ebf5fe91 bl 0xffd83f80 + 4538: 080c095a stmeqda ip, {r1, r3, r4, r6, r8, fp} + 453c: e1a00003 mov r0, r3 + 4540: e28cc015 add ip, ip, #21 ; 0x15 + 4544: eaf5fae1 b 0xffd830d0 + 4548: 080c09bc stmeqda ip, {r2, r3, r4, r5, r7, r8, fp} + 454c: 00000000 andeq r0, r0, r0 + 4550: ebf5fe8a bl 0xffd83f80 + 4554: 080c09bc stmeqda ip, {r2, r3, r4, r5, r7, r8, fp} + 4558: e59d9434 ldr r9, [sp, #1076] + 455c: e3c99003 bic r9, r9, #3 ; 0x3 + 4560: e2499004 sub r9, r9, #4 ; 0x4 + 4564: e58d9434 str r9, [sp, #1076] + 4568: e2890000 add r0, r9, #0 ; 0x0 + 456c: e59d1438 ldr r1, [sp, #1080] + 4570: ebf5fc35 bl 0xffd8364c + 4574: ebf5fe81 bl 0xffd83f80 + 4578: 080c09be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, fp} + 457c: e59d0434 ldr r0, [sp, #1076] + 4580: e2400f01 sub r0, r0, #4 ; 0x4 + 4584: e58d0434 str r0, [sp, #1076] + 4588: ebf5fe7c bl 0xffd83f80 + 458c: 080c09c0 stmeqda ip, {r6, r7, r8, fp} + 4590: e3a00f7e mov r0, #504 ; 0x1f8 + 4594: e3800b02 orr r0, r0, #2048 ; 0x800 + 4598: e3800703 orr r0, r0, #786432 ; 0xc0000 + 459c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 45a0: ebf5fcdc bl 0xffd83918 + 45a4: 080c09c4 stmeqda ip, {r2, r6, r7, r8, fp} + 45a8: e1a03000 mov r3, r0 + 45ac: ebf5fe73 bl 0xffd83f80 + 45b0: 080c09c2 stmeqda ip, {r1, r6, r7, r8, fp} + 45b4: e2830000 add r0, r3, #0 ; 0x0 + 45b8: ebf5fcd6 bl 0xffd83918 + 45bc: 080c09c6 stmeqda ip, {r1, r2, r6, r7, r8, fp} + 45c0: e1a05000 mov r5, r0 + 45c4: ebf5fe6d bl 0xffd83f80 + 45c8: 080c09c4 stmeqda ip, {r2, r6, r7, r8, fp} + 45cc: e2850000 add r0, r5, #0 ; 0x0 + 45d0: ebf5fcd0 bl 0xffd83918 + 45d4: 080c09c8 stmeqda ip, {r3, r6, r7, r8, fp} + 45d8: e1a04000 mov r4, r0 + 45dc: ebf5fe67 bl 0xffd83f80 + 45e0: 080c09c6 stmeqda ip, {r1, r2, r6, r7, r8, fp} + 45e4: e3a00f7f mov r0, #508 ; 0x1fc + 45e8: e3800b02 orr r0, r0, #2048 ; 0x800 + 45ec: e3800703 orr r0, r0, #786432 ; 0xc0000 + 45f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 45f4: ebf5fcc7 bl 0xffd83918 + 45f8: 080c09ca stmeqda ip, {r1, r3, r6, r7, r8, fp} + 45fc: e1a06000 mov r6, r0 + 4600: ebf5fe5e bl 0xffd83f80 + 4604: 080c09c8 stmeqda ip, {r3, r6, r7, r8, fp} + 4608: e1a01004 mov r1, r4 + 460c: e0943006 adds r3, r4, r6 + 4610: ebf5fe5a bl 0xffd83f80 + 4614: 080c09ca stmeqda ip, {r1, r3, r6, r7, r8, fp} + 4618: e3530001 cmp r3, #1 ; 0x1 + 461c: ebf5fe57 bl 0xffd83f80 + 4620: 080c09cc stmeqda ip, {r2, r3, r6, r7, r8, fp} + 4624: e28cc023 add ip, ip, #35 ; 0x23 + 4628: 9a000004 bls 0x4640 + 462c: e1a00fac mov r0, ip, lsr #31 + 4630: e08ff100 add pc, pc, r0, lsl #2 + 4634: 080c09f0 stmeqda ip, {r4, r5, r6, r7, r8, fp} + 4638: ebf5fa45 bl 0xffd82f54 + 463c: ea000058 b 0x47a4 + 4640: ebf5fe4e bl 0xffd83f80 + 4644: 080c09ce stmeqda ip, {r1, r2, r3, r6, r7, r8, fp} + 4648: e1a01004 mov r1, r4 + 464c: e2943000 adds r3, r4, #0 ; 0x0 + 4650: ebf5fe4a bl 0xffd83f80 + 4654: 080c09d0 stmeqda ip, {r4, r6, r7, r8, fp} + 4658: e1a01003 mov r1, r3 + 465c: e293300a adds r3, r3, #10 ; 0xa + 4660: ebf5fe46 bl 0xffd83f80 + 4664: 080c09d2 stmeqda ip, {r1, r4, r6, r7, r8, fp} + 4668: e2850000 add r0, r5, #0 ; 0x0 + 466c: e1a01003 mov r1, r3 + 4670: ebf5fbd5 bl 0xffd835cc + 4674: 080c09d4 stmeqda ip, {r2, r4, r6, r7, r8, fp} + 4678: ebf5fe40 bl 0xffd83f80 + 467c: 080c09d4 stmeqda ip, {r2, r4, r6, r7, r8, fp} + 4680: e3a00c0a mov r0, #2560 ; 0xa00 + 4684: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4688: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 468c: ebf5fca1 bl 0xffd83918 + 4690: 080c09d8 stmeqda ip, {r3, r4, r6, r7, r8, fp} + 4694: e1a03000 mov r3, r0 + 4698: ebf5fe38 bl 0xffd83f80 + 469c: 080c09d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, fp} + 46a0: e3b04000 movs r4, #0 ; 0x0 + 46a4: ebf5fe35 bl 0xffd83f80 + 46a8: 080c09d8 stmeqda ip, {r3, r4, r6, r7, r8, fp} + 46ac: e2830000 add r0, r3, #0 ; 0x0 + 46b0: e1a01004 mov r1, r4 + 46b4: ebf5fba4 bl 0xffd8354c + 46b8: 080c09da stmeqda ip, {r1, r3, r4, r6, r7, r8, fp} + 46bc: ebf5fe2f bl 0xffd83f80 + 46c0: 080c09da stmeqda ip, {r1, r3, r4, r6, r7, r8, fp} + 46c4: e1a01003 mov r1, r3 + 46c8: e293300c adds r3, r3, #12 ; 0xc + 46cc: ebf5fe2b bl 0xffd83f80 + 46d0: 080c09dc stmeqda ip, {r2, r3, r4, r6, r7, r8, fp} + 46d4: e2830000 add r0, r3, #0 ; 0x0 + 46d8: e1a01004 mov r1, r4 + 46dc: ebf5fb9a bl 0xffd8354c + 46e0: 080c09de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, fp} + 46e4: ebf5fe25 bl 0xffd83f80 + 46e8: 080c09de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, fp} + 46ec: e3b03000 movs r3, #0 ; 0x0 + 46f0: ebf5fe22 bl 0xffd83f80 + 46f4: 080c09e0 stmeqda ip, {r5, r6, r7, r8, fp} + 46f8: e59d0434 ldr r0, [sp, #1076] + 46fc: e2800f00 add r0, r0, #0 ; 0x0 + 4700: e1a01003 mov r1, r3 + 4704: ebf5fbb0 bl 0xffd835cc + 4708: 080c09e2 stmeqda ip, {r1, r5, r6, r7, r8, fp} + 470c: ebf5fe1b bl 0xffd83f80 + 4710: 080c09e2 stmeqda ip, {r1, r5, r6, r7, r8, fp} + 4714: e3b030d4 movs r3, #212 ; 0xd4 + 4718: ebf5fe18 bl 0xffd83f80 + 471c: 080c09e4 stmeqda ip, {r2, r5, r6, r7, r8, fp} + 4720: e1b03103 movs r3, r3, lsl #2 + 4724: ebf5fe15 bl 0xffd83f80 + 4728: 080c09e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, fp} + 472c: e1a01005 mov r1, r5 + 4730: e0954003 adds r4, r5, r3 + 4734: ebf5fe11 bl 0xffd83f80 + 4738: 080c09e8 stmeqda ip, {r3, r5, r6, r7, r8, fp} + 473c: e3a00f81 mov r0, #516 ; 0x204 + 4740: e3800b02 orr r0, r0, #2048 ; 0x800 + 4744: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4748: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 474c: ebf5fc71 bl 0xffd83918 + 4750: 080c09ec stmeqda ip, {r2, r3, r5, r6, r7, r8, fp} + 4754: e1a05000 mov r5, r0 + 4758: ebf5fe08 bl 0xffd83f80 + 475c: 080c09ea stmeqda ip, {r1, r3, r5, r6, r7, r8, fp} + 4760: e59d1434 ldr r1, [sp, #1076] + 4764: e1a03001 mov r3, r1 + 4768: ebf5fe04 bl 0xffd83f80 + 476c: 080c09ec stmeqda ip, {r2, r3, r5, r6, r7, r8, fp} + 4770: ebf5fe02 bl 0xffd83f80 + 4774: 080c09ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, fp} + 4778: e3a000f1 mov r0, #241 ; 0xf1 + 477c: e3800c09 orr r0, r0, #2304 ; 0x900 + 4780: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4784: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4788: e58d0438 str r0, [sp, #1080] + 478c: e28cc03b add ip, ip, #59 ; 0x3b + 4790: e1a00fac mov r0, ip, lsr #31 + 4794: e08ff100 add pc, pc, r0, lsl #2 + 4798: 080c2f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp, sp} + 479c: ebf5f9ec bl 0xffd82f54 + 47a0: eafff4c0 b 0x1aa8 + 47a4: ebf5fdf5 bl 0xffd83f80 + 47a8: 080c09f0 stmeqda ip, {r4, r5, r6, r7, r8, fp} + 47ac: e59d0434 ldr r0, [sp, #1076] + 47b0: e2800f01 add r0, r0, #4 ; 0x4 + 47b4: e58d0434 str r0, [sp, #1076] + 47b8: ebf5fdf0 bl 0xffd83f80 + 47bc: 080c09f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, fp} + 47c0: e59d9434 ldr r9, [sp, #1076] + 47c4: e3c99003 bic r9, r9, #3 ; 0x3 + 47c8: e2890004 add r0, r9, #4 ; 0x4 + 47cc: e58d0434 str r0, [sp, #1076] + 47d0: e2890000 add r0, r9, #0 ; 0x0 + 47d4: ebf5fc4f bl 0xffd83918 + 47d8: 080c09f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, fp} + 47dc: e1a03000 mov r3, r0 + 47e0: e28cc007 add ip, ip, #7 ; 0x7 + 47e4: ebf5fde5 bl 0xffd83f80 + 47e8: 080c09f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, fp} + 47ec: e1a00003 mov r0, r3 + 47f0: e28cc003 add ip, ip, #3 ; 0x3 + 47f4: eaf5fa35 b 0xffd830d0 + 47f8: 080c09f0 stmeqda ip, {r4, r5, r6, r7, r8, fp} + 47fc: 00000000 andeq r0, r0, r0 + 4800: ebf5fdde bl 0xffd83f80 + 4804: 080c09f0 stmeqda ip, {r4, r5, r6, r7, r8, fp} + 4808: e59d0434 ldr r0, [sp, #1076] + 480c: e2800f01 add r0, r0, #4 ; 0x4 + 4810: e58d0434 str r0, [sp, #1076] + 4814: ebf5fdd9 bl 0xffd83f80 + 4818: 080c09f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, fp} + 481c: e59d9434 ldr r9, [sp, #1076] + 4820: e3c99003 bic r9, r9, #3 ; 0x3 + 4824: e2890004 add r0, r9, #4 ; 0x4 + 4828: e58d0434 str r0, [sp, #1076] + 482c: e2890000 add r0, r9, #0 ; 0x0 + 4830: ebf5fc38 bl 0xffd83918 + 4834: 080c09f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, fp} + 4838: e1a03000 mov r3, r0 + 483c: ebf5fdcf bl 0xffd83f80 + 4840: 080c09f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, fp} + 4844: e1a00003 mov r0, r3 + 4848: e28cc00a add ip, ip, #10 ; 0xa + 484c: eaf5fa1f b 0xffd830d0 + 4850: 080c094c stmeqda ip, {r2, r3, r6, r8, fp} + 4854: 00000000 andeq r0, r0, r0 + 4858: ebf5fdc8 bl 0xffd83f80 + 485c: 080c094c stmeqda ip, {r2, r3, r6, r8, fp} + 4860: e1a01007 mov r1, r7 + 4864: e2973000 adds r3, r7, #0 ; 0x0 + 4868: ebf5fdc4 bl 0xffd83f80 + 486c: 080c094e stmeqda ip, {r1, r2, r3, r6, r8, fp} + 4870: ebf5fdc2 bl 0xffd83f80 + 4874: 080c0950 stmeqda ip, {r4, r6, r8, fp} + 4878: e3a00053 mov r0, #83 ; 0x53 + 487c: e3800c09 orr r0, r0, #2304 ; 0x900 + 4880: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4884: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4888: e58d0438 str r0, [sp, #1080] + 488c: e28cc009 add ip, ip, #9 ; 0x9 + 4890: e1a00fac mov r0, ip, lsr #31 + 4894: e08ff100 add pc, pc, r0, lsl #2 + 4898: 080c082c stmeqda ip, {r2, r3, r5, fp} + 489c: ebf5f9ac bl 0xffd82f54 + 48a0: eafff620 b 0x2128 + 48a4: 080c03cc stmeqda ip, {r2, r3, r6, r7, r8, r9} + 48a8: 00000000 andeq r0, r0, r0 + 48ac: ebf5fdb3 bl 0xffd83f80 + 48b0: 080c03cc stmeqda ip, {r2, r3, r6, r7, r8, r9} + 48b4: e3a00f09 mov r0, #36 ; 0x24 + 48b8: e3800b01 orr r0, r0, #1024 ; 0x400 + 48bc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 48c0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 48c4: ebf5fc13 bl 0xffd83918 + 48c8: 080c03d0 stmeqda ip, {r4, r6, r7, r8, r9} + 48cc: e1a03000 mov r3, r0 + 48d0: ebf5fdaa bl 0xffd83f80 + 48d4: 080c03ce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9} + 48d8: e1b03803 movs r3, r3, lsl #16 + 48dc: ebf5fda7 bl 0xffd83f80 + 48e0: 080c03d0 stmeqda ip, {r4, r6, r7, r8, r9} + 48e4: e1b03823 movs r3, r3, lsr #16 + 48e8: ebf5fda4 bl 0xffd83f80 + 48ec: 080c03d2 stmeqda ip, {r1, r4, r6, r7, r8, r9} + 48f0: e3530000 cmp r3, #0 ; 0x0 + 48f4: ebf5fda1 bl 0xffd83f80 + 48f8: 080c03d4 stmeqda ip, {r2, r4, r6, r7, r8, r9} + 48fc: e28cc011 add ip, ip, #17 ; 0x11 + 4900: 1a000004 bne 0x4918 + 4904: e1a00fac mov r0, ip, lsr #31 + 4908: e08ff100 add pc, pc, r0, lsl #2 + 490c: 080c0400 stmeqda ip, {sl} + 4910: ebf5f98f bl 0xffd82f54 + 4914: ea00004d b 0x4a50 + 4918: ebf5fd98 bl 0xffd83f80 + 491c: 080c03d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9} + 4920: e3a00f0a mov r0, #40 ; 0x28 + 4924: e3800b01 orr r0, r0, #1024 ; 0x400 + 4928: e3800703 orr r0, r0, #786432 ; 0xc0000 + 492c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4930: ebf5fbf8 bl 0xffd83918 + 4934: 080c03da stmeqda ip, {r1, r3, r4, r6, r7, r8, r9} + 4938: e1a04000 mov r4, r0 + 493c: ebf5fd8f bl 0xffd83f80 + 4940: 080c03d8 stmeqda ip, {r3, r4, r6, r7, r8, r9} + 4944: e1a00004 mov r0, r4 + 4948: e58d0420 str r0, [sp, #1056] + 494c: ebf5fd8b bl 0xffd83f80 + 4950: 080c03da stmeqda ip, {r1, r3, r4, r6, r7, r8, r9} + 4954: e59d1420 ldr r1, [sp, #1056] + 4958: e1a08001 mov r8, r1 + 495c: ebf5fd87 bl 0xffd83f80 + 4960: 080c03dc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9} + 4964: e3b00000 movs r0, #0 ; 0x0 + 4968: e58d041c str r0, [sp, #1052] + 496c: ebf5fd83 bl 0xffd83f80 + 4970: 080c03de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9} + 4974: e1a01003 mov r1, r3 + 4978: e2930000 adds r0, r3, #0 ; 0x0 + 497c: e58d0418 str r0, [sp, #1048] + 4980: ebf5fd7e bl 0xffd83f80 + 4984: 080c03e0 stmeqda ip, {r5, r6, r7, r8, r9} + 4988: e2880000 add r0, r8, #0 ; 0x0 + 498c: ebf5fbe1 bl 0xffd83918 + 4990: 080c03e4 stmeqda ip, {r2, r5, r6, r7, r8, r9} + 4994: e1a07000 mov r7, r0 + 4998: ebf5fd78 bl 0xffd83f80 + 499c: 080c03e2 stmeqda ip, {r1, r5, r6, r7, r8, r9} + 49a0: e59d1420 ldr r1, [sp, #1056] + 49a4: e1a03001 mov r3, r1 + 49a8: ebf5fd74 bl 0xffd83f80 + 49ac: 080c03e4 stmeqda ip, {r2, r5, r6, r7, r8, r9} + 49b0: e1a01003 mov r1, r3 + 49b4: e2933004 adds r3, r3, #4 ; 0x4 + 49b8: ebf5fd70 bl 0xffd83f80 + 49bc: 080c03e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9} + 49c0: e59d141c ldr r1, [sp, #1052] + 49c4: e59d141c ldr r1, [sp, #1052] + 49c8: e0913003 adds r3, r1, r3 + 49cc: ebf5fd6b bl 0xffd83f80 + 49d0: 080c03e8 stmeqda ip, {r3, r5, r6, r7, r8, r9} + 49d4: e2830000 add r0, r3, #0 ; 0x0 + 49d8: ebf5fbce bl 0xffd83918 + 49dc: 080c03ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9} + 49e0: e1a04000 mov r4, r0 + 49e4: ebf5fd65 bl 0xffd83f80 + 49e8: 080c03ea stmeqda ip, {r1, r3, r5, r6, r7, r8, r9} + 49ec: e2880008 add r0, r8, #8 ; 0x8 + 49f0: ebf5fb71 bl 0xffd837bc + 49f4: 080c03ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9} + 49f8: e1a05000 mov r5, r0 + 49fc: ebf5fd5f bl 0xffd83f80 + 4a00: 080c03ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9} + 4a04: e1a01007 mov r1, r7 + 4a08: e2973000 adds r3, r7, #0 ; 0x0 + 4a0c: ebf5fd5b bl 0xffd83f80 + 4a10: 080c03ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9} + 4a14: ebf5fd59 bl 0xffd83f80 + 4a18: 080c03f0 stmeqda ip, {r4, r5, r6, r7, r8, r9} + 4a1c: e3a000f3 mov r0, #243 ; 0xf3 + 4a20: e3800c03 orr r0, r0, #768 ; 0x300 + 4a24: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4a28: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4a2c: e58d0438 str r0, [sp, #1080] + 4a30: e28cc032 add ip, ip, #50 ; 0x32 + 4a34: e1a00fac mov r0, ip, lsr #31 + 4a38: e08ff100 add pc, pc, r0, lsl #2 + 4a3c: 080c0a44 stmeqda ip, {r2, r6, r9, fp} + 4a40: ebf5f943 bl 0xffd82f54 + 4a44: ea000036 b 0x4b24 + 4a48: 080c0400 stmeqda ip, {sl} + 4a4c: 00000000 andeq r0, r0, r0 + 4a50: ebf5fd4a bl 0xffd83f80 + 4a54: 080c0400 stmeqda ip, {sl} + 4a58: e59d9434 ldr r9, [sp, #1076] + 4a5c: e3c99003 bic r9, r9, #3 ; 0x3 + 4a60: e2890004 add r0, r9, #4 ; 0x4 + 4a64: e58d0434 str r0, [sp, #1076] + 4a68: e2890000 add r0, r9, #0 ; 0x0 + 4a6c: ebf5fba9 bl 0xffd83918 + 4a70: 080c0404 stmeqda ip, {r2, sl} + 4a74: e1a06000 mov r6, r0 + 4a78: ebf5fd40 bl 0xffd83f80 + 4a7c: 080c0402 stmeqda ip, {r1, sl} + 4a80: e1a00006 mov r0, r6 + 4a84: e58d0420 str r0, [sp, #1056] + 4a88: ebf5fd3c bl 0xffd83f80 + 4a8c: 080c0404 stmeqda ip, {r2, sl} + 4a90: e59d9434 ldr r9, [sp, #1076] + 4a94: e3c99003 bic r9, r9, #3 ; 0x3 + 4a98: e2890010 add r0, r9, #16 ; 0x10 + 4a9c: e58d0434 str r0, [sp, #1076] + 4aa0: e2890000 add r0, r9, #0 ; 0x0 + 4aa4: ebf5fb9b bl 0xffd83918 + 4aa8: 080c0408 stmeqda ip, {r3, sl} + 4aac: e1a07000 mov r7, r0 + 4ab0: e2890004 add r0, r9, #4 ; 0x4 + 4ab4: ebf5fb97 bl 0xffd83918 + 4ab8: 080c0408 stmeqda ip, {r3, sl} + 4abc: e1a08000 mov r8, r0 + 4ac0: e2890008 add r0, r9, #8 ; 0x8 + 4ac4: ebf5fb93 bl 0xffd83918 + 4ac8: 080c0408 stmeqda ip, {r3, sl} + 4acc: e58d0418 str r0, [sp, #1048] + 4ad0: e289000c add r0, r9, #12 ; 0xc + 4ad4: ebf5fb8f bl 0xffd83918 + 4ad8: 080c0408 stmeqda ip, {r3, sl} + 4adc: e58d041c str r0, [sp, #1052] + 4ae0: ebf5fd26 bl 0xffd83f80 + 4ae4: 080c0406 stmeqda ip, {r1, r2, sl} + 4ae8: e59d9434 ldr r9, [sp, #1076] + 4aec: e3c99003 bic r9, r9, #3 ; 0x3 + 4af0: e2890004 add r0, r9, #4 ; 0x4 + 4af4: e58d0434 str r0, [sp, #1076] + 4af8: e2890000 add r0, r9, #0 ; 0x0 + 4afc: ebf5fb85 bl 0xffd83918 + 4b00: 080c040a stmeqda ip, {r1, r3, sl} + 4b04: e1a03000 mov r3, r0 + 4b08: ebf5fd1c bl 0xffd83f80 + 4b0c: 080c0408 stmeqda ip, {r3, sl} + 4b10: e1a00003 mov r0, r3 + 4b14: e28cc015 add ip, ip, #21 ; 0x15 + 4b18: eaf5f96c b 0xffd830d0 + 4b1c: 080c0a44 stmeqda ip, {r2, r6, r9, fp} + 4b20: 00000000 andeq r0, r0, r0 + 4b24: ebf5fd15 bl 0xffd83f80 + 4b28: 080c0a44 stmeqda ip, {r2, r6, r9, fp} + 4b2c: e59d9434 ldr r9, [sp, #1076] + 4b30: e3c99003 bic r9, r9, #3 ; 0x3 + 4b34: e2499014 sub r9, r9, #20 ; 0x14 + 4b38: e58d9434 str r9, [sp, #1076] + 4b3c: e2890000 add r0, r9, #0 ; 0x0 + 4b40: e1a01007 mov r1, r7 + 4b44: ebf5fac0 bl 0xffd8364c + 4b48: e2890004 add r0, r9, #4 ; 0x4 + 4b4c: e1a01008 mov r1, r8 + 4b50: ebf5fabd bl 0xffd8364c + 4b54: e2890008 add r0, r9, #8 ; 0x8 + 4b58: e59d1418 ldr r1, [sp, #1048] + 4b5c: ebf5faba bl 0xffd8364c + 4b60: e289000c add r0, r9, #12 ; 0xc + 4b64: e59d141c ldr r1, [sp, #1052] + 4b68: ebf5fab7 bl 0xffd8364c + 4b6c: e2890010 add r0, r9, #16 ; 0x10 + 4b70: e59d1438 ldr r1, [sp, #1080] + 4b74: ebf5fab4 bl 0xffd8364c + 4b78: ebf5fd00 bl 0xffd83f80 + 4b7c: 080c0a46 stmeqda ip, {r1, r2, r6, r9, fp} + 4b80: e1a01003 mov r1, r3 + 4b84: e2930000 adds r0, r3, #0 ; 0x0 + 4b88: e58d041c str r0, [sp, #1052] + 4b8c: ebf5fcfb bl 0xffd83f80 + 4b90: 080c0a48 stmeqda ip, {r3, r6, r9, fp} + 4b94: e1a01004 mov r1, r4 + 4b98: e2940000 adds r0, r4, #0 ; 0x0 + 4b9c: e58d0418 str r0, [sp, #1048] + 4ba0: ebf5fcf6 bl 0xffd83f80 + 4ba4: 080c0a4a stmeqda ip, {r1, r3, r6, r9, fp} + 4ba8: e1b05c05 movs r5, r5, lsl #24 + 4bac: ebf5fcf3 bl 0xffd83f80 + 4bb0: 080c0a4c stmeqda ip, {r2, r3, r6, r9, fp} + 4bb4: e1b07c25 movs r7, r5, lsr #24 + 4bb8: ebf5fcf0 bl 0xffd83f80 + 4bbc: 080c0a4e stmeqda ip, {r1, r2, r3, r6, r9, fp} + 4bc0: e3570000 cmp r7, #0 ; 0x0 + 4bc4: ebf5fced bl 0xffd83f80 + 4bc8: 080c0a50 stmeqda ip, {r4, r6, r9, fp} + 4bcc: e28cc019 add ip, ip, #25 ; 0x19 + 4bd0: 1a000004 bne 0x4be8 + 4bd4: e1a00fac mov r0, ip, lsr #31 + 4bd8: e08ff100 add pc, pc, r0, lsl #2 + 4bdc: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 4be0: ebf5f8db bl 0xffd82f54 + 4be4: ea000058 b 0x4d4c + 4be8: ebf5fce4 bl 0xffd83f80 + 4bec: 080c0a52 stmeqda ip, {r1, r4, r6, r9, fp} + 4bf0: e3570010 cmp r7, #16 ; 0x10 + 4bf4: ebf5fce1 bl 0xffd83f80 + 4bf8: 080c0a54 stmeqda ip, {r2, r4, r6, r9, fp} + 4bfc: e28cc006 add ip, ip, #6 ; 0x6 + 4c00: 8a000004 bhi 0x4c18 + 4c04: e1a00fac mov r0, ip, lsr #31 + 4c08: e08ff100 add pc, pc, r0, lsl #2 + 4c0c: 080c0a58 stmeqda ip, {r3, r4, r6, r9, fp} + 4c10: ebf5f8cf bl 0xffd82f54 + 4c14: ea000003 b 0x4c28 + 4c18: ebf5fcd8 bl 0xffd83f80 + 4c1c: 080c0a56 stmeqda ip, {r1, r2, r4, r6, r9, fp} + 4c20: e3b07010 movs r7, #16 ; 0x10 + 4c24: e28cc003 add ip, ip, #3 ; 0x3 + 4c28: ebf5fcd4 bl 0xffd83f80 + 4c2c: 080c0a58 stmeqda ip, {r3, r4, r6, r9, fp} + 4c30: e3a00eab mov r0, #2736 ; 0xab0 + 4c34: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4c38: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4c3c: ebf5fb35 bl 0xffd83918 + 4c40: 080c0a5c stmeqda ip, {r2, r3, r4, r6, r9, fp} + 4c44: e1a03000 mov r3, r0 + 4c48: ebf5fccc bl 0xffd83f80 + 4c4c: 080c0a5a stmeqda ip, {r1, r3, r4, r6, r9, fp} + 4c50: e2830000 add r0, r3, #0 ; 0x0 + 4c54: ebf5fb2f bl 0xffd83918 + 4c58: 080c0a5e stmeqda ip, {r1, r2, r3, r4, r6, r9, fp} + 4c5c: e1a08000 mov r8, r0 + 4c60: ebf5fcc6 bl 0xffd83f80 + 4c64: 080c0a5c stmeqda ip, {r2, r3, r4, r6, r9, fp} + 4c68: e2880000 add r0, r8, #0 ; 0x0 + 4c6c: ebf5fb29 bl 0xffd83918 + 4c70: 080c0a60 stmeqda ip, {r5, r6, r9, fp} + 4c74: e1a04000 mov r4, r0 + 4c78: ebf5fcc0 bl 0xffd83f80 + 4c7c: 080c0a5e stmeqda ip, {r1, r2, r3, r4, r6, r9, fp} + 4c80: e3a00fad mov r0, #692 ; 0x2b4 + 4c84: e3800b02 orr r0, r0, #2048 ; 0x800 + 4c88: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4c8c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4c90: ebf5fb20 bl 0xffd83918 + 4c94: 080c0a62 stmeqda ip, {r1, r5, r6, r9, fp} + 4c98: e1a03000 mov r3, r0 + 4c9c: ebf5fcb7 bl 0xffd83f80 + 4ca0: 080c0a60 stmeqda ip, {r5, r6, r9, fp} + 4ca4: e1540003 cmp r4, r3 + 4ca8: ebf5fcb4 bl 0xffd83f80 + 4cac: 080c0a62 stmeqda ip, {r1, r5, r6, r9, fp} + 4cb0: e28cc01a add ip, ip, #26 ; 0x1a + 4cb4: 0a000004 beq 0x4ccc + 4cb8: e1a00fac mov r0, ip, lsr #31 + 4cbc: e08ff100 add pc, pc, r0, lsl #2 + 4cc0: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 4cc4: ebf5f8a2 bl 0xffd82f54 + 4cc8: ea00001f b 0x4d4c + 4ccc: ebf5fcab bl 0xffd83f80 + 4cd0: 080c0a64 stmeqda ip, {r2, r5, r6, r9, fp} + 4cd4: e1a01004 mov r1, r4 + 4cd8: e2943001 adds r3, r4, #1 ; 0x1 + 4cdc: ebf5fca7 bl 0xffd83f80 + 4ce0: 080c0a66 stmeqda ip, {r1, r2, r5, r6, r9, fp} + 4ce4: e2880000 add r0, r8, #0 ; 0x0 + 4ce8: e1a01003 mov r1, r3 + 4cec: ebf5fa36 bl 0xffd835cc + 4cf0: 080c0a68 stmeqda ip, {r3, r5, r6, r9, fp} + 4cf4: ebf5fca1 bl 0xffd83f80 + 4cf8: 080c0a68 stmeqda ip, {r3, r5, r6, r9, fp} + 4cfc: e59d141c ldr r1, [sp, #1052] + 4d00: e59d141c ldr r1, [sp, #1052] + 4d04: e2913000 adds r3, r1, #0 ; 0x0 + 4d08: ebf5fc9c bl 0xffd83f80 + 4d0c: 080c0a6a stmeqda ip, {r1, r3, r5, r6, r9, fp} + 4d10: ebf5fc9a bl 0xffd83f80 + 4d14: 080c0a6c stmeqda ip, {r2, r3, r5, r6, r9, fp} + 4d18: e3a0006f mov r0, #111 ; 0x6f + 4d1c: e3800c0a orr r0, r0, #2560 ; 0xa00 + 4d20: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4d24: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4d28: e58d0438 str r0, [sp, #1080] + 4d2c: e28cc010 add ip, ip, #16 ; 0x10 + 4d30: e1a00fac mov r0, ip, lsr #31 + 4d34: e08ff100 add pc, pc, r0, lsl #2 + 4d38: 080c0758 stmeqda ip, {r3, r4, r6, r8, r9, sl} + 4d3c: ebf5f884 bl 0xffd82f54 + 4d40: ea000028 b 0x4de8 + 4d44: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 4d48: 00000000 andeq r0, r0, r0 + 4d4c: ebf5fc8b bl 0xffd83f80 + 4d50: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 4d54: e59d9434 ldr r9, [sp, #1076] + 4d58: e3c99003 bic r9, r9, #3 ; 0x3 + 4d5c: e2890010 add r0, r9, #16 ; 0x10 + 4d60: e58d0434 str r0, [sp, #1076] + 4d64: e2890000 add r0, r9, #0 ; 0x0 + 4d68: ebf5faea bl 0xffd83918 + 4d6c: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 4d70: e1a07000 mov r7, r0 + 4d74: e2890004 add r0, r9, #4 ; 0x4 + 4d78: ebf5fae6 bl 0xffd83918 + 4d7c: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 4d80: e1a08000 mov r8, r0 + 4d84: e2890008 add r0, r9, #8 ; 0x8 + 4d88: ebf5fae2 bl 0xffd83918 + 4d8c: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 4d90: e58d0418 str r0, [sp, #1048] + 4d94: e289000c add r0, r9, #12 ; 0xc + 4d98: ebf5fade bl 0xffd83918 + 4d9c: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 4da0: e58d041c str r0, [sp, #1052] + 4da4: ebf5fc75 bl 0xffd83f80 + 4da8: 080c0aaa stmeqda ip, {r1, r3, r5, r7, r9, fp} + 4dac: e59d9434 ldr r9, [sp, #1076] + 4db0: e3c99003 bic r9, r9, #3 ; 0x3 + 4db4: e2890004 add r0, r9, #4 ; 0x4 + 4db8: e58d0434 str r0, [sp, #1076] + 4dbc: e2890000 add r0, r9, #0 ; 0x0 + 4dc0: ebf5fad4 bl 0xffd83918 + 4dc4: 080c0aae stmeqda ip, {r1, r2, r3, r5, r7, r9, fp} + 4dc8: e1a03000 mov r3, r0 + 4dcc: ebf5fc6b bl 0xffd83f80 + 4dd0: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 4dd4: e1a00003 mov r0, r3 + 4dd8: e28cc00e add ip, ip, #14 ; 0xe + 4ddc: eaf5f8bb b 0xffd830d0 + 4de0: 080c0758 stmeqda ip, {r3, r4, r6, r8, r9, sl} + 4de4: 00000000 andeq r0, r0, r0 + 4de8: ebf5fc64 bl 0xffd83f80 + 4dec: 080c0758 stmeqda ip, {r3, r4, r6, r8, r9, sl} + 4df0: e59d9434 ldr r9, [sp, #1076] + 4df4: e3c99003 bic r9, r9, #3 ; 0x3 + 4df8: e2499004 sub r9, r9, #4 ; 0x4 + 4dfc: e58d9434 str r9, [sp, #1076] + 4e00: e2890000 add r0, r9, #0 ; 0x0 + 4e04: e59d1438 ldr r1, [sp, #1080] + 4e08: ebf5fa0f bl 0xffd8364c + 4e0c: ebf5fc5b bl 0xffd83f80 + 4e10: 080c075a stmeqda ip, {r1, r3, r4, r6, r8, r9, sl} + 4e14: e3a00fda mov r0, #872 ; 0x368 + 4e18: e3800b01 orr r0, r0, #1024 ; 0x400 + 4e1c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4e20: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4e24: ebf5fabb bl 0xffd83918 + 4e28: 080c075e stmeqda ip, {r1, r2, r3, r4, r6, r8, r9, sl} + 4e2c: e1a04000 mov r4, r0 + 4e30: ebf5fc52 bl 0xffd83f80 + 4e34: 080c075c stmeqda ip, {r2, r3, r4, r6, r8, r9, sl} + 4e38: e2840000 add r0, r4, #0 ; 0x0 + 4e3c: ebf5fab5 bl 0xffd83918 + 4e40: 080c0760 stmeqda ip, {r5, r6, r8, r9, sl} + 4e44: e1a04000 mov r4, r0 + 4e48: ebf5fc4c bl 0xffd83f80 + 4e4c: 080c075e stmeqda ip, {r1, r2, r3, r4, r6, r8, r9, sl} + 4e50: ebf5fc4a bl 0xffd83f80 + 4e54: 080c0760 stmeqda ip, {r5, r6, r8, r9, sl} + 4e58: e3a00063 mov r0, #99 ; 0x63 + 4e5c: e3800c07 orr r0, r0, #1792 ; 0x700 + 4e60: e3800703 orr r0, r0, #786432 ; 0xc0000 + 4e64: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 4e68: e58d0438 str r0, [sp, #1080] + 4e6c: e28cc013 add ip, ip, #19 ; 0x13 + 4e70: e1a00fac mov r0, ip, lsr #31 + 4e74: e08ff100 add pc, pc, r0, lsl #2 + 4e78: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 4e7c: ebf5f834 bl 0xffd82f54 + 4e80: ea000001 b 0x4e8c + 4e84: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 4e88: 00000000 andeq r0, r0, r0 + 4e8c: ebf5fc3b bl 0xffd83f80 + 4e90: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 4e94: e1a00004 mov r0, r4 + 4e98: e28cc003 add ip, ip, #3 ; 0x3 + 4e9c: eaf5f88b b 0xffd830d0 + 4ea0: 080bfb50 stmeqda fp, {r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ea4: 00000000 andeq r0, r0, r0 + 4ea8: ebf5fc34 bl 0xffd83f80 + 4eac: 080bfb50 stmeqda fp, {r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4eb0: e1a00007 mov r0, r7 + 4eb4: e58d0430 str r0, [sp, #1072] + 4eb8: ebf5fc30 bl 0xffd83f80 + 4ebc: 080bfb52 stmeqda fp, {r1, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ec0: e3b04000 movs r4, #0 ; 0x0 + 4ec4: ebf5fc2d bl 0xffd83f80 + 4ec8: 080bfb54 stmeqda fp, {r2, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ecc: e3b05000 movs r5, #0 ; 0x0 + 4ed0: ebf5fc2a bl 0xffd83f80 + 4ed4: 080bfb56 stmeqda fp, {r1, r2, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ed8: e3b06000 movs r6, #0 ; 0x0 + 4edc: ebf5fc27 bl 0xffd83f80 + 4ee0: 080bfb58 stmeqda fp, {r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ee4: e3b07000 movs r7, #0 ; 0x0 + 4ee8: ebf5fc24 bl 0xffd83f80 + 4eec: 080bfb5a stmeqda fp, {r1, r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4ef0: e1a09003 mov r9, r3 + 4ef4: e3c99003 bic r9, r9, #3 ; 0x3 + 4ef8: e2890010 add r0, r9, #16 ; 0x10 + 4efc: e1a03000 mov r3, r0 + 4f00: e2890000 add r0, r9, #0 ; 0x0 + 4f04: e1a01004 mov r1, r4 + 4f08: ebf5f9cf bl 0xffd8364c + 4f0c: e2890004 add r0, r9, #4 ; 0x4 + 4f10: e1a01005 mov r1, r5 + 4f14: ebf5f9cc bl 0xffd8364c + 4f18: e2890008 add r0, r9, #8 ; 0x8 + 4f1c: e1a01006 mov r1, r6 + 4f20: ebf5f9c9 bl 0xffd8364c + 4f24: e289000c add r0, r9, #12 ; 0xc + 4f28: e1a01007 mov r1, r7 + 4f2c: ebf5f9a6 bl 0xffd835cc + 4f30: 080bfb5c stmeqda fp, {r2, r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4f34: ebf5fc11 bl 0xffd83f80 + 4f38: 080bfb5c stmeqda fp, {r2, r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4f3c: e1a09003 mov r9, r3 + 4f40: e3c99003 bic r9, r9, #3 ; 0x3 + 4f44: e2890010 add r0, r9, #16 ; 0x10 + 4f48: e1a03000 mov r3, r0 + 4f4c: e2890000 add r0, r9, #0 ; 0x0 + 4f50: e1a01004 mov r1, r4 + 4f54: ebf5f9bc bl 0xffd8364c + 4f58: e2890004 add r0, r9, #4 ; 0x4 + 4f5c: e1a01005 mov r1, r5 + 4f60: ebf5f9b9 bl 0xffd8364c + 4f64: e2890008 add r0, r9, #8 ; 0x8 + 4f68: e1a01006 mov r1, r6 + 4f6c: ebf5f9b6 bl 0xffd8364c + 4f70: e289000c add r0, r9, #12 ; 0xc + 4f74: e1a01007 mov r1, r7 + 4f78: ebf5f993 bl 0xffd835cc + 4f7c: 080bfb5e stmeqda fp, {r1, r2, r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4f80: ebf5fbfe bl 0xffd83f80 + 4f84: 080bfb5e stmeqda fp, {r1, r2, r3, r4, r6, r8, r9, fp, ip, sp, lr, pc} + 4f88: e1a09003 mov r9, r3 + 4f8c: e3c99003 bic r9, r9, #3 ; 0x3 + 4f90: e2890010 add r0, r9, #16 ; 0x10 + 4f94: e1a03000 mov r3, r0 + 4f98: e2890000 add r0, r9, #0 ; 0x0 + 4f9c: e1a01004 mov r1, r4 + 4fa0: ebf5f9a9 bl 0xffd8364c + 4fa4: e2890004 add r0, r9, #4 ; 0x4 + 4fa8: e1a01005 mov r1, r5 + 4fac: ebf5f9a6 bl 0xffd8364c + 4fb0: e2890008 add r0, r9, #8 ; 0x8 + 4fb4: e1a01006 mov r1, r6 + 4fb8: ebf5f9a3 bl 0xffd8364c + 4fbc: e289000c add r0, r9, #12 ; 0xc + 4fc0: e1a01007 mov r1, r7 + 4fc4: ebf5f980 bl 0xffd835cc + 4fc8: 080bfb60 stmeqda fp, {r5, r6, r8, r9, fp, ip, sp, lr, pc} + 4fcc: ebf5fbeb bl 0xffd83f80 + 4fd0: 080bfb60 stmeqda fp, {r5, r6, r8, r9, fp, ip, sp, lr, pc} + 4fd4: e1a09003 mov r9, r3 + 4fd8: e3c99003 bic r9, r9, #3 ; 0x3 + 4fdc: e2890010 add r0, r9, #16 ; 0x10 + 4fe0: e1a03000 mov r3, r0 + 4fe4: e2890000 add r0, r9, #0 ; 0x0 + 4fe8: e1a01004 mov r1, r4 + 4fec: ebf5f996 bl 0xffd8364c + 4ff0: e2890004 add r0, r9, #4 ; 0x4 + 4ff4: e1a01005 mov r1, r5 + 4ff8: ebf5f993 bl 0xffd8364c + 4ffc: e2890008 add r0, r9, #8 ; 0x8 + 5000: e1a01006 mov r1, r6 + 5004: ebf5f990 bl 0xffd8364c + 5008: e289000c add r0, r9, #12 ; 0xc + 500c: e1a01007 mov r1, r7 + 5010: ebf5f96d bl 0xffd835cc + 5014: 080bfb62 stmeqda fp, {r1, r5, r6, r8, r9, fp, ip, sp, lr, pc} + 5018: ebf5fbd8 bl 0xffd83f80 + 501c: 080bfb62 stmeqda fp, {r1, r5, r6, r8, r9, fp, ip, sp, lr, pc} + 5020: e59d1430 ldr r1, [sp, #1072] + 5024: e1a07001 mov r7, r1 + 5028: e28cc02e add ip, ip, #46 ; 0x2e + 502c: ebf5fbd3 bl 0xffd83f80 + 5030: 080bfb64 stmeqda fp, {r2, r5, r6, r8, r9, fp, ip, sp, lr, pc} + 5034: e59d0438 ldr r0, [sp, #1080] + 5038: e28cc003 add ip, ip, #3 ; 0x3 + 503c: eaf5f823 b 0xffd830d0 + 5040: 080c0762 stmeqda ip, {r1, r5, r6, r8, r9, sl} + 5044: 00000000 andeq r0, r0, r0 + 5048: ebf5fbcc bl 0xffd83f80 + 504c: 080c0762 stmeqda ip, {r1, r5, r6, r8, r9, sl} + 5050: e59d9434 ldr r9, [sp, #1076] + 5054: e3c99003 bic r9, r9, #3 ; 0x3 + 5058: e2890004 add r0, r9, #4 ; 0x4 + 505c: e58d0434 str r0, [sp, #1076] + 5060: e2890000 add r0, r9, #0 ; 0x0 + 5064: ebf5fa2b bl 0xffd83918 + 5068: 080c0766 stmeqda ip, {r1, r2, r5, r6, r8, r9, sl} + 506c: e1a03000 mov r3, r0 + 5070: ebf5fbc2 bl 0xffd83f80 + 5074: 080c0764 stmeqda ip, {r2, r5, r6, r8, r9, sl} + 5078: e1a00003 mov r0, r3 + 507c: e28cc007 add ip, ip, #7 ; 0x7 + 5080: eaf5f812 b 0xffd830d0 + 5084: 080c0a6e stmeqda ip, {r1, r2, r3, r5, r6, r9, fp} + 5088: 00000000 andeq r0, r0, r0 + 508c: ebf5fbbb bl 0xffd83f80 + 5090: 080c0a6e stmeqda ip, {r1, r2, r3, r5, r6, r9, fp} + 5094: e59d041c ldr r0, [sp, #1052] + 5098: e280002c add r0, r0, #44 ; 0x2c + 509c: e59d1418 ldr r1, [sp, #1048] + 50a0: ebf5f949 bl 0xffd835cc + 50a4: 080c0a70 stmeqda ip, {r4, r5, r6, r9, fp} + 50a8: ebf5fbb4 bl 0xffd83f80 + 50ac: 080c0a70 stmeqda ip, {r4, r5, r6, r9, fp} + 50b0: e59d041c ldr r0, [sp, #1052] + 50b4: e2800008 add r0, r0, #8 ; 0x8 + 50b8: e1a01007 mov r1, r7 + 50bc: ebf5f903 bl 0xffd834d0 + 50c0: 080c0a72 stmeqda ip, {r1, r4, r5, r6, r9, fp} + 50c4: ebf5fbad bl 0xffd83f80 + 50c8: 080c0a72 stmeqda ip, {r1, r4, r5, r6, r9, fp} + 50cc: e3b03080 movs r3, #128 ; 0x80 + 50d0: ebf5fbaa bl 0xffd83f80 + 50d4: 080c0a74 stmeqda ip, {r2, r4, r5, r6, r9, fp} + 50d8: e1b03c03 movs r3, r3, lsl #24 + 50dc: ebf5fba7 bl 0xffd83f80 + 50e0: 080c0a76 stmeqda ip, {r1, r2, r4, r5, r6, r9, fp} + 50e4: e59d041c ldr r0, [sp, #1052] + 50e8: e2800004 add r0, r0, #4 ; 0x4 + 50ec: e1a01003 mov r1, r3 + 50f0: ebf5f935 bl 0xffd835cc + 50f4: 080c0a78 stmeqda ip, {r3, r4, r5, r6, r9, fp} + 50f8: ebf5fba0 bl 0xffd83f80 + 50fc: 080c0a78 stmeqda ip, {r3, r4, r5, r6, r9, fp} + 5100: e3570000 cmp r7, #0 ; 0x0 + 5104: ebf5fb9d bl 0xffd83f80 + 5108: 080c0a7a stmeqda ip, {r1, r3, r4, r5, r6, r9, fp} + 510c: e28cc018 add ip, ip, #24 ; 0x18 + 5110: 1a000004 bne 0x5128 + 5114: e1a00fac mov r0, ip, lsr #31 + 5118: e08ff100 add pc, pc, r0, lsl #2 + 511c: 080c0a8c stmeqda ip, {r2, r3, r7, r9, fp} + 5120: ebf5f78b bl 0xffd82f54 + 5124: ea000026 b 0x51c4 + 5128: ebf5fb94 bl 0xffd83f80 + 512c: 080c0a7c stmeqda ip, {r2, r3, r4, r5, r6, r9, fp} + 5130: e3b04000 movs r4, #0 ; 0x0 + 5134: e28cc003 add ip, ip, #3 ; 0x3 + 5138: ebf5fb90 bl 0xffd83f80 + 513c: 080c0a7e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, fp} + 5140: e59d0418 ldr r0, [sp, #1048] + 5144: e2800000 add r0, r0, #0 ; 0x0 + 5148: e1a01004 mov r1, r4 + 514c: ebf5f8df bl 0xffd834d0 + 5150: 080c0a80 stmeqda ip, {r7, r9, fp} + 5154: ebf5fb89 bl 0xffd83f80 + 5158: 080c0a80 stmeqda ip, {r7, r9, fp} + 515c: e1a01007 mov r1, r7 + 5160: e2573001 subs r3, r7, #1 ; 0x1 + 5164: ebf5fb85 bl 0xffd83f80 + 5168: 080c0a82 stmeqda ip, {r1, r7, r9, fp} + 516c: e1b03c03 movs r3, r3, lsl #24 + 5170: ebf5fb82 bl 0xffd83f80 + 5174: 080c0a84 stmeqda ip, {r2, r7, r9, fp} + 5178: e1b07c23 movs r7, r3, lsr #24 + 517c: ebf5fb7f bl 0xffd83f80 + 5180: 080c0a86 stmeqda ip, {r1, r2, r7, r9, fp} + 5184: e59d1418 ldr r1, [sp, #1048] + 5188: e59d1418 ldr r1, [sp, #1048] + 518c: e2910050 adds r0, r1, #80 ; 0x50 + 5190: e58d0418 str r0, [sp, #1048] + 5194: ebf5fb79 bl 0xffd83f80 + 5198: 080c0a88 stmeqda ip, {r3, r7, r9, fp} + 519c: e3570000 cmp r7, #0 ; 0x0 + 51a0: ebf5fb76 bl 0xffd83f80 + 51a4: 080c0a8a stmeqda ip, {r1, r3, r7, r9, fp} + 51a8: e28cc016 add ip, ip, #22 ; 0x16 + 51ac: 0a000004 beq 0x51c4 + 51b0: e1a00fac mov r0, ip, lsr #31 + 51b4: e08ff100 add pc, pc, r0, lsl #2 + 51b8: 080c0a7e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, fp} + 51bc: ebf5f764 bl 0xffd82f54 + 51c0: eaffffdc b 0x5138 + 51c4: ebf5fb6d bl 0xffd83f80 + 51c8: 080c0a8c stmeqda ip, {r2, r3, r7, r9, fp} + 51cc: e2880020 add r0, r8, #32 ; 0x20 + 51d0: ebf5f9d0 bl 0xffd83918 + 51d4: 080c0a90 stmeqda ip, {r4, r7, r9, fp} + 51d8: e1a03000 mov r3, r0 + 51dc: ebf5fb67 bl 0xffd83f80 + 51e0: 080c0a8e stmeqda ip, {r1, r2, r3, r7, r9, fp} + 51e4: e3530000 cmp r3, #0 ; 0x0 + 51e8: ebf5fb64 bl 0xffd83f80 + 51ec: 080c0a90 stmeqda ip, {r4, r7, r9, fp} + 51f0: e28cc00b add ip, ip, #11 ; 0xb + 51f4: 1a000004 bne 0x520c + 51f8: e1a00fac mov r0, ip, lsr #31 + 51fc: e08ff100 add pc, pc, r0, lsl #2 + 5200: 080c0a9c stmeqda ip, {r2, r3, r4, r7, r9, fp} + 5204: ebf5f752 bl 0xffd82f54 + 5208: ea00001d b 0x5284 + 520c: ebf5fb5b bl 0xffd83f80 + 5210: 080c0a92 stmeqda ip, {r1, r4, r7, r9, fp} + 5214: e59d041c ldr r0, [sp, #1052] + 5218: e2800038 add r0, r0, #56 ; 0x38 + 521c: e1a01003 mov r1, r3 + 5220: ebf5f8e9 bl 0xffd835cc + 5224: 080c0a94 stmeqda ip, {r2, r4, r7, r9, fp} + 5228: ebf5fb54 bl 0xffd83f80 + 522c: 080c0a94 stmeqda ip, {r2, r4, r7, r9, fp} + 5230: e2880024 add r0, r8, #36 ; 0x24 + 5234: ebf5f9b7 bl 0xffd83918 + 5238: 080c0a98 stmeqda ip, {r3, r4, r7, r9, fp} + 523c: e1a03000 mov r3, r0 + 5240: ebf5fb4e bl 0xffd83f80 + 5244: 080c0a96 stmeqda ip, {r1, r2, r4, r7, r9, fp} + 5248: e59d041c ldr r0, [sp, #1052] + 524c: e280003c add r0, r0, #60 ; 0x3c + 5250: e1a01003 mov r1, r3 + 5254: ebf5f8dc bl 0xffd835cc + 5258: 080c0a98 stmeqda ip, {r3, r4, r7, r9, fp} + 525c: ebf5fb47 bl 0xffd83f80 + 5260: 080c0a98 stmeqda ip, {r3, r4, r7, r9, fp} + 5264: e3b03000 movs r3, #0 ; 0x0 + 5268: ebf5fb44 bl 0xffd83f80 + 526c: 080c0a9a stmeqda ip, {r1, r3, r4, r7, r9, fp} + 5270: e2880020 add r0, r8, #32 ; 0x20 + 5274: e1a01003 mov r1, r3 + 5278: ebf5f8d3 bl 0xffd835cc + 527c: 080c0a9c stmeqda ip, {r2, r3, r4, r7, r9, fp} + 5280: e28cc014 add ip, ip, #20 ; 0x14 + 5284: ebf5fb3d bl 0xffd83f80 + 5288: 080c0a9c stmeqda ip, {r2, r3, r4, r7, r9, fp} + 528c: e2880024 add r0, r8, #36 ; 0x24 + 5290: e59d141c ldr r1, [sp, #1052] + 5294: ebf5f8cc bl 0xffd835cc + 5298: 080c0a9e stmeqda ip, {r1, r2, r3, r4, r7, r9, fp} + 529c: ebf5fb37 bl 0xffd83f80 + 52a0: 080c0a9e stmeqda ip, {r1, r2, r3, r4, r7, r9, fp} + 52a4: e3a00fae mov r0, #696 ; 0x2b8 + 52a8: e3800b02 orr r0, r0, #2048 ; 0x800 + 52ac: e3800703 orr r0, r0, #786432 ; 0xc0000 + 52b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 52b4: ebf5f997 bl 0xffd83918 + 52b8: 080c0aa2 stmeqda ip, {r1, r5, r7, r9, fp} + 52bc: e1a03000 mov r3, r0 + 52c0: ebf5fb2e bl 0xffd83f80 + 52c4: 080c0aa0 stmeqda ip, {r5, r7, r9, fp} + 52c8: e2880020 add r0, r8, #32 ; 0x20 + 52cc: e1a01003 mov r1, r3 + 52d0: ebf5f8bd bl 0xffd835cc + 52d4: 080c0aa2 stmeqda ip, {r1, r5, r7, r9, fp} + 52d8: ebf5fb28 bl 0xffd83f80 + 52dc: 080c0aa2 stmeqda ip, {r1, r5, r7, r9, fp} + 52e0: e3a00fad mov r0, #692 ; 0x2b4 + 52e4: e3800b02 orr r0, r0, #2048 ; 0x800 + 52e8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 52ec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 52f0: ebf5f988 bl 0xffd83918 + 52f4: 080c0aa6 stmeqda ip, {r1, r2, r5, r7, r9, fp} + 52f8: e1a03000 mov r3, r0 + 52fc: ebf5fb1f bl 0xffd83f80 + 5300: 080c0aa4 stmeqda ip, {r2, r5, r7, r9, fp} + 5304: e2880000 add r0, r8, #0 ; 0x0 + 5308: e1a01003 mov r1, r3 + 530c: ebf5f8ae bl 0xffd835cc + 5310: 080c0aa6 stmeqda ip, {r1, r2, r5, r7, r9, fp} + 5314: ebf5fb19 bl 0xffd83f80 + 5318: 080c0aa6 stmeqda ip, {r1, r2, r5, r7, r9, fp} + 531c: e59d041c ldr r0, [sp, #1052] + 5320: e2800034 add r0, r0, #52 ; 0x34 + 5324: e1a01003 mov r1, r3 + 5328: ebf5f8a7 bl 0xffd835cc + 532c: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 5330: ebf5fb12 bl 0xffd83f80 + 5334: 080c0aa8 stmeqda ip, {r3, r5, r7, r9, fp} + 5338: e59d9434 ldr r9, [sp, #1076] + 533c: e3c99003 bic r9, r9, #3 ; 0x3 + 5340: e2890010 add r0, r9, #16 ; 0x10 + 5344: e58d0434 str r0, [sp, #1076] + 5348: e2890000 add r0, r9, #0 ; 0x0 + 534c: ebf5f971 bl 0xffd83918 + 5350: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 5354: e1a07000 mov r7, r0 + 5358: e2890004 add r0, r9, #4 ; 0x4 + 535c: ebf5f96d bl 0xffd83918 + 5360: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 5364: e1a08000 mov r8, r0 + 5368: e2890008 add r0, r9, #8 ; 0x8 + 536c: ebf5f969 bl 0xffd83918 + 5370: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 5374: e58d0418 str r0, [sp, #1048] + 5378: e289000c add r0, r9, #12 ; 0xc + 537c: ebf5f965 bl 0xffd83918 + 5380: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 5384: e58d041c str r0, [sp, #1052] + 5388: ebf5fafc bl 0xffd83f80 + 538c: 080c0aaa stmeqda ip, {r1, r3, r5, r7, r9, fp} + 5390: e59d9434 ldr r9, [sp, #1076] + 5394: e3c99003 bic r9, r9, #3 ; 0x3 + 5398: e2890004 add r0, r9, #4 ; 0x4 + 539c: e58d0434 str r0, [sp, #1076] + 53a0: e2890000 add r0, r9, #0 ; 0x0 + 53a4: ebf5f95b bl 0xffd83918 + 53a8: 080c0aae stmeqda ip, {r1, r2, r3, r5, r7, r9, fp} + 53ac: e1a03000 mov r3, r0 + 53b0: ebf5faf2 bl 0xffd83f80 + 53b4: 080c0aac stmeqda ip, {r2, r3, r5, r7, r9, fp} + 53b8: e1a00003 mov r0, r3 + 53bc: e28cc028 add ip, ip, #40 ; 0x28 + 53c0: eaf5f742 b 0xffd830d0 + 53c4: 080c03f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, r9} + 53c8: 00000000 andeq r0, r0, r0 + 53cc: ebf5faeb bl 0xffd83f80 + 53d0: 080c03f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, r9} + 53d4: e3a00f0b mov r0, #44 ; 0x2c + 53d8: e3800b01 orr r0, r0, #1024 ; 0x400 + 53dc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 53e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 53e4: ebf5f94b bl 0xffd83918 + 53e8: 080c03f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, r9} + 53ec: e1a03000 mov r3, r0 + 53f0: ebf5fae2 bl 0xffd83f80 + 53f4: 080c03f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, r9} + 53f8: e2870018 add r0, r7, #24 ; 0x18 + 53fc: e1a01003 mov r1, r3 + 5400: ebf5f871 bl 0xffd835cc + 5404: 080c03f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, r9} + 5408: ebf5fadc bl 0xffd83f80 + 540c: 080c03f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, r9} + 5410: e1a01008 mov r1, r8 + 5414: e298800c adds r8, r8, #12 ; 0xc + 5418: ebf5fad8 bl 0xffd83f80 + 541c: 080c03f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, r9} + 5420: e59d141c ldr r1, [sp, #1052] + 5424: e59d141c ldr r1, [sp, #1052] + 5428: e291000c adds r0, r1, #12 ; 0xc + 542c: e58d041c str r0, [sp, #1052] + 5430: ebf5fad2 bl 0xffd83f80 + 5434: 080c03fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, r9} + 5438: e59d1418 ldr r1, [sp, #1048] + 543c: e59d1418 ldr r1, [sp, #1048] + 5440: e2510001 subs r0, r1, #1 ; 0x1 + 5444: e58d0418 str r0, [sp, #1048] + 5448: ebf5facc bl 0xffd83f80 + 544c: 080c03fc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, r9} + 5450: e59d1418 ldr r1, [sp, #1048] + 5454: e3510000 cmp r1, #0 ; 0x0 + 5458: ebf5fac8 bl 0xffd83f80 + 545c: 080c03fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, r9} + 5460: e28cc018 add ip, ip, #24 ; 0x18 + 5464: 0a000004 beq 0x547c + 5468: e1a00fac mov r0, ip, lsr #31 + 546c: e08ff100 add pc, pc, r0, lsl #2 + 5470: 080c03e0 stmeqda ip, {r5, r6, r7, r8, r9} + 5474: ebf5f6b6 bl 0xffd82f54 + 5478: ea000034 b 0x5550 + 547c: ebf5fabf bl 0xffd83f80 + 5480: 080c0400 stmeqda ip, {sl} + 5484: e59d9434 ldr r9, [sp, #1076] + 5488: e3c99003 bic r9, r9, #3 ; 0x3 + 548c: e2890004 add r0, r9, #4 ; 0x4 + 5490: e58d0434 str r0, [sp, #1076] + 5494: e2890000 add r0, r9, #0 ; 0x0 + 5498: ebf5f91e bl 0xffd83918 + 549c: 080c0404 stmeqda ip, {r2, sl} + 54a0: e1a06000 mov r6, r0 + 54a4: ebf5fab5 bl 0xffd83f80 + 54a8: 080c0402 stmeqda ip, {r1, sl} + 54ac: e1a00006 mov r0, r6 + 54b0: e58d0420 str r0, [sp, #1056] + 54b4: ebf5fab1 bl 0xffd83f80 + 54b8: 080c0404 stmeqda ip, {r2, sl} + 54bc: e59d9434 ldr r9, [sp, #1076] + 54c0: e3c99003 bic r9, r9, #3 ; 0x3 + 54c4: e2890010 add r0, r9, #16 ; 0x10 + 54c8: e58d0434 str r0, [sp, #1076] + 54cc: e2890000 add r0, r9, #0 ; 0x0 + 54d0: ebf5f910 bl 0xffd83918 + 54d4: 080c0408 stmeqda ip, {r3, sl} + 54d8: e1a07000 mov r7, r0 + 54dc: e2890004 add r0, r9, #4 ; 0x4 + 54e0: ebf5f90c bl 0xffd83918 + 54e4: 080c0408 stmeqda ip, {r3, sl} + 54e8: e1a08000 mov r8, r0 + 54ec: e2890008 add r0, r9, #8 ; 0x8 + 54f0: ebf5f908 bl 0xffd83918 + 54f4: 080c0408 stmeqda ip, {r3, sl} + 54f8: e58d0418 str r0, [sp, #1048] + 54fc: e289000c add r0, r9, #12 ; 0xc + 5500: ebf5f904 bl 0xffd83918 + 5504: 080c0408 stmeqda ip, {r3, sl} + 5508: e58d041c str r0, [sp, #1052] + 550c: ebf5fa9b bl 0xffd83f80 + 5510: 080c0406 stmeqda ip, {r1, r2, sl} + 5514: e59d9434 ldr r9, [sp, #1076] + 5518: e3c99003 bic r9, r9, #3 ; 0x3 + 551c: e2890004 add r0, r9, #4 ; 0x4 + 5520: e58d0434 str r0, [sp, #1076] + 5524: e2890000 add r0, r9, #0 ; 0x0 + 5528: ebf5f8fa bl 0xffd83918 + 552c: 080c040a stmeqda ip, {r1, r3, sl} + 5530: e1a03000 mov r3, r0 + 5534: ebf5fa91 bl 0xffd83f80 + 5538: 080c0408 stmeqda ip, {r3, sl} + 553c: e1a00003 mov r0, r3 + 5540: e28cc015 add ip, ip, #21 ; 0x15 + 5544: eaf5f6e1 b 0xffd830d0 + 5548: 080c03e0 stmeqda ip, {r5, r6, r7, r8, r9} + 554c: 00000000 andeq r0, r0, r0 + 5550: ebf5fa8a bl 0xffd83f80 + 5554: 080c03e0 stmeqda ip, {r5, r6, r7, r8, r9} + 5558: e2880000 add r0, r8, #0 ; 0x0 + 555c: ebf5f8ed bl 0xffd83918 + 5560: 080c03e4 stmeqda ip, {r2, r5, r6, r7, r8, r9} + 5564: e1a07000 mov r7, r0 + 5568: ebf5fa84 bl 0xffd83f80 + 556c: 080c03e2 stmeqda ip, {r1, r5, r6, r7, r8, r9} + 5570: e59d1420 ldr r1, [sp, #1056] + 5574: e1a03001 mov r3, r1 + 5578: ebf5fa80 bl 0xffd83f80 + 557c: 080c03e4 stmeqda ip, {r2, r5, r6, r7, r8, r9} + 5580: e1a01003 mov r1, r3 + 5584: e2933004 adds r3, r3, #4 ; 0x4 + 5588: ebf5fa7c bl 0xffd83f80 + 558c: 080c03e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9} + 5590: e59d141c ldr r1, [sp, #1052] + 5594: e59d141c ldr r1, [sp, #1052] + 5598: e0913003 adds r3, r1, r3 + 559c: ebf5fa77 bl 0xffd83f80 + 55a0: 080c03e8 stmeqda ip, {r3, r5, r6, r7, r8, r9} + 55a4: e2830000 add r0, r3, #0 ; 0x0 + 55a8: ebf5f8da bl 0xffd83918 + 55ac: 080c03ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9} + 55b0: e1a04000 mov r4, r0 + 55b4: ebf5fa71 bl 0xffd83f80 + 55b8: 080c03ea stmeqda ip, {r1, r3, r5, r6, r7, r8, r9} + 55bc: e2880008 add r0, r8, #8 ; 0x8 + 55c0: ebf5f87d bl 0xffd837bc + 55c4: 080c03ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9} + 55c8: e1a05000 mov r5, r0 + 55cc: ebf5fa6b bl 0xffd83f80 + 55d0: 080c03ec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9} + 55d4: e1a01007 mov r1, r7 + 55d8: e2973000 adds r3, r7, #0 ; 0x0 + 55dc: ebf5fa67 bl 0xffd83f80 + 55e0: 080c03ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9} + 55e4: ebf5fa65 bl 0xffd83f80 + 55e8: 080c03f0 stmeqda ip, {r4, r5, r6, r7, r8, r9} + 55ec: e3a000f3 mov r0, #243 ; 0xf3 + 55f0: e3800c03 orr r0, r0, #768 ; 0x300 + 55f4: e3800703 orr r0, r0, #786432 ; 0xc0000 + 55f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 55fc: e58d0438 str r0, [sp, #1080] + 5600: e28cc021 add ip, ip, #33 ; 0x21 + 5604: e1a00fac mov r0, ip, lsr #31 + 5608: e08ff100 add pc, pc, r0, lsl #2 + 560c: 080c0a44 stmeqda ip, {r2, r6, r9, fp} + 5610: ebf5f64f bl 0xffd82f54 + 5614: eafffd42 b 0x4b24 + 5618: 080002d6 stmeqda r0, {r1, r2, r4, r6, r7, r9} + 561c: 00000000 andeq r0, r0, r0 + 5620: ebf5fa56 bl 0xffd83f80 + 5624: 080002d6 stmeqda r0, {r1, r2, r4, r6, r7, r9} + 5628: e3a00e42 mov r0, #1056 ; 0x420 + 562c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5630: ebf5f8b8 bl 0xffd83918 + 5634: 080002da stmeqda r0, {r1, r3, r4, r6, r7, r9} + 5638: e1a03000 mov r3, r0 + 563c: ebf5fa4f bl 0xffd83f80 + 5640: 080002d8 stmeqda r0, {r3, r4, r6, r7, r9} + 5644: e2830004 add r0, r3, #4 ; 0x4 + 5648: ebf5f8b2 bl 0xffd83918 + 564c: 080002dc stmeqda r0, {r2, r3, r4, r6, r7, r9} + 5650: e1a04000 mov r4, r0 + 5654: ebf5fa49 bl 0xffd83f80 + 5658: 080002da stmeqda r0, {r1, r3, r4, r6, r7, r9} + 565c: e2830000 add r0, r3, #0 ; 0x0 + 5660: ebf5f8ac bl 0xffd83918 + 5664: 080002de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9} + 5668: e1a03000 mov r3, r0 + 566c: ebf5fa43 bl 0xffd83f80 + 5670: 080002dc stmeqda r0, {r2, r3, r4, r6, r7, r9} + 5674: e1a01004 mov r1, r4 + 5678: e0544003 subs r4, r4, r3 + 567c: ebf5fa3f bl 0xffd83f80 + 5680: 080002de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9} + 5684: e3540000 cmp r4, #0 ; 0x0 + 5688: ebf5fa3c bl 0xffd83f80 + 568c: 080002e0 stmeqda r0, {r5, r6, r7, r9} + 5690: e28cc018 add ip, ip, #24 ; 0x18 + 5694: ca000004 bgt 0x56ac + 5698: e1a00fac mov r0, ip, lsr #31 + 569c: e08ff100 add pc, pc, r0, lsl #2 + 56a0: 080002f2 stmeqda r0, {r1, r4, r5, r6, r7, r9} + 56a4: ebf5f62a bl 0xffd82f54 + 56a8: ea000025 b 0x5744 + 56ac: ebf5fa33 bl 0xffd83f80 + 56b0: 080002e2 stmeqda r0, {r1, r5, r6, r7, r9} + 56b4: e2870000 add r0, r7, #0 ; 0x0 + 56b8: e1a01003 mov r1, r3 + 56bc: ebf5f7c2 bl 0xffd835cc + 56c0: 080002e4 stmeqda r0, {r2, r5, r6, r7, r9} + 56c4: ebf5fa2d bl 0xffd83f80 + 56c8: 080002e4 stmeqda r0, {r2, r5, r6, r7, r9} + 56cc: e2870004 add r0, r7, #4 ; 0x4 + 56d0: e59d141c ldr r1, [sp, #1052] + 56d4: ebf5f7bc bl 0xffd835cc + 56d8: 080002e6 stmeqda r0, {r1, r2, r5, r6, r7, r9} + 56dc: ebf5fa27 bl 0xffd83f80 + 56e0: 080002e6 stmeqda r0, {r1, r2, r5, r6, r7, r9} + 56e4: e1b03144 movs r3, r4, asr #2 + 56e8: ebf5fa24 bl 0xffd83f80 + 56ec: 080002e8 stmeqda r0, {r3, r5, r6, r7, r9} + 56f0: e3b04084 movs r4, #132 ; 0x84 + 56f4: ebf5fa21 bl 0xffd83f80 + 56f8: 080002ea stmeqda r0, {r1, r3, r5, r6, r7, r9} + 56fc: e1b04c04 movs r4, r4, lsl #24 + 5700: ebf5fa1e bl 0xffd83f80 + 5704: 080002ec stmeqda r0, {r2, r3, r5, r6, r7, r9} + 5708: e1a01003 mov r1, r3 + 570c: e1933004 orrs r3, r3, r4 + 5710: ebf5fa1a bl 0xffd83f80 + 5714: 080002ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9} + 5718: e2870008 add r0, r7, #8 ; 0x8 + 571c: e1a01003 mov r1, r3 + 5720: ebf5f7a9 bl 0xffd835cc + 5724: 080002f0 stmeqda r0, {r4, r5, r6, r7, r9} + 5728: ebf5fa14 bl 0xffd83f80 + 572c: 080002f0 stmeqda r0, {r4, r5, r6, r7, r9} + 5730: e2870008 add r0, r7, #8 ; 0x8 + 5734: ebf5f877 bl 0xffd83918 + 5738: 080002f4 stmeqda r0, {r2, r4, r5, r6, r7, r9} + 573c: e1a03000 mov r3, r0 + 5740: e28cc01d add ip, ip, #29 ; 0x1d + 5744: ebf5fa0d bl 0xffd83f80 + 5748: 080002f2 stmeqda r0, {r1, r4, r5, r6, r7, r9} + 574c: e3a00f09 mov r0, #36 ; 0x24 + 5750: e3800b01 orr r0, r0, #1024 ; 0x400 + 5754: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5758: ebf5f86e bl 0xffd83918 + 575c: 080002f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9} + 5760: e1a03000 mov r3, r0 + 5764: ebf5fa05 bl 0xffd83f80 + 5768: 080002f4 stmeqda r0, {r2, r4, r5, r6, r7, r9} + 576c: e2870000 add r0, r7, #0 ; 0x0 + 5770: e1a01003 mov r1, r3 + 5774: ebf5f794 bl 0xffd835cc + 5778: 080002f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9} + 577c: ebf5f9ff bl 0xffd83f80 + 5780: 080002f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9} + 5784: e3a00f0a mov r0, #40 ; 0x28 + 5788: e3800b01 orr r0, r0, #1024 ; 0x400 + 578c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5790: ebf5f860 bl 0xffd83918 + 5794: 080002fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9} + 5798: e1a04000 mov r4, r0 + 579c: ebf5f9f7 bl 0xffd83f80 + 57a0: 080002f8 stmeqda r0, {r3, r4, r5, r6, r7, r9} + 57a4: e2870004 add r0, r7, #4 ; 0x4 + 57a8: e1a01004 mov r1, r4 + 57ac: ebf5f786 bl 0xffd835cc + 57b0: 080002fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9} + 57b4: ebf5f9f1 bl 0xffd83f80 + 57b8: 080002fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9} + 57bc: e3a00f0b mov r0, #44 ; 0x2c + 57c0: e3800b01 orr r0, r0, #1024 ; 0x400 + 57c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 57c8: ebf5f852 bl 0xffd83918 + 57cc: 080002fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9} + 57d0: e1a03000 mov r3, r0 + 57d4: ebf5f9e9 bl 0xffd83f80 + 57d8: 080002fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9} + 57dc: e2870008 add r0, r7, #8 ; 0x8 + 57e0: e1a01003 mov r1, r3 + 57e4: ebf5f778 bl 0xffd835cc + 57e8: 080002fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9} + 57ec: ebf5f9e3 bl 0xffd83f80 + 57f0: 080002fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9} + 57f4: e2870008 add r0, r7, #8 ; 0x8 + 57f8: ebf5f846 bl 0xffd83918 + 57fc: 08000302 stmeqda r0, {r1, r8, r9} + 5800: e1a03000 mov r3, r0 + 5804: ebf5f9dd bl 0xffd83f80 + 5808: 08000300 stmeqda r0, {r8, r9} + 580c: e3a00e43 mov r0, #1072 ; 0x430 + 5810: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5814: ebf5f83f bl 0xffd83918 + 5818: 08000304 stmeqda r0, {r2, r8, r9} + 581c: e1a03000 mov r3, r0 + 5820: ebf5f9d6 bl 0xffd83f80 + 5824: 08000302 stmeqda r0, {r1, r8, r9} + 5828: e2830000 add r0, r3, #0 ; 0x0 + 582c: e1a01004 mov r1, r4 + 5830: ebf5f765 bl 0xffd835cc + 5834: 08000304 stmeqda r0, {r2, r8, r9} + 5838: ebf5f9d0 bl 0xffd83f80 + 583c: 08000304 stmeqda r0, {r2, r8, r9} + 5840: e3a00f0d mov r0, #52 ; 0x34 + 5844: e3800b01 orr r0, r0, #1024 ; 0x400 + 5848: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 584c: ebf5f831 bl 0xffd83918 + 5850: 08000308 stmeqda r0, {r3, r8, r9} + 5854: e1a05000 mov r5, r0 + 5858: ebf5f9c8 bl 0xffd83f80 + 585c: 08000306 stmeqda r0, {r1, r2, r8, r9} + 5860: e2850000 add r0, r5, #0 ; 0x0 + 5864: ebf5f7ff bl 0xffd83868 + 5868: 0800030a stmeqda r0, {r1, r3, r8, r9} + 586c: e1a03000 mov r3, r0 + 5870: ebf5f9c2 bl 0xffd83f80 + 5874: 08000308 stmeqda r0, {r3, r8, r9} + 5878: e1a01003 mov r1, r3 + 587c: e59d0418 ldr r0, [sp, #1048] + 5880: e0133000 ands r3, r3, r0 + 5884: ebf5f9bd bl 0xffd83f80 + 5888: 0800030a stmeqda r0, {r1, r3, r8, r9} + 588c: e2850000 add r0, r5, #0 ; 0x0 + 5890: e1a01003 mov r1, r3 + 5894: ebf5f72c bl 0xffd8354c + 5898: 0800030c stmeqda r0, {r2, r3, r8, r9} + 589c: ebf5f9b7 bl 0xffd83f80 + 58a0: 0800030c stmeqda r0, {r2, r3, r8, r9} + 58a4: e3a00f0e mov r0, #56 ; 0x38 + 58a8: e3800b01 orr r0, r0, #1024 ; 0x400 + 58ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 58b0: ebf5f818 bl 0xffd83918 + 58b4: 08000310 stmeqda r0, {r4, r8, r9} + 58b8: e1a03000 mov r3, r0 + 58bc: ebf5f9af bl 0xffd83f80 + 58c0: 0800030e stmeqda r0, {r1, r2, r3, r8, r9} + 58c4: e3b04001 movs r4, #1 ; 0x1 + 58c8: ebf5f9ac bl 0xffd83f80 + 58cc: 08000310 stmeqda r0, {r4, r8, r9} + 58d0: e2830000 add r0, r3, #0 ; 0x0 + 58d4: e1a01004 mov r1, r4 + 58d8: ebf5f71b bl 0xffd8354c + 58dc: 08000312 stmeqda r0, {r1, r4, r8, r9} + 58e0: ebf5f9a6 bl 0xffd83f80 + 58e4: 08000312 stmeqda r0, {r1, r4, r8, r9} + 58e8: e2850000 add r0, r5, #0 ; 0x0 + 58ec: ebf5f7dd bl 0xffd83868 + 58f0: 08000316 stmeqda r0, {r1, r2, r4, r8, r9} + 58f4: e1a03000 mov r3, r0 + 58f8: ebf5f9a0 bl 0xffd83f80 + 58fc: 08000314 stmeqda r0, {r2, r4, r8, r9} + 5900: e1a01003 mov r1, r3 + 5904: e1933004 orrs r3, r3, r4 + 5908: ebf5f99c bl 0xffd83f80 + 590c: 08000316 stmeqda r0, {r1, r2, r4, r8, r9} + 5910: e2850000 add r0, r5, #0 ; 0x0 + 5914: e1a01003 mov r1, r3 + 5918: ebf5f70b bl 0xffd8354c + 591c: 08000318 stmeqda r0, {r3, r4, r8, r9} + 5920: ebf5f996 bl 0xffd83f80 + 5924: 08000318 stmeqda r0, {r3, r4, r8, r9} + 5928: e2850000 add r0, r5, #0 ; 0x0 + 592c: ebf5f7cd bl 0xffd83868 + 5930: 0800031c stmeqda r0, {r2, r3, r4, r8, r9} + 5934: e1a03000 mov r3, r0 + 5938: ebf5f990 bl 0xffd83f80 + 593c: 0800031a stmeqda r0, {r1, r3, r4, r8, r9} + 5940: e3b04010 movs r4, #16 ; 0x10 + 5944: ebf5f98d bl 0xffd83f80 + 5948: 0800031c stmeqda r0, {r2, r3, r4, r8, r9} + 594c: e1a01003 mov r1, r3 + 5950: e1933004 orrs r3, r3, r4 + 5954: ebf5f989 bl 0xffd83f80 + 5958: 0800031e stmeqda r0, {r1, r2, r3, r4, r8, r9} + 595c: e2850000 add r0, r5, #0 ; 0x0 + 5960: e1a01003 mov r1, r3 + 5964: ebf5f6f8 bl 0xffd8354c + 5968: 08000320 stmeqda r0, {r5, r8, r9} + 596c: ebf5f983 bl 0xffd83f80 + 5970: 08000320 stmeqda r0, {r5, r8, r9} + 5974: e2850000 add r0, r5, #0 ; 0x0 + 5978: ebf5f7ba bl 0xffd83868 + 597c: 08000324 stmeqda r0, {r2, r5, r8, r9} + 5980: e1a03000 mov r3, r0 + 5984: ebf5f97d bl 0xffd83f80 + 5988: 08000322 stmeqda r0, {r1, r5, r8, r9} + 598c: e3b06080 movs r6, #128 ; 0x80 + 5990: ebf5f97a bl 0xffd83f80 + 5994: 08000324 stmeqda r0, {r2, r5, r8, r9} + 5998: e1b06106 movs r6, r6, lsl #2 + 599c: ebf5f977 bl 0xffd83f80 + 59a0: 08000326 stmeqda r0, {r1, r2, r5, r8, r9} + 59a4: e1a01006 mov r1, r6 + 59a8: e2964000 adds r4, r6, #0 ; 0x0 + 59ac: ebf5f973 bl 0xffd83f80 + 59b0: 08000328 stmeqda r0, {r3, r5, r8, r9} + 59b4: e1a01003 mov r1, r3 + 59b8: e1933004 orrs r3, r3, r4 + 59bc: ebf5f96f bl 0xffd83f80 + 59c0: 0800032a stmeqda r0, {r1, r3, r5, r8, r9} + 59c4: e2850000 add r0, r5, #0 ; 0x0 + 59c8: e1a01003 mov r1, r3 + 59cc: ebf5f6de bl 0xffd8354c + 59d0: 0800032c stmeqda r0, {r2, r3, r5, r8, r9} + 59d4: ebf5f969 bl 0xffd83f80 + 59d8: 0800032c stmeqda r0, {r2, r3, r5, r8, r9} + 59dc: e2850000 add r0, r5, #0 ; 0x0 + 59e0: ebf5f7a0 bl 0xffd83868 + 59e4: 08000330 stmeqda r0, {r4, r5, r8, r9} + 59e8: e1a03000 mov r3, r0 + 59ec: ebf5f963 bl 0xffd83f80 + 59f0: 0800032e stmeqda r0, {r1, r2, r3, r5, r8, r9} + 59f4: e3b04004 movs r4, #4 ; 0x4 + 59f8: ebf5f960 bl 0xffd83f80 + 59fc: 08000330 stmeqda r0, {r4, r5, r8, r9} + 5a00: e1a01003 mov r1, r3 + 5a04: e1933004 orrs r3, r3, r4 + 5a08: ebf5f95c bl 0xffd83f80 + 5a0c: 08000332 stmeqda r0, {r1, r4, r5, r8, r9} + 5a10: e2850000 add r0, r5, #0 ; 0x0 + 5a14: e1a01003 mov r1, r3 + 5a18: ebf5f6cb bl 0xffd8354c + 5a1c: 08000334 stmeqda r0, {r2, r4, r5, r8, r9} + 5a20: ebf5f956 bl 0xffd83f80 + 5a24: 08000334 stmeqda r0, {r2, r4, r5, r8, r9} + 5a28: e2850000 add r0, r5, #0 ; 0x0 + 5a2c: ebf5f78d bl 0xffd83868 + 5a30: 08000338 stmeqda r0, {r3, r4, r5, r8, r9} + 5a34: e1a03000 mov r3, r0 + 5a38: ebf5f950 bl 0xffd83f80 + 5a3c: 08000336 stmeqda r0, {r1, r2, r4, r5, r8, r9} + 5a40: e3b06080 movs r6, #128 ; 0x80 + 5a44: ebf5f94d bl 0xffd83f80 + 5a48: 08000338 stmeqda r0, {r3, r4, r5, r8, r9} + 5a4c: e1b06306 movs r6, r6, lsl #6 + 5a50: ebf5f94a bl 0xffd83f80 + 5a54: 0800033a stmeqda r0, {r1, r3, r4, r5, r8, r9} + 5a58: e1a01006 mov r1, r6 + 5a5c: e2964000 adds r4, r6, #0 ; 0x0 + 5a60: ebf5f946 bl 0xffd83f80 + 5a64: 0800033c stmeqda r0, {r2, r3, r4, r5, r8, r9} + 5a68: e1a01003 mov r1, r3 + 5a6c: e1933004 orrs r3, r3, r4 + 5a70: ebf5f942 bl 0xffd83f80 + 5a74: 0800033e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9} + 5a78: e2850000 add r0, r5, #0 ; 0x0 + 5a7c: e1a01003 mov r1, r3 + 5a80: ebf5f6b1 bl 0xffd8354c + 5a84: 08000340 stmeqda r0, {r6, r8, r9} + 5a88: ebf5f93c bl 0xffd83f80 + 5a8c: 08000340 stmeqda r0, {r6, r8, r9} + 5a90: e3a00f0f mov r0, #60 ; 0x3c + 5a94: e3800b01 orr r0, r0, #1024 ; 0x400 + 5a98: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5a9c: ebf5f79d bl 0xffd83918 + 5aa0: 08000344 stmeqda r0, {r2, r6, r8, r9} + 5aa4: e1a05000 mov r5, r0 + 5aa8: ebf5f934 bl 0xffd83f80 + 5aac: 08000342 stmeqda r0, {r1, r6, r8, r9} + 5ab0: e2850000 add r0, r5, #0 ; 0x0 + 5ab4: ebf5f76b bl 0xffd83868 + 5ab8: 08000346 stmeqda r0, {r1, r2, r6, r8, r9} + 5abc: e1a03000 mov r3, r0 + 5ac0: ebf5f92e bl 0xffd83f80 + 5ac4: 08000344 stmeqda r0, {r2, r6, r8, r9} + 5ac8: e3b04008 movs r4, #8 ; 0x8 + 5acc: ebf5f92b bl 0xffd83f80 + 5ad0: 08000346 stmeqda r0, {r1, r2, r6, r8, r9} + 5ad4: e1a01003 mov r1, r3 + 5ad8: e1933004 orrs r3, r3, r4 + 5adc: ebf5f927 bl 0xffd83f80 + 5ae0: 08000348 stmeqda r0, {r3, r6, r8, r9} + 5ae4: e2850000 add r0, r5, #0 ; 0x0 + 5ae8: e1a01003 mov r1, r3 + 5aec: ebf5f696 bl 0xffd8354c + 5af0: 0800034a stmeqda r0, {r1, r3, r6, r8, r9} + 5af4: ebf5f921 bl 0xffd83f80 + 5af8: 0800034a stmeqda r0, {r1, r3, r6, r8, r9} + 5afc: e3a00d11 mov r0, #1088 ; 0x440 + 5b00: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5b04: ebf5f783 bl 0xffd83918 + 5b08: 0800034e stmeqda r0, {r1, r2, r3, r6, r8, r9} + 5b0c: e1a03000 mov r3, r0 + 5b10: ebf5f91a bl 0xffd83f80 + 5b14: 0800034c stmeqda r0, {r2, r3, r6, r8, r9} + 5b18: e2830000 add r0, r3, #0 ; 0x0 + 5b1c: e1a01008 mov r1, r8 + 5b20: ebf5f689 bl 0xffd8354c + 5b24: 0800034e stmeqda r0, {r1, r2, r3, r6, r8, r9} + 5b28: ebf5f914 bl 0xffd83f80 + 5b2c: 0800034e stmeqda r0, {r1, r2, r3, r6, r8, r9} + 5b30: e28cc0ba add ip, ip, #186 ; 0xba + 5b34: ebf5f911 bl 0xffd83f80 + 5b38: 08000350 stmeqda r0, {r4, r6, r8, r9} + 5b3c: e3a00053 mov r0, #83 ; 0x53 + 5b40: e3800c03 orr r0, r0, #768 ; 0x300 + 5b44: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5b48: e58d0438 str r0, [sp, #1080] + 5b4c: e28cc003 add ip, ip, #3 ; 0x3 + 5b50: e1a00fac mov r0, ip, lsr #31 + 5b54: e08ff100 add pc, pc, r0, lsl #2 + 5b58: 08003aa0 stmeqda r0, {r5, r7, r9, fp, ip, sp} + 5b5c: ebf5f4fc bl 0xffd82f54 + 5b60: ea000001 b 0x5b6c + 5b64: 08003aa0 stmeqda r0, {r5, r7, r9, fp, ip, sp} + 5b68: 00000000 andeq r0, r0, r0 + 5b6c: ebf5f903 bl 0xffd83f80 + 5b70: 08003aa0 stmeqda r0, {r5, r7, r9, fp, ip, sp} + 5b74: e59d0434 ldr r0, [sp, #1076] + 5b78: e2400f01 sub r0, r0, #4 ; 0x4 + 5b7c: e58d0434 str r0, [sp, #1076] + 5b80: ebf5f8fe bl 0xffd83f80 + 5b84: 08003aa2 stmeqda r0, {r1, r5, r7, r9, fp, ip, sp} + 5b88: e3b03000 movs r3, #0 ; 0x0 + 5b8c: ebf5f8fb bl 0xffd83f80 + 5b90: 08003aa4 stmeqda r0, {r2, r5, r7, r9, fp, ip, sp} + 5b94: e59d0434 ldr r0, [sp, #1076] + 5b98: e2800f00 add r0, r0, #0 ; 0x0 + 5b9c: e1a01003 mov r1, r3 + 5ba0: ebf5f689 bl 0xffd835cc + 5ba4: 08003aa6 stmeqda r0, {r1, r2, r5, r7, r9, fp, ip, sp} + 5ba8: ebf5f8f4 bl 0xffd83f80 + 5bac: 08003aa6 stmeqda r0, {r1, r2, r5, r7, r9, fp, ip, sp} + 5bb0: e3a00faf mov r0, #700 ; 0x2bc + 5bb4: e3800b0e orr r0, r0, #14336 ; 0x3800 + 5bb8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5bbc: ebf5f755 bl 0xffd83918 + 5bc0: 08003aaa stmeqda r0, {r1, r3, r5, r7, r9, fp, ip, sp} + 5bc4: e1a04000 mov r4, r0 + 5bc8: ebf5f8ec bl 0xffd83f80 + 5bcc: 08003aa8 stmeqda r0, {r3, r5, r7, r9, fp, ip, sp} + 5bd0: e59d1434 ldr r1, [sp, #1076] + 5bd4: e1a03001 mov r3, r1 + 5bd8: ebf5f8e8 bl 0xffd83f80 + 5bdc: 08003aaa stmeqda r0, {r1, r3, r5, r7, r9, fp, ip, sp} + 5be0: e2840000 add r0, r4, #0 ; 0x0 + 5be4: e1a01003 mov r1, r3 + 5be8: ebf5f677 bl 0xffd835cc + 5bec: 08003aac stmeqda r0, {r2, r3, r5, r7, r9, fp, ip, sp} + 5bf0: ebf5f8e2 bl 0xffd83f80 + 5bf4: 08003aac stmeqda r0, {r2, r3, r5, r7, r9, fp, ip, sp} + 5bf8: e3a00deb mov r0, #15040 ; 0x3ac0 + 5bfc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5c00: ebf5f744 bl 0xffd83918 + 5c04: 08003ab0 stmeqda r0, {r4, r5, r7, r9, fp, ip, sp} + 5c08: e1a03000 mov r3, r0 + 5c0c: ebf5f8db bl 0xffd83f80 + 5c10: 08003aae stmeqda r0, {r1, r2, r3, r5, r7, r9, fp, ip, sp} + 5c14: e2840004 add r0, r4, #4 ; 0x4 + 5c18: e1a01003 mov r1, r3 + 5c1c: ebf5f66a bl 0xffd835cc + 5c20: 08003ab0 stmeqda r0, {r4, r5, r7, r9, fp, ip, sp} + 5c24: ebf5f8d5 bl 0xffd83f80 + 5c28: 08003ab0 stmeqda r0, {r4, r5, r7, r9, fp, ip, sp} + 5c2c: e3a00fb1 mov r0, #708 ; 0x2c4 + 5c30: e3800b0e orr r0, r0, #14336 ; 0x3800 + 5c34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5c38: ebf5f736 bl 0xffd83918 + 5c3c: 08003ab4 stmeqda r0, {r2, r4, r5, r7, r9, fp, ip, sp} + 5c40: e1a03000 mov r3, r0 + 5c44: ebf5f8cd bl 0xffd83f80 + 5c48: 08003ab2 stmeqda r0, {r1, r4, r5, r7, r9, fp, ip, sp} + 5c4c: e2840008 add r0, r4, #8 ; 0x8 + 5c50: e1a01003 mov r1, r3 + 5c54: ebf5f65c bl 0xffd835cc + 5c58: 08003ab4 stmeqda r0, {r2, r4, r5, r7, r9, fp, ip, sp} + 5c5c: ebf5f8c7 bl 0xffd83f80 + 5c60: 08003ab4 stmeqda r0, {r2, r4, r5, r7, r9, fp, ip, sp} + 5c64: e2840008 add r0, r4, #8 ; 0x8 + 5c68: ebf5f72a bl 0xffd83918 + 5c6c: 08003ab8 stmeqda r0, {r3, r4, r5, r7, r9, fp, ip, sp} + 5c70: e1a03000 mov r3, r0 + 5c74: ebf5f8c1 bl 0xffd83f80 + 5c78: 08003ab6 stmeqda r0, {r1, r2, r4, r5, r7, r9, fp, ip, sp} + 5c7c: e59d0434 ldr r0, [sp, #1076] + 5c80: e2800f01 add r0, r0, #4 ; 0x4 + 5c84: e58d0434 str r0, [sp, #1076] + 5c88: ebf5f8bc bl 0xffd83f80 + 5c8c: 08003ab8 stmeqda r0, {r3, r4, r5, r7, r9, fp, ip, sp} + 5c90: e59d0438 ldr r0, [sp, #1080] + 5c94: e28cc033 add ip, ip, #51 ; 0x33 + 5c98: eaf5f50c b 0xffd830d0 + 5c9c: 08000352 stmeqda r0, {r1, r4, r6, r8, r9} + 5ca0: 00000000 andeq r0, r0, r0 + 5ca4: ebf5f8b5 bl 0xffd83f80 + 5ca8: 08000352 stmeqda r0, {r1, r4, r6, r8, r9} + 5cac: ebf5f8b3 bl 0xffd83f80 + 5cb0: 08000354 stmeqda r0, {r2, r4, r6, r8, r9} + 5cb4: e3a00057 mov r0, #87 ; 0x57 + 5cb8: e3800c03 orr r0, r0, #768 ; 0x300 + 5cbc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5cc0: e58d0438 str r0, [sp, #1080] + 5cc4: e28cc006 add ip, ip, #6 ; 0x6 + 5cc8: e1a00fac mov r0, ip, lsr #31 + 5ccc: e08ff100 add pc, pc, r0, lsl #2 + 5cd0: 08006268 stmeqda r0, {r3, r5, r6, r9, sp, lr} + 5cd4: ebf5f49e bl 0xffd82f54 + 5cd8: ea000001 b 0x5ce4 + 5cdc: 08006268 stmeqda r0, {r3, r5, r6, r9, sp, lr} + 5ce0: 00000000 andeq r0, r0, r0 + 5ce4: ebf5f8a5 bl 0xffd83f80 + 5ce8: 08006268 stmeqda r0, {r3, r5, r6, r9, sp, lr} + 5cec: e3a00e2a mov r0, #672 ; 0x2a0 + 5cf0: e3800a06 orr r0, r0, #24576 ; 0x6000 + 5cf4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5cf8: ebf5f706 bl 0xffd83918 + 5cfc: 0800626c stmeqda r0, {r2, r3, r5, r6, r9, sp, lr} + 5d00: e1a04000 mov r4, r0 + 5d04: ebf5f89d bl 0xffd83f80 + 5d08: 0800626a stmeqda r0, {r1, r3, r5, r6, r9, sp, lr} + 5d0c: e3b050a3 movs r5, #163 ; 0xa3 + 5d10: ebf5f89a bl 0xffd83f80 + 5d14: 0800626c stmeqda r0, {r2, r3, r5, r6, r9, sp, lr} + 5d18: e1b05285 movs r5, r5, lsl #5 + 5d1c: ebf5f897 bl 0xffd83f80 + 5d20: 0800626e stmeqda r0, {r1, r2, r3, r5, r6, r9, sp, lr} + 5d24: e1a01004 mov r1, r4 + 5d28: e0943005 adds r3, r4, r5 + 5d2c: ebf5f893 bl 0xffd83f80 + 5d30: 08006270 stmeqda r0, {r4, r5, r6, r9, sp, lr} + 5d34: e3b05000 movs r5, #0 ; 0x0 + 5d38: ebf5f890 bl 0xffd83f80 + 5d3c: 08006272 stmeqda r0, {r1, r4, r5, r6, r9, sp, lr} + 5d40: e2830000 add r0, r3, #0 ; 0x0 + 5d44: e1a01005 mov r1, r5 + 5d48: ebf5f5e0 bl 0xffd834d0 + 5d4c: 08006274 stmeqda r0, {r2, r4, r5, r6, r9, sp, lr} + 5d50: ebf5f88a bl 0xffd83f80 + 5d54: 08006274 stmeqda r0, {r2, r4, r5, r6, r9, sp, lr} + 5d58: e3a00fa9 mov r0, #676 ; 0x2a4 + 5d5c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 5d60: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5d64: ebf5f6eb bl 0xffd83918 + 5d68: 08006278 stmeqda r0, {r3, r4, r5, r6, r9, sp, lr} + 5d6c: e1a06000 mov r6, r0 + 5d70: ebf5f882 bl 0xffd83f80 + 5d74: 08006276 stmeqda r0, {r1, r2, r4, r5, r6, r9, sp, lr} + 5d78: e1a01004 mov r1, r4 + 5d7c: e0943006 adds r3, r4, r6 + 5d80: ebf5f87e bl 0xffd83f80 + 5d84: 08006278 stmeqda r0, {r3, r4, r5, r6, r9, sp, lr} + 5d88: e2830000 add r0, r3, #0 ; 0x0 + 5d8c: e1a01005 mov r1, r5 + 5d90: ebf5f5ce bl 0xffd834d0 + 5d94: 0800627a stmeqda r0, {r1, r3, r4, r5, r6, r9, sp, lr} + 5d98: ebf5f878 bl 0xffd83f80 + 5d9c: 0800627a stmeqda r0, {r1, r3, r4, r5, r6, r9, sp, lr} + 5da0: e1a01006 mov r1, r6 + 5da4: e2566002 subs r6, r6, #2 ; 0x2 + 5da8: ebf5f874 bl 0xffd83f80 + 5dac: 0800627c stmeqda r0, {r2, r3, r4, r5, r6, r9, sp, lr} + 5db0: e1a01004 mov r1, r4 + 5db4: e0943006 adds r3, r4, r6 + 5db8: ebf5f870 bl 0xffd83f80 + 5dbc: 0800627e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sp, lr} + 5dc0: e2830000 add r0, r3, #0 ; 0x0 + 5dc4: e1a01005 mov r1, r5 + 5dc8: ebf5f5c0 bl 0xffd834d0 + 5dcc: 08006280 stmeqda r0, {r7, r9, sp, lr} + 5dd0: ebf5f86a bl 0xffd83f80 + 5dd4: 08006280 stmeqda r0, {r7, r9, sp, lr} + 5dd8: e1a01006 mov r1, r6 + 5ddc: e2966004 adds r6, r6, #4 ; 0x4 + 5de0: ebf5f866 bl 0xffd83f80 + 5de4: 08006282 stmeqda r0, {r1, r7, r9, sp, lr} + 5de8: e1a01004 mov r1, r4 + 5dec: e0943006 adds r3, r4, r6 + 5df0: ebf5f862 bl 0xffd83f80 + 5df4: 08006284 stmeqda r0, {r2, r7, r9, sp, lr} + 5df8: e2830000 add r0, r3, #0 ; 0x0 + 5dfc: e1a01005 mov r1, r5 + 5e00: ebf5f5b2 bl 0xffd834d0 + 5e04: 08006286 stmeqda r0, {r1, r2, r7, r9, sp, lr} + 5e08: ebf5f85c bl 0xffd83f80 + 5e0c: 08006286 stmeqda r0, {r1, r2, r7, r9, sp, lr} + 5e10: e1a01006 mov r1, r6 + 5e14: e2566005 subs r6, r6, #5 ; 0x5 + 5e18: ebf5f858 bl 0xffd83f80 + 5e1c: 08006288 stmeqda r0, {r3, r7, r9, sp, lr} + 5e20: e1a01004 mov r1, r4 + 5e24: e0943006 adds r3, r4, r6 + 5e28: ebf5f854 bl 0xffd83f80 + 5e2c: 0800628a stmeqda r0, {r1, r3, r7, r9, sp, lr} + 5e30: e2830000 add r0, r3, #0 ; 0x0 + 5e34: e1a01005 mov r1, r5 + 5e38: ebf5f5a4 bl 0xffd834d0 + 5e3c: 0800628c stmeqda r0, {r2, r3, r7, r9, sp, lr} + 5e40: ebf5f84e bl 0xffd83f80 + 5e44: 0800628c stmeqda r0, {r2, r3, r7, r9, sp, lr} + 5e48: e1a01006 mov r1, r6 + 5e4c: e2966004 adds r6, r6, #4 ; 0x4 + 5e50: ebf5f84a bl 0xffd83f80 + 5e54: 0800628e stmeqda r0, {r1, r2, r3, r7, r9, sp, lr} + 5e58: e1a01004 mov r1, r4 + 5e5c: e0943006 adds r3, r4, r6 + 5e60: ebf5f846 bl 0xffd83f80 + 5e64: 08006290 stmeqda r0, {r4, r7, r9, sp, lr} + 5e68: e2830000 add r0, r3, #0 ; 0x0 + 5e6c: e1a01005 mov r1, r5 + 5e70: ebf5f596 bl 0xffd834d0 + 5e74: 08006292 stmeqda r0, {r1, r4, r7, r9, sp, lr} + 5e78: ebf5f840 bl 0xffd83f80 + 5e7c: 08006292 stmeqda r0, {r1, r4, r7, r9, sp, lr} + 5e80: e1a01006 mov r1, r6 + 5e84: e2566002 subs r6, r6, #2 ; 0x2 + 5e88: ebf5f83c bl 0xffd83f80 + 5e8c: 08006294 stmeqda r0, {r2, r4, r7, r9, sp, lr} + 5e90: e1a01004 mov r1, r4 + 5e94: e0943006 adds r3, r4, r6 + 5e98: ebf5f838 bl 0xffd83f80 + 5e9c: 08006296 stmeqda r0, {r1, r2, r4, r7, r9, sp, lr} + 5ea0: e2830000 add r0, r3, #0 ; 0x0 + 5ea4: e1a01005 mov r1, r5 + 5ea8: ebf5f588 bl 0xffd834d0 + 5eac: 08006298 stmeqda r0, {r3, r4, r7, r9, sp, lr} + 5eb0: ebf5f832 bl 0xffd83f80 + 5eb4: 08006298 stmeqda r0, {r3, r4, r7, r9, sp, lr} + 5eb8: e3a00faa mov r0, #680 ; 0x2a8 + 5ebc: e3800a06 orr r0, r0, #24576 ; 0x6000 + 5ec0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5ec4: ebf5f693 bl 0xffd83918 + 5ec8: 0800629c stmeqda r0, {r2, r3, r4, r7, r9, sp, lr} + 5ecc: e1a03000 mov r3, r0 + 5ed0: ebf5f82a bl 0xffd83f80 + 5ed4: 0800629a stmeqda r0, {r1, r3, r4, r7, r9, sp, lr} + 5ed8: e1a01004 mov r1, r4 + 5edc: e0944003 adds r4, r4, r3 + 5ee0: ebf5f826 bl 0xffd83f80 + 5ee4: 0800629c stmeqda r0, {r2, r3, r4, r7, r9, sp, lr} + 5ee8: e2840000 add r0, r4, #0 ; 0x0 + 5eec: e1a01005 mov r1, r5 + 5ef0: ebf5f576 bl 0xffd834d0 + 5ef4: 0800629e stmeqda r0, {r1, r2, r3, r4, r7, r9, sp, lr} + 5ef8: ebf5f820 bl 0xffd83f80 + 5efc: 0800629e stmeqda r0, {r1, r2, r3, r4, r7, r9, sp, lr} + 5f00: e59d0438 ldr r0, [sp, #1080] + 5f04: e28cc062 add ip, ip, #98 ; 0x62 + 5f08: eaf5f470 b 0xffd830d0 + 5f0c: 08000356 stmeqda r0, {r1, r2, r4, r6, r8, r9} + 5f10: 00000000 andeq r0, r0, r0 + 5f14: ebf5f819 bl 0xffd83f80 + 5f18: 08000356 stmeqda r0, {r1, r2, r4, r6, r8, r9} + 5f1c: ebf5f817 bl 0xffd83f80 + 5f20: 08000358 stmeqda r0, {r3, r4, r6, r8, r9} + 5f24: e3a0005b mov r0, #91 ; 0x5b + 5f28: e3800c03 orr r0, r0, #768 ; 0x300 + 5f2c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5f30: e58d0438 str r0, [sp, #1080] + 5f34: e28cc006 add ip, ip, #6 ; 0x6 + 5f38: e1a00fac mov r0, ip, lsr #31 + 5f3c: e08ff100 add pc, pc, r0, lsl #2 + 5f40: 080036cc stmeqda r0, {r2, r3, r6, r7, r9, sl, ip, sp} + 5f44: ebf5f402 bl 0xffd82f54 + 5f48: ea000001 b 0x5f54 + 5f4c: 080036cc stmeqda r0, {r2, r3, r6, r7, r9, sl, ip, sp} + 5f50: 00000000 andeq r0, r0, r0 + 5f54: ebf5f809 bl 0xffd83f80 + 5f58: 080036cc stmeqda r0, {r2, r3, r6, r7, r9, sl, ip, sp} + 5f5c: e59d9434 ldr r9, [sp, #1076] + 5f60: e3c99003 bic r9, r9, #3 ; 0x3 + 5f64: e2499004 sub r9, r9, #4 ; 0x4 + 5f68: e58d9434 str r9, [sp, #1076] + 5f6c: e2890000 add r0, r9, #0 ; 0x0 + 5f70: e59d1438 ldr r1, [sp, #1080] + 5f74: ebf5f5b4 bl 0xffd8364c + 5f78: ebf5f800 bl 0xffd83f80 + 5f7c: 080036ce stmeqda r0, {r1, r2, r3, r6, r7, r9, sl, ip, sp} + 5f80: e59d0434 ldr r0, [sp, #1076] + 5f84: e2400f02 sub r0, r0, #8 ; 0x8 + 5f88: e58d0434 str r0, [sp, #1076] + 5f8c: ebf5f7fb bl 0xffd83f80 + 5f90: 080036d0 stmeqda r0, {r4, r6, r7, r9, sl, ip, sp} + 5f94: e3a00fc7 mov r0, #796 ; 0x31c + 5f98: e3800b0d orr r0, r0, #13312 ; 0x3400 + 5f9c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5fa0: ebf5f65c bl 0xffd83918 + 5fa4: 080036d4 stmeqda r0, {r2, r4, r6, r7, r9, sl, ip, sp} + 5fa8: e1a04000 mov r4, r0 + 5fac: ebf5f7f3 bl 0xffd83f80 + 5fb0: 080036d2 stmeqda r0, {r1, r4, r6, r7, r9, sl, ip, sp} + 5fb4: e3a00e72 mov r0, #1824 ; 0x720 + 5fb8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 5fbc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5fc0: ebf5f654 bl 0xffd83918 + 5fc4: 080036d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl, ip, sp} + 5fc8: e1a03000 mov r3, r0 + 5fcc: ebf5f7eb bl 0xffd83f80 + 5fd0: 080036d4 stmeqda r0, {r2, r4, r6, r7, r9, sl, ip, sp} + 5fd4: e2840000 add r0, r4, #0 ; 0x0 + 5fd8: e1a01003 mov r1, r3 + 5fdc: ebf5f57a bl 0xffd835cc + 5fe0: 080036d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl, ip, sp} + 5fe4: ebf5f7e5 bl 0xffd83f80 + 5fe8: 080036d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl, ip, sp} + 5fec: e3a00fc9 mov r0, #804 ; 0x324 + 5ff0: e3800b0d orr r0, r0, #13312 ; 0x3400 + 5ff4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 5ff8: ebf5f646 bl 0xffd83918 + 5ffc: 080036da stmeqda r0, {r1, r3, r4, r6, r7, r9, sl, ip, sp} + 6000: e1a04000 mov r4, r0 + 6004: ebf5f7dd bl 0xffd83f80 + 6008: 080036d8 stmeqda r0, {r3, r4, r6, r7, r9, sl, ip, sp} + 600c: e3a00fca mov r0, #808 ; 0x328 + 6010: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6014: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6018: ebf5f63e bl 0xffd83918 + 601c: 080036dc stmeqda r0, {r2, r3, r4, r6, r7, r9, sl, ip, sp} + 6020: e1a03000 mov r3, r0 + 6024: ebf5f7d5 bl 0xffd83f80 + 6028: 080036da stmeqda r0, {r1, r3, r4, r6, r7, r9, sl, ip, sp} + 602c: e2840000 add r0, r4, #0 ; 0x0 + 6030: e1a01003 mov r1, r3 + 6034: ebf5f564 bl 0xffd835cc + 6038: 080036dc stmeqda r0, {r2, r3, r4, r6, r7, r9, sl, ip, sp} + 603c: ebf5f7cf bl 0xffd83f80 + 6040: 080036dc stmeqda r0, {r2, r3, r4, r6, r7, r9, sl, ip, sp} + 6044: e3b03000 movs r3, #0 ; 0x0 + 6048: ebf5f7cc bl 0xffd83f80 + 604c: 080036de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl, ip, sp} + 6050: e3b04000 movs r4, #0 ; 0x0 + 6054: ebf5f7c9 bl 0xffd83f80 + 6058: 080036e0 stmeqda r0, {r5, r6, r7, r9, sl, ip, sp} + 605c: ebf5f7c7 bl 0xffd83f80 + 6060: 080036e2 stmeqda r0, {r1, r5, r6, r7, r9, sl, ip, sp} + 6064: e3a000e5 mov r0, #229 ; 0xe5 + 6068: e3800c36 orr r0, r0, #13824 ; 0x3600 + 606c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6070: e58d0438 str r0, [sp, #1080] + 6074: e28cc02e add ip, ip, #46 ; 0x2e + 6078: e1a00fac mov r0, ip, lsr #31 + 607c: e08ff100 add pc, pc, r0, lsl #2 + 6080: 08003638 stmeqda r0, {r3, r4, r5, r9, sl, ip, sp} + 6084: ebf5f3b2 bl 0xffd82f54 + 6088: ea000001 b 0x6094 + 608c: 08003638 stmeqda r0, {r3, r4, r5, r9, sl, ip, sp} + 6090: 00000000 andeq r0, r0, r0 + 6094: ebf5f7b9 bl 0xffd83f80 + 6098: 08003638 stmeqda r0, {r3, r4, r5, r9, sl, ip, sp} + 609c: e3a00f92 mov r0, #584 ; 0x248 + 60a0: e3800b0d orr r0, r0, #13312 ; 0x3400 + 60a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 60a8: ebf5f61a bl 0xffd83918 + 60ac: 0800363c stmeqda r0, {r2, r3, r4, r5, r9, sl, ip, sp} + 60b0: e1a05000 mov r5, r0 + 60b4: ebf5f7b1 bl 0xffd83f80 + 60b8: 0800363a stmeqda r0, {r1, r3, r4, r5, r9, sl, ip, sp} + 60bc: e2850000 add r0, r5, #0 ; 0x0 + 60c0: ebf5f614 bl 0xffd83918 + 60c4: 0800363e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, ip, sp} + 60c8: e1a05000 mov r5, r0 + 60cc: ebf5f7ab bl 0xffd83f80 + 60d0: 0800363c stmeqda r0, {r2, r3, r4, r5, r9, sl, ip, sp} + 60d4: e2850000 add r0, r5, #0 ; 0x0 + 60d8: e1a01003 mov r1, r3 + 60dc: ebf5f53a bl 0xffd835cc + 60e0: 0800363e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, ip, sp} + 60e4: ebf5f7a5 bl 0xffd83f80 + 60e8: 0800363e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, ip, sp} + 60ec: e3a00f93 mov r0, #588 ; 0x24c + 60f0: e3800b0d orr r0, r0, #13312 ; 0x3400 + 60f4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 60f8: ebf5f606 bl 0xffd83918 + 60fc: 08003642 stmeqda r0, {r1, r6, r9, sl, ip, sp} + 6100: e1a03000 mov r3, r0 + 6104: ebf5f79d bl 0xffd83f80 + 6108: 08003640 stmeqda r0, {r6, r9, sl, ip, sp} + 610c: e2830000 add r0, r3, #0 ; 0x0 + 6110: ebf5f600 bl 0xffd83918 + 6114: 08003644 stmeqda r0, {r2, r6, r9, sl, ip, sp} + 6118: e1a03000 mov r3, r0 + 611c: ebf5f797 bl 0xffd83f80 + 6120: 08003642 stmeqda r0, {r1, r6, r9, sl, ip, sp} + 6124: e2830000 add r0, r3, #0 ; 0x0 + 6128: e1a01004 mov r1, r4 + 612c: ebf5f526 bl 0xffd835cc + 6130: 08003644 stmeqda r0, {r2, r6, r9, sl, ip, sp} + 6134: ebf5f791 bl 0xffd83f80 + 6138: 08003644 stmeqda r0, {r2, r6, r9, sl, ip, sp} + 613c: e59d0438 ldr r0, [sp, #1080] + 6140: e28cc01f add ip, ip, #31 ; 0x1f + 6144: eaf5f3e1 b 0xffd830d0 + 6148: 080036e4 stmeqda r0, {r2, r5, r6, r7, r9, sl, ip, sp} + 614c: 00000000 andeq r0, r0, r0 + 6150: ebf5f78a bl 0xffd83f80 + 6154: 080036e4 stmeqda r0, {r2, r5, r6, r7, r9, sl, ip, sp} + 6158: e3a00fcb mov r0, #812 ; 0x32c + 615c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6160: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6164: ebf5f5eb bl 0xffd83918 + 6168: 080036e8 stmeqda r0, {r3, r5, r6, r7, r9, sl, ip, sp} + 616c: e1a04000 mov r4, r0 + 6170: ebf5f782 bl 0xffd83f80 + 6174: 080036e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, sl, ip, sp} + 6178: e3b03000 movs r3, #0 ; 0x0 + 617c: ebf5f77f bl 0xffd83f80 + 6180: 080036e8 stmeqda r0, {r3, r5, r6, r7, r9, sl, ip, sp} + 6184: e2840000 add r0, r4, #0 ; 0x0 + 6188: e1a01003 mov r1, r3 + 618c: ebf5f50e bl 0xffd835cc + 6190: 080036ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl, ip, sp} + 6194: ebf5f779 bl 0xffd83f80 + 6198: 080036ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl, ip, sp} + 619c: e3a00e73 mov r0, #1840 ; 0x730 + 61a0: e3800a03 orr r0, r0, #12288 ; 0x3000 + 61a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 61a8: ebf5f5da bl 0xffd83918 + 61ac: 080036ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl, ip, sp} + 61b0: e1a04000 mov r4, r0 + 61b4: ebf5f771 bl 0xffd83f80 + 61b8: 080036ec stmeqda r0, {r2, r3, r5, r6, r7, r9, sl, ip, sp} + 61bc: e2840000 add r0, r4, #0 ; 0x0 + 61c0: e1a01003 mov r1, r3 + 61c4: ebf5f500 bl 0xffd835cc + 61c8: 080036ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl, ip, sp} + 61cc: ebf5f76b bl 0xffd83f80 + 61d0: 080036ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl, ip, sp} + 61d4: e59d0434 ldr r0, [sp, #1076] + 61d8: e2800f00 add r0, r0, #0 ; 0x0 + 61dc: e1a01003 mov r1, r3 + 61e0: ebf5f4f9 bl 0xffd835cc + 61e4: 080036f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, ip, sp} + 61e8: ebf5f764 bl 0xffd83f80 + 61ec: 080036f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, ip, sp} + 61f0: e59d0434 ldr r0, [sp, #1076] + 61f4: e2800f01 add r0, r0, #4 ; 0x4 + 61f8: e1a01003 mov r1, r3 + 61fc: ebf5f4f2 bl 0xffd835cc + 6200: 080036f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sl, ip, sp} + 6204: ebf5f75d bl 0xffd83f80 + 6208: 080036f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sl, ip, sp} + 620c: e3b04000 movs r4, #0 ; 0x0 + 6210: ebf5f75a bl 0xffd83f80 + 6214: 080036f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sl, ip, sp} + 6218: e3b05000 movs r5, #0 ; 0x0 + 621c: ebf5f757 bl 0xffd83f80 + 6220: 080036f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl, ip, sp} + 6224: e3b06000 movs r6, #0 ; 0x0 + 6228: ebf5f754 bl 0xffd83f80 + 622c: 080036f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip, sp} + 6230: ebf5f752 bl 0xffd83f80 + 6234: 080036fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 6238: e3a000fd mov r0, #253 ; 0xfd + 623c: e3800c36 orr r0, r0, #13824 ; 0x3600 + 6240: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6244: e58d0438 str r0, [sp, #1080] + 6248: e28cc02c add ip, ip, #44 ; 0x2c + 624c: e1a00fac mov r0, ip, lsr #31 + 6250: e08ff100 add pc, pc, r0, lsl #2 + 6254: 08003650 stmeqda r0, {r4, r6, r9, sl, ip, sp} + 6258: ebf5f33d bl 0xffd82f54 + 625c: ea000001 b 0x6268 + 6260: 08003650 stmeqda r0, {r4, r6, r9, sl, ip, sp} + 6264: 00000000 andeq r0, r0, r0 + 6268: ebf5f744 bl 0xffd83f80 + 626c: 08003650 stmeqda r0, {r4, r6, r9, sl, ip, sp} + 6270: e59d9434 ldr r9, [sp, #1076] + 6274: e3c99003 bic r9, r9, #3 ; 0x3 + 6278: e2499010 sub r9, r9, #16 ; 0x10 + 627c: e58d9434 str r9, [sp, #1076] + 6280: e2890000 add r0, r9, #0 ; 0x0 + 6284: e1a01007 mov r1, r7 + 6288: ebf5f4ef bl 0xffd8364c + 628c: e2890004 add r0, r9, #4 ; 0x4 + 6290: e1a01008 mov r1, r8 + 6294: ebf5f4ec bl 0xffd8364c + 6298: e2890008 add r0, r9, #8 ; 0x8 + 629c: e59d1418 ldr r1, [sp, #1048] + 62a0: ebf5f4e9 bl 0xffd8364c + 62a4: e289000c add r0, r9, #12 ; 0xc + 62a8: e59d1438 ldr r1, [sp, #1080] + 62ac: ebf5f4e6 bl 0xffd8364c + 62b0: ebf5f732 bl 0xffd83f80 + 62b4: 08003652 stmeqda r0, {r1, r4, r6, r9, sl, ip, sp} + 62b8: e59d0434 ldr r0, [sp, #1076] + 62bc: e2800f04 add r0, r0, #16 ; 0x10 + 62c0: ebf5f594 bl 0xffd83918 + 62c4: 08003656 stmeqda r0, {r1, r2, r4, r6, r9, sl, ip, sp} + 62c8: e1a08000 mov r8, r0 + 62cc: ebf5f72b bl 0xffd83f80 + 62d0: 08003654 stmeqda r0, {r2, r4, r6, r9, sl, ip, sp} + 62d4: e59d0434 ldr r0, [sp, #1076] + 62d8: e2800f05 add r0, r0, #20 ; 0x14 + 62dc: ebf5f58d bl 0xffd83918 + 62e0: 08003658 stmeqda r0, {r3, r4, r6, r9, sl, ip, sp} + 62e4: e58d0418 str r0, [sp, #1048] + 62e8: ebf5f724 bl 0xffd83f80 + 62ec: 08003656 stmeqda r0, {r1, r2, r4, r6, r9, sl, ip, sp} + 62f0: e3a00f9d mov r0, #628 ; 0x274 + 62f4: e3800b0d orr r0, r0, #13312 ; 0x3400 + 62f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 62fc: ebf5f585 bl 0xffd83918 + 6300: 0800365a stmeqda r0, {r1, r3, r4, r6, r9, sl, ip, sp} + 6304: e1a07000 mov r7, r0 + 6308: ebf5f71c bl 0xffd83f80 + 630c: 08003658 stmeqda r0, {r3, r4, r6, r9, sl, ip, sp} + 6310: e2870000 add r0, r7, #0 ; 0x0 + 6314: e1a01003 mov r1, r3 + 6318: ebf5f4ab bl 0xffd835cc + 631c: 0800365a stmeqda r0, {r1, r3, r4, r6, r9, sl, ip, sp} + 6320: ebf5f716 bl 0xffd83f80 + 6324: 0800365a stmeqda r0, {r1, r3, r4, r6, r9, sl, ip, sp} + 6328: e3a00f9e mov r0, #632 ; 0x278 + 632c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6330: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6334: ebf5f577 bl 0xffd83918 + 6338: 0800365e stmeqda r0, {r1, r2, r3, r4, r6, r9, sl, ip, sp} + 633c: e1a03000 mov r3, r0 + 6340: ebf5f70e bl 0xffd83f80 + 6344: 0800365c stmeqda r0, {r2, r3, r4, r6, r9, sl, ip, sp} + 6348: e2830000 add r0, r3, #0 ; 0x0 + 634c: e1a01004 mov r1, r4 + 6350: ebf5f49d bl 0xffd835cc + 6354: 0800365e stmeqda r0, {r1, r2, r3, r4, r6, r9, sl, ip, sp} + 6358: ebf5f708 bl 0xffd83f80 + 635c: 0800365e stmeqda r0, {r1, r2, r3, r4, r6, r9, sl, ip, sp} + 6360: e3a00f9f mov r0, #636 ; 0x27c + 6364: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6368: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 636c: ebf5f569 bl 0xffd83918 + 6370: 08003662 stmeqda r0, {r1, r5, r6, r9, sl, ip, sp} + 6374: e1a03000 mov r3, r0 + 6378: ebf5f700 bl 0xffd83f80 + 637c: 08003660 stmeqda r0, {r5, r6, r9, sl, ip, sp} + 6380: e2830000 add r0, r3, #0 ; 0x0 + 6384: e1a01005 mov r1, r5 + 6388: ebf5f48f bl 0xffd835cc + 638c: 08003662 stmeqda r0, {r1, r5, r6, r9, sl, ip, sp} + 6390: ebf5f6fa bl 0xffd83f80 + 6394: 08003662 stmeqda r0, {r1, r5, r6, r9, sl, ip, sp} + 6398: e3a00dda mov r0, #13952 ; 0x3680 + 639c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 63a0: ebf5f55c bl 0xffd83918 + 63a4: 08003666 stmeqda r0, {r1, r2, r5, r6, r9, sl, ip, sp} + 63a8: e1a03000 mov r3, r0 + 63ac: ebf5f6f3 bl 0xffd83f80 + 63b0: 08003664 stmeqda r0, {r2, r5, r6, r9, sl, ip, sp} + 63b4: e2830000 add r0, r3, #0 ; 0x0 + 63b8: e1a01006 mov r1, r6 + 63bc: ebf5f462 bl 0xffd8354c + 63c0: 08003666 stmeqda r0, {r1, r2, r5, r6, r9, sl, ip, sp} + 63c4: ebf5f6ed bl 0xffd83f80 + 63c8: 08003666 stmeqda r0, {r1, r2, r5, r6, r9, sl, ip, sp} + 63cc: e3a00fa1 mov r0, #644 ; 0x284 + 63d0: e3800b0d orr r0, r0, #13312 ; 0x3400 + 63d4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 63d8: ebf5f54e bl 0xffd83918 + 63dc: 0800366a stmeqda r0, {r1, r3, r5, r6, r9, sl, ip, sp} + 63e0: e1a03000 mov r3, r0 + 63e4: ebf5f6e5 bl 0xffd83f80 + 63e8: 08003668 stmeqda r0, {r3, r5, r6, r9, sl, ip, sp} + 63ec: e2830000 add r0, r3, #0 ; 0x0 + 63f0: e1a01008 mov r1, r8 + 63f4: ebf5f454 bl 0xffd8354c + 63f8: 0800366a stmeqda r0, {r1, r3, r5, r6, r9, sl, ip, sp} + 63fc: ebf5f6df bl 0xffd83f80 + 6400: 0800366a stmeqda r0, {r1, r3, r5, r6, r9, sl, ip, sp} + 6404: e3a00fa2 mov r0, #648 ; 0x288 + 6408: e3800b0d orr r0, r0, #13312 ; 0x3400 + 640c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6410: ebf5f540 bl 0xffd83918 + 6414: 0800366e stmeqda r0, {r1, r2, r3, r5, r6, r9, sl, ip, sp} + 6418: e1a03000 mov r3, r0 + 641c: ebf5f6d7 bl 0xffd83f80 + 6420: 0800366c stmeqda r0, {r2, r3, r5, r6, r9, sl, ip, sp} + 6424: e2830000 add r0, r3, #0 ; 0x0 + 6428: e59d1418 ldr r1, [sp, #1048] + 642c: ebf5f446 bl 0xffd8354c + 6430: 0800366e stmeqda r0, {r1, r2, r3, r5, r6, r9, sl, ip, sp} + 6434: ebf5f6d1 bl 0xffd83f80 + 6438: 0800366e stmeqda r0, {r1, r2, r3, r5, r6, r9, sl, ip, sp} + 643c: e59d9434 ldr r9, [sp, #1076] + 6440: e3c99003 bic r9, r9, #3 ; 0x3 + 6444: e289000c add r0, r9, #12 ; 0xc + 6448: e58d0434 str r0, [sp, #1076] + 644c: e2890000 add r0, r9, #0 ; 0x0 + 6450: ebf5f530 bl 0xffd83918 + 6454: 08003672 stmeqda r0, {r1, r4, r5, r6, r9, sl, ip, sp} + 6458: e1a07000 mov r7, r0 + 645c: e2890004 add r0, r9, #4 ; 0x4 + 6460: ebf5f52c bl 0xffd83918 + 6464: 08003672 stmeqda r0, {r1, r4, r5, r6, r9, sl, ip, sp} + 6468: e1a08000 mov r8, r0 + 646c: e2890008 add r0, r9, #8 ; 0x8 + 6470: ebf5f528 bl 0xffd83918 + 6474: 08003672 stmeqda r0, {r1, r4, r5, r6, r9, sl, ip, sp} + 6478: e58d0418 str r0, [sp, #1048] + 647c: ebf5f6bf bl 0xffd83f80 + 6480: 08003670 stmeqda r0, {r4, r5, r6, r9, sl, ip, sp} + 6484: e59d9434 ldr r9, [sp, #1076] + 6488: e3c99003 bic r9, r9, #3 ; 0x3 + 648c: e2890004 add r0, r9, #4 ; 0x4 + 6490: e58d0434 str r0, [sp, #1076] + 6494: e2890000 add r0, r9, #0 ; 0x0 + 6498: ebf5f51e bl 0xffd83918 + 649c: 08003674 stmeqda r0, {r2, r4, r5, r6, r9, sl, ip, sp} + 64a0: e1a03000 mov r3, r0 + 64a4: ebf5f6b5 bl 0xffd83f80 + 64a8: 08003672 stmeqda r0, {r1, r4, r5, r6, r9, sl, ip, sp} + 64ac: e1a00003 mov r0, r3 + 64b0: e28cc053 add ip, ip, #83 ; 0x53 + 64b4: eaf5f305 b 0xffd830d0 + 64b8: 080036fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 64bc: 00000000 andeq r0, r0, r0 + 64c0: ebf5f6ae bl 0xffd83f80 + 64c4: 080036fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 64c8: e3a00fcd mov r0, #820 ; 0x334 + 64cc: e3800b0d orr r0, r0, #13312 ; 0x3400 + 64d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 64d4: ebf5f50f bl 0xffd83918 + 64d8: 08003700 stmeqda r0, {r8, r9, sl, ip, sp} + 64dc: e1a03000 mov r3, r0 + 64e0: ebf5f6a6 bl 0xffd83f80 + 64e4: 080036fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 64e8: e3a00fce mov r0, #824 ; 0x338 + 64ec: e3800b0d orr r0, r0, #13312 ; 0x3400 + 64f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 64f4: ebf5f507 bl 0xffd83918 + 64f8: 08003702 stmeqda r0, {r1, r8, r9, sl, ip, sp} + 64fc: e1a05000 mov r5, r0 + 6500: ebf5f69e bl 0xffd83f80 + 6504: 08003700 stmeqda r0, {r8, r9, sl, ip, sp} + 6508: e3a00fcf mov r0, #828 ; 0x33c + 650c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6510: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6514: ebf5f4ff bl 0xffd83918 + 6518: 08003704 stmeqda r0, {r2, r8, r9, sl, ip, sp} + 651c: e1a06000 mov r6, r0 + 6520: ebf5f696 bl 0xffd83f80 + 6524: 08003702 stmeqda r0, {r1, r8, r9, sl, ip, sp} + 6528: e3b04080 movs r4, #128 ; 0x80 + 652c: ebf5f693 bl 0xffd83f80 + 6530: 08003704 stmeqda r0, {r2, r8, r9, sl, ip, sp} + 6534: e59d0434 ldr r0, [sp, #1076] + 6538: e2800f00 add r0, r0, #0 ; 0x0 + 653c: e1a01004 mov r1, r4 + 6540: ebf5f421 bl 0xffd835cc + 6544: 08003706 stmeqda r0, {r1, r2, r8, r9, sl, ip, sp} + 6548: ebf5f68c bl 0xffd83f80 + 654c: 08003706 stmeqda r0, {r1, r2, r8, r9, sl, ip, sp} + 6550: ebf5f68a bl 0xffd83f80 + 6554: 08003708 stmeqda r0, {r3, r8, r9, sl, ip, sp} + 6558: e3a0000b mov r0, #11 ; 0xb + 655c: e3800c37 orr r0, r0, #14080 ; 0x3700 + 6560: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6564: e58d0438 str r0, [sp, #1080] + 6568: e28cc01c add ip, ip, #28 ; 0x1c + 656c: e1a00fac mov r0, ip, lsr #31 + 6570: e08ff100 add pc, pc, r0, lsl #2 + 6574: 0800368c stmeqda r0, {r2, r3, r7, r9, sl, ip, sp} + 6578: ebf5f275 bl 0xffd82f54 + 657c: ea000001 b 0x6588 + 6580: 0800368c stmeqda r0, {r2, r3, r7, r9, sl, ip, sp} + 6584: 00000000 andeq r0, r0, r0 + 6588: ebf5f67c bl 0xffd83f80 + 658c: 0800368c stmeqda r0, {r2, r3, r7, r9, sl, ip, sp} + 6590: e59d9434 ldr r9, [sp, #1076] + 6594: e3c99003 bic r9, r9, #3 ; 0x3 + 6598: e249900c sub r9, r9, #12 ; 0xc + 659c: e58d9434 str r9, [sp, #1076] + 65a0: e2890000 add r0, r9, #0 ; 0x0 + 65a4: e1a01007 mov r1, r7 + 65a8: ebf5f427 bl 0xffd8364c + 65ac: e2890004 add r0, r9, #4 ; 0x4 + 65b0: e1a01008 mov r1, r8 + 65b4: ebf5f424 bl 0xffd8364c + 65b8: e2890008 add r0, r9, #8 ; 0x8 + 65bc: e59d1438 ldr r1, [sp, #1080] + 65c0: ebf5f421 bl 0xffd8364c + 65c4: ebf5f66d bl 0xffd83f80 + 65c8: 0800368e stmeqda r0, {r1, r2, r3, r7, r9, sl, ip, sp} + 65cc: e59d0434 ldr r0, [sp, #1076] + 65d0: e2800f03 add r0, r0, #12 ; 0xc + 65d4: ebf5f4cf bl 0xffd83918 + 65d8: 08003692 stmeqda r0, {r1, r4, r7, r9, sl, ip, sp} + 65dc: e1a08000 mov r8, r0 + 65e0: ebf5f666 bl 0xffd83f80 + 65e4: 08003690 stmeqda r0, {r4, r7, r9, sl, ip, sp} + 65e8: e3a00fab mov r0, #684 ; 0x2ac + 65ec: e3800b0d orr r0, r0, #13312 ; 0x3400 + 65f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 65f4: ebf5f4c7 bl 0xffd83918 + 65f8: 08003694 stmeqda r0, {r2, r4, r7, r9, sl, ip, sp} + 65fc: e1a07000 mov r7, r0 + 6600: ebf5f65e bl 0xffd83f80 + 6604: 08003692 stmeqda r0, {r1, r4, r7, r9, sl, ip, sp} + 6608: e2870000 add r0, r7, #0 ; 0x0 + 660c: e1a01003 mov r1, r3 + 6610: ebf5f3ed bl 0xffd835cc + 6614: 08003694 stmeqda r0, {r2, r4, r7, r9, sl, ip, sp} + 6618: ebf5f658 bl 0xffd83f80 + 661c: 08003694 stmeqda r0, {r2, r4, r7, r9, sl, ip, sp} + 6620: e3a00e6b mov r0, #1712 ; 0x6b0 + 6624: e3800a03 orr r0, r0, #12288 ; 0x3000 + 6628: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 662c: ebf5f4b9 bl 0xffd83918 + 6630: 08003698 stmeqda r0, {r3, r4, r7, r9, sl, ip, sp} + 6634: e1a03000 mov r3, r0 + 6638: ebf5f650 bl 0xffd83f80 + 663c: 08003696 stmeqda r0, {r1, r2, r4, r7, r9, sl, ip, sp} + 6640: e2830000 add r0, r3, #0 ; 0x0 + 6644: e1a01004 mov r1, r4 + 6648: ebf5f3df bl 0xffd835cc + 664c: 08003698 stmeqda r0, {r3, r4, r7, r9, sl, ip, sp} + 6650: ebf5f64a bl 0xffd83f80 + 6654: 08003698 stmeqda r0, {r3, r4, r7, r9, sl, ip, sp} + 6658: e3a00fad mov r0, #692 ; 0x2b4 + 665c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6660: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6664: ebf5f4ab bl 0xffd83918 + 6668: 0800369c stmeqda r0, {r2, r3, r4, r7, r9, sl, ip, sp} + 666c: e1a03000 mov r3, r0 + 6670: ebf5f642 bl 0xffd83f80 + 6674: 0800369a stmeqda r0, {r1, r3, r4, r7, r9, sl, ip, sp} + 6678: e2830000 add r0, r3, #0 ; 0x0 + 667c: e1a01005 mov r1, r5 + 6680: ebf5f3d1 bl 0xffd835cc + 6684: 0800369c stmeqda r0, {r2, r3, r4, r7, r9, sl, ip, sp} + 6688: ebf5f63c bl 0xffd83f80 + 668c: 0800369c stmeqda r0, {r2, r3, r4, r7, r9, sl, ip, sp} + 6690: e3a00fae mov r0, #696 ; 0x2b8 + 6694: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6698: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 669c: ebf5f49d bl 0xffd83918 + 66a0: 080036a0 stmeqda r0, {r5, r7, r9, sl, ip, sp} + 66a4: e1a03000 mov r3, r0 + 66a8: ebf5f634 bl 0xffd83f80 + 66ac: 0800369e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, ip, sp} + 66b0: e2830000 add r0, r3, #0 ; 0x0 + 66b4: e1a01006 mov r1, r6 + 66b8: ebf5f3c3 bl 0xffd835cc + 66bc: 080036a0 stmeqda r0, {r5, r7, r9, sl, ip, sp} + 66c0: ebf5f62e bl 0xffd83f80 + 66c4: 080036a0 stmeqda r0, {r5, r7, r9, sl, ip, sp} + 66c8: e3a00faf mov r0, #700 ; 0x2bc + 66cc: e3800b0d orr r0, r0, #13312 ; 0x3400 + 66d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 66d4: ebf5f48f bl 0xffd83918 + 66d8: 080036a4 stmeqda r0, {r2, r5, r7, r9, sl, ip, sp} + 66dc: e1a03000 mov r3, r0 + 66e0: ebf5f626 bl 0xffd83f80 + 66e4: 080036a2 stmeqda r0, {r1, r5, r7, r9, sl, ip, sp} + 66e8: e2830000 add r0, r3, #0 ; 0x0 + 66ec: e1a01008 mov r1, r8 + 66f0: ebf5f3b5 bl 0xffd835cc + 66f4: 080036a4 stmeqda r0, {r2, r5, r7, r9, sl, ip, sp} + 66f8: ebf5f620 bl 0xffd83f80 + 66fc: 080036a4 stmeqda r0, {r2, r5, r7, r9, sl, ip, sp} + 6700: e59d9434 ldr r9, [sp, #1076] + 6704: e3c99003 bic r9, r9, #3 ; 0x3 + 6708: e2890008 add r0, r9, #8 ; 0x8 + 670c: e58d0434 str r0, [sp, #1076] + 6710: e2890000 add r0, r9, #0 ; 0x0 + 6714: ebf5f47f bl 0xffd83918 + 6718: 080036a8 stmeqda r0, {r3, r5, r7, r9, sl, ip, sp} + 671c: e1a07000 mov r7, r0 + 6720: e2890004 add r0, r9, #4 ; 0x4 + 6724: ebf5f47b bl 0xffd83918 + 6728: 080036a8 stmeqda r0, {r3, r5, r7, r9, sl, ip, sp} + 672c: e1a08000 mov r8, r0 + 6730: ebf5f612 bl 0xffd83f80 + 6734: 080036a6 stmeqda r0, {r1, r2, r5, r7, r9, sl, ip, sp} + 6738: e59d9434 ldr r9, [sp, #1076] + 673c: e3c99003 bic r9, r9, #3 ; 0x3 + 6740: e2890004 add r0, r9, #4 ; 0x4 + 6744: e58d0434 str r0, [sp, #1076] + 6748: e2890000 add r0, r9, #0 ; 0x0 + 674c: ebf5f471 bl 0xffd83918 + 6750: 080036aa stmeqda r0, {r1, r3, r5, r7, r9, sl, ip, sp} + 6754: e1a03000 mov r3, r0 + 6758: ebf5f608 bl 0xffd83f80 + 675c: 080036a8 stmeqda r0, {r3, r5, r7, r9, sl, ip, sp} + 6760: e1a00003 mov r0, r3 + 6764: e28cc043 add ip, ip, #67 ; 0x43 + 6768: eaf5f258 b 0xffd830d0 + 676c: 0800370a stmeqda r0, {r1, r3, r8, r9, sl, ip, sp} + 6770: 00000000 andeq r0, r0, r0 + 6774: ebf5f601 bl 0xffd83f80 + 6778: 0800370a stmeqda r0, {r1, r3, r8, r9, sl, ip, sp} + 677c: e3b03007 movs r3, #7 ; 0x7 + 6780: ebf5f5fe bl 0xffd83f80 + 6784: 0800370c stmeqda r0, {r2, r3, r8, r9, sl, ip, sp} + 6788: ebf5f5fc bl 0xffd83f80 + 678c: 0800370e stmeqda r0, {r1, r2, r3, r8, r9, sl, ip, sp} + 6790: e3a00011 mov r0, #17 ; 0x11 + 6794: e3800c37 orr r0, r0, #14080 ; 0x3700 + 6798: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 679c: e58d0438 str r0, [sp, #1080] + 67a0: e28cc009 add ip, ip, #9 ; 0x9 + 67a4: e1a00fac mov r0, ip, lsr #31 + 67a8: e08ff100 add pc, pc, r0, lsl #2 + 67ac: 080036c0 stmeqda r0, {r6, r7, r9, sl, ip, sp} + 67b0: ebf5f1e7 bl 0xffd82f54 + 67b4: ea000001 b 0x67c0 + 67b8: 080036c0 stmeqda r0, {r6, r7, r9, sl, ip, sp} + 67bc: 00000000 andeq r0, r0, r0 + 67c0: ebf5f5ee bl 0xffd83f80 + 67c4: 080036c0 stmeqda r0, {r6, r7, r9, sl, ip, sp} + 67c8: e3a00fb2 mov r0, #712 ; 0x2c8 + 67cc: e3800b0d orr r0, r0, #13312 ; 0x3400 + 67d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 67d4: ebf5f44f bl 0xffd83918 + 67d8: 080036c4 stmeqda r0, {r2, r6, r7, r9, sl, ip, sp} + 67dc: e1a04000 mov r4, r0 + 67e0: ebf5f5e6 bl 0xffd83f80 + 67e4: 080036c2 stmeqda r0, {r1, r6, r7, r9, sl, ip, sp} + 67e8: e2840000 add r0, r4, #0 ; 0x0 + 67ec: e1a01003 mov r1, r3 + 67f0: ebf5f336 bl 0xffd834d0 + 67f4: 080036c4 stmeqda r0, {r2, r6, r7, r9, sl, ip, sp} + 67f8: ebf5f5e0 bl 0xffd83f80 + 67fc: 080036c4 stmeqda r0, {r2, r6, r7, r9, sl, ip, sp} + 6800: e59d0438 ldr r0, [sp, #1080] + 6804: e28cc00c add ip, ip, #12 ; 0xc + 6808: eaf5f230 b 0xffd830d0 + 680c: 08003710 stmeqda r0, {r4, r8, r9, sl, ip, sp} + 6810: 00000000 andeq r0, r0, r0 + 6814: ebf5f5d9 bl 0xffd83f80 + 6818: 08003710 stmeqda r0, {r4, r8, r9, sl, ip, sp} + 681c: ebf5f5d7 bl 0xffd83f80 + 6820: 08003712 stmeqda r0, {r1, r4, r8, r9, sl, ip, sp} + 6824: e3a00015 mov r0, #21 ; 0x15 + 6828: e3800c37 orr r0, r0, #14080 ; 0x3700 + 682c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6830: e58d0438 str r0, [sp, #1080] + 6834: e28cc006 add ip, ip, #6 ; 0x6 + 6838: e1a00fac mov r0, ip, lsr #31 + 683c: e08ff100 add pc, pc, r0, lsl #2 + 6840: 08003534 stmeqda r0, {r2, r4, r5, r8, sl, ip, sp} + 6844: ebf5f1c2 bl 0xffd82f54 + 6848: ea000001 b 0x6854 + 684c: 08003534 stmeqda r0, {r2, r4, r5, r8, sl, ip, sp} + 6850: 00000000 andeq r0, r0, r0 + 6854: ebf5f5c9 bl 0xffd83f80 + 6858: 08003534 stmeqda r0, {r2, r4, r5, r8, sl, ip, sp} + 685c: e59d9434 ldr r9, [sp, #1076] + 6860: e3c99003 bic r9, r9, #3 ; 0x3 + 6864: e2499004 sub r9, r9, #4 ; 0x4 + 6868: e58d9434 str r9, [sp, #1076] + 686c: e2890000 add r0, r9, #0 ; 0x0 + 6870: e59d1438 ldr r1, [sp, #1080] + 6874: ebf5f374 bl 0xffd8364c + 6878: ebf5f5c0 bl 0xffd83f80 + 687c: 08003536 stmeqda r0, {r1, r2, r4, r5, r8, sl, ip, sp} + 6880: ebf5f5be bl 0xffd83f80 + 6884: 08003538 stmeqda r0, {r3, r4, r5, r8, sl, ip, sp} + 6888: e3a0003b mov r0, #59 ; 0x3b + 688c: e3800c35 orr r0, r0, #13568 ; 0x3500 + 6890: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6894: e58d0438 str r0, [sp, #1080] + 6898: e28cc009 add ip, ip, #9 ; 0x9 + 689c: e1a00fac mov r0, ip, lsr #31 + 68a0: e08ff100 add pc, pc, r0, lsl #2 + 68a4: 080034cc stmeqda r0, {r2, r3, r6, r7, sl, ip, sp} + 68a8: ebf5f1a9 bl 0xffd82f54 + 68ac: ea000001 b 0x68b8 + 68b0: 080034cc stmeqda r0, {r2, r3, r6, r7, sl, ip, sp} + 68b4: 00000000 andeq r0, r0, r0 + 68b8: ebf5f5b0 bl 0xffd83f80 + 68bc: 080034cc stmeqda r0, {r2, r3, r6, r7, sl, ip, sp} + 68c0: e3a00f36 mov r0, #216 ; 0xd8 + 68c4: e3800b0d orr r0, r0, #13312 ; 0x3400 + 68c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 68cc: ebf5f411 bl 0xffd83918 + 68d0: 080034d0 stmeqda r0, {r4, r6, r7, sl, ip, sp} + 68d4: e1a05000 mov r5, r0 + 68d8: ebf5f5a8 bl 0xffd83f80 + 68dc: 080034ce stmeqda r0, {r1, r2, r3, r6, r7, sl, ip, sp} + 68e0: e2850000 add r0, r5, #0 ; 0x0 + 68e4: ebf5f3b4 bl 0xffd837bc + 68e8: 080034d2 stmeqda r0, {r1, r4, r6, r7, sl, ip, sp} + 68ec: e1a04000 mov r4, r0 + 68f0: ebf5f5a2 bl 0xffd83f80 + 68f4: 080034d0 stmeqda r0, {r4, r6, r7, sl, ip, sp} + 68f8: e3b030fe movs r3, #254 ; 0xfe + 68fc: ebf5f59f bl 0xffd83f80 + 6900: 080034d2 stmeqda r0, {r1, r4, r6, r7, sl, ip, sp} + 6904: e1a01003 mov r1, r3 + 6908: e0133004 ands r3, r3, r4 + 690c: ebf5f59b bl 0xffd83f80 + 6910: 080034d4 stmeqda r0, {r2, r4, r6, r7, sl, ip, sp} + 6914: e2850000 add r0, r5, #0 ; 0x0 + 6918: e1a01003 mov r1, r3 + 691c: ebf5f2eb bl 0xffd834d0 + 6920: 080034d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, ip, sp} + 6924: ebf5f595 bl 0xffd83f80 + 6928: 080034d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, ip, sp} + 692c: e59d0438 ldr r0, [sp, #1080] + 6930: e28cc017 add ip, ip, #23 ; 0x17 + 6934: eaf5f1e5 b 0xffd830d0 + 6938: 0800353a stmeqda r0, {r1, r3, r4, r5, r8, sl, ip, sp} + 693c: 00000000 andeq r0, r0, r0 + 6940: ebf5f58e bl 0xffd83f80 + 6944: 0800353a stmeqda r0, {r1, r3, r4, r5, r8, sl, ip, sp} + 6948: ebf5f58c bl 0xffd83f80 + 694c: 0800353c stmeqda r0, {r2, r3, r4, r5, r8, sl, ip, sp} + 6950: e3a0003f mov r0, #63 ; 0x3f + 6954: e3800c35 orr r0, r0, #13568 ; 0x3500 + 6958: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 695c: e58d0438 str r0, [sp, #1080] + 6960: e28cc006 add ip, ip, #6 ; 0x6 + 6964: e1a00fac mov r0, ip, lsr #31 + 6968: e08ff100 add pc, pc, r0, lsl #2 + 696c: 080034ec stmeqda r0, {r2, r3, r5, r6, r7, sl, ip, sp} + 6970: ebf5f177 bl 0xffd82f54 + 6974: ea000001 b 0x6980 + 6978: 080034ec stmeqda r0, {r2, r3, r5, r6, r7, sl, ip, sp} + 697c: 00000000 andeq r0, r0, r0 + 6980: ebf5f57e bl 0xffd83f80 + 6984: 080034ec stmeqda r0, {r2, r3, r5, r6, r7, sl, ip, sp} + 6988: e3a00f3e mov r0, #248 ; 0xf8 + 698c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6990: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6994: ebf5f3df bl 0xffd83918 + 6998: 080034f0 stmeqda r0, {r4, r5, r6, r7, sl, ip, sp} + 699c: e1a05000 mov r5, r0 + 69a0: ebf5f576 bl 0xffd83f80 + 69a4: 080034ee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, ip, sp} + 69a8: e2850000 add r0, r5, #0 ; 0x0 + 69ac: ebf5f382 bl 0xffd837bc + 69b0: 080034f2 stmeqda r0, {r1, r4, r5, r6, r7, sl, ip, sp} + 69b4: e1a04000 mov r4, r0 + 69b8: ebf5f570 bl 0xffd83f80 + 69bc: 080034f0 stmeqda r0, {r4, r5, r6, r7, sl, ip, sp} + 69c0: e3b030fd movs r3, #253 ; 0xfd + 69c4: ebf5f56d bl 0xffd83f80 + 69c8: 080034f2 stmeqda r0, {r1, r4, r5, r6, r7, sl, ip, sp} + 69cc: e1a01003 mov r1, r3 + 69d0: e0133004 ands r3, r3, r4 + 69d4: ebf5f569 bl 0xffd83f80 + 69d8: 080034f4 stmeqda r0, {r2, r4, r5, r6, r7, sl, ip, sp} + 69dc: e2850000 add r0, r5, #0 ; 0x0 + 69e0: e1a01003 mov r1, r3 + 69e4: ebf5f2b9 bl 0xffd834d0 + 69e8: 080034f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, sl, ip, sp} + 69ec: ebf5f563 bl 0xffd83f80 + 69f0: 080034f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, sl, ip, sp} + 69f4: e59d0438 ldr r0, [sp, #1080] + 69f8: e28cc017 add ip, ip, #23 ; 0x17 + 69fc: eaf5f1b3 b 0xffd830d0 + 6a00: 0800353e stmeqda r0, {r1, r2, r3, r4, r5, r8, sl, ip, sp} + 6a04: 00000000 andeq r0, r0, r0 + 6a08: ebf5f55c bl 0xffd83f80 + 6a0c: 0800353e stmeqda r0, {r1, r2, r3, r4, r5, r8, sl, ip, sp} + 6a10: ebf5f55a bl 0xffd83f80 + 6a14: 08003540 stmeqda r0, {r6, r8, sl, ip, sp} + 6a18: e3a00043 mov r0, #67 ; 0x43 + 6a1c: e3800c35 orr r0, r0, #13568 ; 0x3500 + 6a20: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6a24: e58d0438 str r0, [sp, #1080] + 6a28: e28cc006 add ip, ip, #6 ; 0x6 + 6a2c: e1a00fac mov r0, ip, lsr #31 + 6a30: e08ff100 add pc, pc, r0, lsl #2 + 6a34: 0800350c stmeqda r0, {r2, r3, r8, sl, ip, sp} + 6a38: ebf5f145 bl 0xffd82f54 + 6a3c: ea000001 b 0x6a48 + 6a40: 0800350c stmeqda r0, {r2, r3, r8, sl, ip, sp} + 6a44: 00000000 andeq r0, r0, r0 + 6a48: ebf5f54c bl 0xffd83f80 + 6a4c: 0800350c stmeqda r0, {r2, r3, r8, sl, ip, sp} + 6a50: e3a00f47 mov r0, #284 ; 0x11c + 6a54: e3800b0d orr r0, r0, #13312 ; 0x3400 + 6a58: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6a5c: ebf5f3ad bl 0xffd83918 + 6a60: 08003510 stmeqda r0, {r4, r8, sl, ip, sp} + 6a64: e1a05000 mov r5, r0 + 6a68: ebf5f544 bl 0xffd83f80 + 6a6c: 0800350e stmeqda r0, {r1, r2, r3, r8, sl, ip, sp} + 6a70: e2850000 add r0, r5, #0 ; 0x0 + 6a74: ebf5f37b bl 0xffd83868 + 6a78: 08003512 stmeqda r0, {r1, r4, r8, sl, ip, sp} + 6a7c: e1a04000 mov r4, r0 + 6a80: ebf5f53e bl 0xffd83f80 + 6a84: 08003510 stmeqda r0, {r4, r8, sl, ip, sp} + 6a88: e3b06082 movs r6, #130 ; 0x82 + 6a8c: ebf5f53b bl 0xffd83f80 + 6a90: 08003512 stmeqda r0, {r1, r4, r8, sl, ip, sp} + 6a94: e1b06286 movs r6, r6, lsl #5 + 6a98: ebf5f538 bl 0xffd83f80 + 6a9c: 08003514 stmeqda r0, {r2, r4, r8, sl, ip, sp} + 6aa0: e1a01006 mov r1, r6 + 6aa4: e2963000 adds r3, r6, #0 ; 0x0 + 6aa8: ebf5f534 bl 0xffd83f80 + 6aac: 08003516 stmeqda r0, {r1, r2, r4, r8, sl, ip, sp} + 6ab0: e1a01003 mov r1, r3 + 6ab4: e1933004 orrs r3, r3, r4 + 6ab8: ebf5f530 bl 0xffd83f80 + 6abc: 08003518 stmeqda r0, {r3, r4, r8, sl, ip, sp} + 6ac0: e2850000 add r0, r5, #0 ; 0x0 + 6ac4: e1a01003 mov r1, r3 + 6ac8: ebf5f29f bl 0xffd8354c + 6acc: 0800351a stmeqda r0, {r1, r3, r4, r8, sl, ip, sp} + 6ad0: ebf5f52a bl 0xffd83f80 + 6ad4: 0800351a stmeqda r0, {r1, r3, r4, r8, sl, ip, sp} + 6ad8: e59d0438 ldr r0, [sp, #1080] + 6adc: e28cc01d add ip, ip, #29 ; 0x1d + 6ae0: eaf5f17a b 0xffd830d0 + 6ae4: 08003542 stmeqda r0, {r1, r6, r8, sl, ip, sp} + 6ae8: 00000000 andeq r0, r0, r0 + 6aec: ebf5f523 bl 0xffd83f80 + 6af0: 08003542 stmeqda r0, {r1, r6, r8, sl, ip, sp} + 6af4: e59d9434 ldr r9, [sp, #1076] + 6af8: e3c99003 bic r9, r9, #3 ; 0x3 + 6afc: e2890004 add r0, r9, #4 ; 0x4 + 6b00: e58d0434 str r0, [sp, #1076] + 6b04: e2890000 add r0, r9, #0 ; 0x0 + 6b08: ebf5f382 bl 0xffd83918 + 6b0c: 08003546 stmeqda r0, {r1, r2, r6, r8, sl, ip, sp} + 6b10: e1a03000 mov r3, r0 + 6b14: ebf5f519 bl 0xffd83f80 + 6b18: 08003544 stmeqda r0, {r2, r6, r8, sl, ip, sp} + 6b1c: e1a00003 mov r0, r3 + 6b20: e28cc007 add ip, ip, #7 ; 0x7 + 6b24: eaf5f169 b 0xffd830d0 + 6b28: 08003714 stmeqda r0, {r2, r4, r8, r9, sl, ip, sp} + 6b2c: 00000000 andeq r0, r0, r0 + 6b30: ebf5f512 bl 0xffd83f80 + 6b34: 08003714 stmeqda r0, {r2, r4, r8, r9, sl, ip, sp} + 6b38: e59d0434 ldr r0, [sp, #1076] + 6b3c: e2800f02 add r0, r0, #8 ; 0x8 + 6b40: e58d0434 str r0, [sp, #1076] + 6b44: ebf5f50d bl 0xffd83f80 + 6b48: 08003716 stmeqda r0, {r1, r2, r4, r8, r9, sl, ip, sp} + 6b4c: e59d9434 ldr r9, [sp, #1076] + 6b50: e3c99003 bic r9, r9, #3 ; 0x3 + 6b54: e2890004 add r0, r9, #4 ; 0x4 + 6b58: e58d0434 str r0, [sp, #1076] + 6b5c: e2890000 add r0, r9, #0 ; 0x0 + 6b60: ebf5f36c bl 0xffd83918 + 6b64: 0800371a stmeqda r0, {r1, r3, r4, r8, r9, sl, ip, sp} + 6b68: e1a03000 mov r3, r0 + 6b6c: ebf5f503 bl 0xffd83f80 + 6b70: 08003718 stmeqda r0, {r3, r4, r8, r9, sl, ip, sp} + 6b74: e1a00003 mov r0, r3 + 6b78: e28cc00a add ip, ip, #10 ; 0xa + 6b7c: eaf5f153 b 0xffd830d0 + 6b80: 0800035a stmeqda r0, {r1, r3, r4, r6, r8, r9} + 6b84: 00000000 andeq r0, r0, r0 + 6b88: ebf5f4fc bl 0xffd83f80 + 6b8c: 0800035a stmeqda r0, {r1, r3, r4, r6, r8, r9} + 6b90: ebf5f4fa bl 0xffd83f80 + 6b94: 0800035c stmeqda r0, {r2, r3, r4, r6, r8, r9} + 6b98: e3a0005f mov r0, #95 ; 0x5f + 6b9c: e3800c03 orr r0, r0, #768 ; 0x300 + 6ba0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6ba4: e58d0438 str r0, [sp, #1080] + 6ba8: e28cc006 add ip, ip, #6 ; 0x6 + 6bac: e1a00fac mov r0, ip, lsr #31 + 6bb0: e08ff100 add pc, pc, r0, lsl #2 + 6bb4: 08010158 stmeqda r1, {r3, r4, r6, r8} + 6bb8: ebf5f0e5 bl 0xffd82f54 + 6bbc: ea000001 b 0x6bc8 + 6bc0: 08010158 stmeqda r1, {r3, r4, r6, r8} + 6bc4: 00000000 andeq r0, r0, r0 + 6bc8: ebf5f4ec bl 0xffd83f80 + 6bcc: 08010158 stmeqda r1, {r3, r4, r6, r8} + 6bd0: e59d9434 ldr r9, [sp, #1076] + 6bd4: e3c99003 bic r9, r9, #3 ; 0x3 + 6bd8: e2499008 sub r9, r9, #8 ; 0x8 + 6bdc: e58d9434 str r9, [sp, #1076] + 6be0: e2890000 add r0, r9, #0 ; 0x0 + 6be4: e1a01007 mov r1, r7 + 6be8: ebf5f297 bl 0xffd8364c + 6bec: e2890004 add r0, r9, #4 ; 0x4 + 6bf0: e59d1438 ldr r1, [sp, #1080] + 6bf4: ebf5f294 bl 0xffd8364c + 6bf8: ebf5f4e0 bl 0xffd83f80 + 6bfc: 0801015a stmeqda r1, {r1, r3, r4, r6, r8} + 6c00: e59d0434 ldr r0, [sp, #1076] + 6c04: e2400f01 sub r0, r0, #4 ; 0x4 + 6c08: e58d0434 str r0, [sp, #1076] + 6c0c: ebf5f4db bl 0xffd83f80 + 6c10: 0801015c stmeqda r1, {r2, r3, r4, r6, r8} + 6c14: e3a00e1f mov r0, #496 ; 0x1f0 + 6c18: e3800801 orr r0, r0, #65536 ; 0x10000 + 6c1c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6c20: ebf5f33c bl 0xffd83918 + 6c24: 08010160 stmeqda r1, {r5, r6, r8} + 6c28: e1a04000 mov r4, r0 + 6c2c: ebf5f4d3 bl 0xffd83f80 + 6c30: 0801015e stmeqda r1, {r1, r2, r3, r4, r6, r8} + 6c34: e3b030e0 movs r3, #224 ; 0xe0 + 6c38: ebf5f4d0 bl 0xffd83f80 + 6c3c: 08010160 stmeqda r1, {r5, r6, r8} + 6c40: e1b03a03 movs r3, r3, lsl #20 + 6c44: ebf5f4cd bl 0xffd83f80 + 6c48: 08010162 stmeqda r1, {r1, r5, r6, r8} + 6c4c: e2840000 add r0, r4, #0 ; 0x0 + 6c50: e1a01003 mov r1, r3 + 6c54: ebf5f25c bl 0xffd835cc + 6c58: 08010164 stmeqda r1, {r2, r5, r6, r8} + 6c5c: ebf5f4c7 bl 0xffd83f80 + 6c60: 08010164 stmeqda r1, {r2, r5, r6, r8} + 6c64: ebf5f4c5 bl 0xffd83f80 + 6c68: 08010166 stmeqda r1, {r1, r2, r5, r6, r8} + 6c6c: e3a00069 mov r0, #105 ; 0x69 + 6c70: e3800c01 orr r0, r0, #256 ; 0x100 + 6c74: e3800801 orr r0, r0, #65536 ; 0x10000 + 6c78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6c7c: e58d0438 str r0, [sp, #1080] + 6c80: e28cc01c add ip, ip, #28 ; 0x1c + 6c84: e1a00fac mov r0, ip, lsr #31 + 6c88: e08ff100 add pc, pc, r0, lsl #2 + 6c8c: 08010250 stmeqda r1, {r4, r6, r9} + 6c90: ebf5f0af bl 0xffd82f54 + 6c94: ea000001 b 0x6ca0 + 6c98: 08010250 stmeqda r1, {r4, r6, r9} + 6c9c: 00000000 andeq r0, r0, r0 + 6ca0: ebf5f4b6 bl 0xffd83f80 + 6ca4: 08010250 stmeqda r1, {r4, r6, r9} + 6ca8: e59d9434 ldr r9, [sp, #1076] + 6cac: e3c99003 bic r9, r9, #3 ; 0x3 + 6cb0: e2499004 sub r9, r9, #4 ; 0x4 + 6cb4: e58d9434 str r9, [sp, #1076] + 6cb8: e2890000 add r0, r9, #0 ; 0x0 + 6cbc: e59d1438 ldr r1, [sp, #1080] + 6cc0: ebf5f261 bl 0xffd8364c + 6cc4: ebf5f4ad bl 0xffd83f80 + 6cc8: 08010252 stmeqda r1, {r1, r4, r6, r9} + 6ccc: e3a00f99 mov r0, #612 ; 0x264 + 6cd0: e3800801 orr r0, r0, #65536 ; 0x10000 + 6cd4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6cd8: ebf5f30e bl 0xffd83918 + 6cdc: 08010256 stmeqda r1, {r1, r2, r4, r6, r9} + 6ce0: e1a03000 mov r3, r0 + 6ce4: ebf5f4a5 bl 0xffd83f80 + 6ce8: 08010254 stmeqda r1, {r2, r4, r6, r9} + 6cec: e2830000 add r0, r3, #0 ; 0x0 + 6cf0: ebf5f308 bl 0xffd83918 + 6cf4: 08010258 stmeqda r1, {r3, r4, r6, r9} + 6cf8: e1a03000 mov r3, r0 + 6cfc: ebf5f49f bl 0xffd83f80 + 6d00: 08010256 stmeqda r1, {r1, r2, r4, r6, r9} + 6d04: e3a00f9a mov r0, #616 ; 0x268 + 6d08: e3800801 orr r0, r0, #65536 ; 0x10000 + 6d0c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6d10: ebf5f300 bl 0xffd83918 + 6d14: 0801025a stmeqda r1, {r1, r3, r4, r6, r9} + 6d18: e1a04000 mov r4, r0 + 6d1c: ebf5f497 bl 0xffd83f80 + 6d20: 08010258 stmeqda r1, {r3, r4, r6, r9} + 6d24: e3b05010 movs r5, #16 ; 0x10 + 6d28: ebf5f494 bl 0xffd83f80 + 6d2c: 0801025a stmeqda r1, {r1, r3, r4, r6, r9} + 6d30: ebf5f492 bl 0xffd83f80 + 6d34: 0801025c stmeqda r1, {r2, r3, r4, r6, r9} + 6d38: e3a0005f mov r0, #95 ; 0x5f + 6d3c: e3800c02 orr r0, r0, #512 ; 0x200 + 6d40: e3800801 orr r0, r0, #65536 ; 0x10000 + 6d44: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6d48: e58d0438 str r0, [sp, #1080] + 6d4c: e28cc01b add ip, ip, #27 ; 0x1b + 6d50: e1a00fac mov r0, ip, lsr #31 + 6d54: e08ff100 add pc, pc, r0, lsl #2 + 6d58: 080c2f88 stmeqda ip, {r3, r7, r8, r9, sl, fp, sp} + 6d5c: ebf5f07c bl 0xffd82f54 + 6d60: ea000001 b 0x6d6c + 6d64: 080c2f88 stmeqda ip, {r3, r7, r8, r9, sl, fp, sp} + 6d68: 00000000 andeq r0, r0, r0 + 6d6c: ebf5f483 bl 0xffd83f80 + 6d70: 080c2f88 stmeqda ip, {r3, r7, r8, r9, sl, fp, sp} + 6d74: e59d9434 ldr r9, [sp, #1076] + 6d78: e3c99003 bic r9, r9, #3 ; 0x3 + 6d7c: e249900c sub r9, r9, #12 ; 0xc + 6d80: e58d9434 str r9, [sp, #1076] + 6d84: e2890000 add r0, r9, #0 ; 0x0 + 6d88: e1a01007 mov r1, r7 + 6d8c: ebf5f22e bl 0xffd8364c + 6d90: e2890004 add r0, r9, #4 ; 0x4 + 6d94: e59d141c ldr r1, [sp, #1052] + 6d98: ebf5f22b bl 0xffd8364c + 6d9c: e2890008 add r0, r9, #8 ; 0x8 + 6da0: e59d1438 ldr r1, [sp, #1080] + 6da4: ebf5f228 bl 0xffd8364c + 6da8: ebf5f474 bl 0xffd83f80 + 6dac: 080c2f8a stmeqda ip, {r1, r3, r7, r8, r9, sl, fp, sp} + 6db0: e59d0434 ldr r0, [sp, #1076] + 6db4: e2400f27 sub r0, r0, #156 ; 0x9c + 6db8: e58d0434 str r0, [sp, #1076] + 6dbc: ebf5f46f bl 0xffd83f80 + 6dc0: 080c2f8c stmeqda ip, {r2, r3, r7, r8, r9, sl, fp, sp} + 6dc4: e59d1434 ldr r1, [sp, #1076] + 6dc8: e1a00001 mov r0, r1 + 6dcc: e58d041c str r0, [sp, #1052] + 6dd0: ebf5f46a bl 0xffd83f80 + 6dd4: 080c2f8e stmeqda ip, {r1, r2, r3, r7, r8, r9, sl, fp, sp} + 6dd8: e59d041c ldr r0, [sp, #1052] + 6ddc: e2800000 add r0, r0, #0 ; 0x0 + 6de0: e1a01003 mov r1, r3 + 6de4: ebf5f1f8 bl 0xffd835cc + 6de8: 080c2f90 stmeqda ip, {r4, r7, r8, r9, sl, fp, sp} + 6dec: ebf5f463 bl 0xffd83f80 + 6df0: 080c2f90 stmeqda ip, {r4, r7, r8, r9, sl, fp, sp} + 6df4: e59d041c ldr r0, [sp, #1052] + 6df8: e2800004 add r0, r0, #4 ; 0x4 + 6dfc: e1a01004 mov r1, r4 + 6e00: ebf5f1f1 bl 0xffd835cc + 6e04: 080c2f92 stmeqda ip, {r1, r4, r7, r8, r9, sl, fp, sp} + 6e08: ebf5f45c bl 0xffd83f80 + 6e0c: 080c2f92 stmeqda ip, {r1, r4, r7, r8, r9, sl, fp, sp} + 6e10: e59d041c ldr r0, [sp, #1052] + 6e14: e2800008 add r0, r0, #8 ; 0x8 + 6e18: e1a01005 mov r1, r5 + 6e1c: ebf5f1ea bl 0xffd835cc + 6e20: 080c2f94 stmeqda ip, {r2, r4, r7, r8, r9, sl, fp, sp} + 6e24: ebf5f455 bl 0xffd83f80 + 6e28: 080c2f94 stmeqda ip, {r2, r4, r7, r8, r9, sl, fp, sp} + 6e2c: e3a00ffd mov r0, #1012 ; 0x3f4 + 6e30: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 6e34: e3800703 orr r0, r0, #786432 ; 0xc0000 + 6e38: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6e3c: ebf5f2b5 bl 0xffd83918 + 6e40: 080c2f98 stmeqda ip, {r3, r4, r7, r8, r9, sl, fp, sp} + 6e44: e1a03000 mov r3, r0 + 6e48: ebf5f44c bl 0xffd83f80 + 6e4c: 080c2f96 stmeqda ip, {r1, r2, r4, r7, r8, r9, sl, fp, sp} + 6e50: e3a00ffd mov r0, #1012 ; 0x3f4 + 6e54: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 6e58: e3800703 orr r0, r0, #786432 ; 0xc0000 + 6e5c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6e60: ebf5f2ac bl 0xffd83918 + 6e64: 080c2f9a stmeqda ip, {r1, r3, r4, r7, r8, r9, sl, fp, sp} + 6e68: e1a04000 mov r4, r0 + 6e6c: ebf5f443 bl 0xffd83f80 + 6e70: 080c2f98 stmeqda ip, {r3, r4, r7, r8, r9, sl, fp, sp} + 6e74: e2840000 add r0, r4, #0 ; 0x0 + 6e78: ebf5f27a bl 0xffd83868 + 6e7c: 080c2f9c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, fp, sp} + 6e80: e1a05000 mov r5, r0 + 6e84: ebf5f43d bl 0xffd83f80 + 6e88: 080c2f9a stmeqda ip, {r1, r3, r4, r7, r8, r9, sl, fp, sp} + 6e8c: e3a00ffe mov r0, #1016 ; 0x3f8 + 6e90: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 6e94: e3800703 orr r0, r0, #786432 ; 0xc0000 + 6e98: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6e9c: ebf5f29d bl 0xffd83918 + 6ea0: 080c2f9e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, sl, fp, sp} + 6ea4: e1a06000 mov r6, r0 + 6ea8: ebf5f434 bl 0xffd83f80 + 6eac: 080c2f9c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, fp, sp} + 6eb0: e1a01005 mov r1, r5 + 6eb4: e2954000 adds r4, r5, #0 ; 0x0 + 6eb8: ebf5f430 bl 0xffd83f80 + 6ebc: 080c2f9e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, sl, fp, sp} + 6ec0: e1a01004 mov r1, r4 + 6ec4: e0144006 ands r4, r4, r6 + 6ec8: ebf5f42c bl 0xffd83f80 + 6ecc: 080c2fa0 stmeqda ip, {r5, r7, r8, r9, sl, fp, sp} + 6ed0: e1a01004 mov r1, r4 + 6ed4: e2945000 adds r5, r4, #0 ; 0x0 + 6ed8: ebf5f428 bl 0xffd83f80 + 6edc: 080c2fa2 stmeqda ip, {r1, r5, r7, r8, r9, sl, fp, sp} + 6ee0: e3b06003 movs r6, #3 ; 0x3 + 6ee4: ebf5f425 bl 0xffd83f80 + 6ee8: 080c2fa4 stmeqda ip, {r2, r5, r7, r8, r9, sl, fp, sp} + 6eec: e1a01005 mov r1, r5 + 6ef0: e2954000 adds r4, r5, #0 ; 0x0 + 6ef4: ebf5f421 bl 0xffd83f80 + 6ef8: 080c2fa6 stmeqda ip, {r1, r2, r5, r7, r8, r9, sl, fp, sp} + 6efc: e1a01004 mov r1, r4 + 6f00: e1944006 orrs r4, r4, r6 + 6f04: ebf5f41d bl 0xffd83f80 + 6f08: 080c2fa8 stmeqda ip, {r3, r5, r7, r8, r9, sl, fp, sp} + 6f0c: e1a01004 mov r1, r4 + 6f10: e2945000 adds r5, r4, #0 ; 0x0 + 6f14: ebf5f419 bl 0xffd83f80 + 6f18: 080c2faa stmeqda ip, {r1, r3, r5, r7, r8, r9, sl, fp, sp} + 6f1c: e2830000 add r0, r3, #0 ; 0x0 + 6f20: e1a01005 mov r1, r5 + 6f24: ebf5f188 bl 0xffd8354c + 6f28: 080c2fac stmeqda ip, {r2, r3, r5, r7, r8, r9, sl, fp, sp} + 6f2c: ebf5f413 bl 0xffd83f80 + 6f30: 080c2fac stmeqda ip, {r2, r3, r5, r7, r8, r9, sl, fp, sp} + 6f34: e59d141c ldr r1, [sp, #1052] + 6f38: e59d141c ldr r1, [sp, #1052] + 6f3c: e2913000 adds r3, r1, #0 ; 0x0 + 6f40: ebf5f40e bl 0xffd83f80 + 6f44: 080c2fae stmeqda ip, {r1, r2, r3, r5, r7, r8, r9, sl, fp, sp} + 6f48: e59d141c ldr r1, [sp, #1052] + 6f4c: e59d141c ldr r1, [sp, #1052] + 6f50: e2914000 adds r4, r1, #0 ; 0x0 + 6f54: ebf5f409 bl 0xffd83f80 + 6f58: 080c2fb0 stmeqda ip, {r4, r5, r7, r8, r9, sl, fp, sp} + 6f5c: e1a01004 mov r1, r4 + 6f60: e2944090 adds r4, r4, #144 ; 0x90 + 6f64: ebf5f405 bl 0xffd83f80 + 6f68: 080c2fb2 stmeqda ip, {r1, r4, r5, r7, r8, r9, sl, fp, sp} + 6f6c: e3a00fff mov r0, #1020 ; 0x3fc + 6f70: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 6f74: e3800703 orr r0, r0, #786432 ; 0xc0000 + 6f78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 6f7c: ebf5f265 bl 0xffd83918 + 6f80: 080c2fb6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9, sl, fp, sp} + 6f84: e1a03000 mov r3, r0 + 6f88: ebf5f3fc bl 0xffd83f80 + 6f8c: 080c2fb4 stmeqda ip, {r2, r4, r5, r7, r8, r9, sl, fp, sp} + 6f90: e2840000 add r0, r4, #0 ; 0x0 + 6f94: e1a01003 mov r1, r3 + 6f98: ebf5f18b bl 0xffd835cc + 6f9c: 080c2fb6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9, sl, fp, sp} + 6fa0: ebf5f3f6 bl 0xffd83f80 + 6fa4: 080c2fb6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9, sl, fp, sp} + 6fa8: e59d141c ldr r1, [sp, #1052] + 6fac: e59d141c ldr r1, [sp, #1052] + 6fb0: e2914000 adds r4, r1, #0 ; 0x0 + 6fb4: ebf5f3f1 bl 0xffd83f80 + 6fb8: 080c2fb8 stmeqda ip, {r3, r4, r5, r7, r8, r9, sl, fp, sp} + 6fbc: e59d141c ldr r1, [sp, #1052] + 6fc0: e59d141c ldr r1, [sp, #1052] + 6fc4: e2913000 adds r3, r1, #0 ; 0x0 + 6fc8: ebf5f3ec bl 0xffd83f80 + 6fcc: 080c2fba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9, sl, fp, sp} + 6fd0: e1a01003 mov r1, r3 + 6fd4: e2933090 adds r3, r3, #144 ; 0x90 + 6fd8: ebf5f3e8 bl 0xffd83f80 + 6fdc: 080c2fbc stmeqda ip, {r2, r3, r4, r5, r7, r8, r9, sl, fp, sp} + 6fe0: e59d141c ldr r1, [sp, #1052] + 6fe4: e59d141c ldr r1, [sp, #1052] + 6fe8: e2914000 adds r4, r1, #0 ; 0x0 + 6fec: ebf5f3e3 bl 0xffd83f80 + 6ff0: 080c2fbe stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, sl, fp, sp} + 6ff4: e59d141c ldr r1, [sp, #1052] + 6ff8: e59d141c ldr r1, [sp, #1052] + 6ffc: e2915000 adds r5, r1, #0 ; 0x0 + 7000: ebf5f3de bl 0xffd83f80 + 7004: 080c2fc0 stmeqda ip, {r6, r7, r8, r9, sl, fp, sp} + 7008: e1a01005 mov r1, r5 + 700c: e2955090 adds r5, r5, #144 ; 0x90 + 7010: ebf5f3da bl 0xffd83f80 + 7014: 080c2fc2 stmeqda ip, {r1, r6, r7, r8, r9, sl, fp, sp} + 7018: e2850000 add r0, r5, #0 ; 0x0 + 701c: ebf5f23d bl 0xffd83918 + 7020: 080c2fc6 stmeqda ip, {r1, r2, r6, r7, r8, r9, sl, fp, sp} + 7024: e1a04000 mov r4, r0 + 7028: ebf5f3d4 bl 0xffd83f80 + 702c: 080c2fc4 stmeqda ip, {r2, r6, r7, r8, r9, sl, fp, sp} + 7030: e3b05001 movs r5, #1 ; 0x1 + 7034: ebf5f3d1 bl 0xffd83f80 + 7038: 080c2fc6 stmeqda ip, {r1, r2, r6, r7, r8, r9, sl, fp, sp} + 703c: e1a01004 mov r1, r4 + 7040: e0344005 eors r4, r4, r5 + 7044: ebf5f3cd bl 0xffd83f80 + 7048: 080c2fc8 stmeqda ip, {r3, r6, r7, r8, r9, sl, fp, sp} + 704c: e2830000 add r0, r3, #0 ; 0x0 + 7050: e1a01004 mov r1, r4 + 7054: ebf5f15c bl 0xffd835cc + 7058: 080c2fca stmeqda ip, {r1, r3, r6, r7, r8, r9, sl, fp, sp} + 705c: ebf5f3c7 bl 0xffd83f80 + 7060: 080c2fca stmeqda ip, {r1, r3, r6, r7, r8, r9, sl, fp, sp} + 7064: e59d141c ldr r1, [sp, #1052] + 7068: e59d141c ldr r1, [sp, #1052] + 706c: e2913000 adds r3, r1, #0 ; 0x0 + 7070: ebf5f3c2 bl 0xffd83f80 + 7074: 080c2fcc stmeqda ip, {r2, r3, r6, r7, r8, r9, sl, fp, sp} + 7078: e59d141c ldr r1, [sp, #1052] + 707c: e59d141c ldr r1, [sp, #1052] + 7080: e2914000 adds r4, r1, #0 ; 0x0 + 7084: ebf5f3bd bl 0xffd83f80 + 7088: 080c2fce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9, sl, fp, sp} + 708c: e1a01004 mov r1, r4 + 7090: e2944094 adds r4, r4, #148 ; 0x94 + 7094: ebf5f3b9 bl 0xffd83f80 + 7098: 080c2fd0 stmeqda ip, {r4, r6, r7, r8, r9, sl, fp, sp} + 709c: e59d141c ldr r1, [sp, #1052] + 70a0: e59d141c ldr r1, [sp, #1052] + 70a4: e2913000 adds r3, r1, #0 ; 0x0 + 70a8: ebf5f3b4 bl 0xffd83f80 + 70ac: 080c2fd2 stmeqda ip, {r1, r4, r6, r7, r8, r9, sl, fp, sp} + 70b0: e1a01003 mov r1, r3 + 70b4: e2933010 adds r3, r3, #16 ; 0x10 + 70b8: ebf5f3b0 bl 0xffd83f80 + 70bc: 080c2fd4 stmeqda ip, {r2, r4, r6, r7, r8, r9, sl, fp, sp} + 70c0: e2840000 add r0, r4, #0 ; 0x0 + 70c4: e1a01003 mov r1, r3 + 70c8: ebf5f13f bl 0xffd835cc + 70cc: 080c2fd6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, sl, fp, sp} + 70d0: ebf5f3aa bl 0xffd83f80 + 70d4: 080c2fd6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, sl, fp, sp} + 70d8: e59d141c ldr r1, [sp, #1052] + 70dc: e59d141c ldr r1, [sp, #1052] + 70e0: e2913000 adds r3, r1, #0 ; 0x0 + 70e4: ebf5f3a5 bl 0xffd83f80 + 70e8: 080c2fd8 stmeqda ip, {r3, r4, r6, r7, r8, r9, sl, fp, sp} + 70ec: e1a01003 mov r1, r3 + 70f0: e293300c adds r3, r3, #12 ; 0xc + 70f4: ebf5f3a1 bl 0xffd83f80 + 70f8: 080c2fda stmeqda ip, {r1, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 70fc: e3a00ac3 mov r0, #798720 ; 0xc3000 + 7100: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7104: ebf5f203 bl 0xffd83918 + 7108: 080c2fde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 710c: e1a04000 mov r4, r0 + 7110: ebf5f39a bl 0xffd83f80 + 7114: 080c2fdc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 7118: e3a00fff mov r0, #1020 ; 0x3fc + 711c: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 7120: e3800703 orr r0, r0, #786432 ; 0xc0000 + 7124: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7128: ebf5f1fa bl 0xffd83918 + 712c: 080c2fe0 stmeqda ip, {r5, r6, r7, r8, r9, sl, fp, sp} + 7130: e1a05000 mov r5, r0 + 7134: ebf5f391 bl 0xffd83f80 + 7138: 080c2fde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 713c: e1a01004 mov r1, r4 + 7140: e0544005 subs r4, r4, r5 + 7144: ebf5f38d bl 0xffd83f80 + 7148: 080c2fe0 stmeqda ip, {r5, r6, r7, r8, r9, sl, fp, sp} + 714c: e1b050a4 movs r5, r4, lsr #1 + 7150: ebf5f38a bl 0xffd83f80 + 7154: 080c2fe2 stmeqda ip, {r1, r5, r6, r7, r8, r9, sl, fp, sp} + 7158: e1a01005 mov r1, r5 + 715c: e2954000 adds r4, r5, #0 ; 0x0 + 7160: ebf5f386 bl 0xffd83f80 + 7164: 080c2fe4 stmeqda ip, {r2, r5, r6, r7, r8, r9, sl, fp, sp} + 7168: e2830000 add r0, r3, #0 ; 0x0 + 716c: e1a01004 mov r1, r4 + 7170: ebf5f0f5 bl 0xffd8354c + 7174: 080c2fe6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 7178: ebf5f380 bl 0xffd83f80 + 717c: 080c2fe6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 7180: e59d141c ldr r1, [sp, #1052] + 7184: e59d141c ldr r1, [sp, #1052] + 7188: e2913000 adds r3, r1, #0 ; 0x0 + 718c: ebf5f37b bl 0xffd83f80 + 7190: 080c2fe8 stmeqda ip, {r3, r5, r6, r7, r8, r9, sl, fp, sp} + 7194: e1a01003 mov r1, r3 + 7198: e293300c adds r3, r3, #12 ; 0xc + 719c: ebf5f377 bl 0xffd83f80 + 71a0: 080c2fea stmeqda ip, {r1, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 71a4: e2830000 add r0, r3, #0 ; 0x0 + 71a8: ebf5f1ae bl 0xffd83868 + 71ac: 080c2fee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 71b0: e1a04000 mov r4, r0 + 71b4: ebf5f371 bl 0xffd83f80 + 71b8: 080c2fec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 71bc: e3540000 cmp r4, #0 ; 0x0 + 71c0: ebf5f36e bl 0xffd83f80 + 71c4: 080c2fee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 71c8: e28cc0b8 add ip, ip, #184 ; 0xb8 + 71cc: 0a000004 beq 0x71e4 + 71d0: e1a00fac mov r0, ip, lsr #31 + 71d4: e08ff100 add pc, pc, r0, lsl #2 + 71d8: 080c3004 stmeqda ip, {r2, ip, sp} + 71dc: ebf5ef5c bl 0xffd82f54 + 71e0: ea000009 b 0x720c + 71e4: ebf5f365 bl 0xffd83f80 + 71e8: 080c2ff0 stmeqda ip, {r4, r5, r6, r7, r8, r9, sl, fp, sp} + 71ec: e28cc003 add ip, ip, #3 ; 0x3 + 71f0: e1a00fac mov r0, ip, lsr #31 + 71f4: e08ff100 add pc, pc, r0, lsl #2 + 71f8: 080c3036 stmeqda ip, {r1, r2, r4, r5, ip, sp} + 71fc: ebf5ef54 bl 0xffd82f54 + 7200: ea0000a7 b 0x74a4 + 7204: 080c3004 stmeqda ip, {r2, ip, sp} + 7208: 00000000 andeq r0, r0, r0 + 720c: ebf5f35b bl 0xffd83f80 + 7210: 080c3004 stmeqda ip, {r2, ip, sp} + 7214: e59d141c ldr r1, [sp, #1052] + 7218: e59d141c ldr r1, [sp, #1052] + 721c: e2914000 adds r4, r1, #0 ; 0x0 + 7220: ebf5f356 bl 0xffd83f80 + 7224: 080c3006 stmeqda ip, {r1, r2, ip, sp} + 7228: e59d141c ldr r1, [sp, #1052] + 722c: e59d141c ldr r1, [sp, #1052] + 7230: e2913000 adds r3, r1, #0 ; 0x0 + 7234: ebf5f351 bl 0xffd83f80 + 7238: 080c3008 stmeqda ip, {r3, ip, sp} + 723c: e1a01003 mov r1, r3 + 7240: e2933094 adds r3, r3, #148 ; 0x94 + 7244: ebf5f34d bl 0xffd83f80 + 7248: 080c300a stmeqda ip, {r1, r3, ip, sp} + 724c: e2830000 add r0, r3, #0 ; 0x0 + 7250: ebf5f1b0 bl 0xffd83918 + 7254: 080c300e stmeqda ip, {r1, r2, r3, ip, sp} + 7258: e1a04000 mov r4, r0 + 725c: ebf5f347 bl 0xffd83f80 + 7260: 080c300c stmeqda ip, {r2, r3, ip, sp} + 7264: e59d141c ldr r1, [sp, #1052] + 7268: e59d141c ldr r1, [sp, #1052] + 726c: e2916000 adds r6, r1, #0 ; 0x0 + 7270: ebf5f342 bl 0xffd83f80 + 7274: 080c300e stmeqda ip, {r1, r2, r3, ip, sp} + 7278: e59d141c ldr r1, [sp, #1052] + 727c: e59d141c ldr r1, [sp, #1052] + 7280: e2915000 adds r5, r1, #0 ; 0x0 + 7284: ebf5f33d bl 0xffd83f80 + 7288: 080c3010 stmeqda ip, {r4, ip, sp} + 728c: e1a01005 mov r1, r5 + 7290: e2955090 adds r5, r5, #144 ; 0x90 + 7294: ebf5f339 bl 0xffd83f80 + 7298: 080c3012 stmeqda ip, {r1, r4, ip, sp} + 729c: e2850000 add r0, r5, #0 ; 0x0 + 72a0: ebf5f19c bl 0xffd83918 + 72a4: 080c3016 stmeqda ip, {r1, r2, r4, ip, sp} + 72a8: e1a06000 mov r6, r0 + 72ac: ebf5f333 bl 0xffd83f80 + 72b0: 080c3014 stmeqda ip, {r2, r4, ip, sp} + 72b4: e2860000 add r0, r6, #0 ; 0x0 + 72b8: ebf5f16a bl 0xffd83868 + 72bc: 080c3018 stmeqda ip, {r3, r4, ip, sp} + 72c0: e1a07000 mov r7, r0 + 72c4: ebf5f32d bl 0xffd83f80 + 72c8: 080c3016 stmeqda ip, {r1, r2, r4, ip, sp} + 72cc: e2840000 add r0, r4, #0 ; 0x0 + 72d0: e1a01007 mov r1, r7 + 72d4: ebf5f09c bl 0xffd8354c + 72d8: 080c3018 stmeqda ip, {r3, r4, ip, sp} + 72dc: ebf5f327 bl 0xffd83f80 + 72e0: 080c3018 stmeqda ip, {r3, r4, ip, sp} + 72e4: e1a01006 mov r1, r6 + 72e8: e2966002 adds r6, r6, #2 ; 0x2 + 72ec: ebf5f323 bl 0xffd83f80 + 72f0: 080c301a stmeqda ip, {r1, r3, r4, ip, sp} + 72f4: e2850000 add r0, r5, #0 ; 0x0 + 72f8: e1a01006 mov r1, r6 + 72fc: ebf5f0b2 bl 0xffd835cc + 7300: 080c301c stmeqda ip, {r2, r3, r4, ip, sp} + 7304: ebf5f31d bl 0xffd83f80 + 7308: 080c301c stmeqda ip, {r2, r3, r4, ip, sp} + 730c: e1a01004 mov r1, r4 + 7310: e2944002 adds r4, r4, #2 ; 0x2 + 7314: ebf5f319 bl 0xffd83f80 + 7318: 080c301e stmeqda ip, {r1, r2, r3, r4, ip, sp} + 731c: e2830000 add r0, r3, #0 ; 0x0 + 7320: e1a01004 mov r1, r4 + 7324: ebf5f0a8 bl 0xffd835cc + 7328: 080c3020 stmeqda ip, {r5, ip, sp} + 732c: ebf5f313 bl 0xffd83f80 + 7330: 080c3020 stmeqda ip, {r5, ip, sp} + 7334: e59d141c ldr r1, [sp, #1052] + 7338: e59d141c ldr r1, [sp, #1052] + 733c: e2914000 adds r4, r1, #0 ; 0x0 + 7340: ebf5f30e bl 0xffd83f80 + 7344: 080c3022 stmeqda ip, {r1, r5, ip, sp} + 7348: e1a01004 mov r1, r4 + 734c: e294400c adds r4, r4, #12 ; 0xc + 7350: ebf5f30a bl 0xffd83f80 + 7354: 080c3024 stmeqda ip, {r2, r5, ip, sp} + 7358: e59d141c ldr r1, [sp, #1052] + 735c: e59d141c ldr r1, [sp, #1052] + 7360: e2913000 adds r3, r1, #0 ; 0x0 + 7364: ebf5f305 bl 0xffd83f80 + 7368: 080c3026 stmeqda ip, {r1, r2, r5, ip, sp} + 736c: e1a01003 mov r1, r3 + 7370: e293300c adds r3, r3, #12 ; 0xc + 7374: ebf5f301 bl 0xffd83f80 + 7378: 080c3028 stmeqda ip, {r3, r5, ip, sp} + 737c: e59d141c ldr r1, [sp, #1052] + 7380: e59d141c ldr r1, [sp, #1052] + 7384: e2914000 adds r4, r1, #0 ; 0x0 + 7388: ebf5f2fc bl 0xffd83f80 + 738c: 080c302a stmeqda ip, {r1, r3, r5, ip, sp} + 7390: e1a01004 mov r1, r4 + 7394: e294400c adds r4, r4, #12 ; 0xc + 7398: ebf5f2f8 bl 0xffd83f80 + 739c: 080c302c stmeqda ip, {r2, r3, r5, ip, sp} + 73a0: e2840000 add r0, r4, #0 ; 0x0 + 73a4: ebf5f12f bl 0xffd83868 + 73a8: 080c3030 stmeqda ip, {r4, r5, ip, sp} + 73ac: e1a05000 mov r5, r0 + 73b0: ebf5f2f2 bl 0xffd83f80 + 73b4: 080c302e stmeqda ip, {r1, r2, r3, r5, ip, sp} + 73b8: e1a01005 mov r1, r5 + 73bc: e2554001 subs r4, r5, #1 ; 0x1 + 73c0: ebf5f2ee bl 0xffd83f80 + 73c4: 080c3030 stmeqda ip, {r4, r5, ip, sp} + 73c8: e1a01004 mov r1, r4 + 73cc: e2945000 adds r5, r4, #0 ; 0x0 + 73d0: ebf5f2ea bl 0xffd83f80 + 73d4: 080c3032 stmeqda ip, {r1, r4, r5, ip, sp} + 73d8: e2830000 add r0, r3, #0 ; 0x0 + 73dc: e1a01005 mov r1, r5 + 73e0: ebf5f059 bl 0xffd8354c + 73e4: 080c3034 stmeqda ip, {r2, r4, r5, ip, sp} + 73e8: ebf5f2e4 bl 0xffd83f80 + 73ec: 080c3034 stmeqda ip, {r2, r4, r5, ip, sp} + 73f0: e28cc057 add ip, ip, #87 ; 0x57 + 73f4: e1a00fac mov r0, ip, lsr #31 + 73f8: e08ff100 add pc, pc, r0, lsl #2 + 73fc: 080c2fe6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 7400: ebf5eed3 bl 0xffd82f54 + 7404: ea000001 b 0x7410 + 7408: 080c2fe6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 740c: 00000000 andeq r0, r0, r0 + 7410: ebf5f2da bl 0xffd83f80 + 7414: 080c2fe6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 7418: e59d141c ldr r1, [sp, #1052] + 741c: e59d141c ldr r1, [sp, #1052] + 7420: e2913000 adds r3, r1, #0 ; 0x0 + 7424: ebf5f2d5 bl 0xffd83f80 + 7428: 080c2fe8 stmeqda ip, {r3, r5, r6, r7, r8, r9, sl, fp, sp} + 742c: e1a01003 mov r1, r3 + 7430: e293300c adds r3, r3, #12 ; 0xc + 7434: ebf5f2d1 bl 0xffd83f80 + 7438: 080c2fea stmeqda ip, {r1, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 743c: e2830000 add r0, r3, #0 ; 0x0 + 7440: ebf5f108 bl 0xffd83868 + 7444: 080c2fee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 7448: e1a04000 mov r4, r0 + 744c: ebf5f2cb bl 0xffd83f80 + 7450: 080c2fec stmeqda ip, {r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 7454: e3540000 cmp r4, #0 ; 0x0 + 7458: ebf5f2c8 bl 0xffd83f80 + 745c: 080c2fee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 7460: e28cc011 add ip, ip, #17 ; 0x11 + 7464: 0a000004 beq 0x747c + 7468: e1a00fac mov r0, ip, lsr #31 + 746c: e08ff100 add pc, pc, r0, lsl #2 + 7470: 080c3004 stmeqda ip, {r2, ip, sp} + 7474: ebf5eeb6 bl 0xffd82f54 + 7478: eaffff63 b 0x720c + 747c: ebf5f2bf bl 0xffd83f80 + 7480: 080c2ff0 stmeqda ip, {r4, r5, r6, r7, r8, r9, sl, fp, sp} + 7484: e28cc003 add ip, ip, #3 ; 0x3 + 7488: e1a00fac mov r0, ip, lsr #31 + 748c: e08ff100 add pc, pc, r0, lsl #2 + 7490: 080c3036 stmeqda ip, {r1, r2, r4, r5, ip, sp} + 7494: ebf5eeae bl 0xffd82f54 + 7498: ea000001 b 0x74a4 + 749c: 080c3036 stmeqda ip, {r1, r2, r4, r5, ip, sp} + 74a0: 00000000 andeq r0, r0, r0 + 74a4: ebf5f2b5 bl 0xffd83f80 + 74a8: 080c3036 stmeqda ip, {r1, r2, r4, r5, ip, sp} + 74ac: e59d141c ldr r1, [sp, #1052] + 74b0: e59d141c ldr r1, [sp, #1052] + 74b4: e2914000 adds r4, r1, #0 ; 0x0 + 74b8: ebf5f2b0 bl 0xffd83f80 + 74bc: 080c3038 stmeqda ip, {r3, r4, r5, ip, sp} + 74c0: e59d141c ldr r1, [sp, #1052] + 74c4: e59d141c ldr r1, [sp, #1052] + 74c8: e2913000 adds r3, r1, #0 ; 0x0 + 74cc: ebf5f2ab bl 0xffd83f80 + 74d0: 080c303a stmeqda ip, {r1, r3, r4, r5, ip, sp} + 74d4: e1a01003 mov r1, r3 + 74d8: e2933098 adds r3, r3, #152 ; 0x98 + 74dc: ebf5f2a7 bl 0xffd83f80 + 74e0: 080c303c stmeqda ip, {r2, r3, r4, r5, ip, sp} + 74e4: e59d141c ldr r1, [sp, #1052] + 74e8: e59d141c ldr r1, [sp, #1052] + 74ec: e2914000 adds r4, r1, #0 ; 0x0 + 74f0: ebf5f2a2 bl 0xffd83f80 + 74f4: 080c303e stmeqda ip, {r1, r2, r3, r4, r5, ip, sp} + 74f8: e1a01004 mov r1, r4 + 74fc: e2944010 adds r4, r4, #16 ; 0x10 + 7500: ebf5f29e bl 0xffd83f80 + 7504: 080c3040 stmeqda ip, {r6, ip, sp} + 7508: e1a01004 mov r1, r4 + 750c: e2945001 adds r5, r4, #1 ; 0x1 + 7510: ebf5f29a bl 0xffd83f80 + 7514: 080c3042 stmeqda ip, {r1, r6, ip, sp} + 7518: e2830000 add r0, r3, #0 ; 0x0 + 751c: e1a01005 mov r1, r5 + 7520: ebf5f029 bl 0xffd835cc + 7524: 080c3044 stmeqda ip, {r2, r6, ip, sp} + 7528: ebf5f294 bl 0xffd83f80 + 752c: 080c3044 stmeqda ip, {r2, r6, ip, sp} + 7530: e59d141c ldr r1, [sp, #1052] + 7534: e59d141c ldr r1, [sp, #1052] + 7538: e2914000 adds r4, r1, #0 ; 0x0 + 753c: ebf5f28f bl 0xffd83f80 + 7540: 080c3046 stmeqda ip, {r1, r2, r6, ip, sp} + 7544: e59d141c ldr r1, [sp, #1052] + 7548: e59d141c ldr r1, [sp, #1052] + 754c: e2913000 adds r3, r1, #0 ; 0x0 + 7550: ebf5f28a bl 0xffd83f80 + 7554: 080c3048 stmeqda ip, {r3, r6, ip, sp} + 7558: e1a01003 mov r1, r3 + 755c: e2933098 adds r3, r3, #152 ; 0x98 + 7560: ebf5f286 bl 0xffd83f80 + 7564: 080c304a stmeqda ip, {r1, r3, r6, ip, sp} + 7568: e59d041c ldr r0, [sp, #1052] + 756c: e2800004 add r0, r0, #4 ; 0x4 + 7570: ebf5f0e8 bl 0xffd83918 + 7574: 080c304e stmeqda ip, {r1, r2, r3, r6, ip, sp} + 7578: e1a04000 mov r4, r0 + 757c: ebf5f27f bl 0xffd83f80 + 7580: 080c304c stmeqda ip, {r2, r3, r6, ip, sp} + 7584: e59d041c ldr r0, [sp, #1052] + 7588: e2800008 add r0, r0, #8 ; 0x8 + 758c: ebf5f0e1 bl 0xffd83918 + 7590: 080c3050 stmeqda ip, {r4, r6, ip, sp} + 7594: e1a05000 mov r5, r0 + 7598: ebf5f278 bl 0xffd83f80 + 759c: 080c304e stmeqda ip, {r1, r2, r3, r6, ip, sp} + 75a0: e2830000 add r0, r3, #0 ; 0x0 + 75a4: ebf5f0db bl 0xffd83918 + 75a8: 080c3052 stmeqda ip, {r1, r4, r6, ip, sp} + 75ac: e1a06000 mov r6, r0 + 75b0: ebf5f272 bl 0xffd83f80 + 75b4: 080c3050 stmeqda ip, {r4, r6, ip, sp} + 75b8: e59d041c ldr r0, [sp, #1052] + 75bc: e2800000 add r0, r0, #0 ; 0x0 + 75c0: ebf5f0d4 bl 0xffd83918 + 75c4: 080c3054 stmeqda ip, {r2, r4, r6, ip, sp} + 75c8: e1a03000 mov r3, r0 + 75cc: ebf5f26b bl 0xffd83f80 + 75d0: 080c3052 stmeqda ip, {r1, r4, r6, ip, sp} + 75d4: ebf5f269 bl 0xffd83f80 + 75d8: 080c3054 stmeqda ip, {r2, r4, r6, ip, sp} + 75dc: e3a00057 mov r0, #87 ; 0x57 + 75e0: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 75e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 75e8: e58d0438 str r0, [sp, #1080] + 75ec: e28cc039 add ip, ip, #57 ; 0x39 + 75f0: e1a00fac mov r0, ip, lsr #31 + 75f4: e08ff100 add pc, pc, r0, lsl #2 + 75f8: 080c31e8 stmeqda ip, {r3, r5, r6, r7, r8, ip, sp} + 75fc: ebf5ee54 bl 0xffd82f54 + 7600: ea000001 b 0x760c + 7604: 080c31e8 stmeqda ip, {r3, r5, r6, r7, r8, ip, sp} + 7608: 00000000 andeq r0, r0, r0 + 760c: ebf5f25b bl 0xffd83f80 + 7610: 080c31e8 stmeqda ip, {r3, r5, r6, r7, r8, ip, sp} + 7614: e1a00006 mov r0, r6 + 7618: e28cc003 add ip, ip, #3 ; 0x3 + 761c: eaf5eeab b 0xffd830d0 + 7620: 080c3056 stmeqda ip, {r1, r2, r4, r6, ip, sp} + 7624: 00000000 andeq r0, r0, r0 + 7628: ebf5f254 bl 0xffd83f80 + 762c: 080c3056 stmeqda ip, {r1, r2, r4, r6, ip, sp} + 7630: e59d0434 ldr r0, [sp, #1076] + 7634: e2800f27 add r0, r0, #156 ; 0x9c + 7638: e58d0434 str r0, [sp, #1076] + 763c: ebf5f24f bl 0xffd83f80 + 7640: 080c3058 stmeqda ip, {r3, r4, r6, ip, sp} + 7644: e59d9434 ldr r9, [sp, #1076] + 7648: e3c99003 bic r9, r9, #3 ; 0x3 + 764c: e2890008 add r0, r9, #8 ; 0x8 + 7650: e58d0434 str r0, [sp, #1076] + 7654: e2890000 add r0, r9, #0 ; 0x0 + 7658: ebf5f0ae bl 0xffd83918 + 765c: 080c305c stmeqda ip, {r2, r3, r4, r6, ip, sp} + 7660: e1a07000 mov r7, r0 + 7664: e2890004 add r0, r9, #4 ; 0x4 + 7668: ebf5f0aa bl 0xffd83918 + 766c: 080c305c stmeqda ip, {r2, r3, r4, r6, ip, sp} + 7670: e58d041c str r0, [sp, #1052] + 7674: ebf5f241 bl 0xffd83f80 + 7678: 080c305a stmeqda ip, {r1, r3, r4, r6, ip, sp} + 767c: e59d9434 ldr r9, [sp, #1076] + 7680: e3c99003 bic r9, r9, #3 ; 0x3 + 7684: e2890004 add r0, r9, #4 ; 0x4 + 7688: e58d0434 str r0, [sp, #1076] + 768c: e2890000 add r0, r9, #0 ; 0x0 + 7690: ebf5f0a0 bl 0xffd83918 + 7694: 080c305e stmeqda ip, {r1, r2, r3, r4, r6, ip, sp} + 7698: e1a03000 mov r3, r0 + 769c: ebf5f237 bl 0xffd83f80 + 76a0: 080c305c stmeqda ip, {r2, r3, r4, r6, ip, sp} + 76a4: e1a00003 mov r0, r3 + 76a8: e28cc00f add ip, ip, #15 ; 0xf + 76ac: eaf5ee87 b 0xffd830d0 + 76b0: 0801025e stmeqda r1, {r1, r2, r3, r4, r6, r9} + 76b4: 00000000 andeq r0, r0, r0 + 76b8: ebf5f230 bl 0xffd83f80 + 76bc: 0801025e stmeqda r1, {r1, r2, r3, r4, r6, r9} + 76c0: e59d9434 ldr r9, [sp, #1076] + 76c4: e3c99003 bic r9, r9, #3 ; 0x3 + 76c8: e2890004 add r0, r9, #4 ; 0x4 + 76cc: e58d0434 str r0, [sp, #1076] + 76d0: e2890000 add r0, r9, #0 ; 0x0 + 76d4: ebf5f08f bl 0xffd83918 + 76d8: 08010262 stmeqda r1, {r1, r5, r6, r9} + 76dc: e1a03000 mov r3, r0 + 76e0: ebf5f226 bl 0xffd83f80 + 76e4: 08010260 stmeqda r1, {r5, r6, r9} + 76e8: e1a00003 mov r0, r3 + 76ec: e28cc007 add ip, ip, #7 ; 0x7 + 76f0: eaf5ee76 b 0xffd830d0 + 76f4: 08010168 stmeqda r1, {r3, r5, r6, r8} + 76f8: 00000000 andeq r0, r0, r0 + 76fc: ebf5f21f bl 0xffd83f80 + 7700: 08010168 stmeqda r1, {r3, r5, r6, r8} + 7704: e3a00f7d mov r0, #500 ; 0x1f4 + 7708: e3800801 orr r0, r0, #65536 ; 0x10000 + 770c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7710: ebf5f080 bl 0xffd83918 + 7714: 0801016c stmeqda r1, {r2, r3, r5, r6, r8} + 7718: e1a05000 mov r5, r0 + 771c: ebf5f217 bl 0xffd83f80 + 7720: 0801016a stmeqda r1, {r1, r3, r5, r6, r8} + 7724: e2850000 add r0, r5, #0 ; 0x0 + 7728: ebf5f07a bl 0xffd83918 + 772c: 0801016e stmeqda r1, {r1, r2, r3, r5, r6, r8} + 7730: e1a04000 mov r4, r0 + 7734: ebf5f211 bl 0xffd83f80 + 7738: 0801016c stmeqda r1, {r2, r3, r5, r6, r8} + 773c: e3a00f7e mov r0, #504 ; 0x1f8 + 7740: e3800801 orr r0, r0, #65536 ; 0x10000 + 7744: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7748: ebf5f072 bl 0xffd83918 + 774c: 08010170 stmeqda r1, {r4, r5, r6, r8} + 7750: e1a03000 mov r3, r0 + 7754: ebf5f209 bl 0xffd83f80 + 7758: 0801016e stmeqda r1, {r1, r2, r3, r5, r6, r8} + 775c: e1540003 cmp r4, r3 + 7760: ebf5f206 bl 0xffd83f80 + 7764: 08010170 stmeqda r1, {r4, r5, r6, r8} + 7768: e28cc015 add ip, ip, #21 ; 0x15 + 776c: 0a000004 beq 0x7784 + 7770: e1a00fac mov r0, ip, lsr #31 + 7774: e08ff100 add pc, pc, r0, lsl #2 + 7778: 08010186 stmeqda r1, {r1, r2, r7, r8} + 777c: ebf5edf4 bl 0xffd82f54 + 7780: ea00003f b 0x7884 + 7784: ebf5f1fd bl 0xffd83f80 + 7788: 08010172 stmeqda r1, {r1, r4, r5, r6, r8} + 778c: e2850004 add r0, r5, #4 ; 0x4 + 7790: ebf5f060 bl 0xffd83918 + 7794: 08010176 stmeqda r1, {r1, r2, r4, r5, r6, r8} + 7798: e1a04000 mov r4, r0 + 779c: ebf5f1f7 bl 0xffd83f80 + 77a0: 08010174 stmeqda r1, {r2, r4, r5, r6, r8} + 77a4: e3a00f7f mov r0, #508 ; 0x1fc + 77a8: e3800801 orr r0, r0, #65536 ; 0x10000 + 77ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 77b0: ebf5f058 bl 0xffd83918 + 77b4: 08010178 stmeqda r1, {r3, r4, r5, r6, r8} + 77b8: e1a03000 mov r3, r0 + 77bc: ebf5f1ef bl 0xffd83f80 + 77c0: 08010176 stmeqda r1, {r1, r2, r4, r5, r6, r8} + 77c4: e1540003 cmp r4, r3 + 77c8: ebf5f1ec bl 0xffd83f80 + 77cc: 08010178 stmeqda r1, {r3, r4, r5, r6, r8} + 77d0: e28cc010 add ip, ip, #16 ; 0x10 + 77d4: 0a000004 beq 0x77ec + 77d8: e1a00fac mov r0, ip, lsr #31 + 77dc: e08ff100 add pc, pc, r0, lsl #2 + 77e0: 08010186 stmeqda r1, {r1, r2, r7, r8} + 77e4: ebf5edda bl 0xffd82f54 + 77e8: ea000025 b 0x7884 + 77ec: ebf5f1e3 bl 0xffd83f80 + 77f0: 0801017a stmeqda r1, {r1, r3, r4, r5, r6, r8} + 77f4: e2850008 add r0, r5, #8 ; 0x8 + 77f8: ebf5f046 bl 0xffd83918 + 77fc: 0801017e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8} + 7800: e1a03000 mov r3, r0 + 7804: ebf5f1dd bl 0xffd83f80 + 7808: 0801017c stmeqda r1, {r2, r3, r4, r5, r6, r8} + 780c: e3a00c02 mov r0, #512 ; 0x200 + 7810: e3800801 orr r0, r0, #65536 ; 0x10000 + 7814: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7818: ebf5f03e bl 0xffd83918 + 781c: 08010180 stmeqda r1, {r7, r8} + 7820: e1a04000 mov r4, r0 + 7824: ebf5f1d5 bl 0xffd83f80 + 7828: 0801017e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8} + 782c: e1a01003 mov r1, r3 + 7830: e0133004 ands r3, r3, r4 + 7834: ebf5f1d1 bl 0xffd83f80 + 7838: 08010180 stmeqda r1, {r7, r8} + 783c: e3a00f81 mov r0, #516 ; 0x204 + 7840: e3800801 orr r0, r0, #65536 ; 0x10000 + 7844: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7848: ebf5f032 bl 0xffd83918 + 784c: 08010184 stmeqda r1, {r2, r7, r8} + 7850: e1a04000 mov r4, r0 + 7854: ebf5f1c9 bl 0xffd83f80 + 7858: 08010182 stmeqda r1, {r1, r7, r8} + 785c: e1530004 cmp r3, r4 + 7860: ebf5f1c6 bl 0xffd83f80 + 7864: 08010184 stmeqda r1, {r2, r7, r8} + 7868: e28cc018 add ip, ip, #24 ; 0x18 + 786c: 1a000004 bne 0x7884 + 7870: e1a00fac mov r0, ip, lsr #31 + 7874: e08ff100 add pc, pc, r0, lsl #2 + 7878: 080101e8 stmeqda r1, {r3, r5, r6, r7, r8} + 787c: ebf5edb4 bl 0xffd82f54 + 7880: ea0000d9 b 0x7bec + 7884: ebf5f1bd bl 0xffd83f80 + 7888: 08010186 stmeqda r1, {r1, r2, r7, r8} + 788c: e3b03000 movs r3, #0 ; 0x0 + 7890: ebf5f1ba bl 0xffd83f80 + 7894: 08010188 stmeqda r1, {r3, r7, r8} + 7898: e59d0434 ldr r0, [sp, #1076] + 789c: e2800f00 add r0, r0, #0 ; 0x0 + 78a0: e1a01003 mov r1, r3 + 78a4: ebf5ef48 bl 0xffd835cc + 78a8: 0801018a stmeqda r1, {r1, r3, r7, r8} + 78ac: ebf5f1b3 bl 0xffd83f80 + 78b0: 0801018a stmeqda r1, {r1, r3, r7, r8} + 78b4: e3a00f82 mov r0, #520 ; 0x208 + 78b8: e3800801 orr r0, r0, #65536 ; 0x10000 + 78bc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 78c0: ebf5f014 bl 0xffd83918 + 78c4: 0801018e stmeqda r1, {r1, r2, r3, r7, r8} + 78c8: e1a04000 mov r4, r0 + 78cc: ebf5f1ab bl 0xffd83f80 + 78d0: 0801018c stmeqda r1, {r2, r3, r7, r8} + 78d4: e59d1434 ldr r1, [sp, #1076] + 78d8: e1a03001 mov r3, r1 + 78dc: ebf5f1a7 bl 0xffd83f80 + 78e0: 0801018e stmeqda r1, {r1, r2, r3, r7, r8} + 78e4: e2840000 add r0, r4, #0 ; 0x0 + 78e8: e1a01003 mov r1, r3 + 78ec: ebf5ef36 bl 0xffd835cc + 78f0: 08010190 stmeqda r1, {r4, r7, r8} + 78f4: ebf5f1a1 bl 0xffd83f80 + 78f8: 08010190 stmeqda r1, {r4, r7, r8} + 78fc: e3a00f83 mov r0, #524 ; 0x20c + 7900: e3800801 orr r0, r0, #65536 ; 0x10000 + 7904: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7908: ebf5f002 bl 0xffd83918 + 790c: 08010194 stmeqda r1, {r2, r4, r7, r8} + 7910: e1a03000 mov r3, r0 + 7914: ebf5f199 bl 0xffd83f80 + 7918: 08010192 stmeqda r1, {r1, r4, r7, r8} + 791c: e2840004 add r0, r4, #4 ; 0x4 + 7920: e1a01003 mov r1, r3 + 7924: ebf5ef28 bl 0xffd835cc + 7928: 08010194 stmeqda r1, {r2, r4, r7, r8} + 792c: ebf5f193 bl 0xffd83f80 + 7930: 08010194 stmeqda r1, {r2, r4, r7, r8} + 7934: e3a00e21 mov r0, #528 ; 0x210 + 7938: e3800801 orr r0, r0, #65536 ; 0x10000 + 793c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7940: ebf5eff4 bl 0xffd83918 + 7944: 08010198 stmeqda r1, {r3, r4, r7, r8} + 7948: e1a03000 mov r3, r0 + 794c: ebf5f18b bl 0xffd83f80 + 7950: 08010196 stmeqda r1, {r1, r2, r4, r7, r8} + 7954: e2840008 add r0, r4, #8 ; 0x8 + 7958: e1a01003 mov r1, r3 + 795c: ebf5ef1a bl 0xffd835cc + 7960: 08010198 stmeqda r1, {r3, r4, r7, r8} + 7964: ebf5f185 bl 0xffd83f80 + 7968: 08010198 stmeqda r1, {r3, r4, r7, r8} + 796c: e2840008 add r0, r4, #8 ; 0x8 + 7970: ebf5efe8 bl 0xffd83918 + 7974: 0801019c stmeqda r1, {r2, r3, r4, r7, r8} + 7978: e1a03000 mov r3, r0 + 797c: ebf5f17f bl 0xffd83f80 + 7980: 0801019a stmeqda r1, {r1, r3, r4, r7, r8} + 7984: e2840008 add r0, r4, #8 ; 0x8 + 7988: ebf5efe2 bl 0xffd83918 + 798c: 0801019e stmeqda r1, {r1, r2, r3, r4, r7, r8} + 7990: e1a03000 mov r3, r0 + 7994: ebf5f179 bl 0xffd83f80 + 7998: 0801019c stmeqda r1, {r2, r3, r4, r7, r8} + 799c: e3b06080 movs r6, #128 ; 0x80 + 79a0: ebf5f176 bl 0xffd83f80 + 79a4: 0801019e stmeqda r1, {r1, r2, r3, r4, r7, r8} + 79a8: e1b06c06 movs r6, r6, lsl #24 + 79ac: ebf5f173 bl 0xffd83f80 + 79b0: 080101a0 stmeqda r1, {r5, r7, r8} + 79b4: e3530000 cmp r3, #0 ; 0x0 + 79b8: ebf5f170 bl 0xffd83f80 + 79bc: 080101a2 stmeqda r1, {r1, r5, r7, r8} + 79c0: e28cc03b add ip, ip, #59 ; 0x3b + 79c4: ba000004 blt 0x79dc + 79c8: e1a00fac mov r0, ip, lsr #31 + 79cc: e08ff100 add pc, pc, r0, lsl #2 + 79d0: 080101ac stmeqda r1, {r2, r3, r5, r7, r8} + 79d4: ebf5ed5e bl 0xffd82f54 + 79d8: ea000015 b 0x7a34 + 79dc: ebf5f167 bl 0xffd83f80 + 79e0: 080101a4 stmeqda r1, {r2, r5, r7, r8} + 79e4: e2840008 add r0, r4, #8 ; 0x8 + 79e8: ebf5efca bl 0xffd83918 + 79ec: 080101a8 stmeqda r1, {r3, r5, r7, r8} + 79f0: e1a03000 mov r3, r0 + 79f4: ebf5f161 bl 0xffd83f80 + 79f8: 080101a6 stmeqda r1, {r1, r2, r5, r7, r8} + 79fc: e1a01003 mov r1, r3 + 7a00: e0133006 ands r3, r3, r6 + 7a04: ebf5f15d bl 0xffd83f80 + 7a08: 080101a8 stmeqda r1, {r3, r5, r7, r8} + 7a0c: e3530000 cmp r3, #0 ; 0x0 + 7a10: ebf5f15a bl 0xffd83f80 + 7a14: 080101aa stmeqda r1, {r1, r3, r5, r7, r8} + 7a18: e28cc00e add ip, ip, #14 ; 0xe + 7a1c: 0a000004 beq 0x7a34 + 7a20: e1a00fac mov r0, ip, lsr #31 + 7a24: e08ff100 add pc, pc, r0, lsl #2 + 7a28: 080101a4 stmeqda r1, {r2, r5, r7, r8} + 7a2c: ebf5ed48 bl 0xffd82f54 + 7a30: eaffffe9 b 0x79dc + 7a34: ebf5f151 bl 0xffd83f80 + 7a38: 080101ac stmeqda r1, {r2, r3, r5, r7, r8} + 7a3c: e3b03044 movs r3, #68 ; 0x44 + 7a40: ebf5f14e bl 0xffd83f80 + 7a44: 080101ae stmeqda r1, {r1, r2, r3, r5, r7, r8} + 7a48: e2850000 add r0, r5, #0 ; 0x0 + 7a4c: e1a01003 mov r1, r3 + 7a50: ebf5ee9e bl 0xffd834d0 + 7a54: 080101b0 stmeqda r1, {r4, r5, r7, r8} + 7a58: ebf5f148 bl 0xffd83f80 + 7a5c: 080101b0 stmeqda r1, {r4, r5, r7, r8} + 7a60: e3b03052 movs r3, #82 ; 0x52 + 7a64: ebf5f145 bl 0xffd83f80 + 7a68: 080101b2 stmeqda r1, {r1, r4, r5, r7, r8} + 7a6c: e2850001 add r0, r5, #1 ; 0x1 + 7a70: e1a01003 mov r1, r3 + 7a74: ebf5ee95 bl 0xffd834d0 + 7a78: 080101b4 stmeqda r1, {r2, r4, r5, r7, r8} + 7a7c: ebf5f13f bl 0xffd83f80 + 7a80: 080101b4 stmeqda r1, {r2, r4, r5, r7, r8} + 7a84: e3b04041 movs r4, #65 ; 0x41 + 7a88: ebf5f13c bl 0xffd83f80 + 7a8c: 080101b6 stmeqda r1, {r1, r2, r4, r5, r7, r8} + 7a90: e2850002 add r0, r5, #2 ; 0x2 + 7a94: e1a01004 mov r1, r4 + 7a98: ebf5ee8c bl 0xffd834d0 + 7a9c: 080101b8 stmeqda r1, {r3, r4, r5, r7, r8} + 7aa0: ebf5f136 bl 0xffd83f80 + 7aa4: 080101b8 stmeqda r1, {r3, r4, r5, r7, r8} + 7aa8: e3b03043 movs r3, #67 ; 0x43 + 7aac: ebf5f133 bl 0xffd83f80 + 7ab0: 080101ba stmeqda r1, {r1, r3, r4, r5, r7, r8} + 7ab4: e2850003 add r0, r5, #3 ; 0x3 + 7ab8: e1a01003 mov r1, r3 + 7abc: ebf5ee83 bl 0xffd834d0 + 7ac0: 080101bc stmeqda r1, {r2, r3, r4, r5, r7, r8} + 7ac4: ebf5f12d bl 0xffd83f80 + 7ac8: 080101bc stmeqda r1, {r2, r3, r4, r5, r7, r8} + 7acc: e3b03055 movs r3, #85 ; 0x55 + 7ad0: ebf5f12a bl 0xffd83f80 + 7ad4: 080101be stmeqda r1, {r1, r2, r3, r4, r5, r7, r8} + 7ad8: e2850004 add r0, r5, #4 ; 0x4 + 7adc: e1a01003 mov r1, r3 + 7ae0: ebf5ee7a bl 0xffd834d0 + 7ae4: 080101c0 stmeqda r1, {r6, r7, r8} + 7ae8: ebf5f124 bl 0xffd83f80 + 7aec: 080101c0 stmeqda r1, {r6, r7, r8} + 7af0: e3b0304c movs r3, #76 ; 0x4c + 7af4: ebf5f121 bl 0xffd83f80 + 7af8: 080101c2 stmeqda r1, {r1, r6, r7, r8} + 7afc: e2850005 add r0, r5, #5 ; 0x5 + 7b00: e1a01003 mov r1, r3 + 7b04: ebf5ee71 bl 0xffd834d0 + 7b08: 080101c4 stmeqda r1, {r2, r6, r7, r8} + 7b0c: ebf5f11b bl 0xffd83f80 + 7b10: 080101c4 stmeqda r1, {r2, r6, r7, r8} + 7b14: e2850006 add r0, r5, #6 ; 0x6 + 7b18: e1a01004 mov r1, r4 + 7b1c: ebf5ee6b bl 0xffd834d0 + 7b20: 080101c6 stmeqda r1, {r1, r2, r6, r7, r8} + 7b24: ebf5f115 bl 0xffd83f80 + 7b28: 080101c6 stmeqda r1, {r1, r2, r6, r7, r8} + 7b2c: e3b03020 movs r3, #32 ; 0x20 + 7b30: ebf5f112 bl 0xffd83f80 + 7b34: 080101c8 stmeqda r1, {r3, r6, r7, r8} + 7b38: e2850007 add r0, r5, #7 ; 0x7 + 7b3c: e1a01003 mov r1, r3 + 7b40: ebf5ee62 bl 0xffd834d0 + 7b44: 080101ca stmeqda r1, {r1, r3, r6, r7, r8} + 7b48: ebf5f10c bl 0xffd83f80 + 7b4c: 080101ca stmeqda r1, {r1, r3, r6, r7, r8} + 7b50: e2850008 add r0, r5, #8 ; 0x8 + 7b54: e1a01004 mov r1, r4 + 7b58: ebf5ee5c bl 0xffd834d0 + 7b5c: 080101cc stmeqda r1, {r2, r3, r6, r7, r8} + 7b60: ebf5f106 bl 0xffd83f80 + 7b64: 080101cc stmeqda r1, {r2, r3, r6, r7, r8} + 7b68: e3b03047 movs r3, #71 ; 0x47 + 7b6c: ebf5f103 bl 0xffd83f80 + 7b70: 080101ce stmeqda r1, {r1, r2, r3, r6, r7, r8} + 7b74: e2850009 add r0, r5, #9 ; 0x9 + 7b78: e1a01003 mov r1, r3 + 7b7c: ebf5ee53 bl 0xffd834d0 + 7b80: 080101d0 stmeqda r1, {r4, r6, r7, r8} + 7b84: ebf5f0fd bl 0xffd83f80 + 7b88: 080101d0 stmeqda r1, {r4, r6, r7, r8} + 7b8c: e3b03042 movs r3, #66 ; 0x42 + 7b90: ebf5f0fa bl 0xffd83f80 + 7b94: 080101d2 stmeqda r1, {r1, r4, r6, r7, r8} + 7b98: e285000a add r0, r5, #10 ; 0xa + 7b9c: e1a01003 mov r1, r3 + 7ba0: ebf5ee4a bl 0xffd834d0 + 7ba4: 080101d4 stmeqda r1, {r2, r4, r6, r7, r8} + 7ba8: ebf5f0f4 bl 0xffd83f80 + 7bac: 080101d4 stmeqda r1, {r2, r4, r6, r7, r8} + 7bb0: ebf5f0f2 bl 0xffd83f80 + 7bb4: 080101d6 stmeqda r1, {r1, r2, r4, r6, r7, r8} + 7bb8: e3a000d9 mov r0, #217 ; 0xd9 + 7bbc: e3800c01 orr r0, r0, #256 ; 0x100 + 7bc0: e3800801 orr r0, r0, #65536 ; 0x10000 + 7bc4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7bc8: e58d0438 str r0, [sp, #1080] + 7bcc: e28cc04d add ip, ip, #77 ; 0x4d + 7bd0: e1a00fac mov r0, ip, lsr #31 + 7bd4: e08ff100 add pc, pc, r0, lsl #2 + 7bd8: 0801026c stmeqda r1, {r2, r3, r5, r6, r9} + 7bdc: ebf5ecdc bl 0xffd82f54 + 7be0: ea000021 b 0x7c6c + 7be4: 080101e8 stmeqda r1, {r3, r5, r6, r7, r8} + 7be8: 00000000 andeq r0, r0, r0 + 7bec: ebf5f0e3 bl 0xffd83f80 + 7bf0: 080101e8 stmeqda r1, {r3, r5, r6, r7, r8} + 7bf4: e59d0434 ldr r0, [sp, #1076] + 7bf8: e2800f01 add r0, r0, #4 ; 0x4 + 7bfc: e58d0434 str r0, [sp, #1076] + 7c00: ebf5f0de bl 0xffd83f80 + 7c04: 080101ea stmeqda r1, {r1, r3, r5, r6, r7, r8} + 7c08: e59d9434 ldr r9, [sp, #1076] + 7c0c: e3c99003 bic r9, r9, #3 ; 0x3 + 7c10: e2890004 add r0, r9, #4 ; 0x4 + 7c14: e58d0434 str r0, [sp, #1076] + 7c18: e2890000 add r0, r9, #0 ; 0x0 + 7c1c: ebf5ef3d bl 0xffd83918 + 7c20: 080101ee stmeqda r1, {r1, r2, r3, r5, r6, r7, r8} + 7c24: e1a07000 mov r7, r0 + 7c28: ebf5f0d4 bl 0xffd83f80 + 7c2c: 080101ec stmeqda r1, {r2, r3, r5, r6, r7, r8} + 7c30: e59d9434 ldr r9, [sp, #1076] + 7c34: e3c99003 bic r9, r9, #3 ; 0x3 + 7c38: e2890004 add r0, r9, #4 ; 0x4 + 7c3c: e58d0434 str r0, [sp, #1076] + 7c40: e2890000 add r0, r9, #0 ; 0x0 + 7c44: ebf5ef33 bl 0xffd83918 + 7c48: 080101f0 stmeqda r1, {r4, r5, r6, r7, r8} + 7c4c: e1a03000 mov r3, r0 + 7c50: ebf5f0ca bl 0xffd83f80 + 7c54: 080101ee stmeqda r1, {r1, r2, r3, r5, r6, r7, r8} + 7c58: e1a00003 mov r0, r3 + 7c5c: e28cc00e add ip, ip, #14 ; 0xe + 7c60: eaf5ed1a b 0xffd830d0 + 7c64: 0801026c stmeqda r1, {r2, r3, r5, r6, r9} + 7c68: 00000000 andeq r0, r0, r0 + 7c6c: ebf5f0c3 bl 0xffd83f80 + 7c70: 0801026c stmeqda r1, {r2, r3, r5, r6, r9} + 7c74: e59d9434 ldr r9, [sp, #1076] + 7c78: e3c99003 bic r9, r9, #3 ; 0x3 + 7c7c: e249900c sub r9, r9, #12 ; 0xc + 7c80: e58d9434 str r9, [sp, #1076] + 7c84: e2890000 add r0, r9, #0 ; 0x0 + 7c88: e1a01007 mov r1, r7 + 7c8c: ebf5ee6e bl 0xffd8364c + 7c90: e2890004 add r0, r9, #4 ; 0x4 + 7c94: e1a01008 mov r1, r8 + 7c98: ebf5ee6b bl 0xffd8364c + 7c9c: e2890008 add r0, r9, #8 ; 0x8 + 7ca0: e59d1438 ldr r1, [sp, #1080] + 7ca4: ebf5ee68 bl 0xffd8364c + 7ca8: ebf5f0b4 bl 0xffd83f80 + 7cac: 0801026e stmeqda r1, {r1, r2, r3, r5, r6, r9} + 7cb0: e59d0434 ldr r0, [sp, #1076] + 7cb4: e2400f05 sub r0, r0, #20 ; 0x14 + 7cb8: e58d0434 str r0, [sp, #1076] + 7cbc: ebf5f0af bl 0xffd83f80 + 7cc0: 08010270 stmeqda r1, {r4, r5, r6, r9} + 7cc4: e3b05000 movs r5, #0 ; 0x0 + 7cc8: ebf5f0ac bl 0xffd83f80 + 7ccc: 08010272 stmeqda r1, {r1, r4, r5, r6, r9} + 7cd0: e3a00fa3 mov r0, #652 ; 0x28c + 7cd4: e3800801 orr r0, r0, #65536 ; 0x10000 + 7cd8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7cdc: ebf5ef0d bl 0xffd83918 + 7ce0: 08010276 stmeqda r1, {r1, r2, r4, r5, r6, r9} + 7ce4: e1a03000 mov r3, r0 + 7ce8: ebf5f0a4 bl 0xffd83f80 + 7cec: 08010274 stmeqda r1, {r2, r4, r5, r6, r9} + 7cf0: e2830000 add r0, r3, #0 ; 0x0 + 7cf4: ebf5ef07 bl 0xffd83918 + 7cf8: 08010278 stmeqda r1, {r3, r4, r5, r6, r9} + 7cfc: e1a08000 mov r8, r0 + 7d00: ebf5f09e bl 0xffd83f80 + 7d04: 08010276 stmeqda r1, {r1, r2, r4, r5, r6, r9} + 7d08: e3a00e29 mov r0, #656 ; 0x290 + 7d0c: e3800801 orr r0, r0, #65536 ; 0x10000 + 7d10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7d14: ebf5eeff bl 0xffd83918 + 7d18: 0801027a stmeqda r1, {r1, r3, r4, r5, r6, r9} + 7d1c: e1a04000 mov r4, r0 + 7d20: ebf5f096 bl 0xffd83f80 + 7d24: 08010278 stmeqda r1, {r3, r4, r5, r6, r9} + 7d28: e3a00fa5 mov r0, #660 ; 0x294 + 7d2c: e3800801 orr r0, r0, #65536 ; 0x10000 + 7d30: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7d34: ebf5eef7 bl 0xffd83918 + 7d38: 0801027c stmeqda r1, {r2, r3, r4, r5, r6, r9} + 7d3c: e1a03000 mov r3, r0 + 7d40: ebf5f08e bl 0xffd83f80 + 7d44: 0801027a stmeqda r1, {r1, r3, r4, r5, r6, r9} + 7d48: e2830000 add r0, r3, #0 ; 0x0 + 7d4c: e1a01004 mov r1, r4 + 7d50: ebf5ee1d bl 0xffd835cc + 7d54: 0801027c stmeqda r1, {r2, r3, r4, r5, r6, r9} + 7d58: ebf5f088 bl 0xffd83f80 + 7d5c: 0801027c stmeqda r1, {r2, r3, r4, r5, r6, r9} + 7d60: e59d1434 ldr r1, [sp, #1076] + 7d64: e1a04001 mov r4, r1 + 7d68: ebf5f084 bl 0xffd83f80 + 7d6c: 0801027e stmeqda r1, {r1, r2, r3, r4, r5, r6, r9} + 7d70: e2830004 add r0, r3, #4 ; 0x4 + 7d74: e1a01004 mov r1, r4 + 7d78: ebf5ee13 bl 0xffd835cc + 7d7c: 08010280 stmeqda r1, {r7, r9} + 7d80: ebf5f07e bl 0xffd83f80 + 7d84: 08010280 stmeqda r1, {r7, r9} + 7d88: e3a00fa6 mov r0, #664 ; 0x298 + 7d8c: e3800801 orr r0, r0, #65536 ; 0x10000 + 7d90: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7d94: ebf5eedf bl 0xffd83918 + 7d98: 08010284 stmeqda r1, {r2, r7, r9} + 7d9c: e1a04000 mov r4, r0 + 7da0: ebf5f076 bl 0xffd83f80 + 7da4: 08010282 stmeqda r1, {r1, r7, r9} + 7da8: e2830008 add r0, r3, #8 ; 0x8 + 7dac: e1a01004 mov r1, r4 + 7db0: ebf5ee05 bl 0xffd835cc + 7db4: 08010284 stmeqda r1, {r2, r7, r9} + 7db8: ebf5f070 bl 0xffd83f80 + 7dbc: 08010284 stmeqda r1, {r2, r7, r9} + 7dc0: e2830008 add r0, r3, #8 ; 0x8 + 7dc4: ebf5eed3 bl 0xffd83918 + 7dc8: 08010288 stmeqda r1, {r3, r7, r9} + 7dcc: e1a03000 mov r3, r0 + 7dd0: ebf5f06a bl 0xffd83f80 + 7dd4: 08010286 stmeqda r1, {r1, r2, r7, r9} + 7dd8: e3b07000 movs r7, #0 ; 0x0 + 7ddc: ebf5f067 bl 0xffd83f80 + 7de0: 08010288 stmeqda r1, {r3, r7, r9} + 7de4: e28cc03e add ip, ip, #62 ; 0x3e + 7de8: e1a00fac mov r0, ip, lsr #31 + 7dec: e08ff100 add pc, pc, r0, lsl #2 + 7df0: 0801029e stmeqda r1, {r1, r2, r3, r4, r7, r9} + 7df4: ebf5ec56 bl 0xffd82f54 + 7df8: ea000001 b 0x7e04 + 7dfc: 0801029e stmeqda r1, {r1, r2, r3, r4, r7, r9} + 7e00: 00000000 andeq r0, r0, r0 + 7e04: ebf5f05d bl 0xffd83f80 + 7e08: 0801029e stmeqda r1, {r1, r2, r3, r4, r7, r9} + 7e0c: e3570009 cmp r7, #9 ; 0x9 + 7e10: ebf5f05a bl 0xffd83f80 + 7e14: 080102a0 stmeqda r1, {r5, r7, r9} + 7e18: e28cc006 add ip, ip, #6 ; 0x6 + 7e1c: 9a000004 bls 0x7e34 + 7e20: e1a00fac mov r0, ip, lsr #31 + 7e24: e08ff100 add pc, pc, r0, lsl #2 + 7e28: 080102bc stmeqda r1, {r2, r3, r4, r5, r7, r9} + 7e2c: ebf5ec48 bl 0xffd82f54 + 7e30: ea00001b b 0x7ea4 + 7e34: ebf5f051 bl 0xffd83f80 + 7e38: 080102a2 stmeqda r1, {r1, r5, r7, r9} + 7e3c: e59d1434 ldr r1, [sp, #1076] + 7e40: e1a03001 mov r3, r1 + 7e44: ebf5f04d bl 0xffd83f80 + 7e48: 080102a4 stmeqda r1, {r2, r5, r7, r9} + 7e4c: e1a01008 mov r1, r8 + 7e50: e2984000 adds r4, r8, #0 ; 0x0 + 7e54: ebf5f049 bl 0xffd83f80 + 7e58: 080102a6 stmeqda r1, {r1, r2, r5, r7, r9} + 7e5c: e3b05010 movs r5, #16 ; 0x10 + 7e60: ebf5f046 bl 0xffd83f80 + 7e64: 080102a8 stmeqda r1, {r3, r5, r7, r9} + 7e68: ebf5f044 bl 0xffd83f80 + 7e6c: 080102aa stmeqda r1, {r1, r3, r5, r7, r9} + 7e70: e3a000ad mov r0, #173 ; 0xad + 7e74: e3800c02 orr r0, r0, #512 ; 0x200 + 7e78: e3800801 orr r0, r0, #65536 ; 0x10000 + 7e7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7e80: e58d0438 str r0, [sp, #1080] + 7e84: e28cc00f add ip, ip, #15 ; 0xf + 7e88: e1a00fac mov r0, ip, lsr #31 + 7e8c: e08ff100 add pc, pc, r0, lsl #2 + 7e90: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 7e94: ebf5ec2e bl 0xffd82f54 + 7e98: ea000085 b 0x80b4 + 7e9c: 080102bc stmeqda r1, {r2, r3, r4, r5, r7, r9} + 7ea0: 00000000 andeq r0, r0, r0 + 7ea4: ebf5f035 bl 0xffd83f80 + 7ea8: 080102bc stmeqda r1, {r2, r3, r4, r5, r7, r9} + 7eac: e3550000 cmp r5, #0 ; 0x0 + 7eb0: ebf5f032 bl 0xffd83f80 + 7eb4: 080102be stmeqda r1, {r1, r2, r3, r4, r5, r7, r9} + 7eb8: e28cc006 add ip, ip, #6 ; 0x6 + 7ebc: 1a000004 bne 0x7ed4 + 7ec0: e1a00fac mov r0, ip, lsr #31 + 7ec4: e08ff100 add pc, pc, r0, lsl #2 + 7ec8: 080102de stmeqda r1, {r1, r2, r3, r4, r6, r7, r9} + 7ecc: ebf5ec20 bl 0xffd82f54 + 7ed0: ea000053 b 0x8024 + 7ed4: ebf5f029 bl 0xffd83f80 + 7ed8: 080102c0 stmeqda r1, {r6, r7, r9} + 7edc: e3b03000 movs r3, #0 ; 0x0 + 7ee0: ebf5f026 bl 0xffd83f80 + 7ee4: 080102c2 stmeqda r1, {r1, r6, r7, r9} + 7ee8: e59d0434 ldr r0, [sp, #1076] + 7eec: e2800f04 add r0, r0, #16 ; 0x10 + 7ef0: e1a01003 mov r1, r3 + 7ef4: ebf5edb4 bl 0xffd835cc + 7ef8: 080102c4 stmeqda r1, {r2, r6, r7, r9} + 7efc: ebf5f01f bl 0xffd83f80 + 7f00: 080102c4 stmeqda r1, {r2, r6, r7, r9} + 7f04: e3a00fba mov r0, #744 ; 0x2e8 + 7f08: e3800801 orr r0, r0, #65536 ; 0x10000 + 7f0c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7f10: ebf5ee80 bl 0xffd83918 + 7f14: 080102c8 stmeqda r1, {r3, r6, r7, r9} + 7f18: e1a04000 mov r4, r0 + 7f1c: ebf5f017 bl 0xffd83f80 + 7f20: 080102c6 stmeqda r1, {r1, r2, r6, r7, r9} + 7f24: e59d0434 ldr r0, [sp, #1076] + 7f28: e2803f04 add r3, r0, #16 ; 0x10 + 7f2c: ebf5f013 bl 0xffd83f80 + 7f30: 080102c8 stmeqda r1, {r3, r6, r7, r9} + 7f34: e2840000 add r0, r4, #0 ; 0x0 + 7f38: e1a01003 mov r1, r3 + 7f3c: ebf5eda2 bl 0xffd835cc + 7f40: 080102ca stmeqda r1, {r1, r3, r6, r7, r9} + 7f44: ebf5f00d bl 0xffd83f80 + 7f48: 080102ca stmeqda r1, {r1, r3, r6, r7, r9} + 7f4c: e59d1434 ldr r1, [sp, #1076] + 7f50: e1a03001 mov r3, r1 + 7f54: ebf5f009 bl 0xffd83f80 + 7f58: 080102cc stmeqda r1, {r2, r3, r6, r7, r9} + 7f5c: e2840004 add r0, r4, #4 ; 0x4 + 7f60: e1a01003 mov r1, r3 + 7f64: ebf5ed98 bl 0xffd835cc + 7f68: 080102ce stmeqda r1, {r1, r2, r3, r6, r7, r9} + 7f6c: ebf5f003 bl 0xffd83f80 + 7f70: 080102ce stmeqda r1, {r1, r2, r3, r6, r7, r9} + 7f74: e3a00fbb mov r0, #748 ; 0x2ec + 7f78: e3800801 orr r0, r0, #65536 ; 0x10000 + 7f7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 7f80: ebf5ee64 bl 0xffd83918 + 7f84: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 7f88: e1a03000 mov r3, r0 + 7f8c: ebf5effb bl 0xffd83f80 + 7f90: 080102d0 stmeqda r1, {r4, r6, r7, r9} + 7f94: e2840008 add r0, r4, #8 ; 0x8 + 7f98: e1a01003 mov r1, r3 + 7f9c: ebf5ed8a bl 0xffd835cc + 7fa0: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 7fa4: ebf5eff5 bl 0xffd83f80 + 7fa8: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 7fac: e2840008 add r0, r4, #8 ; 0x8 + 7fb0: ebf5ee58 bl 0xffd83918 + 7fb4: 080102d6 stmeqda r1, {r1, r2, r4, r6, r7, r9} + 7fb8: e1a03000 mov r3, r0 + 7fbc: ebf5efef bl 0xffd83f80 + 7fc0: 080102d4 stmeqda r1, {r2, r4, r6, r7, r9} + 7fc4: e59d1434 ldr r1, [sp, #1076] + 7fc8: e1a03001 mov r3, r1 + 7fcc: ebf5efeb bl 0xffd83f80 + 7fd0: 080102d6 stmeqda r1, {r1, r2, r4, r6, r7, r9} + 7fd4: e1a01008 mov r1, r8 + 7fd8: e2984000 adds r4, r8, #0 ; 0x0 + 7fdc: ebf5efe7 bl 0xffd83f80 + 7fe0: 080102d8 stmeqda r1, {r3, r4, r6, r7, r9} + 7fe4: e3b05010 movs r5, #16 ; 0x10 + 7fe8: ebf5efe4 bl 0xffd83f80 + 7fec: 080102da stmeqda r1, {r1, r3, r4, r6, r7, r9} + 7ff0: ebf5efe2 bl 0xffd83f80 + 7ff4: 080102dc stmeqda r1, {r2, r3, r4, r6, r7, r9} + 7ff8: e3a000df mov r0, #223 ; 0xdf + 7ffc: e3800c02 orr r0, r0, #512 ; 0x200 + 8000: e3800801 orr r0, r0, #65536 ; 0x10000 + 8004: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8008: e58d0438 str r0, [sp, #1080] + 800c: e28cc037 add ip, ip, #55 ; 0x37 + 8010: e1a00fac mov r0, ip, lsr #31 + 8014: e08ff100 add pc, pc, r0, lsl #2 + 8018: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 801c: ebf5ebcc bl 0xffd82f54 + 8020: ea000023 b 0x80b4 + 8024: ebf5efd5 bl 0xffd83f80 + 8028: 080102de stmeqda r1, {r1, r2, r3, r4, r6, r7, r9} + 802c: e59d0434 ldr r0, [sp, #1076] + 8030: e2800f05 add r0, r0, #20 ; 0x14 + 8034: e58d0434 str r0, [sp, #1076] + 8038: ebf5efd0 bl 0xffd83f80 + 803c: 080102e0 stmeqda r1, {r5, r6, r7, r9} + 8040: e59d9434 ldr r9, [sp, #1076] + 8044: e3c99003 bic r9, r9, #3 ; 0x3 + 8048: e2890008 add r0, r9, #8 ; 0x8 + 804c: e58d0434 str r0, [sp, #1076] + 8050: e2890000 add r0, r9, #0 ; 0x0 + 8054: ebf5ee2f bl 0xffd83918 + 8058: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 805c: e1a07000 mov r7, r0 + 8060: e2890004 add r0, r9, #4 ; 0x4 + 8064: ebf5ee2b bl 0xffd83918 + 8068: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 806c: e1a08000 mov r8, r0 + 8070: ebf5efc2 bl 0xffd83f80 + 8074: 080102e2 stmeqda r1, {r1, r5, r6, r7, r9} + 8078: e59d9434 ldr r9, [sp, #1076] + 807c: e3c99003 bic r9, r9, #3 ; 0x3 + 8080: e2890004 add r0, r9, #4 ; 0x4 + 8084: e58d0434 str r0, [sp, #1076] + 8088: e2890000 add r0, r9, #0 ; 0x0 + 808c: ebf5ee21 bl 0xffd83918 + 8090: 080102e6 stmeqda r1, {r1, r2, r5, r6, r7, r9} + 8094: e1a03000 mov r3, r0 + 8098: ebf5efb8 bl 0xffd83f80 + 809c: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 80a0: e1a00003 mov r0, r3 + 80a4: e28cc00f add ip, ip, #15 ; 0xf + 80a8: eaf5ec08 b 0xffd830d0 + 80ac: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 80b0: 00000000 andeq r0, r0, r0 + 80b4: ebf5efb1 bl 0xffd83f80 + 80b8: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 80bc: e59d9434 ldr r9, [sp, #1076] + 80c0: e3c99003 bic r9, r9, #3 ; 0x3 + 80c4: e2499008 sub r9, r9, #8 ; 0x8 + 80c8: e58d9434 str r9, [sp, #1076] + 80cc: e2890000 add r0, r9, #0 ; 0x0 + 80d0: e59d141c ldr r1, [sp, #1052] + 80d4: ebf5ed5c bl 0xffd8364c + 80d8: e2890004 add r0, r9, #4 ; 0x4 + 80dc: e59d1438 ldr r1, [sp, #1080] + 80e0: ebf5ed59 bl 0xffd8364c + 80e4: ebf5efa5 bl 0xffd83f80 + 80e8: 080c3062 stmeqda ip, {r1, r5, r6, ip, sp} + 80ec: e59d0434 ldr r0, [sp, #1076] + 80f0: e2400f03 sub r0, r0, #12 ; 0xc + 80f4: e58d0434 str r0, [sp, #1076] + 80f8: ebf5efa0 bl 0xffd83f80 + 80fc: 080c3064 stmeqda ip, {r2, r5, r6, ip, sp} + 8100: e59d1434 ldr r1, [sp, #1076] + 8104: e1a00001 mov r0, r1 + 8108: e58d041c str r0, [sp, #1052] + 810c: ebf5ef9b bl 0xffd83f80 + 8110: 080c3066 stmeqda ip, {r1, r2, r5, r6, ip, sp} + 8114: e59d041c ldr r0, [sp, #1052] + 8118: e2800000 add r0, r0, #0 ; 0x0 + 811c: e1a01003 mov r1, r3 + 8120: ebf5ed29 bl 0xffd835cc + 8124: 080c3068 stmeqda ip, {r3, r5, r6, ip, sp} + 8128: ebf5ef94 bl 0xffd83f80 + 812c: 080c3068 stmeqda ip, {r3, r5, r6, ip, sp} + 8130: e59d041c ldr r0, [sp, #1052] + 8134: e2800004 add r0, r0, #4 ; 0x4 + 8138: e1a01004 mov r1, r4 + 813c: ebf5ed22 bl 0xffd835cc + 8140: 080c306a stmeqda ip, {r1, r3, r5, r6, ip, sp} + 8144: ebf5ef8d bl 0xffd83f80 + 8148: 080c306a stmeqda ip, {r1, r3, r5, r6, ip, sp} + 814c: e59d041c ldr r0, [sp, #1052] + 8150: e2800008 add r0, r0, #8 ; 0x8 + 8154: e1a01005 mov r1, r5 + 8158: ebf5ed1b bl 0xffd835cc + 815c: 080c306c stmeqda ip, {r2, r3, r5, r6, ip, sp} + 8160: ebf5ef86 bl 0xffd83f80 + 8164: 080c306c stmeqda ip, {r2, r3, r5, r6, ip, sp} + 8168: e3a00f25 mov r0, #148 ; 0x94 + 816c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 8170: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8174: ebf5ede7 bl 0xffd83918 + 8178: 080c3070 stmeqda ip, {r4, r5, r6, ip, sp} + 817c: e1a03000 mov r3, r0 + 8180: ebf5ef7e bl 0xffd83f80 + 8184: 080c306e stmeqda ip, {r1, r2, r3, r5, r6, ip, sp} + 8188: e3a00f25 mov r0, #148 ; 0x94 + 818c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 8190: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8194: ebf5eddf bl 0xffd83918 + 8198: 080c3072 stmeqda ip, {r1, r4, r5, r6, ip, sp} + 819c: e1a04000 mov r4, r0 + 81a0: ebf5ef76 bl 0xffd83f80 + 81a4: 080c3070 stmeqda ip, {r4, r5, r6, ip, sp} + 81a8: e2840000 add r0, r4, #0 ; 0x0 + 81ac: ebf5edad bl 0xffd83868 + 81b0: 080c3074 stmeqda ip, {r2, r4, r5, r6, ip, sp} + 81b4: e1a05000 mov r5, r0 + 81b8: ebf5ef70 bl 0xffd83f80 + 81bc: 080c3072 stmeqda ip, {r1, r4, r5, r6, ip, sp} + 81c0: e3a00f26 mov r0, #152 ; 0x98 + 81c4: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 81c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 81cc: ebf5edd1 bl 0xffd83918 + 81d0: 080c3076 stmeqda ip, {r1, r2, r4, r5, r6, ip, sp} + 81d4: e1a06000 mov r6, r0 + 81d8: ebf5ef68 bl 0xffd83f80 + 81dc: 080c3074 stmeqda ip, {r2, r4, r5, r6, ip, sp} + 81e0: e1a01005 mov r1, r5 + 81e4: e2954000 adds r4, r5, #0 ; 0x0 + 81e8: ebf5ef64 bl 0xffd83f80 + 81ec: 080c3076 stmeqda ip, {r1, r2, r4, r5, r6, ip, sp} + 81f0: e1a01004 mov r1, r4 + 81f4: e0144006 ands r4, r4, r6 + 81f8: ebf5ef60 bl 0xffd83f80 + 81fc: 080c3078 stmeqda ip, {r3, r4, r5, r6, ip, sp} + 8200: e1a01004 mov r1, r4 + 8204: e2945000 adds r5, r4, #0 ; 0x0 + 8208: ebf5ef5c bl 0xffd83f80 + 820c: 080c307a stmeqda ip, {r1, r3, r4, r5, r6, ip, sp} + 8210: e3b06003 movs r6, #3 ; 0x3 + 8214: ebf5ef59 bl 0xffd83f80 + 8218: 080c307c stmeqda ip, {r2, r3, r4, r5, r6, ip, sp} + 821c: e1a01005 mov r1, r5 + 8220: e2954000 adds r4, r5, #0 ; 0x0 + 8224: ebf5ef55 bl 0xffd83f80 + 8228: 080c307e stmeqda ip, {r1, r2, r3, r4, r5, r6, ip, sp} + 822c: e1a01004 mov r1, r4 + 8230: e1944006 orrs r4, r4, r6 + 8234: ebf5ef51 bl 0xffd83f80 + 8238: 080c3080 stmeqda ip, {r7, ip, sp} + 823c: e1a01004 mov r1, r4 + 8240: e2945000 adds r5, r4, #0 ; 0x0 + 8244: ebf5ef4d bl 0xffd83f80 + 8248: 080c3082 stmeqda ip, {r1, r7, ip, sp} + 824c: e2830000 add r0, r3, #0 ; 0x0 + 8250: e1a01005 mov r1, r5 + 8254: ebf5ecbc bl 0xffd8354c + 8258: 080c3084 stmeqda ip, {r2, r7, ip, sp} + 825c: ebf5ef47 bl 0xffd83f80 + 8260: 080c3084 stmeqda ip, {r2, r7, ip, sp} + 8264: e59d041c ldr r0, [sp, #1052] + 8268: e2800008 add r0, r0, #8 ; 0x8 + 826c: ebf5eda9 bl 0xffd83918 + 8270: 080c3088 stmeqda ip, {r3, r7, ip, sp} + 8274: e1a03000 mov r3, r0 + 8278: ebf5ef40 bl 0xffd83f80 + 827c: 080c3086 stmeqda ip, {r1, r2, r7, ip, sp} + 8280: e1a01003 mov r1, r3 + 8284: e2534001 subs r4, r3, #1 ; 0x1 + 8288: ebf5ef3c bl 0xffd83f80 + 828c: 080c3088 stmeqda ip, {r3, r7, ip, sp} + 8290: e1a01004 mov r1, r4 + 8294: e2943000 adds r3, r4, #0 ; 0x0 + 8298: ebf5ef38 bl 0xffd83f80 + 829c: 080c308a stmeqda ip, {r1, r3, r7, ip, sp} + 82a0: e59d041c ldr r0, [sp, #1052] + 82a4: e2800008 add r0, r0, #8 ; 0x8 + 82a8: e1a01003 mov r1, r3 + 82ac: ebf5ecc6 bl 0xffd835cc + 82b0: 080c308c stmeqda ip, {r2, r3, r7, ip, sp} + 82b4: ebf5ef31 bl 0xffd83f80 + 82b8: 080c308c stmeqda ip, {r2, r3, r7, ip, sp} + 82bc: e3b04001 movs r4, #1 ; 0x1 + 82c0: ebf5ef2e bl 0xffd83f80 + 82c4: 080c308e stmeqda ip, {r1, r2, r3, r7, ip, sp} + 82c8: e1730004 cmn r3, r4 + 82cc: ebf5ef2b bl 0xffd83f80 + 82d0: 080c3090 stmeqda ip, {r4, r7, ip, sp} + 82d4: e28cc05b add ip, ip, #91 ; 0x5b + 82d8: 0a000004 beq 0x82f0 + 82dc: e1a00fac mov r0, ip, lsr #31 + 82e0: e08ff100 add pc, pc, r0, lsl #2 + 82e4: 080c309c stmeqda ip, {r2, r3, r4, r7, ip, sp} + 82e8: ebf5eb19 bl 0xffd82f54 + 82ec: ea000009 b 0x8318 + 82f0: ebf5ef22 bl 0xffd83f80 + 82f4: 080c3092 stmeqda ip, {r1, r4, r7, ip, sp} + 82f8: e28cc003 add ip, ip, #3 ; 0x3 + 82fc: e1a00fac mov r0, ip, lsr #31 + 8300: e08ff100 add pc, pc, r0, lsl #2 + 8304: 080c30b0 stmeqda ip, {r4, r5, r7, ip, sp} + 8308: ebf5eb11 bl 0xffd82f54 + 830c: ea00006d b 0x84c8 + 8310: 080c309c stmeqda ip, {r2, r3, r4, r7, ip, sp} + 8314: 00000000 andeq r0, r0, r0 + 8318: ebf5ef18 bl 0xffd83f80 + 831c: 080c309c stmeqda ip, {r2, r3, r4, r7, ip, sp} + 8320: e59d141c ldr r1, [sp, #1052] + 8324: e59d141c ldr r1, [sp, #1052] + 8328: e2913004 adds r3, r1, #4 ; 0x4 + 832c: ebf5ef13 bl 0xffd83f80 + 8330: 080c309e stmeqda ip, {r1, r2, r3, r4, r7, ip, sp} + 8334: e2830000 add r0, r3, #0 ; 0x0 + 8338: ebf5ed76 bl 0xffd83918 + 833c: 080c30a2 stmeqda ip, {r1, r5, r7, ip, sp} + 8340: e1a04000 mov r4, r0 + 8344: ebf5ef0d bl 0xffd83f80 + 8348: 080c30a0 stmeqda ip, {r5, r7, ip, sp} + 834c: e59d041c ldr r0, [sp, #1052] + 8350: e2800000 add r0, r0, #0 ; 0x0 + 8354: ebf5ed6f bl 0xffd83918 + 8358: 080c30a4 stmeqda ip, {r2, r5, r7, ip, sp} + 835c: e1a05000 mov r5, r0 + 8360: ebf5ef06 bl 0xffd83f80 + 8364: 080c30a2 stmeqda ip, {r1, r5, r7, ip, sp} + 8368: e2850000 add r0, r5, #0 ; 0x0 + 836c: ebf5ed12 bl 0xffd837bc + 8370: 080c30a6 stmeqda ip, {r1, r2, r5, r7, ip, sp} + 8374: e1a06000 mov r6, r0 + 8378: ebf5ef00 bl 0xffd83f80 + 837c: 080c30a4 stmeqda ip, {r2, r5, r7, ip, sp} + 8380: e2840000 add r0, r4, #0 ; 0x0 + 8384: e1a01006 mov r1, r6 + 8388: ebf5ec50 bl 0xffd834d0 + 838c: 080c30a6 stmeqda ip, {r1, r2, r5, r7, ip, sp} + 8390: ebf5eefa bl 0xffd83f80 + 8394: 080c30a6 stmeqda ip, {r1, r2, r5, r7, ip, sp} + 8398: e1a01005 mov r1, r5 + 839c: e2955001 adds r5, r5, #1 ; 0x1 + 83a0: ebf5eef6 bl 0xffd83f80 + 83a4: 080c30a8 stmeqda ip, {r3, r5, r7, ip, sp} + 83a8: e59d041c ldr r0, [sp, #1052] + 83ac: e2800000 add r0, r0, #0 ; 0x0 + 83b0: e1a01005 mov r1, r5 + 83b4: ebf5ec84 bl 0xffd835cc + 83b8: 080c30aa stmeqda ip, {r1, r3, r5, r7, ip, sp} + 83bc: ebf5eeef bl 0xffd83f80 + 83c0: 080c30aa stmeqda ip, {r1, r3, r5, r7, ip, sp} + 83c4: e1a01004 mov r1, r4 + 83c8: e2944001 adds r4, r4, #1 ; 0x1 + 83cc: ebf5eeeb bl 0xffd83f80 + 83d0: 080c30ac stmeqda ip, {r2, r3, r5, r7, ip, sp} + 83d4: e2830000 add r0, r3, #0 ; 0x0 + 83d8: e1a01004 mov r1, r4 + 83dc: ebf5ec7a bl 0xffd835cc + 83e0: 080c30ae stmeqda ip, {r1, r2, r3, r5, r7, ip, sp} + 83e4: ebf5eee5 bl 0xffd83f80 + 83e8: 080c30ae stmeqda ip, {r1, r2, r3, r5, r7, ip, sp} + 83ec: e28cc027 add ip, ip, #39 ; 0x27 + 83f0: e1a00fac mov r0, ip, lsr #31 + 83f4: e08ff100 add pc, pc, r0, lsl #2 + 83f8: 080c3084 stmeqda ip, {r2, r7, ip, sp} + 83fc: ebf5ead4 bl 0xffd82f54 + 8400: ea000001 b 0x840c + 8404: 080c3084 stmeqda ip, {r2, r7, ip, sp} + 8408: 00000000 andeq r0, r0, r0 + 840c: ebf5eedb bl 0xffd83f80 + 8410: 080c3084 stmeqda ip, {r2, r7, ip, sp} + 8414: e59d041c ldr r0, [sp, #1052] + 8418: e2800008 add r0, r0, #8 ; 0x8 + 841c: ebf5ed3d bl 0xffd83918 + 8420: 080c3088 stmeqda ip, {r3, r7, ip, sp} + 8424: e1a03000 mov r3, r0 + 8428: ebf5eed4 bl 0xffd83f80 + 842c: 080c3086 stmeqda ip, {r1, r2, r7, ip, sp} + 8430: e1a01003 mov r1, r3 + 8434: e2534001 subs r4, r3, #1 ; 0x1 + 8438: ebf5eed0 bl 0xffd83f80 + 843c: 080c3088 stmeqda ip, {r3, r7, ip, sp} + 8440: e1a01004 mov r1, r4 + 8444: e2943000 adds r3, r4, #0 ; 0x0 + 8448: ebf5eecc bl 0xffd83f80 + 844c: 080c308a stmeqda ip, {r1, r3, r7, ip, sp} + 8450: e59d041c ldr r0, [sp, #1052] + 8454: e2800008 add r0, r0, #8 ; 0x8 + 8458: e1a01003 mov r1, r3 + 845c: ebf5ec5a bl 0xffd835cc + 8460: 080c308c stmeqda ip, {r2, r3, r7, ip, sp} + 8464: ebf5eec5 bl 0xffd83f80 + 8468: 080c308c stmeqda ip, {r2, r3, r7, ip, sp} + 846c: e3b04001 movs r4, #1 ; 0x1 + 8470: ebf5eec2 bl 0xffd83f80 + 8474: 080c308e stmeqda ip, {r1, r2, r3, r7, ip, sp} + 8478: e1730004 cmn r3, r4 + 847c: ebf5eebf bl 0xffd83f80 + 8480: 080c3090 stmeqda ip, {r4, r7, ip, sp} + 8484: e28cc018 add ip, ip, #24 ; 0x18 + 8488: 0a000004 beq 0x84a0 + 848c: e1a00fac mov r0, ip, lsr #31 + 8490: e08ff100 add pc, pc, r0, lsl #2 + 8494: 080c309c stmeqda ip, {r2, r3, r4, r7, ip, sp} + 8498: ebf5eaad bl 0xffd82f54 + 849c: eaffff9d b 0x8318 + 84a0: ebf5eeb6 bl 0xffd83f80 + 84a4: 080c3092 stmeqda ip, {r1, r4, r7, ip, sp} + 84a8: e28cc003 add ip, ip, #3 ; 0x3 + 84ac: e1a00fac mov r0, ip, lsr #31 + 84b0: e08ff100 add pc, pc, r0, lsl #2 + 84b4: 080c30b0 stmeqda ip, {r4, r5, r7, ip, sp} + 84b8: ebf5eaa5 bl 0xffd82f54 + 84bc: ea000001 b 0x84c8 + 84c0: 080c30b0 stmeqda ip, {r4, r5, r7, ip, sp} + 84c4: 00000000 andeq r0, r0, r0 + 84c8: ebf5eeac bl 0xffd83f80 + 84cc: 080c30b0 stmeqda ip, {r4, r5, r7, ip, sp} + 84d0: e59d0434 ldr r0, [sp, #1076] + 84d4: e2800f03 add r0, r0, #12 ; 0xc + 84d8: e58d0434 str r0, [sp, #1076] + 84dc: ebf5eea7 bl 0xffd83f80 + 84e0: 080c30b2 stmeqda ip, {r1, r4, r5, r7, ip, sp} + 84e4: e59d9434 ldr r9, [sp, #1076] + 84e8: e3c99003 bic r9, r9, #3 ; 0x3 + 84ec: e2890004 add r0, r9, #4 ; 0x4 + 84f0: e58d0434 str r0, [sp, #1076] + 84f4: e2890000 add r0, r9, #0 ; 0x0 + 84f8: ebf5ed06 bl 0xffd83918 + 84fc: 080c30b6 stmeqda ip, {r1, r2, r4, r5, r7, ip, sp} + 8500: e58d041c str r0, [sp, #1052] + 8504: ebf5ee9d bl 0xffd83f80 + 8508: 080c30b4 stmeqda ip, {r2, r4, r5, r7, ip, sp} + 850c: e59d9434 ldr r9, [sp, #1076] + 8510: e3c99003 bic r9, r9, #3 ; 0x3 + 8514: e2890004 add r0, r9, #4 ; 0x4 + 8518: e58d0434 str r0, [sp, #1076] + 851c: e2890000 add r0, r9, #0 ; 0x0 + 8520: ebf5ecfc bl 0xffd83918 + 8524: 080c30b8 stmeqda ip, {r3, r4, r5, r7, ip, sp} + 8528: e1a03000 mov r3, r0 + 852c: ebf5ee93 bl 0xffd83f80 + 8530: 080c30b6 stmeqda ip, {r1, r2, r4, r5, r7, ip, sp} + 8534: e1a00003 mov r0, r3 + 8538: e28cc00e add ip, ip, #14 ; 0xe + 853c: eaf5eae3 b 0xffd830d0 + 8540: 080102ac stmeqda r1, {r2, r3, r5, r7, r9} + 8544: 00000000 andeq r0, r0, r0 + 8548: ebf5ee8c bl 0xffd83f80 + 854c: 080102ac stmeqda r1, {r2, r3, r5, r7, r9} + 8550: e59d1434 ldr r1, [sp, #1076] + 8554: e1a03001 mov r3, r1 + 8558: ebf5ee88 bl 0xffd83f80 + 855c: 080102ae stmeqda r1, {r1, r2, r3, r5, r7, r9} + 8560: e1a01008 mov r1, r8 + 8564: e2984000 adds r4, r8, #0 ; 0x0 + 8568: ebf5ee84 bl 0xffd83f80 + 856c: 080102b0 stmeqda r1, {r4, r5, r7, r9} + 8570: e3b05010 movs r5, #16 ; 0x10 + 8574: ebf5ee81 bl 0xffd83f80 + 8578: 080102b2 stmeqda r1, {r1, r4, r5, r7, r9} + 857c: ebf5ee7f bl 0xffd83f80 + 8580: 080102b4 stmeqda r1, {r2, r4, r5, r7, r9} + 8584: e3a000b7 mov r0, #183 ; 0xb7 + 8588: e3800c02 orr r0, r0, #512 ; 0x200 + 858c: e3800801 orr r0, r0, #65536 ; 0x10000 + 8590: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8594: e58d0438 str r0, [sp, #1080] + 8598: e28cc00f add ip, ip, #15 ; 0xf + 859c: e1a00fac mov r0, ip, lsr #31 + 85a0: e08ff100 add pc, pc, r0, lsl #2 + 85a4: 080c3100 stmeqda ip, {r8, ip, sp} + 85a8: ebf5ea69 bl 0xffd82f54 + 85ac: ea000001 b 0x85b8 + 85b0: 080c3100 stmeqda ip, {r8, ip, sp} + 85b4: 00000000 andeq r0, r0, r0 + 85b8: ebf5ee70 bl 0xffd83f80 + 85bc: 080c3100 stmeqda ip, {r8, ip, sp} + 85c0: e59d9434 ldr r9, [sp, #1076] + 85c4: e3c99003 bic r9, r9, #3 ; 0x3 + 85c8: e249900c sub r9, r9, #12 ; 0xc + 85cc: e58d9434 str r9, [sp, #1076] + 85d0: e2890000 add r0, r9, #0 ; 0x0 + 85d4: e1a01007 mov r1, r7 + 85d8: ebf5ec1b bl 0xffd8364c + 85dc: e2890004 add r0, r9, #4 ; 0x4 + 85e0: e59d141c ldr r1, [sp, #1052] + 85e4: ebf5ec18 bl 0xffd8364c + 85e8: e2890008 add r0, r9, #8 ; 0x8 + 85ec: e59d1438 ldr r1, [sp, #1080] + 85f0: ebf5ec15 bl 0xffd8364c + 85f4: ebf5ee61 bl 0xffd83f80 + 85f8: 080c3102 stmeqda ip, {r1, r8, ip, sp} + 85fc: e59d0434 ldr r0, [sp, #1076] + 8600: e2400f37 sub r0, r0, #220 ; 0xdc + 8604: e58d0434 str r0, [sp, #1076] + 8608: ebf5ee5c bl 0xffd83f80 + 860c: 080c3104 stmeqda ip, {r2, r8, ip, sp} + 8610: e59d1434 ldr r1, [sp, #1076] + 8614: e1a00001 mov r0, r1 + 8618: e58d041c str r0, [sp, #1052] + 861c: ebf5ee57 bl 0xffd83f80 + 8620: 080c3106 stmeqda ip, {r1, r2, r8, ip, sp} + 8624: e59d041c ldr r0, [sp, #1052] + 8628: e2800000 add r0, r0, #0 ; 0x0 + 862c: e1a01003 mov r1, r3 + 8630: ebf5ebe5 bl 0xffd835cc + 8634: 080c3108 stmeqda ip, {r3, r8, ip, sp} + 8638: ebf5ee50 bl 0xffd83f80 + 863c: 080c3108 stmeqda ip, {r3, r8, ip, sp} + 8640: e59d041c ldr r0, [sp, #1052] + 8644: e2800004 add r0, r0, #4 ; 0x4 + 8648: e1a01004 mov r1, r4 + 864c: ebf5ebde bl 0xffd835cc + 8650: 080c310a stmeqda ip, {r1, r3, r8, ip, sp} + 8654: ebf5ee49 bl 0xffd83f80 + 8658: 080c310a stmeqda ip, {r1, r3, r8, ip, sp} + 865c: e59d041c ldr r0, [sp, #1052] + 8660: e2800008 add r0, r0, #8 ; 0x8 + 8664: e1a01005 mov r1, r5 + 8668: ebf5ebd7 bl 0xffd835cc + 866c: 080c310c stmeqda ip, {r2, r3, r8, ip, sp} + 8670: ebf5ee42 bl 0xffd83f80 + 8674: 080c310c stmeqda ip, {r2, r3, r8, ip, sp} + 8678: e3a00f5b mov r0, #364 ; 0x16c + 867c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 8680: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8684: ebf5eca3 bl 0xffd83918 + 8688: 080c3110 stmeqda ip, {r4, r8, ip, sp} + 868c: e1a03000 mov r3, r0 + 8690: ebf5ee3a bl 0xffd83f80 + 8694: 080c310e stmeqda ip, {r1, r2, r3, r8, ip, sp} + 8698: e3a00f5b mov r0, #364 ; 0x16c + 869c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 86a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 86a4: ebf5ec9b bl 0xffd83918 + 86a8: 080c3112 stmeqda ip, {r1, r4, r8, ip, sp} + 86ac: e1a04000 mov r4, r0 + 86b0: ebf5ee32 bl 0xffd83f80 + 86b4: 080c3110 stmeqda ip, {r4, r8, ip, sp} + 86b8: e2840000 add r0, r4, #0 ; 0x0 + 86bc: ebf5ec69 bl 0xffd83868 + 86c0: 080c3114 stmeqda ip, {r2, r4, r8, ip, sp} + 86c4: e1a05000 mov r5, r0 + 86c8: ebf5ee2c bl 0xffd83f80 + 86cc: 080c3112 stmeqda ip, {r1, r4, r8, ip, sp} + 86d0: e3a00e17 mov r0, #368 ; 0x170 + 86d4: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 86d8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 86dc: ebf5ec8d bl 0xffd83918 + 86e0: 080c3116 stmeqda ip, {r1, r2, r4, r8, ip, sp} + 86e4: e1a06000 mov r6, r0 + 86e8: ebf5ee24 bl 0xffd83f80 + 86ec: 080c3114 stmeqda ip, {r2, r4, r8, ip, sp} + 86f0: e1a01005 mov r1, r5 + 86f4: e2954000 adds r4, r5, #0 ; 0x0 + 86f8: ebf5ee20 bl 0xffd83f80 + 86fc: 080c3116 stmeqda ip, {r1, r2, r4, r8, ip, sp} + 8700: e1a01004 mov r1, r4 + 8704: e0144006 ands r4, r4, r6 + 8708: ebf5ee1c bl 0xffd83f80 + 870c: 080c3118 stmeqda ip, {r3, r4, r8, ip, sp} + 8710: e1a01004 mov r1, r4 + 8714: e2945000 adds r5, r4, #0 ; 0x0 + 8718: ebf5ee18 bl 0xffd83f80 + 871c: 080c311a stmeqda ip, {r1, r3, r4, r8, ip, sp} + 8720: e3b06003 movs r6, #3 ; 0x3 + 8724: ebf5ee15 bl 0xffd83f80 + 8728: 080c311c stmeqda ip, {r2, r3, r4, r8, ip, sp} + 872c: e1a01005 mov r1, r5 + 8730: e2954000 adds r4, r5, #0 ; 0x0 + 8734: ebf5ee11 bl 0xffd83f80 + 8738: 080c311e stmeqda ip, {r1, r2, r3, r4, r8, ip, sp} + 873c: e1a01004 mov r1, r4 + 8740: e1944006 orrs r4, r4, r6 + 8744: ebf5ee0d bl 0xffd83f80 + 8748: 080c3120 stmeqda ip, {r5, r8, ip, sp} + 874c: e1a01004 mov r1, r4 + 8750: e2945000 adds r5, r4, #0 ; 0x0 + 8754: ebf5ee09 bl 0xffd83f80 + 8758: 080c3122 stmeqda ip, {r1, r5, r8, ip, sp} + 875c: e2830000 add r0, r3, #0 ; 0x0 + 8760: e1a01005 mov r1, r5 + 8764: ebf5eb78 bl 0xffd8354c + 8768: 080c3124 stmeqda ip, {r2, r5, r8, ip, sp} + 876c: ebf5ee03 bl 0xffd83f80 + 8770: 080c3124 stmeqda ip, {r2, r5, r8, ip, sp} + 8774: e59d141c ldr r1, [sp, #1052] + 8778: e59d141c ldr r1, [sp, #1052] + 877c: e2913000 adds r3, r1, #0 ; 0x0 + 8780: ebf5edfe bl 0xffd83f80 + 8784: 080c3126 stmeqda ip, {r1, r2, r5, r8, ip, sp} + 8788: e59d141c ldr r1, [sp, #1052] + 878c: e59d141c ldr r1, [sp, #1052] + 8790: e2914000 adds r4, r1, #0 ; 0x0 + 8794: ebf5edf9 bl 0xffd83f80 + 8798: 080c3128 stmeqda ip, {r3, r5, r8, ip, sp} + 879c: e1a01004 mov r1, r4 + 87a0: e29440d0 adds r4, r4, #208 ; 0xd0 + 87a4: ebf5edf5 bl 0xffd83f80 + 87a8: 080c312a stmeqda ip, {r1, r3, r5, r8, ip, sp} + 87ac: e3a00f5d mov r0, #372 ; 0x174 + 87b0: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 87b4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 87b8: ebf5ec56 bl 0xffd83918 + 87bc: 080c312e stmeqda ip, {r1, r2, r3, r5, r8, ip, sp} + 87c0: e1a03000 mov r3, r0 + 87c4: ebf5eded bl 0xffd83f80 + 87c8: 080c312c stmeqda ip, {r2, r3, r5, r8, ip, sp} + 87cc: e2840000 add r0, r4, #0 ; 0x0 + 87d0: e1a01003 mov r1, r3 + 87d4: ebf5eb7c bl 0xffd835cc + 87d8: 080c312e stmeqda ip, {r1, r2, r3, r5, r8, ip, sp} + 87dc: ebf5ede7 bl 0xffd83f80 + 87e0: 080c312e stmeqda ip, {r1, r2, r3, r5, r8, ip, sp} + 87e4: e59d141c ldr r1, [sp, #1052] + 87e8: e59d141c ldr r1, [sp, #1052] + 87ec: e2914000 adds r4, r1, #0 ; 0x0 + 87f0: ebf5ede2 bl 0xffd83f80 + 87f4: 080c3130 stmeqda ip, {r4, r5, r8, ip, sp} + 87f8: e59d141c ldr r1, [sp, #1052] + 87fc: e59d141c ldr r1, [sp, #1052] + 8800: e2913000 adds r3, r1, #0 ; 0x0 + 8804: ebf5eddd bl 0xffd83f80 + 8808: 080c3132 stmeqda ip, {r1, r4, r5, r8, ip, sp} + 880c: e1a01003 mov r1, r3 + 8810: e29330d0 adds r3, r3, #208 ; 0xd0 + 8814: ebf5edd9 bl 0xffd83f80 + 8818: 080c3134 stmeqda ip, {r2, r4, r5, r8, ip, sp} + 881c: e59d141c ldr r1, [sp, #1052] + 8820: e59d141c ldr r1, [sp, #1052] + 8824: e2914000 adds r4, r1, #0 ; 0x0 + 8828: ebf5edd4 bl 0xffd83f80 + 882c: 080c3136 stmeqda ip, {r1, r2, r4, r5, r8, ip, sp} + 8830: e59d141c ldr r1, [sp, #1052] + 8834: e59d141c ldr r1, [sp, #1052] + 8838: e2915000 adds r5, r1, #0 ; 0x0 + 883c: ebf5edcf bl 0xffd83f80 + 8840: 080c3138 stmeqda ip, {r3, r4, r5, r8, ip, sp} + 8844: e1a01005 mov r1, r5 + 8848: e29550d0 adds r5, r5, #208 ; 0xd0 + 884c: ebf5edcb bl 0xffd83f80 + 8850: 080c313a stmeqda ip, {r1, r3, r4, r5, r8, ip, sp} + 8854: e2850000 add r0, r5, #0 ; 0x0 + 8858: ebf5ec2e bl 0xffd83918 + 885c: 080c313e stmeqda ip, {r1, r2, r3, r4, r5, r8, ip, sp} + 8860: e1a04000 mov r4, r0 + 8864: ebf5edc5 bl 0xffd83f80 + 8868: 080c313c stmeqda ip, {r2, r3, r4, r5, r8, ip, sp} + 886c: e3b05001 movs r5, #1 ; 0x1 + 8870: ebf5edc2 bl 0xffd83f80 + 8874: 080c313e stmeqda ip, {r1, r2, r3, r4, r5, r8, ip, sp} + 8878: e1a01004 mov r1, r4 + 887c: e0344005 eors r4, r4, r5 + 8880: ebf5edbe bl 0xffd83f80 + 8884: 080c3140 stmeqda ip, {r6, r8, ip, sp} + 8888: e2830000 add r0, r3, #0 ; 0x0 + 888c: e1a01004 mov r1, r4 + 8890: ebf5eb4d bl 0xffd835cc + 8894: 080c3142 stmeqda ip, {r1, r6, r8, ip, sp} + 8898: ebf5edb8 bl 0xffd83f80 + 889c: 080c3142 stmeqda ip, {r1, r6, r8, ip, sp} + 88a0: e59d141c ldr r1, [sp, #1052] + 88a4: e59d141c ldr r1, [sp, #1052] + 88a8: e2913000 adds r3, r1, #0 ; 0x0 + 88ac: ebf5edb3 bl 0xffd83f80 + 88b0: 080c3144 stmeqda ip, {r2, r6, r8, ip, sp} + 88b4: e59d141c ldr r1, [sp, #1052] + 88b8: e59d141c ldr r1, [sp, #1052] + 88bc: e2914000 adds r4, r1, #0 ; 0x0 + 88c0: ebf5edae bl 0xffd83f80 + 88c4: 080c3146 stmeqda ip, {r1, r2, r6, r8, ip, sp} + 88c8: e1a01004 mov r1, r4 + 88cc: e29440d4 adds r4, r4, #212 ; 0xd4 + 88d0: ebf5edaa bl 0xffd83f80 + 88d4: 080c3148 stmeqda ip, {r3, r6, r8, ip, sp} + 88d8: e59d141c ldr r1, [sp, #1052] + 88dc: e59d141c ldr r1, [sp, #1052] + 88e0: e2913000 adds r3, r1, #0 ; 0x0 + 88e4: ebf5eda5 bl 0xffd83f80 + 88e8: 080c314a stmeqda ip, {r1, r3, r6, r8, ip, sp} + 88ec: e1a01003 mov r1, r3 + 88f0: e2933010 adds r3, r3, #16 ; 0x10 + 88f4: ebf5eda1 bl 0xffd83f80 + 88f8: 080c314c stmeqda ip, {r2, r3, r6, r8, ip, sp} + 88fc: e2840000 add r0, r4, #0 ; 0x0 + 8900: e1a01003 mov r1, r3 + 8904: ebf5eb30 bl 0xffd835cc + 8908: 080c314e stmeqda ip, {r1, r2, r3, r6, r8, ip, sp} + 890c: ebf5ed9b bl 0xffd83f80 + 8910: 080c314e stmeqda ip, {r1, r2, r3, r6, r8, ip, sp} + 8914: e59d141c ldr r1, [sp, #1052] + 8918: e59d141c ldr r1, [sp, #1052] + 891c: e2913000 adds r3, r1, #0 ; 0x0 + 8920: ebf5ed96 bl 0xffd83f80 + 8924: 080c3150 stmeqda ip, {r4, r6, r8, ip, sp} + 8928: e1a01003 mov r1, r3 + 892c: e293300c adds r3, r3, #12 ; 0xc + 8930: ebf5ed92 bl 0xffd83f80 + 8934: 080c3152 stmeqda ip, {r1, r4, r6, r8, ip, sp} + 8938: e3a00f5e mov r0, #376 ; 0x178 + 893c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 8940: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8944: ebf5ebf3 bl 0xffd83918 + 8948: 080c3156 stmeqda ip, {r1, r2, r4, r6, r8, ip, sp} + 894c: e1a04000 mov r4, r0 + 8950: ebf5ed8a bl 0xffd83f80 + 8954: 080c3154 stmeqda ip, {r2, r4, r6, r8, ip, sp} + 8958: e3a00f5d mov r0, #372 ; 0x174 + 895c: e3800ac3 orr r0, r0, #798720 ; 0xc3000 + 8960: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8964: ebf5ebeb bl 0xffd83918 + 8968: 080c3158 stmeqda ip, {r3, r4, r6, r8, ip, sp} + 896c: e1a05000 mov r5, r0 + 8970: ebf5ed82 bl 0xffd83f80 + 8974: 080c3156 stmeqda ip, {r1, r2, r4, r6, r8, ip, sp} + 8978: e1a01004 mov r1, r4 + 897c: e0544005 subs r4, r4, r5 + 8980: ebf5ed7e bl 0xffd83f80 + 8984: 080c3158 stmeqda ip, {r3, r4, r6, r8, ip, sp} + 8988: e1b050a4 movs r5, r4, lsr #1 + 898c: ebf5ed7b bl 0xffd83f80 + 8990: 080c315a stmeqda ip, {r1, r3, r4, r6, r8, ip, sp} + 8994: e1a01005 mov r1, r5 + 8998: e2954000 adds r4, r5, #0 ; 0x0 + 899c: ebf5ed77 bl 0xffd83f80 + 89a0: 080c315c stmeqda ip, {r2, r3, r4, r6, r8, ip, sp} + 89a4: e2830000 add r0, r3, #0 ; 0x0 + 89a8: e1a01004 mov r1, r4 + 89ac: ebf5eae6 bl 0xffd8354c + 89b0: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 89b4: ebf5ed71 bl 0xffd83f80 + 89b8: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 89bc: e59d141c ldr r1, [sp, #1052] + 89c0: e59d141c ldr r1, [sp, #1052] + 89c4: e2913000 adds r3, r1, #0 ; 0x0 + 89c8: ebf5ed6c bl 0xffd83f80 + 89cc: 080c3160 stmeqda ip, {r5, r6, r8, ip, sp} + 89d0: e1a01003 mov r1, r3 + 89d4: e293300c adds r3, r3, #12 ; 0xc + 89d8: ebf5ed68 bl 0xffd83f80 + 89dc: 080c3162 stmeqda ip, {r1, r5, r6, r8, ip, sp} + 89e0: e2830000 add r0, r3, #0 ; 0x0 + 89e4: ebf5eb9f bl 0xffd83868 + 89e8: 080c3166 stmeqda ip, {r1, r2, r5, r6, r8, ip, sp} + 89ec: e1a04000 mov r4, r0 + 89f0: ebf5ed62 bl 0xffd83f80 + 89f4: 080c3164 stmeqda ip, {r2, r5, r6, r8, ip, sp} + 89f8: e3540000 cmp r4, #0 ; 0x0 + 89fc: ebf5ed5f bl 0xffd83f80 + 8a00: 080c3166 stmeqda ip, {r1, r2, r5, r6, r8, ip, sp} + 8a04: e28cc0b8 add ip, ip, #184 ; 0xb8 + 8a08: 0a000004 beq 0x8a20 + 8a0c: e1a00fac mov r0, ip, lsr #31 + 8a10: e08ff100 add pc, pc, r0, lsl #2 + 8a14: 080c317c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip, sp} + 8a18: ebf5e94d bl 0xffd82f54 + 8a1c: ea000009 b 0x8a48 + 8a20: ebf5ed56 bl 0xffd83f80 + 8a24: 080c3168 stmeqda ip, {r3, r5, r6, r8, ip, sp} + 8a28: e28cc003 add ip, ip, #3 ; 0x3 + 8a2c: e1a00fac mov r0, ip, lsr #31 + 8a30: e08ff100 add pc, pc, r0, lsl #2 + 8a34: 080c31ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip, sp} + 8a38: ebf5e945 bl 0xffd82f54 + 8a3c: ea0000a7 b 0x8ce0 + 8a40: 080c317c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip, sp} + 8a44: 00000000 andeq r0, r0, r0 + 8a48: ebf5ed4c bl 0xffd83f80 + 8a4c: 080c317c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip, sp} + 8a50: e59d141c ldr r1, [sp, #1052] + 8a54: e59d141c ldr r1, [sp, #1052] + 8a58: e2914000 adds r4, r1, #0 ; 0x0 + 8a5c: ebf5ed47 bl 0xffd83f80 + 8a60: 080c317e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, ip, sp} + 8a64: e59d141c ldr r1, [sp, #1052] + 8a68: e59d141c ldr r1, [sp, #1052] + 8a6c: e2913000 adds r3, r1, #0 ; 0x0 + 8a70: ebf5ed42 bl 0xffd83f80 + 8a74: 080c3180 stmeqda ip, {r7, r8, ip, sp} + 8a78: e1a01003 mov r1, r3 + 8a7c: e29330d4 adds r3, r3, #212 ; 0xd4 + 8a80: ebf5ed3e bl 0xffd83f80 + 8a84: 080c3182 stmeqda ip, {r1, r7, r8, ip, sp} + 8a88: e2830000 add r0, r3, #0 ; 0x0 + 8a8c: ebf5eba1 bl 0xffd83918 + 8a90: 080c3186 stmeqda ip, {r1, r2, r7, r8, ip, sp} + 8a94: e1a04000 mov r4, r0 + 8a98: ebf5ed38 bl 0xffd83f80 + 8a9c: 080c3184 stmeqda ip, {r2, r7, r8, ip, sp} + 8aa0: e59d141c ldr r1, [sp, #1052] + 8aa4: e59d141c ldr r1, [sp, #1052] + 8aa8: e2916000 adds r6, r1, #0 ; 0x0 + 8aac: ebf5ed33 bl 0xffd83f80 + 8ab0: 080c3186 stmeqda ip, {r1, r2, r7, r8, ip, sp} + 8ab4: e59d141c ldr r1, [sp, #1052] + 8ab8: e59d141c ldr r1, [sp, #1052] + 8abc: e2915000 adds r5, r1, #0 ; 0x0 + 8ac0: ebf5ed2e bl 0xffd83f80 + 8ac4: 080c3188 stmeqda ip, {r3, r7, r8, ip, sp} + 8ac8: e1a01005 mov r1, r5 + 8acc: e29550d0 adds r5, r5, #208 ; 0xd0 + 8ad0: ebf5ed2a bl 0xffd83f80 + 8ad4: 080c318a stmeqda ip, {r1, r3, r7, r8, ip, sp} + 8ad8: e2850000 add r0, r5, #0 ; 0x0 + 8adc: ebf5eb8d bl 0xffd83918 + 8ae0: 080c318e stmeqda ip, {r1, r2, r3, r7, r8, ip, sp} + 8ae4: e1a06000 mov r6, r0 + 8ae8: ebf5ed24 bl 0xffd83f80 + 8aec: 080c318c stmeqda ip, {r2, r3, r7, r8, ip, sp} + 8af0: e2860000 add r0, r6, #0 ; 0x0 + 8af4: ebf5eb5b bl 0xffd83868 + 8af8: 080c3190 stmeqda ip, {r4, r7, r8, ip, sp} + 8afc: e1a07000 mov r7, r0 + 8b00: ebf5ed1e bl 0xffd83f80 + 8b04: 080c318e stmeqda ip, {r1, r2, r3, r7, r8, ip, sp} + 8b08: e2840000 add r0, r4, #0 ; 0x0 + 8b0c: e1a01007 mov r1, r7 + 8b10: ebf5ea8d bl 0xffd8354c + 8b14: 080c3190 stmeqda ip, {r4, r7, r8, ip, sp} + 8b18: ebf5ed18 bl 0xffd83f80 + 8b1c: 080c3190 stmeqda ip, {r4, r7, r8, ip, sp} + 8b20: e1a01006 mov r1, r6 + 8b24: e2966002 adds r6, r6, #2 ; 0x2 + 8b28: ebf5ed14 bl 0xffd83f80 + 8b2c: 080c3192 stmeqda ip, {r1, r4, r7, r8, ip, sp} + 8b30: e2850000 add r0, r5, #0 ; 0x0 + 8b34: e1a01006 mov r1, r6 + 8b38: ebf5eaa3 bl 0xffd835cc + 8b3c: 080c3194 stmeqda ip, {r2, r4, r7, r8, ip, sp} + 8b40: ebf5ed0e bl 0xffd83f80 + 8b44: 080c3194 stmeqda ip, {r2, r4, r7, r8, ip, sp} + 8b48: e1a01004 mov r1, r4 + 8b4c: e2944002 adds r4, r4, #2 ; 0x2 + 8b50: ebf5ed0a bl 0xffd83f80 + 8b54: 080c3196 stmeqda ip, {r1, r2, r4, r7, r8, ip, sp} + 8b58: e2830000 add r0, r3, #0 ; 0x0 + 8b5c: e1a01004 mov r1, r4 + 8b60: ebf5ea99 bl 0xffd835cc + 8b64: 080c3198 stmeqda ip, {r3, r4, r7, r8, ip, sp} + 8b68: ebf5ed04 bl 0xffd83f80 + 8b6c: 080c3198 stmeqda ip, {r3, r4, r7, r8, ip, sp} + 8b70: e59d141c ldr r1, [sp, #1052] + 8b74: e59d141c ldr r1, [sp, #1052] + 8b78: e2914000 adds r4, r1, #0 ; 0x0 + 8b7c: ebf5ecff bl 0xffd83f80 + 8b80: 080c319a stmeqda ip, {r1, r3, r4, r7, r8, ip, sp} + 8b84: e1a01004 mov r1, r4 + 8b88: e294400c adds r4, r4, #12 ; 0xc + 8b8c: ebf5ecfb bl 0xffd83f80 + 8b90: 080c319c stmeqda ip, {r2, r3, r4, r7, r8, ip, sp} + 8b94: e59d141c ldr r1, [sp, #1052] + 8b98: e59d141c ldr r1, [sp, #1052] + 8b9c: e2913000 adds r3, r1, #0 ; 0x0 + 8ba0: ebf5ecf6 bl 0xffd83f80 + 8ba4: 080c319e stmeqda ip, {r1, r2, r3, r4, r7, r8, ip, sp} + 8ba8: e1a01003 mov r1, r3 + 8bac: e293300c adds r3, r3, #12 ; 0xc + 8bb0: ebf5ecf2 bl 0xffd83f80 + 8bb4: 080c31a0 stmeqda ip, {r5, r7, r8, ip, sp} + 8bb8: e59d141c ldr r1, [sp, #1052] + 8bbc: e59d141c ldr r1, [sp, #1052] + 8bc0: e2914000 adds r4, r1, #0 ; 0x0 + 8bc4: ebf5eced bl 0xffd83f80 + 8bc8: 080c31a2 stmeqda ip, {r1, r5, r7, r8, ip, sp} + 8bcc: e1a01004 mov r1, r4 + 8bd0: e294400c adds r4, r4, #12 ; 0xc + 8bd4: ebf5ece9 bl 0xffd83f80 + 8bd8: 080c31a4 stmeqda ip, {r2, r5, r7, r8, ip, sp} + 8bdc: e2840000 add r0, r4, #0 ; 0x0 + 8be0: ebf5eb20 bl 0xffd83868 + 8be4: 080c31a8 stmeqda ip, {r3, r5, r7, r8, ip, sp} + 8be8: e1a05000 mov r5, r0 + 8bec: ebf5ece3 bl 0xffd83f80 + 8bf0: 080c31a6 stmeqda ip, {r1, r2, r5, r7, r8, ip, sp} + 8bf4: e1a01005 mov r1, r5 + 8bf8: e2554001 subs r4, r5, #1 ; 0x1 + 8bfc: ebf5ecdf bl 0xffd83f80 + 8c00: 080c31a8 stmeqda ip, {r3, r5, r7, r8, ip, sp} + 8c04: e1a01004 mov r1, r4 + 8c08: e2945000 adds r5, r4, #0 ; 0x0 + 8c0c: ebf5ecdb bl 0xffd83f80 + 8c10: 080c31aa stmeqda ip, {r1, r3, r5, r7, r8, ip, sp} + 8c14: e2830000 add r0, r3, #0 ; 0x0 + 8c18: e1a01005 mov r1, r5 + 8c1c: ebf5ea4a bl 0xffd8354c + 8c20: 080c31ac stmeqda ip, {r2, r3, r5, r7, r8, ip, sp} + 8c24: ebf5ecd5 bl 0xffd83f80 + 8c28: 080c31ac stmeqda ip, {r2, r3, r5, r7, r8, ip, sp} + 8c2c: e28cc057 add ip, ip, #87 ; 0x57 + 8c30: e1a00fac mov r0, ip, lsr #31 + 8c34: e08ff100 add pc, pc, r0, lsl #2 + 8c38: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 8c3c: ebf5e8c4 bl 0xffd82f54 + 8c40: ea000001 b 0x8c4c + 8c44: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 8c48: 00000000 andeq r0, r0, r0 + 8c4c: ebf5eccb bl 0xffd83f80 + 8c50: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 8c54: e59d141c ldr r1, [sp, #1052] + 8c58: e59d141c ldr r1, [sp, #1052] + 8c5c: e2913000 adds r3, r1, #0 ; 0x0 + 8c60: ebf5ecc6 bl 0xffd83f80 + 8c64: 080c3160 stmeqda ip, {r5, r6, r8, ip, sp} + 8c68: e1a01003 mov r1, r3 + 8c6c: e293300c adds r3, r3, #12 ; 0xc + 8c70: ebf5ecc2 bl 0xffd83f80 + 8c74: 080c3162 stmeqda ip, {r1, r5, r6, r8, ip, sp} + 8c78: e2830000 add r0, r3, #0 ; 0x0 + 8c7c: ebf5eaf9 bl 0xffd83868 + 8c80: 080c3166 stmeqda ip, {r1, r2, r5, r6, r8, ip, sp} + 8c84: e1a04000 mov r4, r0 + 8c88: ebf5ecbc bl 0xffd83f80 + 8c8c: 080c3164 stmeqda ip, {r2, r5, r6, r8, ip, sp} + 8c90: e3540000 cmp r4, #0 ; 0x0 + 8c94: ebf5ecb9 bl 0xffd83f80 + 8c98: 080c3166 stmeqda ip, {r1, r2, r5, r6, r8, ip, sp} + 8c9c: e28cc011 add ip, ip, #17 ; 0x11 + 8ca0: 0a000004 beq 0x8cb8 + 8ca4: e1a00fac mov r0, ip, lsr #31 + 8ca8: e08ff100 add pc, pc, r0, lsl #2 + 8cac: 080c317c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip, sp} + 8cb0: ebf5e8a7 bl 0xffd82f54 + 8cb4: eaffff63 b 0x8a48 + 8cb8: ebf5ecb0 bl 0xffd83f80 + 8cbc: 080c3168 stmeqda ip, {r3, r5, r6, r8, ip, sp} + 8cc0: e28cc003 add ip, ip, #3 ; 0x3 + 8cc4: e1a00fac mov r0, ip, lsr #31 + 8cc8: e08ff100 add pc, pc, r0, lsl #2 + 8ccc: 080c31ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip, sp} + 8cd0: ebf5e89f bl 0xffd82f54 + 8cd4: ea000001 b 0x8ce0 + 8cd8: 080c31ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip, sp} + 8cdc: 00000000 andeq r0, r0, r0 + 8ce0: ebf5eca6 bl 0xffd83f80 + 8ce4: 080c31ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip, sp} + 8ce8: e59d141c ldr r1, [sp, #1052] + 8cec: e59d141c ldr r1, [sp, #1052] + 8cf0: e2914000 adds r4, r1, #0 ; 0x0 + 8cf4: ebf5eca1 bl 0xffd83f80 + 8cf8: 080c31b0 stmeqda ip, {r4, r5, r7, r8, ip, sp} + 8cfc: e59d141c ldr r1, [sp, #1052] + 8d00: e59d141c ldr r1, [sp, #1052] + 8d04: e2913000 adds r3, r1, #0 ; 0x0 + 8d08: ebf5ec9c bl 0xffd83f80 + 8d0c: 080c31b2 stmeqda ip, {r1, r4, r5, r7, r8, ip, sp} + 8d10: e1a01003 mov r1, r3 + 8d14: e29330d8 adds r3, r3, #216 ; 0xd8 + 8d18: ebf5ec98 bl 0xffd83f80 + 8d1c: 080c31b4 stmeqda ip, {r2, r4, r5, r7, r8, ip, sp} + 8d20: e59d141c ldr r1, [sp, #1052] + 8d24: e59d141c ldr r1, [sp, #1052] + 8d28: e2914000 adds r4, r1, #0 ; 0x0 + 8d2c: ebf5ec93 bl 0xffd83f80 + 8d30: 080c31b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, ip, sp} + 8d34: e1a01004 mov r1, r4 + 8d38: e2944010 adds r4, r4, #16 ; 0x10 + 8d3c: ebf5ec8f bl 0xffd83f80 + 8d40: 080c31b8 stmeqda ip, {r3, r4, r5, r7, r8, ip, sp} + 8d44: e1a01004 mov r1, r4 + 8d48: e2945001 adds r5, r4, #1 ; 0x1 + 8d4c: ebf5ec8b bl 0xffd83f80 + 8d50: 080c31ba stmeqda ip, {r1, r3, r4, r5, r7, r8, ip, sp} + 8d54: e2830000 add r0, r3, #0 ; 0x0 + 8d58: e1a01005 mov r1, r5 + 8d5c: ebf5ea1a bl 0xffd835cc + 8d60: 080c31bc stmeqda ip, {r2, r3, r4, r5, r7, r8, ip, sp} + 8d64: ebf5ec85 bl 0xffd83f80 + 8d68: 080c31bc stmeqda ip, {r2, r3, r4, r5, r7, r8, ip, sp} + 8d6c: e59d141c ldr r1, [sp, #1052] + 8d70: e59d141c ldr r1, [sp, #1052] + 8d74: e2914000 adds r4, r1, #0 ; 0x0 + 8d78: ebf5ec80 bl 0xffd83f80 + 8d7c: 080c31be stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, ip, sp} + 8d80: e59d141c ldr r1, [sp, #1052] + 8d84: e59d141c ldr r1, [sp, #1052] + 8d88: e2913000 adds r3, r1, #0 ; 0x0 + 8d8c: ebf5ec7b bl 0xffd83f80 + 8d90: 080c31c0 stmeqda ip, {r6, r7, r8, ip, sp} + 8d94: e1a01003 mov r1, r3 + 8d98: e29330d8 adds r3, r3, #216 ; 0xd8 + 8d9c: ebf5ec77 bl 0xffd83f80 + 8da0: 080c31c2 stmeqda ip, {r1, r6, r7, r8, ip, sp} + 8da4: e59d041c ldr r0, [sp, #1052] + 8da8: e2800004 add r0, r0, #4 ; 0x4 + 8dac: ebf5ead9 bl 0xffd83918 + 8db0: 080c31c6 stmeqda ip, {r1, r2, r6, r7, r8, ip, sp} + 8db4: e1a04000 mov r4, r0 + 8db8: ebf5ec70 bl 0xffd83f80 + 8dbc: 080c31c4 stmeqda ip, {r2, r6, r7, r8, ip, sp} + 8dc0: e59d041c ldr r0, [sp, #1052] + 8dc4: e2800008 add r0, r0, #8 ; 0x8 + 8dc8: ebf5ead2 bl 0xffd83918 + 8dcc: 080c31c8 stmeqda ip, {r3, r6, r7, r8, ip, sp} + 8dd0: e1a05000 mov r5, r0 + 8dd4: ebf5ec69 bl 0xffd83f80 + 8dd8: 080c31c6 stmeqda ip, {r1, r2, r6, r7, r8, ip, sp} + 8ddc: e2830000 add r0, r3, #0 ; 0x0 + 8de0: ebf5eacc bl 0xffd83918 + 8de4: 080c31ca stmeqda ip, {r1, r3, r6, r7, r8, ip, sp} + 8de8: e1a06000 mov r6, r0 + 8dec: ebf5ec63 bl 0xffd83f80 + 8df0: 080c31c8 stmeqda ip, {r3, r6, r7, r8, ip, sp} + 8df4: e59d041c ldr r0, [sp, #1052] + 8df8: e2800000 add r0, r0, #0 ; 0x0 + 8dfc: ebf5eac5 bl 0xffd83918 + 8e00: 080c31cc stmeqda ip, {r2, r3, r6, r7, r8, ip, sp} + 8e04: e1a03000 mov r3, r0 + 8e08: ebf5ec5c bl 0xffd83f80 + 8e0c: 080c31ca stmeqda ip, {r1, r3, r6, r7, r8, ip, sp} + 8e10: ebf5ec5a bl 0xffd83f80 + 8e14: 080c31cc stmeqda ip, {r2, r3, r6, r7, r8, ip, sp} + 8e18: e3a000cf mov r0, #207 ; 0xcf + 8e1c: e3800c31 orr r0, r0, #12544 ; 0x3100 + 8e20: e3800703 orr r0, r0, #786432 ; 0xc0000 + 8e24: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8e28: e58d0438 str r0, [sp, #1080] + 8e2c: e28cc039 add ip, ip, #57 ; 0x39 + 8e30: e1a00fac mov r0, ip, lsr #31 + 8e34: e08ff100 add pc, pc, r0, lsl #2 + 8e38: 080c31e8 stmeqda ip, {r3, r5, r6, r7, r8, ip, sp} + 8e3c: ebf5e844 bl 0xffd82f54 + 8e40: eafff9f1 b 0x760c + 8e44: 080c31ce stmeqda ip, {r1, r2, r3, r6, r7, r8, ip, sp} + 8e48: 00000000 andeq r0, r0, r0 + 8e4c: ebf5ec4b bl 0xffd83f80 + 8e50: 080c31ce stmeqda ip, {r1, r2, r3, r6, r7, r8, ip, sp} + 8e54: e1a01003 mov r1, r3 + 8e58: e2934000 adds r4, r3, #0 ; 0x0 + 8e5c: ebf5ec47 bl 0xffd83f80 + 8e60: 080c31d0 stmeqda ip, {r4, r6, r7, r8, ip, sp} + 8e64: e1a01004 mov r1, r4 + 8e68: e2943000 adds r3, r4, #0 ; 0x0 + 8e6c: ebf5ec43 bl 0xffd83f80 + 8e70: 080c31d2 stmeqda ip, {r1, r4, r6, r7, r8, ip, sp} + 8e74: e28cc009 add ip, ip, #9 ; 0x9 + 8e78: e1a00fac mov r0, ip, lsr #31 + 8e7c: e08ff100 add pc, pc, r0, lsl #2 + 8e80: 080c31d4 stmeqda ip, {r2, r4, r6, r7, r8, ip, sp} + 8e84: ebf5e832 bl 0xffd82f54 + 8e88: ea000001 b 0x8e94 + 8e8c: 080c31d4 stmeqda ip, {r2, r4, r6, r7, r8, ip, sp} + 8e90: 00000000 andeq r0, r0, r0 + 8e94: ebf5ec39 bl 0xffd83f80 + 8e98: 080c31d4 stmeqda ip, {r2, r4, r6, r7, r8, ip, sp} + 8e9c: e59d0434 ldr r0, [sp, #1076] + 8ea0: e2800f37 add r0, r0, #220 ; 0xdc + 8ea4: e58d0434 str r0, [sp, #1076] + 8ea8: ebf5ec34 bl 0xffd83f80 + 8eac: 080c31d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, ip, sp} + 8eb0: e59d9434 ldr r9, [sp, #1076] + 8eb4: e3c99003 bic r9, r9, #3 ; 0x3 + 8eb8: e2890008 add r0, r9, #8 ; 0x8 + 8ebc: e58d0434 str r0, [sp, #1076] + 8ec0: e2890000 add r0, r9, #0 ; 0x0 + 8ec4: ebf5ea93 bl 0xffd83918 + 8ec8: 080c31da stmeqda ip, {r1, r3, r4, r6, r7, r8, ip, sp} + 8ecc: e1a07000 mov r7, r0 + 8ed0: e2890004 add r0, r9, #4 ; 0x4 + 8ed4: ebf5ea8f bl 0xffd83918 + 8ed8: 080c31da stmeqda ip, {r1, r3, r4, r6, r7, r8, ip, sp} + 8edc: e58d041c str r0, [sp, #1052] + 8ee0: ebf5ec26 bl 0xffd83f80 + 8ee4: 080c31d8 stmeqda ip, {r3, r4, r6, r7, r8, ip, sp} + 8ee8: e59d9434 ldr r9, [sp, #1076] + 8eec: e3c99003 bic r9, r9, #3 ; 0x3 + 8ef0: e2890004 add r0, r9, #4 ; 0x4 + 8ef4: e58d0434 str r0, [sp, #1076] + 8ef8: e2890000 add r0, r9, #0 ; 0x0 + 8efc: ebf5ea85 bl 0xffd83918 + 8f00: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + 8f04: e1a04000 mov r4, r0 + 8f08: ebf5ec1c bl 0xffd83f80 + 8f0c: 080c31da stmeqda ip, {r1, r3, r4, r6, r7, r8, ip, sp} + 8f10: e1a00004 mov r0, r4 + 8f14: e28cc00f add ip, ip, #15 ; 0xf + 8f18: eaf5e86c b 0xffd830d0 + 8f1c: 080102b6 stmeqda r1, {r1, r2, r4, r5, r7, r9} + 8f20: 00000000 andeq r0, r0, r0 + 8f24: ebf5ec15 bl 0xffd83f80 + 8f28: 080102b6 stmeqda r1, {r1, r2, r4, r5, r7, r9} + 8f2c: e1a01003 mov r1, r3 + 8f30: e2935000 adds r5, r3, #0 ; 0x0 + 8f34: ebf5ec11 bl 0xffd83f80 + 8f38: 080102b8 stmeqda r1, {r3, r4, r5, r7, r9} + 8f3c: e3550000 cmp r5, #0 ; 0x0 + 8f40: ebf5ec0e bl 0xffd83f80 + 8f44: 080102ba stmeqda r1, {r1, r3, r4, r5, r7, r9} + 8f48: e28cc009 add ip, ip, #9 ; 0x9 + 8f4c: 0a000004 beq 0x8f64 + 8f50: e1a00fac mov r0, ip, lsr #31 + 8f54: e08ff100 add pc, pc, r0, lsl #2 + 8f58: 0801029c stmeqda r1, {r2, r3, r4, r7, r9} + 8f5c: ebf5e7fc bl 0xffd82f54 + 8f60: ea000083 b 0x9174 + 8f64: ebf5ec05 bl 0xffd83f80 + 8f68: 080102bc stmeqda r1, {r2, r3, r4, r5, r7, r9} + 8f6c: e3550000 cmp r5, #0 ; 0x0 + 8f70: ebf5ec02 bl 0xffd83f80 + 8f74: 080102be stmeqda r1, {r1, r2, r3, r4, r5, r7, r9} + 8f78: e28cc006 add ip, ip, #6 ; 0x6 + 8f7c: 1a000004 bne 0x8f94 + 8f80: e1a00fac mov r0, ip, lsr #31 + 8f84: e08ff100 add pc, pc, r0, lsl #2 + 8f88: 080102de stmeqda r1, {r1, r2, r3, r4, r6, r7, r9} + 8f8c: ebf5e7f0 bl 0xffd82f54 + 8f90: ea000053 b 0x90e4 + 8f94: ebf5ebf9 bl 0xffd83f80 + 8f98: 080102c0 stmeqda r1, {r6, r7, r9} + 8f9c: e3b03000 movs r3, #0 ; 0x0 + 8fa0: ebf5ebf6 bl 0xffd83f80 + 8fa4: 080102c2 stmeqda r1, {r1, r6, r7, r9} + 8fa8: e59d0434 ldr r0, [sp, #1076] + 8fac: e2800f04 add r0, r0, #16 ; 0x10 + 8fb0: e1a01003 mov r1, r3 + 8fb4: ebf5e984 bl 0xffd835cc + 8fb8: 080102c4 stmeqda r1, {r2, r6, r7, r9} + 8fbc: ebf5ebef bl 0xffd83f80 + 8fc0: 080102c4 stmeqda r1, {r2, r6, r7, r9} + 8fc4: e3a00fba mov r0, #744 ; 0x2e8 + 8fc8: e3800801 orr r0, r0, #65536 ; 0x10000 + 8fcc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 8fd0: ebf5ea50 bl 0xffd83918 + 8fd4: 080102c8 stmeqda r1, {r3, r6, r7, r9} + 8fd8: e1a04000 mov r4, r0 + 8fdc: ebf5ebe7 bl 0xffd83f80 + 8fe0: 080102c6 stmeqda r1, {r1, r2, r6, r7, r9} + 8fe4: e59d0434 ldr r0, [sp, #1076] + 8fe8: e2803f04 add r3, r0, #16 ; 0x10 + 8fec: ebf5ebe3 bl 0xffd83f80 + 8ff0: 080102c8 stmeqda r1, {r3, r6, r7, r9} + 8ff4: e2840000 add r0, r4, #0 ; 0x0 + 8ff8: e1a01003 mov r1, r3 + 8ffc: ebf5e972 bl 0xffd835cc + 9000: 080102ca stmeqda r1, {r1, r3, r6, r7, r9} + 9004: ebf5ebdd bl 0xffd83f80 + 9008: 080102ca stmeqda r1, {r1, r3, r6, r7, r9} + 900c: e59d1434 ldr r1, [sp, #1076] + 9010: e1a03001 mov r3, r1 + 9014: ebf5ebd9 bl 0xffd83f80 + 9018: 080102cc stmeqda r1, {r2, r3, r6, r7, r9} + 901c: e2840004 add r0, r4, #4 ; 0x4 + 9020: e1a01003 mov r1, r3 + 9024: ebf5e968 bl 0xffd835cc + 9028: 080102ce stmeqda r1, {r1, r2, r3, r6, r7, r9} + 902c: ebf5ebd3 bl 0xffd83f80 + 9030: 080102ce stmeqda r1, {r1, r2, r3, r6, r7, r9} + 9034: e3a00fbb mov r0, #748 ; 0x2ec + 9038: e3800801 orr r0, r0, #65536 ; 0x10000 + 903c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9040: ebf5ea34 bl 0xffd83918 + 9044: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 9048: e1a03000 mov r3, r0 + 904c: ebf5ebcb bl 0xffd83f80 + 9050: 080102d0 stmeqda r1, {r4, r6, r7, r9} + 9054: e2840008 add r0, r4, #8 ; 0x8 + 9058: e1a01003 mov r1, r3 + 905c: ebf5e95a bl 0xffd835cc + 9060: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 9064: ebf5ebc5 bl 0xffd83f80 + 9068: 080102d2 stmeqda r1, {r1, r4, r6, r7, r9} + 906c: e2840008 add r0, r4, #8 ; 0x8 + 9070: ebf5ea28 bl 0xffd83918 + 9074: 080102d6 stmeqda r1, {r1, r2, r4, r6, r7, r9} + 9078: e1a03000 mov r3, r0 + 907c: ebf5ebbf bl 0xffd83f80 + 9080: 080102d4 stmeqda r1, {r2, r4, r6, r7, r9} + 9084: e59d1434 ldr r1, [sp, #1076] + 9088: e1a03001 mov r3, r1 + 908c: ebf5ebbb bl 0xffd83f80 + 9090: 080102d6 stmeqda r1, {r1, r2, r4, r6, r7, r9} + 9094: e1a01008 mov r1, r8 + 9098: e2984000 adds r4, r8, #0 ; 0x0 + 909c: ebf5ebb7 bl 0xffd83f80 + 90a0: 080102d8 stmeqda r1, {r3, r4, r6, r7, r9} + 90a4: e3b05010 movs r5, #16 ; 0x10 + 90a8: ebf5ebb4 bl 0xffd83f80 + 90ac: 080102da stmeqda r1, {r1, r3, r4, r6, r7, r9} + 90b0: ebf5ebb2 bl 0xffd83f80 + 90b4: 080102dc stmeqda r1, {r2, r3, r4, r6, r7, r9} + 90b8: e3a000df mov r0, #223 ; 0xdf + 90bc: e3800c02 orr r0, r0, #512 ; 0x200 + 90c0: e3800801 orr r0, r0, #65536 ; 0x10000 + 90c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 90c8: e58d0438 str r0, [sp, #1080] + 90cc: e28cc037 add ip, ip, #55 ; 0x37 + 90d0: e1a00fac mov r0, ip, lsr #31 + 90d4: e08ff100 add pc, pc, r0, lsl #2 + 90d8: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 90dc: ebf5e79c bl 0xffd82f54 + 90e0: eafffbf3 b 0x80b4 + 90e4: ebf5eba5 bl 0xffd83f80 + 90e8: 080102de stmeqda r1, {r1, r2, r3, r4, r6, r7, r9} + 90ec: e59d0434 ldr r0, [sp, #1076] + 90f0: e2800f05 add r0, r0, #20 ; 0x14 + 90f4: e58d0434 str r0, [sp, #1076] + 90f8: ebf5eba0 bl 0xffd83f80 + 90fc: 080102e0 stmeqda r1, {r5, r6, r7, r9} + 9100: e59d9434 ldr r9, [sp, #1076] + 9104: e3c99003 bic r9, r9, #3 ; 0x3 + 9108: e2890008 add r0, r9, #8 ; 0x8 + 910c: e58d0434 str r0, [sp, #1076] + 9110: e2890000 add r0, r9, #0 ; 0x0 + 9114: ebf5e9ff bl 0xffd83918 + 9118: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 911c: e1a07000 mov r7, r0 + 9120: e2890004 add r0, r9, #4 ; 0x4 + 9124: ebf5e9fb bl 0xffd83918 + 9128: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 912c: e1a08000 mov r8, r0 + 9130: ebf5eb92 bl 0xffd83f80 + 9134: 080102e2 stmeqda r1, {r1, r5, r6, r7, r9} + 9138: e59d9434 ldr r9, [sp, #1076] + 913c: e3c99003 bic r9, r9, #3 ; 0x3 + 9140: e2890004 add r0, r9, #4 ; 0x4 + 9144: e58d0434 str r0, [sp, #1076] + 9148: e2890000 add r0, r9, #0 ; 0x0 + 914c: ebf5e9f1 bl 0xffd83918 + 9150: 080102e6 stmeqda r1, {r1, r2, r5, r6, r7, r9} + 9154: e1a03000 mov r3, r0 + 9158: ebf5eb88 bl 0xffd83f80 + 915c: 080102e4 stmeqda r1, {r2, r5, r6, r7, r9} + 9160: e1a00003 mov r0, r3 + 9164: e28cc00f add ip, ip, #15 ; 0xf + 9168: eaf5e7d8 b 0xffd830d0 + 916c: 0801029c stmeqda r1, {r2, r3, r4, r7, r9} + 9170: 00000000 andeq r0, r0, r0 + 9174: ebf5eb81 bl 0xffd83f80 + 9178: 0801029c stmeqda r1, {r2, r3, r4, r7, r9} + 917c: e1a01007 mov r1, r7 + 9180: e2977001 adds r7, r7, #1 ; 0x1 + 9184: ebf5eb7d bl 0xffd83f80 + 9188: 0801029e stmeqda r1, {r1, r2, r3, r4, r7, r9} + 918c: e3570009 cmp r7, #9 ; 0x9 + 9190: ebf5eb7a bl 0xffd83f80 + 9194: 080102a0 stmeqda r1, {r5, r7, r9} + 9198: e28cc009 add ip, ip, #9 ; 0x9 + 919c: 9a000004 bls 0x91b4 + 91a0: e1a00fac mov r0, ip, lsr #31 + 91a4: e08ff100 add pc, pc, r0, lsl #2 + 91a8: 080102bc stmeqda r1, {r2, r3, r4, r5, r7, r9} + 91ac: ebf5e768 bl 0xffd82f54 + 91b0: eafffb3b b 0x7ea4 + 91b4: ebf5eb71 bl 0xffd83f80 + 91b8: 080102a2 stmeqda r1, {r1, r5, r7, r9} + 91bc: e59d1434 ldr r1, [sp, #1076] + 91c0: e1a03001 mov r3, r1 + 91c4: ebf5eb6d bl 0xffd83f80 + 91c8: 080102a4 stmeqda r1, {r2, r5, r7, r9} + 91cc: e1a01008 mov r1, r8 + 91d0: e2984000 adds r4, r8, #0 ; 0x0 + 91d4: ebf5eb69 bl 0xffd83f80 + 91d8: 080102a6 stmeqda r1, {r1, r2, r5, r7, r9} + 91dc: e3b05010 movs r5, #16 ; 0x10 + 91e0: ebf5eb66 bl 0xffd83f80 + 91e4: 080102a8 stmeqda r1, {r3, r5, r7, r9} + 91e8: ebf5eb64 bl 0xffd83f80 + 91ec: 080102aa stmeqda r1, {r1, r3, r5, r7, r9} + 91f0: e3a000ad mov r0, #173 ; 0xad + 91f4: e3800c02 orr r0, r0, #512 ; 0x200 + 91f8: e3800801 orr r0, r0, #65536 ; 0x10000 + 91fc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9200: e58d0438 str r0, [sp, #1080] + 9204: e28cc00f add ip, ip, #15 ; 0xf + 9208: e1a00fac mov r0, ip, lsr #31 + 920c: e08ff100 add pc, pc, r0, lsl #2 + 9210: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 9214: ebf5e74e bl 0xffd82f54 + 9218: eafffba5 b 0x80b4 + 921c: 080101d8 stmeqda r1, {r3, r4, r6, r7, r8} + 9220: 00000000 andeq r0, r0, r0 + 9224: ebf5eb55 bl 0xffd83f80 + 9228: 080101d8 stmeqda r1, {r3, r4, r6, r7, r8} + 922c: e3b07000 movs r7, #0 ; 0x0 + 9230: ebf5eb52 bl 0xffd83f80 + 9234: 080101da stmeqda r1, {r1, r3, r4, r6, r7, r8} + 9238: e1b03c07 movs r3, r7, lsl #24 + 923c: ebf5eb4f bl 0xffd83f80 + 9240: 080101dc stmeqda r1, {r2, r3, r4, r6, r7, r8} + 9244: e1b03c23 movs r3, r3, lsr #24 + 9248: ebf5eb4c bl 0xffd83f80 + 924c: 080101de stmeqda r1, {r1, r2, r3, r4, r6, r7, r8} + 9250: ebf5eb4a bl 0xffd83f80 + 9254: 080101e0 stmeqda r1, {r5, r6, r7, r8} + 9258: e3a000e3 mov r0, #227 ; 0xe3 + 925c: e3800c01 orr r0, r0, #256 ; 0x100 + 9260: e3800801 orr r0, r0, #65536 ; 0x10000 + 9264: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9268: e58d0438 str r0, [sp, #1080] + 926c: e28cc00f add ip, ip, #15 ; 0xf + 9270: e1a00fac mov r0, ip, lsr #31 + 9274: e08ff100 add pc, pc, r0, lsl #2 + 9278: 08010320 stmeqda r1, {r5, r8, r9} + 927c: ebf5e734 bl 0xffd82f54 + 9280: ea000001 b 0x928c + 9284: 08010320 stmeqda r1, {r5, r8, r9} + 9288: 00000000 andeq r0, r0, r0 + 928c: ebf5eb3b bl 0xffd83f80 + 9290: 08010320 stmeqda r1, {r5, r8, r9} + 9294: e59d9434 ldr r9, [sp, #1076] + 9298: e3c99003 bic r9, r9, #3 ; 0x3 + 929c: e2499010 sub r9, r9, #16 ; 0x10 + 92a0: e58d9434 str r9, [sp, #1076] + 92a4: e2890000 add r0, r9, #0 ; 0x0 + 92a8: e1a01007 mov r1, r7 + 92ac: ebf5e8e6 bl 0xffd8364c + 92b0: e2890004 add r0, r9, #4 ; 0x4 + 92b4: e1a01008 mov r1, r8 + 92b8: ebf5e8e3 bl 0xffd8364c + 92bc: e2890008 add r0, r9, #8 ; 0x8 + 92c0: e59d1418 ldr r1, [sp, #1048] + 92c4: ebf5e8e0 bl 0xffd8364c + 92c8: e289000c add r0, r9, #12 ; 0xc + 92cc: e59d1438 ldr r1, [sp, #1080] + 92d0: ebf5e8dd bl 0xffd8364c + 92d4: ebf5eb29 bl 0xffd83f80 + 92d8: 08010322 stmeqda r1, {r1, r5, r8, r9} + 92dc: e3a00e36 mov r0, #864 ; 0x360 + 92e0: e3800801 orr r0, r0, #65536 ; 0x10000 + 92e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 92e8: ebf5e98a bl 0xffd83918 + 92ec: 08010326 stmeqda r1, {r1, r2, r5, r8, r9} + 92f0: e1a07000 mov r7, r0 + 92f4: ebf5eb21 bl 0xffd83f80 + 92f8: 08010324 stmeqda r1, {r2, r5, r8, r9} + 92fc: e59d0434 ldr r0, [sp, #1076] + 9300: e0800007 add r0, r0, r7 + 9304: e58d0434 str r0, [sp, #1076] + 9308: ebf5eb1c bl 0xffd83f80 + 930c: 08010326 stmeqda r1, {r1, r2, r5, r8, r9} + 9310: e1b03c03 movs r3, r3, lsl #24 + 9314: ebf5eb19 bl 0xffd83f80 + 9318: 08010328 stmeqda r1, {r3, r5, r8, r9} + 931c: e1b03c23 movs r3, r3, lsr #24 + 9320: ebf5eb16 bl 0xffd83f80 + 9324: 0801032a stmeqda r1, {r1, r3, r5, r8, r9} + 9328: e3a00fd9 mov r0, #868 ; 0x364 + 932c: e3800801 orr r0, r0, #65536 ; 0x10000 + 9330: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9334: ebf5e977 bl 0xffd83918 + 9338: 0801032e stmeqda r1, {r1, r2, r3, r5, r8, r9} + 933c: e1a05000 mov r5, r0 + 9340: ebf5eb0e bl 0xffd83f80 + 9344: 0801032c stmeqda r1, {r2, r3, r5, r8, r9} + 9348: e1b04203 movs r4, r3, lsl #4 + 934c: ebf5eb0b bl 0xffd83f80 + 9350: 0801032e stmeqda r1, {r1, r2, r3, r5, r8, r9} + 9354: e1a01004 mov r1, r4 + 9358: e0544003 subs r4, r4, r3 + 935c: ebf5eb07 bl 0xffd83f80 + 9360: 08010330 stmeqda r1, {r4, r5, r8, r9} + 9364: e1b04104 movs r4, r4, lsl #2 + 9368: ebf5eb04 bl 0xffd83f80 + 936c: 08010332 stmeqda r1, {r1, r4, r5, r8, r9} + 9370: e1a01004 mov r1, r4 + 9374: e0944003 adds r4, r4, r3 + 9378: ebf5eb00 bl 0xffd83f80 + 937c: 08010334 stmeqda r1, {r2, r4, r5, r8, r9} + 9380: e1b04204 movs r4, r4, lsl #4 + 9384: ebf5eafd bl 0xffd83f80 + 9388: 08010336 stmeqda r1, {r1, r2, r4, r5, r8, r9} + 938c: e1a01004 mov r1, r4 + 9390: e2944010 adds r4, r4, #16 ; 0x10 + 9394: ebf5eaf9 bl 0xffd83f80 + 9398: 08010338 stmeqda r1, {r3, r4, r5, r8, r9} + 939c: e2850000 add r0, r5, #0 ; 0x0 + 93a0: ebf5e95c bl 0xffd83918 + 93a4: 0801033c stmeqda r1, {r2, r3, r4, r5, r8, r9} + 93a8: e1a03000 mov r3, r0 + 93ac: ebf5eaf3 bl 0xffd83f80 + 93b0: 0801033a stmeqda r1, {r1, r3, r4, r5, r8, r9} + 93b4: e1a01003 mov r1, r3 + 93b8: e0938004 adds r8, r3, r4 + 93bc: ebf5eaef bl 0xffd83f80 + 93c0: 0801033c stmeqda r1, {r2, r3, r4, r5, r8, r9} + 93c4: e3a00fda mov r0, #872 ; 0x368 + 93c8: e3800801 orr r0, r0, #65536 ; 0x10000 + 93cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 93d0: ebf5e950 bl 0xffd83918 + 93d4: 08010340 stmeqda r1, {r6, r8, r9} + 93d8: e1a04000 mov r4, r0 + 93dc: ebf5eae7 bl 0xffd83f80 + 93e0: 0801033e stmeqda r1, {r1, r2, r3, r4, r5, r8, r9} + 93e4: e3a00fdb mov r0, #876 ; 0x36c + 93e8: e3800801 orr r0, r0, #65536 ; 0x10000 + 93ec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 93f0: ebf5e948 bl 0xffd83918 + 93f4: 08010342 stmeqda r1, {r1, r6, r8, r9} + 93f8: e1a03000 mov r3, r0 + 93fc: ebf5eadf bl 0xffd83f80 + 9400: 08010340 stmeqda r1, {r6, r8, r9} + 9404: e2830000 add r0, r3, #0 ; 0x0 + 9408: e1a01004 mov r1, r4 + 940c: ebf5e86e bl 0xffd835cc + 9410: 08010342 stmeqda r1, {r1, r6, r8, r9} + 9414: ebf5ead9 bl 0xffd83f80 + 9418: 08010342 stmeqda r1, {r1, r6, r8, r9} + 941c: e59d1434 ldr r1, [sp, #1076] + 9420: e1a04001 mov r4, r1 + 9424: ebf5ead5 bl 0xffd83f80 + 9428: 08010344 stmeqda r1, {r2, r6, r8, r9} + 942c: e2830004 add r0, r3, #4 ; 0x4 + 9430: e1a01004 mov r1, r4 + 9434: ebf5e864 bl 0xffd835cc + 9438: 08010346 stmeqda r1, {r1, r2, r6, r8, r9} + 943c: ebf5eacf bl 0xffd83f80 + 9440: 08010346 stmeqda r1, {r1, r2, r6, r8, r9} + 9444: e3a00e37 mov r0, #880 ; 0x370 + 9448: e3800801 orr r0, r0, #65536 ; 0x10000 + 944c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9450: ebf5e930 bl 0xffd83918 + 9454: 0801034a stmeqda r1, {r1, r3, r6, r8, r9} + 9458: e1a04000 mov r4, r0 + 945c: ebf5eac7 bl 0xffd83f80 + 9460: 08010348 stmeqda r1, {r3, r6, r8, r9} + 9464: e2830008 add r0, r3, #8 ; 0x8 + 9468: e1a01004 mov r1, r4 + 946c: ebf5e856 bl 0xffd835cc + 9470: 0801034a stmeqda r1, {r1, r3, r6, r8, r9} + 9474: ebf5eac1 bl 0xffd83f80 + 9478: 0801034a stmeqda r1, {r1, r3, r6, r8, r9} + 947c: e2830008 add r0, r3, #8 ; 0x8 + 9480: ebf5e924 bl 0xffd83918 + 9484: 0801034e stmeqda r1, {r1, r2, r3, r6, r8, r9} + 9488: e1a03000 mov r3, r0 + 948c: ebf5eabb bl 0xffd83f80 + 9490: 0801034c stmeqda r1, {r2, r3, r6, r8, r9} + 9494: e59d1434 ldr r1, [sp, #1076] + 9498: e1a03001 mov r3, r1 + 949c: ebf5eab7 bl 0xffd83f80 + 94a0: 0801034e stmeqda r1, {r1, r2, r3, r6, r8, r9} + 94a4: ebf5eab5 bl 0xffd83f80 + 94a8: 08010350 stmeqda r1, {r4, r6, r8, r9} + 94ac: e3a00053 mov r0, #83 ; 0x53 + 94b0: e3800c03 orr r0, r0, #768 ; 0x300 + 94b4: e3800801 orr r0, r0, #65536 ; 0x10000 + 94b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 94bc: e58d0438 str r0, [sp, #1080] + 94c0: e28cc05f add ip, ip, #95 ; 0x5f + 94c4: e1a00fac mov r0, ip, lsr #31 + 94c8: e08ff100 add pc, pc, r0, lsl #2 + 94cc: 08010490 stmeqda r1, {r4, r7, sl} + 94d0: ebf5e69f bl 0xffd82f54 + 94d4: ea000001 b 0x94e0 + 94d8: 08010490 stmeqda r1, {r4, r7, sl} + 94dc: 00000000 andeq r0, r0, r0 + 94e0: ebf5eaa6 bl 0xffd83f80 + 94e4: 08010490 stmeqda r1, {r4, r7, sl} + 94e8: e59d9434 ldr r9, [sp, #1076] + 94ec: e3c99003 bic r9, r9, #3 ; 0x3 + 94f0: e249900c sub r9, r9, #12 ; 0xc + 94f4: e58d9434 str r9, [sp, #1076] + 94f8: e2890000 add r0, r9, #0 ; 0x0 + 94fc: e1a01007 mov r1, r7 + 9500: ebf5e851 bl 0xffd8364c + 9504: e2890004 add r0, r9, #4 ; 0x4 + 9508: e1a01008 mov r1, r8 + 950c: ebf5e84e bl 0xffd8364c + 9510: e2890008 add r0, r9, #8 ; 0x8 + 9514: e59d1438 ldr r1, [sp, #1080] + 9518: ebf5e84b bl 0xffd8364c + 951c: ebf5ea97 bl 0xffd83f80 + 9520: 08010492 stmeqda r1, {r1, r4, r7, sl} + 9524: e1a01003 mov r1, r3 + 9528: e2937000 adds r7, r3, #0 ; 0x0 + 952c: ebf5ea93 bl 0xffd83f80 + 9530: 08010494 stmeqda r1, {r2, r4, r7, sl} + 9534: e3b05000 movs r5, #0 ; 0x0 + 9538: ebf5ea90 bl 0xffd83f80 + 953c: 08010496 stmeqda r1, {r1, r2, r4, r7, sl} + 9540: e1a01007 mov r1, r7 + 9544: e2976000 adds r6, r7, #0 ; 0x0 + 9548: ebf5ea8c bl 0xffd83f80 + 954c: 08010498 stmeqda r1, {r3, r4, r7, sl} + 9550: e3b04000 movs r4, #0 ; 0x0 + 9554: ebf5ea89 bl 0xffd83f80 + 9558: 0801049a stmeqda r1, {r1, r3, r4, r7, sl} + 955c: e3a00f2f mov r0, #188 ; 0xbc + 9560: e3800b41 orr r0, r0, #66560 ; 0x10400 + 9564: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9568: ebf5e8ea bl 0xffd83918 + 956c: 0801049e stmeqda r1, {r1, r2, r3, r4, r7, sl} + 9570: e1a08000 mov r8, r0 + 9574: e28cc016 add ip, ip, #22 ; 0x16 + 9578: ebf5ea80 bl 0xffd83f80 + 957c: 0801049c stmeqda r1, {r2, r3, r4, r7, sl} + 9580: e1a01006 mov r1, r6 + 9584: e0963004 adds r3, r6, r4 + 9588: ebf5ea7c bl 0xffd83f80 + 958c: 0801049e stmeqda r1, {r1, r2, r3, r4, r7, sl} + 9590: e2830000 add r0, r3, #0 ; 0x0 + 9594: ebf5e888 bl 0xffd837bc + 9598: 080104a2 stmeqda r1, {r1, r5, r7, sl} + 959c: e1a03000 mov r3, r0 + 95a0: ebf5ea76 bl 0xffd83f80 + 95a4: 080104a0 stmeqda r1, {r5, r7, sl} + 95a8: e1a01005 mov r1, r5 + 95ac: e0953003 adds r3, r5, r3 + 95b0: ebf5ea72 bl 0xffd83f80 + 95b4: 080104a2 stmeqda r1, {r1, r5, r7, sl} + 95b8: e1b03c03 movs r3, r3, lsl #24 + 95bc: ebf5ea6f bl 0xffd83f80 + 95c0: 080104a4 stmeqda r1, {r2, r5, r7, sl} + 95c4: e1b05c23 movs r5, r3, lsr #24 + 95c8: ebf5ea6c bl 0xffd83f80 + 95cc: 080104a6 stmeqda r1, {r1, r2, r5, r7, sl} + 95d0: e1a01004 mov r1, r4 + 95d4: e2944001 adds r4, r4, #1 ; 0x1 + 95d8: ebf5ea68 bl 0xffd83f80 + 95dc: 080104a8 stmeqda r1, {r3, r5, r7, sl} + 95e0: e1540008 cmp r4, r8 + 95e4: ebf5ea65 bl 0xffd83f80 + 95e8: 080104aa stmeqda r1, {r1, r3, r5, r7, sl} + 95ec: e28cc01a add ip, ip, #26 ; 0x1a + 95f0: 8a000004 bhi 0x9608 + 95f4: e1a00fac mov r0, ip, lsr #31 + 95f8: e08ff100 add pc, pc, r0, lsl #2 + 95fc: 0801049c stmeqda r1, {r2, r3, r4, r7, sl} + 9600: ebf5e653 bl 0xffd82f54 + 9604: eaffffdb b 0x9578 + 9608: ebf5ea5c bl 0xffd83f80 + 960c: 080104ac stmeqda r1, {r2, r3, r5, r7, sl} + 9610: e2870009 add r0, r7, #9 ; 0x9 + 9614: ebf5e868 bl 0xffd837bc + 9618: 080104b0 stmeqda r1, {r4, r5, r7, sl} + 961c: e1a03000 mov r3, r0 + 9620: ebf5ea56 bl 0xffd83f80 + 9624: 080104ae stmeqda r1, {r1, r2, r3, r5, r7, sl} + 9628: e1a01005 mov r1, r5 + 962c: e0553003 subs r3, r5, r3 + 9630: ebf5ea52 bl 0xffd83f80 + 9634: 080104b0 stmeqda r1, {r4, r5, r7, sl} + 9638: e1b03c03 movs r3, r3, lsl #24 + 963c: ebf5ea4f bl 0xffd83f80 + 9640: 080104b2 stmeqda r1, {r1, r4, r5, r7, sl} + 9644: e1b05c23 movs r5, r3, lsr #24 + 9648: ebf5ea4c bl 0xffd83f80 + 964c: 080104b4 stmeqda r1, {r2, r4, r5, r7, sl} + 9650: e1a01005 mov r1, r5 + 9654: e2953000 adds r3, r5, #0 ; 0x0 + 9658: ebf5ea48 bl 0xffd83f80 + 965c: 080104b6 stmeqda r1, {r1, r2, r4, r5, r7, sl} + 9660: e59d9434 ldr r9, [sp, #1076] + 9664: e3c99003 bic r9, r9, #3 ; 0x3 + 9668: e2890008 add r0, r9, #8 ; 0x8 + 966c: e58d0434 str r0, [sp, #1076] + 9670: e2890000 add r0, r9, #0 ; 0x0 + 9674: ebf5e8a7 bl 0xffd83918 + 9678: 080104ba stmeqda r1, {r1, r3, r4, r5, r7, sl} + 967c: e1a07000 mov r7, r0 + 9680: e2890004 add r0, r9, #4 ; 0x4 + 9684: ebf5e8a3 bl 0xffd83918 + 9688: 080104ba stmeqda r1, {r1, r3, r4, r5, r7, sl} + 968c: e1a08000 mov r8, r0 + 9690: ebf5ea3a bl 0xffd83f80 + 9694: 080104b8 stmeqda r1, {r3, r4, r5, r7, sl} + 9698: e59d9434 ldr r9, [sp, #1076] + 969c: e3c99003 bic r9, r9, #3 ; 0x3 + 96a0: e2890004 add r0, r9, #4 ; 0x4 + 96a4: e58d0434 str r0, [sp, #1076] + 96a8: e2890000 add r0, r9, #0 ; 0x0 + 96ac: ebf5e899 bl 0xffd83918 + 96b0: 080104bc stmeqda r1, {r2, r3, r4, r5, r7, sl} + 96b4: e1a04000 mov r4, r0 + 96b8: ebf5ea30 bl 0xffd83f80 + 96bc: 080104ba stmeqda r1, {r1, r3, r4, r5, r7, sl} + 96c0: e1a00004 mov r0, r4 + 96c4: e28cc01d add ip, ip, #29 ; 0x1d + 96c8: eaf5e680 b 0xffd830d0 + 96cc: 0801034a stmeqda r1, {r1, r3, r6, r8, r9} + 96d0: 00000000 andeq r0, r0, r0 + 96d4: ebf5ea29 bl 0xffd83f80 + 96d8: 0801034a stmeqda r1, {r1, r3, r6, r8, r9} + 96dc: e2830008 add r0, r3, #8 ; 0x8 + 96e0: ebf5e88c bl 0xffd83918 + 96e4: 0801034e stmeqda r1, {r1, r2, r3, r6, r8, r9} + 96e8: e1a03000 mov r3, r0 + 96ec: ebf5ea23 bl 0xffd83f80 + 96f0: 0801034c stmeqda r1, {r2, r3, r6, r8, r9} + 96f4: e59d1434 ldr r1, [sp, #1076] + 96f8: e1a03001 mov r3, r1 + 96fc: ebf5ea1f bl 0xffd83f80 + 9700: 0801034e stmeqda r1, {r1, r2, r3, r6, r8, r9} + 9704: ebf5ea1d bl 0xffd83f80 + 9708: 08010350 stmeqda r1, {r4, r6, r8, r9} + 970c: e3a00053 mov r0, #83 ; 0x53 + 9710: e3800c03 orr r0, r0, #768 ; 0x300 + 9714: e3800801 orr r0, r0, #65536 ; 0x10000 + 9718: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 971c: e58d0438 str r0, [sp, #1080] + 9720: e28cc00e add ip, ip, #14 ; 0xe + 9724: e1a00fac mov r0, ip, lsr #31 + 9728: e08ff100 add pc, pc, r0, lsl #2 + 972c: 08010490 stmeqda r1, {r4, r7, sl} + 9730: ebf5e607 bl 0xffd82f54 + 9734: eaffff69 b 0x94e0 + 9738: 08010352 stmeqda r1, {r1, r4, r6, r8, r9} + 973c: 00000000 andeq r0, r0, r0 + 9740: ebf5ea0e bl 0xffd83f80 + 9744: 08010352 stmeqda r1, {r1, r4, r6, r8, r9} + 9748: e59d1434 ldr r1, [sp, #1076] + 974c: e1a04001 mov r4, r1 + 9750: ebf5ea0a bl 0xffd83f80 + 9754: 08010354 stmeqda r1, {r2, r4, r6, r8, r9} + 9758: e2840009 add r0, r4, #9 ; 0x9 + 975c: e1a01003 mov r1, r3 + 9760: ebf5e75a bl 0xffd834d0 + 9764: 08010356 stmeqda r1, {r1, r2, r4, r6, r8, r9} + 9768: ebf5ea04 bl 0xffd83f80 + 976c: 08010356 stmeqda r1, {r1, r2, r4, r6, r8, r9} + 9770: e3b07000 movs r7, #0 ; 0x0 + 9774: ebf5ea01 bl 0xffd83f80 + 9778: 08010358 stmeqda r1, {r3, r4, r6, r8, r9} + 977c: e3b000f4 movs r0, #244 ; 0xf4 + 9780: e58d0418 str r0, [sp, #1048] + 9784: ebf5e9fd bl 0xffd83f80 + 9788: 0801035a stmeqda r1, {r1, r3, r4, r6, r8, r9} + 978c: e59de418 ldr lr, [sp, #1048] + 9790: e1b0010e movs r0, lr, lsl #2 + 9794: e58d0418 str r0, [sp, #1048] + 9798: ebf5e9f8 bl 0xffd83f80 + 979c: 0801035c stmeqda r1, {r2, r3, r4, r6, r8, r9} + 97a0: e28cc013 add ip, ip, #19 ; 0x13 + 97a4: e1a00fac mov r0, ip, lsr #31 + 97a8: e08ff100 add pc, pc, r0, lsl #2 + 97ac: 08010376 stmeqda r1, {r1, r2, r4, r5, r6, r8, r9} + 97b0: ebf5e5e7 bl 0xffd82f54 + 97b4: ea000001 b 0x97c0 + 97b8: 08010376 stmeqda r1, {r1, r2, r4, r5, r6, r8, r9} + 97bc: 00000000 andeq r0, r0, r0 + 97c0: ebf5e9ee bl 0xffd83f80 + 97c4: 08010376 stmeqda r1, {r1, r2, r4, r5, r6, r8, r9} + 97c8: e3570009 cmp r7, #9 ; 0x9 + 97cc: ebf5e9eb bl 0xffd83f80 + 97d0: 08010378 stmeqda r1, {r3, r4, r5, r6, r8, r9} + 97d4: e28cc006 add ip, ip, #6 ; 0x6 + 97d8: 9a000004 bls 0x97f0 + 97dc: e1a00fac mov r0, ip, lsr #31 + 97e0: e08ff100 add pc, pc, r0, lsl #2 + 97e4: 08010392 stmeqda r1, {r1, r4, r7, r8, r9} + 97e8: ebf5e5d9 bl 0xffd82f54 + 97ec: ea00001e b 0x986c + 97f0: ebf5e9e2 bl 0xffd83f80 + 97f4: 0801037a stmeqda r1, {r1, r3, r4, r5, r6, r8, r9} + 97f8: e59d1434 ldr r1, [sp, #1076] + 97fc: e1a03001 mov r3, r1 + 9800: ebf5e9de bl 0xffd83f80 + 9804: 0801037c stmeqda r1, {r2, r3, r4, r5, r6, r8, r9} + 9808: e1a01008 mov r1, r8 + 980c: e2984000 adds r4, r8, #0 ; 0x0 + 9810: ebf5e9da bl 0xffd83f80 + 9814: 0801037e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8, r9} + 9818: e59d1418 ldr r1, [sp, #1048] + 981c: e59d1418 ldr r1, [sp, #1048] + 9820: e2915000 adds r5, r1, #0 ; 0x0 + 9824: ebf5e9d5 bl 0xffd83f80 + 9828: 08010380 stmeqda r1, {r7, r8, r9} + 982c: e28cc00c add ip, ip, #12 ; 0xc + 9830: ebf5e9d2 bl 0xffd83f80 + 9834: 08010382 stmeqda r1, {r1, r7, r8, r9} + 9838: e3a00085 mov r0, #133 ; 0x85 + 983c: e3800c03 orr r0, r0, #768 ; 0x300 + 9840: e3800801 orr r0, r0, #65536 ; 0x10000 + 9844: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9848: e58d0438 str r0, [sp, #1080] + 984c: e28cc003 add ip, ip, #3 ; 0x3 + 9850: e1a00fac mov r0, ip, lsr #31 + 9854: e08ff100 add pc, pc, r0, lsl #2 + 9858: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 985c: ebf5e5bc bl 0xffd82f54 + 9860: eafffa13 b 0x80b4 + 9864: 08010392 stmeqda r1, {r1, r4, r7, r8, r9} + 9868: 00000000 andeq r0, r0, r0 + 986c: ebf5e9c3 bl 0xffd83f80 + 9870: 08010392 stmeqda r1, {r1, r4, r7, r8, r9} + 9874: e3b060f4 movs r6, #244 ; 0xf4 + 9878: ebf5e9c0 bl 0xffd83f80 + 987c: 08010394 stmeqda r1, {r2, r4, r7, r8, r9} + 9880: e1b06106 movs r6, r6, lsl #2 + 9884: ebf5e9bd bl 0xffd83f80 + 9888: 08010396 stmeqda r1, {r1, r2, r4, r7, r8, r9} + 988c: e59d0434 ldr r0, [sp, #1076] + 9890: e0800006 add r0, r0, r6 + 9894: e58d0434 str r0, [sp, #1076] + 9898: ebf5e9b8 bl 0xffd83f80 + 989c: 08010398 stmeqda r1, {r3, r4, r7, r8, r9} + 98a0: e59d9434 ldr r9, [sp, #1076] + 98a4: e3c99003 bic r9, r9, #3 ; 0x3 + 98a8: e289000c add r0, r9, #12 ; 0xc + 98ac: e58d0434 str r0, [sp, #1076] + 98b0: e2890000 add r0, r9, #0 ; 0x0 + 98b4: ebf5e817 bl 0xffd83918 + 98b8: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 98bc: e1a07000 mov r7, r0 + 98c0: e2890004 add r0, r9, #4 ; 0x4 + 98c4: ebf5e813 bl 0xffd83918 + 98c8: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 98cc: e1a08000 mov r8, r0 + 98d0: e2890008 add r0, r9, #8 ; 0x8 + 98d4: ebf5e80f bl 0xffd83918 + 98d8: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 98dc: e58d0418 str r0, [sp, #1048] + 98e0: ebf5e9a6 bl 0xffd83f80 + 98e4: 0801039a stmeqda r1, {r1, r3, r4, r7, r8, r9} + 98e8: e59d9434 ldr r9, [sp, #1076] + 98ec: e3c99003 bic r9, r9, #3 ; 0x3 + 98f0: e2890004 add r0, r9, #4 ; 0x4 + 98f4: e58d0434 str r0, [sp, #1076] + 98f8: e2890000 add r0, r9, #0 ; 0x0 + 98fc: ebf5e805 bl 0xffd83918 + 9900: 0801039e stmeqda r1, {r1, r2, r3, r4, r7, r8, r9} + 9904: e1a03000 mov r3, r0 + 9908: ebf5e99c bl 0xffd83f80 + 990c: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 9910: e1a00003 mov r0, r3 + 9914: e28cc016 add ip, ip, #22 ; 0x16 + 9918: eaf5e5ec b 0xffd830d0 + 991c: 08010384 stmeqda r1, {r2, r7, r8, r9} + 9920: 00000000 andeq r0, r0, r0 + 9924: ebf5e995 bl 0xffd83f80 + 9928: 08010384 stmeqda r1, {r2, r7, r8, r9} + 992c: e59d1434 ldr r1, [sp, #1076] + 9930: e1a03001 mov r3, r1 + 9934: ebf5e991 bl 0xffd83f80 + 9938: 08010386 stmeqda r1, {r1, r2, r7, r8, r9} + 993c: e1a01008 mov r1, r8 + 9940: e2984000 adds r4, r8, #0 ; 0x0 + 9944: ebf5e98d bl 0xffd83f80 + 9948: 08010388 stmeqda r1, {r3, r7, r8, r9} + 994c: e59d1418 ldr r1, [sp, #1048] + 9950: e59d1418 ldr r1, [sp, #1048] + 9954: e2915000 adds r5, r1, #0 ; 0x0 + 9958: ebf5e988 bl 0xffd83f80 + 995c: 0801038a stmeqda r1, {r1, r3, r7, r8, r9} + 9960: ebf5e986 bl 0xffd83f80 + 9964: 0801038c stmeqda r1, {r2, r3, r7, r8, r9} + 9968: e3a0008f mov r0, #143 ; 0x8f + 996c: e3800c03 orr r0, r0, #768 ; 0x300 + 9970: e3800801 orr r0, r0, #65536 ; 0x10000 + 9974: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9978: e58d0438 str r0, [sp, #1080] + 997c: e28cc00f add ip, ip, #15 ; 0xf + 9980: e1a00fac mov r0, ip, lsr #31 + 9984: e08ff100 add pc, pc, r0, lsl #2 + 9988: 080c3100 stmeqda ip, {r8, ip, sp} + 998c: ebf5e570 bl 0xffd82f54 + 9990: eafffb08 b 0x85b8 + 9994: 0801038e stmeqda r1, {r1, r2, r3, r7, r8, r9} + 9998: 00000000 andeq r0, r0, r0 + 999c: ebf5e977 bl 0xffd83f80 + 99a0: 0801038e stmeqda r1, {r1, r2, r3, r7, r8, r9} + 99a4: e3530000 cmp r3, #0 ; 0x0 + 99a8: ebf5e974 bl 0xffd83f80 + 99ac: 08010390 stmeqda r1, {r4, r7, r8, r9} + 99b0: e28cc006 add ip, ip, #6 ; 0x6 + 99b4: 0a000004 beq 0x99cc + 99b8: e1a00fac mov r0, ip, lsr #31 + 99bc: e08ff100 add pc, pc, r0, lsl #2 + 99c0: 08010374 stmeqda r1, {r2, r4, r5, r6, r8, r9} + 99c4: ebf5e562 bl 0xffd82f54 + 99c8: ea00002d b 0x9a84 + 99cc: ebf5e96b bl 0xffd83f80 + 99d0: 08010392 stmeqda r1, {r1, r4, r7, r8, r9} + 99d4: e3b060f4 movs r6, #244 ; 0xf4 + 99d8: ebf5e968 bl 0xffd83f80 + 99dc: 08010394 stmeqda r1, {r2, r4, r7, r8, r9} + 99e0: e1b06106 movs r6, r6, lsl #2 + 99e4: ebf5e965 bl 0xffd83f80 + 99e8: 08010396 stmeqda r1, {r1, r2, r4, r7, r8, r9} + 99ec: e59d0434 ldr r0, [sp, #1076] + 99f0: e0800006 add r0, r0, r6 + 99f4: e58d0434 str r0, [sp, #1076] + 99f8: ebf5e960 bl 0xffd83f80 + 99fc: 08010398 stmeqda r1, {r3, r4, r7, r8, r9} + 9a00: e59d9434 ldr r9, [sp, #1076] + 9a04: e3c99003 bic r9, r9, #3 ; 0x3 + 9a08: e289000c add r0, r9, #12 ; 0xc + 9a0c: e58d0434 str r0, [sp, #1076] + 9a10: e2890000 add r0, r9, #0 ; 0x0 + 9a14: ebf5e7bf bl 0xffd83918 + 9a18: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 9a1c: e1a07000 mov r7, r0 + 9a20: e2890004 add r0, r9, #4 ; 0x4 + 9a24: ebf5e7bb bl 0xffd83918 + 9a28: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 9a2c: e1a08000 mov r8, r0 + 9a30: e2890008 add r0, r9, #8 ; 0x8 + 9a34: ebf5e7b7 bl 0xffd83918 + 9a38: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 9a3c: e58d0418 str r0, [sp, #1048] + 9a40: ebf5e94e bl 0xffd83f80 + 9a44: 0801039a stmeqda r1, {r1, r3, r4, r7, r8, r9} + 9a48: e59d9434 ldr r9, [sp, #1076] + 9a4c: e3c99003 bic r9, r9, #3 ; 0x3 + 9a50: e2890004 add r0, r9, #4 ; 0x4 + 9a54: e58d0434 str r0, [sp, #1076] + 9a58: e2890000 add r0, r9, #0 ; 0x0 + 9a5c: ebf5e7ad bl 0xffd83918 + 9a60: 0801039e stmeqda r1, {r1, r2, r3, r4, r7, r8, r9} + 9a64: e1a03000 mov r3, r0 + 9a68: ebf5e944 bl 0xffd83f80 + 9a6c: 0801039c stmeqda r1, {r2, r3, r4, r7, r8, r9} + 9a70: e1a00003 mov r0, r3 + 9a74: e28cc016 add ip, ip, #22 ; 0x16 + 9a78: eaf5e594 b 0xffd830d0 + 9a7c: 08010374 stmeqda r1, {r2, r4, r5, r6, r8, r9} + 9a80: 00000000 andeq r0, r0, r0 + 9a84: ebf5e93d bl 0xffd83f80 + 9a88: 08010374 stmeqda r1, {r2, r4, r5, r6, r8, r9} + 9a8c: e1a01007 mov r1, r7 + 9a90: e2977001 adds r7, r7, #1 ; 0x1 + 9a94: ebf5e939 bl 0xffd83f80 + 9a98: 08010376 stmeqda r1, {r1, r2, r4, r5, r6, r8, r9} + 9a9c: e3570009 cmp r7, #9 ; 0x9 + 9aa0: ebf5e936 bl 0xffd83f80 + 9aa4: 08010378 stmeqda r1, {r3, r4, r5, r6, r8, r9} + 9aa8: e28cc009 add ip, ip, #9 ; 0x9 + 9aac: 9a000004 bls 0x9ac4 + 9ab0: e1a00fac mov r0, ip, lsr #31 + 9ab4: e08ff100 add pc, pc, r0, lsl #2 + 9ab8: 08010392 stmeqda r1, {r1, r4, r7, r8, r9} + 9abc: ebf5e524 bl 0xffd82f54 + 9ac0: eaffff69 b 0x986c + 9ac4: ebf5e92d bl 0xffd83f80 + 9ac8: 0801037a stmeqda r1, {r1, r3, r4, r5, r6, r8, r9} + 9acc: e59d1434 ldr r1, [sp, #1076] + 9ad0: e1a03001 mov r3, r1 + 9ad4: ebf5e929 bl 0xffd83f80 + 9ad8: 0801037c stmeqda r1, {r2, r3, r4, r5, r6, r8, r9} + 9adc: e1a01008 mov r1, r8 + 9ae0: e2984000 adds r4, r8, #0 ; 0x0 + 9ae4: ebf5e925 bl 0xffd83f80 + 9ae8: 0801037e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8, r9} + 9aec: e59d1418 ldr r1, [sp, #1048] + 9af0: e59d1418 ldr r1, [sp, #1048] + 9af4: e2915000 adds r5, r1, #0 ; 0x0 + 9af8: ebf5e920 bl 0xffd83f80 + 9afc: 08010380 stmeqda r1, {r7, r8, r9} + 9b00: ebf5e91e bl 0xffd83f80 + 9b04: 08010382 stmeqda r1, {r1, r7, r8, r9} + 9b08: e3a00085 mov r0, #133 ; 0x85 + 9b0c: e3800c03 orr r0, r0, #768 ; 0x300 + 9b10: e3800801 orr r0, r0, #65536 ; 0x10000 + 9b14: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9b18: e58d0438 str r0, [sp, #1080] + 9b1c: e28cc00f add ip, ip, #15 ; 0xf + 9b20: e1a00fac mov r0, ip, lsr #31 + 9b24: e08ff100 add pc, pc, r0, lsl #2 + 9b28: 080c3060 stmeqda ip, {r5, r6, ip, sp} + 9b2c: ebf5e508 bl 0xffd82f54 + 9b30: eafff95f b 0x80b4 + 9b34: 080101e2 stmeqda r1, {r1, r5, r6, r7, r8} + 9b38: 00000000 andeq r0, r0, r0 + 9b3c: ebf5e90f bl 0xffd83f80 + 9b40: 080101e2 stmeqda r1, {r1, r5, r6, r7, r8} + 9b44: e1a01007 mov r1, r7 + 9b48: e2977001 adds r7, r7, #1 ; 0x1 + 9b4c: ebf5e90b bl 0xffd83f80 + 9b50: 080101e4 stmeqda r1, {r2, r5, r6, r7, r8} + 9b54: e3570007 cmp r7, #7 ; 0x7 + 9b58: ebf5e908 bl 0xffd83f80 + 9b5c: 080101e6 stmeqda r1, {r1, r2, r5, r6, r7, r8} + 9b60: e28cc009 add ip, ip, #9 ; 0x9 + 9b64: 8a000004 bhi 0x9b7c + 9b68: e1a00fac mov r0, ip, lsr #31 + 9b6c: e08ff100 add pc, pc, r0, lsl #2 + 9b70: 080101da stmeqda r1, {r1, r3, r4, r6, r7, r8} + 9b74: ebf5e4f6 bl 0xffd82f54 + 9b78: ea00001f b 0x9bfc + 9b7c: ebf5e8ff bl 0xffd83f80 + 9b80: 080101e8 stmeqda r1, {r3, r5, r6, r7, r8} + 9b84: e59d0434 ldr r0, [sp, #1076] + 9b88: e2800f01 add r0, r0, #4 ; 0x4 + 9b8c: e58d0434 str r0, [sp, #1076] + 9b90: ebf5e8fa bl 0xffd83f80 + 9b94: 080101ea stmeqda r1, {r1, r3, r5, r6, r7, r8} + 9b98: e59d9434 ldr r9, [sp, #1076] + 9b9c: e3c99003 bic r9, r9, #3 ; 0x3 + 9ba0: e2890004 add r0, r9, #4 ; 0x4 + 9ba4: e58d0434 str r0, [sp, #1076] + 9ba8: e2890000 add r0, r9, #0 ; 0x0 + 9bac: ebf5e759 bl 0xffd83918 + 9bb0: 080101ee stmeqda r1, {r1, r2, r3, r5, r6, r7, r8} + 9bb4: e1a07000 mov r7, r0 + 9bb8: ebf5e8f0 bl 0xffd83f80 + 9bbc: 080101ec stmeqda r1, {r2, r3, r5, r6, r7, r8} + 9bc0: e59d9434 ldr r9, [sp, #1076] + 9bc4: e3c99003 bic r9, r9, #3 ; 0x3 + 9bc8: e2890004 add r0, r9, #4 ; 0x4 + 9bcc: e58d0434 str r0, [sp, #1076] + 9bd0: e2890000 add r0, r9, #0 ; 0x0 + 9bd4: ebf5e74f bl 0xffd83918 + 9bd8: 080101f0 stmeqda r1, {r4, r5, r6, r7, r8} + 9bdc: e1a03000 mov r3, r0 + 9be0: ebf5e8e6 bl 0xffd83f80 + 9be4: 080101ee stmeqda r1, {r1, r2, r3, r5, r6, r7, r8} + 9be8: e1a00003 mov r0, r3 + 9bec: e28cc00e add ip, ip, #14 ; 0xe + 9bf0: eaf5e536 b 0xffd830d0 + 9bf4: 080101da stmeqda r1, {r1, r3, r4, r6, r7, r8} + 9bf8: 00000000 andeq r0, r0, r0 + 9bfc: ebf5e8df bl 0xffd83f80 + 9c00: 080101da stmeqda r1, {r1, r3, r4, r6, r7, r8} + 9c04: e1b03c07 movs r3, r7, lsl #24 + 9c08: ebf5e8dc bl 0xffd83f80 + 9c0c: 080101dc stmeqda r1, {r2, r3, r4, r6, r7, r8} + 9c10: e1b03c23 movs r3, r3, lsr #24 + 9c14: ebf5e8d9 bl 0xffd83f80 + 9c18: 080101de stmeqda r1, {r1, r2, r3, r4, r6, r7, r8} + 9c1c: ebf5e8d7 bl 0xffd83f80 + 9c20: 080101e0 stmeqda r1, {r5, r6, r7, r8} + 9c24: e3a000e3 mov r0, #227 ; 0xe3 + 9c28: e3800c01 orr r0, r0, #256 ; 0x100 + 9c2c: e3800801 orr r0, r0, #65536 ; 0x10000 + 9c30: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9c34: e58d0438 str r0, [sp, #1080] + 9c38: e28cc00c add ip, ip, #12 ; 0xc + 9c3c: e1a00fac mov r0, ip, lsr #31 + 9c40: e08ff100 add pc, pc, r0, lsl #2 + 9c44: 08010320 stmeqda r1, {r5, r8, r9} + 9c48: ebf5e4c1 bl 0xffd82f54 + 9c4c: eafffd8e b 0x928c + 9c50: 080c3190 stmeqda ip, {r4, r7, r8, ip, sp} + 9c54: 00000000 andeq r0, r0, r0 + 9c58: ebf5e8c8 bl 0xffd83f80 + 9c5c: 080c3190 stmeqda ip, {r4, r7, r8, ip, sp} + 9c60: e1a01006 mov r1, r6 + 9c64: e2966002 adds r6, r6, #2 ; 0x2 + 9c68: ebf5e8c4 bl 0xffd83f80 + 9c6c: 080c3192 stmeqda ip, {r1, r4, r7, r8, ip, sp} + 9c70: e2850000 add r0, r5, #0 ; 0x0 + 9c74: e1a01006 mov r1, r6 + 9c78: ebf5e653 bl 0xffd835cc + 9c7c: 080c3194 stmeqda ip, {r2, r4, r7, r8, ip, sp} + 9c80: ebf5e8be bl 0xffd83f80 + 9c84: 080c3194 stmeqda ip, {r2, r4, r7, r8, ip, sp} + 9c88: e1a01004 mov r1, r4 + 9c8c: e2944002 adds r4, r4, #2 ; 0x2 + 9c90: ebf5e8ba bl 0xffd83f80 + 9c94: 080c3196 stmeqda ip, {r1, r2, r4, r7, r8, ip, sp} + 9c98: e2830000 add r0, r3, #0 ; 0x0 + 9c9c: e1a01004 mov r1, r4 + 9ca0: ebf5e649 bl 0xffd835cc + 9ca4: 080c3198 stmeqda ip, {r3, r4, r7, r8, ip, sp} + 9ca8: ebf5e8b4 bl 0xffd83f80 + 9cac: 080c3198 stmeqda ip, {r3, r4, r7, r8, ip, sp} + 9cb0: e59d141c ldr r1, [sp, #1052] + 9cb4: e59d141c ldr r1, [sp, #1052] + 9cb8: e2914000 adds r4, r1, #0 ; 0x0 + 9cbc: ebf5e8af bl 0xffd83f80 + 9cc0: 080c319a stmeqda ip, {r1, r3, r4, r7, r8, ip, sp} + 9cc4: e1a01004 mov r1, r4 + 9cc8: e294400c adds r4, r4, #12 ; 0xc + 9ccc: ebf5e8ab bl 0xffd83f80 + 9cd0: 080c319c stmeqda ip, {r2, r3, r4, r7, r8, ip, sp} + 9cd4: e59d141c ldr r1, [sp, #1052] + 9cd8: e59d141c ldr r1, [sp, #1052] + 9cdc: e2913000 adds r3, r1, #0 ; 0x0 + 9ce0: ebf5e8a6 bl 0xffd83f80 + 9ce4: 080c319e stmeqda ip, {r1, r2, r3, r4, r7, r8, ip, sp} + 9ce8: e1a01003 mov r1, r3 + 9cec: e293300c adds r3, r3, #12 ; 0xc + 9cf0: ebf5e8a2 bl 0xffd83f80 + 9cf4: 080c31a0 stmeqda ip, {r5, r7, r8, ip, sp} + 9cf8: e59d141c ldr r1, [sp, #1052] + 9cfc: e59d141c ldr r1, [sp, #1052] + 9d00: e2914000 adds r4, r1, #0 ; 0x0 + 9d04: ebf5e89d bl 0xffd83f80 + 9d08: 080c31a2 stmeqda ip, {r1, r5, r7, r8, ip, sp} + 9d0c: e1a01004 mov r1, r4 + 9d10: e294400c adds r4, r4, #12 ; 0xc + 9d14: ebf5e899 bl 0xffd83f80 + 9d18: 080c31a4 stmeqda ip, {r2, r5, r7, r8, ip, sp} + 9d1c: e2840000 add r0, r4, #0 ; 0x0 + 9d20: ebf5e6d0 bl 0xffd83868 + 9d24: 080c31a8 stmeqda ip, {r3, r5, r7, r8, ip, sp} + 9d28: e1a05000 mov r5, r0 + 9d2c: ebf5e893 bl 0xffd83f80 + 9d30: 080c31a6 stmeqda ip, {r1, r2, r5, r7, r8, ip, sp} + 9d34: e1a01005 mov r1, r5 + 9d38: e2554001 subs r4, r5, #1 ; 0x1 + 9d3c: ebf5e88f bl 0xffd83f80 + 9d40: 080c31a8 stmeqda ip, {r3, r5, r7, r8, ip, sp} + 9d44: e1a01004 mov r1, r4 + 9d48: e2945000 adds r5, r4, #0 ; 0x0 + 9d4c: ebf5e88b bl 0xffd83f80 + 9d50: 080c31aa stmeqda ip, {r1, r3, r5, r7, r8, ip, sp} + 9d54: e2830000 add r0, r3, #0 ; 0x0 + 9d58: e1a01005 mov r1, r5 + 9d5c: ebf5e5fa bl 0xffd8354c + 9d60: 080c31ac stmeqda ip, {r2, r3, r5, r7, r8, ip, sp} + 9d64: e28cc02f add ip, ip, #47 ; 0x2f + 9d68: ebf5e884 bl 0xffd83f80 + 9d6c: 080c31ac stmeqda ip, {r2, r3, r5, r7, r8, ip, sp} + 9d70: e28cc003 add ip, ip, #3 ; 0x3 + 9d74: e1a00fac mov r0, ip, lsr #31 + 9d78: e08ff100 add pc, pc, r0, lsl #2 + 9d7c: 080c315e stmeqda ip, {r1, r2, r3, r4, r6, r8, ip, sp} + 9d80: ebf5e473 bl 0xffd82f54 + 9d84: eafffbb0 b 0x8c4c + 9d88: 08000468 stmeqda r0, {r3, r5, r6, sl} + 9d8c: 00000000 andeq r0, r0, r0 + 9d90: ebf5e87a bl 0xffd83f80 + 9d94: 08000468 stmeqda r0, {r3, r5, r6, sl} + 9d98: e59d9434 ldr r9, [sp, #1076] + 9d9c: e3c99003 bic r9, r9, #3 ; 0x3 + 9da0: e2499008 sub r9, r9, #8 ; 0x8 + 9da4: e58d9434 str r9, [sp, #1076] + 9da8: e2890000 add r0, r9, #0 ; 0x0 + 9dac: e1a01007 mov r1, r7 + 9db0: ebf5e625 bl 0xffd8364c + 9db4: e2890004 add r0, r9, #4 ; 0x4 + 9db8: e59d1438 ldr r1, [sp, #1080] + 9dbc: ebf5e622 bl 0xffd8364c + 9dc0: ebf5e86e bl 0xffd83f80 + 9dc4: 0800046a stmeqda r0, {r1, r3, r5, r6, sl} + 9dc8: ebf5e86c bl 0xffd83f80 + 9dcc: 0800046c stmeqda r0, {r2, r3, r5, r6, sl} + 9dd0: e3a0006f mov r0, #111 ; 0x6f + 9dd4: e3800b01 orr r0, r0, #1024 ; 0x400 + 9dd8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9ddc: e58d0438 str r0, [sp, #1080] + 9de0: e28cc00a add ip, ip, #10 ; 0xa + 9de4: e1a00fac mov r0, ip, lsr #31 + 9de8: e08ff100 add pc, pc, r0, lsl #2 + 9dec: 080bfd7c stmeqda fp, {r2, r3, r4, r5, r6, r8, sl, fp, ip, sp, lr, pc} + 9df0: ebf5e457 bl 0xffd82f54 + 9df4: ea000001 b 0x9e00 + 9df8: 080bfd7c stmeqda fp, {r2, r3, r4, r5, r6, r8, sl, fp, ip, sp, lr, pc} + 9dfc: 00000000 andeq r0, r0, r0 + 9e00: ebf5e85e bl 0xffd83f80 + 9e04: 080bfd7c stmeqda fp, {r2, r3, r4, r5, r6, r8, sl, fp, ip, sp, lr, pc} + 9e08: e3a00f06 mov r0, #24 ; 0x18 + 9e0c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 9e10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9e14: ebf5e6bf bl 0xffd83918 + 9e18: 080bfd80 stmeqda fp, {r7, r8, sl, fp, ip, sp, lr, pc} + 9e1c: e1a03000 mov r3, r0 + 9e20: ebf5e856 bl 0xffd83f80 + 9e24: 080bfd7e stmeqda fp, {r1, r2, r3, r4, r5, r6, r8, sl, fp, ip, sp, lr, pc} + 9e28: e2830000 add r0, r3, #0 ; 0x0 + 9e2c: ebf5e6b9 bl 0xffd83918 + 9e30: 080bfd82 stmeqda fp, {r1, r7, r8, sl, fp, ip, sp, lr, pc} + 9e34: e1a03000 mov r3, r0 + 9e38: ebf5e850 bl 0xffd83f80 + 9e3c: 080bfd80 stmeqda fp, {r7, r8, sl, fp, ip, sp, lr, pc} + 9e40: e3a00f07 mov r0, #28 ; 0x1c + 9e44: e3800703 orr r0, r0, #786432 ; 0xc0000 + 9e48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9e4c: ebf5e6b1 bl 0xffd83918 + 9e50: 080bfd84 stmeqda fp, {r2, r7, r8, sl, fp, ip, sp, lr, pc} + 9e54: e1a05000 mov r5, r0 + 9e58: ebf5e848 bl 0xffd83f80 + 9e5c: 080bfd82 stmeqda fp, {r1, r7, r8, sl, fp, ip, sp, lr, pc} + 9e60: e2830000 add r0, r3, #0 ; 0x0 + 9e64: ebf5e6ab bl 0xffd83918 + 9e68: 080bfd86 stmeqda fp, {r1, r2, r7, r8, sl, fp, ip, sp, lr, pc} + 9e6c: e1a06000 mov r6, r0 + 9e70: ebf5e842 bl 0xffd83f80 + 9e74: 080bfd84 stmeqda fp, {r2, r7, r8, sl, fp, ip, sp, lr, pc} + 9e78: e1a01006 mov r1, r6 + 9e7c: e0566005 subs r6, r6, r5 + 9e80: ebf5e83e bl 0xffd83f80 + 9e84: 080bfd86 stmeqda fp, {r1, r2, r7, r8, sl, fp, ip, sp, lr, pc} + 9e88: e3560001 cmp r6, #1 ; 0x1 + 9e8c: ebf5e83b bl 0xffd83f80 + 9e90: 080bfd88 stmeqda fp, {r3, r7, r8, sl, fp, ip, sp, lr, pc} + 9e94: e28cc01d add ip, ip, #29 ; 0x1d + 9e98: 9a000004 bls 0x9eb0 + 9e9c: e1a00fac mov r0, ip, lsr #31 + 9ea0: e08ff100 add pc, pc, r0, lsl #2 + 9ea4: 080bfda8 stmeqda fp, {r3, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9ea8: ebf5e429 bl 0xffd82f54 + 9eac: ea000057 b 0xa010 + 9eb0: ebf5e832 bl 0xffd83f80 + 9eb4: 080bfd8a stmeqda fp, {r1, r3, r7, r8, sl, fp, ip, sp, lr, pc} + 9eb8: e2830004 add r0, r3, #4 ; 0x4 + 9ebc: ebf5e63e bl 0xffd837bc + 9ec0: 080bfd8e stmeqda fp, {r1, r2, r3, r7, r8, sl, fp, ip, sp, lr, pc} + 9ec4: e1a04000 mov r4, r0 + 9ec8: ebf5e82c bl 0xffd83f80 + 9ecc: 080bfd8c stmeqda fp, {r2, r3, r7, r8, sl, fp, ip, sp, lr, pc} + 9ed0: e1a01004 mov r1, r4 + 9ed4: e2544001 subs r4, r4, #1 ; 0x1 + 9ed8: ebf5e828 bl 0xffd83f80 + 9edc: 080bfd8e stmeqda fp, {r1, r2, r3, r7, r8, sl, fp, ip, sp, lr, pc} + 9ee0: e2830004 add r0, r3, #4 ; 0x4 + 9ee4: e1a01004 mov r1, r4 + 9ee8: ebf5e578 bl 0xffd834d0 + 9eec: 080bfd90 stmeqda fp, {r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9ef0: ebf5e822 bl 0xffd83f80 + 9ef4: 080bfd90 stmeqda fp, {r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9ef8: e28cc00f add ip, ip, #15 ; 0xf + 9efc: da000004 ble 0x9f14 + 9f00: e1a00fac mov r0, ip, lsr #31 + 9f04: e08ff100 add pc, pc, r0, lsl #2 + 9f08: 080bfda8 stmeqda fp, {r3, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9f0c: ebf5e410 bl 0xffd82f54 + 9f10: ea00003e b 0xa010 + 9f14: ebf5e819 bl 0xffd83f80 + 9f18: 080bfd92 stmeqda fp, {r1, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f1c: e283000b add r0, r3, #11 ; 0xb + 9f20: ebf5e625 bl 0xffd837bc + 9f24: 080bfd96 stmeqda fp, {r1, r2, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f28: e1a04000 mov r4, r0 + 9f2c: ebf5e813 bl 0xffd83f80 + 9f30: 080bfd94 stmeqda fp, {r2, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f34: e2830004 add r0, r3, #4 ; 0x4 + 9f38: e1a01004 mov r1, r4 + 9f3c: ebf5e563 bl 0xffd834d0 + 9f40: 080bfd96 stmeqda fp, {r1, r2, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f44: ebf5e80d bl 0xffd83f80 + 9f48: 080bfd96 stmeqda fp, {r1, r2, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f4c: e3b03000 movs r3, #0 ; 0x0 + 9f50: ebf5e80a bl 0xffd83f80 + 9f54: 080bfd98 stmeqda fp, {r3, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f58: e3b040b6 movs r4, #182 ; 0xb6 + 9f5c: ebf5e807 bl 0xffd83f80 + 9f60: 080bfd9a stmeqda fp, {r1, r3, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f64: e1b04404 movs r4, r4, lsl #8 + 9f68: ebf5e804 bl 0xffd83f80 + 9f6c: 080bfd9c stmeqda fp, {r2, r3, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f70: e3a00f6b mov r0, #428 ; 0x1ac + 9f74: e3800bff orr r0, r0, #261120 ; 0x3fc00 + 9f78: e3800702 orr r0, r0, #524288 ; 0x80000 + 9f7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9f80: ebf5e664 bl 0xffd83918 + 9f84: 080bfda0 stmeqda fp, {r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9f88: e1a05000 mov r5, r0 + 9f8c: ebf5e7fb bl 0xffd83f80 + 9f90: 080bfd9e stmeqda fp, {r1, r2, r3, r4, r7, r8, sl, fp, ip, sp, lr, pc} + 9f94: e3a00edb mov r0, #3504 ; 0xdb0 + 9f98: e3800abf orr r0, r0, #782336 ; 0xbf000 + 9f9c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 9fa0: ebf5e65c bl 0xffd83918 + 9fa4: 080bfda2 stmeqda fp, {r1, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fa8: e1a06000 mov r6, r0 + 9fac: ebf5e7f3 bl 0xffd83f80 + 9fb0: 080bfda0 stmeqda fp, {r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fb4: e2850000 add r0, r5, #0 ; 0x0 + 9fb8: e1a01003 mov r1, r3 + 9fbc: ebf5e562 bl 0xffd8354c + 9fc0: 080bfda2 stmeqda fp, {r1, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fc4: ebf5e7ed bl 0xffd83f80 + 9fc8: 080bfda2 stmeqda fp, {r1, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fcc: e2860000 add r0, r6, #0 ; 0x0 + 9fd0: e1a01003 mov r1, r3 + 9fd4: ebf5e55c bl 0xffd8354c + 9fd8: 080bfda4 stmeqda fp, {r2, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fdc: ebf5e7e7 bl 0xffd83f80 + 9fe0: 080bfda4 stmeqda fp, {r2, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9fe4: e2850000 add r0, r5, #0 ; 0x0 + 9fe8: e1a01004 mov r1, r4 + 9fec: ebf5e556 bl 0xffd8354c + 9ff0: 080bfda6 stmeqda fp, {r1, r2, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9ff4: ebf5e7e1 bl 0xffd83f80 + 9ff8: 080bfda6 stmeqda fp, {r1, r2, r5, r7, r8, sl, fp, ip, sp, lr, pc} + 9ffc: e2860000 add r0, r6, #0 ; 0x0 + a000: e1a01004 mov r1, r4 + a004: ebf5e550 bl 0xffd8354c + a008: 080bfda8 stmeqda fp, {r3, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a00c: e28cc02c add ip, ip, #44 ; 0x2c + a010: ebf5e7da bl 0xffd83f80 + a014: 080bfda8 stmeqda fp, {r3, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a018: e59d0438 ldr r0, [sp, #1080] + a01c: e28cc003 add ip, ip, #3 ; 0x3 + a020: eaf5e42a b 0xffd830d0 + a024: 0800046e stmeqda r0, {r1, r2, r3, r5, r6, sl} + a028: 00000000 andeq r0, r0, r0 + a02c: ebf5e7d3 bl 0xffd83f80 + a030: 0800046e stmeqda r0, {r1, r2, r3, r5, r6, sl} + a034: e3a00f3a mov r0, #232 ; 0xe8 + a038: e3800b01 orr r0, r0, #1024 ; 0x400 + a03c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a040: ebf5e634 bl 0xffd83918 + a044: 08000472 stmeqda r0, {r1, r4, r5, r6, sl} + a048: e1a06000 mov r6, r0 + a04c: ebf5e7cb bl 0xffd83f80 + a050: 08000470 stmeqda r0, {r4, r5, r6, sl} + a054: e2860000 add r0, r6, #0 ; 0x0 + a058: ebf5e62e bl 0xffd83918 + a05c: 08000474 stmeqda r0, {r2, r4, r5, r6, sl} + a060: e1a03000 mov r3, r0 + a064: ebf5e7c5 bl 0xffd83f80 + a068: 08000472 stmeqda r0, {r1, r4, r5, r6, sl} + a06c: e3b07080 movs r7, #128 ; 0x80 + a070: ebf5e7c2 bl 0xffd83f80 + a074: 08000474 stmeqda r0, {r2, r4, r5, r6, sl} + a078: e1b07a87 movs r7, r7, lsl #21 + a07c: ebf5e7bf bl 0xffd83f80 + a080: 08000476 stmeqda r0, {r1, r2, r4, r5, r6, sl} + a084: e1a01003 mov r1, r3 + a088: e0133007 ands r3, r3, r7 + a08c: ebf5e7bb bl 0xffd83f80 + a090: 08000478 stmeqda r0, {r3, r4, r5, r6, sl} + a094: e3530000 cmp r3, #0 ; 0x0 + a098: ebf5e7b8 bl 0xffd83f80 + a09c: 0800047a stmeqda r0, {r1, r3, r4, r5, r6, sl} + a0a0: e28cc019 add ip, ip, #25 ; 0x19 + a0a4: 1a000004 bne 0xa0bc + a0a8: e1a00fac mov r0, ip, lsr #31 + a0ac: e08ff100 add pc, pc, r0, lsl #2 + a0b0: 08000490 stmeqda r0, {r4, r7, sl} + a0b4: ebf5e3a6 bl 0xffd82f54 + a0b8: ea000037 b 0xa19c + a0bc: ebf5e7af bl 0xffd83f80 + a0c0: 0800047c stmeqda r0, {r2, r3, r4, r5, r6, sl} + a0c4: e3a00f3b mov r0, #236 ; 0xec + a0c8: e3800b01 orr r0, r0, #1024 ; 0x400 + a0cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a0d0: ebf5e610 bl 0xffd83918 + a0d4: 08000480 stmeqda r0, {r7, sl} + a0d8: e1a04000 mov r4, r0 + a0dc: ebf5e7a7 bl 0xffd83f80 + a0e0: 0800047e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl} + a0e4: e284000a add r0, r4, #10 ; 0xa + a0e8: ebf5e5de bl 0xffd83868 + a0ec: 08000482 stmeqda r0, {r1, r7, sl} + a0f0: e1a03000 mov r3, r0 + a0f4: ebf5e7a1 bl 0xffd83f80 + a0f8: 08000480 stmeqda r0, {r7, sl} + a0fc: e1b03883 movs r3, r3, lsl #17 + a100: ebf5e79e bl 0xffd83f80 + a104: 08000482 stmeqda r0, {r1, r7, sl} + a108: e1b038a3 movs r3, r3, lsr #17 + a10c: ebf5e79b bl 0xffd83f80 + a110: 08000484 stmeqda r0, {r2, r7, sl} + a114: e284000a add r0, r4, #10 ; 0xa + a118: e1a01003 mov r1, r3 + a11c: ebf5e50a bl 0xffd8354c + a120: 08000486 stmeqda r0, {r1, r2, r7, sl} + a124: ebf5e795 bl 0xffd83f80 + a128: 08000486 stmeqda r0, {r1, r2, r7, sl} + a12c: e284000a add r0, r4, #10 ; 0xa + a130: ebf5e5cc bl 0xffd83868 + a134: 0800048a stmeqda r0, {r1, r3, r7, sl} + a138: e1a03000 mov r3, r0 + a13c: ebf5e78f bl 0xffd83f80 + a140: 08000488 stmeqda r0, {r3, r7, sl} + a144: e2860000 add r0, r6, #0 ; 0x0 + a148: ebf5e5f2 bl 0xffd83918 + a14c: 0800048c stmeqda r0, {r2, r3, r7, sl} + a150: e1a03000 mov r3, r0 + a154: ebf5e789 bl 0xffd83f80 + a158: 0800048a stmeqda r0, {r1, r3, r7, sl} + a15c: e3a00e4f mov r0, #1264 ; 0x4f0 + a160: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a164: ebf5e5eb bl 0xffd83918 + a168: 0800048e stmeqda r0, {r1, r2, r3, r7, sl} + a16c: e1a04000 mov r4, r0 + a170: ebf5e782 bl 0xffd83f80 + a174: 0800048c stmeqda r0, {r2, r3, r7, sl} + a178: e1a01003 mov r1, r3 + a17c: e0133004 ands r3, r3, r4 + a180: ebf5e77e bl 0xffd83f80 + a184: 0800048e stmeqda r0, {r1, r2, r3, r7, sl} + a188: e2860000 add r0, r6, #0 ; 0x0 + a18c: e1a01003 mov r1, r3 + a190: ebf5e50d bl 0xffd835cc + a194: 08000490 stmeqda r0, {r4, r7, sl} + a198: e28cc02a add ip, ip, #42 ; 0x2a + a19c: ebf5e777 bl 0xffd83f80 + a1a0: 08000490 stmeqda r0, {r4, r7, sl} + a1a4: e2860004 add r0, r6, #4 ; 0x4 + a1a8: ebf5e5da bl 0xffd83918 + a1ac: 08000494 stmeqda r0, {r2, r4, r7, sl} + a1b0: e1a03000 mov r3, r0 + a1b4: ebf5e771 bl 0xffd83f80 + a1b8: 08000492 stmeqda r0, {r1, r4, r7, sl} + a1bc: e1a01003 mov r1, r3 + a1c0: e2933001 adds r3, r3, #1 ; 0x1 + a1c4: ebf5e76d bl 0xffd83f80 + a1c8: 08000494 stmeqda r0, {r2, r4, r7, sl} + a1cc: e2860004 add r0, r6, #4 ; 0x4 + a1d0: e1a01003 mov r1, r3 + a1d4: ebf5e4fc bl 0xffd835cc + a1d8: 08000496 stmeqda r0, {r1, r2, r4, r7, sl} + a1dc: ebf5e767 bl 0xffd83f80 + a1e0: 08000496 stmeqda r0, {r1, r2, r4, r7, sl} + a1e4: e2860012 add r0, r6, #18 ; 0x12 + a1e8: ebf5e59e bl 0xffd83868 + a1ec: 0800049a stmeqda r0, {r1, r3, r4, r7, sl} + a1f0: e1a03000 mov r3, r0 + a1f4: ebf5e761 bl 0xffd83f80 + a1f8: 08000498 stmeqda r0, {r3, r4, r7, sl} + a1fc: e1a01003 mov r1, r3 + a200: e2933001 adds r3, r3, #1 ; 0x1 + a204: ebf5e75d bl 0xffd83f80 + a208: 0800049a stmeqda r0, {r1, r3, r4, r7, sl} + a20c: e2860012 add r0, r6, #18 ; 0x12 + a210: ebf5e594 bl 0xffd83868 + a214: 0800049e stmeqda r0, {r1, r2, r3, r4, r7, sl} + a218: e1a04000 mov r4, r0 + a21c: ebf5e757 bl 0xffd83f80 + a220: 0800049c stmeqda r0, {r2, r3, r4, r7, sl} + a224: e2860012 add r0, r6, #18 ; 0x12 + a228: e1a01003 mov r1, r3 + a22c: ebf5e4c6 bl 0xffd8354c + a230: 0800049e stmeqda r0, {r1, r2, r3, r4, r7, sl} + a234: ebf5e751 bl 0xffd83f80 + a238: 0800049e stmeqda r0, {r1, r2, r3, r4, r7, sl} + a23c: e2860012 add r0, r6, #18 ; 0x12 + a240: ebf5e588 bl 0xffd83868 + a244: 080004a2 stmeqda r0, {r1, r5, r7, sl} + a248: e1a03000 mov r3, r0 + a24c: ebf5e74b bl 0xffd83f80 + a250: 080004a0 stmeqda r0, {r5, r7, sl} + a254: e3530000 cmp r3, #0 ; 0x0 + a258: ebf5e748 bl 0xffd83f80 + a25c: 080004a2 stmeqda r0, {r1, r5, r7, sl} + a260: e28cc028 add ip, ip, #40 ; 0x28 + a264: 0a000004 beq 0xa27c + a268: e1a00fac mov r0, ip, lsr #31 + a26c: e08ff100 add pc, pc, r0, lsl #2 + a270: 080004ae stmeqda r0, {r1, r2, r3, r5, r7, sl} + a274: ebf5e336 bl 0xffd82f54 + a278: ea000019 b 0xa2e4 + a27c: ebf5e73f bl 0xffd83f80 + a280: 080004a4 stmeqda r0, {r2, r5, r7, sl} + a284: e286000c add r0, r6, #12 ; 0xc + a288: ebf5e576 bl 0xffd83868 + a28c: 080004a8 stmeqda r0, {r3, r5, r7, sl} + a290: e1a03000 mov r3, r0 + a294: ebf5e739 bl 0xffd83f80 + a298: 080004a6 stmeqda r0, {r1, r2, r5, r7, sl} + a29c: e286000e add r0, r6, #14 ; 0xe + a2a0: e1a01003 mov r1, r3 + a2a4: ebf5e4a8 bl 0xffd8354c + a2a8: 080004a8 stmeqda r0, {r3, r5, r7, sl} + a2ac: ebf5e733 bl 0xffd83f80 + a2b0: 080004a8 stmeqda r0, {r3, r5, r7, sl} + a2b4: e3b04001 movs r4, #1 ; 0x1 + a2b8: ebf5e730 bl 0xffd83f80 + a2bc: 080004aa stmeqda r0, {r1, r3, r5, r7, sl} + a2c0: e1a01003 mov r1, r3 + a2c4: e0333004 eors r3, r3, r4 + a2c8: ebf5e72c bl 0xffd83f80 + a2cc: 080004ac stmeqda r0, {r2, r3, r5, r7, sl} + a2d0: e286000c add r0, r6, #12 ; 0xc + a2d4: e1a01003 mov r1, r3 + a2d8: ebf5e49b bl 0xffd8354c + a2dc: 080004ae stmeqda r0, {r1, r2, r3, r5, r7, sl} + a2e0: e28cc013 add ip, ip, #19 ; 0x13 + a2e4: ebf5e725 bl 0xffd83f80 + a2e8: 080004ae stmeqda r0, {r1, r2, r3, r5, r7, sl} + a2ec: e2860000 add r0, r6, #0 ; 0x0 + a2f0: ebf5e588 bl 0xffd83918 + a2f4: 080004b2 stmeqda r0, {r1, r4, r5, r7, sl} + a2f8: e1a03000 mov r3, r0 + a2fc: ebf5e71f bl 0xffd83f80 + a300: 080004b0 stmeqda r0, {r4, r5, r7, sl} + a304: e3b04080 movs r4, #128 ; 0x80 + a308: ebf5e71c bl 0xffd83f80 + a30c: 080004b2 stmeqda r0, {r1, r4, r5, r7, sl} + a310: e1b04b04 movs r4, r4, lsl #22 + a314: ebf5e719 bl 0xffd83f80 + a318: 080004b4 stmeqda r0, {r2, r4, r5, r7, sl} + a31c: e1a01003 mov r1, r3 + a320: e0133004 ands r3, r3, r4 + a324: ebf5e715 bl 0xffd83f80 + a328: 080004b6 stmeqda r0, {r1, r2, r4, r5, r7, sl} + a32c: e3530000 cmp r3, #0 ; 0x0 + a330: ebf5e712 bl 0xffd83f80 + a334: 080004b8 stmeqda r0, {r3, r4, r5, r7, sl} + a338: e28cc014 add ip, ip, #20 ; 0x14 + a33c: 1a000004 bne 0xa354 + a340: e1a00fac mov r0, ip, lsr #31 + a344: e08ff100 add pc, pc, r0, lsl #2 + a348: 080004d4 stmeqda r0, {r2, r4, r6, r7, sl} + a34c: ebf5e300 bl 0xffd82f54 + a350: ea00004e b 0xa490 + a354: ebf5e709 bl 0xffd83f80 + a358: 080004ba stmeqda r0, {r1, r3, r4, r5, r7, sl} + a35c: e3a00f3d mov r0, #244 ; 0xf4 + a360: e3800b01 orr r0, r0, #1024 ; 0x400 + a364: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a368: ebf5e56a bl 0xffd83918 + a36c: 080004be stmeqda r0, {r1, r2, r3, r4, r5, r7, sl} + a370: e1a03000 mov r3, r0 + a374: ebf5e701 bl 0xffd83f80 + a378: 080004bc stmeqda r0, {r2, r3, r4, r5, r7, sl} + a37c: e1a01006 mov r1, r6 + a380: e0965003 adds r5, r6, r3 + a384: ebf5e6fd bl 0xffd83f80 + a388: 080004be stmeqda r0, {r1, r2, r3, r4, r5, r7, sl} + a38c: e3a00f3b mov r0, #236 ; 0xec + a390: e3800b01 orr r0, r0, #1024 ; 0x400 + a394: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a398: ebf5e55e bl 0xffd83918 + a39c: 080004c2 stmeqda r0, {r1, r6, r7, sl} + a3a0: e1a04000 mov r4, r0 + a3a4: ebf5e6f5 bl 0xffd83f80 + a3a8: 080004c0 stmeqda r0, {r6, r7, sl} + a3ac: e2850000 add r0, r5, #0 ; 0x0 + a3b0: ebf5e558 bl 0xffd83918 + a3b4: 080004c4 stmeqda r0, {r2, r6, r7, sl} + a3b8: e1a03000 mov r3, r0 + a3bc: ebf5e6ef bl 0xffd83f80 + a3c0: 080004c2 stmeqda r0, {r1, r6, r7, sl} + a3c4: e2840000 add r0, r4, #0 ; 0x0 + a3c8: e1a01003 mov r1, r3 + a3cc: ebf5e47e bl 0xffd835cc + a3d0: 080004c4 stmeqda r0, {r2, r6, r7, sl} + a3d4: ebf5e6e9 bl 0xffd83f80 + a3d8: 080004c4 stmeqda r0, {r2, r6, r7, sl} + a3dc: e2850004 add r0, r5, #4 ; 0x4 + a3e0: ebf5e54c bl 0xffd83918 + a3e4: 080004c8 stmeqda r0, {r3, r6, r7, sl} + a3e8: e1a03000 mov r3, r0 + a3ec: ebf5e6e3 bl 0xffd83f80 + a3f0: 080004c6 stmeqda r0, {r1, r2, r6, r7, sl} + a3f4: e2840004 add r0, r4, #4 ; 0x4 + a3f8: e1a01003 mov r1, r3 + a3fc: ebf5e472 bl 0xffd835cc + a400: 080004c8 stmeqda r0, {r3, r6, r7, sl} + a404: ebf5e6dd bl 0xffd83f80 + a408: 080004c8 stmeqda r0, {r3, r6, r7, sl} + a40c: e2850008 add r0, r5, #8 ; 0x8 + a410: ebf5e540 bl 0xffd83918 + a414: 080004cc stmeqda r0, {r2, r3, r6, r7, sl} + a418: e1a03000 mov r3, r0 + a41c: ebf5e6d7 bl 0xffd83f80 + a420: 080004ca stmeqda r0, {r1, r3, r6, r7, sl} + a424: e2840008 add r0, r4, #8 ; 0x8 + a428: e1a01003 mov r1, r3 + a42c: ebf5e466 bl 0xffd835cc + a430: 080004cc stmeqda r0, {r2, r3, r6, r7, sl} + a434: ebf5e6d1 bl 0xffd83f80 + a438: 080004cc stmeqda r0, {r2, r3, r6, r7, sl} + a43c: e2840008 add r0, r4, #8 ; 0x8 + a440: ebf5e534 bl 0xffd83918 + a444: 080004d0 stmeqda r0, {r4, r6, r7, sl} + a448: e1a03000 mov r3, r0 + a44c: ebf5e6cb bl 0xffd83f80 + a450: 080004ce stmeqda r0, {r1, r2, r3, r6, r7, sl} + a454: e2860000 add r0, r6, #0 ; 0x0 + a458: ebf5e52e bl 0xffd83918 + a45c: 080004d2 stmeqda r0, {r1, r4, r6, r7, sl} + a460: e1a03000 mov r3, r0 + a464: ebf5e6c5 bl 0xffd83f80 + a468: 080004d0 stmeqda r0, {r4, r6, r7, sl} + a46c: e1a01003 mov r1, r3 + a470: e1933007 orrs r3, r3, r7 + a474: ebf5e6c1 bl 0xffd83f80 + a478: 080004d2 stmeqda r0, {r1, r4, r6, r7, sl} + a47c: e2860000 add r0, r6, #0 ; 0x0 + a480: e1a01003 mov r1, r3 + a484: ebf5e450 bl 0xffd835cc + a488: 080004d4 stmeqda r0, {r2, r4, r6, r7, sl} + a48c: e28cc039 add ip, ip, #57 ; 0x39 + a490: ebf5e6ba bl 0xffd83f80 + a494: 080004d4 stmeqda r0, {r2, r4, r6, r7, sl} + a498: e3a00f3e mov r0, #248 ; 0xf8 + a49c: e3800b01 orr r0, r0, #1024 ; 0x400 + a4a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a4a4: ebf5e51b bl 0xffd83918 + a4a8: 080004d8 stmeqda r0, {r3, r4, r6, r7, sl} + a4ac: e1a03000 mov r3, r0 + a4b0: ebf5e6b2 bl 0xffd83f80 + a4b4: 080004d6 stmeqda r0, {r1, r2, r4, r6, r7, sl} + a4b8: e3b04000 movs r4, #0 ; 0x0 + a4bc: ebf5e6af bl 0xffd83f80 + a4c0: 080004d8 stmeqda r0, {r3, r4, r6, r7, sl} + a4c4: e2830000 add r0, r3, #0 ; 0x0 + a4c8: e1a01004 mov r1, r4 + a4cc: ebf5e43e bl 0xffd835cc + a4d0: 080004da stmeqda r0, {r1, r3, r4, r6, r7, sl} + a4d4: ebf5e6a9 bl 0xffd83f80 + a4d8: 080004da stmeqda r0, {r1, r3, r4, r6, r7, sl} + a4dc: e3a00f3f mov r0, #252 ; 0xfc + a4e0: e3800b01 orr r0, r0, #1024 ; 0x400 + a4e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a4e8: ebf5e50a bl 0xffd83918 + a4ec: 080004de stmeqda r0, {r1, r2, r3, r4, r6, r7, sl} + a4f0: e1a04000 mov r4, r0 + a4f4: ebf5e6a1 bl 0xffd83f80 + a4f8: 080004dc stmeqda r0, {r2, r3, r4, r6, r7, sl} + a4fc: e2830000 add r0, r3, #0 ; 0x0 + a500: e1a01004 mov r1, r4 + a504: ebf5e430 bl 0xffd835cc + a508: 080004de stmeqda r0, {r1, r2, r3, r4, r6, r7, sl} + a50c: ebf5e69b bl 0xffd83f80 + a510: 080004de stmeqda r0, {r1, r2, r3, r4, r6, r7, sl} + a514: ebf5e699 bl 0xffd83f80 + a518: 080004e0 stmeqda r0, {r5, r6, r7, sl} + a51c: e3a000e3 mov r0, #227 ; 0xe3 + a520: e3800b01 orr r0, r0, #1024 ; 0x400 + a524: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a528: e58d0438 str r0, [sp, #1080] + a52c: e28cc01b add ip, ip, #27 ; 0x1b + a530: e1a00fac mov r0, ip, lsr #31 + a534: e08ff100 add pc, pc, r0, lsl #2 + a538: 080beab0 stmeqda fp, {r4, r5, r7, r9, fp, sp, lr, pc} + a53c: ebf5e284 bl 0xffd82f54 + a540: ea000001 b 0xa54c + a544: 080beab0 stmeqda fp, {r4, r5, r7, r9, fp, sp, lr, pc} + a548: 00000000 andeq r0, r0, r0 + a54c: ebf5e68b bl 0xffd83f80 + a550: 080beab0 stmeqda fp, {r4, r5, r7, r9, fp, sp, lr, pc} + a554: e59d9434 ldr r9, [sp, #1076] + a558: e3c99003 bic r9, r9, #3 ; 0x3 + a55c: e2499004 sub r9, r9, #4 ; 0x4 + a560: e58d9434 str r9, [sp, #1076] + a564: e2890000 add r0, r9, #0 ; 0x0 + a568: e59d1438 ldr r1, [sp, #1080] + a56c: ebf5e436 bl 0xffd8364c + a570: ebf5e682 bl 0xffd83f80 + a574: 080beab2 stmeqda fp, {r1, r4, r5, r7, r9, fp, sp, lr, pc} + a578: e3a00fb3 mov r0, #716 ; 0x2cc + a57c: e3800bfa orr r0, r0, #256000 ; 0x3e800 + a580: e3800702 orr r0, r0, #524288 ; 0x80000 + a584: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a588: ebf5e4e2 bl 0xffd83918 + a58c: 080beab6 stmeqda fp, {r1, r2, r4, r5, r7, r9, fp, sp, lr, pc} + a590: e1a03000 mov r3, r0 + a594: ebf5e679 bl 0xffd83f80 + a598: 080beab4 stmeqda fp, {r2, r4, r5, r7, r9, fp, sp, lr, pc} + a59c: e3b0409b movs r4, #155 ; 0x9b + a5a0: ebf5e676 bl 0xffd83f80 + a5a4: 080beab6 stmeqda fp, {r1, r2, r4, r5, r7, r9, fp, sp, lr, pc} + a5a8: e1b04284 movs r4, r4, lsl #5 + a5ac: ebf5e673 bl 0xffd83f80 + a5b0: 080beab8 stmeqda fp, {r3, r4, r5, r7, r9, fp, sp, lr, pc} + a5b4: e1a01003 mov r1, r3 + a5b8: e0936004 adds r6, r3, r4 + a5bc: ebf5e66f bl 0xffd83f80 + a5c0: 080beaba stmeqda fp, {r1, r3, r4, r5, r7, r9, fp, sp, lr, pc} + a5c4: e2860000 add r0, r6, #0 ; 0x0 + a5c8: ebf5e47b bl 0xffd837bc + a5cc: 080beabe stmeqda fp, {r1, r2, r3, r4, r5, r7, r9, fp, sp, lr, pc} + a5d0: e1a03000 mov r3, r0 + a5d4: ebf5e669 bl 0xffd83f80 + a5d8: 080beabc stmeqda fp, {r2, r3, r4, r5, r7, r9, fp, sp, lr, pc} + a5dc: e3530000 cmp r3, #0 ; 0x0 + a5e0: ebf5e666 bl 0xffd83f80 + a5e4: 080beabe stmeqda fp, {r1, r2, r3, r4, r5, r7, r9, fp, sp, lr, pc} + a5e8: e28cc01c add ip, ip, #28 ; 0x1c + a5ec: 0a000004 beq 0xa604 + a5f0: e1a00fac mov r0, ip, lsr #31 + a5f4: e08ff100 add pc, pc, r0, lsl #2 + a5f8: 080bead4 stmeqda fp, {r2, r4, r6, r7, r9, fp, sp, lr, pc} + a5fc: ebf5e254 bl 0xffd82f54 + a600: ea000024 b 0xa698 + a604: ebf5e65d bl 0xffd83f80 + a608: 080beac0 stmeqda fp, {r6, r7, r9, fp, sp, lr, pc} + a60c: e3a00ead mov r0, #2768 ; 0xad0 + a610: e3800abe orr r0, r0, #778240 ; 0xbe000 + a614: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a618: ebf5e4be bl 0xffd83918 + a61c: 080beac4 stmeqda fp, {r2, r6, r7, r9, fp, sp, lr, pc} + a620: e1a05000 mov r5, r0 + a624: ebf5e655 bl 0xffd83f80 + a628: 080beac2 stmeqda fp, {r1, r6, r7, r9, fp, sp, lr, pc} + a62c: e2850000 add r0, r5, #0 ; 0x0 + a630: ebf5e461 bl 0xffd837bc + a634: 080beac6 stmeqda fp, {r1, r2, r6, r7, r9, fp, sp, lr, pc} + a638: e1a04000 mov r4, r0 + a63c: ebf5e64f bl 0xffd83f80 + a640: 080beac4 stmeqda fp, {r2, r6, r7, r9, fp, sp, lr, pc} + a644: e3b030df movs r3, #223 ; 0xdf + a648: ebf5e64c bl 0xffd83f80 + a64c: 080beac6 stmeqda fp, {r1, r2, r6, r7, r9, fp, sp, lr, pc} + a650: e1a01003 mov r1, r3 + a654: e0133004 ands r3, r3, r4 + a658: ebf5e648 bl 0xffd83f80 + a65c: 080beac8 stmeqda fp, {r3, r6, r7, r9, fp, sp, lr, pc} + a660: e2850000 add r0, r5, #0 ; 0x0 + a664: e1a01003 mov r1, r3 + a668: ebf5e398 bl 0xffd834d0 + a66c: 080beaca stmeqda fp, {r1, r3, r6, r7, r9, fp, sp, lr, pc} + a670: ebf5e642 bl 0xffd83f80 + a674: 080beaca stmeqda fp, {r1, r3, r6, r7, r9, fp, sp, lr, pc} + a678: e28cc017 add ip, ip, #23 ; 0x17 + a67c: e1a00fac mov r0, ip, lsr #31 + a680: e08ff100 add pc, pc, r0, lsl #2 + a684: 080beaec stmeqda fp, {r2, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a688: ebf5e231 bl 0xffd82f54 + a68c: ea000050 b 0xa7d4 + a690: 080bead4 stmeqda fp, {r2, r4, r6, r7, r9, fp, sp, lr, pc} + a694: 00000000 andeq r0, r0, r0 + a698: ebf5e638 bl 0xffd83f80 + a69c: 080bead4 stmeqda fp, {r2, r4, r6, r7, r9, fp, sp, lr, pc} + a6a0: e3a00eaf mov r0, #2800 ; 0xaf0 + a6a4: e3800abe orr r0, r0, #778240 ; 0xbe000 + a6a8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a6ac: ebf5e499 bl 0xffd83918 + a6b0: 080bead8 stmeqda fp, {r3, r4, r6, r7, r9, fp, sp, lr, pc} + a6b4: e1a05000 mov r5, r0 + a6b8: ebf5e630 bl 0xffd83f80 + a6bc: 080bead6 stmeqda fp, {r1, r2, r4, r6, r7, r9, fp, sp, lr, pc} + a6c0: e2850000 add r0, r5, #0 ; 0x0 + a6c4: ebf5e43c bl 0xffd837bc + a6c8: 080beada stmeqda fp, {r1, r3, r4, r6, r7, r9, fp, sp, lr, pc} + a6cc: e1a03000 mov r3, r0 + a6d0: ebf5e62a bl 0xffd83f80 + a6d4: 080bead8 stmeqda fp, {r3, r4, r6, r7, r9, fp, sp, lr, pc} + a6d8: e3b04020 movs r4, #32 ; 0x20 + a6dc: ebf5e627 bl 0xffd83f80 + a6e0: 080beada stmeqda fp, {r1, r3, r4, r6, r7, r9, fp, sp, lr, pc} + a6e4: e1a01003 mov r1, r3 + a6e8: e1933004 orrs r3, r3, r4 + a6ec: ebf5e623 bl 0xffd83f80 + a6f0: 080beadc stmeqda fp, {r2, r3, r4, r6, r7, r9, fp, sp, lr, pc} + a6f4: e2850000 add r0, r5, #0 ; 0x0 + a6f8: e1a01003 mov r1, r3 + a6fc: ebf5e373 bl 0xffd834d0 + a700: 080beade stmeqda fp, {r1, r2, r3, r4, r6, r7, r9, fp, sp, lr, pc} + a704: ebf5e61d bl 0xffd83f80 + a708: 080beade stmeqda fp, {r1, r2, r3, r4, r6, r7, r9, fp, sp, lr, pc} + a70c: e3a00fbd mov r0, #756 ; 0x2f4 + a710: e3800bfa orr r0, r0, #256000 ; 0x3e800 + a714: e3800702 orr r0, r0, #524288 ; 0x80000 + a718: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a71c: ebf5e47d bl 0xffd83918 + a720: 080beae2 stmeqda fp, {r1, r5, r6, r7, r9, fp, sp, lr, pc} + a724: e1a04000 mov r4, r0 + a728: ebf5e614 bl 0xffd83f80 + a72c: 080beae0 stmeqda fp, {r5, r6, r7, r9, fp, sp, lr, pc} + a730: e2860000 add r0, r6, #0 ; 0x0 + a734: ebf5e420 bl 0xffd837bc + a738: 080beae4 stmeqda fp, {r2, r5, r6, r7, r9, fp, sp, lr, pc} + a73c: e1a03000 mov r3, r0 + a740: ebf5e60e bl 0xffd83f80 + a744: 080beae2 stmeqda fp, {r1, r5, r6, r7, r9, fp, sp, lr, pc} + a748: e1b03103 movs r3, r3, lsl #2 + a74c: ebf5e60b bl 0xffd83f80 + a750: 080beae4 stmeqda fp, {r2, r5, r6, r7, r9, fp, sp, lr, pc} + a754: e1a01003 mov r1, r3 + a758: e0933004 adds r3, r3, r4 + a75c: ebf5e607 bl 0xffd83f80 + a760: 080beae6 stmeqda fp, {r1, r2, r5, r6, r7, r9, fp, sp, lr, pc} + a764: e2830000 add r0, r3, #0 ; 0x0 + a768: ebf5e46a bl 0xffd83918 + a76c: 080beaea stmeqda fp, {r1, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a770: e1a03000 mov r3, r0 + a774: ebf5e601 bl 0xffd83f80 + a778: 080beae8 stmeqda fp, {r3, r5, r6, r7, r9, fp, sp, lr, pc} + a77c: ebf5e5ff bl 0xffd83f80 + a780: 080beaea stmeqda fp, {r1, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a784: e3a000ed mov r0, #237 ; 0xed + a788: e3800cea orr r0, r0, #59904 ; 0xea00 + a78c: e380080b orr r0, r0, #720896 ; 0xb0000 + a790: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a794: e58d0438 str r0, [sp, #1080] + a798: e28cc02f add ip, ip, #47 ; 0x2f + a79c: e1a00fac mov r0, ip, lsr #31 + a7a0: e08ff100 add pc, pc, r0, lsl #2 + a7a4: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + a7a8: ebf5e1e9 bl 0xffd82f54 + a7ac: ea000001 b 0xa7b8 + a7b0: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + a7b4: 00000000 andeq r0, r0, r0 + a7b8: ebf5e5f0 bl 0xffd83f80 + a7bc: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + a7c0: e1a00003 mov r0, r3 + a7c4: e28cc003 add ip, ip, #3 ; 0x3 + a7c8: eaf5e240 b 0xffd830d0 + a7cc: 080beaec stmeqda fp, {r2, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a7d0: 00000000 andeq r0, r0, r0 + a7d4: ebf5e5e9 bl 0xffd83f80 + a7d8: 080beaec stmeqda fp, {r2, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a7dc: e59d9434 ldr r9, [sp, #1076] + a7e0: e3c99003 bic r9, r9, #3 ; 0x3 + a7e4: e2890004 add r0, r9, #4 ; 0x4 + a7e8: e58d0434 str r0, [sp, #1076] + a7ec: e2890000 add r0, r9, #0 ; 0x0 + a7f0: ebf5e448 bl 0xffd83918 + a7f4: 080beaf0 stmeqda fp, {r4, r5, r6, r7, r9, fp, sp, lr, pc} + a7f8: e1a03000 mov r3, r0 + a7fc: ebf5e5df bl 0xffd83f80 + a800: 080beaee stmeqda fp, {r1, r2, r3, r5, r6, r7, r9, fp, sp, lr, pc} + a804: e1a00003 mov r0, r3 + a808: e28cc007 add ip, ip, #7 ; 0x7 + a80c: eaf5e22f b 0xffd830d0 + a810: 080004e2 stmeqda r0, {r1, r5, r6, r7, sl} + a814: 00000000 andeq r0, r0, r0 + a818: ebf5e5d8 bl 0xffd83f80 + a81c: 080004e2 stmeqda r0, {r1, r5, r6, r7, sl} + a820: e59d9434 ldr r9, [sp, #1076] + a824: e3c99003 bic r9, r9, #3 ; 0x3 + a828: e2890004 add r0, r9, #4 ; 0x4 + a82c: e58d0434 str r0, [sp, #1076] + a830: e2890000 add r0, r9, #0 ; 0x0 + a834: ebf5e437 bl 0xffd83918 + a838: 080004e6 stmeqda r0, {r1, r2, r5, r6, r7, sl} + a83c: e1a07000 mov r7, r0 + a840: ebf5e5ce bl 0xffd83f80 + a844: 080004e4 stmeqda r0, {r2, r5, r6, r7, sl} + a848: e59d9434 ldr r9, [sp, #1076] + a84c: e3c99003 bic r9, r9, #3 ; 0x3 + a850: e2890004 add r0, r9, #4 ; 0x4 + a854: e58d0434 str r0, [sp, #1076] + a858: e2890000 add r0, r9, #0 ; 0x0 + a85c: ebf5e42d bl 0xffd83918 + a860: 080004e8 stmeqda r0, {r3, r5, r6, r7, sl} + a864: e1a03000 mov r3, r0 + a868: ebf5e5c4 bl 0xffd83f80 + a86c: 080004e6 stmeqda r0, {r1, r2, r5, r6, r7, sl} + a870: e1a00003 mov r0, r3 + a874: e28cc00b add ip, ip, #11 ; 0xb + a878: eaf5e214 b 0xffd830d0 + a87c: 0800050c stmeqda r0, {r2, r3, r8, sl} + a880: 00000000 andeq r0, r0, r0 + a884: ebf5e5bd bl 0xffd83f80 + a888: 0800050c stmeqda r0, {r2, r3, r8, sl} + a88c: e59d9434 ldr r9, [sp, #1076] + a890: e3c99003 bic r9, r9, #3 ; 0x3 + a894: e2499004 sub r9, r9, #4 ; 0x4 + a898: e58d9434 str r9, [sp, #1076] + a89c: e2890000 add r0, r9, #0 ; 0x0 + a8a0: e59d1438 ldr r1, [sp, #1080] + a8a4: ebf5e368 bl 0xffd8364c + a8a8: ebf5e5b4 bl 0xffd83f80 + a8ac: 0800050e stmeqda r0, {r1, r2, r3, r8, sl} + a8b0: e3a00f47 mov r0, #284 ; 0x11c + a8b4: e3800b01 orr r0, r0, #1024 ; 0x400 + a8b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a8bc: ebf5e415 bl 0xffd83918 + a8c0: 08000512 stmeqda r0, {r1, r4, r8, sl} + a8c4: e1a04000 mov r4, r0 + a8c8: ebf5e5ac bl 0xffd83f80 + a8cc: 08000510 stmeqda r0, {r4, r8, sl} + a8d0: e3b03000 movs r3, #0 ; 0x0 + a8d4: ebf5e5a9 bl 0xffd83f80 + a8d8: 08000512 stmeqda r0, {r1, r4, r8, sl} + a8dc: e2840000 add r0, r4, #0 ; 0x0 + a8e0: e1a01003 mov r1, r3 + a8e4: ebf5e338 bl 0xffd835cc + a8e8: 08000514 stmeqda r0, {r2, r4, r8, sl} + a8ec: ebf5e5a3 bl 0xffd83f80 + a8f0: 08000514 stmeqda r0, {r2, r4, r8, sl} + a8f4: ebf5e5a1 bl 0xffd83f80 + a8f8: 08000516 stmeqda r0, {r1, r2, r4, r8, sl} + a8fc: e3a00019 mov r0, #25 ; 0x19 + a900: e3800c05 orr r0, r0, #1280 ; 0x500 + a904: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a908: e58d0438 str r0, [sp, #1080] + a90c: e28cc015 add ip, ip, #21 ; 0x15 + a910: e1a00fac mov r0, ip, lsr #31 + a914: e08ff100 add pc, pc, r0, lsl #2 + a918: 080c0430 stmeqda ip, {r4, r5, sl} + a91c: ebf5e18c bl 0xffd82f54 + a920: ea000001 b 0xa92c + a924: 080c0430 stmeqda ip, {r4, r5, sl} + a928: 00000000 andeq r0, r0, r0 + a92c: ebf5e593 bl 0xffd83f80 + a930: 080c0430 stmeqda ip, {r4, r5, sl} + a934: e59d9434 ldr r9, [sp, #1076] + a938: e3c99003 bic r9, r9, #3 ; 0x3 + a93c: e2499004 sub r9, r9, #4 ; 0x4 + a940: e58d9434 str r9, [sp, #1076] + a944: e2890000 add r0, r9, #0 ; 0x0 + a948: e59d1438 ldr r1, [sp, #1080] + a94c: ebf5e33e bl 0xffd8364c + a950: ebf5e58a bl 0xffd83f80 + a954: 080c0432 stmeqda ip, {r1, r4, r5, sl} + a958: e3a00f0f mov r0, #60 ; 0x3c + a95c: e3800b01 orr r0, r0, #1024 ; 0x400 + a960: e3800703 orr r0, r0, #786432 ; 0xc0000 + a964: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a968: ebf5e3ea bl 0xffd83918 + a96c: 080c0436 stmeqda ip, {r1, r2, r4, r5, sl} + a970: e1a03000 mov r3, r0 + a974: ebf5e581 bl 0xffd83f80 + a978: 080c0434 stmeqda ip, {r2, r4, r5, sl} + a97c: ebf5e57f bl 0xffd83f80 + a980: 080c0436 stmeqda ip, {r1, r2, r4, r5, sl} + a984: e3a00039 mov r0, #57 ; 0x39 + a988: e3800b01 orr r0, r0, #1024 ; 0x400 + a98c: e3800703 orr r0, r0, #786432 ; 0xc0000 + a990: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a994: e58d0438 str r0, [sp, #1080] + a998: e28cc00e add ip, ip, #14 ; 0xe + a99c: e1a00fac mov r0, ip, lsr #31 + a9a0: e08ff100 add pc, pc, r0, lsl #2 + a9a4: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + a9a8: ebf5e169 bl 0xffd82f54 + a9ac: eaffff81 b 0xa7b8 + a9b0: 080bfdb4 stmeqda fp, {r2, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9b4: 00000000 andeq r0, r0, r0 + a9b8: ebf5e570 bl 0xffd83f80 + a9bc: 080bfdb4 stmeqda fp, {r2, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9c0: e3a00f07 mov r0, #28 ; 0x1c + a9c4: e3800703 orr r0, r0, #786432 ; 0xc0000 + a9c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + a9cc: ebf5e3d1 bl 0xffd83918 + a9d0: 080bfdb8 stmeqda fp, {r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9d4: e1a05000 mov r5, r0 + a9d8: ebf5e568 bl 0xffd83f80 + a9dc: 080bfdb6 stmeqda fp, {r1, r2, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9e0: e2830034 add r0, r3, #52 ; 0x34 + a9e4: ebf5e3cb bl 0xffd83918 + a9e8: 080bfdba stmeqda fp, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9ec: e1a06000 mov r6, r0 + a9f0: ebf5e562 bl 0xffd83f80 + a9f4: 080bfdb8 stmeqda fp, {r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + a9f8: e1550006 cmp r5, r6 + a9fc: ebf5e55f bl 0xffd83f80 + aa00: 080bfdba stmeqda fp, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + aa04: e28cc010 add ip, ip, #16 ; 0x10 + aa08: 1a000004 bne 0xaa20 + aa0c: e1a00fac mov r0, ip, lsr #31 + aa10: e08ff100 add pc, pc, r0, lsl #2 + aa14: 080bfdbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + aa18: ebf5e14d bl 0xffd82f54 + aa1c: ea000006 b 0xaa3c + aa20: ebf5e556 bl 0xffd83f80 + aa24: 080bfdbc stmeqda fp, {r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + aa28: e59d0438 ldr r0, [sp, #1080] + aa2c: e28cc003 add ip, ip, #3 ; 0x3 + aa30: eaf5e1a6 b 0xffd830d0 + aa34: 080bfdbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + aa38: 00000000 andeq r0, r0, r0 + aa3c: ebf5e54f bl 0xffd83f80 + aa40: 080bfdbe stmeqda fp, {r1, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp, lr, pc} + aa44: e1a01006 mov r1, r6 + aa48: e2966001 adds r6, r6, #1 ; 0x1 + aa4c: ebf5e54b bl 0xffd83f80 + aa50: 080bfdc0 stmeqda fp, {r6, r7, r8, sl, fp, ip, sp, lr, pc} + aa54: e2830034 add r0, r3, #52 ; 0x34 + aa58: e1a01006 mov r1, r6 + aa5c: ebf5e2da bl 0xffd835cc + aa60: 080bfdc2 stmeqda fp, {r1, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aa64: ebf5e545 bl 0xffd83f80 + aa68: 080bfdc2 stmeqda fp, {r1, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aa6c: e59d9434 ldr r9, [sp, #1076] + aa70: e3c99003 bic r9, r9, #3 ; 0x3 + aa74: e2499008 sub r9, r9, #8 ; 0x8 + aa78: e58d9434 str r9, [sp, #1076] + aa7c: e2890000 add r0, r9, #0 ; 0x0 + aa80: e1a01003 mov r1, r3 + aa84: ebf5e2f0 bl 0xffd8364c + aa88: e2890004 add r0, r9, #4 ; 0x4 + aa8c: e59d1438 ldr r1, [sp, #1080] + aa90: ebf5e2ed bl 0xffd8364c + aa94: ebf5e539 bl 0xffd83f80 + aa98: 080bfdc4 stmeqda fp, {r2, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aa9c: e2830038 add r0, r3, #56 ; 0x38 + aaa0: ebf5e39c bl 0xffd83918 + aaa4: 080bfdc8 stmeqda fp, {r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aaa8: e1a06000 mov r6, r0 + aaac: ebf5e533 bl 0xffd83f80 + aab0: 080bfdc6 stmeqda fp, {r1, r2, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aab4: e3560000 cmp r6, #0 ; 0x0 + aab8: ebf5e530 bl 0xffd83f80 + aabc: 080bfdc8 stmeqda fp, {r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aac0: e28cc016 add ip, ip, #22 ; 0x16 + aac4: 1a000004 bne 0xaadc + aac8: e1a00fac mov r0, ip, lsr #31 + aacc: e08ff100 add pc, pc, r0, lsl #2 + aad0: 080bfdd0 stmeqda fp, {r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aad4: ebf5e11e bl 0xffd82f54 + aad8: ea000014 b 0xab30 + aadc: ebf5e527 bl 0xffd83f80 + aae0: 080bfdca stmeqda fp, {r1, r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aae4: e283003c add r0, r3, #60 ; 0x3c + aae8: ebf5e38a bl 0xffd83918 + aaec: 080bfdce stmeqda fp, {r1, r2, r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aaf0: e1a03000 mov r3, r0 + aaf4: ebf5e521 bl 0xffd83f80 + aaf8: 080bfdcc stmeqda fp, {r2, r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aafc: ebf5e51f bl 0xffd83f80 + ab00: 080bfdce stmeqda fp, {r1, r2, r3, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ab04: e3a000d1 mov r0, #209 ; 0xd1 + ab08: e3800cfd orr r0, r0, #64768 ; 0xfd00 + ab0c: e380080b orr r0, r0, #720896 ; 0xb0000 + ab10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ab14: e58d0438 str r0, [sp, #1080] + ab18: e28cc00b add ip, ip, #11 ; 0xb + ab1c: e1a00fac mov r0, ip, lsr #31 + ab20: e08ff100 add pc, pc, r0, lsl #2 + ab24: 080c0010 stmeqda ip, {r4} + ab28: ebf5e109 bl 0xffd82f54 + ab2c: ea000089 b 0xad58 + ab30: ebf5e512 bl 0xffd83f80 + ab34: 080bfdd0 stmeqda fp, {r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ab38: e59d9434 ldr r9, [sp, #1076] + ab3c: e3c99003 bic r9, r9, #3 ; 0x3 + ab40: e2890004 add r0, r9, #4 ; 0x4 + ab44: e58d0434 str r0, [sp, #1076] + ab48: e2890000 add r0, r9, #0 ; 0x0 + ab4c: ebf5e371 bl 0xffd83918 + ab50: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ab54: e1a03000 mov r3, r0 + ab58: ebf5e508 bl 0xffd83f80 + ab5c: 080bfdd2 stmeqda fp, {r1, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ab60: e59d9434 ldr r9, [sp, #1076] + ab64: e3c99003 bic r9, r9, #3 ; 0x3 + ab68: e2499010 sub r9, r9, #16 ; 0x10 + ab6c: e58d9434 str r9, [sp, #1076] + ab70: e2890000 add r0, r9, #0 ; 0x0 + ab74: e1a01007 mov r1, r7 + ab78: ebf5e2b3 bl 0xffd8364c + ab7c: e2890004 add r0, r9, #4 ; 0x4 + ab80: e1a01008 mov r1, r8 + ab84: ebf5e2b0 bl 0xffd8364c + ab88: e2890008 add r0, r9, #8 ; 0x8 + ab8c: e59d1418 ldr r1, [sp, #1048] + ab90: ebf5e2ad bl 0xffd8364c + ab94: e289000c add r0, r9, #12 ; 0xc + ab98: e59d141c ldr r1, [sp, #1052] + ab9c: ebf5e28a bl 0xffd835cc + aba0: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aba4: ebf5e4f5 bl 0xffd83f80 + aba8: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + abac: e59d1420 ldr r1, [sp, #1056] + abb0: e1a07001 mov r7, r1 + abb4: ebf5e4f1 bl 0xffd83f80 + abb8: 080bfdd6 stmeqda fp, {r1, r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + abbc: e59d1424 ldr r1, [sp, #1060] + abc0: e1a08001 mov r8, r1 + abc4: ebf5e4ed bl 0xffd83f80 + abc8: 080bfdd8 stmeqda fp, {r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + abcc: e59d1428 ldr r1, [sp, #1064] + abd0: e1a00001 mov r0, r1 + abd4: e58d0418 str r0, [sp, #1048] + abd8: ebf5e4e8 bl 0xffd83f80 + abdc: 080bfdda stmeqda fp, {r1, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + abe0: e59d142c ldr r1, [sp, #1068] + abe4: e1a00001 mov r0, r1 + abe8: e58d041c str r0, [sp, #1052] + abec: ebf5e4e3 bl 0xffd83f80 + abf0: 080bfddc stmeqda fp, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + abf4: e59d9434 ldr r9, [sp, #1076] + abf8: e3c99003 bic r9, r9, #3 ; 0x3 + abfc: e2499010 sub r9, r9, #16 ; 0x10 + ac00: e58d9434 str r9, [sp, #1076] + ac04: e2890000 add r0, r9, #0 ; 0x0 + ac08: e1a01007 mov r1, r7 + ac0c: ebf5e28e bl 0xffd8364c + ac10: e2890004 add r0, r9, #4 ; 0x4 + ac14: e1a01008 mov r1, r8 + ac18: ebf5e28b bl 0xffd8364c + ac1c: e2890008 add r0, r9, #8 ; 0x8 + ac20: e59d1418 ldr r1, [sp, #1048] + ac24: ebf5e288 bl 0xffd8364c + ac28: e289000c add r0, r9, #12 ; 0xc + ac2c: e59d141c ldr r1, [sp, #1052] + ac30: ebf5e265 bl 0xffd835cc + ac34: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac38: ebf5e4d0 bl 0xffd83f80 + ac3c: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac40: e1a01003 mov r1, r3 + ac44: e2930000 adds r0, r3, #0 ; 0x0 + ac48: e58d041c str r0, [sp, #1052] + ac4c: ebf5e4cb bl 0xffd83f80 + ac50: 080bfde0 stmeqda fp, {r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac54: e59d041c ldr r0, [sp, #1052] + ac58: e2800004 add r0, r0, #4 ; 0x4 + ac5c: ebf5e32d bl 0xffd83918 + ac60: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac64: e1a03000 mov r3, r0 + ac68: ebf5e4c4 bl 0xffd83f80 + ac6c: 080bfde2 stmeqda fp, {r1, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac70: e3530000 cmp r3, #0 ; 0x0 + ac74: ebf5e4c1 bl 0xffd83f80 + ac78: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac7c: e28cc02c add ip, ip, #44 ; 0x2c + ac80: ba000004 blt 0xac98 + ac84: e1a00fac mov r0, ip, lsr #31 + ac88: e08ff100 add pc, pc, r0, lsl #2 + ac8c: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ac90: ebf5e0af bl 0xffd82f54 + ac94: ea000007 b 0xacb8 + ac98: ebf5e4b8 bl 0xffd83f80 + ac9c: 080bfde6 stmeqda fp, {r1, r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + aca0: e28cc003 add ip, ip, #3 ; 0x3 + aca4: e1a00fac mov r0, ip, lsr #31 + aca8: e08ff100 add pc, pc, r0, lsl #2 + acac: 080c0000 stmeqda ip, {} + acb0: ebf5e0a7 bl 0xffd82f54 + acb4: ea00002e b 0xad74 + acb8: ebf5e4b0 bl 0xffd83f80 + acbc: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + acc0: e3a00f06 mov r0, #24 ; 0x18 + acc4: e3800703 orr r0, r0, #786432 ; 0xc0000 + acc8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + accc: ebf5e311 bl 0xffd83918 + acd0: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + acd4: e1a03000 mov r3, r0 + acd8: ebf5e4a8 bl 0xffd83f80 + acdc: 080bfdea stmeqda fp, {r1, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ace0: e2830000 add r0, r3, #0 ; 0x0 + ace4: ebf5e30b bl 0xffd83918 + ace8: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + acec: e1a03000 mov r3, r0 + acf0: ebf5e4a2 bl 0xffd83f80 + acf4: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + acf8: e1a00003 mov r0, r3 + acfc: e58d0420 str r0, [sp, #1056] + ad00: ebf5e49e bl 0xffd83f80 + ad04: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ad08: e59d141c ldr r1, [sp, #1052] + ad0c: e59d141c ldr r1, [sp, #1052] + ad10: e2913000 adds r3, r1, #0 ; 0x0 + ad14: ebf5e499 bl 0xffd83f80 + ad18: 080bfdf0 stmeqda fp, {r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ad1c: ebf5e497 bl 0xffd83f80 + ad20: 080bfdf2 stmeqda fp, {r1, r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ad24: e3a000f5 mov r0, #245 ; 0xf5 + ad28: e3800cfd orr r0, r0, #64768 ; 0xfd00 + ad2c: e380080b orr r0, r0, #720896 ; 0xb0000 + ad30: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ad34: e58d0438 str r0, [sp, #1080] + ad38: e28cc016 add ip, ip, #22 ; 0x16 + ad3c: e1a00fac mov r0, ip, lsr #31 + ad40: e08ff100 add pc, pc, r0, lsl #2 + ad44: 080c0bb0 stmeqda ip, {r4, r5, r7, r8, r9, fp} + ad48: ebf5e081 bl 0xffd82f54 + ad4c: ea00005e b 0xaecc + ad50: 080c0010 stmeqda ip, {r4} + ad54: 00000000 andeq r0, r0, r0 + ad58: ebf5e488 bl 0xffd83f80 + ad5c: 080c0010 stmeqda ip, {r4} + ad60: e1a00006 mov r0, r6 + ad64: e28cc003 add ip, ip, #3 ; 0x3 + ad68: eaf5e0d8 b 0xffd830d0 + ad6c: 080c0000 stmeqda ip, {} + ad70: 00000000 andeq r0, r0, r0 + ad74: ebf5e481 bl 0xffd83f80 + ad78: 080c0000 stmeqda ip, {} + ad7c: e3a00f07 mov r0, #28 ; 0x1c + ad80: e3800703 orr r0, r0, #786432 ; 0xc0000 + ad84: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ad88: ebf5e2e2 bl 0xffd83918 + ad8c: 080c0004 stmeqda ip, {r2} + ad90: e1a03000 mov r3, r0 + ad94: ebf5e479 bl 0xffd83f80 + ad98: 080c0002 stmeqda ip, {r1} + ad9c: e59d041c ldr r0, [sp, #1052] + ada0: e2800034 add r0, r0, #52 ; 0x34 + ada4: e1a01003 mov r1, r3 + ada8: ebf5e207 bl 0xffd835cc + adac: 080c0004 stmeqda ip, {r2} + adb0: ebf5e472 bl 0xffd83f80 + adb4: 080c0004 stmeqda ip, {r2} + adb8: e59d9434 ldr r9, [sp, #1076] + adbc: e3c99003 bic r9, r9, #3 ; 0x3 + adc0: e2890020 add r0, r9, #32 ; 0x20 + adc4: e58d0434 str r0, [sp, #1076] + adc8: e2890000 add r0, r9, #0 ; 0x0 + adcc: ebf5e2d1 bl 0xffd83918 + add0: 080c0008 stmeqda ip, {r3} + add4: e1a03000 mov r3, r0 + add8: e2890004 add r0, r9, #4 ; 0x4 + addc: ebf5e2cd bl 0xffd83918 + ade0: 080c0008 stmeqda ip, {r3} + ade4: e1a04000 mov r4, r0 + ade8: e2890008 add r0, r9, #8 ; 0x8 + adec: ebf5e2c9 bl 0xffd83918 + adf0: 080c0008 stmeqda ip, {r3} + adf4: e1a05000 mov r5, r0 + adf8: e289000c add r0, r9, #12 ; 0xc + adfc: ebf5e2c5 bl 0xffd83918 + ae00: 080c0008 stmeqda ip, {r3} + ae04: e1a06000 mov r6, r0 + ae08: e2890010 add r0, r9, #16 ; 0x10 + ae0c: ebf5e2c1 bl 0xffd83918 + ae10: 080c0008 stmeqda ip, {r3} + ae14: e1a07000 mov r7, r0 + ae18: e2890014 add r0, r9, #20 ; 0x14 + ae1c: ebf5e2bd bl 0xffd83918 + ae20: 080c0008 stmeqda ip, {r3} + ae24: e1a08000 mov r8, r0 + ae28: e2890018 add r0, r9, #24 ; 0x18 + ae2c: ebf5e2b9 bl 0xffd83918 + ae30: 080c0008 stmeqda ip, {r3} + ae34: e58d0418 str r0, [sp, #1048] + ae38: e289001c add r0, r9, #28 ; 0x1c + ae3c: ebf5e2b5 bl 0xffd83918 + ae40: 080c0008 stmeqda ip, {r3} + ae44: e58d041c str r0, [sp, #1052] + ae48: ebf5e44c bl 0xffd83f80 + ae4c: 080c0006 stmeqda ip, {r1, r2} + ae50: e1a00003 mov r0, r3 + ae54: e58d0420 str r0, [sp, #1056] + ae58: ebf5e448 bl 0xffd83f80 + ae5c: 080c0008 stmeqda ip, {r3} + ae60: e1a00004 mov r0, r4 + ae64: e58d0424 str r0, [sp, #1060] + ae68: ebf5e444 bl 0xffd83f80 + ae6c: 080c000a stmeqda ip, {r1, r3} + ae70: e1a00005 mov r0, r5 + ae74: e58d0428 str r0, [sp, #1064] + ae78: ebf5e440 bl 0xffd83f80 + ae7c: 080c000c stmeqda ip, {r2, r3} + ae80: e1a00006 mov r0, r6 + ae84: e58d042c str r0, [sp, #1068] + ae88: ebf5e43c bl 0xffd83f80 + ae8c: 080c000e stmeqda ip, {r1, r2, r3} + ae90: e59d9434 ldr r9, [sp, #1076] + ae94: e3c99003 bic r9, r9, #3 ; 0x3 + ae98: e2890004 add r0, r9, #4 ; 0x4 + ae9c: e58d0434 str r0, [sp, #1076] + aea0: e2890000 add r0, r9, #0 ; 0x0 + aea4: ebf5e29b bl 0xffd83918 + aea8: 080c0012 stmeqda ip, {r1, r4} + aeac: e1a06000 mov r6, r0 + aeb0: ebf5e432 bl 0xffd83f80 + aeb4: 080c0010 stmeqda ip, {r4} + aeb8: e1a00006 mov r0, r6 + aebc: e28cc027 add ip, ip, #39 ; 0x27 + aec0: eaf5e082 b 0xffd830d0 + aec4: 080c0bb0 stmeqda ip, {r4, r5, r7, r8, r9, fp} + aec8: 00000000 andeq r0, r0, r0 + aecc: ebf5e42b bl 0xffd83f80 + aed0: 080c0bb0 stmeqda ip, {r4, r5, r7, r8, r9, fp} + aed4: e59d9434 ldr r9, [sp, #1076] + aed8: e3c99003 bic r9, r9, #3 ; 0x3 + aedc: e2499014 sub r9, r9, #20 ; 0x14 + aee0: e58d9434 str r9, [sp, #1076] + aee4: e2890000 add r0, r9, #0 ; 0x0 + aee8: e1a01007 mov r1, r7 + aeec: ebf5e1d6 bl 0xffd8364c + aef0: e2890004 add r0, r9, #4 ; 0x4 + aef4: e1a01008 mov r1, r8 + aef8: ebf5e1d3 bl 0xffd8364c + aefc: e2890008 add r0, r9, #8 ; 0x8 + af00: e59d1418 ldr r1, [sp, #1048] + af04: ebf5e1d0 bl 0xffd8364c + af08: e289000c add r0, r9, #12 ; 0xc + af0c: e59d141c ldr r1, [sp, #1052] + af10: ebf5e1cd bl 0xffd8364c + af14: e2890010 add r0, r9, #16 ; 0x10 + af18: e59d1438 ldr r1, [sp, #1080] + af1c: ebf5e1ca bl 0xffd8364c + af20: ebf5e416 bl 0xffd83f80 + af24: 080c0bb2 stmeqda ip, {r1, r4, r5, r7, r8, r9, fp} + af28: e1a01003 mov r1, r3 + af2c: e2930000 adds r0, r3, #0 ; 0x0 + af30: e58d0418 str r0, [sp, #1048] + af34: ebf5e411 bl 0xffd83f80 + af38: 080c0bb4 stmeqda ip, {r2, r4, r5, r7, r8, r9, fp} + af3c: e59d0418 ldr r0, [sp, #1048] + af40: e2800024 add r0, r0, #36 ; 0x24 + af44: ebf5e247 bl 0xffd83868 + af48: 080c0bb8 stmeqda ip, {r3, r4, r5, r7, r8, r9, fp} + af4c: e1a05000 mov r5, r0 + af50: ebf5e40a bl 0xffd83f80 + af54: 080c0bb6 stmeqda ip, {r1, r2, r4, r5, r7, r8, r9, fp} + af58: e3550000 cmp r5, #0 ; 0x0 + af5c: ebf5e407 bl 0xffd83f80 + af60: 080c0bb8 stmeqda ip, {r3, r4, r5, r7, r8, r9, fp} + af64: e28cc015 add ip, ip, #21 ; 0x15 + af68: 1a000004 bne 0xaf80 + af6c: e1a00fac mov r0, ip, lsr #31 + af70: e08ff100 add pc, pc, r0, lsl #2 + af74: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + af78: ebf5dff5 bl 0xffd82f54 + af7c: ea00008a b 0xb1ac + af80: ebf5e3fe bl 0xffd83f80 + af84: 080c0bba stmeqda ip, {r1, r3, r4, r5, r7, r8, r9, fp} + af88: e59d0418 ldr r0, [sp, #1048] + af8c: e2800026 add r0, r0, #38 ; 0x26 + af90: ebf5e234 bl 0xffd83868 + af94: 080c0bbe stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, fp} + af98: e1a03000 mov r3, r0 + af9c: ebf5e3f7 bl 0xffd83f80 + afa0: 080c0bbc stmeqda ip, {r2, r3, r4, r5, r7, r8, r9, fp} + afa4: e1a01003 mov r1, r3 + afa8: e2533001 subs r3, r3, #1 ; 0x1 + afac: ebf5e3f3 bl 0xffd83f80 + afb0: 080c0bbe stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, r9, fp} + afb4: e59d0418 ldr r0, [sp, #1048] + afb8: e2800026 add r0, r0, #38 ; 0x26 + afbc: e1a01003 mov r1, r3 + afc0: ebf5e161 bl 0xffd8354c + afc4: 080c0bc0 stmeqda ip, {r6, r7, r8, r9, fp} + afc8: ebf5e3ec bl 0xffd83f80 + afcc: 080c0bc0 stmeqda ip, {r6, r7, r8, r9, fp} + afd0: e3a00ffe mov r0, #1016 ; 0x3f8 + afd4: e3800b02 orr r0, r0, #2048 ; 0x800 + afd8: e3800703 orr r0, r0, #786432 ; 0xc0000 + afdc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + afe0: ebf5e24c bl 0xffd83918 + afe4: 080c0bc4 stmeqda ip, {r2, r6, r7, r8, r9, fp} + afe8: e1a06000 mov r6, r0 + afec: ebf5e3e3 bl 0xffd83f80 + aff0: 080c0bc2 stmeqda ip, {r1, r6, r7, r8, r9, fp} + aff4: e1a01006 mov r1, r6 + aff8: e2964000 adds r4, r6, #0 ; 0x0 + affc: ebf5e3df bl 0xffd83f80 + b000: 080c0bc4 stmeqda ip, {r2, r6, r7, r8, r9, fp} + b004: e1b03803 movs r3, r3, lsl #16 + b008: ebf5e3dc bl 0xffd83f80 + b00c: 080c0bc6 stmeqda ip, {r1, r2, r6, r7, r8, r9, fp} + b010: e3530000 cmp r3, #0 ; 0x0 + b014: ebf5e3d9 bl 0xffd83f80 + b018: 080c0bc8 stmeqda ip, {r3, r6, r7, r8, r9, fp} + b01c: e28cc01d add ip, ip, #29 ; 0x1d + b020: 0a000004 beq 0xb038 + b024: e1a00fac mov r0, ip, lsr #31 + b028: e08ff100 add pc, pc, r0, lsl #2 + b02c: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b030: ebf5dfc7 bl 0xffd82f54 + b034: ea00005c b 0xb1ac + b038: ebf5e3d0 bl 0xffd83f80 + b03c: 080c0bca stmeqda ip, {r1, r3, r6, r7, r8, r9, fp} + b040: e59d0418 ldr r0, [sp, #1048] + b044: e2800028 add r0, r0, #40 ; 0x28 + b048: ebf5e206 bl 0xffd83868 + b04c: 080c0bce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9, fp} + b050: e1a03000 mov r3, r0 + b054: ebf5e3c9 bl 0xffd83f80 + b058: 080c0bcc stmeqda ip, {r2, r3, r6, r7, r8, r9, fp} + b05c: e1a01003 mov r1, r3 + b060: e2533010 subs r3, r3, #16 ; 0x10 + b064: ebf5e3c5 bl 0xffd83f80 + b068: 080c0bce stmeqda ip, {r1, r2, r3, r6, r7, r8, r9, fp} + b06c: e59d0418 ldr r0, [sp, #1048] + b070: e2800028 add r0, r0, #40 ; 0x28 + b074: e1a01003 mov r1, r3 + b078: ebf5e133 bl 0xffd8354c + b07c: 080c0bd0 stmeqda ip, {r4, r6, r7, r8, r9, fp} + b080: ebf5e3be bl 0xffd83f80 + b084: 080c0bd0 stmeqda ip, {r4, r6, r7, r8, r9, fp} + b088: e1a01003 mov r1, r3 + b08c: e0133004 ands r3, r3, r4 + b090: ebf5e3ba bl 0xffd83f80 + b094: 080c0bd2 stmeqda ip, {r1, r4, r6, r7, r8, r9, fp} + b098: e1b03803 movs r3, r3, lsl #16 + b09c: ebf5e3b7 bl 0xffd83f80 + b0a0: 080c0bd4 stmeqda ip, {r2, r4, r6, r7, r8, r9, fp} + b0a4: e3530000 cmp r3, #0 ; 0x0 + b0a8: ebf5e3b4 bl 0xffd83f80 + b0ac: 080c0bd6 stmeqda ip, {r1, r2, r4, r6, r7, r8, r9, fp} + b0b0: e28cc018 add ip, ip, #24 ; 0x18 + b0b4: da000004 ble 0xb0cc + b0b8: e1a00fac mov r0, ip, lsr #31 + b0bc: e08ff100 add pc, pc, r0, lsl #2 + b0c0: 080c0bfc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, r9, fp} + b0c4: ebf5dfa2 bl 0xffd82f54 + b0c8: ea00005e b 0xb248 + b0cc: ebf5e3ab bl 0xffd83f80 + b0d0: 080c0bd8 stmeqda ip, {r3, r4, r6, r7, r8, r9, fp} + b0d4: e59d0418 ldr r0, [sp, #1048] + b0d8: e2800008 add r0, r0, #8 ; 0x8 + b0dc: ebf5e1b6 bl 0xffd837bc + b0e0: 080c0bdc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9, fp} + b0e4: e1a08000 mov r8, r0 + b0e8: ebf5e3a4 bl 0xffd83f80 + b0ec: 080c0bda stmeqda ip, {r1, r3, r4, r6, r7, r8, r9, fp} + b0f0: e59d0418 ldr r0, [sp, #1048] + b0f4: e280002c add r0, r0, #44 ; 0x2c + b0f8: ebf5e206 bl 0xffd83918 + b0fc: 080c0bde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, fp} + b100: e1a07000 mov r7, r0 + b104: ebf5e39d bl 0xffd83f80 + b108: 080c0bdc stmeqda ip, {r2, r3, r4, r6, r7, r8, r9, fp} + b10c: e3580000 cmp r8, #0 ; 0x0 + b110: ebf5e39a bl 0xffd83f80 + b114: 080c0bde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, r9, fp} + b118: e28cc010 add ip, ip, #16 ; 0x10 + b11c: ca000004 bgt 0xb134 + b120: e1a00fac mov r0, ip, lsr #31 + b124: e08ff100 add pc, pc, r0, lsl #2 + b128: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b12c: ebf5df88 bl 0xffd82f54 + b130: ea00001d b 0xb1ac + b134: ebf5e391 bl 0xffd83f80 + b138: 080c0be0 stmeqda ip, {r5, r6, r7, r8, r9, fp} + b13c: e3b00000 movs r0, #0 ; 0x0 + b140: e58d041c str r0, [sp, #1052] + b144: ebf5e38d bl 0xffd83f80 + b148: 080c0be2 stmeqda ip, {r1, r5, r6, r7, r8, r9, fp} + b14c: e59d1418 ldr r1, [sp, #1048] + b150: e59d1418 ldr r1, [sp, #1048] + b154: e2913000 adds r3, r1, #0 ; 0x0 + b158: ebf5e388 bl 0xffd83f80 + b15c: 080c0be4 stmeqda ip, {r2, r5, r6, r7, r8, r9, fp} + b160: e1a01007 mov r1, r7 + b164: e2974000 adds r4, r7, #0 ; 0x0 + b168: ebf5e384 bl 0xffd83f80 + b16c: 080c0be6 stmeqda ip, {r1, r2, r5, r6, r7, r8, r9, fp} + b170: ebf5e382 bl 0xffd83f80 + b174: 080c0be8 stmeqda ip, {r3, r5, r6, r7, r8, r9, fp} + b178: e3a000eb mov r0, #235 ; 0xeb + b17c: e3800c0b orr r0, r0, #2816 ; 0xb00 + b180: e3800703 orr r0, r0, #786432 ; 0xc0000 + b184: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b188: e58d0438 str r0, [sp, #1080] + b18c: e28cc00f add ip, ip, #15 ; 0xf + b190: e1a00fac mov r0, ip, lsr #31 + b194: e08ff100 add pc, pc, r0, lsl #2 + b198: 080c0020 stmeqda ip, {r5} + b19c: ebf5df6c bl 0xffd82f54 + b1a0: ea0000c9 b 0xb4cc + b1a4: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b1a8: 00000000 andeq r0, r0, r0 + b1ac: ebf5e373 bl 0xffd83f80 + b1b0: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b1b4: e59d9434 ldr r9, [sp, #1076] + b1b8: e3c99003 bic r9, r9, #3 ; 0x3 + b1bc: e2890010 add r0, r9, #16 ; 0x10 + b1c0: e58d0434 str r0, [sp, #1076] + b1c4: e2890000 add r0, r9, #0 ; 0x0 + b1c8: ebf5e1d2 bl 0xffd83918 + b1cc: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b1d0: e1a07000 mov r7, r0 + b1d4: e2890004 add r0, r9, #4 ; 0x4 + b1d8: ebf5e1ce bl 0xffd83918 + b1dc: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b1e0: e1a08000 mov r8, r0 + b1e4: e2890008 add r0, r9, #8 ; 0x8 + b1e8: ebf5e1ca bl 0xffd83918 + b1ec: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b1f0: e58d0418 str r0, [sp, #1048] + b1f4: e289000c add r0, r9, #12 ; 0xc + b1f8: ebf5e1c6 bl 0xffd83918 + b1fc: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b200: e58d041c str r0, [sp, #1052] + b204: ebf5e35d bl 0xffd83f80 + b208: 080c0c2c stmeqda ip, {r2, r3, r5, sl, fp} + b20c: e59d9434 ldr r9, [sp, #1076] + b210: e3c99003 bic r9, r9, #3 ; 0x3 + b214: e2890004 add r0, r9, #4 ; 0x4 + b218: e58d0434 str r0, [sp, #1076] + b21c: e2890000 add r0, r9, #0 ; 0x0 + b220: ebf5e1bc bl 0xffd83918 + b224: 080c0c30 stmeqda ip, {r4, r5, sl, fp} + b228: e1a03000 mov r3, r0 + b22c: ebf5e353 bl 0xffd83f80 + b230: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b234: e1a00003 mov r0, r3 + b238: e28cc00e add ip, ip, #14 ; 0xe + b23c: eaf5dfa3 b 0xffd830d0 + b240: 080c0bfc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, r9, fp} + b244: 00000000 andeq r0, r0, r0 + b248: ebf5e34c bl 0xffd83f80 + b24c: 080c0bfc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, r9, fp} + b250: e59d0418 ldr r0, [sp, #1048] + b254: e2800026 add r0, r0, #38 ; 0x26 + b258: e1a01005 mov r1, r5 + b25c: ebf5e0ba bl 0xffd8354c + b260: 080c0bfe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp} + b264: ebf5e345 bl 0xffd83f80 + b268: 080c0bfe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp} + b26c: e59d0418 ldr r0, [sp, #1048] + b270: e2800008 add r0, r0, #8 ; 0x8 + b274: ebf5e150 bl 0xffd837bc + b278: 080c0c02 stmeqda ip, {r1, sl, fp} + b27c: e1a08000 mov r8, r0 + b280: ebf5e33e bl 0xffd83f80 + b284: 080c0c00 stmeqda ip, {sl, fp} + b288: e59d0418 ldr r0, [sp, #1048] + b28c: e280002c add r0, r0, #44 ; 0x2c + b290: ebf5e1a0 bl 0xffd83918 + b294: 080c0c04 stmeqda ip, {r2, sl, fp} + b298: e1a07000 mov r7, r0 + b29c: ebf5e337 bl 0xffd83f80 + b2a0: 080c0c02 stmeqda ip, {r1, sl, fp} + b2a4: e3580000 cmp r8, #0 ; 0x0 + b2a8: ebf5e334 bl 0xffd83f80 + b2ac: 080c0c04 stmeqda ip, {r2, sl, fp} + b2b0: e28cc014 add ip, ip, #20 ; 0x14 + b2b4: ca000004 bgt 0xb2cc + b2b8: e1a00fac mov r0, ip, lsr #31 + b2bc: e08ff100 add pc, pc, r0, lsl #2 + b2c0: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b2c4: ebf5df22 bl 0xffd82f54 + b2c8: ea000058 b 0xb430 + b2cc: ebf5e32b bl 0xffd83f80 + b2d0: 080c0c06 stmeqda ip, {r1, r2, sl, fp} + b2d4: e3b06080 movs r6, #128 ; 0x80 + b2d8: ebf5e328 bl 0xffd83f80 + b2dc: 080c0c08 stmeqda ip, {r3, sl, fp} + b2e0: e3b00000 movs r0, #0 ; 0x0 + b2e4: e58d041c str r0, [sp, #1052] + b2e8: ebf5e324 bl 0xffd83f80 + b2ec: 080c0c0a stmeqda ip, {r1, r3, sl, fp} + b2f0: e3b05003 movs r5, #3 ; 0x3 + b2f4: e28cc009 add ip, ip, #9 ; 0x9 + b2f8: ebf5e320 bl 0xffd83f80 + b2fc: 080c0c0c stmeqda ip, {r2, r3, sl, fp} + b300: e2870000 add r0, r7, #0 ; 0x0 + b304: ebf5e12c bl 0xffd837bc + b308: 080c0c10 stmeqda ip, {r4, sl, fp} + b30c: e1a04000 mov r4, r0 + b310: ebf5e31a bl 0xffd83f80 + b314: 080c0c0e stmeqda ip, {r1, r2, r3, sl, fp} + b318: e1a01006 mov r1, r6 + b31c: e2963000 adds r3, r6, #0 ; 0x0 + b320: ebf5e316 bl 0xffd83f80 + b324: 080c0c10 stmeqda ip, {r4, sl, fp} + b328: e1a01003 mov r1, r3 + b32c: e0133004 ands r3, r3, r4 + b330: ebf5e312 bl 0xffd83f80 + b334: 080c0c12 stmeqda ip, {r1, r4, sl, fp} + b338: e3530000 cmp r3, #0 ; 0x0 + b33c: ebf5e30f bl 0xffd83f80 + b340: 080c0c14 stmeqda ip, {r2, r4, sl, fp} + b344: e28cc011 add ip, ip, #17 ; 0x11 + b348: 1a000004 bne 0xb360 + b34c: e1a00fac mov r0, ip, lsr #31 + b350: e08ff100 add pc, pc, r0, lsl #2 + b354: 080c0c22 stmeqda ip, {r1, r5, sl, fp} + b358: ebf5defd bl 0xffd82f54 + b35c: ea00001f b 0xb3e0 + b360: ebf5e306 bl 0xffd83f80 + b364: 080c0c16 stmeqda ip, {r1, r2, r4, sl, fp} + b368: e59d0418 ldr r0, [sp, #1048] + b36c: e2800028 add r0, r0, #40 ; 0x28 + b370: ebf5e13c bl 0xffd83868 + b374: 080c0c1a stmeqda ip, {r1, r3, r4, sl, fp} + b378: e58d041c str r0, [sp, #1052] + b37c: ebf5e2ff bl 0xffd83f80 + b380: 080c0c18 stmeqda ip, {r3, r4, sl, fp} + b384: e59de41c ldr lr, [sp, #1052] + b388: e1b0312e movs r3, lr, lsr #2 + b38c: ebf5e2fb bl 0xffd83f80 + b390: 080c0c1a stmeqda ip, {r1, r3, r4, sl, fp} + b394: e2870013 add r0, r7, #19 ; 0x13 + b398: e1a01003 mov r1, r3 + b39c: ebf5e04b bl 0xffd834d0 + b3a0: 080c0c1c stmeqda ip, {r2, r3, r4, sl, fp} + b3a4: ebf5e2f5 bl 0xffd83f80 + b3a8: 080c0c1c stmeqda ip, {r2, r3, r4, sl, fp} + b3ac: e1a01004 mov r1, r4 + b3b0: e2943000 adds r3, r4, #0 ; 0x0 + b3b4: ebf5e2f1 bl 0xffd83f80 + b3b8: 080c0c1e stmeqda ip, {r1, r2, r3, r4, sl, fp} + b3bc: e1a01003 mov r1, r3 + b3c0: e1933005 orrs r3, r3, r5 + b3c4: ebf5e2ed bl 0xffd83f80 + b3c8: 080c0c20 stmeqda ip, {r5, sl, fp} + b3cc: e2870000 add r0, r7, #0 ; 0x0 + b3d0: e1a01003 mov r1, r3 + b3d4: ebf5e03d bl 0xffd834d0 + b3d8: 080c0c22 stmeqda ip, {r1, r5, sl, fp} + b3dc: e28cc016 add ip, ip, #22 ; 0x16 + b3e0: ebf5e2e6 bl 0xffd83f80 + b3e4: 080c0c22 stmeqda ip, {r1, r5, sl, fp} + b3e8: e1a01008 mov r1, r8 + b3ec: e2588001 subs r8, r8, #1 ; 0x1 + b3f0: ebf5e2e2 bl 0xffd83f80 + b3f4: 080c0c24 stmeqda ip, {r2, r5, sl, fp} + b3f8: e1a01007 mov r1, r7 + b3fc: e2977050 adds r7, r7, #80 ; 0x50 + b400: ebf5e2de bl 0xffd83f80 + b404: 080c0c26 stmeqda ip, {r1, r2, r5, sl, fp} + b408: e3580000 cmp r8, #0 ; 0x0 + b40c: ebf5e2db bl 0xffd83f80 + b410: 080c0c28 stmeqda ip, {r3, r5, sl, fp} + b414: e28cc00c add ip, ip, #12 ; 0xc + b418: da000004 ble 0xb430 + b41c: e1a00fac mov r0, ip, lsr #31 + b420: e08ff100 add pc, pc, r0, lsl #2 + b424: 080c0c0c stmeqda ip, {r2, r3, sl, fp} + b428: ebf5dec9 bl 0xffd82f54 + b42c: eaffffb1 b 0xb2f8 + b430: ebf5e2d2 bl 0xffd83f80 + b434: 080c0c2a stmeqda ip, {r1, r3, r5, sl, fp} + b438: e59d9434 ldr r9, [sp, #1076] + b43c: e3c99003 bic r9, r9, #3 ; 0x3 + b440: e2890010 add r0, r9, #16 ; 0x10 + b444: e58d0434 str r0, [sp, #1076] + b448: e2890000 add r0, r9, #0 ; 0x0 + b44c: ebf5e131 bl 0xffd83918 + b450: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b454: e1a07000 mov r7, r0 + b458: e2890004 add r0, r9, #4 ; 0x4 + b45c: ebf5e12d bl 0xffd83918 + b460: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b464: e1a08000 mov r8, r0 + b468: e2890008 add r0, r9, #8 ; 0x8 + b46c: ebf5e129 bl 0xffd83918 + b470: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b474: e58d0418 str r0, [sp, #1048] + b478: e289000c add r0, r9, #12 ; 0xc + b47c: ebf5e125 bl 0xffd83918 + b480: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b484: e58d041c str r0, [sp, #1052] + b488: ebf5e2bc bl 0xffd83f80 + b48c: 080c0c2c stmeqda ip, {r2, r3, r5, sl, fp} + b490: e59d9434 ldr r9, [sp, #1076] + b494: e3c99003 bic r9, r9, #3 ; 0x3 + b498: e2890004 add r0, r9, #4 ; 0x4 + b49c: e58d0434 str r0, [sp, #1076] + b4a0: e2890000 add r0, r9, #0 ; 0x0 + b4a4: ebf5e11b bl 0xffd83918 + b4a8: 080c0c30 stmeqda ip, {r4, r5, sl, fp} + b4ac: e1a03000 mov r3, r0 + b4b0: ebf5e2b2 bl 0xffd83f80 + b4b4: 080c0c2e stmeqda ip, {r1, r2, r3, r5, sl, fp} + b4b8: e1a00003 mov r0, r3 + b4bc: e28cc00e add ip, ip, #14 ; 0xe + b4c0: eaf5df02 b 0xffd830d0 + b4c4: 080c0020 stmeqda ip, {r5} + b4c8: 00000000 andeq r0, r0, r0 + b4cc: ebf5e2ab bl 0xffd83f80 + b4d0: 080c0020 stmeqda ip, {r5} + b4d4: e59d9434 ldr r9, [sp, #1076] + b4d8: e3c99003 bic r9, r9, #3 ; 0x3 + b4dc: e2499010 sub r9, r9, #16 ; 0x10 + b4e0: e58d9434 str r9, [sp, #1076] + b4e4: e2890000 add r0, r9, #0 ; 0x0 + b4e8: e1a01007 mov r1, r7 + b4ec: ebf5e056 bl 0xffd8364c + b4f0: e2890004 add r0, r9, #4 ; 0x4 + b4f4: e1a01008 mov r1, r8 + b4f8: ebf5e053 bl 0xffd8364c + b4fc: e2890008 add r0, r9, #8 ; 0x8 + b500: e59d1418 ldr r1, [sp, #1048] + b504: ebf5e050 bl 0xffd8364c + b508: e289000c add r0, r9, #12 ; 0xc + b50c: e59d1438 ldr r1, [sp, #1080] + b510: ebf5e04d bl 0xffd8364c + b514: ebf5e299 bl 0xffd83f80 + b518: 080c0022 stmeqda ip, {r1, r5} + b51c: e1a01004 mov r1, r4 + b520: e2948000 adds r8, r4, #0 ; 0x0 + b524: ebf5e295 bl 0xffd83f80 + b528: 080c0024 stmeqda ip, {r2, r5} + b52c: e2880000 add r0, r8, #0 ; 0x0 + b530: ebf5e0a1 bl 0xffd837bc + b534: 080c0028 stmeqda ip, {r3, r5} + b538: e1a04000 mov r4, r0 + b53c: ebf5e28f bl 0xffd83f80 + b540: 080c0026 stmeqda ip, {r1, r2, r5} + b544: e3b03080 movs r3, #128 ; 0x80 + b548: ebf5e28c bl 0xffd83f80 + b54c: 080c0028 stmeqda ip, {r3, r5} + b550: e1130004 tst r3, r4 + b554: ebf5e289 bl 0xffd83f80 + b558: 080c002a stmeqda ip, {r1, r3, r5} + b55c: e28cc017 add ip, ip, #23 ; 0x17 + b560: 1a000004 bne 0xb578 + b564: e1a00fac mov r0, ip, lsr #31 + b568: e08ff100 add pc, pc, r0, lsl #2 + b56c: 080c0058 stmeqda ip, {r3, r4, r6} + b570: ebf5de77 bl 0xffd82f54 + b574: ea000086 b 0xb794 + b578: ebf5e280 bl 0xffd83f80 + b57c: 080c002c stmeqda ip, {r2, r3, r5} + b580: e2880020 add r0, r8, #32 ; 0x20 + b584: ebf5e0e3 bl 0xffd83918 + b588: 080c0030 stmeqda ip, {r4, r5} + b58c: e1a07000 mov r7, r0 + b590: ebf5e27a bl 0xffd83f80 + b594: 080c002e stmeqda ip, {r1, r2, r3, r5} + b598: e3570000 cmp r7, #0 ; 0x0 + b59c: ebf5e277 bl 0xffd83f80 + b5a0: 080c0030 stmeqda ip, {r4, r5} + b5a4: e28cc00b add ip, ip, #11 ; 0xb + b5a8: 1a000004 bne 0xb5c0 + b5ac: e1a00fac mov r0, ip, lsr #31 + b5b0: e08ff100 add pc, pc, r0, lsl #2 + b5b4: 080c0056 stmeqda ip, {r1, r2, r4, r6} + b5b8: ebf5de65 bl 0xffd82f54 + b5bc: ea00006d b 0xb778 + b5c0: ebf5e26e bl 0xffd83f80 + b5c4: 080c0032 stmeqda ip, {r1, r4, r5} + b5c8: e3b00000 movs r0, #0 ; 0x0 + b5cc: e58d0418 str r0, [sp, #1048] + b5d0: e28cc003 add ip, ip, #3 ; 0x3 + b5d4: ebf5e269 bl 0xffd83f80 + b5d8: 080c0034 stmeqda ip, {r2, r4, r5} + b5dc: e2870000 add r0, r7, #0 ; 0x0 + b5e0: ebf5e075 bl 0xffd837bc + b5e4: 080c0038 stmeqda ip, {r3, r4, r5} + b5e8: e1a03000 mov r3, r0 + b5ec: ebf5e263 bl 0xffd83f80 + b5f0: 080c0036 stmeqda ip, {r1, r2, r4, r5} + b5f4: e3530000 cmp r3, #0 ; 0x0 + b5f8: ebf5e260 bl 0xffd83f80 + b5fc: 080c0038 stmeqda ip, {r3, r4, r5} + b600: e28cc00b add ip, ip, #11 ; 0xb + b604: 1a000004 bne 0xb61c + b608: e1a00fac mov r0, ip, lsr #31 + b60c: e08ff100 add pc, pc, r0, lsl #2 + b610: 080c004e stmeqda ip, {r1, r2, r3, r6} + b614: ebf5de4e bl 0xffd82f54 + b618: ea00003e b 0xb718 + b61c: ebf5e257 bl 0xffd83f80 + b620: 080c003a stmeqda ip, {r1, r3, r4, r5} + b624: e2870001 add r0, r7, #1 ; 0x1 + b628: ebf5e063 bl 0xffd837bc + b62c: 080c003e stmeqda ip, {r1, r2, r3, r4, r5} + b630: e1a03000 mov r3, r0 + b634: ebf5e251 bl 0xffd83f80 + b638: 080c003c stmeqda ip, {r2, r3, r4, r5} + b63c: e3b06007 movs r6, #7 ; 0x7 + b640: ebf5e24e bl 0xffd83f80 + b644: 080c003e stmeqda ip, {r1, r2, r3, r4, r5} + b648: e1a01003 mov r1, r3 + b64c: e0133006 ands r3, r3, r6 + b650: ebf5e24a bl 0xffd83f80 + b654: 080c0040 stmeqda ip, {r6} + b658: e28cc00e add ip, ip, #14 ; 0xe + b65c: 1a000004 bne 0xb674 + b660: e1a00fac mov r0, ip, lsr #31 + b664: e08ff100 add pc, pc, r0, lsl #2 + b668: 080c004c stmeqda ip, {r2, r3, r6} + b66c: ebf5de38 bl 0xffd82f54 + b670: ea000021 b 0xb6fc + b674: ebf5e241 bl 0xffd83f80 + b678: 080c0042 stmeqda ip, {r1, r6} + b67c: e3a00e06 mov r0, #96 ; 0x60 + b680: e3800703 orr r0, r0, #786432 ; 0xc0000 + b684: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b688: ebf5e0a2 bl 0xffd83918 + b68c: 080c0046 stmeqda ip, {r1, r2, r6} + b690: e1a06000 mov r6, r0 + b694: ebf5e239 bl 0xffd83f80 + b698: 080c0044 stmeqda ip, {r2, r6} + b69c: e2860000 add r0, r6, #0 ; 0x0 + b6a0: ebf5e09c bl 0xffd83918 + b6a4: 080c0048 stmeqda ip, {r3, r6} + b6a8: e1a06000 mov r6, r0 + b6ac: ebf5e233 bl 0xffd83f80 + b6b0: 080c0046 stmeqda ip, {r1, r2, r6} + b6b4: e286002c add r0, r6, #44 ; 0x2c + b6b8: ebf5e096 bl 0xffd83918 + b6bc: 080c004a stmeqda ip, {r1, r3, r6} + b6c0: e1a06000 mov r6, r0 + b6c4: ebf5e22d bl 0xffd83f80 + b6c8: 080c0048 stmeqda ip, {r3, r6} + b6cc: ebf5e22b bl 0xffd83f80 + b6d0: 080c004a stmeqda ip, {r1, r3, r6} + b6d4: e3a0004d mov r0, #77 ; 0x4d + b6d8: e3800703 orr r0, r0, #786432 ; 0xc0000 + b6dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b6e0: e58d0438 str r0, [sp, #1080] + b6e4: e28cc015 add ip, ip, #21 ; 0x15 + b6e8: e1a00fac mov r0, ip, lsr #31 + b6ec: e08ff100 add pc, pc, r0, lsl #2 + b6f0: 080c0010 stmeqda ip, {r4} + b6f4: ebf5de16 bl 0xffd82f54 + b6f8: eafffd96 b 0xad58 + b6fc: ebf5e21f bl 0xffd83f80 + b700: 080c004c stmeqda ip, {r2, r3, r6} + b704: e2870000 add r0, r7, #0 ; 0x0 + b708: e59d1418 ldr r1, [sp, #1048] + b70c: ebf5df6f bl 0xffd834d0 + b710: 080c004e stmeqda ip, {r1, r2, r3, r6} + b714: e28cc004 add ip, ip, #4 ; 0x4 + b718: ebf5e218 bl 0xffd83f80 + b71c: 080c004e stmeqda ip, {r1, r2, r3, r6} + b720: e287002c add r0, r7, #44 ; 0x2c + b724: e59d1418 ldr r1, [sp, #1048] + b728: ebf5dfa7 bl 0xffd835cc + b72c: 080c0050 stmeqda ip, {r4, r6} + b730: ebf5e212 bl 0xffd83f80 + b734: 080c0050 stmeqda ip, {r4, r6} + b738: e2870034 add r0, r7, #52 ; 0x34 + b73c: ebf5e075 bl 0xffd83918 + b740: 080c0054 stmeqda ip, {r2, r4, r6} + b744: e1a07000 mov r7, r0 + b748: ebf5e20c bl 0xffd83f80 + b74c: 080c0052 stmeqda ip, {r1, r4, r6} + b750: e3570000 cmp r7, #0 ; 0x0 + b754: ebf5e209 bl 0xffd83f80 + b758: 080c0054 stmeqda ip, {r2, r4, r6} + b75c: e28cc00f add ip, ip, #15 ; 0xf + b760: 0a000004 beq 0xb778 + b764: e1a00fac mov r0, ip, lsr #31 + b768: e08ff100 add pc, pc, r0, lsl #2 + b76c: 080c0034 stmeqda ip, {r2, r4, r5} + b770: ebf5ddf7 bl 0xffd82f54 + b774: eaffff96 b 0xb5d4 + b778: ebf5e200 bl 0xffd83f80 + b77c: 080c0056 stmeqda ip, {r1, r2, r4, r6} + b780: e2880020 add r0, r8, #32 ; 0x20 + b784: e1a01007 mov r1, r7 + b788: ebf5df8f bl 0xffd835cc + b78c: 080c0058 stmeqda ip, {r3, r4, r6} + b790: e28cc004 add ip, ip, #4 ; 0x4 + b794: ebf5e1f9 bl 0xffd83f80 + b798: 080c0058 stmeqda ip, {r3, r4, r6} + b79c: e59d9434 ldr r9, [sp, #1076] + b7a0: e3c99003 bic r9, r9, #3 ; 0x3 + b7a4: e289000c add r0, r9, #12 ; 0xc + b7a8: e58d0434 str r0, [sp, #1076] + b7ac: e2890000 add r0, r9, #0 ; 0x0 + b7b0: ebf5e058 bl 0xffd83918 + b7b4: 080c005c stmeqda ip, {r2, r3, r4, r6} + b7b8: e1a07000 mov r7, r0 + b7bc: e2890004 add r0, r9, #4 ; 0x4 + b7c0: ebf5e054 bl 0xffd83918 + b7c4: 080c005c stmeqda ip, {r2, r3, r4, r6} + b7c8: e1a08000 mov r8, r0 + b7cc: e2890008 add r0, r9, #8 ; 0x8 + b7d0: ebf5e050 bl 0xffd83918 + b7d4: 080c005c stmeqda ip, {r2, r3, r4, r6} + b7d8: e58d0418 str r0, [sp, #1048] + b7dc: ebf5e1e7 bl 0xffd83f80 + b7e0: 080c005a stmeqda ip, {r1, r3, r4, r6} + b7e4: e59d9434 ldr r9, [sp, #1076] + b7e8: e3c99003 bic r9, r9, #3 ; 0x3 + b7ec: e2890004 add r0, r9, #4 ; 0x4 + b7f0: e58d0434 str r0, [sp, #1076] + b7f4: e2890000 add r0, r9, #0 ; 0x0 + b7f8: ebf5e046 bl 0xffd83918 + b7fc: 080c005e stmeqda ip, {r1, r2, r3, r4, r6} + b800: e1a03000 mov r3, r0 + b804: ebf5e1dd bl 0xffd83f80 + b808: 080c005c stmeqda ip, {r2, r3, r4, r6} + b80c: e1a00003 mov r0, r3 + b810: e28cc00d add ip, ip, #13 ; 0xd + b814: eaf5de2d b 0xffd830d0 + b818: 080bfdd0 stmeqda fp, {r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b81c: 00000000 andeq r0, r0, r0 + b820: ebf5e1d6 bl 0xffd83f80 + b824: 080bfdd0 stmeqda fp, {r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b828: e59d9434 ldr r9, [sp, #1076] + b82c: e3c99003 bic r9, r9, #3 ; 0x3 + b830: e2890004 add r0, r9, #4 ; 0x4 + b834: e58d0434 str r0, [sp, #1076] + b838: e2890000 add r0, r9, #0 ; 0x0 + b83c: ebf5e035 bl 0xffd83918 + b840: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b844: e1a03000 mov r3, r0 + b848: ebf5e1cc bl 0xffd83f80 + b84c: 080bfdd2 stmeqda fp, {r1, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b850: e59d9434 ldr r9, [sp, #1076] + b854: e3c99003 bic r9, r9, #3 ; 0x3 + b858: e2499010 sub r9, r9, #16 ; 0x10 + b85c: e58d9434 str r9, [sp, #1076] + b860: e2890000 add r0, r9, #0 ; 0x0 + b864: e1a01007 mov r1, r7 + b868: ebf5df77 bl 0xffd8364c + b86c: e2890004 add r0, r9, #4 ; 0x4 + b870: e1a01008 mov r1, r8 + b874: ebf5df74 bl 0xffd8364c + b878: e2890008 add r0, r9, #8 ; 0x8 + b87c: e59d1418 ldr r1, [sp, #1048] + b880: ebf5df71 bl 0xffd8364c + b884: e289000c add r0, r9, #12 ; 0xc + b888: e59d141c ldr r1, [sp, #1052] + b88c: ebf5df4e bl 0xffd835cc + b890: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b894: ebf5e1b9 bl 0xffd83f80 + b898: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b89c: e59d1420 ldr r1, [sp, #1056] + b8a0: e1a07001 mov r7, r1 + b8a4: ebf5e1b5 bl 0xffd83f80 + b8a8: 080bfdd6 stmeqda fp, {r1, r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b8ac: e59d1424 ldr r1, [sp, #1060] + b8b0: e1a08001 mov r8, r1 + b8b4: ebf5e1b1 bl 0xffd83f80 + b8b8: 080bfdd8 stmeqda fp, {r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b8bc: e59d1428 ldr r1, [sp, #1064] + b8c0: e1a00001 mov r0, r1 + b8c4: e58d0418 str r0, [sp, #1048] + b8c8: ebf5e1ac bl 0xffd83f80 + b8cc: 080bfdda stmeqda fp, {r1, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b8d0: e59d142c ldr r1, [sp, #1068] + b8d4: e1a00001 mov r0, r1 + b8d8: e58d041c str r0, [sp, #1052] + b8dc: ebf5e1a7 bl 0xffd83f80 + b8e0: 080bfddc stmeqda fp, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b8e4: e59d9434 ldr r9, [sp, #1076] + b8e8: e3c99003 bic r9, r9, #3 ; 0x3 + b8ec: e2499010 sub r9, r9, #16 ; 0x10 + b8f0: e58d9434 str r9, [sp, #1076] + b8f4: e2890000 add r0, r9, #0 ; 0x0 + b8f8: e1a01007 mov r1, r7 + b8fc: ebf5df52 bl 0xffd8364c + b900: e2890004 add r0, r9, #4 ; 0x4 + b904: e1a01008 mov r1, r8 + b908: ebf5df4f bl 0xffd8364c + b90c: e2890008 add r0, r9, #8 ; 0x8 + b910: e59d1418 ldr r1, [sp, #1048] + b914: ebf5df4c bl 0xffd8364c + b918: e289000c add r0, r9, #12 ; 0xc + b91c: e59d141c ldr r1, [sp, #1052] + b920: ebf5df29 bl 0xffd835cc + b924: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b928: ebf5e194 bl 0xffd83f80 + b92c: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b930: e1a01003 mov r1, r3 + b934: e2930000 adds r0, r3, #0 ; 0x0 + b938: e58d041c str r0, [sp, #1052] + b93c: ebf5e18f bl 0xffd83f80 + b940: 080bfde0 stmeqda fp, {r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b944: e59d041c ldr r0, [sp, #1052] + b948: e2800004 add r0, r0, #4 ; 0x4 + b94c: ebf5dff1 bl 0xffd83918 + b950: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b954: e1a03000 mov r3, r0 + b958: ebf5e188 bl 0xffd83f80 + b95c: 080bfde2 stmeqda fp, {r1, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b960: e3530000 cmp r3, #0 ; 0x0 + b964: ebf5e185 bl 0xffd83f80 + b968: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b96c: e28cc02c add ip, ip, #44 ; 0x2c + b970: ba000004 blt 0xb988 + b974: e1a00fac mov r0, ip, lsr #31 + b978: e08ff100 add pc, pc, r0, lsl #2 + b97c: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b980: ebf5dd73 bl 0xffd82f54 + b984: ea000007 b 0xb9a8 + b988: ebf5e17c bl 0xffd83f80 + b98c: 080bfde6 stmeqda fp, {r1, r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b990: e28cc003 add ip, ip, #3 ; 0x3 + b994: e1a00fac mov r0, ip, lsr #31 + b998: e08ff100 add pc, pc, r0, lsl #2 + b99c: 080c0000 stmeqda ip, {} + b9a0: ebf5dd6b bl 0xffd82f54 + b9a4: eafffcf2 b 0xad74 + b9a8: ebf5e174 bl 0xffd83f80 + b9ac: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9b0: e3a00f06 mov r0, #24 ; 0x18 + b9b4: e3800703 orr r0, r0, #786432 ; 0xc0000 + b9b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + b9bc: ebf5dfd5 bl 0xffd83918 + b9c0: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9c4: e1a03000 mov r3, r0 + b9c8: ebf5e16c bl 0xffd83f80 + b9cc: 080bfdea stmeqda fp, {r1, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9d0: e2830000 add r0, r3, #0 ; 0x0 + b9d4: ebf5dfcf bl 0xffd83918 + b9d8: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9dc: e1a03000 mov r3, r0 + b9e0: ebf5e166 bl 0xffd83f80 + b9e4: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9e8: e1a00003 mov r0, r3 + b9ec: e58d0420 str r0, [sp, #1056] + b9f0: ebf5e162 bl 0xffd83f80 + b9f4: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + b9f8: e59d141c ldr r1, [sp, #1052] + b9fc: e59d141c ldr r1, [sp, #1052] + ba00: e2913000 adds r3, r1, #0 ; 0x0 + ba04: ebf5e15d bl 0xffd83f80 + ba08: 080bfdf0 stmeqda fp, {r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ba0c: ebf5e15b bl 0xffd83f80 + ba10: 080bfdf2 stmeqda fp, {r1, r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + ba14: e3a000f5 mov r0, #245 ; 0xf5 + ba18: e3800cfd orr r0, r0, #64768 ; 0xfd00 + ba1c: e380080b orr r0, r0, #720896 ; 0xb0000 + ba20: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ba24: e58d0438 str r0, [sp, #1080] + ba28: e28cc016 add ip, ip, #22 ; 0x16 + ba2c: e1a00fac mov r0, ip, lsr #31 + ba30: e08ff100 add pc, pc, r0, lsl #2 + ba34: 080c0bb0 stmeqda ip, {r4, r5, r7, r8, r9, fp} + ba38: ebf5dd45 bl 0xffd82f54 + ba3c: eafffd22 b 0xaecc + ba40: 080c0e58 stmeqda ip, {r3, r4, r6, r9, sl, fp} + ba44: 00000000 andeq r0, r0, r0 + ba48: ebf5e14c bl 0xffd83f80 + ba4c: 080c0e58 stmeqda ip, {r3, r4, r6, r9, sl, fp} + ba50: e59d9434 ldr r9, [sp, #1076] + ba54: e3c99003 bic r9, r9, #3 ; 0x3 + ba58: e2499014 sub r9, r9, #20 ; 0x14 + ba5c: e58d9434 str r9, [sp, #1076] + ba60: e2890000 add r0, r9, #0 ; 0x0 + ba64: e1a01007 mov r1, r7 + ba68: ebf5def7 bl 0xffd8364c + ba6c: e2890004 add r0, r9, #4 ; 0x4 + ba70: e1a01008 mov r1, r8 + ba74: ebf5def4 bl 0xffd8364c + ba78: e2890008 add r0, r9, #8 ; 0x8 + ba7c: e59d1418 ldr r1, [sp, #1048] + ba80: ebf5def1 bl 0xffd8364c + ba84: e289000c add r0, r9, #12 ; 0xc + ba88: e59d141c ldr r1, [sp, #1052] + ba8c: ebf5deee bl 0xffd8364c + ba90: e2890010 add r0, r9, #16 ; 0x10 + ba94: e59d1438 ldr r1, [sp, #1080] + ba98: ebf5deeb bl 0xffd8364c + ba9c: ebf5e137 bl 0xffd83f80 + baa0: 080c0e5a stmeqda ip, {r1, r3, r4, r6, r9, sl, fp} + baa4: e59d1428 ldr r1, [sp, #1064] + baa8: e1a00001 mov r0, r1 + baac: e58d041c str r0, [sp, #1052] + bab0: ebf5e132 bl 0xffd83f80 + bab4: 080c0e5c stmeqda ip, {r2, r3, r4, r6, r9, sl, fp} + bab8: e59d1424 ldr r1, [sp, #1060] + babc: e1a00001 mov r0, r1 + bac0: e58d0418 str r0, [sp, #1048] + bac4: ebf5e12d bl 0xffd83f80 + bac8: 080c0e5e stmeqda ip, {r1, r2, r3, r4, r6, r9, sl, fp} + bacc: e59d1420 ldr r1, [sp, #1056] + bad0: e1a08001 mov r8, r1 + bad4: ebf5e129 bl 0xffd83f80 + bad8: 080c0e60 stmeqda ip, {r5, r6, r9, sl, fp} + badc: e59d9434 ldr r9, [sp, #1076] + bae0: e3c99003 bic r9, r9, #3 ; 0x3 + bae4: e249900c sub r9, r9, #12 ; 0xc + bae8: e58d9434 str r9, [sp, #1076] + baec: e2890000 add r0, r9, #0 ; 0x0 + baf0: e1a01008 mov r1, r8 + baf4: ebf5ded4 bl 0xffd8364c + baf8: e2890004 add r0, r9, #4 ; 0x4 + bafc: e59d1418 ldr r1, [sp, #1048] + bb00: ebf5ded1 bl 0xffd8364c + bb04: e2890008 add r0, r9, #8 ; 0x8 + bb08: e59d141c ldr r1, [sp, #1052] + bb0c: ebf5deae bl 0xffd835cc + bb10: 080c0e62 stmeqda ip, {r1, r5, r6, r9, sl, fp} + bb14: ebf5e119 bl 0xffd83f80 + bb18: 080c0e62 stmeqda ip, {r1, r5, r6, r9, sl, fp} + bb1c: e59d0434 ldr r0, [sp, #1076] + bb20: e2400f06 sub r0, r0, #24 ; 0x18 + bb24: e58d0434 str r0, [sp, #1076] + bb28: ebf5e114 bl 0xffd83f80 + bb2c: 080c0e64 stmeqda ip, {r2, r5, r6, r9, sl, fp} + bb30: e3a00f9e mov r0, #632 ; 0x278 + bb34: e3800b03 orr r0, r0, #3072 ; 0xc00 + bb38: e3800703 orr r0, r0, #786432 ; 0xc0000 + bb3c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + bb40: ebf5df74 bl 0xffd83918 + bb44: 080c0e68 stmeqda ip, {r3, r5, r6, r9, sl, fp} + bb48: e1a03000 mov r3, r0 + bb4c: ebf5e10b bl 0xffd83f80 + bb50: 080c0e66 stmeqda ip, {r1, r2, r5, r6, r9, sl, fp} + bb54: e2830000 add r0, r3, #0 ; 0x0 + bb58: ebf5df6e bl 0xffd83918 + bb5c: 080c0e6a stmeqda ip, {r1, r3, r5, r6, r9, sl, fp} + bb60: e1a03000 mov r3, r0 + bb64: ebf5e105 bl 0xffd83f80 + bb68: 080c0e68 stmeqda ip, {r3, r5, r6, r9, sl, fp} + bb6c: e59d0434 ldr r0, [sp, #1076] + bb70: e2800f01 add r0, r0, #4 ; 0x4 + bb74: e1a01003 mov r1, r3 + bb78: ebf5de93 bl 0xffd835cc + bb7c: 080c0e6a stmeqda ip, {r1, r3, r5, r6, r9, sl, fp} + bb80: ebf5e0fe bl 0xffd83f80 + bb84: 080c0e6a stmeqda ip, {r1, r3, r5, r6, r9, sl, fp} + bb88: e283000a add r0, r3, #10 ; 0xa + bb8c: ebf5df0a bl 0xffd837bc + bb90: 080c0e6e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl, fp} + bb94: e1a03000 mov r3, r0 + bb98: ebf5e0f8 bl 0xffd83f80 + bb9c: 080c0e6c stmeqda ip, {r2, r3, r5, r6, r9, sl, fp} + bba0: e3530000 cmp r3, #0 ; 0x0 + bba4: ebf5e0f5 bl 0xffd83f80 + bba8: 080c0e6e stmeqda ip, {r1, r2, r3, r5, r6, r9, sl, fp} + bbac: e28cc032 add ip, ip, #50 ; 0x32 + bbb0: 1a000004 bne 0xbbc8 + bbb4: e1a00fac mov r0, ip, lsr #31 + bbb8: e08ff100 add pc, pc, r0, lsl #2 + bbbc: 080c0e7c stmeqda ip, {r2, r3, r4, r5, r6, r9, sl, fp} + bbc0: ebf5dce3 bl 0xffd82f54 + bbc4: ea00001a b 0xbc34 + bbc8: ebf5e0ec bl 0xffd83f80 + bbcc: 080c0e70 stmeqda ip, {r4, r5, r6, r9, sl, fp} + bbd0: e1a01003 mov r1, r3 + bbd4: e2533001 subs r3, r3, #1 ; 0x1 + bbd8: ebf5e0e8 bl 0xffd83f80 + bbdc: 080c0e72 stmeqda ip, {r1, r4, r5, r6, r9, sl, fp} + bbe0: e59d0434 ldr r0, [sp, #1076] + bbe4: e2800f01 add r0, r0, #4 ; 0x4 + bbe8: ebf5df4a bl 0xffd83918 + bbec: 080c0e76 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl, fp} + bbf0: e1a04000 mov r4, r0 + bbf4: ebf5e0e1 bl 0xffd83f80 + bbf8: 080c0e74 stmeqda ip, {r2, r4, r5, r6, r9, sl, fp} + bbfc: e284000a add r0, r4, #10 ; 0xa + bc00: e1a01003 mov r1, r3 + bc04: ebf5de31 bl 0xffd834d0 + bc08: 080c0e76 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl, fp} + bc0c: ebf5e0db bl 0xffd83f80 + bc10: 080c0e76 stmeqda ip, {r1, r2, r4, r5, r6, r9, sl, fp} + bc14: e28cc00f add ip, ip, #15 ; 0xf + bc18: e1a00fac mov r0, ip, lsr #31 + bc1c: e08ff100 add pc, pc, r0, lsl #2 + bc20: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + bc24: ebf5dcca bl 0xffd82f54 + bc28: ea000e50 b 0xf570 + bc2c: 080c0e7c stmeqda ip, {r2, r3, r4, r5, r6, r9, sl, fp} + bc30: 00000000 andeq r0, r0, r0 + bc34: ebf5e0d1 bl 0xffd83f80 + bc38: 080c0e7c stmeqda ip, {r2, r3, r4, r5, r6, r9, sl, fp} + bc3c: e3b0300e movs r3, #14 ; 0xe + bc40: ebf5e0ce bl 0xffd83f80 + bc44: 080c0e7e stmeqda ip, {r1, r2, r3, r4, r5, r6, r9, sl, fp} + bc48: e59d0434 ldr r0, [sp, #1076] + bc4c: e2800f01 add r0, r0, #4 ; 0x4 + bc50: ebf5df30 bl 0xffd83918 + bc54: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + bc58: e1a05000 mov r5, r0 + bc5c: ebf5e0c7 bl 0xffd83f80 + bc60: 080c0e80 stmeqda ip, {r7, r9, sl, fp} + bc64: e285000a add r0, r5, #10 ; 0xa + bc68: e1a01003 mov r1, r3 + bc6c: ebf5de17 bl 0xffd834d0 + bc70: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + bc74: ebf5e0c1 bl 0xffd83f80 + bc78: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + bc7c: e3b00001 movs r0, #1 ; 0x1 + bc80: e58d0418 str r0, [sp, #1048] + bc84: ebf5e0bd bl 0xffd83f80 + bc88: 080c0e84 stmeqda ip, {r2, r7, r9, sl, fp} + bc8c: e59d0434 ldr r0, [sp, #1076] + bc90: e2800f01 add r0, r0, #4 ; 0x4 + bc94: ebf5df1f bl 0xffd83918 + bc98: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + bc9c: e1a03000 mov r3, r0 + bca0: ebf5e0b6 bl 0xffd83f80 + bca4: 080c0e86 stmeqda ip, {r1, r2, r7, r9, sl, fp} + bca8: e283001c add r0, r3, #28 ; 0x1c + bcac: ebf5df19 bl 0xffd83918 + bcb0: 080c0e8a stmeqda ip, {r1, r3, r7, r9, sl, fp} + bcb4: e1a07000 mov r7, r0 + bcb8: ebf5e0b0 bl 0xffd83f80 + bcbc: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + bcc0: e2870000 add r0, r7, #0 ; 0x0 + bcc4: ebf5debc bl 0xffd837bc + bcc8: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + bccc: e1a04000 mov r4, r0 + bcd0: ebf5e0aa bl 0xffd83f80 + bcd4: 080c0e8a stmeqda ip, {r1, r3, r7, r9, sl, fp} + bcd8: e3b030c7 movs r3, #199 ; 0xc7 + bcdc: ebf5e0a7 bl 0xffd83f80 + bce0: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + bce4: e1a01003 mov r1, r3 + bce8: e0133004 ands r3, r3, r4 + bcec: ebf5e0a3 bl 0xffd83f80 + bcf0: 080c0e8e stmeqda ip, {r1, r2, r3, r7, r9, sl, fp} + bcf4: e59d1418 ldr r1, [sp, #1048] + bcf8: e59d1418 ldr r1, [sp, #1048] + bcfc: e2915001 adds r5, r1, #1 ; 0x1 + bd00: ebf5e09e bl 0xffd83f80 + bd04: 080c0e90 stmeqda ip, {r4, r7, r9, sl, fp} + bd08: e1a00005 mov r0, r5 + bd0c: e58d0424 str r0, [sp, #1060] + bd10: ebf5e09a bl 0xffd83f80 + bd14: 080c0e92 stmeqda ip, {r1, r4, r7, r9, sl, fp} + bd18: e3b05040 movs r5, #64 ; 0x40 + bd1c: ebf5e097 bl 0xffd83f80 + bd20: 080c0e94 stmeqda ip, {r2, r4, r7, r9, sl, fp} + bd24: e1a01005 mov r1, r5 + bd28: e0955007 adds r5, r5, r7 + bd2c: ebf5e093 bl 0xffd83f80 + bd30: 080c0e96 stmeqda ip, {r1, r2, r4, r7, r9, sl, fp} + bd34: e1a00005 mov r0, r5 + bd38: e58d0420 str r0, [sp, #1056] + bd3c: ebf5e08f bl 0xffd83f80 + bd40: 080c0e98 stmeqda ip, {r3, r4, r7, r9, sl, fp} + bd44: e3530000 cmp r3, #0 ; 0x0 + bd48: ebf5e08c bl 0xffd83f80 + bd4c: 080c0e9a stmeqda ip, {r1, r3, r4, r7, r9, sl, fp} + bd50: e28cc039 add ip, ip, #57 ; 0x39 + bd54: 0a000004 beq 0xbd6c + bd58: e1a00fac mov r0, ip, lsr #31 + bd5c: e08ff100 add pc, pc, r0, lsl #2 + bd60: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + bd64: ebf5dc7a bl 0xffd82f54 + bd68: ea000007 b 0xbd8c + bd6c: ebf5e083 bl 0xffd83f80 + bd70: 080c0e9c stmeqda ip, {r2, r3, r4, r7, r9, sl, fp} + bd74: e28cc003 add ip, ip, #3 ; 0x3 + bd78: e1a00fac mov r0, ip, lsr #31 + bd7c: e08ff100 add pc, pc, r0, lsl #2 + bd80: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + bd84: ebf5dc72 bl 0xffd82f54 + bd88: ea000082 b 0xbf98 + bd8c: ebf5e07b bl 0xffd83f80 + bd90: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + bd94: e59d1418 ldr r1, [sp, #1048] + bd98: e3510002 cmp r1, #2 ; 0x2 + bd9c: ebf5e077 bl 0xffd83f80 + bda0: 080c0ea0 stmeqda ip, {r5, r7, r9, sl, fp} + bda4: e28cc006 add ip, ip, #6 ; 0x6 + bda8: 1a000004 bne 0xbdc0 + bdac: e1a00fac mov r0, ip, lsr #31 + bdb0: e08ff100 add pc, pc, r0, lsl #2 + bdb4: 080c0ed0 stmeqda ip, {r4, r6, r7, r9, sl, fp} + bdb8: ebf5dc65 bl 0xffd82f54 + bdbc: ea000195 b 0xc418 + bdc0: ebf5e06e bl 0xffd83f80 + bdc4: 080c0ea2 stmeqda ip, {r1, r5, r7, r9, sl, fp} + bdc8: e59d1418 ldr r1, [sp, #1048] + bdcc: e3510002 cmp r1, #2 ; 0x2 + bdd0: ebf5e06a bl 0xffd83f80 + bdd4: 080c0ea4 stmeqda ip, {r2, r5, r7, r9, sl, fp} + bdd8: e28cc006 add ip, ip, #6 ; 0x6 + bddc: da000004 ble 0xbdf4 + bde0: e1a00fac mov r0, ip, lsr #31 + bde4: e08ff100 add pc, pc, r0, lsl #2 + bde8: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + bdec: ebf5dc58 bl 0xffd82f54 + bdf0: ea000014 b 0xbe48 + bdf4: ebf5e061 bl 0xffd83f80 + bdf8: 080c0ea6 stmeqda ip, {r1, r2, r5, r7, r9, sl, fp} + bdfc: e59d1418 ldr r1, [sp, #1048] + be00: e3510001 cmp r1, #1 ; 0x1 + be04: ebf5e05d bl 0xffd83f80 + be08: 080c0ea8 stmeqda ip, {r3, r5, r7, r9, sl, fp} + be0c: e28cc006 add ip, ip, #6 ; 0x6 + be10: 1a000004 bne 0xbe28 + be14: e1a00fac mov r0, ip, lsr #31 + be18: e08ff100 add pc, pc, r0, lsl #2 + be1c: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + be20: ebf5dc4b bl 0xffd82f54 + be24: ea00001c b 0xbe9c + be28: ebf5e054 bl 0xffd83f80 + be2c: 080c0eaa stmeqda ip, {r1, r3, r5, r7, r9, sl, fp} + be30: e28cc003 add ip, ip, #3 ; 0x3 + be34: e1a00fac mov r0, ip, lsr #31 + be38: e08ff100 add pc, pc, r0, lsl #2 + be3c: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + be40: ebf5dc43 bl 0xffd82f54 + be44: ea000c3b b 0xef38 + be48: ebf5e04c bl 0xffd83f80 + be4c: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + be50: e59d1418 ldr r1, [sp, #1048] + be54: e3510003 cmp r1, #3 ; 0x3 + be58: ebf5e048 bl 0xffd83f80 + be5c: 080c0eae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl, fp} + be60: e28cc006 add ip, ip, #6 ; 0x6 + be64: 1a000004 bne 0xbe7c + be68: e1a00fac mov r0, ip, lsr #31 + be6c: e08ff100 add pc, pc, r0, lsl #2 + be70: 080c0ee8 stmeqda ip, {r3, r5, r6, r7, r9, sl, fp} + be74: ebf5dc36 bl 0xffd82f54 + be78: ea000cf0 b 0xf240 + be7c: ebf5e03f bl 0xffd83f80 + be80: 080c0eb0 stmeqda ip, {r4, r5, r7, r9, sl, fp} + be84: e28cc003 add ip, ip, #3 ; 0x3 + be88: e1a00fac mov r0, ip, lsr #31 + be8c: e08ff100 add pc, pc, r0, lsl #2 + be90: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + be94: ebf5dc2e bl 0xffd82f54 + be98: ea000c26 b 0xef38 + be9c: ebf5e037 bl 0xffd83f80 + bea0: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + bea4: e3a00fb1 mov r0, #708 ; 0x2c4 + bea8: e3800b03 orr r0, r0, #3072 ; 0xc00 + beac: e3800703 orr r0, r0, #786432 ; 0xc0000 + beb0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + beb4: ebf5de97 bl 0xffd83918 + beb8: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + bebc: e1a03000 mov r3, r0 + bec0: ebf5e02e bl 0xffd83f80 + bec4: 080c0eb4 stmeqda ip, {r2, r4, r5, r7, r9, sl, fp} + bec8: e59d0434 ldr r0, [sp, #1076] + becc: e2800f02 add r0, r0, #8 ; 0x8 + bed0: e1a01003 mov r1, r3 + bed4: ebf5ddbc bl 0xffd835cc + bed8: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + bedc: ebf5e027 bl 0xffd83f80 + bee0: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + bee4: e3a00fb2 mov r0, #712 ; 0x2c8 + bee8: e3800b03 orr r0, r0, #3072 ; 0xc00 + beec: e3800703 orr r0, r0, #786432 ; 0xc0000 + bef0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + bef4: ebf5de87 bl 0xffd83918 + bef8: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + befc: e58d041c str r0, [sp, #1052] + bf00: ebf5e01e bl 0xffd83f80 + bf04: 080c0eb8 stmeqda ip, {r3, r4, r5, r7, r9, sl, fp} + bf08: e3a00fb3 mov r0, #716 ; 0x2cc + bf0c: e3800b03 orr r0, r0, #3072 ; 0xc00 + bf10: e3800703 orr r0, r0, #786432 ; 0xc0000 + bf14: e3800302 orr r0, r0, #134217728 ; 0x8000000 + bf18: ebf5de7e bl 0xffd83918 + bf1c: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + bf20: e1a05000 mov r5, r0 + bf24: ebf5e015 bl 0xffd83f80 + bf28: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + bf2c: e1a00005 mov r0, r5 + bf30: e58d0428 str r0, [sp, #1064] + bf34: ebf5e011 bl 0xffd83f80 + bf38: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + bf3c: e1a01003 mov r1, r3 + bf40: e2933004 adds r3, r3, #4 ; 0x4 + bf44: ebf5e00d bl 0xffd83f80 + bf48: 080c0ebe stmeqda ip, {r1, r2, r3, r4, r5, r7, r9, sl, fp} + bf4c: e59d0434 ldr r0, [sp, #1076] + bf50: e2800f03 add r0, r0, #12 ; 0xc + bf54: e1a01003 mov r1, r3 + bf58: ebf5dd9b bl 0xffd835cc + bf5c: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + bf60: ebf5e006 bl 0xffd83f80 + bf64: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + bf68: e1a01005 mov r1, r5 + bf6c: e2955002 adds r5, r5, #2 ; 0x2 + bf70: ebf5e002 bl 0xffd83f80 + bf74: 080c0ec2 stmeqda ip, {r1, r6, r7, r9, sl, fp} + bf78: e28cc023 add ip, ip, #35 ; 0x23 + bf7c: e1a00fac mov r0, ip, lsr #31 + bf80: e08ff100 add pc, pc, r0, lsl #2 + bf84: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + bf88: ebf5dbf1 bl 0xffd82f54 + bf8c: ea000ce9 b 0xf338 + bf90: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + bf94: 00000000 andeq r0, r0, r0 + bf98: ebf5dff8 bl 0xffd83f80 + bf9c: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + bfa0: e59d1424 ldr r1, [sp, #1060] + bfa4: e1a00001 mov r0, r1 + bfa8: e58d0418 str r0, [sp, #1048] + bfac: ebf5dff3 bl 0xffd83f80 + bfb0: 080c125a stmeqda ip, {r1, r3, r4, r6, r9, ip} + bfb4: e59d1420 ldr r1, [sp, #1056] + bfb8: e1a07001 mov r7, r1 + bfbc: ebf5dfef bl 0xffd83f80 + bfc0: 080c125c stmeqda ip, {r2, r3, r4, r6, r9, ip} + bfc4: e59d1418 ldr r1, [sp, #1048] + bfc8: e3510004 cmp r1, #4 ; 0x4 + bfcc: ebf5dfeb bl 0xffd83f80 + bfd0: 080c125e stmeqda ip, {r1, r2, r3, r4, r6, r9, ip} + bfd4: e28cc00c add ip, ip, #12 ; 0xc + bfd8: da000004 ble 0xbff0 + bfdc: e1a00fac mov r0, ip, lsr #31 + bfe0: e08ff100 add pc, pc, r0, lsl #2 + bfe4: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + bfe8: ebf5dbd9 bl 0xffd82f54 + bfec: ea000007 b 0xc010 + bff0: ebf5dfe2 bl 0xffd83f80 + bff4: 080c1260 stmeqda ip, {r5, r6, r9, ip} + bff8: e28cc003 add ip, ip, #3 ; 0x3 + bffc: e1a00fac mov r0, ip, lsr #31 + c000: e08ff100 add pc, pc, r0, lsl #2 + c004: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + c008: ebf5dbd1 bl 0xffd82f54 + c00c: ea000049 b 0xc138 + c010: ebf5dfda bl 0xffd83f80 + c014: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + c018: e59d0434 ldr r0, [sp, #1076] + c01c: e2800f06 add r0, r0, #24 ; 0x18 + c020: e58d0434 str r0, [sp, #1076] + c024: ebf5dfd5 bl 0xffd83f80 + c028: 080c1264 stmeqda ip, {r2, r5, r6, r9, ip} + c02c: e59d9434 ldr r9, [sp, #1076] + c030: e3c99003 bic r9, r9, #3 ; 0x3 + c034: e289000c add r0, r9, #12 ; 0xc + c038: e58d0434 str r0, [sp, #1076] + c03c: e2890000 add r0, r9, #0 ; 0x0 + c040: ebf5de34 bl 0xffd83918 + c044: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + c048: e1a06000 mov r6, r0 + c04c: e2890004 add r0, r9, #4 ; 0x4 + c050: ebf5de30 bl 0xffd83918 + c054: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + c058: e1a07000 mov r7, r0 + c05c: e2890008 add r0, r9, #8 ; 0x8 + c060: ebf5de2c bl 0xffd83918 + c064: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + c068: e1a08000 mov r8, r0 + c06c: ebf5dfc3 bl 0xffd83f80 + c070: 080c1266 stmeqda ip, {r1, r2, r5, r6, r9, ip} + c074: e1a00006 mov r0, r6 + c078: e58d0420 str r0, [sp, #1056] + c07c: ebf5dfbf bl 0xffd83f80 + c080: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + c084: e1a00007 mov r0, r7 + c088: e58d0424 str r0, [sp, #1060] + c08c: ebf5dfbb bl 0xffd83f80 + c090: 080c126a stmeqda ip, {r1, r3, r5, r6, r9, ip} + c094: e1a00008 mov r0, r8 + c098: e58d0428 str r0, [sp, #1064] + c09c: ebf5dfb7 bl 0xffd83f80 + c0a0: 080c126c stmeqda ip, {r2, r3, r5, r6, r9, ip} + c0a4: e59d9434 ldr r9, [sp, #1076] + c0a8: e3c99003 bic r9, r9, #3 ; 0x3 + c0ac: e2890010 add r0, r9, #16 ; 0x10 + c0b0: e58d0434 str r0, [sp, #1076] + c0b4: e2890000 add r0, r9, #0 ; 0x0 + c0b8: ebf5de16 bl 0xffd83918 + c0bc: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + c0c0: e1a07000 mov r7, r0 + c0c4: e2890004 add r0, r9, #4 ; 0x4 + c0c8: ebf5de12 bl 0xffd83918 + c0cc: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + c0d0: e1a08000 mov r8, r0 + c0d4: e2890008 add r0, r9, #8 ; 0x8 + c0d8: ebf5de0e bl 0xffd83918 + c0dc: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + c0e0: e58d0418 str r0, [sp, #1048] + c0e4: e289000c add r0, r9, #12 ; 0xc + c0e8: ebf5de0a bl 0xffd83918 + c0ec: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + c0f0: e58d041c str r0, [sp, #1052] + c0f4: ebf5dfa1 bl 0xffd83f80 + c0f8: 080c126e stmeqda ip, {r1, r2, r3, r5, r6, r9, ip} + c0fc: e59d9434 ldr r9, [sp, #1076] + c100: e3c99003 bic r9, r9, #3 ; 0x3 + c104: e2890004 add r0, r9, #4 ; 0x4 + c108: e58d0434 str r0, [sp, #1076] + c10c: e2890000 add r0, r9, #0 ; 0x0 + c110: ebf5de00 bl 0xffd83918 + c114: 080c1272 stmeqda ip, {r1, r4, r5, r6, r9, ip} + c118: e1a03000 mov r3, r0 + c11c: ebf5df97 bl 0xffd83f80 + c120: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + c124: e1a00003 mov r0, r3 + c128: e28cc020 add ip, ip, #32 ; 0x20 + c12c: eaf5dbe7 b 0xffd830d0 + c130: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + c134: 00000000 andeq r0, r0, r0 + c138: ebf5df90 bl 0xffd83f80 + c13c: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + c140: e2870000 add r0, r7, #0 ; 0x0 + c144: ebf5dd9c bl 0xffd837bc + c148: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + c14c: e1a04000 mov r4, r0 + c150: ebf5df8a bl 0xffd83f80 + c154: 080c0e8a stmeqda ip, {r1, r3, r7, r9, sl, fp} + c158: e3b030c7 movs r3, #199 ; 0xc7 + c15c: ebf5df87 bl 0xffd83f80 + c160: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + c164: e1a01003 mov r1, r3 + c168: e0133004 ands r3, r3, r4 + c16c: ebf5df83 bl 0xffd83f80 + c170: 080c0e8e stmeqda ip, {r1, r2, r3, r7, r9, sl, fp} + c174: e59d1418 ldr r1, [sp, #1048] + c178: e59d1418 ldr r1, [sp, #1048] + c17c: e2915001 adds r5, r1, #1 ; 0x1 + c180: ebf5df7e bl 0xffd83f80 + c184: 080c0e90 stmeqda ip, {r4, r7, r9, sl, fp} + c188: e1a00005 mov r0, r5 + c18c: e58d0424 str r0, [sp, #1060] + c190: ebf5df7a bl 0xffd83f80 + c194: 080c0e92 stmeqda ip, {r1, r4, r7, r9, sl, fp} + c198: e3b05040 movs r5, #64 ; 0x40 + c19c: ebf5df77 bl 0xffd83f80 + c1a0: 080c0e94 stmeqda ip, {r2, r4, r7, r9, sl, fp} + c1a4: e1a01005 mov r1, r5 + c1a8: e0955007 adds r5, r5, r7 + c1ac: ebf5df73 bl 0xffd83f80 + c1b0: 080c0e96 stmeqda ip, {r1, r2, r4, r7, r9, sl, fp} + c1b4: e1a00005 mov r0, r5 + c1b8: e58d0420 str r0, [sp, #1056] + c1bc: ebf5df6f bl 0xffd83f80 + c1c0: 080c0e98 stmeqda ip, {r3, r4, r7, r9, sl, fp} + c1c4: e3530000 cmp r3, #0 ; 0x0 + c1c8: ebf5df6c bl 0xffd83f80 + c1cc: 080c0e9a stmeqda ip, {r1, r3, r4, r7, r9, sl, fp} + c1d0: e28cc020 add ip, ip, #32 ; 0x20 + c1d4: 0a000004 beq 0xc1ec + c1d8: e1a00fac mov r0, ip, lsr #31 + c1dc: e08ff100 add pc, pc, r0, lsl #2 + c1e0: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + c1e4: ebf5db5a bl 0xffd82f54 + c1e8: ea000007 b 0xc20c + c1ec: ebf5df63 bl 0xffd83f80 + c1f0: 080c0e9c stmeqda ip, {r2, r3, r4, r7, r9, sl, fp} + c1f4: e28cc003 add ip, ip, #3 ; 0x3 + c1f8: e1a00fac mov r0, ip, lsr #31 + c1fc: e08ff100 add pc, pc, r0, lsl #2 + c200: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + c204: ebf5db52 bl 0xffd82f54 + c208: eaffff62 b 0xbf98 + c20c: ebf5df5b bl 0xffd83f80 + c210: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + c214: e59d1418 ldr r1, [sp, #1048] + c218: e3510002 cmp r1, #2 ; 0x2 + c21c: ebf5df57 bl 0xffd83f80 + c220: 080c0ea0 stmeqda ip, {r5, r7, r9, sl, fp} + c224: e28cc006 add ip, ip, #6 ; 0x6 + c228: 1a000004 bne 0xc240 + c22c: e1a00fac mov r0, ip, lsr #31 + c230: e08ff100 add pc, pc, r0, lsl #2 + c234: 080c0ed0 stmeqda ip, {r4, r6, r7, r9, sl, fp} + c238: ebf5db45 bl 0xffd82f54 + c23c: ea000075 b 0xc418 + c240: ebf5df4e bl 0xffd83f80 + c244: 080c0ea2 stmeqda ip, {r1, r5, r7, r9, sl, fp} + c248: e59d1418 ldr r1, [sp, #1048] + c24c: e3510002 cmp r1, #2 ; 0x2 + c250: ebf5df4a bl 0xffd83f80 + c254: 080c0ea4 stmeqda ip, {r2, r5, r7, r9, sl, fp} + c258: e28cc006 add ip, ip, #6 ; 0x6 + c25c: da000004 ble 0xc274 + c260: e1a00fac mov r0, ip, lsr #31 + c264: e08ff100 add pc, pc, r0, lsl #2 + c268: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + c26c: ebf5db38 bl 0xffd82f54 + c270: ea000014 b 0xc2c8 + c274: ebf5df41 bl 0xffd83f80 + c278: 080c0ea6 stmeqda ip, {r1, r2, r5, r7, r9, sl, fp} + c27c: e59d1418 ldr r1, [sp, #1048] + c280: e3510001 cmp r1, #1 ; 0x1 + c284: ebf5df3d bl 0xffd83f80 + c288: 080c0ea8 stmeqda ip, {r3, r5, r7, r9, sl, fp} + c28c: e28cc006 add ip, ip, #6 ; 0x6 + c290: 1a000004 bne 0xc2a8 + c294: e1a00fac mov r0, ip, lsr #31 + c298: e08ff100 add pc, pc, r0, lsl #2 + c29c: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + c2a0: ebf5db2b bl 0xffd82f54 + c2a4: ea00001c b 0xc31c + c2a8: ebf5df34 bl 0xffd83f80 + c2ac: 080c0eaa stmeqda ip, {r1, r3, r5, r7, r9, sl, fp} + c2b0: e28cc003 add ip, ip, #3 ; 0x3 + c2b4: e1a00fac mov r0, ip, lsr #31 + c2b8: e08ff100 add pc, pc, r0, lsl #2 + c2bc: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + c2c0: ebf5db23 bl 0xffd82f54 + c2c4: ea000b1b b 0xef38 + c2c8: ebf5df2c bl 0xffd83f80 + c2cc: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + c2d0: e59d1418 ldr r1, [sp, #1048] + c2d4: e3510003 cmp r1, #3 ; 0x3 + c2d8: ebf5df28 bl 0xffd83f80 + c2dc: 080c0eae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl, fp} + c2e0: e28cc006 add ip, ip, #6 ; 0x6 + c2e4: 1a000004 bne 0xc2fc + c2e8: e1a00fac mov r0, ip, lsr #31 + c2ec: e08ff100 add pc, pc, r0, lsl #2 + c2f0: 080c0ee8 stmeqda ip, {r3, r5, r6, r7, r9, sl, fp} + c2f4: ebf5db16 bl 0xffd82f54 + c2f8: ea000bd0 b 0xf240 + c2fc: ebf5df1f bl 0xffd83f80 + c300: 080c0eb0 stmeqda ip, {r4, r5, r7, r9, sl, fp} + c304: e28cc003 add ip, ip, #3 ; 0x3 + c308: e1a00fac mov r0, ip, lsr #31 + c30c: e08ff100 add pc, pc, r0, lsl #2 + c310: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + c314: ebf5db0e bl 0xffd82f54 + c318: ea000b06 b 0xef38 + c31c: ebf5df17 bl 0xffd83f80 + c320: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + c324: e3a00fb1 mov r0, #708 ; 0x2c4 + c328: e3800b03 orr r0, r0, #3072 ; 0xc00 + c32c: e3800703 orr r0, r0, #786432 ; 0xc0000 + c330: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c334: ebf5dd77 bl 0xffd83918 + c338: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + c33c: e1a03000 mov r3, r0 + c340: ebf5df0e bl 0xffd83f80 + c344: 080c0eb4 stmeqda ip, {r2, r4, r5, r7, r9, sl, fp} + c348: e59d0434 ldr r0, [sp, #1076] + c34c: e2800f02 add r0, r0, #8 ; 0x8 + c350: e1a01003 mov r1, r3 + c354: ebf5dc9c bl 0xffd835cc + c358: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + c35c: ebf5df07 bl 0xffd83f80 + c360: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + c364: e3a00fb2 mov r0, #712 ; 0x2c8 + c368: e3800b03 orr r0, r0, #3072 ; 0xc00 + c36c: e3800703 orr r0, r0, #786432 ; 0xc0000 + c370: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c374: ebf5dd67 bl 0xffd83918 + c378: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + c37c: e58d041c str r0, [sp, #1052] + c380: ebf5defe bl 0xffd83f80 + c384: 080c0eb8 stmeqda ip, {r3, r4, r5, r7, r9, sl, fp} + c388: e3a00fb3 mov r0, #716 ; 0x2cc + c38c: e3800b03 orr r0, r0, #3072 ; 0xc00 + c390: e3800703 orr r0, r0, #786432 ; 0xc0000 + c394: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c398: ebf5dd5e bl 0xffd83918 + c39c: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + c3a0: e1a05000 mov r5, r0 + c3a4: ebf5def5 bl 0xffd83f80 + c3a8: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + c3ac: e1a00005 mov r0, r5 + c3b0: e58d0428 str r0, [sp, #1064] + c3b4: ebf5def1 bl 0xffd83f80 + c3b8: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + c3bc: e1a01003 mov r1, r3 + c3c0: e2933004 adds r3, r3, #4 ; 0x4 + c3c4: ebf5deed bl 0xffd83f80 + c3c8: 080c0ebe stmeqda ip, {r1, r2, r3, r4, r5, r7, r9, sl, fp} + c3cc: e59d0434 ldr r0, [sp, #1076] + c3d0: e2800f03 add r0, r0, #12 ; 0xc + c3d4: e1a01003 mov r1, r3 + c3d8: ebf5dc7b bl 0xffd835cc + c3dc: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + c3e0: ebf5dee6 bl 0xffd83f80 + c3e4: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + c3e8: e1a01005 mov r1, r5 + c3ec: e2955002 adds r5, r5, #2 ; 0x2 + c3f0: ebf5dee2 bl 0xffd83f80 + c3f4: 080c0ec2 stmeqda ip, {r1, r6, r7, r9, sl, fp} + c3f8: e28cc023 add ip, ip, #35 ; 0x23 + c3fc: e1a00fac mov r0, ip, lsr #31 + c400: e08ff100 add pc, pc, r0, lsl #2 + c404: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + c408: ebf5dad1 bl 0xffd82f54 + c40c: ea000bc9 b 0xf338 + c410: 080c0ed0 stmeqda ip, {r4, r6, r7, r9, sl, fp} + c414: 00000000 andeq r0, r0, r0 + c418: ebf5ded8 bl 0xffd83f80 + c41c: 080c0ed0 stmeqda ip, {r4, r6, r7, r9, sl, fp} + c420: e3a00fb7 mov r0, #732 ; 0x2dc + c424: e3800b03 orr r0, r0, #3072 ; 0xc00 + c428: e3800703 orr r0, r0, #786432 ; 0xc0000 + c42c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c430: ebf5dd38 bl 0xffd83918 + c434: 080c0ed4 stmeqda ip, {r2, r4, r6, r7, r9, sl, fp} + c438: e1a03000 mov r3, r0 + c43c: ebf5decf bl 0xffd83f80 + c440: 080c0ed2 stmeqda ip, {r1, r4, r6, r7, r9, sl, fp} + c444: e59d0434 ldr r0, [sp, #1076] + c448: e2800f02 add r0, r0, #8 ; 0x8 + c44c: e1a01003 mov r1, r3 + c450: ebf5dc5d bl 0xffd835cc + c454: 080c0ed4 stmeqda ip, {r2, r4, r6, r7, r9, sl, fp} + c458: ebf5dec8 bl 0xffd83f80 + c45c: 080c0ed4 stmeqda ip, {r2, r4, r6, r7, r9, sl, fp} + c460: e3a00eee mov r0, #3808 ; 0xee0 + c464: e3800703 orr r0, r0, #786432 ; 0xc0000 + c468: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c46c: ebf5dd29 bl 0xffd83918 + c470: 080c0ed8 stmeqda ip, {r3, r4, r6, r7, r9, sl, fp} + c474: e58d041c str r0, [sp, #1052] + c478: ebf5dec0 bl 0xffd83f80 + c47c: 080c0ed6 stmeqda ip, {r1, r2, r4, r6, r7, r9, sl, fp} + c480: e3a00fb9 mov r0, #740 ; 0x2e4 + c484: e3800b03 orr r0, r0, #3072 ; 0xc00 + c488: e3800703 orr r0, r0, #786432 ; 0xc0000 + c48c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c490: ebf5dd20 bl 0xffd83918 + c494: 080c0eda stmeqda ip, {r1, r3, r4, r6, r7, r9, sl, fp} + c498: e1a05000 mov r5, r0 + c49c: ebf5deb7 bl 0xffd83f80 + c4a0: 080c0ed8 stmeqda ip, {r3, r4, r6, r7, r9, sl, fp} + c4a4: e28cc016 add ip, ip, #22 ; 0x16 + c4a8: e1a00fac mov r0, ip, lsr #31 + c4ac: e08ff100 add pc, pc, r0, lsl #2 + c4b0: 080c0f10 stmeqda ip, {r4, r8, r9, sl, fp} + c4b4: ebf5daa6 bl 0xffd82f54 + c4b8: ea000001 b 0xc4c4 + c4bc: 080c0f10 stmeqda ip, {r4, r8, r9, sl, fp} + c4c0: 00000000 andeq r0, r0, r0 + c4c4: ebf5dead bl 0xffd83f80 + c4c8: 080c0f10 stmeqda ip, {r4, r8, r9, sl, fp} + c4cc: e1a00005 mov r0, r5 + c4d0: e58d0428 str r0, [sp, #1064] + c4d4: ebf5dea9 bl 0xffd83f80 + c4d8: 080c0f12 stmeqda ip, {r1, r4, r8, r9, sl, fp} + c4dc: e1a01003 mov r1, r3 + c4e0: e293300b adds r3, r3, #11 ; 0xb + c4e4: ebf5dea5 bl 0xffd83f80 + c4e8: 080c0f14 stmeqda ip, {r2, r4, r8, r9, sl, fp} + c4ec: e59d0434 ldr r0, [sp, #1076] + c4f0: e2800f03 add r0, r0, #12 ; 0xc + c4f4: e1a01003 mov r1, r3 + c4f8: ebf5dc33 bl 0xffd835cc + c4fc: 080c0f16 stmeqda ip, {r1, r2, r4, r8, r9, sl, fp} + c500: ebf5de9e bl 0xffd83f80 + c504: 080c0f16 stmeqda ip, {r1, r2, r4, r8, r9, sl, fp} + c508: e1a01005 mov r1, r5 + c50c: e2955004 adds r5, r5, #4 ; 0x4 + c510: ebf5de9a bl 0xffd83f80 + c514: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + c518: e59d0434 ldr r0, [sp, #1076] + c51c: e2800f04 add r0, r0, #16 ; 0x10 + c520: e1a01005 mov r1, r5 + c524: ebf5dc28 bl 0xffd835cc + c528: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + c52c: ebf5de93 bl 0xffd83f80 + c530: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + c534: e59d0434 ldr r0, [sp, #1076] + c538: e2800f01 add r0, r0, #4 ; 0x4 + c53c: ebf5dcf5 bl 0xffd83918 + c540: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + c544: e1a03000 mov r3, r0 + c548: ebf5de8c bl 0xffd83f80 + c54c: 080c0f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp} + c550: e283000a add r0, r3, #10 ; 0xa + c554: ebf5dc98 bl 0xffd837bc + c558: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + c55c: e1a03000 mov r3, r0 + c560: ebf5de86 bl 0xffd83f80 + c564: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + c568: e59d0434 ldr r0, [sp, #1076] + c56c: e2800f00 add r0, r0, #0 ; 0x0 + c570: e1a01003 mov r1, r3 + c574: ebf5dc14 bl 0xffd835cc + c578: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + c57c: ebf5de7f bl 0xffd83f80 + c580: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + c584: e1a01004 mov r1, r4 + c588: e2945000 adds r5, r4, #0 ; 0x0 + c58c: ebf5de7b bl 0xffd83f80 + c590: 080c0f22 stmeqda ip, {r1, r5, r8, r9, sl, fp} + c594: e3b03080 movs r3, #128 ; 0x80 + c598: ebf5de78 bl 0xffd83f80 + c59c: 080c0f24 stmeqda ip, {r2, r5, r8, r9, sl, fp} + c5a0: e1a01003 mov r1, r3 + c5a4: e0133005 ands r3, r3, r5 + c5a8: ebf5de74 bl 0xffd83f80 + c5ac: 080c0f26 stmeqda ip, {r1, r2, r5, r8, r9, sl, fp} + c5b0: e3530000 cmp r3, #0 ; 0x0 + c5b4: ebf5de71 bl 0xffd83f80 + c5b8: 080c0f28 stmeqda ip, {r3, r5, r8, r9, sl, fp} + c5bc: e28cc02e add ip, ip, #46 ; 0x2e + c5c0: 1a000004 bne 0xc5d8 + c5c4: e1a00fac mov r0, ip, lsr #31 + c5c8: e08ff100 add pc, pc, r0, lsl #2 + c5cc: 080c1008 stmeqda ip, {r3, ip} + c5d0: ebf5da5f bl 0xffd82f54 + c5d4: ea00005b b 0xc748 + c5d8: ebf5de68 bl 0xffd83f80 + c5dc: 080c0f2a stmeqda ip, {r1, r3, r5, r8, r9, sl, fp} + c5e0: e3b06040 movs r6, #64 ; 0x40 + c5e4: ebf5de65 bl 0xffd83f80 + c5e8: 080c0f2c stmeqda ip, {r2, r3, r5, r8, r9, sl, fp} + c5ec: e1a01006 mov r1, r6 + c5f0: e2963000 adds r3, r6, #0 ; 0x0 + c5f4: ebf5de61 bl 0xffd83f80 + c5f8: 080c0f2e stmeqda ip, {r1, r2, r3, r5, r8, r9, sl, fp} + c5fc: e1a01003 mov r1, r3 + c600: e0133005 ands r3, r3, r5 + c604: ebf5de5d bl 0xffd83f80 + c608: 080c0f30 stmeqda ip, {r4, r5, r8, r9, sl, fp} + c60c: e1b03c03 movs r3, r3, lsl #24 + c610: ebf5de5a bl 0xffd83f80 + c614: 080c0f32 stmeqda ip, {r1, r4, r5, r8, r9, sl, fp} + c618: e1b08c23 movs r8, r3, lsr #24 + c61c: ebf5de57 bl 0xffd83f80 + c620: 080c0f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp} + c624: e59d1418 ldr r1, [sp, #1048] + c628: e59d1418 ldr r1, [sp, #1048] + c62c: e2914001 adds r4, r1, #1 ; 0x1 + c630: ebf5de52 bl 0xffd83f80 + c634: 080c0f36 stmeqda ip, {r1, r2, r4, r5, r8, r9, sl, fp} + c638: e1a00004 mov r0, r4 + c63c: e58d0424 str r0, [sp, #1060] + c640: ebf5de4e bl 0xffd83f80 + c644: 080c0f38 stmeqda ip, {r3, r4, r5, r8, r9, sl, fp} + c648: e3b05040 movs r5, #64 ; 0x40 + c64c: ebf5de4b bl 0xffd83f80 + c650: 080c0f3a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, fp} + c654: e1a01005 mov r1, r5 + c658: e0955007 adds r5, r5, r7 + c65c: ebf5de47 bl 0xffd83f80 + c660: 080c0f3c stmeqda ip, {r2, r3, r4, r5, r8, r9, sl, fp} + c664: e1a00005 mov r0, r5 + c668: e58d0420 str r0, [sp, #1056] + c66c: ebf5de43 bl 0xffd83f80 + c670: 080c0f3e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, fp} + c674: e3580000 cmp r8, #0 ; 0x0 + c678: ebf5de40 bl 0xffd83f80 + c67c: 080c0f40 stmeqda ip, {r6, r8, r9, sl, fp} + c680: e28cc024 add ip, ip, #36 ; 0x24 + c684: 0a000004 beq 0xc69c + c688: e1a00fac mov r0, ip, lsr #31 + c68c: e08ff100 add pc, pc, r0, lsl #2 + c690: 080c102c stmeqda ip, {r2, r3, r5, ip} + c694: ebf5da2e bl 0xffd82f54 + c698: ea0001c4 b 0xcdb0 + c69c: ebf5de37 bl 0xffd83f80 + c6a0: 080c0f42 stmeqda ip, {r1, r6, r8, r9, sl, fp} + c6a4: e3b03003 movs r3, #3 ; 0x3 + c6a8: ebf5de34 bl 0xffd83f80 + c6ac: 080c0f44 stmeqda ip, {r2, r6, r8, r9, sl, fp} + c6b0: e2870000 add r0, r7, #0 ; 0x0 + c6b4: e1a01003 mov r1, r3 + c6b8: ebf5db84 bl 0xffd834d0 + c6bc: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + c6c0: ebf5de2e bl 0xffd83f80 + c6c4: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + c6c8: e287001d add r0, r7, #29 ; 0x1d + c6cc: e1a01003 mov r1, r3 + c6d0: ebf5db7e bl 0xffd834d0 + c6d4: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + c6d8: ebf5de28 bl 0xffd83f80 + c6dc: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + c6e0: e1a01007 mov r1, r7 + c6e4: e2973000 adds r3, r7, #0 ; 0x0 + c6e8: ebf5de24 bl 0xffd83f80 + c6ec: 080c0f4a stmeqda ip, {r1, r3, r6, r8, r9, sl, fp} + c6f0: e59d0434 ldr r0, [sp, #1076] + c6f4: e2800f05 add r0, r0, #20 ; 0x14 + c6f8: e1a01006 mov r1, r6 + c6fc: ebf5dbb2 bl 0xffd835cc + c700: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + c704: ebf5de1d bl 0xffd83f80 + c708: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + c70c: ebf5de1b bl 0xffd83f80 + c710: 080c0f4e stmeqda ip, {r1, r2, r3, r6, r8, r9, sl, fp} + c714: e3a00051 mov r0, #81 ; 0x51 + c718: e3800c0f orr r0, r0, #3840 ; 0xf00 + c71c: e3800703 orr r0, r0, #786432 ; 0xc0000 + c720: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c724: e58d0438 str r0, [sp, #1080] + c728: e28cc018 add ip, ip, #24 ; 0x18 + c72c: e1a00fac mov r0, ip, lsr #31 + c730: e08ff100 add pc, pc, r0, lsl #2 + c734: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + c738: ebf5da05 bl 0xffd82f54 + c73c: ea0008e3 b 0xead0 + c740: 080c1008 stmeqda ip, {r3, ip} + c744: 00000000 andeq r0, r0, r0 + c748: ebf5de0c bl 0xffd83f80 + c74c: 080c1008 stmeqda ip, {r3, ip} + c750: e3b03004 movs r3, #4 ; 0x4 + c754: ebf5de09 bl 0xffd83f80 + c758: 080c100a stmeqda ip, {r1, r3, ip} + c75c: e1a01003 mov r1, r3 + c760: e0133005 ands r3, r3, r5 + c764: ebf5de05 bl 0xffd83f80 + c768: 080c100c stmeqda ip, {r2, r3, ip} + c76c: e3530000 cmp r3, #0 ; 0x0 + c770: ebf5de02 bl 0xffd83f80 + c774: 080c100e stmeqda ip, {r1, r2, r3, ip} + c778: e28cc00c add ip, ip, #12 ; 0xc + c77c: 1a000004 bne 0xc794 + c780: e1a00fac mov r0, ip, lsr #31 + c784: e08ff100 add pc, pc, r0, lsl #2 + c788: 080c103a stmeqda ip, {r1, r3, r4, r5, ip} + c78c: ebf5d9f0 bl 0xffd82f54 + c790: ea000058 b 0xc8f8 + c794: ebf5ddf9 bl 0xffd83f80 + c798: 080c1010 stmeqda ip, {r4, ip} + c79c: e287000d add r0, r7, #13 ; 0xd + c7a0: ebf5dc05 bl 0xffd837bc + c7a4: 080c1014 stmeqda ip, {r2, r4, ip} + c7a8: e1a03000 mov r3, r0 + c7ac: ebf5ddf3 bl 0xffd83f80 + c7b0: 080c1012 stmeqda ip, {r1, r4, ip} + c7b4: e1a01003 mov r1, r3 + c7b8: e2533001 subs r3, r3, #1 ; 0x1 + c7bc: ebf5ddef bl 0xffd83f80 + c7c0: 080c1014 stmeqda ip, {r2, r4, ip} + c7c4: e287000d add r0, r7, #13 ; 0xd + c7c8: e1a01003 mov r1, r3 + c7cc: ebf5db3f bl 0xffd834d0 + c7d0: 080c1016 stmeqda ip, {r1, r2, r4, ip} + c7d4: ebf5dde9 bl 0xffd83f80 + c7d8: 080c1016 stmeqda ip, {r1, r2, r4, ip} + c7dc: e3b050ff movs r5, #255 ; 0xff + c7e0: ebf5dde6 bl 0xffd83f80 + c7e4: 080c1018 stmeqda ip, {r3, r4, ip} + c7e8: e1a01003 mov r1, r3 + c7ec: e0133005 ands r3, r3, r5 + c7f0: ebf5dde2 bl 0xffd83f80 + c7f4: 080c101a stmeqda ip, {r1, r3, r4, ip} + c7f8: e1b03c03 movs r3, r3, lsl #24 + c7fc: ebf5dddf bl 0xffd83f80 + c800: 080c101c stmeqda ip, {r2, r3, r4, ip} + c804: e59d1418 ldr r1, [sp, #1048] + c808: e59d1418 ldr r1, [sp, #1048] + c80c: e2914001 adds r4, r1, #1 ; 0x1 + c810: ebf5ddda bl 0xffd83f80 + c814: 080c101e stmeqda ip, {r1, r2, r3, r4, ip} + c818: e1a00004 mov r0, r4 + c81c: e58d0424 str r0, [sp, #1060] + c820: ebf5ddd6 bl 0xffd83f80 + c824: 080c1020 stmeqda ip, {r5, ip} + c828: e3b05040 movs r5, #64 ; 0x40 + c82c: ebf5ddd3 bl 0xffd83f80 + c830: 080c1022 stmeqda ip, {r1, r5, ip} + c834: e1a01005 mov r1, r5 + c838: e0955007 adds r5, r5, r7 + c83c: ebf5ddcf bl 0xffd83f80 + c840: 080c1024 stmeqda ip, {r2, r5, ip} + c844: e1a00005 mov r0, r5 + c848: e58d0420 str r0, [sp, #1056] + c84c: ebf5ddcb bl 0xffd83f80 + c850: 080c1026 stmeqda ip, {r1, r2, r5, ip} + c854: e3530000 cmp r3, #0 ; 0x0 + c858: ebf5ddc8 bl 0xffd83f80 + c85c: 080c1028 stmeqda ip, {r3, r5, ip} + c860: e28cc02a add ip, ip, #42 ; 0x2a + c864: ca000004 bgt 0xc87c + c868: e1a00fac mov r0, ip, lsr #31 + c86c: e08ff100 add pc, pc, r0, lsl #2 + c870: 080c102c stmeqda ip, {r2, r3, r5, ip} + c874: ebf5d9b6 bl 0xffd82f54 + c878: ea000007 b 0xc89c + c87c: ebf5ddbf bl 0xffd83f80 + c880: 080c102a stmeqda ip, {r1, r3, r5, ip} + c884: e28cc003 add ip, ip, #3 ; 0x3 + c888: e1a00fac mov r0, ip, lsr #31 + c88c: e08ff100 add pc, pc, r0, lsl #2 + c890: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + c894: ebf5d9ae bl 0xffd82f54 + c898: ea00024e b 0xd1d8 + c89c: ebf5ddb7 bl 0xffd83f80 + c8a0: 080c102c stmeqda ip, {r2, r3, r5, ip} + c8a4: e59de418 ldr lr, [sp, #1048] + c8a8: e1b03c0e movs r3, lr, lsl #24 + c8ac: ebf5ddb3 bl 0xffd83f80 + c8b0: 080c102e stmeqda ip, {r1, r2, r3, r5, ip} + c8b4: e1b03c23 movs r3, r3, lsr #24 + c8b8: ebf5ddb0 bl 0xffd83f80 + c8bc: 080c1030 stmeqda ip, {r4, r5, ip} + c8c0: ebf5ddae bl 0xffd83f80 + c8c4: 080c1032 stmeqda ip, {r1, r4, r5, ip} + c8c8: e3a00035 mov r0, #53 ; 0x35 + c8cc: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + c8d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + c8d4: e58d0438 str r0, [sp, #1080] + c8d8: e28cc00c add ip, ip, #12 ; 0xc + c8dc: e1a00fac mov r0, ip, lsr #31 + c8e0: e08ff100 add pc, pc, r0, lsl #2 + c8e4: 080c0da0 stmeqda ip, {r5, r7, r8, sl, fp} + c8e8: ebf5d999 bl 0xffd82f54 + c8ec: ea000146 b 0xce0c + c8f0: 080c103a stmeqda ip, {r1, r3, r4, r5, ip} + c8f4: 00000000 andeq r0, r0, r0 + c8f8: ebf5dda0 bl 0xffd83f80 + c8fc: 080c103a stmeqda ip, {r1, r3, r4, r5, ip} + c900: e3b03040 movs r3, #64 ; 0x40 + c904: ebf5dd9d bl 0xffd83f80 + c908: 080c103c stmeqda ip, {r2, r3, r4, r5, ip} + c90c: e1a01003 mov r1, r3 + c910: e0133004 ands r3, r3, r4 + c914: ebf5dd99 bl 0xffd83f80 + c918: 080c103e stmeqda ip, {r1, r2, r3, r4, r5, ip} + c91c: e59d1418 ldr r1, [sp, #1048] + c920: e59d1418 ldr r1, [sp, #1048] + c924: e2915001 adds r5, r1, #1 ; 0x1 + c928: ebf5dd94 bl 0xffd83f80 + c92c: 080c1040 stmeqda ip, {r6, ip} + c930: e1a00005 mov r0, r5 + c934: e58d0424 str r0, [sp, #1060] + c938: ebf5dd90 bl 0xffd83f80 + c93c: 080c1042 stmeqda ip, {r1, r6, ip} + c940: e3b05040 movs r5, #64 ; 0x40 + c944: ebf5dd8d bl 0xffd83f80 + c948: 080c1044 stmeqda ip, {r2, r6, ip} + c94c: e1a01005 mov r1, r5 + c950: e0955007 adds r5, r5, r7 + c954: ebf5dd89 bl 0xffd83f80 + c958: 080c1046 stmeqda ip, {r1, r2, r6, ip} + c95c: e1a00005 mov r0, r5 + c960: e58d0420 str r0, [sp, #1056] + c964: ebf5dd85 bl 0xffd83f80 + c968: 080c1048 stmeqda ip, {r3, r6, ip} + c96c: e3530000 cmp r3, #0 ; 0x0 + c970: ebf5dd82 bl 0xffd83f80 + c974: 080c104a stmeqda ip, {r1, r3, r6, ip} + c978: e28cc01b add ip, ip, #27 ; 0x1b + c97c: 1a000004 bne 0xc994 + c980: e1a00fac mov r0, ip, lsr #31 + c984: e08ff100 add pc, pc, r0, lsl #2 + c988: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + c98c: ebf5d970 bl 0xffd82f54 + c990: ea00005c b 0xcb08 + c994: ebf5dd79 bl 0xffd83f80 + c998: 080c104c stmeqda ip, {r2, r3, r6, ip} + c99c: e3b03003 movs r3, #3 ; 0x3 + c9a0: ebf5dd76 bl 0xffd83f80 + c9a4: 080c104e stmeqda ip, {r1, r2, r3, r6, ip} + c9a8: e1a01003 mov r1, r3 + c9ac: e0133004 ands r3, r3, r4 + c9b0: ebf5dd72 bl 0xffd83f80 + c9b4: 080c1050 stmeqda ip, {r4, r6, ip} + c9b8: e3530000 cmp r3, #0 ; 0x0 + c9bc: ebf5dd6f bl 0xffd83f80 + c9c0: 080c1052 stmeqda ip, {r1, r4, r6, ip} + c9c4: e28cc00c add ip, ip, #12 ; 0xc + c9c8: 1a000004 bne 0xc9e0 + c9cc: e1a00fac mov r0, ip, lsr #31 + c9d0: e08ff100 add pc, pc, r0, lsl #2 + c9d4: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + c9d8: ebf5d95d bl 0xffd82f54 + c9dc: ea000049 b 0xcb08 + c9e0: ebf5dd66 bl 0xffd83f80 + c9e4: 080c1054 stmeqda ip, {r2, r4, r6, ip} + c9e8: e3b030fc movs r3, #252 ; 0xfc + c9ec: ebf5dd63 bl 0xffd83f80 + c9f0: 080c1056 stmeqda ip, {r1, r2, r4, r6, ip} + c9f4: e1a01003 mov r1, r3 + c9f8: e0133004 ands r3, r3, r4 + c9fc: ebf5dd5f bl 0xffd83f80 + ca00: 080c1058 stmeqda ip, {r3, r4, r6, ip} + ca04: e3b05000 movs r5, #0 ; 0x0 + ca08: ebf5dd5c bl 0xffd83f80 + ca0c: 080c105a stmeqda ip, {r1, r3, r4, r6, ip} + ca10: e2870000 add r0, r7, #0 ; 0x0 + ca14: e1a01003 mov r1, r3 + ca18: ebf5daac bl 0xffd834d0 + ca1c: 080c105c stmeqda ip, {r2, r3, r4, r6, ip} + ca20: ebf5dd56 bl 0xffd83f80 + ca24: 080c105c stmeqda ip, {r2, r3, r4, r6, ip} + ca28: e2870007 add r0, r7, #7 ; 0x7 + ca2c: ebf5db62 bl 0xffd837bc + ca30: 080c1060 stmeqda ip, {r5, r6, ip} + ca34: e1a04000 mov r4, r0 + ca38: ebf5dd50 bl 0xffd83f80 + ca3c: 080c105e stmeqda ip, {r1, r2, r3, r4, r6, ip} + ca40: e287000b add r0, r7, #11 ; 0xb + ca44: e1a01004 mov r1, r4 + ca48: ebf5daa0 bl 0xffd834d0 + ca4c: 080c1060 stmeqda ip, {r5, r6, ip} + ca50: ebf5dd4a bl 0xffd83f80 + ca54: 080c1060 stmeqda ip, {r5, r6, ip} + ca58: e3b030ff movs r3, #255 ; 0xff + ca5c: ebf5dd47 bl 0xffd83f80 + ca60: 080c1062 stmeqda ip, {r1, r5, r6, ip} + ca64: e1a01003 mov r1, r3 + ca68: e0133004 ands r3, r3, r4 + ca6c: ebf5dd43 bl 0xffd83f80 + ca70: 080c1064 stmeqda ip, {r2, r5, r6, ip} + ca74: e3530000 cmp r3, #0 ; 0x0 + ca78: ebf5dd40 bl 0xffd83f80 + ca7c: 080c1066 stmeqda ip, {r1, r2, r5, r6, ip} + ca80: e28cc022 add ip, ip, #34 ; 0x22 + ca84: 1a000004 bne 0xca9c + ca88: e1a00fac mov r0, ip, lsr #31 + ca8c: e08ff100 add pc, pc, r0, lsl #2 + ca90: 080c10a4 stmeqda ip, {r2, r5, r7, ip} + ca94: ebf5d92e bl 0xffd82f54 + ca98: ea000061 b 0xcc24 + ca9c: ebf5dd37 bl 0xffd83f80 + caa0: 080c1068 stmeqda ip, {r3, r5, r6, ip} + caa4: e3b03001 movs r3, #1 ; 0x1 + caa8: ebf5dd34 bl 0xffd83f80 + caac: 080c106a stmeqda ip, {r1, r3, r5, r6, ip} + cab0: e287001d add r0, r7, #29 ; 0x1d + cab4: ebf5db40 bl 0xffd837bc + cab8: 080c106e stmeqda ip, {r1, r2, r3, r5, r6, ip} + cabc: e1a05000 mov r5, r0 + cac0: ebf5dd2e bl 0xffd83f80 + cac4: 080c106c stmeqda ip, {r2, r3, r5, r6, ip} + cac8: e1a01003 mov r1, r3 + cacc: e1933005 orrs r3, r3, r5 + cad0: ebf5dd2a bl 0xffd83f80 + cad4: 080c106e stmeqda ip, {r1, r2, r3, r5, r6, ip} + cad8: e287001d add r0, r7, #29 ; 0x1d + cadc: e1a01003 mov r1, r3 + cae0: ebf5da7a bl 0xffd834d0 + cae4: 080c1070 stmeqda ip, {r4, r5, r6, ip} + cae8: ebf5dd24 bl 0xffd83f80 + caec: 080c1070 stmeqda ip, {r4, r5, r6, ip} + caf0: e28cc012 add ip, ip, #18 ; 0x12 + caf4: e1a00fac mov r0, ip, lsr #31 + caf8: e08ff100 add pc, pc, r0, lsl #2 + cafc: 080c1152 stmeqda ip, {r1, r4, r6, r8, ip} + cb00: ebf5d913 bl 0xffd82f54 + cb04: ea0006de b 0xe684 + cb08: ebf5dd1c bl 0xffd83f80 + cb0c: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + cb10: e287000b add r0, r7, #11 ; 0xb + cb14: ebf5db28 bl 0xffd837bc + cb18: 080c1076 stmeqda ip, {r1, r2, r4, r5, r6, ip} + cb1c: e1a03000 mov r3, r0 + cb20: ebf5dd16 bl 0xffd83f80 + cb24: 080c1074 stmeqda ip, {r2, r4, r5, r6, ip} + cb28: e3530000 cmp r3, #0 ; 0x0 + cb2c: ebf5dd13 bl 0xffd83f80 + cb30: 080c1076 stmeqda ip, {r1, r2, r4, r5, r6, ip} + cb34: e28cc00b add ip, ip, #11 ; 0xb + cb38: 0a000004 beq 0xcb50 + cb3c: e1a00fac mov r0, ip, lsr #31 + cb40: e08ff100 add pc, pc, r0, lsl #2 + cb44: 080c1160 stmeqda ip, {r5, r6, r8, ip} + cb48: ebf5d901 bl 0xffd82f54 + cb4c: ea0006ed b 0xe708 + cb50: ebf5dd0a bl 0xffd83f80 + cb54: 080c1078 stmeqda ip, {r3, r4, r5, r6, ip} + cb58: e59d1418 ldr r1, [sp, #1048] + cb5c: e3510003 cmp r1, #3 ; 0x3 + cb60: ebf5dd06 bl 0xffd83f80 + cb64: 080c107a stmeqda ip, {r1, r3, r4, r5, r6, ip} + cb68: e28cc006 add ip, ip, #6 ; 0x6 + cb6c: 0a000004 beq 0xcb84 + cb70: e1a00fac mov r0, ip, lsr #31 + cb74: e08ff100 add pc, pc, r0, lsl #2 + cb78: 080c1084 stmeqda ip, {r2, r7, ip} + cb7c: ebf5d8f4 bl 0xffd82f54 + cb80: ea000013 b 0xcbd4 + cb84: ebf5dcfd bl 0xffd83f80 + cb88: 080c107c stmeqda ip, {r2, r3, r4, r5, r6, ip} + cb8c: e3b03001 movs r3, #1 ; 0x1 + cb90: ebf5dcfa bl 0xffd83f80 + cb94: 080c107e stmeqda ip, {r1, r2, r3, r4, r5, r6, ip} + cb98: e287001d add r0, r7, #29 ; 0x1d + cb9c: ebf5db06 bl 0xffd837bc + cba0: 080c1082 stmeqda ip, {r1, r7, ip} + cba4: e1a04000 mov r4, r0 + cba8: ebf5dcf4 bl 0xffd83f80 + cbac: 080c1080 stmeqda ip, {r7, ip} + cbb0: e1a01003 mov r1, r3 + cbb4: e1933004 orrs r3, r3, r4 + cbb8: ebf5dcf0 bl 0xffd83f80 + cbbc: 080c1082 stmeqda ip, {r1, r7, ip} + cbc0: e287001d add r0, r7, #29 ; 0x1d + cbc4: e1a01003 mov r1, r3 + cbc8: ebf5da40 bl 0xffd834d0 + cbcc: 080c1084 stmeqda ip, {r2, r7, ip} + cbd0: e28cc00f add ip, ip, #15 ; 0xf + cbd4: ebf5dce9 bl 0xffd83f80 + cbd8: 080c1084 stmeqda ip, {r2, r7, ip} + cbdc: e1a01007 mov r1, r7 + cbe0: e2973000 adds r3, r7, #0 ; 0x0 + cbe4: ebf5dce5 bl 0xffd83f80 + cbe8: 080c1086 stmeqda ip, {r1, r2, r7, ip} + cbec: ebf5dce3 bl 0xffd83f80 + cbf0: 080c1088 stmeqda ip, {r3, r7, ip} + cbf4: e3a0008b mov r0, #139 ; 0x8b + cbf8: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + cbfc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + cc00: e58d0438 str r0, [sp, #1080] + cc04: e28cc009 add ip, ip, #9 ; 0x9 + cc08: e1a00fac mov r0, ip, lsr #31 + cc0c: e08ff100 add pc, pc, r0, lsl #2 + cc10: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + cc14: ebf5d8ce bl 0xffd82f54 + cc18: ea0007ac b 0xead0 + cc1c: 080c10a4 stmeqda ip, {r2, r5, r7, ip} + cc20: 00000000 andeq r0, r0, r0 + cc24: ebf5dcd5 bl 0xffd83f80 + cc28: 080c10a4 stmeqda ip, {r2, r5, r7, ip} + cc2c: e287000c add r0, r7, #12 ; 0xc + cc30: ebf5dae1 bl 0xffd837bc + cc34: 080c10a8 stmeqda ip, {r3, r5, r7, ip} + cc38: e1a05000 mov r5, r0 + cc3c: ebf5dccf bl 0xffd83f80 + cc40: 080c10a6 stmeqda ip, {r1, r2, r5, r7, ip} + cc44: e287000a add r0, r7, #10 ; 0xa + cc48: ebf5dadb bl 0xffd837bc + cc4c: 080c10aa stmeqda ip, {r1, r3, r5, r7, ip} + cc50: e1a04000 mov r4, r0 + cc54: ebf5dcc9 bl 0xffd83f80 + cc58: 080c10a8 stmeqda ip, {r3, r5, r7, ip} + cc5c: e1a01005 mov r1, r5 + cc60: e2953000 adds r3, r5, #0 ; 0x0 + cc64: ebf5dcc5 bl 0xffd83f80 + cc68: 080c10aa stmeqda ip, {r1, r3, r5, r7, ip} + cc6c: e1a01003 mov r1, r3 + cc70: e0130493 muls r3, r3, r4 + cc74: ebf5dcc1 bl 0xffd83f80 + cc78: 080c10ac stmeqda ip, {r2, r3, r5, r7, ip} + cc7c: e1a01003 mov r1, r3 + cc80: e29330ff adds r3, r3, #255 ; 0xff + cc84: ebf5dcbd bl 0xffd83f80 + cc88: 080c10ae stmeqda ip, {r1, r2, r3, r5, r7, ip} + cc8c: e1b03443 movs r3, r3, asr #8 + cc90: ebf5dcba bl 0xffd83f80 + cc94: 080c10b0 stmeqda ip, {r4, r5, r7, ip} + cc98: e3b04000 movs r4, #0 ; 0x0 + cc9c: ebf5dcb7 bl 0xffd83f80 + cca0: 080c10b2 stmeqda ip, {r1, r4, r5, r7, ip} + cca4: e2870009 add r0, r7, #9 ; 0x9 + cca8: e1a01003 mov r1, r3 + ccac: ebf5da07 bl 0xffd834d0 + ccb0: 080c10b4 stmeqda ip, {r2, r4, r5, r7, ip} + ccb4: ebf5dcb1 bl 0xffd83f80 + ccb8: 080c10b4 stmeqda ip, {r2, r4, r5, r7, ip} + ccbc: e1b03c03 movs r3, r3, lsl #24 + ccc0: ebf5dcae bl 0xffd83f80 + ccc4: 080c10b6 stmeqda ip, {r1, r2, r4, r5, r7, ip} + ccc8: e3530000 cmp r3, #0 ; 0x0 + cccc: ebf5dcab bl 0xffd83f80 + ccd0: 080c10b8 stmeqda ip, {r3, r4, r5, r7, ip} + ccd4: e28cc026 add ip, ip, #38 ; 0x26 + ccd8: 1a000004 bne 0xccf0 + ccdc: e1a00fac mov r0, ip, lsr #31 + cce0: e08ff100 add pc, pc, r0, lsl #2 + cce4: 080c102c stmeqda ip, {r2, r3, r5, ip} + cce8: ebf5d899 bl 0xffd82f54 + ccec: ea00002f b 0xcdb0 + ccf0: ebf5dca2 bl 0xffd83f80 + ccf4: 080c10ba stmeqda ip, {r1, r3, r4, r5, r7, ip} + ccf8: e3b03004 movs r3, #4 ; 0x4 + ccfc: ebf5dc9f bl 0xffd83f80 + cd00: 080c10bc stmeqda ip, {r2, r3, r4, r5, r7, ip} + cd04: e2870000 add r0, r7, #0 ; 0x0 + cd08: ebf5daab bl 0xffd837bc + cd0c: 080c10c0 stmeqda ip, {r6, r7, ip} + cd10: e1a05000 mov r5, r0 + cd14: ebf5dc99 bl 0xffd83f80 + cd18: 080c10be stmeqda ip, {r1, r2, r3, r4, r5, r7, ip} + cd1c: e1a01003 mov r1, r3 + cd20: e1933005 orrs r3, r3, r5 + cd24: ebf5dc95 bl 0xffd83f80 + cd28: 080c10c0 stmeqda ip, {r6, r7, ip} + cd2c: e2870000 add r0, r7, #0 ; 0x0 + cd30: e1a01003 mov r1, r3 + cd34: ebf5d9e5 bl 0xffd834d0 + cd38: 080c10c2 stmeqda ip, {r1, r6, r7, ip} + cd3c: ebf5dc8f bl 0xffd83f80 + cd40: 080c10c2 stmeqda ip, {r1, r6, r7, ip} + cd44: e3b03001 movs r3, #1 ; 0x1 + cd48: ebf5dc8c bl 0xffd83f80 + cd4c: 080c10c4 stmeqda ip, {r2, r6, r7, ip} + cd50: e287001d add r0, r7, #29 ; 0x1d + cd54: ebf5da98 bl 0xffd837bc + cd58: 080c10c8 stmeqda ip, {r3, r6, r7, ip} + cd5c: e1a04000 mov r4, r0 + cd60: ebf5dc86 bl 0xffd83f80 + cd64: 080c10c6 stmeqda ip, {r1, r2, r6, r7, ip} + cd68: e1a01003 mov r1, r3 + cd6c: e1933004 orrs r3, r3, r4 + cd70: ebf5dc82 bl 0xffd83f80 + cd74: 080c10c8 stmeqda ip, {r3, r6, r7, ip} + cd78: e287001d add r0, r7, #29 ; 0x1d + cd7c: e1a01003 mov r1, r3 + cd80: ebf5d9d2 bl 0xffd834d0 + cd84: 080c10ca stmeqda ip, {r1, r3, r6, r7, ip} + cd88: ebf5dc7c bl 0xffd83f80 + cd8c: 080c10ca stmeqda ip, {r1, r3, r6, r7, ip} + cd90: e28cc021 add ip, ip, #33 ; 0x21 + cd94: e1a00fac mov r0, ip, lsr #31 + cd98: e08ff100 add pc, pc, r0, lsl #2 + cd9c: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + cda0: ebf5d86b bl 0xffd82f54 + cda4: ea00010b b 0xd1d8 + cda8: 080c102c stmeqda ip, {r2, r3, r5, ip} + cdac: 00000000 andeq r0, r0, r0 + cdb0: ebf5dc72 bl 0xffd83f80 + cdb4: 080c102c stmeqda ip, {r2, r3, r5, ip} + cdb8: e59de418 ldr lr, [sp, #1048] + cdbc: e1b03c0e movs r3, lr, lsl #24 + cdc0: ebf5dc6e bl 0xffd83f80 + cdc4: 080c102e stmeqda ip, {r1, r2, r3, r5, ip} + cdc8: e1b03c23 movs r3, r3, lsr #24 + cdcc: ebf5dc6b bl 0xffd83f80 + cdd0: 080c1030 stmeqda ip, {r4, r5, ip} + cdd4: ebf5dc69 bl 0xffd83f80 + cdd8: 080c1032 stmeqda ip, {r1, r4, r5, ip} + cddc: e3a00035 mov r0, #53 ; 0x35 + cde0: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + cde4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + cde8: e58d0438 str r0, [sp, #1080] + cdec: e28cc00c add ip, ip, #12 ; 0xc + cdf0: e1a00fac mov r0, ip, lsr #31 + cdf4: e08ff100 add pc, pc, r0, lsl #2 + cdf8: 080c0da0 stmeqda ip, {r5, r7, r8, sl, fp} + cdfc: ebf5d854 bl 0xffd82f54 + ce00: ea000001 b 0xce0c + ce04: 080c0da0 stmeqda ip, {r5, r7, r8, sl, fp} + ce08: 00000000 andeq r0, r0, r0 + ce0c: ebf5dc5b bl 0xffd83f80 + ce10: 080c0da0 stmeqda ip, {r5, r7, r8, sl, fp} + ce14: e1b03c03 movs r3, r3, lsl #24 + ce18: ebf5dc58 bl 0xffd83f80 + ce1c: 080c0da2 stmeqda ip, {r1, r5, r7, r8, sl, fp} + ce20: e1b03c23 movs r3, r3, lsr #24 + ce24: ebf5dc55 bl 0xffd83f80 + ce28: 080c0da4 stmeqda ip, {r2, r5, r7, r8, sl, fp} + ce2c: e1a01003 mov r1, r3 + ce30: e2934000 adds r4, r3, #0 ; 0x0 + ce34: ebf5dc51 bl 0xffd83f80 + ce38: 080c0da6 stmeqda ip, {r1, r2, r5, r7, r8, sl, fp} + ce3c: e3530002 cmp r3, #2 ; 0x2 + ce40: ebf5dc4e bl 0xffd83f80 + ce44: 080c0da8 stmeqda ip, {r3, r5, r7, r8, sl, fp} + ce48: e28cc00f add ip, ip, #15 ; 0xf + ce4c: 1a000004 bne 0xce64 + ce50: e1a00fac mov r0, ip, lsr #31 + ce54: e08ff100 add pc, pc, r0, lsl #2 + ce58: 080c0dc8 stmeqda ip, {r3, r6, r7, r8, sl, fp} + ce5c: ebf5d83c bl 0xffd82f54 + ce60: ea000053 b 0xcfb4 + ce64: ebf5dc45 bl 0xffd83f80 + ce68: 080c0daa stmeqda ip, {r1, r3, r5, r7, r8, sl, fp} + ce6c: e3530002 cmp r3, #2 ; 0x2 + ce70: ebf5dc42 bl 0xffd83f80 + ce74: 080c0dac stmeqda ip, {r2, r3, r5, r7, r8, sl, fp} + ce78: e28cc006 add ip, ip, #6 ; 0x6 + ce7c: da000004 ble 0xce94 + ce80: e1a00fac mov r0, ip, lsr #31 + ce84: e08ff100 add pc, pc, r0, lsl #2 + ce88: 080c0db4 stmeqda ip, {r2, r4, r5, r7, r8, sl, fp} + ce8c: ebf5d830 bl 0xffd82f54 + ce90: ea000013 b 0xcee4 + ce94: ebf5dc39 bl 0xffd83f80 + ce98: 080c0dae stmeqda ip, {r1, r2, r3, r5, r7, r8, sl, fp} + ce9c: e3530001 cmp r3, #1 ; 0x1 + cea0: ebf5dc36 bl 0xffd83f80 + cea4: 080c0db0 stmeqda ip, {r4, r5, r7, r8, sl, fp} + cea8: e28cc006 add ip, ip, #6 ; 0x6 + ceac: 1a000004 bne 0xcec4 + ceb0: e1a00fac mov r0, ip, lsr #31 + ceb4: e08ff100 add pc, pc, r0, lsl #2 + ceb8: 080c0dba stmeqda ip, {r1, r3, r4, r5, r7, r8, sl, fp} + cebc: ebf5d824 bl 0xffd82f54 + cec0: ea00001b b 0xcf34 + cec4: ebf5dc2d bl 0xffd83f80 + cec8: 080c0db2 stmeqda ip, {r1, r4, r5, r7, r8, sl, fp} + cecc: e28cc003 add ip, ip, #3 ; 0x3 + ced0: e1a00fac mov r0, ip, lsr #31 + ced4: e08ff100 add pc, pc, r0, lsl #2 + ced8: 080c0ddc stmeqda ip, {r2, r3, r4, r6, r7, r8, sl, fp} + cedc: ebf5d81c bl 0xffd82f54 + cee0: ea000063 b 0xd074 + cee4: ebf5dc25 bl 0xffd83f80 + cee8: 080c0db4 stmeqda ip, {r2, r4, r5, r7, r8, sl, fp} + ceec: e3540003 cmp r4, #3 ; 0x3 + cef0: ebf5dc22 bl 0xffd83f80 + cef4: 080c0db6 stmeqda ip, {r1, r2, r4, r5, r7, r8, sl, fp} + cef8: e28cc006 add ip, ip, #6 ; 0x6 + cefc: 1a000004 bne 0xcf14 + cf00: e1a00fac mov r0, ip, lsr #31 + cf04: e08ff100 add pc, pc, r0, lsl #2 + cf08: 080c0dd0 stmeqda ip, {r4, r6, r7, r8, sl, fp} + cf0c: ebf5d810 bl 0xffd82f54 + cf10: ea00007d b 0xd10c + cf14: ebf5dc19 bl 0xffd83f80 + cf18: 080c0db8 stmeqda ip, {r3, r4, r5, r7, r8, sl, fp} + cf1c: e28cc003 add ip, ip, #3 ; 0x3 + cf20: e1a00fac mov r0, ip, lsr #31 + cf24: e08ff100 add pc, pc, r0, lsl #2 + cf28: 080c0ddc stmeqda ip, {r2, r3, r4, r6, r7, r8, sl, fp} + cf2c: ebf5d808 bl 0xffd82f54 + cf30: ea00004f b 0xd074 + cf34: ebf5dc11 bl 0xffd83f80 + cf38: 080c0dba stmeqda ip, {r1, r3, r4, r5, r7, r8, sl, fp} + cf3c: e3a00f71 mov r0, #452 ; 0x1c4 + cf40: e3800b03 orr r0, r0, #3072 ; 0xc00 + cf44: e3800703 orr r0, r0, #786432 ; 0xc0000 + cf48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + cf4c: ebf5da71 bl 0xffd83918 + cf50: 080c0dbe stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, sl, fp} + cf54: e1a04000 mov r4, r0 + cf58: ebf5dc08 bl 0xffd83f80 + cf5c: 080c0dbc stmeqda ip, {r2, r3, r4, r5, r7, r8, sl, fp} + cf60: e3b03008 movs r3, #8 ; 0x8 + cf64: ebf5dc05 bl 0xffd83f80 + cf68: 080c0dbe stmeqda ip, {r1, r2, r3, r4, r5, r7, r8, sl, fp} + cf6c: e2840000 add r0, r4, #0 ; 0x0 + cf70: e1a01003 mov r1, r3 + cf74: ebf5d955 bl 0xffd834d0 + cf78: 080c0dc0 stmeqda ip, {r6, r7, r8, sl, fp} + cf7c: ebf5dbff bl 0xffd83f80 + cf80: 080c0dc0 stmeqda ip, {r6, r7, r8, sl, fp} + cf84: e1a01004 mov r1, r4 + cf88: e2944002 adds r4, r4, #2 ; 0x2 + cf8c: ebf5dbfb bl 0xffd83f80 + cf90: 080c0dc2 stmeqda ip, {r1, r6, r7, r8, sl, fp} + cf94: e28cc012 add ip, ip, #18 ; 0x12 + cf98: e1a00fac mov r0, ip, lsr #31 + cf9c: e08ff100 add pc, pc, r0, lsl #2 + cfa0: 080c0de4 stmeqda ip, {r2, r5, r6, r7, r8, sl, fp} + cfa4: ebf5d7ea bl 0xffd82f54 + cfa8: ea00007a b 0xd198 + cfac: 080c0dc8 stmeqda ip, {r3, r6, r7, r8, sl, fp} + cfb0: 00000000 andeq r0, r0, r0 + cfb4: ebf5dbf1 bl 0xffd83f80 + cfb8: 080c0dc8 stmeqda ip, {r3, r6, r7, r8, sl, fp} + cfbc: e3a00f73 mov r0, #460 ; 0x1cc + cfc0: e3800b03 orr r0, r0, #3072 ; 0xc00 + cfc4: e3800703 orr r0, r0, #786432 ; 0xc0000 + cfc8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + cfcc: ebf5da51 bl 0xffd83918 + cfd0: 080c0dcc stmeqda ip, {r2, r3, r6, r7, r8, sl, fp} + cfd4: e1a04000 mov r4, r0 + cfd8: ebf5dbe8 bl 0xffd83f80 + cfdc: 080c0dca stmeqda ip, {r1, r3, r6, r7, r8, sl, fp} + cfe0: e28cc008 add ip, ip, #8 ; 0x8 + cfe4: e1a00fac mov r0, ip, lsr #31 + cfe8: e08ff100 add pc, pc, r0, lsl #2 + cfec: 080c0dde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, sl, fp} + cff0: ebf5d7d7 bl 0xffd82f54 + cff4: ea000001 b 0xd000 + cff8: 080c0dde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, sl, fp} + cffc: 00000000 andeq r0, r0, r0 + d000: ebf5dbde bl 0xffd83f80 + d004: 080c0dde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, sl, fp} + d008: e3b03008 movs r3, #8 ; 0x8 + d00c: ebf5dbdb bl 0xffd83f80 + d010: 080c0de0 stmeqda ip, {r5, r6, r7, r8, sl, fp} + d014: e2840000 add r0, r4, #0 ; 0x0 + d018: e1a01003 mov r1, r3 + d01c: ebf5d92b bl 0xffd834d0 + d020: 080c0de2 stmeqda ip, {r1, r5, r6, r7, r8, sl, fp} + d024: ebf5dbd5 bl 0xffd83f80 + d028: 080c0de2 stmeqda ip, {r1, r5, r6, r7, r8, sl, fp} + d02c: e1a01004 mov r1, r4 + d030: e2944004 adds r4, r4, #4 ; 0x4 + d034: ebf5dbd1 bl 0xffd83f80 + d038: 080c0de4 stmeqda ip, {r2, r5, r6, r7, r8, sl, fp} + d03c: e3b03080 movs r3, #128 ; 0x80 + d040: ebf5dbce bl 0xffd83f80 + d044: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d048: e2840000 add r0, r4, #0 ; 0x0 + d04c: e1a01003 mov r1, r3 + d050: ebf5d91e bl 0xffd834d0 + d054: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d058: ebf5dbc8 bl 0xffd83f80 + d05c: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d060: e59d0438 ldr r0, [sp, #1080] + d064: e28cc014 add ip, ip, #20 ; 0x14 + d068: eaf5d818 b 0xffd830d0 + d06c: 080c0ddc stmeqda ip, {r2, r3, r4, r6, r7, r8, sl, fp} + d070: 00000000 andeq r0, r0, r0 + d074: ebf5dbc1 bl 0xffd83f80 + d078: 080c0ddc stmeqda ip, {r2, r3, r4, r6, r7, r8, sl, fp} + d07c: e3a00f7b mov r0, #492 ; 0x1ec + d080: e3800b03 orr r0, r0, #3072 ; 0xc00 + d084: e3800703 orr r0, r0, #786432 ; 0xc0000 + d088: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d08c: ebf5da21 bl 0xffd83918 + d090: 080c0de0 stmeqda ip, {r5, r6, r7, r8, sl, fp} + d094: e1a04000 mov r4, r0 + d098: ebf5dbb8 bl 0xffd83f80 + d09c: 080c0dde stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, sl, fp} + d0a0: e3b03008 movs r3, #8 ; 0x8 + d0a4: ebf5dbb5 bl 0xffd83f80 + d0a8: 080c0de0 stmeqda ip, {r5, r6, r7, r8, sl, fp} + d0ac: e2840000 add r0, r4, #0 ; 0x0 + d0b0: e1a01003 mov r1, r3 + d0b4: ebf5d905 bl 0xffd834d0 + d0b8: 080c0de2 stmeqda ip, {r1, r5, r6, r7, r8, sl, fp} + d0bc: ebf5dbaf bl 0xffd83f80 + d0c0: 080c0de2 stmeqda ip, {r1, r5, r6, r7, r8, sl, fp} + d0c4: e1a01004 mov r1, r4 + d0c8: e2944004 adds r4, r4, #4 ; 0x4 + d0cc: ebf5dbab bl 0xffd83f80 + d0d0: 080c0de4 stmeqda ip, {r2, r5, r6, r7, r8, sl, fp} + d0d4: e3b03080 movs r3, #128 ; 0x80 + d0d8: ebf5dba8 bl 0xffd83f80 + d0dc: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d0e0: e2840000 add r0, r4, #0 ; 0x0 + d0e4: e1a01003 mov r1, r3 + d0e8: ebf5d8f8 bl 0xffd834d0 + d0ec: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d0f0: ebf5dba2 bl 0xffd83f80 + d0f4: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d0f8: e59d0438 ldr r0, [sp, #1080] + d0fc: e28cc019 add ip, ip, #25 ; 0x19 + d100: eaf5d7f2 b 0xffd830d0 + d104: 080c0dd0 stmeqda ip, {r4, r6, r7, r8, sl, fp} + d108: 00000000 andeq r0, r0, r0 + d10c: ebf5db9b bl 0xffd83f80 + d110: 080c0dd0 stmeqda ip, {r4, r6, r7, r8, sl, fp} + d114: e3a00f76 mov r0, #472 ; 0x1d8 + d118: e3800b03 orr r0, r0, #3072 ; 0xc00 + d11c: e3800703 orr r0, r0, #786432 ; 0xc0000 + d120: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d124: ebf5d9fb bl 0xffd83918 + d128: 080c0dd4 stmeqda ip, {r2, r4, r6, r7, r8, sl, fp} + d12c: e1a04000 mov r4, r0 + d130: ebf5db92 bl 0xffd83f80 + d134: 080c0dd2 stmeqda ip, {r1, r4, r6, r7, r8, sl, fp} + d138: e3b03000 movs r3, #0 ; 0x0 + d13c: ebf5db8f bl 0xffd83f80 + d140: 080c0dd4 stmeqda ip, {r2, r4, r6, r7, r8, sl, fp} + d144: e28cc00b add ip, ip, #11 ; 0xb + d148: e1a00fac mov r0, ip, lsr #31 + d14c: e08ff100 add pc, pc, r0, lsl #2 + d150: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d154: ebf5d77e bl 0xffd82f54 + d158: ea000001 b 0xd164 + d15c: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d160: 00000000 andeq r0, r0, r0 + d164: ebf5db85 bl 0xffd83f80 + d168: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d16c: e2840000 add r0, r4, #0 ; 0x0 + d170: e1a01003 mov r1, r3 + d174: ebf5d8d5 bl 0xffd834d0 + d178: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d17c: ebf5db7f bl 0xffd83f80 + d180: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d184: e59d0438 ldr r0, [sp, #1080] + d188: e28cc007 add ip, ip, #7 ; 0x7 + d18c: eaf5d7cf b 0xffd830d0 + d190: 080c0de4 stmeqda ip, {r2, r5, r6, r7, r8, sl, fp} + d194: 00000000 andeq r0, r0, r0 + d198: ebf5db78 bl 0xffd83f80 + d19c: 080c0de4 stmeqda ip, {r2, r5, r6, r7, r8, sl, fp} + d1a0: e3b03080 movs r3, #128 ; 0x80 + d1a4: ebf5db75 bl 0xffd83f80 + d1a8: 080c0de6 stmeqda ip, {r1, r2, r5, r6, r7, r8, sl, fp} + d1ac: e2840000 add r0, r4, #0 ; 0x0 + d1b0: e1a01003 mov r1, r3 + d1b4: ebf5d8c5 bl 0xffd834d0 + d1b8: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d1bc: ebf5db6f bl 0xffd83f80 + d1c0: 080c0de8 stmeqda ip, {r3, r5, r6, r7, r8, sl, fp} + d1c4: e59d0438 ldr r0, [sp, #1080] + d1c8: e28cc00a add ip, ip, #10 ; 0xa + d1cc: eaf5d7bf b 0xffd830d0 + d1d0: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + d1d4: 00000000 andeq r0, r0, r0 + d1d8: ebf5db68 bl 0xffd83f80 + d1dc: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + d1e0: e3b03002 movs r3, #2 ; 0x2 + d1e4: ebf5db65 bl 0xffd83f80 + d1e8: 080c1174 stmeqda ip, {r2, r4, r5, r6, r8, ip} + d1ec: e287001d add r0, r7, #29 ; 0x1d + d1f0: ebf5d971 bl 0xffd837bc + d1f4: 080c1178 stmeqda ip, {r3, r4, r5, r6, r8, ip} + d1f8: e1a05000 mov r5, r0 + d1fc: ebf5db5f bl 0xffd83f80 + d200: 080c1176 stmeqda ip, {r1, r2, r4, r5, r6, r8, ip} + d204: e1a01003 mov r1, r3 + d208: e0133005 ands r3, r3, r5 + d20c: ebf5db5b bl 0xffd83f80 + d210: 080c1178 stmeqda ip, {r3, r4, r5, r6, r8, ip} + d214: e3530000 cmp r3, #0 ; 0x0 + d218: ebf5db58 bl 0xffd83f80 + d21c: 080c117a stmeqda ip, {r1, r3, r4, r5, r6, r8, ip} + d220: e28cc011 add ip, ip, #17 ; 0x11 + d224: 1a000004 bne 0xd23c + d228: e1a00fac mov r0, ip, lsr #31 + d22c: e08ff100 add pc, pc, r0, lsl #2 + d230: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + d234: ebf5d746 bl 0xffd82f54 + d238: ea00005b b 0xd3ac + d23c: ebf5db4f bl 0xffd83f80 + d240: 080c117c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip} + d244: e59d1418 ldr r1, [sp, #1048] + d248: e3510003 cmp r1, #3 ; 0x3 + d24c: ebf5db4b bl 0xffd83f80 + d250: 080c117e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, ip} + d254: e28cc006 add ip, ip, #6 ; 0x6 + d258: da000004 ble 0xd270 + d25c: e1a00fac mov r0, ip, lsr #31 + d260: e08ff100 add pc, pc, r0, lsl #2 + d264: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + d268: ebf5d739 bl 0xffd82f54 + d26c: ea00023c b 0xdb64 + d270: ebf5db42 bl 0xffd83f80 + d274: 080c1180 stmeqda ip, {r7, r8, ip} + d278: e3b03008 movs r3, #8 ; 0x8 + d27c: ebf5db3f bl 0xffd83f80 + d280: 080c1182 stmeqda ip, {r1, r7, r8, ip} + d284: e2870001 add r0, r7, #1 ; 0x1 + d288: ebf5d94b bl 0xffd837bc + d28c: 080c1186 stmeqda ip, {r1, r2, r7, r8, ip} + d290: e1a04000 mov r4, r0 + d294: ebf5db39 bl 0xffd83f80 + d298: 080c1184 stmeqda ip, {r2, r7, r8, ip} + d29c: e1a01003 mov r1, r3 + d2a0: e0133004 ands r3, r3, r4 + d2a4: ebf5db35 bl 0xffd83f80 + d2a8: 080c1186 stmeqda ip, {r1, r2, r7, r8, ip} + d2ac: e3530000 cmp r3, #0 ; 0x0 + d2b0: ebf5db32 bl 0xffd83f80 + d2b4: 080c1188 stmeqda ip, {r3, r7, r8, ip} + d2b8: e28cc011 add ip, ip, #17 ; 0x11 + d2bc: 1a000004 bne 0xd2d4 + d2c0: e1a00fac mov r0, ip, lsr #31 + d2c4: e08ff100 add pc, pc, r0, lsl #2 + d2c8: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + d2cc: ebf5d720 bl 0xffd82f54 + d2d0: ea000223 b 0xdb64 + d2d4: ebf5db29 bl 0xffd83f80 + d2d8: 080c118a stmeqda ip, {r1, r3, r7, r8, ip} + d2dc: e3a00f67 mov r0, #412 ; 0x19c + d2e0: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + d2e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d2e8: ebf5d98a bl 0xffd83918 + d2ec: 080c118e stmeqda ip, {r1, r2, r3, r7, r8, ip} + d2f0: e1a03000 mov r3, r0 + d2f4: ebf5db21 bl 0xffd83f80 + d2f8: 080c118c stmeqda ip, {r2, r3, r7, r8, ip} + d2fc: e2830000 add r0, r3, #0 ; 0x0 + d300: ebf5d92d bl 0xffd837bc + d304: 080c1190 stmeqda ip, {r4, r7, r8, ip} + d308: e1a03000 mov r3, r0 + d30c: ebf5db1b bl 0xffd83f80 + d310: 080c118e stmeqda ip, {r1, r2, r3, r7, r8, ip} + d314: e353003f cmp r3, #63 ; 0x3f + d318: ebf5db18 bl 0xffd83f80 + d31c: 080c1190 stmeqda ip, {r4, r7, r8, ip} + d320: e28cc010 add ip, ip, #16 ; 0x10 + d324: da000004 ble 0xd33c + d328: e1a00fac mov r0, ip, lsr #31 + d32c: e08ff100 add pc, pc, r0, lsl #2 + d330: 080c11a4 stmeqda ip, {r2, r5, r7, r8, ip} + d334: ebf5d706 bl 0xffd82f54 + d338: ea000464 b 0xe4d0 + d33c: ebf5db0f bl 0xffd83f80 + d340: 080c1192 stmeqda ip, {r1, r4, r7, r8, ip} + d344: e2870020 add r0, r7, #32 ; 0x20 + d348: ebf5d972 bl 0xffd83918 + d34c: 080c1196 stmeqda ip, {r1, r2, r4, r7, r8, ip} + d350: e1a03000 mov r3, r0 + d354: ebf5db09 bl 0xffd83f80 + d358: 080c1194 stmeqda ip, {r2, r4, r7, r8, ip} + d35c: e1a01003 mov r1, r3 + d360: e2933002 adds r3, r3, #2 ; 0x2 + d364: ebf5db05 bl 0xffd83f80 + d368: 080c1196 stmeqda ip, {r1, r2, r4, r7, r8, ip} + d36c: e3a00e1a mov r0, #416 ; 0x1a0 + d370: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + d374: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d378: ebf5d966 bl 0xffd83918 + d37c: 080c119a stmeqda ip, {r1, r3, r4, r7, r8, ip} + d380: e1a04000 mov r4, r0 + d384: ebf5dafd bl 0xffd83f80 + d388: 080c1198 stmeqda ip, {r3, r4, r7, r8, ip} + d38c: e28cc010 add ip, ip, #16 ; 0x10 + d390: e1a00fac mov r0, ip, lsr #31 + d394: e08ff100 add pc, pc, r0, lsl #2 + d398: 080c11ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip} + d39c: ebf5d6ec bl 0xffd82f54 + d3a0: ea000490 b 0xe5e8 + d3a4: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + d3a8: 00000000 andeq r0, r0, r0 + d3ac: ebf5daf3 bl 0xffd83f80 + d3b0: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + d3b4: e3b03001 movs r3, #1 ; 0x1 + d3b8: ebf5daf0 bl 0xffd83f80 + d3bc: 080c11ea stmeqda ip, {r1, r3, r5, r6, r7, r8, ip} + d3c0: e287001d add r0, r7, #29 ; 0x1d + d3c4: ebf5d8fc bl 0xffd837bc + d3c8: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + d3cc: e1a05000 mov r5, r0 + d3d0: ebf5daea bl 0xffd83f80 + d3d4: 080c11ec stmeqda ip, {r2, r3, r5, r6, r7, r8, ip} + d3d8: e1a01003 mov r1, r3 + d3dc: e0133005 ands r3, r3, r5 + d3e0: ebf5dae6 bl 0xffd83f80 + d3e4: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + d3e8: e3530000 cmp r3, #0 ; 0x0 + d3ec: ebf5dae3 bl 0xffd83f80 + d3f0: 080c11f0 stmeqda ip, {r4, r5, r6, r7, r8, ip} + d3f4: e28cc011 add ip, ip, #17 ; 0x11 + d3f8: 1a000004 bne 0xd410 + d3fc: e1a00fac mov r0, ip, lsr #31 + d400: e08ff100 add pc, pc, r0, lsl #2 + d404: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d408: ebf5d6d1 bl 0xffd82f54 + d40c: ea0000b0 b 0xd6d4 + d410: ebf5dada bl 0xffd83f80 + d414: 080c11f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, ip} + d418: e3a00e23 mov r0, #560 ; 0x230 + d41c: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + d420: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d424: ebf5d93b bl 0xffd83918 + d428: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + d42c: e1a04000 mov r4, r0 + d430: ebf5dad2 bl 0xffd83f80 + d434: 080c11f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, ip} + d438: e2840000 add r0, r4, #0 ; 0x0 + d43c: ebf5d8de bl 0xffd837bc + d440: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + d444: e1a03000 mov r3, r0 + d448: ebf5dacc bl 0xffd83f80 + d44c: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + d450: e287001c add r0, r7, #28 ; 0x1c + d454: ebf5d8d8 bl 0xffd837bc + d458: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + d45c: e1a05000 mov r5, r0 + d460: ebf5dac6 bl 0xffd83f80 + d464: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + d468: e1a01003 mov r1, r3 + d46c: e1d33005 bics r3, r3, r5 + d470: ebf5dac2 bl 0xffd83f80 + d474: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + d478: e287001b add r0, r7, #27 ; 0x1b + d47c: ebf5d8ce bl 0xffd837bc + d480: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + d484: e1a05000 mov r5, r0 + d488: ebf5dabc bl 0xffd83f80 + d48c: 080c11fc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, ip} + d490: e1a01003 mov r1, r3 + d494: e1933005 orrs r3, r3, r5 + d498: ebf5dab8 bl 0xffd83f80 + d49c: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + d4a0: e2840000 add r0, r4, #0 ; 0x0 + d4a4: e1a01003 mov r1, r3 + d4a8: ebf5d808 bl 0xffd834d0 + d4ac: 080c1200 stmeqda ip, {r9, ip} + d4b0: ebf5dab2 bl 0xffd83f80 + d4b4: 080c1200 stmeqda ip, {r9, ip} + d4b8: e59d1418 ldr r1, [sp, #1048] + d4bc: e3510003 cmp r1, #3 ; 0x3 + d4c0: ebf5daae bl 0xffd83f80 + d4c4: 080c1202 stmeqda ip, {r1, r9, ip} + d4c8: e28cc024 add ip, ip, #36 ; 0x24 + d4cc: 0a000004 beq 0xd4e4 + d4d0: e1a00fac mov r0, ip, lsr #31 + d4d4: e08ff100 add pc, pc, r0, lsl #2 + d4d8: 080c1238 stmeqda ip, {r3, r4, r5, r9, ip} + d4dc: ebf5d69c bl 0xffd82f54 + d4e0: ea0000ec b 0xd898 + d4e4: ebf5daa5 bl 0xffd83f80 + d4e8: 080c1204 stmeqda ip, {r2, r9, ip} + d4ec: e3a00f8d mov r0, #564 ; 0x234 + d4f0: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + d4f4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + d4f8: ebf5d906 bl 0xffd83918 + d4fc: 080c1208 stmeqda ip, {r3, r9, ip} + d500: e1a03000 mov r3, r0 + d504: ebf5da9d bl 0xffd83f80 + d508: 080c1206 stmeqda ip, {r1, r2, r9, ip} + d50c: e2870009 add r0, r7, #9 ; 0x9 + d510: ebf5d8a9 bl 0xffd837bc + d514: 080c120a stmeqda ip, {r1, r3, r9, ip} + d518: e1a04000 mov r4, r0 + d51c: ebf5da97 bl 0xffd83f80 + d520: 080c1208 stmeqda ip, {r3, r9, ip} + d524: e1a01004 mov r1, r4 + d528: e0943003 adds r3, r4, r3 + d52c: ebf5da93 bl 0xffd83f80 + d530: 080c120a stmeqda ip, {r1, r3, r9, ip} + d534: e2830000 add r0, r3, #0 ; 0x0 + d538: ebf5d89f bl 0xffd837bc + d53c: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + d540: e1a03000 mov r3, r0 + d544: ebf5da8d bl 0xffd83f80 + d548: 080c120c stmeqda ip, {r2, r3, r9, ip} + d54c: e59d1428 ldr r1, [sp, #1064] + d550: e1a05001 mov r5, r1 + d554: ebf5da89 bl 0xffd83f80 + d558: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + d55c: e2850000 add r0, r5, #0 ; 0x0 + d560: e1a01003 mov r1, r3 + d564: ebf5d7d9 bl 0xffd834d0 + d568: 080c1210 stmeqda ip, {r4, r9, ip} + d56c: ebf5da83 bl 0xffd83f80 + d570: 080c1210 stmeqda ip, {r4, r9, ip} + d574: e3b04080 movs r4, #128 ; 0x80 + d578: ebf5da80 bl 0xffd83f80 + d57c: 080c1212 stmeqda ip, {r1, r4, r9, ip} + d580: e1a01004 mov r1, r4 + d584: e2943000 adds r3, r4, #0 ; 0x0 + d588: ebf5da7c bl 0xffd83f80 + d58c: 080c1214 stmeqda ip, {r2, r4, r9, ip} + d590: e287001a add r0, r7, #26 ; 0x1a + d594: ebf5d888 bl 0xffd837bc + d598: 080c1218 stmeqda ip, {r3, r4, r9, ip} + d59c: e1a05000 mov r5, r0 + d5a0: ebf5da76 bl 0xffd83f80 + d5a4: 080c1216 stmeqda ip, {r1, r2, r4, r9, ip} + d5a8: e1a01003 mov r1, r3 + d5ac: e0133005 ands r3, r3, r5 + d5b0: ebf5da72 bl 0xffd83f80 + d5b4: 080c1218 stmeqda ip, {r3, r4, r9, ip} + d5b8: e3530000 cmp r3, #0 ; 0x0 + d5bc: ebf5da6f bl 0xffd83f80 + d5c0: 080c121a stmeqda ip, {r1, r3, r4, r9, ip} + d5c4: e28cc02d add ip, ip, #45 ; 0x2d + d5c8: 1a000004 bne 0xd5e0 + d5cc: e1a00fac mov r0, ip, lsr #31 + d5d0: e08ff100 add pc, pc, r0, lsl #2 + d5d4: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d5d8: ebf5d65d bl 0xffd82f54 + d5dc: ea00003c b 0xd6d4 + d5e0: ebf5da66 bl 0xffd83f80 + d5e4: 080c121c stmeqda ip, {r2, r3, r4, r9, ip} + d5e8: e59d0434 ldr r0, [sp, #1076] + d5ec: e2800f02 add r0, r0, #8 ; 0x8 + d5f0: ebf5d8c8 bl 0xffd83918 + d5f4: 080c1220 stmeqda ip, {r5, r9, ip} + d5f8: e1a03000 mov r3, r0 + d5fc: ebf5da5f bl 0xffd83f80 + d600: 080c121e stmeqda ip, {r1, r2, r3, r4, r9, ip} + d604: e2830000 add r0, r3, #0 ; 0x0 + d608: e1a01004 mov r1, r4 + d60c: ebf5d7af bl 0xffd834d0 + d610: 080c1220 stmeqda ip, {r5, r9, ip} + d614: ebf5da59 bl 0xffd83f80 + d618: 080c1220 stmeqda ip, {r5, r9, ip} + d61c: e287001a add r0, r7, #26 ; 0x1a + d620: ebf5d865 bl 0xffd837bc + d624: 080c1224 stmeqda ip, {r2, r5, r9, ip} + d628: e1a03000 mov r3, r0 + d62c: ebf5da53 bl 0xffd83f80 + d630: 080c1222 stmeqda ip, {r1, r5, r9, ip} + d634: e59d0434 ldr r0, [sp, #1076] + d638: e2800f04 add r0, r0, #16 ; 0x10 + d63c: ebf5d8b5 bl 0xffd83918 + d640: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + d644: e1a04000 mov r4, r0 + d648: ebf5da4c bl 0xffd83f80 + d64c: 080c1224 stmeqda ip, {r2, r5, r9, ip} + d650: e2840000 add r0, r4, #0 ; 0x0 + d654: e1a01003 mov r1, r3 + d658: ebf5d79c bl 0xffd834d0 + d65c: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + d660: ebf5da46 bl 0xffd83f80 + d664: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + d668: e3b0307f movs r3, #127 ; 0x7f + d66c: ebf5da43 bl 0xffd83f80 + d670: 080c1228 stmeqda ip, {r3, r5, r9, ip} + d674: e287001a add r0, r7, #26 ; 0x1a + d678: ebf5d84f bl 0xffd837bc + d67c: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + d680: e1a05000 mov r5, r0 + d684: ebf5da3d bl 0xffd83f80 + d688: 080c122a stmeqda ip, {r1, r3, r5, r9, ip} + d68c: e1a01003 mov r1, r3 + d690: e0133005 ands r3, r3, r5 + d694: ebf5da39 bl 0xffd83f80 + d698: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + d69c: e287001a add r0, r7, #26 ; 0x1a + d6a0: e1a01003 mov r1, r3 + d6a4: ebf5d789 bl 0xffd834d0 + d6a8: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + d6ac: ebf5da33 bl 0xffd83f80 + d6b0: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + d6b4: e28cc029 add ip, ip, #41 ; 0x29 + d6b8: e1a00fac mov r0, ip, lsr #31 + d6bc: e08ff100 add pc, pc, r0, lsl #2 + d6c0: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d6c4: ebf5d622 bl 0xffd82f54 + d6c8: ea000001 b 0xd6d4 + d6cc: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d6d0: 00000000 andeq r0, r0, r0 + d6d4: ebf5da29 bl 0xffd83f80 + d6d8: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d6dc: e3b03000 movs r3, #0 ; 0x0 + d6e0: ebf5da26 bl 0xffd83f80 + d6e4: 080c1256 stmeqda ip, {r1, r2, r4, r6, r9, ip} + d6e8: e287001d add r0, r7, #29 ; 0x1d + d6ec: e1a01003 mov r1, r3 + d6f0: ebf5d776 bl 0xffd834d0 + d6f4: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + d6f8: ebf5da20 bl 0xffd83f80 + d6fc: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + d700: e59d1424 ldr r1, [sp, #1060] + d704: e1a00001 mov r0, r1 + d708: e58d0418 str r0, [sp, #1048] + d70c: ebf5da1b bl 0xffd83f80 + d710: 080c125a stmeqda ip, {r1, r3, r4, r6, r9, ip} + d714: e59d1420 ldr r1, [sp, #1056] + d718: e1a07001 mov r7, r1 + d71c: ebf5da17 bl 0xffd83f80 + d720: 080c125c stmeqda ip, {r2, r3, r4, r6, r9, ip} + d724: e59d1418 ldr r1, [sp, #1048] + d728: e3510004 cmp r1, #4 ; 0x4 + d72c: ebf5da13 bl 0xffd83f80 + d730: 080c125e stmeqda ip, {r1, r2, r3, r4, r6, r9, ip} + d734: e28cc013 add ip, ip, #19 ; 0x13 + d738: da000004 ble 0xd750 + d73c: e1a00fac mov r0, ip, lsr #31 + d740: e08ff100 add pc, pc, r0, lsl #2 + d744: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + d748: ebf5d601 bl 0xffd82f54 + d74c: ea000007 b 0xd770 + d750: ebf5da0a bl 0xffd83f80 + d754: 080c1260 stmeqda ip, {r5, r6, r9, ip} + d758: e28cc003 add ip, ip, #3 ; 0x3 + d75c: e1a00fac mov r0, ip, lsr #31 + d760: e08ff100 add pc, pc, r0, lsl #2 + d764: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + d768: ebf5d5f9 bl 0xffd82f54 + d76c: eafffa71 b 0xc138 + d770: ebf5da02 bl 0xffd83f80 + d774: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + d778: e59d0434 ldr r0, [sp, #1076] + d77c: e2800f06 add r0, r0, #24 ; 0x18 + d780: e58d0434 str r0, [sp, #1076] + d784: ebf5d9fd bl 0xffd83f80 + d788: 080c1264 stmeqda ip, {r2, r5, r6, r9, ip} + d78c: e59d9434 ldr r9, [sp, #1076] + d790: e3c99003 bic r9, r9, #3 ; 0x3 + d794: e289000c add r0, r9, #12 ; 0xc + d798: e58d0434 str r0, [sp, #1076] + d79c: e2890000 add r0, r9, #0 ; 0x0 + d7a0: ebf5d85c bl 0xffd83918 + d7a4: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + d7a8: e1a06000 mov r6, r0 + d7ac: e2890004 add r0, r9, #4 ; 0x4 + d7b0: ebf5d858 bl 0xffd83918 + d7b4: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + d7b8: e1a07000 mov r7, r0 + d7bc: e2890008 add r0, r9, #8 ; 0x8 + d7c0: ebf5d854 bl 0xffd83918 + d7c4: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + d7c8: e1a08000 mov r8, r0 + d7cc: ebf5d9eb bl 0xffd83f80 + d7d0: 080c1266 stmeqda ip, {r1, r2, r5, r6, r9, ip} + d7d4: e1a00006 mov r0, r6 + d7d8: e58d0420 str r0, [sp, #1056] + d7dc: ebf5d9e7 bl 0xffd83f80 + d7e0: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + d7e4: e1a00007 mov r0, r7 + d7e8: e58d0424 str r0, [sp, #1060] + d7ec: ebf5d9e3 bl 0xffd83f80 + d7f0: 080c126a stmeqda ip, {r1, r3, r5, r6, r9, ip} + d7f4: e1a00008 mov r0, r8 + d7f8: e58d0428 str r0, [sp, #1064] + d7fc: ebf5d9df bl 0xffd83f80 + d800: 080c126c stmeqda ip, {r2, r3, r5, r6, r9, ip} + d804: e59d9434 ldr r9, [sp, #1076] + d808: e3c99003 bic r9, r9, #3 ; 0x3 + d80c: e2890010 add r0, r9, #16 ; 0x10 + d810: e58d0434 str r0, [sp, #1076] + d814: e2890000 add r0, r9, #0 ; 0x0 + d818: ebf5d83e bl 0xffd83918 + d81c: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + d820: e1a07000 mov r7, r0 + d824: e2890004 add r0, r9, #4 ; 0x4 + d828: ebf5d83a bl 0xffd83918 + d82c: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + d830: e1a08000 mov r8, r0 + d834: e2890008 add r0, r9, #8 ; 0x8 + d838: ebf5d836 bl 0xffd83918 + d83c: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + d840: e58d0418 str r0, [sp, #1048] + d844: e289000c add r0, r9, #12 ; 0xc + d848: ebf5d832 bl 0xffd83918 + d84c: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + d850: e58d041c str r0, [sp, #1052] + d854: ebf5d9c9 bl 0xffd83f80 + d858: 080c126e stmeqda ip, {r1, r2, r3, r5, r6, r9, ip} + d85c: e59d9434 ldr r9, [sp, #1076] + d860: e3c99003 bic r9, r9, #3 ; 0x3 + d864: e2890004 add r0, r9, #4 ; 0x4 + d868: e58d0434 str r0, [sp, #1076] + d86c: e2890000 add r0, r9, #0 ; 0x0 + d870: ebf5d828 bl 0xffd83918 + d874: 080c1272 stmeqda ip, {r1, r4, r5, r6, r9, ip} + d878: e1a03000 mov r3, r0 + d87c: ebf5d9bf bl 0xffd83f80 + d880: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + d884: e1a00003 mov r0, r3 + d888: e28cc020 add ip, ip, #32 ; 0x20 + d88c: eaf5d60f b 0xffd830d0 + d890: 080c1238 stmeqda ip, {r3, r4, r5, r9, ip} + d894: 00000000 andeq r0, r0, r0 + d898: ebf5d9b8 bl 0xffd83f80 + d89c: 080c1238 stmeqda ip, {r3, r4, r5, r9, ip} + d8a0: e59d1428 ldr r1, [sp, #1064] + d8a4: e1a03001 mov r3, r1 + d8a8: ebf5d9b4 bl 0xffd83f80 + d8ac: 080c123a stmeqda ip, {r1, r3, r4, r5, r9, ip} + d8b0: e2830000 add r0, r3, #0 ; 0x0 + d8b4: ebf5d7c0 bl 0xffd837bc + d8b8: 080c123e stmeqda ip, {r1, r2, r3, r4, r5, r9, ip} + d8bc: e1a04000 mov r4, r0 + d8c0: ebf5d9ae bl 0xffd83f80 + d8c4: 080c123c stmeqda ip, {r2, r3, r4, r5, r9, ip} + d8c8: e3b0300f movs r3, #15 ; 0xf + d8cc: ebf5d9ab bl 0xffd83f80 + d8d0: 080c123e stmeqda ip, {r1, r2, r3, r4, r5, r9, ip} + d8d4: e1a01003 mov r1, r3 + d8d8: e0133004 ands r3, r3, r4 + d8dc: ebf5d9a7 bl 0xffd83f80 + d8e0: 080c1240 stmeqda ip, {r6, r9, ip} + d8e4: e2870009 add r0, r7, #9 ; 0x9 + d8e8: ebf5d7b3 bl 0xffd837bc + d8ec: 080c1244 stmeqda ip, {r2, r6, r9, ip} + d8f0: e1a05000 mov r5, r0 + d8f4: ebf5d9a1 bl 0xffd83f80 + d8f8: 080c1242 stmeqda ip, {r1, r6, r9, ip} + d8fc: e1b04205 movs r4, r5, lsl #4 + d900: ebf5d99e bl 0xffd83f80 + d904: 080c1244 stmeqda ip, {r2, r6, r9, ip} + d908: e1a01003 mov r1, r3 + d90c: e0933004 adds r3, r3, r4 + d910: ebf5d99a bl 0xffd83f80 + d914: 080c1246 stmeqda ip, {r1, r2, r6, r9, ip} + d918: e59d1428 ldr r1, [sp, #1064] + d91c: e1a04001 mov r4, r1 + d920: ebf5d996 bl 0xffd83f80 + d924: 080c1248 stmeqda ip, {r3, r6, r9, ip} + d928: e2840000 add r0, r4, #0 ; 0x0 + d92c: e1a01003 mov r1, r3 + d930: ebf5d6e6 bl 0xffd834d0 + d934: 080c124a stmeqda ip, {r1, r3, r6, r9, ip} + d938: ebf5d990 bl 0xffd83f80 + d93c: 080c124a stmeqda ip, {r1, r3, r6, r9, ip} + d940: e3b03080 movs r3, #128 ; 0x80 + d944: ebf5d98d bl 0xffd83f80 + d948: 080c124c stmeqda ip, {r2, r3, r6, r9, ip} + d94c: e287001a add r0, r7, #26 ; 0x1a + d950: ebf5d799 bl 0xffd837bc + d954: 080c1250 stmeqda ip, {r4, r6, r9, ip} + d958: e1a05000 mov r5, r0 + d95c: ebf5d987 bl 0xffd83f80 + d960: 080c124e stmeqda ip, {r1, r2, r3, r6, r9, ip} + d964: e1a01003 mov r1, r3 + d968: e1933005 orrs r3, r3, r5 + d96c: ebf5d983 bl 0xffd83f80 + d970: 080c1250 stmeqda ip, {r4, r6, r9, ip} + d974: e59d0434 ldr r0, [sp, #1076] + d978: e2800f04 add r0, r0, #16 ; 0x10 + d97c: ebf5d7e5 bl 0xffd83918 + d980: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d984: e1a04000 mov r4, r0 + d988: ebf5d97c bl 0xffd83f80 + d98c: 080c1252 stmeqda ip, {r1, r4, r6, r9, ip} + d990: e2840000 add r0, r4, #0 ; 0x0 + d994: e1a01003 mov r1, r3 + d998: ebf5d6cc bl 0xffd834d0 + d99c: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d9a0: ebf5d976 bl 0xffd83f80 + d9a4: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + d9a8: e3b03000 movs r3, #0 ; 0x0 + d9ac: ebf5d973 bl 0xffd83f80 + d9b0: 080c1256 stmeqda ip, {r1, r2, r4, r6, r9, ip} + d9b4: e287001d add r0, r7, #29 ; 0x1d + d9b8: e1a01003 mov r1, r3 + d9bc: ebf5d6c3 bl 0xffd834d0 + d9c0: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + d9c4: ebf5d96d bl 0xffd83f80 + d9c8: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + d9cc: e59d1424 ldr r1, [sp, #1060] + d9d0: e1a00001 mov r0, r1 + d9d4: e58d0418 str r0, [sp, #1048] + d9d8: ebf5d968 bl 0xffd83f80 + d9dc: 080c125a stmeqda ip, {r1, r3, r4, r6, r9, ip} + d9e0: e59d1420 ldr r1, [sp, #1056] + d9e4: e1a07001 mov r7, r1 + d9e8: ebf5d964 bl 0xffd83f80 + d9ec: 080c125c stmeqda ip, {r2, r3, r4, r6, r9, ip} + d9f0: e59d1418 ldr r1, [sp, #1048] + d9f4: e3510004 cmp r1, #4 ; 0x4 + d9f8: ebf5d960 bl 0xffd83f80 + d9fc: 080c125e stmeqda ip, {r1, r2, r3, r4, r6, r9, ip} + da00: e28cc047 add ip, ip, #71 ; 0x47 + da04: da000004 ble 0xda1c + da08: e1a00fac mov r0, ip, lsr #31 + da0c: e08ff100 add pc, pc, r0, lsl #2 + da10: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + da14: ebf5d54e bl 0xffd82f54 + da18: ea000007 b 0xda3c + da1c: ebf5d957 bl 0xffd83f80 + da20: 080c1260 stmeqda ip, {r5, r6, r9, ip} + da24: e28cc003 add ip, ip, #3 ; 0x3 + da28: e1a00fac mov r0, ip, lsr #31 + da2c: e08ff100 add pc, pc, r0, lsl #2 + da30: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + da34: ebf5d546 bl 0xffd82f54 + da38: eafff9be b 0xc138 + da3c: ebf5d94f bl 0xffd83f80 + da40: 080c1262 stmeqda ip, {r1, r5, r6, r9, ip} + da44: e59d0434 ldr r0, [sp, #1076] + da48: e2800f06 add r0, r0, #24 ; 0x18 + da4c: e58d0434 str r0, [sp, #1076] + da50: ebf5d94a bl 0xffd83f80 + da54: 080c1264 stmeqda ip, {r2, r5, r6, r9, ip} + da58: e59d9434 ldr r9, [sp, #1076] + da5c: e3c99003 bic r9, r9, #3 ; 0x3 + da60: e289000c add r0, r9, #12 ; 0xc + da64: e58d0434 str r0, [sp, #1076] + da68: e2890000 add r0, r9, #0 ; 0x0 + da6c: ebf5d7a9 bl 0xffd83918 + da70: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + da74: e1a06000 mov r6, r0 + da78: e2890004 add r0, r9, #4 ; 0x4 + da7c: ebf5d7a5 bl 0xffd83918 + da80: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + da84: e1a07000 mov r7, r0 + da88: e2890008 add r0, r9, #8 ; 0x8 + da8c: ebf5d7a1 bl 0xffd83918 + da90: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + da94: e1a08000 mov r8, r0 + da98: ebf5d938 bl 0xffd83f80 + da9c: 080c1266 stmeqda ip, {r1, r2, r5, r6, r9, ip} + daa0: e1a00006 mov r0, r6 + daa4: e58d0420 str r0, [sp, #1056] + daa8: ebf5d934 bl 0xffd83f80 + daac: 080c1268 stmeqda ip, {r3, r5, r6, r9, ip} + dab0: e1a00007 mov r0, r7 + dab4: e58d0424 str r0, [sp, #1060] + dab8: ebf5d930 bl 0xffd83f80 + dabc: 080c126a stmeqda ip, {r1, r3, r5, r6, r9, ip} + dac0: e1a00008 mov r0, r8 + dac4: e58d0428 str r0, [sp, #1064] + dac8: ebf5d92c bl 0xffd83f80 + dacc: 080c126c stmeqda ip, {r2, r3, r5, r6, r9, ip} + dad0: e59d9434 ldr r9, [sp, #1076] + dad4: e3c99003 bic r9, r9, #3 ; 0x3 + dad8: e2890010 add r0, r9, #16 ; 0x10 + dadc: e58d0434 str r0, [sp, #1076] + dae0: e2890000 add r0, r9, #0 ; 0x0 + dae4: ebf5d78b bl 0xffd83918 + dae8: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + daec: e1a07000 mov r7, r0 + daf0: e2890004 add r0, r9, #4 ; 0x4 + daf4: ebf5d787 bl 0xffd83918 + daf8: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + dafc: e1a08000 mov r8, r0 + db00: e2890008 add r0, r9, #8 ; 0x8 + db04: ebf5d783 bl 0xffd83918 + db08: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + db0c: e58d0418 str r0, [sp, #1048] + db10: e289000c add r0, r9, #12 ; 0xc + db14: ebf5d77f bl 0xffd83918 + db18: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + db1c: e58d041c str r0, [sp, #1052] + db20: ebf5d916 bl 0xffd83f80 + db24: 080c126e stmeqda ip, {r1, r2, r3, r5, r6, r9, ip} + db28: e59d9434 ldr r9, [sp, #1076] + db2c: e3c99003 bic r9, r9, #3 ; 0x3 + db30: e2890004 add r0, r9, #4 ; 0x4 + db34: e58d0434 str r0, [sp, #1076] + db38: e2890000 add r0, r9, #0 ; 0x0 + db3c: ebf5d775 bl 0xffd83918 + db40: 080c1272 stmeqda ip, {r1, r4, r5, r6, r9, ip} + db44: e1a03000 mov r3, r0 + db48: ebf5d90c bl 0xffd83f80 + db4c: 080c1270 stmeqda ip, {r4, r5, r6, r9, ip} + db50: e1a00003 mov r0, r3 + db54: e28cc020 add ip, ip, #32 ; 0x20 + db58: eaf5d55c b 0xffd830d0 + db5c: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + db60: 00000000 andeq r0, r0, r0 + db64: ebf5d905 bl 0xffd83f80 + db68: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + db6c: e59d1418 ldr r1, [sp, #1048] + db70: e3510004 cmp r1, #4 ; 0x4 + db74: ebf5d901 bl 0xffd83f80 + db78: 080c11b4 stmeqda ip, {r2, r4, r5, r7, r8, ip} + db7c: e28cc006 add ip, ip, #6 ; 0x6 + db80: 1a000004 bne 0xdb98 + db84: e1a00fac mov r0, ip, lsr #31 + db88: e08ff100 add pc, pc, r0, lsl #2 + db8c: 080c11c0 stmeqda ip, {r6, r7, r8, ip} + db90: ebf5d4ef bl 0xffd82f54 + db94: ea00000f b 0xdbd8 + db98: ebf5d8f8 bl 0xffd83f80 + db9c: 080c11b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, ip} + dba0: e2870020 add r0, r7, #32 ; 0x20 + dba4: ebf5d75b bl 0xffd83918 + dba8: 080c11ba stmeqda ip, {r1, r3, r4, r5, r7, r8, ip} + dbac: e1a03000 mov r3, r0 + dbb0: ebf5d8f2 bl 0xffd83f80 + dbb4: 080c11b8 stmeqda ip, {r3, r4, r5, r7, r8, ip} + dbb8: e28cc008 add ip, ip, #8 ; 0x8 + dbbc: e1a00fac mov r0, ip, lsr #31 + dbc0: e08ff100 add pc, pc, r0, lsl #2 + dbc4: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + dbc8: ebf5d4e1 bl 0xffd82f54 + dbcc: ea00012f b 0xe090 + dbd0: 080c11c0 stmeqda ip, {r6, r7, r8, ip} + dbd4: 00000000 andeq r0, r0, r0 + dbd8: ebf5d8e8 bl 0xffd83f80 + dbdc: 080c11c0 stmeqda ip, {r6, r7, r8, ip} + dbe0: e59d0434 ldr r0, [sp, #1076] + dbe4: e2800f03 add r0, r0, #12 ; 0xc + dbe8: ebf5d74a bl 0xffd83918 + dbec: 080c11c4 stmeqda ip, {r2, r6, r7, r8, ip} + dbf0: e1a04000 mov r4, r0 + dbf4: ebf5d8e1 bl 0xffd83f80 + dbf8: 080c11c2 stmeqda ip, {r1, r6, r7, r8, ip} + dbfc: e2840000 add r0, r4, #0 ; 0x0 + dc00: ebf5d6ed bl 0xffd837bc + dc04: 080c11c6 stmeqda ip, {r1, r2, r6, r7, r8, ip} + dc08: e1a03000 mov r3, r0 + dc0c: ebf5d8db bl 0xffd83f80 + dc10: 080c11c4 stmeqda ip, {r2, r6, r7, r8, ip} + dc14: e3b04008 movs r4, #8 ; 0x8 + dc18: ebf5d8d8 bl 0xffd83f80 + dc1c: 080c11c6 stmeqda ip, {r1, r2, r6, r7, r8, ip} + dc20: e1a01004 mov r1, r4 + dc24: e0144003 ands r4, r4, r3 + dc28: ebf5d8d4 bl 0xffd83f80 + dc2c: 080c11c8 stmeqda ip, {r3, r6, r7, r8, ip} + dc30: e2870020 add r0, r7, #32 ; 0x20 + dc34: ebf5d737 bl 0xffd83918 + dc38: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + dc3c: e1a03000 mov r3, r0 + dc40: ebf5d8ce bl 0xffd83f80 + dc44: 080c11ca stmeqda ip, {r1, r3, r6, r7, r8, ip} + dc48: e1a01003 mov r1, r3 + dc4c: e1933004 orrs r3, r3, r4 + dc50: ebf5d8ca bl 0xffd83f80 + dc54: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + dc58: e59d0434 ldr r0, [sp, #1076] + dc5c: e2800f03 add r0, r0, #12 ; 0xc + dc60: ebf5d72c bl 0xffd83918 + dc64: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + dc68: e1a05000 mov r5, r0 + dc6c: ebf5d8c3 bl 0xffd83f80 + dc70: 080c11ce stmeqda ip, {r1, r2, r3, r6, r7, r8, ip} + dc74: e2850000 add r0, r5, #0 ; 0x0 + dc78: e1a01003 mov r1, r3 + dc7c: ebf5d613 bl 0xffd834d0 + dc80: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + dc84: ebf5d8bd bl 0xffd83f80 + dc88: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + dc8c: e3b030c0 movs r3, #192 ; 0xc0 + dc90: ebf5d8ba bl 0xffd83f80 + dc94: 080c11d2 stmeqda ip, {r1, r4, r6, r7, r8, ip} + dc98: e287001a add r0, r7, #26 ; 0x1a + dc9c: ebf5d6c6 bl 0xffd837bc + dca0: 080c11d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, ip} + dca4: e1a04000 mov r4, r0 + dca8: ebf5d8b4 bl 0xffd83f80 + dcac: 080c11d4 stmeqda ip, {r2, r4, r6, r7, r8, ip} + dcb0: e1a01003 mov r1, r3 + dcb4: e0133004 ands r3, r3, r4 + dcb8: ebf5d8b0 bl 0xffd83f80 + dcbc: 080c11d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, ip} + dcc0: e1a01007 mov r1, r7 + dcc4: e2974000 adds r4, r7, #0 ; 0x0 + dcc8: ebf5d8ac bl 0xffd83f80 + dccc: 080c11d8 stmeqda ip, {r3, r4, r6, r7, r8, ip} + dcd0: e1a01004 mov r1, r4 + dcd4: e2944021 adds r4, r4, #33 ; 0x21 + dcd8: ebf5d8a8 bl 0xffd83f80 + dcdc: 080c11da stmeqda ip, {r1, r3, r4, r6, r7, r8, ip} + dce0: e2840000 add r0, r4, #0 ; 0x0 + dce4: ebf5d6b4 bl 0xffd837bc + dce8: 080c11de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, ip} + dcec: e1a04000 mov r4, r0 + dcf0: ebf5d8a2 bl 0xffd83f80 + dcf4: 080c11dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip} + dcf8: e1a01004 mov r1, r4 + dcfc: e0943003 adds r3, r4, r3 + dd00: ebf5d89e bl 0xffd83f80 + dd04: 080c11de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, ip} + dd08: e287001a add r0, r7, #26 ; 0x1a + dd0c: e1a01003 mov r1, r3 + dd10: ebf5d5ee bl 0xffd834d0 + dd14: 080c11e0 stmeqda ip, {r5, r6, r7, r8, ip} + dd18: ebf5d898 bl 0xffd83f80 + dd1c: 080c11e0 stmeqda ip, {r5, r6, r7, r8, ip} + dd20: e3b050ff movs r5, #255 ; 0xff + dd24: ebf5d895 bl 0xffd83f80 + dd28: 080c11e2 stmeqda ip, {r1, r5, r6, r7, r8, ip} + dd2c: e1a01003 mov r1, r3 + dd30: e0133005 ands r3, r3, r5 + dd34: ebf5d891 bl 0xffd83f80 + dd38: 080c11e4 stmeqda ip, {r2, r5, r6, r7, r8, ip} + dd3c: e59d0434 ldr r0, [sp, #1076] + dd40: e2800f04 add r0, r0, #16 ; 0x10 + dd44: ebf5d6f3 bl 0xffd83918 + dd48: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + dd4c: e1a04000 mov r4, r0 + dd50: ebf5d88a bl 0xffd83f80 + dd54: 080c11e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, ip} + dd58: e2840000 add r0, r4, #0 ; 0x0 + dd5c: e1a01003 mov r1, r3 + dd60: ebf5d5da bl 0xffd834d0 + dd64: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + dd68: ebf5d884 bl 0xffd83f80 + dd6c: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + dd70: e3b03001 movs r3, #1 ; 0x1 + dd74: ebf5d881 bl 0xffd83f80 + dd78: 080c11ea stmeqda ip, {r1, r3, r5, r6, r7, r8, ip} + dd7c: e287001d add r0, r7, #29 ; 0x1d + dd80: ebf5d68d bl 0xffd837bc + dd84: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + dd88: e1a05000 mov r5, r0 + dd8c: ebf5d87b bl 0xffd83f80 + dd90: 080c11ec stmeqda ip, {r2, r3, r5, r6, r7, r8, ip} + dd94: e1a01003 mov r1, r3 + dd98: e0133005 ands r3, r3, r5 + dd9c: ebf5d877 bl 0xffd83f80 + dda0: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + dda4: e3530000 cmp r3, #0 ; 0x0 + dda8: ebf5d874 bl 0xffd83f80 + ddac: 080c11f0 stmeqda ip, {r4, r5, r6, r7, r8, ip} + ddb0: e28cc05e add ip, ip, #94 ; 0x5e + ddb4: 1a000004 bne 0xddcc + ddb8: e1a00fac mov r0, ip, lsr #31 + ddbc: e08ff100 add pc, pc, r0, lsl #2 + ddc0: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + ddc4: ebf5d462 bl 0xffd82f54 + ddc8: eafffe41 b 0xd6d4 + ddcc: ebf5d86b bl 0xffd83f80 + ddd0: 080c11f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, ip} + ddd4: e3a00e23 mov r0, #560 ; 0x230 + ddd8: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + dddc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + dde0: ebf5d6cc bl 0xffd83918 + dde4: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + dde8: e1a04000 mov r4, r0 + ddec: ebf5d863 bl 0xffd83f80 + ddf0: 080c11f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, ip} + ddf4: e2840000 add r0, r4, #0 ; 0x0 + ddf8: ebf5d66f bl 0xffd837bc + ddfc: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + de00: e1a03000 mov r3, r0 + de04: ebf5d85d bl 0xffd83f80 + de08: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + de0c: e287001c add r0, r7, #28 ; 0x1c + de10: ebf5d669 bl 0xffd837bc + de14: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + de18: e1a05000 mov r5, r0 + de1c: ebf5d857 bl 0xffd83f80 + de20: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + de24: e1a01003 mov r1, r3 + de28: e1d33005 bics r3, r3, r5 + de2c: ebf5d853 bl 0xffd83f80 + de30: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + de34: e287001b add r0, r7, #27 ; 0x1b + de38: ebf5d65f bl 0xffd837bc + de3c: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + de40: e1a05000 mov r5, r0 + de44: ebf5d84d bl 0xffd83f80 + de48: 080c11fc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, ip} + de4c: e1a01003 mov r1, r3 + de50: e1933005 orrs r3, r3, r5 + de54: ebf5d849 bl 0xffd83f80 + de58: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + de5c: e2840000 add r0, r4, #0 ; 0x0 + de60: e1a01003 mov r1, r3 + de64: ebf5d599 bl 0xffd834d0 + de68: 080c1200 stmeqda ip, {r9, ip} + de6c: ebf5d843 bl 0xffd83f80 + de70: 080c1200 stmeqda ip, {r9, ip} + de74: e59d1418 ldr r1, [sp, #1048] + de78: e3510003 cmp r1, #3 ; 0x3 + de7c: ebf5d83f bl 0xffd83f80 + de80: 080c1202 stmeqda ip, {r1, r9, ip} + de84: e28cc024 add ip, ip, #36 ; 0x24 + de88: 0a000004 beq 0xdea0 + de8c: e1a00fac mov r0, ip, lsr #31 + de90: e08ff100 add pc, pc, r0, lsl #2 + de94: 080c1238 stmeqda ip, {r3, r4, r5, r9, ip} + de98: ebf5d42d bl 0xffd82f54 + de9c: eafffe7d b 0xd898 + dea0: ebf5d836 bl 0xffd83f80 + dea4: 080c1204 stmeqda ip, {r2, r9, ip} + dea8: e3a00f8d mov r0, #564 ; 0x234 + deac: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + deb0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + deb4: ebf5d697 bl 0xffd83918 + deb8: 080c1208 stmeqda ip, {r3, r9, ip} + debc: e1a03000 mov r3, r0 + dec0: ebf5d82e bl 0xffd83f80 + dec4: 080c1206 stmeqda ip, {r1, r2, r9, ip} + dec8: e2870009 add r0, r7, #9 ; 0x9 + decc: ebf5d63a bl 0xffd837bc + ded0: 080c120a stmeqda ip, {r1, r3, r9, ip} + ded4: e1a04000 mov r4, r0 + ded8: ebf5d828 bl 0xffd83f80 + dedc: 080c1208 stmeqda ip, {r3, r9, ip} + dee0: e1a01004 mov r1, r4 + dee4: e0943003 adds r3, r4, r3 + dee8: ebf5d824 bl 0xffd83f80 + deec: 080c120a stmeqda ip, {r1, r3, r9, ip} + def0: e2830000 add r0, r3, #0 ; 0x0 + def4: ebf5d630 bl 0xffd837bc + def8: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + defc: e1a03000 mov r3, r0 + df00: ebf5d81e bl 0xffd83f80 + df04: 080c120c stmeqda ip, {r2, r3, r9, ip} + df08: e59d1428 ldr r1, [sp, #1064] + df0c: e1a05001 mov r5, r1 + df10: ebf5d81a bl 0xffd83f80 + df14: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + df18: e2850000 add r0, r5, #0 ; 0x0 + df1c: e1a01003 mov r1, r3 + df20: ebf5d56a bl 0xffd834d0 + df24: 080c1210 stmeqda ip, {r4, r9, ip} + df28: ebf5d814 bl 0xffd83f80 + df2c: 080c1210 stmeqda ip, {r4, r9, ip} + df30: e3b04080 movs r4, #128 ; 0x80 + df34: ebf5d811 bl 0xffd83f80 + df38: 080c1212 stmeqda ip, {r1, r4, r9, ip} + df3c: e1a01004 mov r1, r4 + df40: e2943000 adds r3, r4, #0 ; 0x0 + df44: ebf5d80d bl 0xffd83f80 + df48: 080c1214 stmeqda ip, {r2, r4, r9, ip} + df4c: e287001a add r0, r7, #26 ; 0x1a + df50: ebf5d619 bl 0xffd837bc + df54: 080c1218 stmeqda ip, {r3, r4, r9, ip} + df58: e1a05000 mov r5, r0 + df5c: ebf5d807 bl 0xffd83f80 + df60: 080c1216 stmeqda ip, {r1, r2, r4, r9, ip} + df64: e1a01003 mov r1, r3 + df68: e0133005 ands r3, r3, r5 + df6c: ebf5d803 bl 0xffd83f80 + df70: 080c1218 stmeqda ip, {r3, r4, r9, ip} + df74: e3530000 cmp r3, #0 ; 0x0 + df78: ebf5d800 bl 0xffd83f80 + df7c: 080c121a stmeqda ip, {r1, r3, r4, r9, ip} + df80: e28cc02d add ip, ip, #45 ; 0x2d + df84: 1a000004 bne 0xdf9c + df88: e1a00fac mov r0, ip, lsr #31 + df8c: e08ff100 add pc, pc, r0, lsl #2 + df90: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + df94: ebf5d3ee bl 0xffd82f54 + df98: eafffdcd b 0xd6d4 + df9c: ebf5d7f7 bl 0xffd83f80 + dfa0: 080c121c stmeqda ip, {r2, r3, r4, r9, ip} + dfa4: e59d0434 ldr r0, [sp, #1076] + dfa8: e2800f02 add r0, r0, #8 ; 0x8 + dfac: ebf5d659 bl 0xffd83918 + dfb0: 080c1220 stmeqda ip, {r5, r9, ip} + dfb4: e1a03000 mov r3, r0 + dfb8: ebf5d7f0 bl 0xffd83f80 + dfbc: 080c121e stmeqda ip, {r1, r2, r3, r4, r9, ip} + dfc0: e2830000 add r0, r3, #0 ; 0x0 + dfc4: e1a01004 mov r1, r4 + dfc8: ebf5d540 bl 0xffd834d0 + dfcc: 080c1220 stmeqda ip, {r5, r9, ip} + dfd0: ebf5d7ea bl 0xffd83f80 + dfd4: 080c1220 stmeqda ip, {r5, r9, ip} + dfd8: e287001a add r0, r7, #26 ; 0x1a + dfdc: ebf5d5f6 bl 0xffd837bc + dfe0: 080c1224 stmeqda ip, {r2, r5, r9, ip} + dfe4: e1a03000 mov r3, r0 + dfe8: ebf5d7e4 bl 0xffd83f80 + dfec: 080c1222 stmeqda ip, {r1, r5, r9, ip} + dff0: e59d0434 ldr r0, [sp, #1076] + dff4: e2800f04 add r0, r0, #16 ; 0x10 + dff8: ebf5d646 bl 0xffd83918 + dffc: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e000: e1a04000 mov r4, r0 + e004: ebf5d7dd bl 0xffd83f80 + e008: 080c1224 stmeqda ip, {r2, r5, r9, ip} + e00c: e2840000 add r0, r4, #0 ; 0x0 + e010: e1a01003 mov r1, r3 + e014: ebf5d52d bl 0xffd834d0 + e018: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e01c: ebf5d7d7 bl 0xffd83f80 + e020: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e024: e3b0307f movs r3, #127 ; 0x7f + e028: ebf5d7d4 bl 0xffd83f80 + e02c: 080c1228 stmeqda ip, {r3, r5, r9, ip} + e030: e287001a add r0, r7, #26 ; 0x1a + e034: ebf5d5e0 bl 0xffd837bc + e038: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + e03c: e1a05000 mov r5, r0 + e040: ebf5d7ce bl 0xffd83f80 + e044: 080c122a stmeqda ip, {r1, r3, r5, r9, ip} + e048: e1a01003 mov r1, r3 + e04c: e0133005 ands r3, r3, r5 + e050: ebf5d7ca bl 0xffd83f80 + e054: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + e058: e287001a add r0, r7, #26 ; 0x1a + e05c: e1a01003 mov r1, r3 + e060: ebf5d51a bl 0xffd834d0 + e064: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + e068: ebf5d7c4 bl 0xffd83f80 + e06c: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + e070: e28cc029 add ip, ip, #41 ; 0x29 + e074: e1a00fac mov r0, ip, lsr #31 + e078: e08ff100 add pc, pc, r0, lsl #2 + e07c: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + e080: ebf5d3b3 bl 0xffd82f54 + e084: eafffd92 b 0xd6d4 + e088: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + e08c: 00000000 andeq r0, r0, r0 + e090: ebf5d7ba bl 0xffd83f80 + e094: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + e098: e59d0434 ldr r0, [sp, #1076] + e09c: e2800f03 add r0, r0, #12 ; 0xc + e0a0: ebf5d61c bl 0xffd83918 + e0a4: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + e0a8: e1a05000 mov r5, r0 + e0ac: ebf5d7b3 bl 0xffd83f80 + e0b0: 080c11ce stmeqda ip, {r1, r2, r3, r6, r7, r8, ip} + e0b4: e2850000 add r0, r5, #0 ; 0x0 + e0b8: e1a01003 mov r1, r3 + e0bc: ebf5d503 bl 0xffd834d0 + e0c0: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + e0c4: ebf5d7ad bl 0xffd83f80 + e0c8: 080c11d0 stmeqda ip, {r4, r6, r7, r8, ip} + e0cc: e3b030c0 movs r3, #192 ; 0xc0 + e0d0: ebf5d7aa bl 0xffd83f80 + e0d4: 080c11d2 stmeqda ip, {r1, r4, r6, r7, r8, ip} + e0d8: e287001a add r0, r7, #26 ; 0x1a + e0dc: ebf5d5b6 bl 0xffd837bc + e0e0: 080c11d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, ip} + e0e4: e1a04000 mov r4, r0 + e0e8: ebf5d7a4 bl 0xffd83f80 + e0ec: 080c11d4 stmeqda ip, {r2, r4, r6, r7, r8, ip} + e0f0: e1a01003 mov r1, r3 + e0f4: e0133004 ands r3, r3, r4 + e0f8: ebf5d7a0 bl 0xffd83f80 + e0fc: 080c11d6 stmeqda ip, {r1, r2, r4, r6, r7, r8, ip} + e100: e1a01007 mov r1, r7 + e104: e2974000 adds r4, r7, #0 ; 0x0 + e108: ebf5d79c bl 0xffd83f80 + e10c: 080c11d8 stmeqda ip, {r3, r4, r6, r7, r8, ip} + e110: e1a01004 mov r1, r4 + e114: e2944021 adds r4, r4, #33 ; 0x21 + e118: ebf5d798 bl 0xffd83f80 + e11c: 080c11da stmeqda ip, {r1, r3, r4, r6, r7, r8, ip} + e120: e2840000 add r0, r4, #0 ; 0x0 + e124: ebf5d5a4 bl 0xffd837bc + e128: 080c11de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, ip} + e12c: e1a04000 mov r4, r0 + e130: ebf5d792 bl 0xffd83f80 + e134: 080c11dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip} + e138: e1a01004 mov r1, r4 + e13c: e0943003 adds r3, r4, r3 + e140: ebf5d78e bl 0xffd83f80 + e144: 080c11de stmeqda ip, {r1, r2, r3, r4, r6, r7, r8, ip} + e148: e287001a add r0, r7, #26 ; 0x1a + e14c: e1a01003 mov r1, r3 + e150: ebf5d4de bl 0xffd834d0 + e154: 080c11e0 stmeqda ip, {r5, r6, r7, r8, ip} + e158: ebf5d788 bl 0xffd83f80 + e15c: 080c11e0 stmeqda ip, {r5, r6, r7, r8, ip} + e160: e3b050ff movs r5, #255 ; 0xff + e164: ebf5d785 bl 0xffd83f80 + e168: 080c11e2 stmeqda ip, {r1, r5, r6, r7, r8, ip} + e16c: e1a01003 mov r1, r3 + e170: e0133005 ands r3, r3, r5 + e174: ebf5d781 bl 0xffd83f80 + e178: 080c11e4 stmeqda ip, {r2, r5, r6, r7, r8, ip} + e17c: e59d0434 ldr r0, [sp, #1076] + e180: e2800f04 add r0, r0, #16 ; 0x10 + e184: ebf5d5e3 bl 0xffd83918 + e188: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + e18c: e1a04000 mov r4, r0 + e190: ebf5d77a bl 0xffd83f80 + e194: 080c11e6 stmeqda ip, {r1, r2, r5, r6, r7, r8, ip} + e198: e2840000 add r0, r4, #0 ; 0x0 + e19c: e1a01003 mov r1, r3 + e1a0: ebf5d4ca bl 0xffd834d0 + e1a4: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + e1a8: ebf5d774 bl 0xffd83f80 + e1ac: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + e1b0: e3b03001 movs r3, #1 ; 0x1 + e1b4: ebf5d771 bl 0xffd83f80 + e1b8: 080c11ea stmeqda ip, {r1, r3, r5, r6, r7, r8, ip} + e1bc: e287001d add r0, r7, #29 ; 0x1d + e1c0: ebf5d57d bl 0xffd837bc + e1c4: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + e1c8: e1a05000 mov r5, r0 + e1cc: ebf5d76b bl 0xffd83f80 + e1d0: 080c11ec stmeqda ip, {r2, r3, r5, r6, r7, r8, ip} + e1d4: e1a01003 mov r1, r3 + e1d8: e0133005 ands r3, r3, r5 + e1dc: ebf5d767 bl 0xffd83f80 + e1e0: 080c11ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r8, ip} + e1e4: e3530000 cmp r3, #0 ; 0x0 + e1e8: ebf5d764 bl 0xffd83f80 + e1ec: 080c11f0 stmeqda ip, {r4, r5, r6, r7, r8, ip} + e1f0: e28cc046 add ip, ip, #70 ; 0x46 + e1f4: 1a000004 bne 0xe20c + e1f8: e1a00fac mov r0, ip, lsr #31 + e1fc: e08ff100 add pc, pc, r0, lsl #2 + e200: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + e204: ebf5d352 bl 0xffd82f54 + e208: eafffd31 b 0xd6d4 + e20c: ebf5d75b bl 0xffd83f80 + e210: 080c11f2 stmeqda ip, {r1, r4, r5, r6, r7, r8, ip} + e214: e3a00e23 mov r0, #560 ; 0x230 + e218: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + e21c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e220: ebf5d5bc bl 0xffd83918 + e224: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + e228: e1a04000 mov r4, r0 + e22c: ebf5d753 bl 0xffd83f80 + e230: 080c11f4 stmeqda ip, {r2, r4, r5, r6, r7, r8, ip} + e234: e2840000 add r0, r4, #0 ; 0x0 + e238: ebf5d55f bl 0xffd837bc + e23c: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + e240: e1a03000 mov r3, r0 + e244: ebf5d74d bl 0xffd83f80 + e248: 080c11f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, ip} + e24c: e287001c add r0, r7, #28 ; 0x1c + e250: ebf5d559 bl 0xffd837bc + e254: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + e258: e1a05000 mov r5, r0 + e25c: ebf5d747 bl 0xffd83f80 + e260: 080c11f8 stmeqda ip, {r3, r4, r5, r6, r7, r8, ip} + e264: e1a01003 mov r1, r3 + e268: e1d33005 bics r3, r3, r5 + e26c: ebf5d743 bl 0xffd83f80 + e270: 080c11fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, ip} + e274: e287001b add r0, r7, #27 ; 0x1b + e278: ebf5d54f bl 0xffd837bc + e27c: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + e280: e1a05000 mov r5, r0 + e284: ebf5d73d bl 0xffd83f80 + e288: 080c11fc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, ip} + e28c: e1a01003 mov r1, r3 + e290: e1933005 orrs r3, r3, r5 + e294: ebf5d739 bl 0xffd83f80 + e298: 080c11fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, ip} + e29c: e2840000 add r0, r4, #0 ; 0x0 + e2a0: e1a01003 mov r1, r3 + e2a4: ebf5d489 bl 0xffd834d0 + e2a8: 080c1200 stmeqda ip, {r9, ip} + e2ac: ebf5d733 bl 0xffd83f80 + e2b0: 080c1200 stmeqda ip, {r9, ip} + e2b4: e59d1418 ldr r1, [sp, #1048] + e2b8: e3510003 cmp r1, #3 ; 0x3 + e2bc: ebf5d72f bl 0xffd83f80 + e2c0: 080c1202 stmeqda ip, {r1, r9, ip} + e2c4: e28cc024 add ip, ip, #36 ; 0x24 + e2c8: 0a000004 beq 0xe2e0 + e2cc: e1a00fac mov r0, ip, lsr #31 + e2d0: e08ff100 add pc, pc, r0, lsl #2 + e2d4: 080c1238 stmeqda ip, {r3, r4, r5, r9, ip} + e2d8: ebf5d31d bl 0xffd82f54 + e2dc: eafffd6d b 0xd898 + e2e0: ebf5d726 bl 0xffd83f80 + e2e4: 080c1204 stmeqda ip, {r2, r9, ip} + e2e8: e3a00f8d mov r0, #564 ; 0x234 + e2ec: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + e2f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e2f4: ebf5d587 bl 0xffd83918 + e2f8: 080c1208 stmeqda ip, {r3, r9, ip} + e2fc: e1a03000 mov r3, r0 + e300: ebf5d71e bl 0xffd83f80 + e304: 080c1206 stmeqda ip, {r1, r2, r9, ip} + e308: e2870009 add r0, r7, #9 ; 0x9 + e30c: ebf5d52a bl 0xffd837bc + e310: 080c120a stmeqda ip, {r1, r3, r9, ip} + e314: e1a04000 mov r4, r0 + e318: ebf5d718 bl 0xffd83f80 + e31c: 080c1208 stmeqda ip, {r3, r9, ip} + e320: e1a01004 mov r1, r4 + e324: e0943003 adds r3, r4, r3 + e328: ebf5d714 bl 0xffd83f80 + e32c: 080c120a stmeqda ip, {r1, r3, r9, ip} + e330: e2830000 add r0, r3, #0 ; 0x0 + e334: ebf5d520 bl 0xffd837bc + e338: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + e33c: e1a03000 mov r3, r0 + e340: ebf5d70e bl 0xffd83f80 + e344: 080c120c stmeqda ip, {r2, r3, r9, ip} + e348: e59d1428 ldr r1, [sp, #1064] + e34c: e1a05001 mov r5, r1 + e350: ebf5d70a bl 0xffd83f80 + e354: 080c120e stmeqda ip, {r1, r2, r3, r9, ip} + e358: e2850000 add r0, r5, #0 ; 0x0 + e35c: e1a01003 mov r1, r3 + e360: ebf5d45a bl 0xffd834d0 + e364: 080c1210 stmeqda ip, {r4, r9, ip} + e368: ebf5d704 bl 0xffd83f80 + e36c: 080c1210 stmeqda ip, {r4, r9, ip} + e370: e3b04080 movs r4, #128 ; 0x80 + e374: ebf5d701 bl 0xffd83f80 + e378: 080c1212 stmeqda ip, {r1, r4, r9, ip} + e37c: e1a01004 mov r1, r4 + e380: e2943000 adds r3, r4, #0 ; 0x0 + e384: ebf5d6fd bl 0xffd83f80 + e388: 080c1214 stmeqda ip, {r2, r4, r9, ip} + e38c: e287001a add r0, r7, #26 ; 0x1a + e390: ebf5d509 bl 0xffd837bc + e394: 080c1218 stmeqda ip, {r3, r4, r9, ip} + e398: e1a05000 mov r5, r0 + e39c: ebf5d6f7 bl 0xffd83f80 + e3a0: 080c1216 stmeqda ip, {r1, r2, r4, r9, ip} + e3a4: e1a01003 mov r1, r3 + e3a8: e0133005 ands r3, r3, r5 + e3ac: ebf5d6f3 bl 0xffd83f80 + e3b0: 080c1218 stmeqda ip, {r3, r4, r9, ip} + e3b4: e3530000 cmp r3, #0 ; 0x0 + e3b8: ebf5d6f0 bl 0xffd83f80 + e3bc: 080c121a stmeqda ip, {r1, r3, r4, r9, ip} + e3c0: e28cc02d add ip, ip, #45 ; 0x2d + e3c4: 1a000004 bne 0xe3dc + e3c8: e1a00fac mov r0, ip, lsr #31 + e3cc: e08ff100 add pc, pc, r0, lsl #2 + e3d0: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + e3d4: ebf5d2de bl 0xffd82f54 + e3d8: eafffcbd b 0xd6d4 + e3dc: ebf5d6e7 bl 0xffd83f80 + e3e0: 080c121c stmeqda ip, {r2, r3, r4, r9, ip} + e3e4: e59d0434 ldr r0, [sp, #1076] + e3e8: e2800f02 add r0, r0, #8 ; 0x8 + e3ec: ebf5d549 bl 0xffd83918 + e3f0: 080c1220 stmeqda ip, {r5, r9, ip} + e3f4: e1a03000 mov r3, r0 + e3f8: ebf5d6e0 bl 0xffd83f80 + e3fc: 080c121e stmeqda ip, {r1, r2, r3, r4, r9, ip} + e400: e2830000 add r0, r3, #0 ; 0x0 + e404: e1a01004 mov r1, r4 + e408: ebf5d430 bl 0xffd834d0 + e40c: 080c1220 stmeqda ip, {r5, r9, ip} + e410: ebf5d6da bl 0xffd83f80 + e414: 080c1220 stmeqda ip, {r5, r9, ip} + e418: e287001a add r0, r7, #26 ; 0x1a + e41c: ebf5d4e6 bl 0xffd837bc + e420: 080c1224 stmeqda ip, {r2, r5, r9, ip} + e424: e1a03000 mov r3, r0 + e428: ebf5d6d4 bl 0xffd83f80 + e42c: 080c1222 stmeqda ip, {r1, r5, r9, ip} + e430: e59d0434 ldr r0, [sp, #1076] + e434: e2800f04 add r0, r0, #16 ; 0x10 + e438: ebf5d536 bl 0xffd83918 + e43c: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e440: e1a04000 mov r4, r0 + e444: ebf5d6cd bl 0xffd83f80 + e448: 080c1224 stmeqda ip, {r2, r5, r9, ip} + e44c: e2840000 add r0, r4, #0 ; 0x0 + e450: e1a01003 mov r1, r3 + e454: ebf5d41d bl 0xffd834d0 + e458: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e45c: ebf5d6c7 bl 0xffd83f80 + e460: 080c1226 stmeqda ip, {r1, r2, r5, r9, ip} + e464: e3b0307f movs r3, #127 ; 0x7f + e468: ebf5d6c4 bl 0xffd83f80 + e46c: 080c1228 stmeqda ip, {r3, r5, r9, ip} + e470: e287001a add r0, r7, #26 ; 0x1a + e474: ebf5d4d0 bl 0xffd837bc + e478: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + e47c: e1a05000 mov r5, r0 + e480: ebf5d6be bl 0xffd83f80 + e484: 080c122a stmeqda ip, {r1, r3, r5, r9, ip} + e488: e1a01003 mov r1, r3 + e48c: e0133005 ands r3, r3, r5 + e490: ebf5d6ba bl 0xffd83f80 + e494: 080c122c stmeqda ip, {r2, r3, r5, r9, ip} + e498: e287001a add r0, r7, #26 ; 0x1a + e49c: e1a01003 mov r1, r3 + e4a0: ebf5d40a bl 0xffd834d0 + e4a4: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + e4a8: ebf5d6b4 bl 0xffd83f80 + e4ac: 080c122e stmeqda ip, {r1, r2, r3, r5, r9, ip} + e4b0: e28cc029 add ip, ip, #41 ; 0x29 + e4b4: e1a00fac mov r0, ip, lsr #31 + e4b8: e08ff100 add pc, pc, r0, lsl #2 + e4bc: 080c1254 stmeqda ip, {r2, r4, r6, r9, ip} + e4c0: ebf5d2a3 bl 0xffd82f54 + e4c4: eafffc82 b 0xd6d4 + e4c8: 080c11a4 stmeqda ip, {r2, r5, r7, r8, ip} + e4cc: 00000000 andeq r0, r0, r0 + e4d0: ebf5d6aa bl 0xffd83f80 + e4d4: 080c11a4 stmeqda ip, {r2, r5, r7, r8, ip} + e4d8: e353007f cmp r3, #127 ; 0x7f + e4dc: ebf5d6a7 bl 0xffd83f80 + e4e0: 080c11a6 stmeqda ip, {r1, r2, r5, r7, r8, ip} + e4e4: e28cc006 add ip, ip, #6 ; 0x6 + e4e8: da000004 ble 0xe500 + e4ec: e1a00fac mov r0, ip, lsr #31 + e4f0: e08ff100 add pc, pc, r0, lsl #2 + e4f4: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e4f8: ebf5d295 bl 0xffd82f54 + e4fc: ea00001c b 0xe574 + e500: ebf5d69e bl 0xffd83f80 + e504: 080c11a8 stmeqda ip, {r3, r5, r7, r8, ip} + e508: e2870020 add r0, r7, #32 ; 0x20 + e50c: ebf5d501 bl 0xffd83918 + e510: 080c11ac stmeqda ip, {r2, r3, r5, r7, r8, ip} + e514: e1a03000 mov r3, r0 + e518: ebf5d698 bl 0xffd83f80 + e51c: 080c11aa stmeqda ip, {r1, r3, r5, r7, r8, ip} + e520: e1a01003 mov r1, r3 + e524: e2933001 adds r3, r3, #1 ; 0x1 + e528: ebf5d694 bl 0xffd83f80 + e52c: 080c11ac stmeqda ip, {r2, r3, r5, r7, r8, ip} + e530: e3a00f6f mov r0, #444 ; 0x1bc + e534: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + e538: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e53c: ebf5d4f5 bl 0xffd83918 + e540: 080c11b0 stmeqda ip, {r4, r5, r7, r8, ip} + e544: e1a04000 mov r4, r0 + e548: ebf5d68c bl 0xffd83f80 + e54c: 080c11ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip} + e550: e1a01003 mov r1, r3 + e554: e0133004 ands r3, r3, r4 + e558: ebf5d688 bl 0xffd83f80 + e55c: 080c11b0 stmeqda ip, {r4, r5, r7, r8, ip} + e560: e2870020 add r0, r7, #32 ; 0x20 + e564: e1a01003 mov r1, r3 + e568: ebf5d417 bl 0xffd835cc + e56c: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e570: e28cc014 add ip, ip, #20 ; 0x14 + e574: ebf5d681 bl 0xffd83f80 + e578: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e57c: e59d1418 ldr r1, [sp, #1048] + e580: e3510004 cmp r1, #4 ; 0x4 + e584: ebf5d67d bl 0xffd83f80 + e588: 080c11b4 stmeqda ip, {r2, r4, r5, r7, r8, ip} + e58c: e28cc006 add ip, ip, #6 ; 0x6 + e590: 1a000004 bne 0xe5a8 + e594: e1a00fac mov r0, ip, lsr #31 + e598: e08ff100 add pc, pc, r0, lsl #2 + e59c: 080c11c0 stmeqda ip, {r6, r7, r8, ip} + e5a0: ebf5d26b bl 0xffd82f54 + e5a4: eafffd8b b 0xdbd8 + e5a8: ebf5d674 bl 0xffd83f80 + e5ac: 080c11b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, ip} + e5b0: e2870020 add r0, r7, #32 ; 0x20 + e5b4: ebf5d4d7 bl 0xffd83918 + e5b8: 080c11ba stmeqda ip, {r1, r3, r4, r5, r7, r8, ip} + e5bc: e1a03000 mov r3, r0 + e5c0: ebf5d66e bl 0xffd83f80 + e5c4: 080c11b8 stmeqda ip, {r3, r4, r5, r7, r8, ip} + e5c8: e28cc008 add ip, ip, #8 ; 0x8 + e5cc: e1a00fac mov r0, ip, lsr #31 + e5d0: e08ff100 add pc, pc, r0, lsl #2 + e5d4: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + e5d8: ebf5d25d bl 0xffd82f54 + e5dc: eafffeab b 0xe090 + e5e0: 080c11ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip} + e5e4: 00000000 andeq r0, r0, r0 + e5e8: ebf5d664 bl 0xffd83f80 + e5ec: 080c11ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip} + e5f0: e1a01003 mov r1, r3 + e5f4: e0133004 ands r3, r3, r4 + e5f8: ebf5d660 bl 0xffd83f80 + e5fc: 080c11b0 stmeqda ip, {r4, r5, r7, r8, ip} + e600: e2870020 add r0, r7, #32 ; 0x20 + e604: e1a01003 mov r1, r3 + e608: ebf5d3ef bl 0xffd835cc + e60c: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e610: ebf5d65a bl 0xffd83f80 + e614: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e618: e59d1418 ldr r1, [sp, #1048] + e61c: e3510004 cmp r1, #4 ; 0x4 + e620: ebf5d656 bl 0xffd83f80 + e624: 080c11b4 stmeqda ip, {r2, r4, r5, r7, r8, ip} + e628: e28cc00d add ip, ip, #13 ; 0xd + e62c: 1a000004 bne 0xe644 + e630: e1a00fac mov r0, ip, lsr #31 + e634: e08ff100 add pc, pc, r0, lsl #2 + e638: 080c11c0 stmeqda ip, {r6, r7, r8, ip} + e63c: ebf5d244 bl 0xffd82f54 + e640: eafffd64 b 0xdbd8 + e644: ebf5d64d bl 0xffd83f80 + e648: 080c11b6 stmeqda ip, {r1, r2, r4, r5, r7, r8, ip} + e64c: e2870020 add r0, r7, #32 ; 0x20 + e650: ebf5d4b0 bl 0xffd83918 + e654: 080c11ba stmeqda ip, {r1, r3, r4, r5, r7, r8, ip} + e658: e1a03000 mov r3, r0 + e65c: ebf5d647 bl 0xffd83f80 + e660: 080c11b8 stmeqda ip, {r3, r4, r5, r7, r8, ip} + e664: e28cc008 add ip, ip, #8 ; 0x8 + e668: e1a00fac mov r0, ip, lsr #31 + e66c: e08ff100 add pc, pc, r0, lsl #2 + e670: 080c11cc stmeqda ip, {r2, r3, r6, r7, r8, ip} + e674: ebf5d236 bl 0xffd82f54 + e678: eafffe84 b 0xe090 + e67c: 080c1152 stmeqda ip, {r1, r4, r6, r8, ip} + e680: 00000000 andeq r0, r0, r0 + e684: ebf5d63d bl 0xffd83f80 + e688: 080c1152 stmeqda ip, {r1, r4, r6, r8, ip} + e68c: e59d1418 ldr r1, [sp, #1048] + e690: e3510003 cmp r1, #3 ; 0x3 + e694: ebf5d639 bl 0xffd83f80 + e698: 080c1154 stmeqda ip, {r2, r4, r6, r8, ip} + e69c: e28cc006 add ip, ip, #6 ; 0x6 + e6a0: 1a000004 bne 0xe6b8 + e6a4: e1a00fac mov r0, ip, lsr #31 + e6a8: e08ff100 add pc, pc, r0, lsl #2 + e6ac: 080c1160 stmeqda ip, {r5, r6, r8, ip} + e6b0: ebf5d227 bl 0xffd82f54 + e6b4: ea000013 b 0xe708 + e6b8: ebf5d630 bl 0xffd83f80 + e6bc: 080c1156 stmeqda ip, {r1, r2, r4, r6, r8, ip} + e6c0: e59d1428 ldr r1, [sp, #1064] + e6c4: e1a03001 mov r3, r1 + e6c8: ebf5d62c bl 0xffd83f80 + e6cc: 080c1158 stmeqda ip, {r3, r4, r6, r8, ip} + e6d0: e2830000 add r0, r3, #0 ; 0x0 + e6d4: e1a01004 mov r1, r4 + e6d8: ebf5d37c bl 0xffd834d0 + e6dc: 080c115a stmeqda ip, {r1, r3, r4, r6, r8, ip} + e6e0: ebf5d626 bl 0xffd83f80 + e6e4: 080c115a stmeqda ip, {r1, r3, r4, r6, r8, ip} + e6e8: e28cc00a add ip, ip, #10 ; 0xa + e6ec: e1a00fac mov r0, ip, lsr #31 + e6f0: e08ff100 add pc, pc, r0, lsl #2 + e6f4: 080c1160 stmeqda ip, {r5, r6, r8, ip} + e6f8: ebf5d215 bl 0xffd82f54 + e6fc: ea000001 b 0xe708 + e700: 080c1160 stmeqda ip, {r5, r6, r8, ip} + e704: 00000000 andeq r0, r0, r0 + e708: ebf5d61c bl 0xffd83f80 + e70c: 080c1160 stmeqda ip, {r5, r6, r8, ip} + e710: e287000b add r0, r7, #11 ; 0xb + e714: ebf5d428 bl 0xffd837bc + e718: 080c1164 stmeqda ip, {r2, r5, r6, r8, ip} + e71c: e1a03000 mov r3, r0 + e720: ebf5d616 bl 0xffd83f80 + e724: 080c1162 stmeqda ip, {r1, r5, r6, r8, ip} + e728: e1a01003 mov r1, r3 + e72c: e2533001 subs r3, r3, #1 ; 0x1 + e730: ebf5d612 bl 0xffd83f80 + e734: 080c1164 stmeqda ip, {r2, r5, r6, r8, ip} + e738: e287000b add r0, r7, #11 ; 0xb + e73c: e1a01003 mov r1, r3 + e740: ebf5d362 bl 0xffd834d0 + e744: 080c1166 stmeqda ip, {r1, r2, r5, r6, r8, ip} + e748: ebf5d60c bl 0xffd83f80 + e74c: 080c1166 stmeqda ip, {r1, r2, r5, r6, r8, ip} + e750: e59d0434 ldr r0, [sp, #1076] + e754: e2800f00 add r0, r0, #0 ; 0x0 + e758: ebf5d46e bl 0xffd83918 + e75c: 080c116a stmeqda ip, {r1, r3, r5, r6, r8, ip} + e760: e1a04000 mov r4, r0 + e764: ebf5d605 bl 0xffd83f80 + e768: 080c1168 stmeqda ip, {r3, r5, r6, r8, ip} + e76c: e3540000 cmp r4, #0 ; 0x0 + e770: ebf5d602 bl 0xffd83f80 + e774: 080c116a stmeqda ip, {r1, r3, r5, r6, r8, ip} + e778: e28cc017 add ip, ip, #23 ; 0x17 + e77c: 0a000004 beq 0xe794 + e780: e1a00fac mov r0, ip, lsr #31 + e784: e08ff100 add pc, pc, r0, lsl #2 + e788: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + e78c: ebf5d1f0 bl 0xffd82f54 + e790: ea000012 b 0xe7e0 + e794: ebf5d5f9 bl 0xffd83f80 + e798: 080c116c stmeqda ip, {r2, r3, r5, r6, r8, ip} + e79c: e1a01004 mov r1, r4 + e7a0: e2544001 subs r4, r4, #1 ; 0x1 + e7a4: ebf5d5f5 bl 0xffd83f80 + e7a8: 080c116e stmeqda ip, {r1, r2, r3, r5, r6, r8, ip} + e7ac: e59d0434 ldr r0, [sp, #1076] + e7b0: e2800f00 add r0, r0, #0 ; 0x0 + e7b4: e1a01004 mov r1, r4 + e7b8: ebf5d383 bl 0xffd835cc + e7bc: 080c1170 stmeqda ip, {r4, r5, r6, r8, ip} + e7c0: ebf5d5ee bl 0xffd83f80 + e7c4: 080c1170 stmeqda ip, {r4, r5, r6, r8, ip} + e7c8: e28cc00a add ip, ip, #10 ; 0xa + e7cc: e1a00fac mov r0, ip, lsr #31 + e7d0: e08ff100 add pc, pc, r0, lsl #2 + e7d4: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + e7d8: ebf5d1dd bl 0xffd82f54 + e7dc: ea000074 b 0xe9b4 + e7e0: ebf5d5e6 bl 0xffd83f80 + e7e4: 080c1172 stmeqda ip, {r1, r4, r5, r6, r8, ip} + e7e8: e3b03002 movs r3, #2 ; 0x2 + e7ec: ebf5d5e3 bl 0xffd83f80 + e7f0: 080c1174 stmeqda ip, {r2, r4, r5, r6, r8, ip} + e7f4: e287001d add r0, r7, #29 ; 0x1d + e7f8: ebf5d3ef bl 0xffd837bc + e7fc: 080c1178 stmeqda ip, {r3, r4, r5, r6, r8, ip} + e800: e1a05000 mov r5, r0 + e804: ebf5d5dd bl 0xffd83f80 + e808: 080c1176 stmeqda ip, {r1, r2, r4, r5, r6, r8, ip} + e80c: e1a01003 mov r1, r3 + e810: e0133005 ands r3, r3, r5 + e814: ebf5d5d9 bl 0xffd83f80 + e818: 080c1178 stmeqda ip, {r3, r4, r5, r6, r8, ip} + e81c: e3530000 cmp r3, #0 ; 0x0 + e820: ebf5d5d6 bl 0xffd83f80 + e824: 080c117a stmeqda ip, {r1, r3, r4, r5, r6, r8, ip} + e828: e28cc011 add ip, ip, #17 ; 0x11 + e82c: 1a000004 bne 0xe844 + e830: e1a00fac mov r0, ip, lsr #31 + e834: e08ff100 add pc, pc, r0, lsl #2 + e838: 080c11e8 stmeqda ip, {r3, r5, r6, r7, r8, ip} + e83c: ebf5d1c4 bl 0xffd82f54 + e840: eafffad9 b 0xd3ac + e844: ebf5d5cd bl 0xffd83f80 + e848: 080c117c stmeqda ip, {r2, r3, r4, r5, r6, r8, ip} + e84c: e59d1418 ldr r1, [sp, #1048] + e850: e3510003 cmp r1, #3 ; 0x3 + e854: ebf5d5c9 bl 0xffd83f80 + e858: 080c117e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, ip} + e85c: e28cc006 add ip, ip, #6 ; 0x6 + e860: da000004 ble 0xe878 + e864: e1a00fac mov r0, ip, lsr #31 + e868: e08ff100 add pc, pc, r0, lsl #2 + e86c: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e870: ebf5d1b7 bl 0xffd82f54 + e874: eafffcba b 0xdb64 + e878: ebf5d5c0 bl 0xffd83f80 + e87c: 080c1180 stmeqda ip, {r7, r8, ip} + e880: e3b03008 movs r3, #8 ; 0x8 + e884: ebf5d5bd bl 0xffd83f80 + e888: 080c1182 stmeqda ip, {r1, r7, r8, ip} + e88c: e2870001 add r0, r7, #1 ; 0x1 + e890: ebf5d3c9 bl 0xffd837bc + e894: 080c1186 stmeqda ip, {r1, r2, r7, r8, ip} + e898: e1a04000 mov r4, r0 + e89c: ebf5d5b7 bl 0xffd83f80 + e8a0: 080c1184 stmeqda ip, {r2, r7, r8, ip} + e8a4: e1a01003 mov r1, r3 + e8a8: e0133004 ands r3, r3, r4 + e8ac: ebf5d5b3 bl 0xffd83f80 + e8b0: 080c1186 stmeqda ip, {r1, r2, r7, r8, ip} + e8b4: e3530000 cmp r3, #0 ; 0x0 + e8b8: ebf5d5b0 bl 0xffd83f80 + e8bc: 080c1188 stmeqda ip, {r3, r7, r8, ip} + e8c0: e28cc011 add ip, ip, #17 ; 0x11 + e8c4: 1a000004 bne 0xe8dc + e8c8: e1a00fac mov r0, ip, lsr #31 + e8cc: e08ff100 add pc, pc, r0, lsl #2 + e8d0: 080c11b2 stmeqda ip, {r1, r4, r5, r7, r8, ip} + e8d4: ebf5d19e bl 0xffd82f54 + e8d8: eafffca1 b 0xdb64 + e8dc: ebf5d5a7 bl 0xffd83f80 + e8e0: 080c118a stmeqda ip, {r1, r3, r7, r8, ip} + e8e4: e3a00f67 mov r0, #412 ; 0x19c + e8e8: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + e8ec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e8f0: ebf5d408 bl 0xffd83918 + e8f4: 080c118e stmeqda ip, {r1, r2, r3, r7, r8, ip} + e8f8: e1a03000 mov r3, r0 + e8fc: ebf5d59f bl 0xffd83f80 + e900: 080c118c stmeqda ip, {r2, r3, r7, r8, ip} + e904: e2830000 add r0, r3, #0 ; 0x0 + e908: ebf5d3ab bl 0xffd837bc + e90c: 080c1190 stmeqda ip, {r4, r7, r8, ip} + e910: e1a03000 mov r3, r0 + e914: ebf5d599 bl 0xffd83f80 + e918: 080c118e stmeqda ip, {r1, r2, r3, r7, r8, ip} + e91c: e353003f cmp r3, #63 ; 0x3f + e920: ebf5d596 bl 0xffd83f80 + e924: 080c1190 stmeqda ip, {r4, r7, r8, ip} + e928: e28cc010 add ip, ip, #16 ; 0x10 + e92c: da000004 ble 0xe944 + e930: e1a00fac mov r0, ip, lsr #31 + e934: e08ff100 add pc, pc, r0, lsl #2 + e938: 080c11a4 stmeqda ip, {r2, r5, r7, r8, ip} + e93c: ebf5d184 bl 0xffd82f54 + e940: eafffee2 b 0xe4d0 + e944: ebf5d58d bl 0xffd83f80 + e948: 080c1192 stmeqda ip, {r1, r4, r7, r8, ip} + e94c: e2870020 add r0, r7, #32 ; 0x20 + e950: ebf5d3f0 bl 0xffd83918 + e954: 080c1196 stmeqda ip, {r1, r2, r4, r7, r8, ip} + e958: e1a03000 mov r3, r0 + e95c: ebf5d587 bl 0xffd83f80 + e960: 080c1194 stmeqda ip, {r2, r4, r7, r8, ip} + e964: e1a01003 mov r1, r3 + e968: e2933002 adds r3, r3, #2 ; 0x2 + e96c: ebf5d583 bl 0xffd83f80 + e970: 080c1196 stmeqda ip, {r1, r2, r4, r7, r8, ip} + e974: e3a00e1a mov r0, #416 ; 0x1a0 + e978: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + e97c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + e980: ebf5d3e4 bl 0xffd83918 + e984: 080c119a stmeqda ip, {r1, r3, r4, r7, r8, ip} + e988: e1a04000 mov r4, r0 + e98c: ebf5d57b bl 0xffd83f80 + e990: 080c1198 stmeqda ip, {r3, r4, r7, r8, ip} + e994: e28cc010 add ip, ip, #16 ; 0x10 + e998: e1a00fac mov r0, ip, lsr #31 + e99c: e08ff100 add pc, pc, r0, lsl #2 + e9a0: 080c11ae stmeqda ip, {r1, r2, r3, r5, r7, r8, ip} + e9a4: ebf5d16a bl 0xffd82f54 + e9a8: eaffff0e b 0xe5e8 + e9ac: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + e9b0: 00000000 andeq r0, r0, r0 + e9b4: ebf5d571 bl 0xffd83f80 + e9b8: 080c1072 stmeqda ip, {r1, r4, r5, r6, ip} + e9bc: e287000b add r0, r7, #11 ; 0xb + e9c0: ebf5d37d bl 0xffd837bc + e9c4: 080c1076 stmeqda ip, {r1, r2, r4, r5, r6, ip} + e9c8: e1a03000 mov r3, r0 + e9cc: ebf5d56b bl 0xffd83f80 + e9d0: 080c1074 stmeqda ip, {r2, r4, r5, r6, ip} + e9d4: e3530000 cmp r3, #0 ; 0x0 + e9d8: ebf5d568 bl 0xffd83f80 + e9dc: 080c1076 stmeqda ip, {r1, r2, r4, r5, r6, ip} + e9e0: e28cc00b add ip, ip, #11 ; 0xb + e9e4: 0a000004 beq 0xe9fc + e9e8: e1a00fac mov r0, ip, lsr #31 + e9ec: e08ff100 add pc, pc, r0, lsl #2 + e9f0: 080c1160 stmeqda ip, {r5, r6, r8, ip} + e9f4: ebf5d156 bl 0xffd82f54 + e9f8: eaffff42 b 0xe708 + e9fc: ebf5d55f bl 0xffd83f80 + ea00: 080c1078 stmeqda ip, {r3, r4, r5, r6, ip} + ea04: e59d1418 ldr r1, [sp, #1048] + ea08: e3510003 cmp r1, #3 ; 0x3 + ea0c: ebf5d55b bl 0xffd83f80 + ea10: 080c107a stmeqda ip, {r1, r3, r4, r5, r6, ip} + ea14: e28cc006 add ip, ip, #6 ; 0x6 + ea18: 0a000004 beq 0xea30 + ea1c: e1a00fac mov r0, ip, lsr #31 + ea20: e08ff100 add pc, pc, r0, lsl #2 + ea24: 080c1084 stmeqda ip, {r2, r7, ip} + ea28: ebf5d149 bl 0xffd82f54 + ea2c: ea000013 b 0xea80 + ea30: ebf5d552 bl 0xffd83f80 + ea34: 080c107c stmeqda ip, {r2, r3, r4, r5, r6, ip} + ea38: e3b03001 movs r3, #1 ; 0x1 + ea3c: ebf5d54f bl 0xffd83f80 + ea40: 080c107e stmeqda ip, {r1, r2, r3, r4, r5, r6, ip} + ea44: e287001d add r0, r7, #29 ; 0x1d + ea48: ebf5d35b bl 0xffd837bc + ea4c: 080c1082 stmeqda ip, {r1, r7, ip} + ea50: e1a04000 mov r4, r0 + ea54: ebf5d549 bl 0xffd83f80 + ea58: 080c1080 stmeqda ip, {r7, ip} + ea5c: e1a01003 mov r1, r3 + ea60: e1933004 orrs r3, r3, r4 + ea64: ebf5d545 bl 0xffd83f80 + ea68: 080c1082 stmeqda ip, {r1, r7, ip} + ea6c: e287001d add r0, r7, #29 ; 0x1d + ea70: e1a01003 mov r1, r3 + ea74: ebf5d295 bl 0xffd834d0 + ea78: 080c1084 stmeqda ip, {r2, r7, ip} + ea7c: e28cc00f add ip, ip, #15 ; 0xf + ea80: ebf5d53e bl 0xffd83f80 + ea84: 080c1084 stmeqda ip, {r2, r7, ip} + ea88: e1a01007 mov r1, r7 + ea8c: e2973000 adds r3, r7, #0 ; 0x0 + ea90: ebf5d53a bl 0xffd83f80 + ea94: 080c1086 stmeqda ip, {r1, r2, r7, ip} + ea98: ebf5d538 bl 0xffd83f80 + ea9c: 080c1088 stmeqda ip, {r3, r7, ip} + eaa0: e3a0008b mov r0, #139 ; 0x8b + eaa4: e3800ac1 orr r0, r0, #790528 ; 0xc1000 + eaa8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + eaac: e58d0438 str r0, [sp, #1080] + eab0: e28cc009 add ip, ip, #9 ; 0x9 + eab4: e1a00fac mov r0, ip, lsr #31 + eab8: e08ff100 add pc, pc, r0, lsl #2 + eabc: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + eac0: ebf5d123 bl 0xffd82f54 + eac4: ea000001 b 0xead0 + eac8: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + eacc: 00000000 andeq r0, r0, r0 + ead0: ebf5d52a bl 0xffd83f80 + ead4: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + ead8: e59d9434 ldr r9, [sp, #1076] + eadc: e3c99003 bic r9, r9, #3 ; 0x3 + eae0: e2499008 sub r9, r9, #8 ; 0x8 + eae4: e58d9434 str r9, [sp, #1076] + eae8: e2890000 add r0, r9, #0 ; 0x0 + eaec: e1a01007 mov r1, r7 + eaf0: ebf5d2d5 bl 0xffd8364c + eaf4: e2890004 add r0, r9, #4 ; 0x4 + eaf8: e59d1438 ldr r1, [sp, #1080] + eafc: ebf5d2d2 bl 0xffd8364c + eb00: ebf5d51e bl 0xffd83f80 + eb04: 080c0df2 stmeqda ip, {r1, r4, r5, r6, r7, r8, sl, fp} + eb08: e1a01003 mov r1, r3 + eb0c: e2934000 adds r4, r3, #0 ; 0x0 + eb10: ebf5d51a bl 0xffd83f80 + eb14: 080c0df4 stmeqda ip, {r2, r4, r5, r6, r7, r8, sl, fp} + eb18: e2840002 add r0, r4, #2 ; 0x2 + eb1c: ebf5d326 bl 0xffd837bc + eb20: 080c0df8 stmeqda ip, {r3, r4, r5, r6, r7, r8, sl, fp} + eb24: e1a03000 mov r3, r0 + eb28: ebf5d514 bl 0xffd83f80 + eb2c: 080c0df6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + eb30: e1b05c03 movs r5, r3, lsl #24 + eb34: ebf5d511 bl 0xffd83f80 + eb38: 080c0df8 stmeqda ip, {r3, r4, r5, r6, r7, r8, sl, fp} + eb3c: e1b07c25 movs r7, r5, lsr #24 + eb40: ebf5d50e bl 0xffd83f80 + eb44: 080c0dfa stmeqda ip, {r1, r3, r4, r5, r6, r7, r8, sl, fp} + eb48: e2840003 add r0, r4, #3 ; 0x3 + eb4c: ebf5d31a bl 0xffd837bc + eb50: 080c0dfe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, sl, fp} + eb54: e1a06000 mov r6, r0 + eb58: ebf5d508 bl 0xffd83f80 + eb5c: 080c0dfc stmeqda ip, {r2, r3, r4, r5, r6, r7, r8, sl, fp} + eb60: e1b03c06 movs r3, r6, lsl #24 + eb64: ebf5d505 bl 0xffd83f80 + eb68: 080c0dfe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r8, sl, fp} + eb6c: e1b06c23 movs r6, r3, lsr #24 + eb70: ebf5d502 bl 0xffd83f80 + eb74: 080c0e00 stmeqda ip, {r9, sl, fp} + eb78: e1570006 cmp r7, r6 + eb7c: ebf5d4ff bl 0xffd83f80 + eb80: 080c0e02 stmeqda ip, {r1, r9, sl, fp} + eb84: e28cc023 add ip, ip, #35 ; 0x23 + eb88: 2a000004 bcs 0xeba0 + eb8c: e1a00fac mov r0, ip, lsr #31 + eb90: e08ff100 add pc, pc, r0, lsl #2 + eb94: 080c0e10 stmeqda ip, {r4, r9, sl, fp} + eb98: ebf5d0ed bl 0xffd82f54 + eb9c: ea00001f b 0xec20 + eba0: ebf5d4f6 bl 0xffd83f80 + eba4: 080c0e04 stmeqda ip, {r2, r9, sl, fp} + eba8: e1b03ca5 movs r3, r5, lsr #25 + ebac: ebf5d4f3 bl 0xffd83f80 + ebb0: 080c0e06 stmeqda ip, {r1, r2, r9, sl, fp} + ebb4: e1530006 cmp r3, r6 + ebb8: ebf5d4f0 bl 0xffd83f80 + ebbc: 080c0e08 stmeqda ip, {r3, r9, sl, fp} + ebc0: e28cc009 add ip, ip, #9 ; 0x9 + ebc4: 2a000004 bcs 0xebdc + ebc8: e1a00fac mov r0, ip, lsr #31 + ebcc: e08ff100 add pc, pc, r0, lsl #2 + ebd0: 080c0e1c stmeqda ip, {r2, r3, r4, r9, sl, fp} + ebd4: ebf5d0de bl 0xffd82f54 + ebd8: ea000030 b 0xeca0 + ebdc: ebf5d4e7 bl 0xffd83f80 + ebe0: 080c0e0a stmeqda ip, {r1, r3, r9, sl, fp} + ebe4: e3b0300f movs r3, #15 ; 0xf + ebe8: ebf5d4e4 bl 0xffd83f80 + ebec: 080c0e0c stmeqda ip, {r2, r3, r9, sl, fp} + ebf0: e284001b add r0, r4, #27 ; 0x1b + ebf4: e1a01003 mov r1, r3 + ebf8: ebf5d234 bl 0xffd834d0 + ebfc: 080c0e0e stmeqda ip, {r1, r2, r3, r9, sl, fp} + ec00: ebf5d4de bl 0xffd83f80 + ec04: 080c0e0e stmeqda ip, {r1, r2, r3, r9, sl, fp} + ec08: e28cc00a add ip, ip, #10 ; 0xa + ec0c: e1a00fac mov r0, ip, lsr #31 + ec10: e08ff100 add pc, pc, r0, lsl #2 + ec14: 080c0e2a stmeqda ip, {r1, r3, r5, r9, sl, fp} + ec18: ebf5d0cd bl 0xffd82f54 + ec1c: ea000043 b 0xed30 + ec20: ebf5d4d6 bl 0xffd83f80 + ec24: 080c0e10 stmeqda ip, {r4, r9, sl, fp} + ec28: e1b03ca3 movs r3, r3, lsr #25 + ec2c: ebf5d4d3 bl 0xffd83f80 + ec30: 080c0e12 stmeqda ip, {r1, r4, r9, sl, fp} + ec34: e1530007 cmp r3, r7 + ec38: ebf5d4d0 bl 0xffd83f80 + ec3c: 080c0e14 stmeqda ip, {r2, r4, r9, sl, fp} + ec40: e28cc009 add ip, ip, #9 ; 0x9 + ec44: 2a000004 bcs 0xec5c + ec48: e1a00fac mov r0, ip, lsr #31 + ec4c: e08ff100 add pc, pc, r0, lsl #2 + ec50: 080c0e1c stmeqda ip, {r2, r3, r4, r9, sl, fp} + ec54: ebf5d0be bl 0xffd82f54 + ec58: ea000010 b 0xeca0 + ec5c: ebf5d4c7 bl 0xffd83f80 + ec60: 080c0e16 stmeqda ip, {r1, r2, r4, r9, sl, fp} + ec64: e3b030f0 movs r3, #240 ; 0xf0 + ec68: ebf5d4c4 bl 0xffd83f80 + ec6c: 080c0e18 stmeqda ip, {r3, r4, r9, sl, fp} + ec70: e284001b add r0, r4, #27 ; 0x1b + ec74: e1a01003 mov r1, r3 + ec78: ebf5d214 bl 0xffd834d0 + ec7c: 080c0e1a stmeqda ip, {r1, r3, r4, r9, sl, fp} + ec80: ebf5d4be bl 0xffd83f80 + ec84: 080c0e1a stmeqda ip, {r1, r3, r4, r9, sl, fp} + ec88: e28cc00a add ip, ip, #10 ; 0xa + ec8c: e1a00fac mov r0, ip, lsr #31 + ec90: e08ff100 add pc, pc, r0, lsl #2 + ec94: 080c0e2a stmeqda ip, {r1, r3, r5, r9, sl, fp} + ec98: ebf5d0ad bl 0xffd82f54 + ec9c: ea000023 b 0xed30 + eca0: ebf5d4b6 bl 0xffd83f80 + eca4: 080c0e1c stmeqda ip, {r2, r3, r4, r9, sl, fp} + eca8: e3b030ff movs r3, #255 ; 0xff + ecac: ebf5d4b3 bl 0xffd83f80 + ecb0: 080c0e1e stmeqda ip, {r1, r2, r3, r4, r9, sl, fp} + ecb4: e284001b add r0, r4, #27 ; 0x1b + ecb8: e1a01003 mov r1, r3 + ecbc: ebf5d203 bl 0xffd834d0 + ecc0: 080c0e20 stmeqda ip, {r5, r9, sl, fp} + ecc4: ebf5d4ad bl 0xffd83f80 + ecc8: 080c0e20 stmeqda ip, {r5, r9, sl, fp} + eccc: e2840003 add r0, r4, #3 ; 0x3 + ecd0: ebf5d2b9 bl 0xffd837bc + ecd4: 080c0e24 stmeqda ip, {r2, r5, r9, sl, fp} + ecd8: e1a05000 mov r5, r0 + ecdc: ebf5d4a7 bl 0xffd83f80 + ece0: 080c0e22 stmeqda ip, {r1, r5, r9, sl, fp} + ece4: e2840002 add r0, r4, #2 ; 0x2 + ece8: ebf5d2b3 bl 0xffd837bc + ecec: 080c0e26 stmeqda ip, {r1, r2, r5, r9, sl, fp} + ecf0: e1a06000 mov r6, r0 + ecf4: ebf5d4a1 bl 0xffd83f80 + ecf8: 080c0e24 stmeqda ip, {r2, r5, r9, sl, fp} + ecfc: e1a01005 mov r1, r5 + ed00: e0953006 adds r3, r5, r6 + ed04: ebf5d49d bl 0xffd83f80 + ed08: 080c0e26 stmeqda ip, {r1, r2, r5, r9, sl, fp} + ed0c: e1b03223 movs r3, r3, lsr #4 + ed10: ebf5d49a bl 0xffd83f80 + ed14: 080c0e28 stmeqda ip, {r3, r5, r9, sl, fp} + ed18: e28cc01a add ip, ip, #26 ; 0x1a + ed1c: e1a00fac mov r0, ip, lsr #31 + ed20: e08ff100 add pc, pc, r0, lsl #2 + ed24: 080c0e3a stmeqda ip, {r1, r3, r4, r5, r9, sl, fp} + ed28: ebf5d089 bl 0xffd82f54 + ed2c: ea000028 b 0xedd4 + ed30: ebf5d492 bl 0xffd83f80 + ed34: 080c0e2a stmeqda ip, {r1, r3, r5, r9, sl, fp} + ed38: e2840003 add r0, r4, #3 ; 0x3 + ed3c: ebf5d29e bl 0xffd837bc + ed40: 080c0e2e stmeqda ip, {r1, r2, r3, r5, r9, sl, fp} + ed44: e1a05000 mov r5, r0 + ed48: ebf5d48c bl 0xffd83f80 + ed4c: 080c0e2c stmeqda ip, {r2, r3, r5, r9, sl, fp} + ed50: e2840002 add r0, r4, #2 ; 0x2 + ed54: ebf5d298 bl 0xffd837bc + ed58: 080c0e30 stmeqda ip, {r4, r5, r9, sl, fp} + ed5c: e1a06000 mov r6, r0 + ed60: ebf5d486 bl 0xffd83f80 + ed64: 080c0e2e stmeqda ip, {r1, r2, r3, r5, r9, sl, fp} + ed68: e1a01005 mov r1, r5 + ed6c: e0953006 adds r3, r5, r6 + ed70: ebf5d482 bl 0xffd83f80 + ed74: 080c0e30 stmeqda ip, {r4, r5, r9, sl, fp} + ed78: e1b03223 movs r3, r3, lsr #4 + ed7c: ebf5d47f bl 0xffd83f80 + ed80: 080c0e32 stmeqda ip, {r1, r4, r5, r9, sl, fp} + ed84: e284000a add r0, r4, #10 ; 0xa + ed88: e1a01003 mov r1, r3 + ed8c: ebf5d1cf bl 0xffd834d0 + ed90: 080c0e34 stmeqda ip, {r2, r4, r5, r9, sl, fp} + ed94: ebf5d479 bl 0xffd83f80 + ed98: 080c0e34 stmeqda ip, {r2, r4, r5, r9, sl, fp} + ed9c: e353000f cmp r3, #15 ; 0xf + eda0: ebf5d476 bl 0xffd83f80 + eda4: 080c0e36 stmeqda ip, {r1, r2, r4, r5, r9, sl, fp} + eda8: e28cc01a add ip, ip, #26 ; 0x1a + edac: 8a000004 bhi 0xedc4 + edb0: e1a00fac mov r0, ip, lsr #31 + edb4: e08ff100 add pc, pc, r0, lsl #2 + edb8: 080c0e3c stmeqda ip, {r2, r3, r4, r5, r9, sl, fp} + edbc: ebf5d064 bl 0xffd82f54 + edc0: ea00000a b 0xedf0 + edc4: ebf5d46d bl 0xffd83f80 + edc8: 080c0e38 stmeqda ip, {r3, r4, r5, r9, sl, fp} + edcc: e3b0300f movs r3, #15 ; 0xf + edd0: e28cc003 add ip, ip, #3 ; 0x3 + edd4: ebf5d469 bl 0xffd83f80 + edd8: 080c0e3a stmeqda ip, {r1, r3, r4, r5, r9, sl, fp} + eddc: e284000a add r0, r4, #10 ; 0xa + ede0: e1a01003 mov r1, r3 + ede4: ebf5d1b9 bl 0xffd834d0 + ede8: 080c0e3c stmeqda ip, {r2, r3, r4, r5, r9, sl, fp} + edec: e28cc004 add ip, ip, #4 ; 0x4 + edf0: ebf5d462 bl 0xffd83f80 + edf4: 080c0e3c stmeqda ip, {r2, r3, r4, r5, r9, sl, fp} + edf8: e2840006 add r0, r4, #6 ; 0x6 + edfc: ebf5d26e bl 0xffd837bc + ee00: 080c0e40 stmeqda ip, {r6, r9, sl, fp} + ee04: e1a05000 mov r5, r0 + ee08: ebf5d45c bl 0xffd83f80 + ee0c: 080c0e3e stmeqda ip, {r1, r2, r3, r4, r5, r9, sl, fp} + ee10: e284000a add r0, r4, #10 ; 0xa + ee14: ebf5d268 bl 0xffd837bc + ee18: 080c0e42 stmeqda ip, {r1, r6, r9, sl, fp} + ee1c: e1a06000 mov r6, r0 + ee20: ebf5d456 bl 0xffd83f80 + ee24: 080c0e40 stmeqda ip, {r6, r9, sl, fp} + ee28: e1a01005 mov r1, r5 + ee2c: e2953000 adds r3, r5, #0 ; 0x0 + ee30: ebf5d452 bl 0xffd83f80 + ee34: 080c0e42 stmeqda ip, {r1, r6, r9, sl, fp} + ee38: e1a01003 mov r1, r3 + ee3c: e0130693 muls r3, r3, r6 + ee40: ebf5d44e bl 0xffd83f80 + ee44: 080c0e44 stmeqda ip, {r2, r6, r9, sl, fp} + ee48: e1a01003 mov r1, r3 + ee4c: e293300f adds r3, r3, #15 ; 0xf + ee50: ebf5d44a bl 0xffd83f80 + ee54: 080c0e46 stmeqda ip, {r1, r2, r6, r9, sl, fp} + ee58: e1b03243 movs r3, r3, asr #4 + ee5c: ebf5d447 bl 0xffd83f80 + ee60: 080c0e48 stmeqda ip, {r3, r6, r9, sl, fp} + ee64: e2840019 add r0, r4, #25 ; 0x19 + ee68: e1a01003 mov r1, r3 + ee6c: ebf5d197 bl 0xffd834d0 + ee70: 080c0e4a stmeqda ip, {r1, r3, r6, r9, sl, fp} + ee74: ebf5d441 bl 0xffd83f80 + ee78: 080c0e4a stmeqda ip, {r1, r3, r6, r9, sl, fp} + ee7c: e284001c add r0, r4, #28 ; 0x1c + ee80: ebf5d24d bl 0xffd837bc + ee84: 080c0e4e stmeqda ip, {r1, r2, r3, r6, r9, sl, fp} + ee88: e1a03000 mov r3, r0 + ee8c: ebf5d43b bl 0xffd83f80 + ee90: 080c0e4c stmeqda ip, {r2, r3, r6, r9, sl, fp} + ee94: e284001b add r0, r4, #27 ; 0x1b + ee98: ebf5d247 bl 0xffd837bc + ee9c: 080c0e50 stmeqda ip, {r4, r6, r9, sl, fp} + eea0: e1a05000 mov r5, r0 + eea4: ebf5d435 bl 0xffd83f80 + eea8: 080c0e4e stmeqda ip, {r1, r2, r3, r6, r9, sl, fp} + eeac: e1a01003 mov r1, r3 + eeb0: e0133005 ands r3, r3, r5 + eeb4: ebf5d431 bl 0xffd83f80 + eeb8: 080c0e50 stmeqda ip, {r4, r6, r9, sl, fp} + eebc: e284001b add r0, r4, #27 ; 0x1b + eec0: e1a01003 mov r1, r3 + eec4: ebf5d181 bl 0xffd834d0 + eec8: 080c0e52 stmeqda ip, {r1, r4, r6, r9, sl, fp} + eecc: ebf5d42b bl 0xffd83f80 + eed0: 080c0e52 stmeqda ip, {r1, r4, r6, r9, sl, fp} + eed4: e59d9434 ldr r9, [sp, #1076] + eed8: e3c99003 bic r9, r9, #3 ; 0x3 + eedc: e2890004 add r0, r9, #4 ; 0x4 + eee0: e58d0434 str r0, [sp, #1076] + eee4: e2890000 add r0, r9, #0 ; 0x0 + eee8: ebf5d28a bl 0xffd83918 + eeec: 080c0e56 stmeqda ip, {r1, r2, r4, r6, r9, sl, fp} + eef0: e1a07000 mov r7, r0 + eef4: ebf5d421 bl 0xffd83f80 + eef8: 080c0e54 stmeqda ip, {r2, r4, r6, r9, sl, fp} + eefc: e59d9434 ldr r9, [sp, #1076] + ef00: e3c99003 bic r9, r9, #3 ; 0x3 + ef04: e2890004 add r0, r9, #4 ; 0x4 + ef08: e58d0434 str r0, [sp, #1076] + ef0c: e2890000 add r0, r9, #0 ; 0x0 + ef10: ebf5d280 bl 0xffd83918 + ef14: 080c0e58 stmeqda ip, {r3, r4, r6, r9, sl, fp} + ef18: e1a03000 mov r3, r0 + ef1c: ebf5d417 bl 0xffd83f80 + ef20: 080c0e56 stmeqda ip, {r1, r2, r4, r6, r9, sl, fp} + ef24: e1a00003 mov r0, r3 + ef28: e28cc036 add ip, ip, #54 ; 0x36 + ef2c: eaf5d067 b 0xffd830d0 + ef30: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + ef34: 00000000 andeq r0, r0, r0 + ef38: ebf5d410 bl 0xffd83f80 + ef3c: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + ef40: e3a00ef6 mov r0, #3936 ; 0xf60 + ef44: e3800703 orr r0, r0, #786432 ; 0xc0000 + ef48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ef4c: ebf5d271 bl 0xffd83918 + ef50: 080c0f0c stmeqda ip, {r2, r3, r8, r9, sl, fp} + ef54: e1a03000 mov r3, r0 + ef58: ebf5d408 bl 0xffd83f80 + ef5c: 080c0f0a stmeqda ip, {r1, r3, r8, r9, sl, fp} + ef60: e59d0434 ldr r0, [sp, #1076] + ef64: e2800f02 add r0, r0, #8 ; 0x8 + ef68: e1a01003 mov r1, r3 + ef6c: ebf5d196 bl 0xffd835cc + ef70: 080c0f0c stmeqda ip, {r2, r3, r8, r9, sl, fp} + ef74: ebf5d401 bl 0xffd83f80 + ef78: 080c0f0c stmeqda ip, {r2, r3, r8, r9, sl, fp} + ef7c: e3a00fd9 mov r0, #868 ; 0x364 + ef80: e3800b03 orr r0, r0, #3072 ; 0xc00 + ef84: e3800703 orr r0, r0, #786432 ; 0xc0000 + ef88: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ef8c: ebf5d261 bl 0xffd83918 + ef90: 080c0f10 stmeqda ip, {r4, r8, r9, sl, fp} + ef94: e58d041c str r0, [sp, #1052] + ef98: ebf5d3f8 bl 0xffd83f80 + ef9c: 080c0f0e stmeqda ip, {r1, r2, r3, r8, r9, sl, fp} + efa0: e3a00fda mov r0, #872 ; 0x368 + efa4: e3800b03 orr r0, r0, #3072 ; 0xc00 + efa8: e3800703 orr r0, r0, #786432 ; 0xc0000 + efac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + efb0: ebf5d258 bl 0xffd83918 + efb4: 080c0f12 stmeqda ip, {r1, r4, r8, r9, sl, fp} + efb8: e1a05000 mov r5, r0 + efbc: ebf5d3ef bl 0xffd83f80 + efc0: 080c0f10 stmeqda ip, {r4, r8, r9, sl, fp} + efc4: e1a00005 mov r0, r5 + efc8: e58d0428 str r0, [sp, #1064] + efcc: ebf5d3eb bl 0xffd83f80 + efd0: 080c0f12 stmeqda ip, {r1, r4, r8, r9, sl, fp} + efd4: e1a01003 mov r1, r3 + efd8: e293300b adds r3, r3, #11 ; 0xb + efdc: ebf5d3e7 bl 0xffd83f80 + efe0: 080c0f14 stmeqda ip, {r2, r4, r8, r9, sl, fp} + efe4: e59d0434 ldr r0, [sp, #1076] + efe8: e2800f03 add r0, r0, #12 ; 0xc + efec: e1a01003 mov r1, r3 + eff0: ebf5d175 bl 0xffd835cc + eff4: 080c0f16 stmeqda ip, {r1, r2, r4, r8, r9, sl, fp} + eff8: ebf5d3e0 bl 0xffd83f80 + effc: 080c0f16 stmeqda ip, {r1, r2, r4, r8, r9, sl, fp} + f000: e1a01005 mov r1, r5 + f004: e2955004 adds r5, r5, #4 ; 0x4 + f008: ebf5d3dc bl 0xffd83f80 + f00c: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + f010: e59d0434 ldr r0, [sp, #1076] + f014: e2800f04 add r0, r0, #16 ; 0x10 + f018: e1a01005 mov r1, r5 + f01c: ebf5d16a bl 0xffd835cc + f020: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + f024: ebf5d3d5 bl 0xffd83f80 + f028: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + f02c: e59d0434 ldr r0, [sp, #1076] + f030: e2800f01 add r0, r0, #4 ; 0x4 + f034: ebf5d237 bl 0xffd83918 + f038: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + f03c: e1a03000 mov r3, r0 + f040: ebf5d3ce bl 0xffd83f80 + f044: 080c0f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp} + f048: e283000a add r0, r3, #10 ; 0xa + f04c: ebf5d1da bl 0xffd837bc + f050: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f054: e1a03000 mov r3, r0 + f058: ebf5d3c8 bl 0xffd83f80 + f05c: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + f060: e59d0434 ldr r0, [sp, #1076] + f064: e2800f00 add r0, r0, #0 ; 0x0 + f068: e1a01003 mov r1, r3 + f06c: ebf5d156 bl 0xffd835cc + f070: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f074: ebf5d3c1 bl 0xffd83f80 + f078: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f07c: e1a01004 mov r1, r4 + f080: e2945000 adds r5, r4, #0 ; 0x0 + f084: ebf5d3bd bl 0xffd83f80 + f088: 080c0f22 stmeqda ip, {r1, r5, r8, r9, sl, fp} + f08c: e3b03080 movs r3, #128 ; 0x80 + f090: ebf5d3ba bl 0xffd83f80 + f094: 080c0f24 stmeqda ip, {r2, r5, r8, r9, sl, fp} + f098: e1a01003 mov r1, r3 + f09c: e0133005 ands r3, r3, r5 + f0a0: ebf5d3b6 bl 0xffd83f80 + f0a4: 080c0f26 stmeqda ip, {r1, r2, r5, r8, r9, sl, fp} + f0a8: e3530000 cmp r3, #0 ; 0x0 + f0ac: ebf5d3b3 bl 0xffd83f80 + f0b0: 080c0f28 stmeqda ip, {r3, r5, r8, r9, sl, fp} + f0b4: e28cc041 add ip, ip, #65 ; 0x41 + f0b8: 1a000004 bne 0xf0d0 + f0bc: e1a00fac mov r0, ip, lsr #31 + f0c0: e08ff100 add pc, pc, r0, lsl #2 + f0c4: 080c1008 stmeqda ip, {r3, ip} + f0c8: ebf5cfa1 bl 0xffd82f54 + f0cc: eafff59d b 0xc748 + f0d0: ebf5d3aa bl 0xffd83f80 + f0d4: 080c0f2a stmeqda ip, {r1, r3, r5, r8, r9, sl, fp} + f0d8: e3b06040 movs r6, #64 ; 0x40 + f0dc: ebf5d3a7 bl 0xffd83f80 + f0e0: 080c0f2c stmeqda ip, {r2, r3, r5, r8, r9, sl, fp} + f0e4: e1a01006 mov r1, r6 + f0e8: e2963000 adds r3, r6, #0 ; 0x0 + f0ec: ebf5d3a3 bl 0xffd83f80 + f0f0: 080c0f2e stmeqda ip, {r1, r2, r3, r5, r8, r9, sl, fp} + f0f4: e1a01003 mov r1, r3 + f0f8: e0133005 ands r3, r3, r5 + f0fc: ebf5d39f bl 0xffd83f80 + f100: 080c0f30 stmeqda ip, {r4, r5, r8, r9, sl, fp} + f104: e1b03c03 movs r3, r3, lsl #24 + f108: ebf5d39c bl 0xffd83f80 + f10c: 080c0f32 stmeqda ip, {r1, r4, r5, r8, r9, sl, fp} + f110: e1b08c23 movs r8, r3, lsr #24 + f114: ebf5d399 bl 0xffd83f80 + f118: 080c0f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp} + f11c: e59d1418 ldr r1, [sp, #1048] + f120: e59d1418 ldr r1, [sp, #1048] + f124: e2914001 adds r4, r1, #1 ; 0x1 + f128: ebf5d394 bl 0xffd83f80 + f12c: 080c0f36 stmeqda ip, {r1, r2, r4, r5, r8, r9, sl, fp} + f130: e1a00004 mov r0, r4 + f134: e58d0424 str r0, [sp, #1060] + f138: ebf5d390 bl 0xffd83f80 + f13c: 080c0f38 stmeqda ip, {r3, r4, r5, r8, r9, sl, fp} + f140: e3b05040 movs r5, #64 ; 0x40 + f144: ebf5d38d bl 0xffd83f80 + f148: 080c0f3a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, fp} + f14c: e1a01005 mov r1, r5 + f150: e0955007 adds r5, r5, r7 + f154: ebf5d389 bl 0xffd83f80 + f158: 080c0f3c stmeqda ip, {r2, r3, r4, r5, r8, r9, sl, fp} + f15c: e1a00005 mov r0, r5 + f160: e58d0420 str r0, [sp, #1056] + f164: ebf5d385 bl 0xffd83f80 + f168: 080c0f3e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, fp} + f16c: e3580000 cmp r8, #0 ; 0x0 + f170: ebf5d382 bl 0xffd83f80 + f174: 080c0f40 stmeqda ip, {r6, r8, r9, sl, fp} + f178: e28cc024 add ip, ip, #36 ; 0x24 + f17c: 0a000004 beq 0xf194 + f180: e1a00fac mov r0, ip, lsr #31 + f184: e08ff100 add pc, pc, r0, lsl #2 + f188: 080c102c stmeqda ip, {r2, r3, r5, ip} + f18c: ebf5cf70 bl 0xffd82f54 + f190: eafff706 b 0xcdb0 + f194: ebf5d379 bl 0xffd83f80 + f198: 080c0f42 stmeqda ip, {r1, r6, r8, r9, sl, fp} + f19c: e3b03003 movs r3, #3 ; 0x3 + f1a0: ebf5d376 bl 0xffd83f80 + f1a4: 080c0f44 stmeqda ip, {r2, r6, r8, r9, sl, fp} + f1a8: e2870000 add r0, r7, #0 ; 0x0 + f1ac: e1a01003 mov r1, r3 + f1b0: ebf5d0c6 bl 0xffd834d0 + f1b4: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + f1b8: ebf5d370 bl 0xffd83f80 + f1bc: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + f1c0: e287001d add r0, r7, #29 ; 0x1d + f1c4: e1a01003 mov r1, r3 + f1c8: ebf5d0c0 bl 0xffd834d0 + f1cc: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + f1d0: ebf5d36a bl 0xffd83f80 + f1d4: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + f1d8: e1a01007 mov r1, r7 + f1dc: e2973000 adds r3, r7, #0 ; 0x0 + f1e0: ebf5d366 bl 0xffd83f80 + f1e4: 080c0f4a stmeqda ip, {r1, r3, r6, r8, r9, sl, fp} + f1e8: e59d0434 ldr r0, [sp, #1076] + f1ec: e2800f05 add r0, r0, #20 ; 0x14 + f1f0: e1a01006 mov r1, r6 + f1f4: ebf5d0f4 bl 0xffd835cc + f1f8: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + f1fc: ebf5d35f bl 0xffd83f80 + f200: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + f204: ebf5d35d bl 0xffd83f80 + f208: 080c0f4e stmeqda ip, {r1, r2, r3, r6, r8, r9, sl, fp} + f20c: e3a00051 mov r0, #81 ; 0x51 + f210: e3800c0f orr r0, r0, #3840 ; 0xf00 + f214: e3800703 orr r0, r0, #786432 ; 0xc0000 + f218: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f21c: e58d0438 str r0, [sp, #1080] + f220: e28cc018 add ip, ip, #24 ; 0x18 + f224: e1a00fac mov r0, ip, lsr #31 + f228: e08ff100 add pc, pc, r0, lsl #2 + f22c: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + f230: ebf5cf47 bl 0xffd82f54 + f234: eafffe25 b 0xead0 + f238: 080c0ee8 stmeqda ip, {r3, r5, r6, r7, r9, sl, fp} + f23c: 00000000 andeq r0, r0, r0 + f240: ebf5d34e bl 0xffd83f80 + f244: 080c0ee8 stmeqda ip, {r3, r5, r6, r7, r9, sl, fp} + f248: e3a00fbf mov r0, #764 ; 0x2fc + f24c: e3800b03 orr r0, r0, #3072 ; 0xc00 + f250: e3800703 orr r0, r0, #786432 ; 0xc0000 + f254: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f258: ebf5d1ae bl 0xffd83918 + f25c: 080c0eec stmeqda ip, {r2, r3, r5, r6, r7, r9, sl, fp} + f260: e1a03000 mov r3, r0 + f264: ebf5d345 bl 0xffd83f80 + f268: 080c0eea stmeqda ip, {r1, r3, r5, r6, r7, r9, sl, fp} + f26c: e59d0434 ldr r0, [sp, #1076] + f270: e2800f02 add r0, r0, #8 ; 0x8 + f274: e1a01003 mov r1, r3 + f278: ebf5d0d3 bl 0xffd835cc + f27c: 080c0eec stmeqda ip, {r2, r3, r5, r6, r7, r9, sl, fp} + f280: ebf5d33e bl 0xffd83f80 + f284: 080c0eec stmeqda ip, {r2, r3, r5, r6, r7, r9, sl, fp} + f288: e3a00c0f mov r0, #3840 ; 0xf00 + f28c: e3800703 orr r0, r0, #786432 ; 0xc0000 + f290: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f294: ebf5d19f bl 0xffd83918 + f298: 080c0ef0 stmeqda ip, {r4, r5, r6, r7, r9, sl, fp} + f29c: e58d041c str r0, [sp, #1052] + f2a0: ebf5d336 bl 0xffd83f80 + f2a4: 080c0eee stmeqda ip, {r1, r2, r3, r5, r6, r7, r9, sl, fp} + f2a8: e3a00fc1 mov r0, #772 ; 0x304 + f2ac: e3800b03 orr r0, r0, #3072 ; 0xc00 + f2b0: e3800703 orr r0, r0, #786432 ; 0xc0000 + f2b4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f2b8: ebf5d196 bl 0xffd83918 + f2bc: 080c0ef2 stmeqda ip, {r1, r4, r5, r6, r7, r9, sl, fp} + f2c0: e1a05000 mov r5, r0 + f2c4: ebf5d32d bl 0xffd83f80 + f2c8: 080c0ef0 stmeqda ip, {r4, r5, r6, r7, r9, sl, fp} + f2cc: e1a00005 mov r0, r5 + f2d0: e58d0428 str r0, [sp, #1064] + f2d4: ebf5d329 bl 0xffd83f80 + f2d8: 080c0ef2 stmeqda ip, {r1, r4, r5, r6, r7, r9, sl, fp} + f2dc: e1a01003 mov r1, r3 + f2e0: e2933004 adds r3, r3, #4 ; 0x4 + f2e4: ebf5d325 bl 0xffd83f80 + f2e8: 080c0ef4 stmeqda ip, {r2, r4, r5, r6, r7, r9, sl, fp} + f2ec: e59d0434 ldr r0, [sp, #1076] + f2f0: e2800f03 add r0, r0, #12 ; 0xc + f2f4: e1a01003 mov r1, r3 + f2f8: ebf5d0b3 bl 0xffd835cc + f2fc: 080c0ef6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r9, sl, fp} + f300: ebf5d31e bl 0xffd83f80 + f304: 080c0ef6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r9, sl, fp} + f308: e1a01005 mov r1, r5 + f30c: e2955002 adds r5, r5, #2 ; 0x2 + f310: ebf5d31a bl 0xffd83f80 + f314: 080c0ef8 stmeqda ip, {r3, r4, r5, r6, r7, r9, sl, fp} + f318: e28cc023 add ip, ip, #35 ; 0x23 + f31c: e1a00fac mov r0, ip, lsr #31 + f320: e08ff100 add pc, pc, r0, lsl #2 + f324: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + f328: ebf5cf09 bl 0xffd82f54 + f32c: ea000001 b 0xf338 + f330: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + f334: 00000000 andeq r0, r0, r0 + f338: ebf5d310 bl 0xffd83f80 + f33c: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + f340: e59d0434 ldr r0, [sp, #1076] + f344: e2800f04 add r0, r0, #16 ; 0x10 + f348: e1a01005 mov r1, r5 + f34c: ebf5d09e bl 0xffd835cc + f350: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + f354: ebf5d309 bl 0xffd83f80 + f358: 080c0f1a stmeqda ip, {r1, r3, r4, r8, r9, sl, fp} + f35c: e59d0434 ldr r0, [sp, #1076] + f360: e2800f01 add r0, r0, #4 ; 0x4 + f364: ebf5d16b bl 0xffd83918 + f368: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + f36c: e1a03000 mov r3, r0 + f370: ebf5d302 bl 0xffd83f80 + f374: 080c0f1c stmeqda ip, {r2, r3, r4, r8, r9, sl, fp} + f378: e283000a add r0, r3, #10 ; 0xa + f37c: ebf5d10e bl 0xffd837bc + f380: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f384: e1a03000 mov r3, r0 + f388: ebf5d2fc bl 0xffd83f80 + f38c: 080c0f1e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, fp} + f390: e59d0434 ldr r0, [sp, #1076] + f394: e2800f00 add r0, r0, #0 ; 0x0 + f398: e1a01003 mov r1, r3 + f39c: ebf5d08a bl 0xffd835cc + f3a0: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f3a4: ebf5d2f5 bl 0xffd83f80 + f3a8: 080c0f20 stmeqda ip, {r5, r8, r9, sl, fp} + f3ac: e1a01004 mov r1, r4 + f3b0: e2945000 adds r5, r4, #0 ; 0x0 + f3b4: ebf5d2f1 bl 0xffd83f80 + f3b8: 080c0f22 stmeqda ip, {r1, r5, r8, r9, sl, fp} + f3bc: e3b03080 movs r3, #128 ; 0x80 + f3c0: ebf5d2ee bl 0xffd83f80 + f3c4: 080c0f24 stmeqda ip, {r2, r5, r8, r9, sl, fp} + f3c8: e1a01003 mov r1, r3 + f3cc: e0133005 ands r3, r3, r5 + f3d0: ebf5d2ea bl 0xffd83f80 + f3d4: 080c0f26 stmeqda ip, {r1, r2, r5, r8, r9, sl, fp} + f3d8: e3530000 cmp r3, #0 ; 0x0 + f3dc: ebf5d2e7 bl 0xffd83f80 + f3e0: 080c0f28 stmeqda ip, {r3, r5, r8, r9, sl, fp} + f3e4: e28cc021 add ip, ip, #33 ; 0x21 + f3e8: 1a000004 bne 0xf400 + f3ec: e1a00fac mov r0, ip, lsr #31 + f3f0: e08ff100 add pc, pc, r0, lsl #2 + f3f4: 080c1008 stmeqda ip, {r3, ip} + f3f8: ebf5ced5 bl 0xffd82f54 + f3fc: eafff4d1 b 0xc748 + f400: ebf5d2de bl 0xffd83f80 + f404: 080c0f2a stmeqda ip, {r1, r3, r5, r8, r9, sl, fp} + f408: e3b06040 movs r6, #64 ; 0x40 + f40c: ebf5d2db bl 0xffd83f80 + f410: 080c0f2c stmeqda ip, {r2, r3, r5, r8, r9, sl, fp} + f414: e1a01006 mov r1, r6 + f418: e2963000 adds r3, r6, #0 ; 0x0 + f41c: ebf5d2d7 bl 0xffd83f80 + f420: 080c0f2e stmeqda ip, {r1, r2, r3, r5, r8, r9, sl, fp} + f424: e1a01003 mov r1, r3 + f428: e0133005 ands r3, r3, r5 + f42c: ebf5d2d3 bl 0xffd83f80 + f430: 080c0f30 stmeqda ip, {r4, r5, r8, r9, sl, fp} + f434: e1b03c03 movs r3, r3, lsl #24 + f438: ebf5d2d0 bl 0xffd83f80 + f43c: 080c0f32 stmeqda ip, {r1, r4, r5, r8, r9, sl, fp} + f440: e1b08c23 movs r8, r3, lsr #24 + f444: ebf5d2cd bl 0xffd83f80 + f448: 080c0f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp} + f44c: e59d1418 ldr r1, [sp, #1048] + f450: e59d1418 ldr r1, [sp, #1048] + f454: e2914001 adds r4, r1, #1 ; 0x1 + f458: ebf5d2c8 bl 0xffd83f80 + f45c: 080c0f36 stmeqda ip, {r1, r2, r4, r5, r8, r9, sl, fp} + f460: e1a00004 mov r0, r4 + f464: e58d0424 str r0, [sp, #1060] + f468: ebf5d2c4 bl 0xffd83f80 + f46c: 080c0f38 stmeqda ip, {r3, r4, r5, r8, r9, sl, fp} + f470: e3b05040 movs r5, #64 ; 0x40 + f474: ebf5d2c1 bl 0xffd83f80 + f478: 080c0f3a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, fp} + f47c: e1a01005 mov r1, r5 + f480: e0955007 adds r5, r5, r7 + f484: ebf5d2bd bl 0xffd83f80 + f488: 080c0f3c stmeqda ip, {r2, r3, r4, r5, r8, r9, sl, fp} + f48c: e1a00005 mov r0, r5 + f490: e58d0420 str r0, [sp, #1056] + f494: ebf5d2b9 bl 0xffd83f80 + f498: 080c0f3e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, fp} + f49c: e3580000 cmp r8, #0 ; 0x0 + f4a0: ebf5d2b6 bl 0xffd83f80 + f4a4: 080c0f40 stmeqda ip, {r6, r8, r9, sl, fp} + f4a8: e28cc024 add ip, ip, #36 ; 0x24 + f4ac: 0a000004 beq 0xf4c4 + f4b0: e1a00fac mov r0, ip, lsr #31 + f4b4: e08ff100 add pc, pc, r0, lsl #2 + f4b8: 080c102c stmeqda ip, {r2, r3, r5, ip} + f4bc: ebf5cea4 bl 0xffd82f54 + f4c0: eafff63a b 0xcdb0 + f4c4: ebf5d2ad bl 0xffd83f80 + f4c8: 080c0f42 stmeqda ip, {r1, r6, r8, r9, sl, fp} + f4cc: e3b03003 movs r3, #3 ; 0x3 + f4d0: ebf5d2aa bl 0xffd83f80 + f4d4: 080c0f44 stmeqda ip, {r2, r6, r8, r9, sl, fp} + f4d8: e2870000 add r0, r7, #0 ; 0x0 + f4dc: e1a01003 mov r1, r3 + f4e0: ebf5cffa bl 0xffd834d0 + f4e4: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + f4e8: ebf5d2a4 bl 0xffd83f80 + f4ec: 080c0f46 stmeqda ip, {r1, r2, r6, r8, r9, sl, fp} + f4f0: e287001d add r0, r7, #29 ; 0x1d + f4f4: e1a01003 mov r1, r3 + f4f8: ebf5cff4 bl 0xffd834d0 + f4fc: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + f500: ebf5d29e bl 0xffd83f80 + f504: 080c0f48 stmeqda ip, {r3, r6, r8, r9, sl, fp} + f508: e1a01007 mov r1, r7 + f50c: e2973000 adds r3, r7, #0 ; 0x0 + f510: ebf5d29a bl 0xffd83f80 + f514: 080c0f4a stmeqda ip, {r1, r3, r6, r8, r9, sl, fp} + f518: e59d0434 ldr r0, [sp, #1076] + f51c: e2800f05 add r0, r0, #20 ; 0x14 + f520: e1a01006 mov r1, r6 + f524: ebf5d028 bl 0xffd835cc + f528: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + f52c: ebf5d293 bl 0xffd83f80 + f530: 080c0f4c stmeqda ip, {r2, r3, r6, r8, r9, sl, fp} + f534: ebf5d291 bl 0xffd83f80 + f538: 080c0f4e stmeqda ip, {r1, r2, r3, r6, r8, r9, sl, fp} + f53c: e3a00051 mov r0, #81 ; 0x51 + f540: e3800c0f orr r0, r0, #3840 ; 0xf00 + f544: e3800703 orr r0, r0, #786432 ; 0xc0000 + f548: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f54c: e58d0438 str r0, [sp, #1080] + f550: e28cc018 add ip, ip, #24 ; 0x18 + f554: e1a00fac mov r0, ip, lsr #31 + f558: e08ff100 add pc, pc, r0, lsl #2 + f55c: 080c0df0 stmeqda ip, {r4, r5, r6, r7, r8, sl, fp} + f560: ebf5ce7b bl 0xffd82f54 + f564: eafffd59 b 0xead0 + f568: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + f56c: 00000000 andeq r0, r0, r0 + f570: ebf5d282 bl 0xffd83f80 + f574: 080c0e82 stmeqda ip, {r1, r7, r9, sl, fp} + f578: e3b00001 movs r0, #1 ; 0x1 + f57c: e58d0418 str r0, [sp, #1048] + f580: ebf5d27e bl 0xffd83f80 + f584: 080c0e84 stmeqda ip, {r2, r7, r9, sl, fp} + f588: e59d0434 ldr r0, [sp, #1076] + f58c: e2800f01 add r0, r0, #4 ; 0x4 + f590: ebf5d0e0 bl 0xffd83918 + f594: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + f598: e1a03000 mov r3, r0 + f59c: ebf5d277 bl 0xffd83f80 + f5a0: 080c0e86 stmeqda ip, {r1, r2, r7, r9, sl, fp} + f5a4: e283001c add r0, r3, #28 ; 0x1c + f5a8: ebf5d0da bl 0xffd83918 + f5ac: 080c0e8a stmeqda ip, {r1, r3, r7, r9, sl, fp} + f5b0: e1a07000 mov r7, r0 + f5b4: ebf5d271 bl 0xffd83f80 + f5b8: 080c0e88 stmeqda ip, {r3, r7, r9, sl, fp} + f5bc: e2870000 add r0, r7, #0 ; 0x0 + f5c0: ebf5d07d bl 0xffd837bc + f5c4: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + f5c8: e1a04000 mov r4, r0 + f5cc: ebf5d26b bl 0xffd83f80 + f5d0: 080c0e8a stmeqda ip, {r1, r3, r7, r9, sl, fp} + f5d4: e3b030c7 movs r3, #199 ; 0xc7 + f5d8: ebf5d268 bl 0xffd83f80 + f5dc: 080c0e8c stmeqda ip, {r2, r3, r7, r9, sl, fp} + f5e0: e1a01003 mov r1, r3 + f5e4: e0133004 ands r3, r3, r4 + f5e8: ebf5d264 bl 0xffd83f80 + f5ec: 080c0e8e stmeqda ip, {r1, r2, r3, r7, r9, sl, fp} + f5f0: e59d1418 ldr r1, [sp, #1048] + f5f4: e59d1418 ldr r1, [sp, #1048] + f5f8: e2915001 adds r5, r1, #1 ; 0x1 + f5fc: ebf5d25f bl 0xffd83f80 + f600: 080c0e90 stmeqda ip, {r4, r7, r9, sl, fp} + f604: e1a00005 mov r0, r5 + f608: e58d0424 str r0, [sp, #1060] + f60c: ebf5d25b bl 0xffd83f80 + f610: 080c0e92 stmeqda ip, {r1, r4, r7, r9, sl, fp} + f614: e3b05040 movs r5, #64 ; 0x40 + f618: ebf5d258 bl 0xffd83f80 + f61c: 080c0e94 stmeqda ip, {r2, r4, r7, r9, sl, fp} + f620: e1a01005 mov r1, r5 + f624: e0955007 adds r5, r5, r7 + f628: ebf5d254 bl 0xffd83f80 + f62c: 080c0e96 stmeqda ip, {r1, r2, r4, r7, r9, sl, fp} + f630: e1a00005 mov r0, r5 + f634: e58d0420 str r0, [sp, #1056] + f638: ebf5d250 bl 0xffd83f80 + f63c: 080c0e98 stmeqda ip, {r3, r4, r7, r9, sl, fp} + f640: e3530000 cmp r3, #0 ; 0x0 + f644: ebf5d24d bl 0xffd83f80 + f648: 080c0e9a stmeqda ip, {r1, r3, r4, r7, r9, sl, fp} + f64c: e28cc02d add ip, ip, #45 ; 0x2d + f650: 0a000004 beq 0xf668 + f654: e1a00fac mov r0, ip, lsr #31 + f658: e08ff100 add pc, pc, r0, lsl #2 + f65c: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + f660: ebf5ce3b bl 0xffd82f54 + f664: ea000007 b 0xf688 + f668: ebf5d244 bl 0xffd83f80 + f66c: 080c0e9c stmeqda ip, {r2, r3, r4, r7, r9, sl, fp} + f670: e28cc003 add ip, ip, #3 ; 0x3 + f674: e1a00fac mov r0, ip, lsr #31 + f678: e08ff100 add pc, pc, r0, lsl #2 + f67c: 080c1258 stmeqda ip, {r3, r4, r6, r9, ip} + f680: ebf5ce33 bl 0xffd82f54 + f684: eafff243 b 0xbf98 + f688: ebf5d23c bl 0xffd83f80 + f68c: 080c0e9e stmeqda ip, {r1, r2, r3, r4, r7, r9, sl, fp} + f690: e59d1418 ldr r1, [sp, #1048] + f694: e3510002 cmp r1, #2 ; 0x2 + f698: ebf5d238 bl 0xffd83f80 + f69c: 080c0ea0 stmeqda ip, {r5, r7, r9, sl, fp} + f6a0: e28cc006 add ip, ip, #6 ; 0x6 + f6a4: 1a000004 bne 0xf6bc + f6a8: e1a00fac mov r0, ip, lsr #31 + f6ac: e08ff100 add pc, pc, r0, lsl #2 + f6b0: 080c0ed0 stmeqda ip, {r4, r6, r7, r9, sl, fp} + f6b4: ebf5ce26 bl 0xffd82f54 + f6b8: eafff356 b 0xc418 + f6bc: ebf5d22f bl 0xffd83f80 + f6c0: 080c0ea2 stmeqda ip, {r1, r5, r7, r9, sl, fp} + f6c4: e59d1418 ldr r1, [sp, #1048] + f6c8: e3510002 cmp r1, #2 ; 0x2 + f6cc: ebf5d22b bl 0xffd83f80 + f6d0: 080c0ea4 stmeqda ip, {r2, r5, r7, r9, sl, fp} + f6d4: e28cc006 add ip, ip, #6 ; 0x6 + f6d8: da000004 ble 0xf6f0 + f6dc: e1a00fac mov r0, ip, lsr #31 + f6e0: e08ff100 add pc, pc, r0, lsl #2 + f6e4: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + f6e8: ebf5ce19 bl 0xffd82f54 + f6ec: ea000014 b 0xf744 + f6f0: ebf5d222 bl 0xffd83f80 + f6f4: 080c0ea6 stmeqda ip, {r1, r2, r5, r7, r9, sl, fp} + f6f8: e59d1418 ldr r1, [sp, #1048] + f6fc: e3510001 cmp r1, #1 ; 0x1 + f700: ebf5d21e bl 0xffd83f80 + f704: 080c0ea8 stmeqda ip, {r3, r5, r7, r9, sl, fp} + f708: e28cc006 add ip, ip, #6 ; 0x6 + f70c: 1a000004 bne 0xf724 + f710: e1a00fac mov r0, ip, lsr #31 + f714: e08ff100 add pc, pc, r0, lsl #2 + f718: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + f71c: ebf5ce0c bl 0xffd82f54 + f720: ea00001c b 0xf798 + f724: ebf5d215 bl 0xffd83f80 + f728: 080c0eaa stmeqda ip, {r1, r3, r5, r7, r9, sl, fp} + f72c: e28cc003 add ip, ip, #3 ; 0x3 + f730: e1a00fac mov r0, ip, lsr #31 + f734: e08ff100 add pc, pc, r0, lsl #2 + f738: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + f73c: ebf5ce04 bl 0xffd82f54 + f740: eafffdfc b 0xef38 + f744: ebf5d20d bl 0xffd83f80 + f748: 080c0eac stmeqda ip, {r2, r3, r5, r7, r9, sl, fp} + f74c: e59d1418 ldr r1, [sp, #1048] + f750: e3510003 cmp r1, #3 ; 0x3 + f754: ebf5d209 bl 0xffd83f80 + f758: 080c0eae stmeqda ip, {r1, r2, r3, r5, r7, r9, sl, fp} + f75c: e28cc006 add ip, ip, #6 ; 0x6 + f760: 1a000004 bne 0xf778 + f764: e1a00fac mov r0, ip, lsr #31 + f768: e08ff100 add pc, pc, r0, lsl #2 + f76c: 080c0ee8 stmeqda ip, {r3, r5, r6, r7, r9, sl, fp} + f770: ebf5cdf7 bl 0xffd82f54 + f774: eafffeb1 b 0xf240 + f778: ebf5d200 bl 0xffd83f80 + f77c: 080c0eb0 stmeqda ip, {r4, r5, r7, r9, sl, fp} + f780: e28cc003 add ip, ip, #3 ; 0x3 + f784: e1a00fac mov r0, ip, lsr #31 + f788: e08ff100 add pc, pc, r0, lsl #2 + f78c: 080c0f08 stmeqda ip, {r3, r8, r9, sl, fp} + f790: ebf5cdef bl 0xffd82f54 + f794: eafffde7 b 0xef38 + f798: ebf5d1f8 bl 0xffd83f80 + f79c: 080c0eb2 stmeqda ip, {r1, r4, r5, r7, r9, sl, fp} + f7a0: e3a00fb1 mov r0, #708 ; 0x2c4 + f7a4: e3800b03 orr r0, r0, #3072 ; 0xc00 + f7a8: e3800703 orr r0, r0, #786432 ; 0xc0000 + f7ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f7b0: ebf5d058 bl 0xffd83918 + f7b4: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + f7b8: e1a03000 mov r3, r0 + f7bc: ebf5d1ef bl 0xffd83f80 + f7c0: 080c0eb4 stmeqda ip, {r2, r4, r5, r7, r9, sl, fp} + f7c4: e59d0434 ldr r0, [sp, #1076] + f7c8: e2800f02 add r0, r0, #8 ; 0x8 + f7cc: e1a01003 mov r1, r3 + f7d0: ebf5cf7d bl 0xffd835cc + f7d4: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + f7d8: ebf5d1e8 bl 0xffd83f80 + f7dc: 080c0eb6 stmeqda ip, {r1, r2, r4, r5, r7, r9, sl, fp} + f7e0: e3a00fb2 mov r0, #712 ; 0x2c8 + f7e4: e3800b03 orr r0, r0, #3072 ; 0xc00 + f7e8: e3800703 orr r0, r0, #786432 ; 0xc0000 + f7ec: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f7f0: ebf5d048 bl 0xffd83918 + f7f4: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + f7f8: e58d041c str r0, [sp, #1052] + f7fc: ebf5d1df bl 0xffd83f80 + f800: 080c0eb8 stmeqda ip, {r3, r4, r5, r7, r9, sl, fp} + f804: e3a00fb3 mov r0, #716 ; 0x2cc + f808: e3800b03 orr r0, r0, #3072 ; 0xc00 + f80c: e3800703 orr r0, r0, #786432 ; 0xc0000 + f810: e3800302 orr r0, r0, #134217728 ; 0x8000000 + f814: ebf5d03f bl 0xffd83918 + f818: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + f81c: e1a05000 mov r5, r0 + f820: ebf5d1d6 bl 0xffd83f80 + f824: 080c0eba stmeqda ip, {r1, r3, r4, r5, r7, r9, sl, fp} + f828: e1a00005 mov r0, r5 + f82c: e58d0428 str r0, [sp, #1064] + f830: ebf5d1d2 bl 0xffd83f80 + f834: 080c0ebc stmeqda ip, {r2, r3, r4, r5, r7, r9, sl, fp} + f838: e1a01003 mov r1, r3 + f83c: e2933004 adds r3, r3, #4 ; 0x4 + f840: ebf5d1ce bl 0xffd83f80 + f844: 080c0ebe stmeqda ip, {r1, r2, r3, r4, r5, r7, r9, sl, fp} + f848: e59d0434 ldr r0, [sp, #1076] + f84c: e2800f03 add r0, r0, #12 ; 0xc + f850: e1a01003 mov r1, r3 + f854: ebf5cf5c bl 0xffd835cc + f858: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + f85c: ebf5d1c7 bl 0xffd83f80 + f860: 080c0ec0 stmeqda ip, {r6, r7, r9, sl, fp} + f864: e1a01005 mov r1, r5 + f868: e2955002 adds r5, r5, #2 ; 0x2 + f86c: ebf5d1c3 bl 0xffd83f80 + f870: 080c0ec2 stmeqda ip, {r1, r6, r7, r9, sl, fp} + f874: e28cc023 add ip, ip, #35 ; 0x23 + f878: e1a00fac mov r0, ip, lsr #31 + f87c: e08ff100 add pc, pc, r0, lsl #2 + f880: 080c0f18 stmeqda ip, {r3, r4, r8, r9, sl, fp} + f884: ebf5cdb2 bl 0xffd82f54 + f888: eafffeaa b 0xf338 + f88c: 080c0438 stmeqda ip, {r3, r4, r5, sl} + f890: 00000000 andeq r0, r0, r0 + f894: ebf5d1b9 bl 0xffd83f80 + f898: 080c0438 stmeqda ip, {r3, r4, r5, sl} + f89c: e59d9434 ldr r9, [sp, #1076] + f8a0: e3c99003 bic r9, r9, #3 ; 0x3 + f8a4: e2890004 add r0, r9, #4 ; 0x4 + f8a8: e58d0434 str r0, [sp, #1076] + f8ac: e2890000 add r0, r9, #0 ; 0x0 + f8b0: ebf5d018 bl 0xffd83918 + f8b4: 080c043c stmeqda ip, {r2, r3, r4, r5, sl} + f8b8: e1a03000 mov r3, r0 + f8bc: ebf5d1af bl 0xffd83f80 + f8c0: 080c043a stmeqda ip, {r1, r3, r4, r5, sl} + f8c4: e1a00003 mov r0, r3 + f8c8: e28cc007 add ip, ip, #7 ; 0x7 + f8cc: eaf5cdff b 0xffd830d0 + f8d0: 08000518 stmeqda r0, {r3, r4, r8, sl} + f8d4: 00000000 andeq r0, r0, r0 + f8d8: ebf5d1a8 bl 0xffd83f80 + f8dc: 08000518 stmeqda r0, {r3, r4, r8, sl} + f8e0: e59d9434 ldr r9, [sp, #1076] + f8e4: e3c99003 bic r9, r9, #3 ; 0x3 + f8e8: e2890004 add r0, r9, #4 ; 0x4 + f8ec: e58d0434 str r0, [sp, #1076] + f8f0: e2890000 add r0, r9, #0 ; 0x0 + f8f4: ebf5d007 bl 0xffd83918 + f8f8: 0800051c stmeqda r0, {r2, r3, r4, r8, sl} + f8fc: e1a03000 mov r3, r0 + f900: ebf5d19e bl 0xffd83f80 + f904: 0800051a stmeqda r0, {r1, r3, r4, r8, sl} + f908: e1a00003 mov r0, r3 + f90c: e28cc007 add ip, ip, #7 ; 0x7 + f910: eaf5cdee b 0xffd830d0 + f914: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f918: 00000000 andeq r0, r0, r0 + f91c: ebf5d197 bl 0xffd83f80 + f920: 080bfdd4 stmeqda fp, {r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f924: e59d1420 ldr r1, [sp, #1056] + f928: e1a07001 mov r7, r1 + f92c: ebf5d193 bl 0xffd83f80 + f930: 080bfdd6 stmeqda fp, {r1, r2, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f934: e59d1424 ldr r1, [sp, #1060] + f938: e1a08001 mov r8, r1 + f93c: ebf5d18f bl 0xffd83f80 + f940: 080bfdd8 stmeqda fp, {r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f944: e59d1428 ldr r1, [sp, #1064] + f948: e1a00001 mov r0, r1 + f94c: e58d0418 str r0, [sp, #1048] + f950: ebf5d18a bl 0xffd83f80 + f954: 080bfdda stmeqda fp, {r1, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f958: e59d142c ldr r1, [sp, #1068] + f95c: e1a00001 mov r0, r1 + f960: e58d041c str r0, [sp, #1052] + f964: ebf5d185 bl 0xffd83f80 + f968: 080bfddc stmeqda fp, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f96c: e59d9434 ldr r9, [sp, #1076] + f970: e3c99003 bic r9, r9, #3 ; 0x3 + f974: e2499010 sub r9, r9, #16 ; 0x10 + f978: e58d9434 str r9, [sp, #1076] + f97c: e2890000 add r0, r9, #0 ; 0x0 + f980: e1a01007 mov r1, r7 + f984: ebf5cf30 bl 0xffd8364c + f988: e2890004 add r0, r9, #4 ; 0x4 + f98c: e1a01008 mov r1, r8 + f990: ebf5cf2d bl 0xffd8364c + f994: e2890008 add r0, r9, #8 ; 0x8 + f998: e59d1418 ldr r1, [sp, #1048] + f99c: ebf5cf2a bl 0xffd8364c + f9a0: e289000c add r0, r9, #12 ; 0xc + f9a4: e59d141c ldr r1, [sp, #1052] + f9a8: ebf5cf07 bl 0xffd835cc + f9ac: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9b0: ebf5d172 bl 0xffd83f80 + f9b4: 080bfdde stmeqda fp, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9b8: e1a01003 mov r1, r3 + f9bc: e2930000 adds r0, r3, #0 ; 0x0 + f9c0: e58d041c str r0, [sp, #1052] + f9c4: ebf5d16d bl 0xffd83f80 + f9c8: 080bfde0 stmeqda fp, {r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9cc: e59d041c ldr r0, [sp, #1052] + f9d0: e2800004 add r0, r0, #4 ; 0x4 + f9d4: ebf5cfcf bl 0xffd83918 + f9d8: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9dc: e1a03000 mov r3, r0 + f9e0: ebf5d166 bl 0xffd83f80 + f9e4: 080bfde2 stmeqda fp, {r1, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9e8: e3530000 cmp r3, #0 ; 0x0 + f9ec: ebf5d163 bl 0xffd83f80 + f9f0: 080bfde4 stmeqda fp, {r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + f9f4: e28cc021 add ip, ip, #33 ; 0x21 + f9f8: ba000004 blt 0xfa10 + f9fc: e1a00fac mov r0, ip, lsr #31 + fa00: e08ff100 add pc, pc, r0, lsl #2 + fa04: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa08: ebf5cd51 bl 0xffd82f54 + fa0c: ea000007 b 0xfa30 + fa10: ebf5d15a bl 0xffd83f80 + fa14: 080bfde6 stmeqda fp, {r1, r2, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa18: e28cc003 add ip, ip, #3 ; 0x3 + fa1c: e1a00fac mov r0, ip, lsr #31 + fa20: e08ff100 add pc, pc, r0, lsl #2 + fa24: 080c0000 stmeqda ip, {} + fa28: ebf5cd49 bl 0xffd82f54 + fa2c: eaffecd0 b 0xad74 + fa30: ebf5d152 bl 0xffd83f80 + fa34: 080bfde8 stmeqda fp, {r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa38: e3a00f06 mov r0, #24 ; 0x18 + fa3c: e3800703 orr r0, r0, #786432 ; 0xc0000 + fa40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fa44: ebf5cfb3 bl 0xffd83918 + fa48: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa4c: e1a03000 mov r3, r0 + fa50: ebf5d14a bl 0xffd83f80 + fa54: 080bfdea stmeqda fp, {r1, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa58: e2830000 add r0, r3, #0 ; 0x0 + fa5c: ebf5cfad bl 0xffd83918 + fa60: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa64: e1a03000 mov r3, r0 + fa68: ebf5d144 bl 0xffd83f80 + fa6c: 080bfdec stmeqda fp, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa70: e1a00003 mov r0, r3 + fa74: e58d0420 str r0, [sp, #1056] + fa78: ebf5d140 bl 0xffd83f80 + fa7c: 080bfdee stmeqda fp, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa80: e59d141c ldr r1, [sp, #1052] + fa84: e59d141c ldr r1, [sp, #1052] + fa88: e2913000 adds r3, r1, #0 ; 0x0 + fa8c: ebf5d13b bl 0xffd83f80 + fa90: 080bfdf0 stmeqda fp, {r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa94: ebf5d139 bl 0xffd83f80 + fa98: 080bfdf2 stmeqda fp, {r1, r4, r5, r6, r7, r8, sl, fp, ip, sp, lr, pc} + fa9c: e3a000f5 mov r0, #245 ; 0xf5 + faa0: e3800cfd orr r0, r0, #64768 ; 0xfd00 + faa4: e380080b orr r0, r0, #720896 ; 0xb0000 + faa8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + faac: e58d0438 str r0, [sp, #1080] + fab0: e28cc016 add ip, ip, #22 ; 0x16 + fab4: e1a00fac mov r0, ip, lsr #31 + fab8: e08ff100 add pc, pc, r0, lsl #2 + fabc: 080c0bb0 stmeqda ip, {r4, r5, r7, r8, r9, fp} + fac0: ebf5cd23 bl 0xffd82f54 + fac4: eaffed00 b 0xaecc + fac8: 0800035e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9} + facc: 00000000 andeq r0, r0, r0 + fad0: ebf5d12a bl 0xffd83f80 + fad4: 0800035e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9} + fad8: e3a00f11 mov r0, #68 ; 0x44 + fadc: e3800b01 orr r0, r0, #1024 ; 0x400 + fae0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fae4: ebf5cf8b bl 0xffd83918 + fae8: 08000362 stmeqda r0, {r1, r5, r6, r8, r9} + faec: e1a03000 mov r3, r0 + faf0: ebf5d122 bl 0xffd83f80 + faf4: 08000360 stmeqda r0, {r5, r6, r8, r9} + faf8: ebf5d120 bl 0xffd83f80 + fafc: 08000362 stmeqda r0, {r1, r5, r6, r8, r9} + fb00: e3a00065 mov r0, #101 ; 0x65 + fb04: e3800c03 orr r0, r0, #768 ; 0x300 + fb08: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fb0c: e58d0438 str r0, [sp, #1080] + fb10: e28cc00b add ip, ip, #11 ; 0xb + fb14: e1a00fac mov r0, ip, lsr #31 + fb18: e08ff100 add pc, pc, r0, lsl #2 + fb1c: 080057c8 stmeqda r0, {r3, r6, r7, r8, r9, sl, ip, lr} + fb20: ebf5cd0b bl 0xffd82f54 + fb24: ea000001 b 0xfb30 + fb28: 080057c8 stmeqda r0, {r3, r6, r7, r8, r9, sl, ip, lr} + fb2c: 00000000 andeq r0, r0, r0 + fb30: ebf5d112 bl 0xffd83f80 + fb34: 080057c8 stmeqda r0, {r3, r6, r7, r8, r9, sl, ip, lr} + fb38: e3a00e7d mov r0, #2000 ; 0x7d0 + fb3c: e3800a05 orr r0, r0, #20480 ; 0x5000 + fb40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fb44: ebf5cf73 bl 0xffd83918 + fb48: 080057cc stmeqda r0, {r2, r3, r6, r7, r8, r9, sl, ip, lr} + fb4c: e1a04000 mov r4, r0 + fb50: ebf5d10a bl 0xffd83f80 + fb54: 080057ca stmeqda r0, {r1, r3, r6, r7, r8, r9, sl, ip, lr} + fb58: e2840000 add r0, r4, #0 ; 0x0 + fb5c: e1a01003 mov r1, r3 + fb60: ebf5ce99 bl 0xffd835cc + fb64: 080057cc stmeqda r0, {r2, r3, r6, r7, r8, r9, sl, ip, lr} + fb68: ebf5d104 bl 0xffd83f80 + fb6c: 080057cc stmeqda r0, {r2, r3, r6, r7, r8, r9, sl, ip, lr} + fb70: e59d0438 ldr r0, [sp, #1080] + fb74: e28cc00c add ip, ip, #12 ; 0xc + fb78: eaf5cd54 b 0xffd830d0 + fb7c: 08000364 stmeqda r0, {r2, r5, r6, r8, r9} + fb80: 00000000 andeq r0, r0, r0 + fb84: ebf5d0fd bl 0xffd83f80 + fb88: 08000364 stmeqda r0, {r2, r5, r6, r8, r9} + fb8c: e3b03000 movs r3, #0 ; 0x0 + fb90: ebf5d0fa bl 0xffd83f80 + fb94: 08000366 stmeqda r0, {r1, r2, r5, r6, r8, r9} + fb98: ebf5d0f8 bl 0xffd83f80 + fb9c: 08000368 stmeqda r0, {r3, r5, r6, r8, r9} + fba0: e3a0006b mov r0, #107 ; 0x6b + fba4: e3800c03 orr r0, r0, #768 ; 0x300 + fba8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fbac: e58d0438 str r0, [sp, #1080] + fbb0: e28cc009 add ip, ip, #9 ; 0x9 + fbb4: e1a00fac mov r0, ip, lsr #31 + fbb8: e08ff100 add pc, pc, r0, lsl #2 + fbbc: 08002b80 stmeqda r0, {r7, r8, r9, fp, sp} + fbc0: ebf5cce3 bl 0xffd82f54 + fbc4: ea000001 b 0xfbd0 + fbc8: 08002b80 stmeqda r0, {r7, r8, r9, fp, sp} + fbcc: 00000000 andeq r0, r0, r0 + fbd0: ebf5d0ea bl 0xffd83f80 + fbd4: 08002b80 stmeqda r0, {r7, r8, r9, fp, sp} + fbd8: e59d9434 ldr r9, [sp, #1076] + fbdc: e3c99003 bic r9, r9, #3 ; 0x3 + fbe0: e2499010 sub r9, r9, #16 ; 0x10 + fbe4: e58d9434 str r9, [sp, #1076] + fbe8: e2890000 add r0, r9, #0 ; 0x0 + fbec: e1a01007 mov r1, r7 + fbf0: ebf5ce95 bl 0xffd8364c + fbf4: e2890004 add r0, r9, #4 ; 0x4 + fbf8: e1a01008 mov r1, r8 + fbfc: ebf5ce92 bl 0xffd8364c + fc00: e2890008 add r0, r9, #8 ; 0x8 + fc04: e59d1418 ldr r1, [sp, #1048] + fc08: ebf5ce8f bl 0xffd8364c + fc0c: e289000c add r0, r9, #12 ; 0xc + fc10: e59d1438 ldr r1, [sp, #1080] + fc14: ebf5ce8c bl 0xffd8364c + fc18: ebf5d0d8 bl 0xffd83f80 + fc1c: 08002b82 stmeqda r0, {r1, r7, r8, r9, fp, sp} + fc20: e1a01003 mov r1, r3 + fc24: e2937000 adds r7, r3, #0 ; 0x0 + fc28: ebf5d0d4 bl 0xffd83f80 + fc2c: 08002b84 stmeqda r0, {r2, r7, r8, r9, fp, sp} + fc30: e1b07807 movs r7, r7, lsl #16 + fc34: ebf5d0d1 bl 0xffd83f80 + fc38: 08002b86 stmeqda r0, {r1, r2, r7, r8, r9, fp, sp} + fc3c: e1b00827 movs r0, r7, lsr #16 + fc40: e58d0418 str r0, [sp, #1048] + fc44: ebf5d0cd bl 0xffd83f80 + fc48: 08002b88 stmeqda r0, {r3, r7, r8, r9, fp, sp} + fc4c: e1b07847 movs r7, r7, asr #16 + fc50: ebf5d0ca bl 0xffd83f80 + fc54: 08002b8a stmeqda r0, {r1, r3, r7, r8, r9, fp, sp} + fc58: e1a01007 mov r1, r7 + fc5c: e2973000 adds r3, r7, #0 ; 0x0 + fc60: ebf5d0c6 bl 0xffd83f80 + fc64: 08002b8c stmeqda r0, {r2, r3, r7, r8, r9, fp, sp} + fc68: ebf5d0c4 bl 0xffd83f80 + fc6c: 08002b8e stmeqda r0, {r1, r2, r3, r7, r8, r9, fp, sp} + fc70: e3a00091 mov r0, #145 ; 0x91 + fc74: e3800c2b orr r0, r0, #11008 ; 0x2b00 + fc78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fc7c: e58d0438 str r0, [sp, #1080] + fc80: e28cc01b add ip, ip, #27 ; 0x1b + fc84: e1a00fac mov r0, ip, lsr #31 + fc88: e08ff100 add pc, pc, r0, lsl #2 + fc8c: 08002b44 stmeqda r0, {r2, r6, r8, r9, fp, sp} + fc90: ebf5ccaf bl 0xffd82f54 + fc94: ea000001 b 0xfca0 + fc98: 08002b44 stmeqda r0, {r2, r6, r8, r9, fp, sp} + fc9c: 00000000 andeq r0, r0, r0 + fca0: ebf5d0b6 bl 0xffd83f80 + fca4: 08002b44 stmeqda r0, {r2, r6, r8, r9, fp, sp} + fca8: e59d9434 ldr r9, [sp, #1076] + fcac: e3c99003 bic r9, r9, #3 ; 0x3 + fcb0: e2499004 sub r9, r9, #4 ; 0x4 + fcb4: e58d9434 str r9, [sp, #1076] + fcb8: e2890000 add r0, r9, #0 ; 0x0 + fcbc: e59d1438 ldr r1, [sp, #1080] + fcc0: ebf5ce61 bl 0xffd8364c + fcc4: ebf5d0ad bl 0xffd83f80 + fcc8: 08002b46 stmeqda r0, {r1, r2, r6, r8, r9, fp, sp} + fccc: e3a00fde mov r0, #888 ; 0x378 + fcd0: e3800b0a orr r0, r0, #10240 ; 0x2800 + fcd4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fcd8: ebf5cf0e bl 0xffd83918 + fcdc: 08002b4a stmeqda r0, {r1, r3, r6, r8, r9, fp, sp} + fce0: e1a04000 mov r4, r0 + fce4: ebf5d0a5 bl 0xffd83f80 + fce8: 08002b48 stmeqda r0, {r3, r6, r8, r9, fp, sp} + fcec: e3a00fdf mov r0, #892 ; 0x37c + fcf0: e3800b0a orr r0, r0, #10240 ; 0x2800 + fcf4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fcf8: ebf5cf06 bl 0xffd83918 + fcfc: 08002b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, sp} + fd00: e1a05000 mov r5, r0 + fd04: ebf5d09d bl 0xffd83f80 + fd08: 08002b4a stmeqda r0, {r1, r3, r6, r8, r9, fp, sp} + fd0c: e1b03803 movs r3, r3, lsl #16 + fd10: ebf5d09a bl 0xffd83f80 + fd14: 08002b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, sp} + fd18: e1b036c3 movs r3, r3, asr #13 + fd1c: ebf5d097 bl 0xffd83f80 + fd20: 08002b4e stmeqda r0, {r1, r2, r3, r6, r8, r9, fp, sp} + fd24: e1a01003 mov r1, r3 + fd28: e0933005 adds r3, r3, r5 + fd2c: ebf5d093 bl 0xffd83f80 + fd30: 08002b50 stmeqda r0, {r4, r6, r8, r9, fp, sp} + fd34: e2830000 add r0, r3, #0 ; 0x0 + fd38: ebf5ceca bl 0xffd83868 + fd3c: 08002b54 stmeqda r0, {r2, r4, r6, r8, r9, fp, sp} + fd40: e1a03000 mov r3, r0 + fd44: ebf5d08d bl 0xffd83f80 + fd48: 08002b52 stmeqda r0, {r1, r4, r6, r8, r9, fp, sp} + fd4c: e2840010 add r0, r4, #16 ; 0x10 + fd50: ebf5cec4 bl 0xffd83868 + fd54: 08002b56 stmeqda r0, {r1, r2, r4, r6, r8, r9, fp, sp} + fd58: e1a05000 mov r5, r0 + fd5c: ebf5d087 bl 0xffd83f80 + fd60: 08002b54 stmeqda r0, {r2, r4, r6, r8, r9, fp, sp} + fd64: e3b05000 movs r5, #0 ; 0x0 + fd68: ebf5d084 bl 0xffd83f80 + fd6c: 08002b56 stmeqda r0, {r1, r2, r4, r6, r8, r9, fp, sp} + fd70: e2840010 add r0, r4, #16 ; 0x10 + fd74: e1a01003 mov r1, r3 + fd78: ebf5cdf3 bl 0xffd8354c + fd7c: 08002b58 stmeqda r0, {r3, r4, r6, r8, r9, fp, sp} + fd80: ebf5d07e bl 0xffd83f80 + fd84: 08002b58 stmeqda r0, {r3, r4, r6, r8, r9, fp, sp} + fd88: e3b030aa movs r3, #170 ; 0xaa + fd8c: ebf5d07b bl 0xffd83f80 + fd90: 08002b5a stmeqda r0, {r1, r3, r4, r6, r8, r9, fp, sp} + fd94: e1b03183 movs r3, r3, lsl #3 + fd98: ebf5d078 bl 0xffd83f80 + fd9c: 08002b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, sp} + fda0: e1a01004 mov r1, r4 + fda4: e0944003 adds r4, r4, r3 + fda8: ebf5d074 bl 0xffd83f80 + fdac: 08002b5e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, fp, sp} + fdb0: e2840000 add r0, r4, #0 ; 0x0 + fdb4: e1a01005 mov r1, r5 + fdb8: ebf5ce03 bl 0xffd835cc + fdbc: 08002b60 stmeqda r0, {r5, r6, r8, r9, fp, sp} + fdc0: ebf5d06e bl 0xffd83f80 + fdc4: 08002b60 stmeqda r0, {r5, r6, r8, r9, fp, sp} + fdc8: ebf5d06c bl 0xffd83f80 + fdcc: 08002b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, sp} + fdd0: e3a00065 mov r0, #101 ; 0x65 + fdd4: e3800c2b orr r0, r0, #11008 ; 0x2b00 + fdd8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fddc: e58d0438 str r0, [sp, #1080] + fde0: e28cc03a add ip, ip, #58 ; 0x3a + fde4: e1a00fac mov r0, ip, lsr #31 + fde8: e08ff100 add pc, pc, r0, lsl #2 + fdec: 08000a40 stmeqda r0, {r6, r9, fp} + fdf0: ebf5cc57 bl 0xffd82f54 + fdf4: ea000001 b 0xfe00 + fdf8: 08000a40 stmeqda r0, {r6, r9, fp} + fdfc: 00000000 andeq r0, r0, r0 + fe00: ebf5d05e bl 0xffd83f80 + fe04: 08000a40 stmeqda r0, {r6, r9, fp} + fe08: e59d9434 ldr r9, [sp, #1076] + fe0c: e3c99003 bic r9, r9, #3 ; 0x3 + fe10: e2499004 sub r9, r9, #4 ; 0x4 + fe14: e58d9434 str r9, [sp, #1076] + fe18: e2890000 add r0, r9, #0 ; 0x0 + fe1c: e59d1438 ldr r1, [sp, #1080] + fe20: ebf5ce09 bl 0xffd8364c + fe24: ebf5d055 bl 0xffd83f80 + fe28: 08000a42 stmeqda r0, {r1, r6, r9, fp} + fe2c: e3b05007 movs r5, #7 ; 0x7 + fe30: ebf5d052 bl 0xffd83f80 + fe34: 08000a44 stmeqda r0, {r2, r6, r9, fp} + fe38: e3a00f99 mov r0, #612 ; 0x264 + fe3c: e3800b02 orr r0, r0, #2048 ; 0x800 + fe40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fe44: ebf5ceb3 bl 0xffd83918 + fe48: 08000a48 stmeqda r0, {r3, r6, r9, fp} + fe4c: e1a04000 mov r4, r0 + fe50: ebf5d04a bl 0xffd83f80 + fe54: 08000a46 stmeqda r0, {r1, r2, r6, r9, fp} + fe58: e3a00f9a mov r0, #616 ; 0x268 + fe5c: e3800b02 orr r0, r0, #2048 ; 0x800 + fe60: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fe64: ebf5ceab bl 0xffd83918 + fe68: 08000a4a stmeqda r0, {r1, r3, r6, r9, fp} + fe6c: e1a03000 mov r3, r0 + fe70: ebf5d042 bl 0xffd83f80 + fe74: 08000a48 stmeqda r0, {r3, r6, r9, fp} + fe78: e3b06000 movs r6, #0 ; 0x0 + fe7c: ebf5d03f bl 0xffd83f80 + fe80: 08000a4a stmeqda r0, {r1, r3, r6, r9, fp} + fe84: e1a01003 mov r1, r3 + fe88: e2933054 adds r3, r3, #84 ; 0x54 + fe8c: e28cc016 add ip, ip, #22 ; 0x16 + fe90: ebf5d03a bl 0xffd83f80 + fe94: 08000a4c stmeqda r0, {r2, r3, r6, r9, fp} + fe98: e2830000 add r0, r3, #0 ; 0x0 + fe9c: e1a01006 mov r1, r6 + fea0: ebf5cda9 bl 0xffd8354c + fea4: 08000a4e stmeqda r0, {r1, r2, r3, r6, r9, fp} + fea8: ebf5d034 bl 0xffd83f80 + feac: 08000a4e stmeqda r0, {r1, r2, r3, r6, r9, fp} + feb0: e1a01003 mov r1, r3 + feb4: e253300c subs r3, r3, #12 ; 0xc + feb8: ebf5d030 bl 0xffd83f80 + febc: 08000a50 stmeqda r0, {r4, r6, r9, fp} + fec0: e1a01005 mov r1, r5 + fec4: e2555001 subs r5, r5, #1 ; 0x1 + fec8: ebf5d02c bl 0xffd83f80 + fecc: 08000a52 stmeqda r0, {r1, r4, r6, r9, fp} + fed0: e3550000 cmp r5, #0 ; 0x0 + fed4: ebf5d029 bl 0xffd83f80 + fed8: 08000a54 stmeqda r0, {r2, r4, r6, r9, fp} + fedc: e28cc010 add ip, ip, #16 ; 0x10 + fee0: da000004 ble 0xfef8 + fee4: e1a00fac mov r0, ip, lsr #31 + fee8: e08ff100 add pc, pc, r0, lsl #2 + feec: 08000a4c stmeqda r0, {r2, r3, r6, r9, fp} + fef0: ebf5cc17 bl 0xffd82f54 + fef4: eaffffe5 b 0xfe90 + fef8: ebf5d020 bl 0xffd83f80 + fefc: 08000a56 stmeqda r0, {r1, r2, r4, r6, r9, fp} + ff00: e3b05080 movs r5, #128 ; 0x80 + ff04: ebf5d01d bl 0xffd83f80 + ff08: 08000a58 stmeqda r0, {r3, r4, r6, r9, fp} + ff0c: e1b05385 movs r5, r5, lsl #7 + ff10: ebf5d01a bl 0xffd83f80 + ff14: 08000a5a stmeqda r0, {r1, r3, r4, r6, r9, fp} + ff18: e3b03000 movs r3, #0 ; 0x0 + ff1c: ebf5d017 bl 0xffd83f80 + ff20: 08000a5c stmeqda r0, {r2, r3, r4, r6, r9, fp} + ff24: ebf5d015 bl 0xffd83f80 + ff28: 08000a5e stmeqda r0, {r1, r2, r3, r4, r6, r9, fp} + ff2c: e3a00061 mov r0, #97 ; 0x61 + ff30: e3800c0a orr r0, r0, #2560 ; 0xa00 + ff34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + ff38: e58d0438 str r0, [sp, #1080] + ff3c: e28cc00f add ip, ip, #15 ; 0xf + ff40: e1a00fac mov r0, ip, lsr #31 + ff44: e08ff100 add pc, pc, r0, lsl #2 + ff48: 080009dc stmeqda r0, {r2, r3, r4, r6, r7, r8, fp} + ff4c: ebf5cc00 bl 0xffd82f54 + ff50: ea000001 b 0xff5c + ff54: 080009dc stmeqda r0, {r2, r3, r4, r6, r7, r8, fp} + ff58: 00000000 andeq r0, r0, r0 + ff5c: ebf5d007 bl 0xffd83f80 + ff60: 080009dc stmeqda r0, {r2, r3, r4, r6, r7, r8, fp} + ff64: e59d9434 ldr r9, [sp, #1076] + ff68: e3c99003 bic r9, r9, #3 ; 0x3 + ff6c: e2499010 sub r9, r9, #16 ; 0x10 + ff70: e58d9434 str r9, [sp, #1076] + ff74: e2890000 add r0, r9, #0 ; 0x0 + ff78: e1a01007 mov r1, r7 + ff7c: ebf5cdb2 bl 0xffd8364c + ff80: e2890004 add r0, r9, #4 ; 0x4 + ff84: e1a01008 mov r1, r8 + ff88: ebf5cdaf bl 0xffd8364c + ff8c: e2890008 add r0, r9, #8 ; 0x8 + ff90: e59d1418 ldr r1, [sp, #1048] + ff94: ebf5cdac bl 0xffd8364c + ff98: e289000c add r0, r9, #12 ; 0xc + ff9c: e59d1438 ldr r1, [sp, #1080] + ffa0: ebf5cda9 bl 0xffd8364c + ffa4: ebf5cff5 bl 0xffd83f80 + ffa8: 080009de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, fp} + ffac: e59d1420 ldr r1, [sp, #1056] + ffb0: e1a00001 mov r0, r1 + ffb4: e58d0418 str r0, [sp, #1048] + ffb8: ebf5cff0 bl 0xffd83f80 + ffbc: 080009e0 stmeqda r0, {r5, r6, r7, r8, fp} + ffc0: e59d9434 ldr r9, [sp, #1076] + ffc4: e3c99003 bic r9, r9, #3 ; 0x3 + ffc8: e2499004 sub r9, r9, #4 ; 0x4 + ffcc: e58d9434 str r9, [sp, #1076] + ffd0: e2890000 add r0, r9, #0 ; 0x0 + ffd4: e59d1418 ldr r1, [sp, #1048] + ffd8: ebf5cd7b bl 0xffd835cc + ffdc: 080009e2 stmeqda r0, {r1, r5, r6, r7, r8, fp} + ffe0: ebf5cfe6 bl 0xffd83f80 + ffe4: 080009e2 stmeqda r0, {r1, r5, r6, r7, r8, fp} + ffe8: e3a00f8a mov r0, #552 ; 0x228 + ffec: e3800b02 orr r0, r0, #2048 ; 0x800 + fff0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + fff4: ebf5ce47 bl 0xffd83918 + fff8: 080009e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, fp} + fffc: e1a08000 mov r8, r0 + 10000: ebf5cfde bl 0xffd83f80 + 10004: 080009e4 stmeqda r0, {r2, r5, r6, r7, r8, fp} + 10008: e1b06083 movs r6, r3, lsl #1 + 1000c: ebf5cfdb bl 0xffd83f80 + 10010: 080009e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, fp} + 10014: e1a01006 mov r1, r6 + 10018: e0966003 adds r6, r6, r3 + 1001c: ebf5cfd7 bl 0xffd83f80 + 10020: 080009e8 stmeqda r0, {r3, r5, r6, r7, r8, fp} + 10024: e1b06106 movs r6, r6, lsl #2 + 10028: ebf5cfd4 bl 0xffd83f80 + 1002c: 080009ea stmeqda r0, {r1, r3, r5, r6, r7, r8, fp} + 10030: e1a01006 mov r1, r6 + 10034: e0967008 adds r7, r6, r8 + 10038: ebf5cfd0 bl 0xffd83f80 + 1003c: 080009ec stmeqda r0, {r2, r3, r5, r6, r7, r8, fp} + 10040: e3b03000 movs r3, #0 ; 0x0 + 10044: ebf5cfcd bl 0xffd83f80 + 10048: 080009ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, fp} + 1004c: e1a00003 mov r0, r3 + 10050: e58d0420 str r0, [sp, #1056] + 10054: ebf5cfc9 bl 0xffd83f80 + 10058: 080009f0 stmeqda r0, {r4, r5, r6, r7, r8, fp} + 1005c: e3b03080 movs r3, #128 ; 0x80 + 10060: ebf5cfc6 bl 0xffd83f80 + 10064: 080009f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, fp} + 10068: e2870000 add r0, r7, #0 ; 0x0 + 1006c: e1a01003 mov r1, r3 + 10070: ebf5cd35 bl 0xffd8354c + 10074: 080009f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, fp} + 10078: ebf5cfc0 bl 0xffd83f80 + 1007c: 080009f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, fp} + 10080: e1a01008 mov r1, r8 + 10084: e2987004 adds r7, r8, #4 ; 0x4 + 10088: ebf5cfbc bl 0xffd83f80 + 1008c: 080009f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, fp} + 10090: e1a01006 mov r1, r6 + 10094: e0967007 adds r7, r6, r7 + 10098: ebf5cfb8 bl 0xffd83f80 + 1009c: 080009f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, fp} + 100a0: e1a01005 mov r1, r5 + 100a4: e2955003 adds r5, r5, #3 ; 0x3 + 100a8: ebf5cfb4 bl 0xffd83f80 + 100ac: 080009fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, fp} + 100b0: e3b00004 movs r0, #4 ; 0x4 + 100b4: e58d0418 str r0, [sp, #1048] + 100b8: ebf5cfb0 bl 0xffd83f80 + 100bc: 080009fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, fp} + 100c0: e59d0418 ldr r0, [sp, #1048] + 100c4: e3a01000 mov r1, #0 ; 0x0 + 100c8: e0510000 subs r0, r1, r0 + 100cc: e58d0418 str r0, [sp, #1048] + 100d0: ebf5cfaa bl 0xffd83f80 + 100d4: 080009fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, fp} + 100d8: e1a01005 mov r1, r5 + 100dc: e59d0418 ldr r0, [sp, #1048] + 100e0: e0155000 ands r5, r5, r0 + 100e4: ebf5cfa5 bl 0xffd83f80 + 100e8: 08000a00 stmeqda r0, {r9, fp} + 100ec: e2870000 add r0, r7, #0 ; 0x0 + 100f0: e1a01005 mov r1, r5 + 100f4: ebf5cd34 bl 0xffd835cc + 100f8: 08000a02 stmeqda r0, {r1, r9, fp} + 100fc: ebf5cf9f bl 0xffd83f80 + 10100: 08000a02 stmeqda r0, {r1, r9, fp} + 10104: e1a01008 mov r1, r8 + 10108: e2988008 adds r8, r8, #8 ; 0x8 + 1010c: ebf5cf9b bl 0xffd83f80 + 10110: 08000a04 stmeqda r0, {r2, r9, fp} + 10114: e1a01006 mov r1, r6 + 10118: e0966008 adds r6, r6, r8 + 1011c: ebf5cf97 bl 0xffd83f80 + 10120: 08000a06 stmeqda r0, {r1, r2, r9, fp} + 10124: e1a01004 mov r1, r4 + 10128: e2943003 adds r3, r4, #3 ; 0x3 + 1012c: ebf5cf93 bl 0xffd83f80 + 10130: 08000a08 stmeqda r0, {r3, r9, fp} + 10134: e1a01003 mov r1, r3 + 10138: e59d0418 ldr r0, [sp, #1048] + 1013c: e0133000 ands r3, r3, r0 + 10140: ebf5cf8e bl 0xffd83f80 + 10144: 08000a0a stmeqda r0, {r1, r3, r9, fp} + 10148: e2860000 add r0, r6, #0 ; 0x0 + 1014c: e1a01003 mov r1, r3 + 10150: ebf5cd1d bl 0xffd835cc + 10154: 08000a0c stmeqda r0, {r2, r3, r9, fp} + 10158: ebf5cf88 bl 0xffd83f80 + 1015c: 08000a0c stmeqda r0, {r2, r3, r9, fp} + 10160: e59d1420 ldr r1, [sp, #1056] + 10164: e1a03001 mov r3, r1 + 10168: ebf5cf84 bl 0xffd83f80 + 1016c: 08000a0e stmeqda r0, {r1, r2, r3, r9, fp} + 10170: e2840000 add r0, r4, #0 ; 0x0 + 10174: e1a01003 mov r1, r3 + 10178: ebf5ccd4 bl 0xffd834d0 + 1017c: 08000a10 stmeqda r0, {r4, r9, fp} + 10180: ebf5cf7e bl 0xffd83f80 + 10184: 08000a10 stmeqda r0, {r4, r9, fp} + 10188: e2870000 add r0, r7, #0 ; 0x0 + 1018c: ebf5cde1 bl 0xffd83918 + 10190: 08000a14 stmeqda r0, {r2, r4, r9, fp} + 10194: e1a05000 mov r5, r0 + 10198: ebf5cf78 bl 0xffd83f80 + 1019c: 08000a12 stmeqda r0, {r1, r4, r9, fp} + 101a0: e1a01005 mov r1, r5 + 101a4: e2555004 subs r5, r5, #4 ; 0x4 + 101a8: ebf5cf74 bl 0xffd83f80 + 101ac: 08000a14 stmeqda r0, {r2, r4, r9, fp} + 101b0: e1b05405 movs r5, r5, lsl #8 + 101b4: ebf5cf71 bl 0xffd83f80 + 101b8: 08000a16 stmeqda r0, {r1, r2, r4, r9, fp} + 101bc: e2840000 add r0, r4, #0 ; 0x0 + 101c0: ebf5cd7d bl 0xffd837bc + 101c4: 08000a1a stmeqda r0, {r1, r3, r4, r9, fp} + 101c8: e1a03000 mov r3, r0 + 101cc: ebf5cf6b bl 0xffd83f80 + 101d0: 08000a18 stmeqda r0, {r3, r4, r9, fp} + 101d4: e1a01003 mov r1, r3 + 101d8: e1933005 orrs r3, r3, r5 + 101dc: ebf5cf67 bl 0xffd83f80 + 101e0: 08000a1a stmeqda r0, {r1, r3, r4, r9, fp} + 101e4: e2840000 add r0, r4, #0 ; 0x0 + 101e8: e1a01003 mov r1, r3 + 101ec: ebf5ccf6 bl 0xffd835cc + 101f0: 08000a1c stmeqda r0, {r2, r3, r4, r9, fp} + 101f4: ebf5cf61 bl 0xffd83f80 + 101f8: 08000a1c stmeqda r0, {r2, r3, r4, r9, fp} + 101fc: e59d9434 ldr r9, [sp, #1076] + 10200: e3c99003 bic r9, r9, #3 ; 0x3 + 10204: e2890004 add r0, r9, #4 ; 0x4 + 10208: e58d0434 str r0, [sp, #1076] + 1020c: e2890000 add r0, r9, #0 ; 0x0 + 10210: ebf5cdc0 bl 0xffd83918 + 10214: 08000a20 stmeqda r0, {r5, r9, fp} + 10218: e1a06000 mov r6, r0 + 1021c: ebf5cf57 bl 0xffd83f80 + 10220: 08000a1e stmeqda r0, {r1, r2, r3, r4, r9, fp} + 10224: e1a00006 mov r0, r6 + 10228: e58d0420 str r0, [sp, #1056] + 1022c: ebf5cf53 bl 0xffd83f80 + 10230: 08000a20 stmeqda r0, {r5, r9, fp} + 10234: e59d9434 ldr r9, [sp, #1076] + 10238: e3c99003 bic r9, r9, #3 ; 0x3 + 1023c: e289000c add r0, r9, #12 ; 0xc + 10240: e58d0434 str r0, [sp, #1076] + 10244: e2890000 add r0, r9, #0 ; 0x0 + 10248: ebf5cdb2 bl 0xffd83918 + 1024c: 08000a24 stmeqda r0, {r2, r5, r9, fp} + 10250: e1a07000 mov r7, r0 + 10254: e2890004 add r0, r9, #4 ; 0x4 + 10258: ebf5cdae bl 0xffd83918 + 1025c: 08000a24 stmeqda r0, {r2, r5, r9, fp} + 10260: e1a08000 mov r8, r0 + 10264: e2890008 add r0, r9, #8 ; 0x8 + 10268: ebf5cdaa bl 0xffd83918 + 1026c: 08000a24 stmeqda r0, {r2, r5, r9, fp} + 10270: e58d0418 str r0, [sp, #1048] + 10274: ebf5cf41 bl 0xffd83f80 + 10278: 08000a22 stmeqda r0, {r1, r5, r9, fp} + 1027c: e59d9434 ldr r9, [sp, #1076] + 10280: e3c99003 bic r9, r9, #3 ; 0x3 + 10284: e2890004 add r0, r9, #4 ; 0x4 + 10288: e58d0434 str r0, [sp, #1076] + 1028c: e2890000 add r0, r9, #0 ; 0x0 + 10290: ebf5cda0 bl 0xffd83918 + 10294: 08000a26 stmeqda r0, {r1, r2, r5, r9, fp} + 10298: e1a03000 mov r3, r0 + 1029c: ebf5cf37 bl 0xffd83f80 + 102a0: 08000a24 stmeqda r0, {r2, r5, r9, fp} + 102a4: e1a00003 mov r0, r3 + 102a8: e28cc083 add ip, ip, #131 ; 0x83 + 102ac: eaf5cb87 b 0xffd830d0 + 102b0: 08000a60 stmeqda r0, {r5, r6, r9, fp} + 102b4: 00000000 andeq r0, r0, r0 + 102b8: ebf5cf30 bl 0xffd83f80 + 102bc: 08000a60 stmeqda r0, {r5, r6, r9, fp} + 102c0: e59d9434 ldr r9, [sp, #1076] + 102c4: e3c99003 bic r9, r9, #3 ; 0x3 + 102c8: e2890004 add r0, r9, #4 ; 0x4 + 102cc: e58d0434 str r0, [sp, #1076] + 102d0: e2890000 add r0, r9, #0 ; 0x0 + 102d4: ebf5cd8f bl 0xffd83918 + 102d8: 08000a64 stmeqda r0, {r2, r5, r6, r9, fp} + 102dc: e1a03000 mov r3, r0 + 102e0: ebf5cf26 bl 0xffd83f80 + 102e4: 08000a62 stmeqda r0, {r1, r5, r6, r9, fp} + 102e8: e1a00003 mov r0, r3 + 102ec: e28cc007 add ip, ip, #7 ; 0x7 + 102f0: eaf5cb76 b 0xffd830d0 + 102f4: 08002b64 stmeqda r0, {r2, r5, r6, r8, r9, fp, sp} + 102f8: 00000000 andeq r0, r0, r0 + 102fc: ebf5cf1f bl 0xffd83f80 + 10300: 08002b64 stmeqda r0, {r2, r5, r6, r8, r9, fp, sp} + 10304: e3b03080 movs r3, #128 ; 0x80 + 10308: ebf5cf1c bl 0xffd83f80 + 1030c: 08002b66 stmeqda r0, {r1, r2, r5, r6, r8, r9, fp, sp} + 10310: ebf5cf1a bl 0xffd83f80 + 10314: 08002b68 stmeqda r0, {r3, r5, r6, r8, r9, fp, sp} + 10318: e3a0006b mov r0, #107 ; 0x6b + 1031c: e3800c2b orr r0, r0, #11008 ; 0x2b00 + 10320: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10324: e58d0438 str r0, [sp, #1080] + 10328: e28cc009 add ip, ip, #9 ; 0x9 + 1032c: e1a00fac mov r0, ip, lsr #31 + 10330: e08ff100 add pc, pc, r0, lsl #2 + 10334: 080012c4 stmeqda r0, {r2, r6, r7, r9, ip} + 10338: ebf5cb05 bl 0xffd82f54 + 1033c: ea000001 b 0x10348 + 10340: 080012c4 stmeqda r0, {r2, r6, r7, r9, ip} + 10344: 00000000 andeq r0, r0, r0 + 10348: ebf5cf0c bl 0xffd83f80 + 1034c: 080012c4 stmeqda r0, {r2, r6, r7, r9, ip} + 10350: e59d9434 ldr r9, [sp, #1076] + 10354: e3c99003 bic r9, r9, #3 ; 0x3 + 10358: e2499008 sub r9, r9, #8 ; 0x8 + 1035c: e58d9434 str r9, [sp, #1076] + 10360: e2890000 add r0, r9, #0 ; 0x0 + 10364: e1a01007 mov r1, r7 + 10368: ebf5ccb7 bl 0xffd8364c + 1036c: e2890004 add r0, r9, #4 ; 0x4 + 10370: e59d1438 ldr r1, [sp, #1080] + 10374: ebf5ccb4 bl 0xffd8364c + 10378: ebf5cf00 bl 0xffd83f80 + 1037c: 080012c6 stmeqda r0, {r1, r2, r6, r7, r9, ip} + 10380: e3a00fba mov r0, #744 ; 0x2e8 + 10384: e3800a01 orr r0, r0, #4096 ; 0x1000 + 10388: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1038c: ebf5cd61 bl 0xffd83918 + 10390: 080012ca stmeqda r0, {r1, r3, r6, r7, r9, ip} + 10394: e1a04000 mov r4, r0 + 10398: ebf5cef8 bl 0xffd83f80 + 1039c: 080012c8 stmeqda r0, {r3, r6, r7, r9, ip} + 103a0: e3a00fbb mov r0, #748 ; 0x2ec + 103a4: e3800a01 orr r0, r0, #4096 ; 0x1000 + 103a8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 103ac: ebf5cd59 bl 0xffd83918 + 103b0: 080012cc stmeqda r0, {r2, r3, r6, r7, r9, ip} + 103b4: e1a05000 mov r5, r0 + 103b8: ebf5cef0 bl 0xffd83f80 + 103bc: 080012ca stmeqda r0, {r1, r3, r6, r7, r9, ip} + 103c0: e2840000 add r0, r4, #0 ; 0x0 + 103c4: e1a01005 mov r1, r5 + 103c8: ebf5cc7f bl 0xffd835cc + 103cc: 080012cc stmeqda r0, {r2, r3, r6, r7, r9, ip} + 103d0: ebf5ceea bl 0xffd83f80 + 103d4: 080012cc stmeqda r0, {r2, r3, r6, r7, r9, ip} + 103d8: e3a00e2f mov r0, #752 ; 0x2f0 + 103dc: e3800a01 orr r0, r0, #4096 ; 0x1000 + 103e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 103e4: ebf5cd4b bl 0xffd83918 + 103e8: 080012d0 stmeqda r0, {r4, r6, r7, r9, ip} + 103ec: e1a06000 mov r6, r0 + 103f0: ebf5cee2 bl 0xffd83f80 + 103f4: 080012ce stmeqda r0, {r1, r2, r3, r6, r7, r9, ip} + 103f8: e3a00fbd mov r0, #756 ; 0x2f4 + 103fc: e3800a01 orr r0, r0, #4096 ; 0x1000 + 10400: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10404: ebf5cd43 bl 0xffd83918 + 10408: 080012d2 stmeqda r0, {r1, r4, r6, r7, r9, ip} + 1040c: e1a07000 mov r7, r0 + 10410: ebf5ceda bl 0xffd83f80 + 10414: 080012d0 stmeqda r0, {r4, r6, r7, r9, ip} + 10418: e2870000 add r0, r7, #0 ; 0x0 + 1041c: e1a01003 mov r1, r3 + 10420: ebf5cc69 bl 0xffd835cc + 10424: 080012d2 stmeqda r0, {r1, r4, r6, r7, r9, ip} + 10428: ebf5ced4 bl 0xffd83f80 + 1042c: 080012d2 stmeqda r0, {r1, r4, r6, r7, r9, ip} + 10430: e3b040bc movs r4, #188 ; 0xbc + 10434: ebf5ced1 bl 0xffd83f80 + 10438: 080012d4 stmeqda r0, {r2, r4, r6, r7, r9, ip} + 1043c: e1a01003 mov r1, r3 + 10440: e0130493 muls r3, r3, r4 + 10444: ebf5cecd bl 0xffd83f80 + 10448: 080012d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, ip} + 1044c: e1a01003 mov r1, r3 + 10450: e0933005 adds r3, r3, r5 + 10454: ebf5cec9 bl 0xffd83f80 + 10458: 080012d8 stmeqda r0, {r3, r4, r6, r7, r9, ip} + 1045c: e2860000 add r0, r6, #0 ; 0x0 + 10460: e1a01003 mov r1, r3 + 10464: ebf5cc58 bl 0xffd835cc + 10468: 080012da stmeqda r0, {r1, r3, r4, r6, r7, r9, ip} + 1046c: ebf5cec3 bl 0xffd83f80 + 10470: 080012da stmeqda r0, {r1, r3, r4, r6, r7, r9, ip} + 10474: ebf5cec1 bl 0xffd83f80 + 10478: 080012dc stmeqda r0, {r2, r3, r4, r6, r7, r9, ip} + 1047c: e3a000df mov r0, #223 ; 0xdf + 10480: e3800c12 orr r0, r0, #4608 ; 0x1200 + 10484: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10488: e58d0438 str r0, [sp, #1080] + 1048c: e28cc033 add ip, ip, #51 ; 0x33 + 10490: e1a00fac mov r0, ip, lsr #31 + 10494: e08ff100 add pc, pc, r0, lsl #2 + 10498: 080013d0 stmeqda r0, {r4, r6, r7, r8, r9, ip} + 1049c: ebf5caac bl 0xffd82f54 + 104a0: ea000001 b 0x104ac + 104a4: 080013d0 stmeqda r0, {r4, r6, r7, r8, r9, ip} + 104a8: 00000000 andeq r0, r0, r0 + 104ac: ebf5ceb3 bl 0xffd83f80 + 104b0: 080013d0 stmeqda r0, {r4, r6, r7, r8, r9, ip} + 104b4: e59d9434 ldr r9, [sp, #1076] + 104b8: e3c99003 bic r9, r9, #3 ; 0x3 + 104bc: e249900c sub r9, r9, #12 ; 0xc + 104c0: e58d9434 str r9, [sp, #1076] + 104c4: e2890000 add r0, r9, #0 ; 0x0 + 104c8: e1a01007 mov r1, r7 + 104cc: ebf5cc5e bl 0xffd8364c + 104d0: e2890004 add r0, r9, #4 ; 0x4 + 104d4: e1a01008 mov r1, r8 + 104d8: ebf5cc5b bl 0xffd8364c + 104dc: e2890008 add r0, r9, #8 ; 0x8 + 104e0: e59d1438 ldr r1, [sp, #1080] + 104e4: ebf5cc58 bl 0xffd8364c + 104e8: ebf5cea4 bl 0xffd83f80 + 104ec: 080013d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, ip} + 104f0: e3a00f02 mov r0, #8 ; 0x8 + 104f4: e3800b05 orr r0, r0, #5120 ; 0x1400 + 104f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 104fc: ebf5cd05 bl 0xffd83918 + 10500: 080013d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, ip} + 10504: e1a07000 mov r7, r0 + 10508: ebf5ce9c bl 0xffd83f80 + 1050c: 080013d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, ip} + 10510: e3a00f03 mov r0, #12 ; 0xc + 10514: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10518: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1051c: ebf5ccfd bl 0xffd83918 + 10520: 080013d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, ip} + 10524: e1a03000 mov r3, r0 + 10528: ebf5ce94 bl 0xffd83f80 + 1052c: 080013d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, ip} + 10530: e3a00e41 mov r0, #1040 ; 0x410 + 10534: e3800a01 orr r0, r0, #4096 ; 0x1000 + 10538: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1053c: ebf5ccf5 bl 0xffd83918 + 10540: 080013da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, ip} + 10544: e1a08000 mov r8, r0 + 10548: ebf5ce8c bl 0xffd83f80 + 1054c: 080013d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, ip} + 10550: e3b06000 movs r6, #0 ; 0x0 + 10554: ebf5ce89 bl 0xffd83f80 + 10558: 080013da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, ip} + 1055c: e3a00f05 mov r0, #20 ; 0x14 + 10560: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10564: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10568: ebf5ccea bl 0xffd83918 + 1056c: 080013de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, ip} + 10570: e1a05000 mov r5, r0 + 10574: ebf5ce81 bl 0xffd83f80 + 10578: 080013dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, ip} + 1057c: e3a00f06 mov r0, #24 ; 0x18 + 10580: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10584: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10588: ebf5cce2 bl 0xffd83918 + 1058c: 080013e0 stmeqda r0, {r5, r6, r7, r8, r9, ip} + 10590: e1a04000 mov r4, r0 + 10594: e28cc021 add ip, ip, #33 ; 0x21 + 10598: ebf5ce78 bl 0xffd83f80 + 1059c: 080013de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, ip} + 105a0: e2850000 add r0, r5, #0 ; 0x0 + 105a4: e1a01006 mov r1, r6 + 105a8: ebf5cbe7 bl 0xffd8354c + 105ac: 080013e0 stmeqda r0, {r5, r6, r7, r8, r9, ip} + 105b0: ebf5ce72 bl 0xffd83f80 + 105b4: 080013e0 stmeqda r0, {r5, r6, r7, r8, r9, ip} + 105b8: e1a01005 mov r1, r5 + 105bc: e2955002 adds r5, r5, #2 ; 0x2 + 105c0: ebf5ce6e bl 0xffd83f80 + 105c4: 080013e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, ip} + 105c8: e1a01004 mov r1, r4 + 105cc: e2544001 subs r4, r4, #1 ; 0x1 + 105d0: ebf5ce6a bl 0xffd83f80 + 105d4: 080013e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, ip} + 105d8: e3540000 cmp r4, #0 ; 0x0 + 105dc: ebf5ce67 bl 0xffd83f80 + 105e0: 080013e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, ip} + 105e4: e28cc010 add ip, ip, #16 ; 0x10 + 105e8: 0a000004 beq 0x10600 + 105ec: e1a00fac mov r0, ip, lsr #31 + 105f0: e08ff100 add pc, pc, r0, lsl #2 + 105f4: 080013de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, ip} + 105f8: ebf5ca55 bl 0xffd82f54 + 105fc: eaffffe5 b 0x10598 + 10600: ebf5ce5e bl 0xffd83f80 + 10604: 080013e8 stmeqda r0, {r3, r5, r6, r7, r8, r9, ip} + 10608: e2870000 add r0, r7, #0 ; 0x0 + 1060c: ebf5ccc1 bl 0xffd83918 + 10610: 080013ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, ip} + 10614: e1a04000 mov r4, r0 + 10618: ebf5ce58 bl 0xffd83f80 + 1061c: 080013ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, ip} + 10620: e1a01003 mov r1, r3 + 10624: e2935000 adds r5, r3, #0 ; 0x0 + 10628: ebf5ce54 bl 0xffd83f80 + 1062c: 080013ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, ip} + 10630: e2850000 add r0, r5, #0 ; 0x0 + 10634: ebf5ccb7 bl 0xffd83918 + 10638: 080013f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, ip} + 1063c: e1a03000 mov r3, r0 + 10640: ebf5ce4e bl 0xffd83f80 + 10644: 080013ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, ip} + 10648: e1540003 cmp r4, r3 + 1064c: ebf5ce4b bl 0xffd83f80 + 10650: 080013f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, ip} + 10654: e28cc013 add ip, ip, #19 ; 0x13 + 10658: 3a000004 bcc 0x10670 + 1065c: e1a00fac mov r0, ip, lsr #31 + 10660: e08ff100 add pc, pc, r0, lsl #2 + 10664: 080013fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, ip} + 10668: ebf5ca39 bl 0xffd82f54 + 1066c: ea00001f b 0x106f0 + 10670: ebf5ce42 bl 0xffd83f80 + 10674: 080013f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, ip} + 10678: e3b06000 movs r6, #0 ; 0x0 + 1067c: e28cc003 add ip, ip, #3 ; 0x3 + 10680: ebf5ce3e bl 0xffd83f80 + 10684: 080013f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, ip} + 10688: e2840000 add r0, r4, #0 ; 0x0 + 1068c: e1a01006 mov r1, r6 + 10690: ebf5cbcd bl 0xffd835cc + 10694: 080013f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, ip} + 10698: ebf5ce38 bl 0xffd83f80 + 1069c: 080013f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, ip} + 106a0: e1a01004 mov r1, r4 + 106a4: e29440bc adds r4, r4, #188 ; 0xbc + 106a8: ebf5ce34 bl 0xffd83f80 + 106ac: 080013f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, ip} + 106b0: e2850000 add r0, r5, #0 ; 0x0 + 106b4: ebf5cc97 bl 0xffd83918 + 106b8: 080013fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, ip} + 106bc: e1a03000 mov r3, r0 + 106c0: ebf5ce2e bl 0xffd83f80 + 106c4: 080013fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, ip} + 106c8: e1540003 cmp r4, r3 + 106cc: ebf5ce2b bl 0xffd83f80 + 106d0: 080013fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, ip} + 106d4: e28cc012 add ip, ip, #18 ; 0x12 + 106d8: 2a000004 bcs 0x106f0 + 106dc: e1a00fac mov r0, ip, lsr #31 + 106e0: e08ff100 add pc, pc, r0, lsl #2 + 106e4: 080013f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, ip} + 106e8: ebf5ca19 bl 0xffd82f54 + 106ec: eaffffe3 b 0x10680 + 106f0: ebf5ce22 bl 0xffd83f80 + 106f4: 080013fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, ip} + 106f8: e2870000 add r0, r7, #0 ; 0x0 + 106fc: ebf5cc85 bl 0xffd83918 + 10700: 08001402 stmeqda r0, {r1, sl, ip} + 10704: e1a03000 mov r3, r0 + 10708: ebf5ce1c bl 0xffd83f80 + 1070c: 08001400 stmeqda r0, {sl, ip} + 10710: e2880000 add r0, r8, #0 ; 0x0 + 10714: e1a01003 mov r1, r3 + 10718: ebf5cbab bl 0xffd835cc + 1071c: 08001402 stmeqda r0, {r1, sl, ip} + 10720: ebf5ce16 bl 0xffd83f80 + 10724: 08001402 stmeqda r0, {r1, sl, ip} + 10728: e59d9434 ldr r9, [sp, #1076] + 1072c: e3c99003 bic r9, r9, #3 ; 0x3 + 10730: e2890008 add r0, r9, #8 ; 0x8 + 10734: e58d0434 str r0, [sp, #1076] + 10738: e2890000 add r0, r9, #0 ; 0x0 + 1073c: ebf5cc75 bl 0xffd83918 + 10740: 08001406 stmeqda r0, {r1, r2, sl, ip} + 10744: e1a07000 mov r7, r0 + 10748: e2890004 add r0, r9, #4 ; 0x4 + 1074c: ebf5cc71 bl 0xffd83918 + 10750: 08001406 stmeqda r0, {r1, r2, sl, ip} + 10754: e1a08000 mov r8, r0 + 10758: ebf5ce08 bl 0xffd83f80 + 1075c: 08001404 stmeqda r0, {r2, sl, ip} + 10760: e59d9434 ldr r9, [sp, #1076] + 10764: e3c99003 bic r9, r9, #3 ; 0x3 + 10768: e2890004 add r0, r9, #4 ; 0x4 + 1076c: e58d0434 str r0, [sp, #1076] + 10770: e2890000 add r0, r9, #0 ; 0x0 + 10774: ebf5cc67 bl 0xffd83918 + 10778: 08001408 stmeqda r0, {r3, sl, ip} + 1077c: e1a03000 mov r3, r0 + 10780: ebf5cdfe bl 0xffd83f80 + 10784: 08001406 stmeqda r0, {r1, r2, sl, ip} + 10788: e1a00003 mov r0, r3 + 1078c: e28cc015 add ip, ip, #21 ; 0x15 + 10790: eaf5ca4e b 0xffd830d0 + 10794: 080012de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, ip} + 10798: 00000000 andeq r0, r0, r0 + 1079c: ebf5cdf7 bl 0xffd83f80 + 107a0: 080012de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, ip} + 107a4: e2870000 add r0, r7, #0 ; 0x0 + 107a8: ebf5cc5a bl 0xffd83918 + 107ac: 080012e2 stmeqda r0, {r1, r5, r6, r7, r9, ip} + 107b0: e1a03000 mov r3, r0 + 107b4: ebf5cdf1 bl 0xffd83f80 + 107b8: 080012e0 stmeqda r0, {r5, r6, r7, r9, ip} + 107bc: e59d9434 ldr r9, [sp, #1076] + 107c0: e3c99003 bic r9, r9, #3 ; 0x3 + 107c4: e2890004 add r0, r9, #4 ; 0x4 + 107c8: e58d0434 str r0, [sp, #1076] + 107cc: e2890000 add r0, r9, #0 ; 0x0 + 107d0: ebf5cc50 bl 0xffd83918 + 107d4: 080012e4 stmeqda r0, {r2, r5, r6, r7, r9, ip} + 107d8: e1a07000 mov r7, r0 + 107dc: ebf5cde7 bl 0xffd83f80 + 107e0: 080012e2 stmeqda r0, {r1, r5, r6, r7, r9, ip} + 107e4: e59d9434 ldr r9, [sp, #1076] + 107e8: e3c99003 bic r9, r9, #3 ; 0x3 + 107ec: e2890004 add r0, r9, #4 ; 0x4 + 107f0: e58d0434 str r0, [sp, #1076] + 107f4: e2890000 add r0, r9, #0 ; 0x0 + 107f8: ebf5cc46 bl 0xffd83918 + 107fc: 080012e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, ip} + 10800: e1a04000 mov r4, r0 + 10804: ebf5cddd bl 0xffd83f80 + 10808: 080012e4 stmeqda r0, {r2, r5, r6, r7, r9, ip} + 1080c: e1a00004 mov r0, r4 + 10810: e28cc010 add ip, ip, #16 ; 0x10 + 10814: eaf5ca2d b 0xffd830d0 + 10818: 08002b6a stmeqda r0, {r1, r3, r5, r6, r8, r9, fp, sp} + 1081c: 00000000 andeq r0, r0, r0 + 10820: ebf5cdd6 bl 0xffd83f80 + 10824: 08002b6a stmeqda r0, {r1, r3, r5, r6, r8, r9, fp, sp} + 10828: ebf5cdd4 bl 0xffd83f80 + 1082c: 08002b6c stmeqda r0, {r2, r3, r5, r6, r8, r9, fp, sp} + 10830: e3a0006f mov r0, #111 ; 0x6f + 10834: e3800c2b orr r0, r0, #11008 ; 0x2b00 + 10838: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1083c: e58d0438 str r0, [sp, #1080] + 10840: e28cc006 add ip, ip, #6 ; 0x6 + 10844: e1a00fac mov r0, ip, lsr #31 + 10848: e08ff100 add pc, pc, r0, lsl #2 + 1084c: 08003aa0 stmeqda r0, {r5, r7, r9, fp, ip, sp} + 10850: ebf5c9bf bl 0xffd82f54 + 10854: eaffd4c4 b 0x5b6c + 10858: 08002b6e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, fp, sp} + 1085c: 00000000 andeq r0, r0, r0 + 10860: ebf5cdc6 bl 0xffd83f80 + 10864: 08002b6e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, fp, sp} + 10868: ebf5cdc4 bl 0xffd83f80 + 1086c: 08002b70 stmeqda r0, {r4, r5, r6, r8, r9, fp, sp} + 10870: e3a00073 mov r0, #115 ; 0x73 + 10874: e3800c2b orr r0, r0, #11008 ; 0x2b00 + 10878: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1087c: e58d0438 str r0, [sp, #1080] + 10880: e28cc006 add ip, ip, #6 ; 0x6 + 10884: e1a00fac mov r0, ip, lsr #31 + 10888: e08ff100 add pc, pc, r0, lsl #2 + 1088c: 08000bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp} + 10890: ebf5c9af bl 0xffd82f54 + 10894: ea000001 b 0x108a0 + 10898: 08000bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp} + 1089c: 00000000 andeq r0, r0, r0 + 108a0: ebf5cdb6 bl 0xffd83f80 + 108a4: 08000bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp} + 108a8: e3a00f02 mov r0, #8 ; 0x8 + 108ac: e3800b03 orr r0, r0, #3072 ; 0xc00 + 108b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 108b4: ebf5cc17 bl 0xffd83918 + 108b8: 08000bf4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, fp} + 108bc: e1a03000 mov r3, r0 + 108c0: ebf5cdae bl 0xffd83f80 + 108c4: 08000bf2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, fp} + 108c8: e3b05080 movs r5, #128 ; 0x80 + 108cc: ebf5cdab bl 0xffd83f80 + 108d0: 08000bf4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, fp} + 108d4: e1b05185 movs r5, r5, lsl #3 + 108d8: ebf5cda8 bl 0xffd83f80 + 108dc: 08000bf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, fp} + 108e0: e1a01003 mov r1, r3 + 108e4: e0934005 adds r4, r3, r5 + 108e8: ebf5cda4 bl 0xffd83f80 + 108ec: 08000bf8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, fp} + 108f0: e1530004 cmp r3, r4 + 108f4: ebf5cda1 bl 0xffd83f80 + 108f8: 08000bfa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, fp} + 108fc: e28cc014 add ip, ip, #20 ; 0x14 + 10900: 3a000004 bcc 0x10918 + 10904: e1a00fac mov r0, ip, lsr #31 + 10908: e08ff100 add pc, pc, r0, lsl #2 + 1090c: 08000c06 stmeqda r0, {r1, r2, sl, fp} + 10910: ebf5c98f bl 0xffd82f54 + 10914: ea000019 b 0x10980 + 10918: ebf5cd98 bl 0xffd83f80 + 1091c: 08000bfc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, fp} + 10920: e3b05000 movs r5, #0 ; 0x0 + 10924: e28cc003 add ip, ip, #3 ; 0x3 + 10928: ebf5cd94 bl 0xffd83f80 + 1092c: 08000bfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp} + 10930: e2830004 add r0, r3, #4 ; 0x4 + 10934: e1a01005 mov r1, r5 + 10938: ebf5cb23 bl 0xffd835cc + 1093c: 08000c00 stmeqda r0, {sl, fp} + 10940: ebf5cd8e bl 0xffd83f80 + 10944: 08000c00 stmeqda r0, {sl, fp} + 10948: e1a01003 mov r1, r3 + 1094c: e2933008 adds r3, r3, #8 ; 0x8 + 10950: ebf5cd8a bl 0xffd83f80 + 10954: 08000c02 stmeqda r0, {r1, sl, fp} + 10958: e1530004 cmp r3, r4 + 1095c: ebf5cd87 bl 0xffd83f80 + 10960: 08000c04 stmeqda r0, {r2, sl, fp} + 10964: e28cc00d add ip, ip, #13 ; 0xd + 10968: 2a000004 bcs 0x10980 + 1096c: e1a00fac mov r0, ip, lsr #31 + 10970: e08ff100 add pc, pc, r0, lsl #2 + 10974: 08000bfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp} + 10978: ebf5c975 bl 0xffd82f54 + 1097c: eaffffe9 b 0x10928 + 10980: ebf5cd7e bl 0xffd83f80 + 10984: 08000c06 stmeqda r0, {r1, r2, sl, fp} + 10988: e59d0438 ldr r0, [sp, #1080] + 1098c: e28cc003 add ip, ip, #3 ; 0x3 + 10990: eaf5c9ce b 0xffd830d0 + 10994: 08002b72 stmeqda r0, {r1, r4, r5, r6, r8, r9, fp, sp} + 10998: 00000000 andeq r0, r0, r0 + 1099c: ebf5cd77 bl 0xffd83f80 + 109a0: 08002b72 stmeqda r0, {r1, r4, r5, r6, r8, r9, fp, sp} + 109a4: e59d9434 ldr r9, [sp, #1076] + 109a8: e3c99003 bic r9, r9, #3 ; 0x3 + 109ac: e2890004 add r0, r9, #4 ; 0x4 + 109b0: e58d0434 str r0, [sp, #1076] + 109b4: e2890000 add r0, r9, #0 ; 0x0 + 109b8: ebf5cbd6 bl 0xffd83918 + 109bc: 08002b76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, fp, sp} + 109c0: e1a03000 mov r3, r0 + 109c4: ebf5cd6d bl 0xffd83f80 + 109c8: 08002b74 stmeqda r0, {r2, r4, r5, r6, r8, r9, fp, sp} + 109cc: e1a00003 mov r0, r3 + 109d0: e28cc007 add ip, ip, #7 ; 0x7 + 109d4: eaf5c9bd b 0xffd830d0 + 109d8: 08002b90 stmeqda r0, {r4, r7, r8, r9, fp, sp} + 109dc: 00000000 andeq r0, r0, r0 + 109e0: ebf5cd66 bl 0xffd83f80 + 109e4: 08002b90 stmeqda r0, {r4, r7, r8, r9, fp, sp} + 109e8: e3b03000 movs r3, #0 ; 0x0 + 109ec: ebf5cd63 bl 0xffd83f80 + 109f0: 08002b92 stmeqda r0, {r1, r4, r7, r8, r9, fp, sp} + 109f4: e3b04001 movs r4, #1 ; 0x1 + 109f8: ebf5cd60 bl 0xffd83f80 + 109fc: 08002b94 stmeqda r0, {r2, r4, r7, r8, r9, fp, sp} + 10a00: ebf5cd5e bl 0xffd83f80 + 10a04: 08002b96 stmeqda r0, {r1, r2, r4, r7, r8, r9, fp, sp} + 10a08: e3a00099 mov r0, #153 ; 0x99 + 10a0c: e3800c2b orr r0, r0, #11008 ; 0x2b00 + 10a10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10a14: e58d0438 str r0, [sp, #1080] + 10a18: e28cc00c add ip, ip, #12 ; 0xc + 10a1c: e1a00fac mov r0, ip, lsr #31 + 10a20: e08ff100 add pc, pc, r0, lsl #2 + 10a24: 08001480 stmeqda r0, {r7, sl, ip} + 10a28: ebf5c949 bl 0xffd82f54 + 10a2c: ea000001 b 0x10a38 + 10a30: 08001480 stmeqda r0, {r7, sl, ip} + 10a34: 00000000 andeq r0, r0, r0 + 10a38: ebf5cd50 bl 0xffd83f80 + 10a3c: 08001480 stmeqda r0, {r7, sl, ip} + 10a40: e59d9434 ldr r9, [sp, #1076] + 10a44: e3c99003 bic r9, r9, #3 ; 0x3 + 10a48: e249900c sub r9, r9, #12 ; 0xc + 10a4c: e58d9434 str r9, [sp, #1076] + 10a50: e2890000 add r0, r9, #0 ; 0x0 + 10a54: e1a01007 mov r1, r7 + 10a58: ebf5cafb bl 0xffd8364c + 10a5c: e2890004 add r0, r9, #4 ; 0x4 + 10a60: e1a01008 mov r1, r8 + 10a64: ebf5caf8 bl 0xffd8364c + 10a68: e2890008 add r0, r9, #8 ; 0x8 + 10a6c: e59d1438 ldr r1, [sp, #1080] + 10a70: ebf5caf5 bl 0xffd8364c + 10a74: ebf5cd41 bl 0xffd83f80 + 10a78: 08001482 stmeqda r0, {r1, r7, sl, ip} + 10a7c: e1a01003 mov r1, r3 + 10a80: e2937000 adds r7, r3, #0 ; 0x0 + 10a84: ebf5cd3d bl 0xffd83f80 + 10a88: 08001484 stmeqda r0, {r2, r7, sl, ip} + 10a8c: e1a01004 mov r1, r4 + 10a90: e2948000 adds r8, r4, #0 ; 0x0 + 10a94: ebf5cd39 bl 0xffd83f80 + 10a98: 08001486 stmeqda r0, {r1, r2, r7, sl, ip} + 10a9c: e1a01008 mov r1, r8 + 10aa0: e2983000 adds r3, r8, #0 ; 0x0 + 10aa4: ebf5cd35 bl 0xffd83f80 + 10aa8: 08001488 stmeqda r0, {r3, r7, sl, ip} + 10aac: ebf5cd33 bl 0xffd83f80 + 10ab0: 0800148a stmeqda r0, {r1, r3, r7, sl, ip} + 10ab4: e3a0008d mov r0, #141 ; 0x8d + 10ab8: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10abc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10ac0: e58d0438 str r0, [sp, #1080] + 10ac4: e28cc014 add ip, ip, #20 ; 0x14 + 10ac8: e1a00fac mov r0, ip, lsr #31 + 10acc: e08ff100 add pc, pc, r0, lsl #2 + 10ad0: 0800141c stmeqda r0, {r2, r3, r4, sl, ip} + 10ad4: ebf5c91e bl 0xffd82f54 + 10ad8: ea000001 b 0x10ae4 + 10adc: 0800141c stmeqda r0, {r2, r3, r4, sl, ip} + 10ae0: 00000000 andeq r0, r0, r0 + 10ae4: ebf5cd25 bl 0xffd83f80 + 10ae8: 0800141c stmeqda r0, {r2, r3, r4, sl, ip} + 10aec: e59d9434 ldr r9, [sp, #1076] + 10af0: e3c99003 bic r9, r9, #3 ; 0x3 + 10af4: e249900c sub r9, r9, #12 ; 0xc + 10af8: e58d9434 str r9, [sp, #1076] + 10afc: e2890000 add r0, r9, #0 ; 0x0 + 10b00: e1a01007 mov r1, r7 + 10b04: ebf5cad0 bl 0xffd8364c + 10b08: e2890004 add r0, r9, #4 ; 0x4 + 10b0c: e1a01008 mov r1, r8 + 10b10: ebf5cacd bl 0xffd8364c + 10b14: e2890008 add r0, r9, #8 ; 0x8 + 10b18: e59d1438 ldr r1, [sp, #1080] + 10b1c: ebf5caca bl 0xffd8364c + 10b20: ebf5cd16 bl 0xffd83f80 + 10b24: 0800141e stmeqda r0, {r1, r2, r3, r4, sl, ip} + 10b28: e1a01003 mov r1, r3 + 10b2c: e2938000 adds r8, r3, #0 ; 0x0 + 10b30: ebf5cd12 bl 0xffd83f80 + 10b34: 08001420 stmeqda r0, {r5, sl, ip} + 10b38: e3a00f0f mov r0, #60 ; 0x3c + 10b3c: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10b40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10b44: ebf5cb73 bl 0xffd83918 + 10b48: 08001424 stmeqda r0, {r2, r5, sl, ip} + 10b4c: e1a03000 mov r3, r0 + 10b50: ebf5cd0a bl 0xffd83f80 + 10b54: 08001422 stmeqda r0, {r1, r5, sl, ip} + 10b58: e2830000 add r0, r3, #0 ; 0x0 + 10b5c: ebf5cb6d bl 0xffd83918 + 10b60: 08001426 stmeqda r0, {r1, r2, r5, sl, ip} + 10b64: e1a03000 mov r3, r0 + 10b68: ebf5cd04 bl 0xffd83f80 + 10b6c: 08001424 stmeqda r0, {r2, r5, sl, ip} + 10b70: ebf5cd02 bl 0xffd83f80 + 10b74: 08001426 stmeqda r0, {r1, r2, r5, sl, ip} + 10b78: e3a00029 mov r0, #41 ; 0x29 + 10b7c: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10b80: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10b84: e58d0438 str r0, [sp, #1080] + 10b88: e28cc018 add ip, ip, #24 ; 0x18 + 10b8c: e1a00fac mov r0, ip, lsr #31 + 10b90: e08ff100 add pc, pc, r0, lsl #2 + 10b94: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + 10b98: ebf5c8ed bl 0xffd82f54 + 10b9c: eaffe705 b 0xa7b8 + 10ba0: 08001428 stmeqda r0, {r3, r5, sl, ip} + 10ba4: 00000000 andeq r0, r0, r0 + 10ba8: ebf5ccf4 bl 0xffd83f80 + 10bac: 08001428 stmeqda r0, {r3, r5, sl, ip} + 10bb0: e1a01003 mov r1, r3 + 10bb4: e2937000 adds r7, r3, #0 ; 0x0 + 10bb8: ebf5ccf0 bl 0xffd83f80 + 10bbc: 0800142a stmeqda r0, {r1, r3, r5, sl, ip} + 10bc0: e3570000 cmp r7, #0 ; 0x0 + 10bc4: ebf5cced bl 0xffd83f80 + 10bc8: 0800142c stmeqda r0, {r2, r3, r5, sl, ip} + 10bcc: e28cc009 add ip, ip, #9 ; 0x9 + 10bd0: 1a000004 bne 0x10be8 + 10bd4: e1a00fac mov r0, ip, lsr #31 + 10bd8: e08ff100 add pc, pc, r0, lsl #2 + 10bdc: 08001440 stmeqda r0, {r6, sl, ip} + 10be0: ebf5c8db bl 0xffd82f54 + 10be4: ea000012 b 0x10c34 + 10be8: ebf5cce4 bl 0xffd83f80 + 10bec: 0800142e stmeqda r0, {r1, r2, r3, r5, sl, ip} + 10bf0: e3b040bc movs r4, #188 ; 0xbc + 10bf4: ebf5cce1 bl 0xffd83f80 + 10bf8: 08001430 stmeqda r0, {r4, r5, sl, ip} + 10bfc: ebf5ccdf bl 0xffd83f80 + 10c00: 08001432 stmeqda r0, {r1, r4, r5, sl, ip} + 10c04: e3a00035 mov r0, #53 ; 0x35 + 10c08: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10c0c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10c10: e58d0438 str r0, [sp, #1080] + 10c14: e28cc009 add ip, ip, #9 ; 0x9 + 10c18: e1a00fac mov r0, ip, lsr #31 + 10c1c: e08ff100 add pc, pc, r0, lsl #2 + 10c20: 080c2e4c stmeqda ip, {r2, r3, r6, r9, sl, fp, sp} + 10c24: ebf5c8ca bl 0xffd82f54 + 10c28: ea000023 b 0x10cbc + 10c2c: 08001440 stmeqda r0, {r6, sl, ip} + 10c30: 00000000 andeq r0, r0, r0 + 10c34: ebf5ccd1 bl 0xffd83f80 + 10c38: 08001440 stmeqda r0, {r6, sl, ip} + 10c3c: e3b03000 movs r3, #0 ; 0x0 + 10c40: ebf5ccce bl 0xffd83f80 + 10c44: 08001442 stmeqda r0, {r1, r6, sl, ip} + 10c48: e59d9434 ldr r9, [sp, #1076] + 10c4c: e3c99003 bic r9, r9, #3 ; 0x3 + 10c50: e2890008 add r0, r9, #8 ; 0x8 + 10c54: e58d0434 str r0, [sp, #1076] + 10c58: e2890000 add r0, r9, #0 ; 0x0 + 10c5c: ebf5cb2d bl 0xffd83918 + 10c60: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10c64: e1a07000 mov r7, r0 + 10c68: e2890004 add r0, r9, #4 ; 0x4 + 10c6c: ebf5cb29 bl 0xffd83918 + 10c70: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10c74: e1a08000 mov r8, r0 + 10c78: ebf5ccc0 bl 0xffd83f80 + 10c7c: 08001444 stmeqda r0, {r2, r6, sl, ip} + 10c80: e59d9434 ldr r9, [sp, #1076] + 10c84: e3c99003 bic r9, r9, #3 ; 0x3 + 10c88: e2890004 add r0, r9, #4 ; 0x4 + 10c8c: e58d0434 str r0, [sp, #1076] + 10c90: e2890000 add r0, r9, #0 ; 0x0 + 10c94: ebf5cb1f bl 0xffd83918 + 10c98: 08001448 stmeqda r0, {r3, r6, sl, ip} + 10c9c: e1a04000 mov r4, r0 + 10ca0: ebf5ccb6 bl 0xffd83f80 + 10ca4: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10ca8: e1a00004 mov r0, r4 + 10cac: e28cc00f add ip, ip, #15 ; 0xf + 10cb0: eaf5c906 b 0xffd830d0 + 10cb4: 080c2e4c stmeqda ip, {r2, r3, r6, r9, sl, fp, sp} + 10cb8: 00000000 andeq r0, r0, r0 + 10cbc: ebf5ccaf bl 0xffd83f80 + 10cc0: 080c2e4c stmeqda ip, {r2, r3, r6, r9, sl, fp, sp} + 10cc4: e1a01003 mov r1, r3 + 10cc8: e2935000 adds r5, r3, #0 ; 0x0 + 10ccc: ebf5ccab bl 0xffd83f80 + 10cd0: 080c2e4e stmeqda ip, {r1, r2, r3, r6, r9, sl, fp, sp} + 10cd4: e1a01004 mov r1, r4 + 10cd8: e2943000 adds r3, r4, #0 ; 0x0 + 10cdc: ebf5cca7 bl 0xffd83f80 + 10ce0: 080c2e50 stmeqda ip, {r4, r6, r9, sl, fp, sp} + 10ce4: e1a01004 mov r1, r4 + 10ce8: e2544001 subs r4, r4, #1 ; 0x1 + 10cec: ebf5cca3 bl 0xffd83f80 + 10cf0: 080c2e52 stmeqda ip, {r1, r4, r6, r9, sl, fp, sp} + 10cf4: e3530000 cmp r3, #0 ; 0x0 + 10cf8: ebf5cca0 bl 0xffd83f80 + 10cfc: 080c2e54 stmeqda ip, {r2, r4, r6, r9, sl, fp, sp} + 10d00: e28cc00f add ip, ip, #15 ; 0xf + 10d04: 1a000004 bne 0x10d1c + 10d08: e1a00fac mov r0, ip, lsr #31 + 10d0c: e08ff100 add pc, pc, r0, lsl #2 + 10d10: 080c2e64 stmeqda ip, {r2, r5, r6, r9, sl, fp, sp} + 10d14: ebf5c88e bl 0xffd82f54 + 10d18: ea000021 b 0x10da4 + 10d1c: ebf5cc97 bl 0xffd83f80 + 10d20: 080c2e56 stmeqda ip, {r1, r2, r4, r6, r9, sl, fp, sp} + 10d24: e3b06000 movs r6, #0 ; 0x0 + 10d28: e28cc003 add ip, ip, #3 ; 0x3 + 10d2c: ebf5cc93 bl 0xffd83f80 + 10d30: 080c2e58 stmeqda ip, {r3, r4, r6, r9, sl, fp, sp} + 10d34: e2850000 add r0, r5, #0 ; 0x0 + 10d38: e1a01006 mov r1, r6 + 10d3c: ebf5c9e3 bl 0xffd834d0 + 10d40: 080c2e5a stmeqda ip, {r1, r3, r4, r6, r9, sl, fp, sp} + 10d44: ebf5cc8d bl 0xffd83f80 + 10d48: 080c2e5a stmeqda ip, {r1, r3, r4, r6, r9, sl, fp, sp} + 10d4c: e1a01005 mov r1, r5 + 10d50: e2955001 adds r5, r5, #1 ; 0x1 + 10d54: ebf5cc89 bl 0xffd83f80 + 10d58: 080c2e5c stmeqda ip, {r2, r3, r4, r6, r9, sl, fp, sp} + 10d5c: e1a01004 mov r1, r4 + 10d60: e2943000 adds r3, r4, #0 ; 0x0 + 10d64: ebf5cc85 bl 0xffd83f80 + 10d68: 080c2e5e stmeqda ip, {r1, r2, r3, r4, r6, r9, sl, fp, sp} + 10d6c: e1a01004 mov r1, r4 + 10d70: e2544001 subs r4, r4, #1 ; 0x1 + 10d74: ebf5cc81 bl 0xffd83f80 + 10d78: 080c2e60 stmeqda ip, {r5, r6, r9, sl, fp, sp} + 10d7c: e3530000 cmp r3, #0 ; 0x0 + 10d80: ebf5cc7e bl 0xffd83f80 + 10d84: 080c2e62 stmeqda ip, {r1, r5, r6, r9, sl, fp, sp} + 10d88: e28cc013 add ip, ip, #19 ; 0x13 + 10d8c: 0a000004 beq 0x10da4 + 10d90: e1a00fac mov r0, ip, lsr #31 + 10d94: e08ff100 add pc, pc, r0, lsl #2 + 10d98: 080c2e58 stmeqda ip, {r3, r4, r6, r9, sl, fp, sp} + 10d9c: ebf5c86c bl 0xffd82f54 + 10da0: eaffffe1 b 0x10d2c + 10da4: ebf5cc75 bl 0xffd83f80 + 10da8: 080c2e64 stmeqda ip, {r2, r5, r6, r9, sl, fp, sp} + 10dac: e59d0438 ldr r0, [sp, #1080] + 10db0: e28cc003 add ip, ip, #3 ; 0x3 + 10db4: eaf5c8c5 b 0xffd830d0 + 10db8: 08001434 stmeqda r0, {r2, r4, r5, sl, ip} + 10dbc: 00000000 andeq r0, r0, r0 + 10dc0: ebf5cc6e bl 0xffd83f80 + 10dc4: 08001434 stmeqda r0, {r2, r4, r5, sl, ip} + 10dc8: e2870000 add r0, r7, #0 ; 0x0 + 10dcc: e1a01008 mov r1, r8 + 10dd0: ebf5c9dd bl 0xffd8354c + 10dd4: 08001436 stmeqda r0, {r1, r2, r4, r5, sl, ip} + 10dd8: ebf5cc68 bl 0xffd83f80 + 10ddc: 08001436 stmeqda r0, {r1, r2, r4, r5, sl, ip} + 10de0: e1a01007 mov r1, r7 + 10de4: e2973000 adds r3, r7, #0 ; 0x0 + 10de8: ebf5cc64 bl 0xffd83f80 + 10dec: 08001438 stmeqda r0, {r3, r4, r5, sl, ip} + 10df0: e28cc00a add ip, ip, #10 ; 0xa + 10df4: e1a00fac mov r0, ip, lsr #31 + 10df8: e08ff100 add pc, pc, r0, lsl #2 + 10dfc: 08001442 stmeqda r0, {r1, r6, sl, ip} + 10e00: ebf5c853 bl 0xffd82f54 + 10e04: ea000001 b 0x10e10 + 10e08: 08001442 stmeqda r0, {r1, r6, sl, ip} + 10e0c: 00000000 andeq r0, r0, r0 + 10e10: ebf5cc5a bl 0xffd83f80 + 10e14: 08001442 stmeqda r0, {r1, r6, sl, ip} + 10e18: e59d9434 ldr r9, [sp, #1076] + 10e1c: e3c99003 bic r9, r9, #3 ; 0x3 + 10e20: e2890008 add r0, r9, #8 ; 0x8 + 10e24: e58d0434 str r0, [sp, #1076] + 10e28: e2890000 add r0, r9, #0 ; 0x0 + 10e2c: ebf5cab9 bl 0xffd83918 + 10e30: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10e34: e1a07000 mov r7, r0 + 10e38: e2890004 add r0, r9, #4 ; 0x4 + 10e3c: ebf5cab5 bl 0xffd83918 + 10e40: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10e44: e1a08000 mov r8, r0 + 10e48: ebf5cc4c bl 0xffd83f80 + 10e4c: 08001444 stmeqda r0, {r2, r6, sl, ip} + 10e50: e59d9434 ldr r9, [sp, #1076] + 10e54: e3c99003 bic r9, r9, #3 ; 0x3 + 10e58: e2890004 add r0, r9, #4 ; 0x4 + 10e5c: e58d0434 str r0, [sp, #1076] + 10e60: e2890000 add r0, r9, #0 ; 0x0 + 10e64: ebf5caab bl 0xffd83918 + 10e68: 08001448 stmeqda r0, {r3, r6, sl, ip} + 10e6c: e1a04000 mov r4, r0 + 10e70: ebf5cc42 bl 0xffd83f80 + 10e74: 08001446 stmeqda r0, {r1, r2, r6, sl, ip} + 10e78: e1a00004 mov r0, r4 + 10e7c: e28cc00c add ip, ip, #12 ; 0xc + 10e80: eaf5c892 b 0xffd830d0 + 10e84: 0800148c stmeqda r0, {r2, r3, r7, sl, ip} + 10e88: 00000000 andeq r0, r0, r0 + 10e8c: ebf5cc3b bl 0xffd83f80 + 10e90: 0800148c stmeqda r0, {r2, r3, r7, sl, ip} + 10e94: e1a01003 mov r1, r3 + 10e98: e2935000 adds r5, r3, #0 ; 0x0 + 10e9c: ebf5cc37 bl 0xffd83f80 + 10ea0: 0800148e stmeqda r0, {r1, r2, r3, r7, sl, ip} + 10ea4: e3550000 cmp r5, #0 ; 0x0 + 10ea8: ebf5cc34 bl 0xffd83f80 + 10eac: 08001490 stmeqda r0, {r4, r7, sl, ip} + 10eb0: e28cc009 add ip, ip, #9 ; 0x9 + 10eb4: 1a000004 bne 0x10ecc + 10eb8: e1a00fac mov r0, ip, lsr #31 + 10ebc: e08ff100 add pc, pc, r0, lsl #2 + 10ec0: 080014b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, ip} + 10ec4: ebf5c822 bl 0xffd82f54 + 10ec8: ea00006b b 0x1107c + 10ecc: ebf5cc2b bl 0xffd83f80 + 10ed0: 08001492 stmeqda r0, {r1, r4, r7, sl, ip} + 10ed4: e3a00d53 mov r0, #5312 ; 0x14c0 + 10ed8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10edc: ebf5ca8d bl 0xffd83918 + 10ee0: 08001496 stmeqda r0, {r1, r2, r4, r7, sl, ip} + 10ee4: e1a03000 mov r3, r0 + 10ee8: ebf5cc24 bl 0xffd83f80 + 10eec: 08001494 stmeqda r0, {r2, r4, r7, sl, ip} + 10ef0: e1a01008 mov r1, r8 + 10ef4: e0188003 ands r8, r8, r3 + 10ef8: ebf5cc20 bl 0xffd83f80 + 10efc: 08001496 stmeqda r0, {r1, r2, r4, r7, sl, ip} + 10f00: e3a00f31 mov r0, #196 ; 0xc4 + 10f04: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10f08: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10f0c: ebf5ca81 bl 0xffd83918 + 10f10: 0800149a stmeqda r0, {r1, r3, r4, r7, sl, ip} + 10f14: e1a03000 mov r3, r0 + 10f18: ebf5cc18 bl 0xffd83f80 + 10f1c: 08001498 stmeqda r0, {r3, r4, r7, sl, ip} + 10f20: e2850022 add r0, r5, #34 ; 0x22 + 10f24: e1a01003 mov r1, r3 + 10f28: ebf5c987 bl 0xffd8354c + 10f2c: 0800149a stmeqda r0, {r1, r3, r4, r7, sl, ip} + 10f30: ebf5cc12 bl 0xffd83f80 + 10f34: 0800149a stmeqda r0, {r1, r3, r4, r7, sl, ip} + 10f38: e3570000 cmp r7, #0 ; 0x0 + 10f3c: ebf5cc0f bl 0xffd83f80 + 10f40: 0800149c stmeqda r0, {r2, r3, r4, r7, sl, ip} + 10f44: e28cc017 add ip, ip, #23 ; 0x17 + 10f48: 1a000004 bne 0x10f60 + 10f4c: e1a00fac mov r0, ip, lsr #31 + 10f50: e08ff100 add pc, pc, r0, lsl #2 + 10f54: 080014a6 stmeqda r0, {r1, r2, r5, r7, sl, ip} + 10f58: ebf5c7fd bl 0xffd82f54 + 10f5c: ea000018 b 0x10fc4 + 10f60: ebf5cc06 bl 0xffd83f80 + 10f64: 0800149e stmeqda r0, {r1, r2, r3, r4, r7, sl, ip} + 10f68: e2850028 add r0, r5, #40 ; 0x28 + 10f6c: e1a01007 mov r1, r7 + 10f70: ebf5c995 bl 0xffd835cc + 10f74: 080014a0 stmeqda r0, {r5, r7, sl, ip} + 10f78: ebf5cc00 bl 0xffd83f80 + 10f7c: 080014a0 stmeqda r0, {r5, r7, sl, ip} + 10f80: e2870030 add r0, r7, #48 ; 0x30 + 10f84: ebf5ca63 bl 0xffd83918 + 10f88: 080014a4 stmeqda r0, {r2, r5, r7, sl, ip} + 10f8c: e1a03000 mov r3, r0 + 10f90: ebf5cbfa bl 0xffd83f80 + 10f94: 080014a2 stmeqda r0, {r1, r5, r7, sl, ip} + 10f98: e285002c add r0, r5, #44 ; 0x2c + 10f9c: e1a01003 mov r1, r3 + 10fa0: ebf5c989 bl 0xffd835cc + 10fa4: 080014a4 stmeqda r0, {r2, r5, r7, sl, ip} + 10fa8: ebf5cbf4 bl 0xffd83f80 + 10fac: 080014a4 stmeqda r0, {r2, r5, r7, sl, ip} + 10fb0: e2870030 add r0, r7, #48 ; 0x30 + 10fb4: e1a01005 mov r1, r5 + 10fb8: ebf5c983 bl 0xffd835cc + 10fbc: 080014a6 stmeqda r0, {r1, r2, r5, r7, sl, ip} + 10fc0: e28cc011 add ip, ip, #17 ; 0x11 + 10fc4: ebf5cbed bl 0xffd83f80 + 10fc8: 080014a6 stmeqda r0, {r1, r2, r5, r7, sl, ip} + 10fcc: e3a00f32 mov r0, #200 ; 0xc8 + 10fd0: e3800b05 orr r0, r0, #5120 ; 0x1400 + 10fd4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 10fd8: ebf5ca4e bl 0xffd83918 + 10fdc: 080014aa stmeqda r0, {r1, r3, r5, r7, sl, ip} + 10fe0: e1a03000 mov r3, r0 + 10fe4: ebf5cbe5 bl 0xffd83f80 + 10fe8: 080014a8 stmeqda r0, {r3, r5, r7, sl, ip} + 10fec: e2850024 add r0, r5, #36 ; 0x24 + 10ff0: e1a01003 mov r1, r3 + 10ff4: ebf5c974 bl 0xffd835cc + 10ff8: 080014aa stmeqda r0, {r1, r3, r5, r7, sl, ip} + 10ffc: ebf5cbdf bl 0xffd83f80 + 11000: 080014aa stmeqda r0, {r1, r3, r5, r7, sl, ip} + 11004: e1b04088 movs r4, r8, lsl #1 + 11008: ebf5cbdc bl 0xffd83f80 + 1100c: 080014ac stmeqda r0, {r2, r3, r5, r7, sl, ip} + 11010: e3a00f33 mov r0, #204 ; 0xcc + 11014: e3800b05 orr r0, r0, #5120 ; 0x1400 + 11018: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1101c: ebf5ca3d bl 0xffd83918 + 11020: 080014b0 stmeqda r0, {r4, r5, r7, sl, ip} + 11024: e1a03000 mov r3, r0 + 11028: ebf5cbd4 bl 0xffd83f80 + 1102c: 080014ae stmeqda r0, {r1, r2, r3, r5, r7, sl, ip} + 11030: e1a01004 mov r1, r4 + 11034: e0944003 adds r4, r4, r3 + 11038: ebf5cbd0 bl 0xffd83f80 + 1103c: 080014b0 stmeqda r0, {r4, r5, r7, sl, ip} + 11040: e2840000 add r0, r4, #0 ; 0x0 + 11044: ebf5ca07 bl 0xffd83868 + 11048: 080014b4 stmeqda r0, {r2, r4, r5, r7, sl, ip} + 1104c: e1a03000 mov r3, r0 + 11050: ebf5cbca bl 0xffd83f80 + 11054: 080014b2 stmeqda r0, {r1, r4, r5, r7, sl, ip} + 11058: e1a01003 mov r1, r3 + 1105c: e2933001 adds r3, r3, #1 ; 0x1 + 11060: ebf5cbc6 bl 0xffd83f80 + 11064: 080014b4 stmeqda r0, {r2, r4, r5, r7, sl, ip} + 11068: e2840000 add r0, r4, #0 ; 0x0 + 1106c: e1a01003 mov r1, r3 + 11070: ebf5c935 bl 0xffd8354c + 11074: 080014b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, ip} + 11078: e28cc020 add ip, ip, #32 ; 0x20 + 1107c: ebf5cbbf bl 0xffd83f80 + 11080: 080014b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, ip} + 11084: e1a01005 mov r1, r5 + 11088: e2953000 adds r3, r5, #0 ; 0x0 + 1108c: ebf5cbbb bl 0xffd83f80 + 11090: 080014b8 stmeqda r0, {r3, r4, r5, r7, sl, ip} + 11094: e59d9434 ldr r9, [sp, #1076] + 11098: e3c99003 bic r9, r9, #3 ; 0x3 + 1109c: e2890008 add r0, r9, #8 ; 0x8 + 110a0: e58d0434 str r0, [sp, #1076] + 110a4: e2890000 add r0, r9, #0 ; 0x0 + 110a8: ebf5ca1a bl 0xffd83918 + 110ac: 080014bc stmeqda r0, {r2, r3, r4, r5, r7, sl, ip} + 110b0: e1a07000 mov r7, r0 + 110b4: e2890004 add r0, r9, #4 ; 0x4 + 110b8: ebf5ca16 bl 0xffd83918 + 110bc: 080014bc stmeqda r0, {r2, r3, r4, r5, r7, sl, ip} + 110c0: e1a08000 mov r8, r0 + 110c4: ebf5cbad bl 0xffd83f80 + 110c8: 080014ba stmeqda r0, {r1, r3, r4, r5, r7, sl, ip} + 110cc: e59d9434 ldr r9, [sp, #1076] + 110d0: e3c99003 bic r9, r9, #3 ; 0x3 + 110d4: e2890004 add r0, r9, #4 ; 0x4 + 110d8: e58d0434 str r0, [sp, #1076] + 110dc: e2890000 add r0, r9, #0 ; 0x0 + 110e0: ebf5ca0c bl 0xffd83918 + 110e4: 080014be stmeqda r0, {r1, r2, r3, r4, r5, r7, sl, ip} + 110e8: e1a04000 mov r4, r0 + 110ec: ebf5cba3 bl 0xffd83f80 + 110f0: 080014bc stmeqda r0, {r2, r3, r4, r5, r7, sl, ip} + 110f4: e1a00004 mov r0, r4 + 110f8: e28cc00f add ip, ip, #15 ; 0xf + 110fc: eaf5c7f3 b 0xffd830d0 + 11100: 08002b98 stmeqda r0, {r3, r4, r7, r8, r9, fp, sp} + 11104: 00000000 andeq r0, r0, r0 + 11108: ebf5cb9c bl 0xffd83f80 + 1110c: 08002b98 stmeqda r0, {r3, r4, r7, r8, r9, fp, sp} + 11110: e3a00ff2 mov r0, #968 ; 0x3c8 + 11114: e3800b0a orr r0, r0, #10240 ; 0x2800 + 11118: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1111c: ebf5c9fd bl 0xffd83918 + 11120: 08002b9c stmeqda r0, {r2, r3, r4, r7, r8, r9, fp, sp} + 11124: e1a08000 mov r8, r0 + 11128: ebf5cb94 bl 0xffd83f80 + 1112c: 08002b9a stmeqda r0, {r1, r3, r4, r7, r8, r9, fp, sp} + 11130: e2880000 add r0, r8, #0 ; 0x0 + 11134: e1a01003 mov r1, r3 + 11138: ebf5c923 bl 0xffd835cc + 1113c: 08002b9c stmeqda r0, {r2, r3, r4, r7, r8, r9, fp, sp} + 11140: ebf5cb8e bl 0xffd83f80 + 11144: 08002b9c stmeqda r0, {r2, r3, r4, r7, r8, r9, fp, sp} + 11148: e2830038 add r0, r3, #56 ; 0x38 + 1114c: e59d1418 ldr r1, [sp, #1048] + 11150: ebf5c8fd bl 0xffd8354c + 11154: 08002b9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, fp, sp} + 11158: ebf5cb88 bl 0xffd83f80 + 1115c: 08002b9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, fp, sp} + 11160: e2880000 add r0, r8, #0 ; 0x0 + 11164: ebf5c9eb bl 0xffd83918 + 11168: 08002ba2 stmeqda r0, {r1, r5, r7, r8, r9, fp, sp} + 1116c: e1a03000 mov r3, r0 + 11170: ebf5cb82 bl 0xffd83f80 + 11174: 08002ba0 stmeqda r0, {r5, r7, r8, r9, fp, sp} + 11178: e3a00ff3 mov r0, #972 ; 0x3cc + 1117c: e3800b0a orr r0, r0, #10240 ; 0x2800 + 11180: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11184: ebf5c9e3 bl 0xffd83918 + 11188: 08002ba4 stmeqda r0, {r2, r5, r7, r8, r9, fp, sp} + 1118c: e1a04000 mov r4, r0 + 11190: ebf5cb7a bl 0xffd83f80 + 11194: 08002ba2 stmeqda r0, {r1, r5, r7, r8, r9, fp, sp} + 11198: e1b07187 movs r7, r7, lsl #3 + 1119c: ebf5cb77 bl 0xffd83f80 + 111a0: 08002ba4 stmeqda r0, {r2, r5, r7, r8, r9, fp, sp} + 111a4: e1a01007 mov r1, r7 + 111a8: e0977004 adds r7, r7, r4 + 111ac: ebf5cb73 bl 0xffd83f80 + 111b0: 08002ba6 stmeqda r0, {r1, r2, r5, r7, r8, r9, fp, sp} + 111b4: e2870004 add r0, r7, #4 ; 0x4 + 111b8: ebf5c9aa bl 0xffd83868 + 111bc: 08002baa stmeqda r0, {r1, r3, r5, r7, r8, r9, fp, sp} + 111c0: e1a04000 mov r4, r0 + 111c4: ebf5cb6d bl 0xffd83f80 + 111c8: 08002ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, sp} + 111cc: ebf5cb6b bl 0xffd83f80 + 111d0: 08002baa stmeqda r0, {r1, r3, r5, r7, r8, r9, fp, sp} + 111d4: e3a000ad mov r0, #173 ; 0xad + 111d8: e3800c2b orr r0, r0, #11008 ; 0x2b00 + 111dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 111e0: e58d0438 str r0, [sp, #1080] + 111e4: e28cc028 add ip, ip, #40 ; 0x28 + 111e8: e1a00fac mov r0, ip, lsr #31 + 111ec: e08ff100 add pc, pc, r0, lsl #2 + 111f0: 08001480 stmeqda r0, {r7, sl, ip} + 111f4: ebf5c756 bl 0xffd82f54 + 111f8: eafffe0e b 0x10a38 + 111fc: 08002bac stmeqda r0, {r2, r3, r5, r7, r8, r9, fp, sp} + 11200: 00000000 andeq r0, r0, r0 + 11204: ebf5cb5d bl 0xffd83f80 + 11208: 08002bac stmeqda r0, {r2, r3, r5, r7, r8, r9, fp, sp} + 1120c: e2880000 add r0, r8, #0 ; 0x0 + 11210: ebf5c9c0 bl 0xffd83918 + 11214: 08002bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, sp} + 11218: e1a04000 mov r4, r0 + 1121c: ebf5cb57 bl 0xffd83f80 + 11220: 08002bae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, fp, sp} + 11224: e284004c add r0, r4, #76 ; 0x4c + 11228: e1a01003 mov r1, r3 + 1122c: ebf5c8e6 bl 0xffd835cc + 11230: 08002bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, sp} + 11234: ebf5cb51 bl 0xffd83f80 + 11238: 08002bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, sp} + 1123c: e2840002 add r0, r4, #2 ; 0x2 + 11240: ebf5c988 bl 0xffd83868 + 11244: 08002bb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, fp, sp} + 11248: e1a05000 mov r5, r0 + 1124c: ebf5cb4b bl 0xffd83f80 + 11250: 08002bb2 stmeqda r0, {r1, r4, r5, r7, r8, r9, fp, sp} + 11254: e3b06080 movs r6, #128 ; 0x80 + 11258: ebf5cb48 bl 0xffd83f80 + 1125c: 08002bb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, fp, sp} + 11260: e1b06386 movs r6, r6, lsl #7 + 11264: ebf5cb45 bl 0xffd83f80 + 11268: 08002bb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, fp, sp} + 1126c: e1a01006 mov r1, r6 + 11270: e2963000 adds r3, r6, #0 ; 0x0 + 11274: ebf5cb41 bl 0xffd83f80 + 11278: 08002bb8 stmeqda r0, {r3, r4, r5, r7, r8, r9, fp, sp} + 1127c: e1a01003 mov r1, r3 + 11280: e1933005 orrs r3, r3, r5 + 11284: ebf5cb3d bl 0xffd83f80 + 11288: 08002bba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, fp, sp} + 1128c: e2840002 add r0, r4, #2 ; 0x2 + 11290: e1a01003 mov r1, r3 + 11294: ebf5c8ac bl 0xffd8354c + 11298: 08002bbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, fp, sp} + 1129c: ebf5cb37 bl 0xffd83f80 + 112a0: 08002bbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, fp, sp} + 112a4: e3a00ebd mov r0, #3024 ; 0xbd0 + 112a8: e3800a02 orr r0, r0, #8192 ; 0x2000 + 112ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 112b0: ebf5c998 bl 0xffd83918 + 112b4: 08002bc0 stmeqda r0, {r6, r7, r8, r9, fp, sp} + 112b8: e1a03000 mov r3, r0 + 112bc: ebf5cb2f bl 0xffd83f80 + 112c0: 08002bbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, fp, sp} + 112c4: e2840014 add r0, r4, #20 ; 0x14 + 112c8: e1a01003 mov r1, r3 + 112cc: ebf5c8be bl 0xffd835cc + 112d0: 08002bc0 stmeqda r0, {r6, r7, r8, r9, fp, sp} + 112d4: ebf5cb29 bl 0xffd83f80 + 112d8: 08002bc0 stmeqda r0, {r6, r7, r8, r9, fp, sp} + 112dc: e59d9434 ldr r9, [sp, #1076] + 112e0: e3c99003 bic r9, r9, #3 ; 0x3 + 112e4: e289000c add r0, r9, #12 ; 0xc + 112e8: e58d0434 str r0, [sp, #1076] + 112ec: e2890000 add r0, r9, #0 ; 0x0 + 112f0: ebf5c988 bl 0xffd83918 + 112f4: 08002bc4 stmeqda r0, {r2, r6, r7, r8, r9, fp, sp} + 112f8: e1a07000 mov r7, r0 + 112fc: e2890004 add r0, r9, #4 ; 0x4 + 11300: ebf5c984 bl 0xffd83918 + 11304: 08002bc4 stmeqda r0, {r2, r6, r7, r8, r9, fp, sp} + 11308: e1a08000 mov r8, r0 + 1130c: e2890008 add r0, r9, #8 ; 0x8 + 11310: ebf5c980 bl 0xffd83918 + 11314: 08002bc4 stmeqda r0, {r2, r6, r7, r8, r9, fp, sp} + 11318: e58d0418 str r0, [sp, #1048] + 1131c: ebf5cb17 bl 0xffd83f80 + 11320: 08002bc2 stmeqda r0, {r1, r6, r7, r8, r9, fp, sp} + 11324: e59d9434 ldr r9, [sp, #1076] + 11328: e3c99003 bic r9, r9, #3 ; 0x3 + 1132c: e2890004 add r0, r9, #4 ; 0x4 + 11330: e58d0434 str r0, [sp, #1076] + 11334: e2890000 add r0, r9, #0 ; 0x0 + 11338: ebf5c976 bl 0xffd83918 + 1133c: 08002bc6 stmeqda r0, {r1, r2, r6, r7, r8, r9, fp, sp} + 11340: e1a03000 mov r3, r0 + 11344: ebf5cb0d bl 0xffd83f80 + 11348: 08002bc4 stmeqda r0, {r2, r6, r7, r8, r9, fp, sp} + 1134c: e1a00003 mov r0, r3 + 11350: e28cc034 add ip, ip, #52 ; 0x34 + 11354: eaf5c75d b 0xffd830d0 + 11358: 0800036a stmeqda r0, {r1, r3, r5, r6, r8, r9} + 1135c: 00000000 andeq r0, r0, r0 + 11360: ebf5cb06 bl 0xffd83f80 + 11364: 0800036a stmeqda r0, {r1, r3, r5, r6, r8, r9} + 11368: ebf5cb04 bl 0xffd83f80 + 1136c: 0800036c stmeqda r0, {r2, r3, r5, r6, r8, r9} + 11370: e3a0006f mov r0, #111 ; 0x6f + 11374: e3800c03 orr r0, r0, #768 ; 0x300 + 11378: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1137c: e58d0438 str r0, [sp, #1080] + 11380: e28cc006 add ip, ip, #6 ; 0x6 + 11384: e1a00fac mov r0, ip, lsr #31 + 11388: e08ff100 add pc, pc, r0, lsl #2 + 1138c: 080007d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl} + 11390: ebf5c6ef bl 0xffd82f54 + 11394: ea000001 b 0x113a0 + 11398: 080007d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl} + 1139c: 00000000 andeq r0, r0, r0 + 113a0: ebf5caf6 bl 0xffd83f80 + 113a4: 080007d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl} + 113a8: e59d9434 ldr r9, [sp, #1076] + 113ac: e3c99003 bic r9, r9, #3 ; 0x3 + 113b0: e2499014 sub r9, r9, #20 ; 0x14 + 113b4: e58d9434 str r9, [sp, #1076] + 113b8: e2890000 add r0, r9, #0 ; 0x0 + 113bc: e1a01007 mov r1, r7 + 113c0: ebf5c8a1 bl 0xffd8364c + 113c4: e2890004 add r0, r9, #4 ; 0x4 + 113c8: e1a01008 mov r1, r8 + 113cc: ebf5c89e bl 0xffd8364c + 113d0: e2890008 add r0, r9, #8 ; 0x8 + 113d4: e59d1418 ldr r1, [sp, #1048] + 113d8: ebf5c89b bl 0xffd8364c + 113dc: e289000c add r0, r9, #12 ; 0xc + 113e0: e59d141c ldr r1, [sp, #1052] + 113e4: ebf5c898 bl 0xffd8364c + 113e8: e2890010 add r0, r9, #16 ; 0x10 + 113ec: e59d1438 ldr r1, [sp, #1080] + 113f0: ebf5c895 bl 0xffd8364c + 113f4: ebf5cae1 bl 0xffd83f80 + 113f8: 080007da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, sl} + 113fc: e3a00f0f mov r0, #60 ; 0x3c + 11400: e3800b02 orr r0, r0, #2048 ; 0x800 + 11404: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11408: ebf5c942 bl 0xffd83918 + 1140c: 080007de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl} + 11410: e1a08000 mov r8, r0 + 11414: ebf5cad9 bl 0xffd83f80 + 11418: 080007dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, sl} + 1141c: e3a00d21 mov r0, #2112 ; 0x840 + 11420: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11424: ebf5c93b bl 0xffd83918 + 11428: 080007e0 stmeqda r0, {r5, r6, r7, r8, r9, sl} + 1142c: e1a03000 mov r3, r0 + 11430: ebf5cad2 bl 0xffd83f80 + 11434: 080007de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl} + 11438: e2830000 add r0, r3, #0 ; 0x0 + 1143c: ebf5c909 bl 0xffd83868 + 11440: 080007e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl} + 11444: e1a03000 mov r3, r0 + 11448: ebf5cacc bl 0xffd83f80 + 1144c: 080007e0 stmeqda r0, {r5, r6, r7, r8, r9, sl} + 11450: e1f03003 mvns r3, r3 + 11454: ebf5cac9 bl 0xffd83f80 + 11458: 080007e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl} + 1145c: e3a00f11 mov r0, #68 ; 0x44 + 11460: e3800b02 orr r0, r0, #2048 ; 0x800 + 11464: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11468: ebf5c92a bl 0xffd83918 + 1146c: 080007e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl} + 11470: e1a05000 mov r5, r0 + 11474: ebf5cac1 bl 0xffd83f80 + 11478: 080007e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl} + 1147c: e1a01008 mov r1, r8 + 11480: e0984005 adds r4, r8, r5 + 11484: ebf5cabd bl 0xffd83f80 + 11488: 080007e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl} + 1148c: e3b06000 movs r6, #0 ; 0x0 + 11490: ebf5caba bl 0xffd83f80 + 11494: 080007e8 stmeqda r0, {r3, r5, r6, r7, r8, r9, sl} + 11498: e1a00006 mov r0, r6 + 1149c: e58d0430 str r0, [sp, #1072] + 114a0: ebf5cab6 bl 0xffd83f80 + 114a4: 080007ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl} + 114a8: e2840000 add r0, r4, #0 ; 0x0 + 114ac: e1a01003 mov r1, r3 + 114b0: ebf5c825 bl 0xffd8354c + 114b4: 080007ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl} + 114b8: ebf5cab0 bl 0xffd83f80 + 114bc: 080007ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl} + 114c0: e2840000 add r0, r4, #0 ; 0x0 + 114c4: ebf5c8e7 bl 0xffd83868 + 114c8: 080007f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, sl} + 114cc: e1a07000 mov r7, r0 + 114d0: ebf5caaa bl 0xffd83f80 + 114d4: 080007ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, sl} + 114d8: e3a00f12 mov r0, #72 ; 0x48 + 114dc: e3800b02 orr r0, r0, #2048 ; 0x800 + 114e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 114e4: ebf5c90b bl 0xffd83918 + 114e8: 080007f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, sl} + 114ec: e1a03000 mov r3, r0 + 114f0: ebf5caa2 bl 0xffd83f80 + 114f4: 080007f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, sl} + 114f8: e1a01008 mov r1, r8 + 114fc: e0985003 adds r5, r8, r3 + 11500: ebf5ca9e bl 0xffd83f80 + 11504: 080007f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, sl} + 11508: e2850000 add r0, r5, #0 ; 0x0 + 1150c: ebf5c8d5 bl 0xffd83868 + 11510: 080007f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, sl} + 11514: e1a03000 mov r3, r0 + 11518: ebf5ca98 bl 0xffd83f80 + 1151c: 080007f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, sl} + 11520: e1a01007 mov r1, r7 + 11524: e2974000 adds r4, r7, #0 ; 0x0 + 11528: ebf5ca94 bl 0xffd83f80 + 1152c: 080007f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, sl} + 11530: e1a01004 mov r1, r4 + 11534: e1d44003 bics r4, r4, r3 + 11538: ebf5ca90 bl 0xffd83f80 + 1153c: 080007f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, sl} + 11540: e3a00f13 mov r0, #76 ; 0x4c + 11544: e3800b02 orr r0, r0, #2048 ; 0x800 + 11548: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1154c: ebf5c8f1 bl 0xffd83918 + 11550: 080007fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, sl} + 11554: e1a06000 mov r6, r0 + 11558: ebf5ca88 bl 0xffd83f80 + 1155c: 080007fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, sl} + 11560: e1a01008 mov r1, r8 + 11564: e0983006 adds r3, r8, r6 + 11568: ebf5ca84 bl 0xffd83f80 + 1156c: 080007fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, sl} + 11570: e2830000 add r0, r3, #0 ; 0x0 + 11574: e1a01004 mov r1, r4 + 11578: ebf5c7f3 bl 0xffd8354c + 1157c: 080007fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl} + 11580: ebf5ca7e bl 0xffd83f80 + 11584: 080007fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl} + 11588: e2850000 add r0, r5, #0 ; 0x0 + 1158c: e1a01007 mov r1, r7 + 11590: ebf5c7ed bl 0xffd8354c + 11594: 08000800 stmeqda r0, {fp} + 11598: ebf5ca78 bl 0xffd83f80 + 1159c: 08000800 stmeqda r0, {fp} + 115a0: e3a00e85 mov r0, #2128 ; 0x850 + 115a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 115a8: ebf5c8da bl 0xffd83918 + 115ac: 08000804 stmeqda r0, {r2, fp} + 115b0: e1a03000 mov r3, r0 + 115b4: ebf5ca71 bl 0xffd83f80 + 115b8: 08000802 stmeqda r0, {r1, fp} + 115bc: e1a01008 mov r1, r8 + 115c0: e0980003 adds r0, r8, r3 + 115c4: e58d041c str r0, [sp, #1052] + 115c8: ebf5ca6c bl 0xffd83f80 + 115cc: 08000804 stmeqda r0, {r2, fp} + 115d0: e59d041c ldr r0, [sp, #1052] + 115d4: e2800000 add r0, r0, #0 ; 0x0 + 115d8: e1a01004 mov r1, r4 + 115dc: ebf5c7da bl 0xffd8354c + 115e0: 08000806 stmeqda r0, {r1, r2, fp} + 115e4: ebf5ca65 bl 0xffd83f80 + 115e8: 08000806 stmeqda r0, {r1, r2, fp} + 115ec: e3a00f15 mov r0, #84 ; 0x54 + 115f0: e3800b02 orr r0, r0, #2048 ; 0x800 + 115f4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 115f8: ebf5c8c6 bl 0xffd83918 + 115fc: 0800080a stmeqda r0, {r1, r3, fp} + 11600: e1a03000 mov r3, r0 + 11604: ebf5ca5d bl 0xffd83f80 + 11608: 08000808 stmeqda r0, {r3, fp} + 1160c: e1a01003 mov r1, r3 + 11610: e2936000 adds r6, r3, #0 ; 0x0 + 11614: ebf5ca59 bl 0xffd83f80 + 11618: 0800080a stmeqda r0, {r1, r3, fp} + 1161c: e1a01006 mov r1, r6 + 11620: e0166004 ands r6, r6, r4 + 11624: ebf5ca55 bl 0xffd83f80 + 11628: 0800080c stmeqda r0, {r2, r3, fp} + 1162c: e3560000 cmp r6, #0 ; 0x0 + 11630: ebf5ca52 bl 0xffd83f80 + 11634: 0800080e stmeqda r0, {r1, r2, r3, fp} + 11638: e28cc070 add ip, ip, #112 ; 0x70 + 1163c: 0a000004 beq 0x11654 + 11640: e1a00fac mov r0, ip, lsr #31 + 11644: e08ff100 add pc, pc, r0, lsl #2 + 11648: 08000870 stmeqda r0, {r4, r5, r6, fp} + 1164c: ebf5c640 bl 0xffd82f54 + 11650: ea000076 b 0x11830 + 11654: ebf5ca49 bl 0xffd83f80 + 11658: 08000810 stmeqda r0, {r4, fp} + 1165c: e3a00f16 mov r0, #88 ; 0x58 + 11660: e3800b02 orr r0, r0, #2048 ; 0x800 + 11664: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11668: ebf5c8aa bl 0xffd83918 + 1166c: 08000814 stmeqda r0, {r2, r4, fp} + 11670: e1a04000 mov r4, r0 + 11674: ebf5ca41 bl 0xffd83f80 + 11678: 08000812 stmeqda r0, {r1, r4, fp} + 1167c: e1a01008 mov r1, r8 + 11680: e0980004 adds r0, r8, r4 + 11684: e58d0418 str r0, [sp, #1048] + 11688: ebf5ca3c bl 0xffd83f80 + 1168c: 08000814 stmeqda r0, {r2, r4, fp} + 11690: e1a01003 mov r1, r3 + 11694: e2934000 adds r4, r3, #0 ; 0x0 + 11698: ebf5ca38 bl 0xffd83f80 + 1169c: 08000816 stmeqda r0, {r1, r2, r4, fp} + 116a0: e1a01004 mov r1, r4 + 116a4: e0144007 ands r4, r4, r7 + 116a8: ebf5ca34 bl 0xffd83f80 + 116ac: 08000818 stmeqda r0, {r3, r4, fp} + 116b0: e59d0418 ldr r0, [sp, #1048] + 116b4: e2800000 add r0, r0, #0 ; 0x0 + 116b8: ebf5c86a bl 0xffd83868 + 116bc: 0800081c stmeqda r0, {r2, r3, r4, fp} + 116c0: e1a03000 mov r3, r0 + 116c4: ebf5ca2d bl 0xffd83f80 + 116c8: 0800081a stmeqda r0, {r1, r3, r4, fp} + 116cc: e1530004 cmp r3, r4 + 116d0: ebf5ca2a bl 0xffd83f80 + 116d4: 0800081c stmeqda r0, {r2, r3, r4, fp} + 116d8: e28cc019 add ip, ip, #25 ; 0x19 + 116dc: 0a000004 beq 0x116f4 + 116e0: e1a00fac mov r0, ip, lsr #31 + 116e4: e08ff100 add pc, pc, r0, lsl #2 + 116e8: 08000860 stmeqda r0, {r5, r6, fp} + 116ec: ebf5c618 bl 0xffd82f54 + 116f0: ea0000a1 b 0x1197c + 116f4: ebf5ca21 bl 0xffd83f80 + 116f8: 0800081e stmeqda r0, {r1, r2, r3, r4, fp} + 116fc: e3a00f17 mov r0, #92 ; 0x5c + 11700: e3800b02 orr r0, r0, #2048 ; 0x800 + 11704: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11708: ebf5c882 bl 0xffd83918 + 1170c: 08000822 stmeqda r0, {r1, r5, fp} + 11710: e1a06000 mov r6, r0 + 11714: ebf5ca19 bl 0xffd83f80 + 11718: 08000820 stmeqda r0, {r5, fp} + 1171c: e1a01008 mov r1, r8 + 11720: e0985006 adds r5, r8, r6 + 11724: ebf5ca15 bl 0xffd83f80 + 11728: 08000822 stmeqda r0, {r1, r5, fp} + 1172c: e2850000 add r0, r5, #0 ; 0x0 + 11730: ebf5c821 bl 0xffd837bc + 11734: 08000826 stmeqda r0, {r1, r2, r5, fp} + 11738: e1a03000 mov r3, r0 + 1173c: ebf5ca0f bl 0xffd83f80 + 11740: 08000824 stmeqda r0, {r2, r5, fp} + 11744: e1a01003 mov r1, r3 + 11748: e2933001 adds r3, r3, #1 ; 0x1 + 1174c: ebf5ca0b bl 0xffd83f80 + 11750: 08000826 stmeqda r0, {r1, r2, r5, fp} + 11754: e2850000 add r0, r5, #0 ; 0x0 + 11758: e1a01003 mov r1, r3 + 1175c: ebf5c75b bl 0xffd834d0 + 11760: 08000828 stmeqda r0, {r3, r5, fp} + 11764: ebf5ca05 bl 0xffd83f80 + 11768: 08000828 stmeqda r0, {r3, r5, fp} + 1176c: e1b03c03 movs r3, r3, lsl #24 + 11770: ebf5ca02 bl 0xffd83f80 + 11774: 0800082a stmeqda r0, {r1, r3, r5, fp} + 11778: e1b03c23 movs r3, r3, lsr #24 + 1177c: ebf5c9ff bl 0xffd83f80 + 11780: 0800082c stmeqda r0, {r2, r3, r5, fp} + 11784: e353001e cmp r3, #30 ; 0x1e + 11788: ebf5c9fc bl 0xffd83f80 + 1178c: 0800082e stmeqda r0, {r1, r2, r3, r5, fp} + 11790: e28cc020 add ip, ip, #32 ; 0x20 + 11794: 0a000004 beq 0x117ac + 11798: e1a00fac mov r0, ip, lsr #31 + 1179c: e08ff100 add pc, pc, r0, lsl #2 + 117a0: 08000880 stmeqda r0, {r7, fp} + 117a4: ebf5c5ea bl 0xffd82f54 + 117a8: ea00009a b 0x11a18 + 117ac: ebf5c9f3 bl 0xffd83f80 + 117b0: 08000830 stmeqda r0, {r4, r5, fp} + 117b4: e59d041c ldr r0, [sp, #1052] + 117b8: e2800000 add r0, r0, #0 ; 0x0 + 117bc: e1a01004 mov r1, r4 + 117c0: ebf5c761 bl 0xffd8354c + 117c4: 08000832 stmeqda r0, {r1, r4, r5, fp} + 117c8: ebf5c9ec bl 0xffd83f80 + 117cc: 08000832 stmeqda r0, {r1, r4, r5, fp} + 117d0: e59d0418 ldr r0, [sp, #1048] + 117d4: e2800000 add r0, r0, #0 ; 0x0 + 117d8: e1a01004 mov r1, r4 + 117dc: ebf5c75a bl 0xffd8354c + 117e0: 08000834 stmeqda r0, {r2, r4, r5, fp} + 117e4: ebf5c9e5 bl 0xffd83f80 + 117e8: 08000834 stmeqda r0, {r2, r4, r5, fp} + 117ec: e3b0301b movs r3, #27 ; 0x1b + 117f0: ebf5c9e2 bl 0xffd83f80 + 117f4: 08000836 stmeqda r0, {r1, r2, r4, r5, fp} + 117f8: e2850000 add r0, r5, #0 ; 0x0 + 117fc: e1a01003 mov r1, r3 + 11800: ebf5c732 bl 0xffd834d0 + 11804: 08000838 stmeqda r0, {r3, r4, r5, fp} + 11808: ebf5c9dc bl 0xffd83f80 + 1180c: 08000838 stmeqda r0, {r3, r4, r5, fp} + 11810: e28cc012 add ip, ip, #18 ; 0x12 + 11814: e1a00fac mov r0, ip, lsr #31 + 11818: e08ff100 add pc, pc, r0, lsl #2 + 1181c: 08000880 stmeqda r0, {r7, fp} + 11820: ebf5c5cb bl 0xffd82f54 + 11824: ea00007b b 0x11a18 + 11828: 08000870 stmeqda r0, {r4, r5, r6, fp} + 1182c: 00000000 andeq r0, r0, r0 + 11830: ebf5c9d2 bl 0xffd83f80 + 11834: 08000870 stmeqda r0, {r4, r5, r6, fp} + 11838: e1a01007 mov r1, r7 + 1183c: e0177003 ands r7, r7, r3 + 11840: ebf5c9ce bl 0xffd83f80 + 11844: 08000872 stmeqda r0, {r1, r4, r5, r6, fp} + 11848: e3a00f22 mov r0, #136 ; 0x88 + 1184c: e3800b02 orr r0, r0, #2048 ; 0x800 + 11850: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11854: ebf5c82f bl 0xffd83918 + 11858: 08000876 stmeqda r0, {r1, r2, r4, r5, r6, fp} + 1185c: e1a06000 mov r6, r0 + 11860: ebf5c9c6 bl 0xffd83f80 + 11864: 08000874 stmeqda r0, {r2, r4, r5, r6, fp} + 11868: e1a01008 mov r1, r8 + 1186c: e0983006 adds r3, r8, r6 + 11870: ebf5c9c2 bl 0xffd83f80 + 11874: 08000876 stmeqda r0, {r1, r2, r4, r5, r6, fp} + 11878: e2830000 add r0, r3, #0 ; 0x0 + 1187c: e1a01007 mov r1, r7 + 11880: ebf5c731 bl 0xffd8354c + 11884: 08000878 stmeqda r0, {r3, r4, r5, r6, fp} + 11888: ebf5c9bc bl 0xffd83f80 + 1188c: 08000878 stmeqda r0, {r3, r4, r5, r6, fp} + 11890: e3a00f23 mov r0, #140 ; 0x8c + 11894: e3800b02 orr r0, r0, #2048 ; 0x800 + 11898: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1189c: ebf5c81d bl 0xffd83918 + 118a0: 0800087c stmeqda r0, {r2, r3, r4, r5, r6, fp} + 118a4: e1a04000 mov r4, r0 + 118a8: ebf5c9b4 bl 0xffd83f80 + 118ac: 0800087a stmeqda r0, {r1, r3, r4, r5, r6, fp} + 118b0: e1a01008 mov r1, r8 + 118b4: e0983004 adds r3, r8, r4 + 118b8: ebf5c9b0 bl 0xffd83f80 + 118bc: 0800087c stmeqda r0, {r2, r3, r4, r5, r6, fp} + 118c0: e59d1430 ldr r1, [sp, #1072] + 118c4: e1a05001 mov r5, r1 + 118c8: ebf5c9ac bl 0xffd83f80 + 118cc: 0800087e stmeqda r0, {r1, r2, r3, r4, r5, r6, fp} + 118d0: e2830000 add r0, r3, #0 ; 0x0 + 118d4: e1a01005 mov r1, r5 + 118d8: ebf5c6fc bl 0xffd834d0 + 118dc: 08000880 stmeqda r0, {r7, fp} + 118e0: ebf5c9a6 bl 0xffd83f80 + 118e4: 08000880 stmeqda r0, {r7, fp} + 118e8: e59d9434 ldr r9, [sp, #1076] + 118ec: e3c99003 bic r9, r9, #3 ; 0x3 + 118f0: e2890010 add r0, r9, #16 ; 0x10 + 118f4: e58d0434 str r0, [sp, #1076] + 118f8: e2890000 add r0, r9, #0 ; 0x0 + 118fc: ebf5c805 bl 0xffd83918 + 11900: 08000884 stmeqda r0, {r2, r7, fp} + 11904: e1a07000 mov r7, r0 + 11908: e2890004 add r0, r9, #4 ; 0x4 + 1190c: ebf5c801 bl 0xffd83918 + 11910: 08000884 stmeqda r0, {r2, r7, fp} + 11914: e1a08000 mov r8, r0 + 11918: e2890008 add r0, r9, #8 ; 0x8 + 1191c: ebf5c7fd bl 0xffd83918 + 11920: 08000884 stmeqda r0, {r2, r7, fp} + 11924: e58d0418 str r0, [sp, #1048] + 11928: e289000c add r0, r9, #12 ; 0xc + 1192c: ebf5c7f9 bl 0xffd83918 + 11930: 08000884 stmeqda r0, {r2, r7, fp} + 11934: e58d041c str r0, [sp, #1052] + 11938: ebf5c990 bl 0xffd83f80 + 1193c: 08000882 stmeqda r0, {r1, r7, fp} + 11940: e59d9434 ldr r9, [sp, #1076] + 11944: e3c99003 bic r9, r9, #3 ; 0x3 + 11948: e2890004 add r0, r9, #4 ; 0x4 + 1194c: e58d0434 str r0, [sp, #1076] + 11950: e2890000 add r0, r9, #0 ; 0x0 + 11954: ebf5c7ef bl 0xffd83918 + 11958: 08000886 stmeqda r0, {r1, r2, r7, fp} + 1195c: e1a03000 mov r3, r0 + 11960: ebf5c986 bl 0xffd83f80 + 11964: 08000884 stmeqda r0, {r2, r7, fp} + 11968: e1a00003 mov r0, r3 + 1196c: e28cc02c add ip, ip, #44 ; 0x2c + 11970: eaf5c5d6 b 0xffd830d0 + 11974: 08000860 stmeqda r0, {r5, r6, fp} + 11978: 00000000 andeq r0, r0, r0 + 1197c: ebf5c97f bl 0xffd83f80 + 11980: 08000860 stmeqda r0, {r5, r6, fp} + 11984: e3a00f1b mov r0, #108 ; 0x6c + 11988: e3800b02 orr r0, r0, #2048 ; 0x800 + 1198c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11990: ebf5c7e0 bl 0xffd83918 + 11994: 08000864 stmeqda r0, {r2, r5, r6, fp} + 11998: e1a04000 mov r4, r0 + 1199c: ebf5c977 bl 0xffd83f80 + 119a0: 08000862 stmeqda r0, {r1, r5, r6, fp} + 119a4: e1a01008 mov r1, r8 + 119a8: e0983004 adds r3, r8, r4 + 119ac: ebf5c973 bl 0xffd83f80 + 119b0: 08000864 stmeqda r0, {r2, r5, r6, fp} + 119b4: e59d1430 ldr r1, [sp, #1072] + 119b8: e1a05001 mov r5, r1 + 119bc: ebf5c96f bl 0xffd83f80 + 119c0: 08000866 stmeqda r0, {r1, r2, r5, r6, fp} + 119c4: e2830000 add r0, r3, #0 ; 0x0 + 119c8: e1a01005 mov r1, r5 + 119cc: ebf5c6bf bl 0xffd834d0 + 119d0: 08000868 stmeqda r0, {r3, r5, r6, fp} + 119d4: ebf5c969 bl 0xffd83f80 + 119d8: 08000868 stmeqda r0, {r3, r5, r6, fp} + 119dc: e59d0418 ldr r0, [sp, #1048] + 119e0: e2800000 add r0, r0, #0 ; 0x0 + 119e4: e1a01006 mov r1, r6 + 119e8: ebf5c6d7 bl 0xffd8354c + 119ec: 0800086a stmeqda r0, {r1, r3, r5, r6, fp} + 119f0: ebf5c962 bl 0xffd83f80 + 119f4: 0800086a stmeqda r0, {r1, r3, r5, r6, fp} + 119f8: e28cc016 add ip, ip, #22 ; 0x16 + 119fc: e1a00fac mov r0, ip, lsr #31 + 11a00: e08ff100 add pc, pc, r0, lsl #2 + 11a04: 08000880 stmeqda r0, {r7, fp} + 11a08: ebf5c551 bl 0xffd82f54 + 11a0c: ea000001 b 0x11a18 + 11a10: 08000880 stmeqda r0, {r7, fp} + 11a14: 00000000 andeq r0, r0, r0 + 11a18: ebf5c958 bl 0xffd83f80 + 11a1c: 08000880 stmeqda r0, {r7, fp} + 11a20: e59d9434 ldr r9, [sp, #1076] + 11a24: e3c99003 bic r9, r9, #3 ; 0x3 + 11a28: e2890010 add r0, r9, #16 ; 0x10 + 11a2c: e58d0434 str r0, [sp, #1076] + 11a30: e2890000 add r0, r9, #0 ; 0x0 + 11a34: ebf5c7b7 bl 0xffd83918 + 11a38: 08000884 stmeqda r0, {r2, r7, fp} + 11a3c: e1a07000 mov r7, r0 + 11a40: e2890004 add r0, r9, #4 ; 0x4 + 11a44: ebf5c7b3 bl 0xffd83918 + 11a48: 08000884 stmeqda r0, {r2, r7, fp} + 11a4c: e1a08000 mov r8, r0 + 11a50: e2890008 add r0, r9, #8 ; 0x8 + 11a54: ebf5c7af bl 0xffd83918 + 11a58: 08000884 stmeqda r0, {r2, r7, fp} + 11a5c: e58d0418 str r0, [sp, #1048] + 11a60: e289000c add r0, r9, #12 ; 0xc + 11a64: ebf5c7ab bl 0xffd83918 + 11a68: 08000884 stmeqda r0, {r2, r7, fp} + 11a6c: e58d041c str r0, [sp, #1052] + 11a70: ebf5c942 bl 0xffd83f80 + 11a74: 08000882 stmeqda r0, {r1, r7, fp} + 11a78: e59d9434 ldr r9, [sp, #1076] + 11a7c: e3c99003 bic r9, r9, #3 ; 0x3 + 11a80: e2890004 add r0, r9, #4 ; 0x4 + 11a84: e58d0434 str r0, [sp, #1076] + 11a88: e2890000 add r0, r9, #0 ; 0x0 + 11a8c: ebf5c7a1 bl 0xffd83918 + 11a90: 08000886 stmeqda r0, {r1, r2, r7, fp} + 11a94: e1a03000 mov r3, r0 + 11a98: ebf5c938 bl 0xffd83f80 + 11a9c: 08000884 stmeqda r0, {r2, r7, fp} + 11aa0: e1a00003 mov r0, r3 + 11aa4: e28cc00e add ip, ip, #14 ; 0xe + 11aa8: eaf5c588 b 0xffd830d0 + 11aac: 0800036e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9} + 11ab0: 00000000 andeq r0, r0, r0 + 11ab4: ebf5c931 bl 0xffd83f80 + 11ab8: 0800036e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9} + 11abc: e59d1420 ldr r1, [sp, #1056] + 11ac0: e1a07001 mov r7, r1 + 11ac4: ebf5c92d bl 0xffd83f80 + 11ac8: 08000370 stmeqda r0, {r4, r5, r6, r8, r9} + 11acc: ebf5c92b bl 0xffd83f80 + 11ad0: 08000372 stmeqda r0, {r1, r4, r5, r6, r8, r9} + 11ad4: e3a00075 mov r0, #117 ; 0x75 + 11ad8: e3800c03 orr r0, r0, #768 ; 0x300 + 11adc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11ae0: e58d0438 str r0, [sp, #1080] + 11ae4: e28cc009 add ip, ip, #9 ; 0x9 + 11ae8: e1a00fac mov r0, ip, lsr #31 + 11aec: e08ff100 add pc, pc, r0, lsl #2 + 11af0: 080007d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl} + 11af4: ebf5c516 bl 0xffd82f54 + 11af8: eafffe28 b 0x113a0 + 11afc: 08000374 stmeqda r0, {r2, r4, r5, r6, r8, r9} + 11b00: 00000000 andeq r0, r0, r0 + 11b04: ebf5c91d bl 0xffd83f80 + 11b08: 08000374 stmeqda r0, {r2, r4, r5, r6, r8, r9} + 11b0c: e3a00f12 mov r0, #72 ; 0x48 + 11b10: e3800b01 orr r0, r0, #1024 ; 0x400 + 11b14: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11b18: ebf5c77e bl 0xffd83918 + 11b1c: 08000378 stmeqda r0, {r3, r4, r5, r6, r8, r9} + 11b20: e1a03000 mov r3, r0 + 11b24: ebf5c915 bl 0xffd83f80 + 11b28: 08000376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9} + 11b2c: e1a01007 mov r1, r7 + 11b30: e0978003 adds r8, r7, r3 + 11b34: ebf5c911 bl 0xffd83f80 + 11b38: 08000378 stmeqda r0, {r3, r4, r5, r6, r8, r9} + 11b3c: e2880000 add r0, r8, #0 ; 0x0 + 11b40: ebf5c774 bl 0xffd83918 + 11b44: 0800037c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9} + 11b48: e1a03000 mov r3, r0 + 11b4c: ebf5c90b bl 0xffd83f80 + 11b50: 0800037a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9} + 11b54: e3a00f13 mov r0, #76 ; 0x4c + 11b58: e3800b01 orr r0, r0, #1024 ; 0x400 + 11b5c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11b60: ebf5c76c bl 0xffd83918 + 11b64: 0800037e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9} + 11b68: e1a04000 mov r4, r0 + 11b6c: ebf5c903 bl 0xffd83f80 + 11b70: 0800037c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9} + 11b74: e1a01003 mov r1, r3 + 11b78: e0133004 ands r3, r3, r4 + 11b7c: ebf5c8ff bl 0xffd83f80 + 11b80: 0800037e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9} + 11b84: e1530004 cmp r3, r4 + 11b88: ebf5c8fc bl 0xffd83f80 + 11b8c: 08000380 stmeqda r0, {r7, r8, r9} + 11b90: e28cc01b add ip, ip, #27 ; 0x1b + 11b94: 0a000004 beq 0x11bac + 11b98: e1a00fac mov r0, ip, lsr #31 + 11b9c: e08ff100 add pc, pc, r0, lsl #2 + 11ba0: 08000388 stmeqda r0, {r3, r7, r8, r9} + 11ba4: ebf5c4ea bl 0xffd82f54 + 11ba8: ea000010 b 0x11bf0 + 11bac: ebf5c8f3 bl 0xffd83f80 + 11bb0: 08000382 stmeqda r0, {r1, r7, r8, r9} + 11bb4: e3b030ff movs r3, #255 ; 0xff + 11bb8: ebf5c8f0 bl 0xffd83f80 + 11bbc: 08000384 stmeqda r0, {r2, r7, r8, r9} + 11bc0: ebf5c8ee bl 0xffd83f80 + 11bc4: 08000386 stmeqda r0, {r1, r2, r7, r8, r9} + 11bc8: e3a00089 mov r0, #137 ; 0x89 + 11bcc: e3800c03 orr r0, r0, #768 ; 0x300 + 11bd0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11bd4: e58d0438 str r0, [sp, #1080] + 11bd8: e28cc009 add ip, ip, #9 ; 0x9 + 11bdc: e1a00fac mov r0, ip, lsr #31 + 11be0: e08ff100 add pc, pc, r0, lsl #2 + 11be4: 080c2f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp, sp} + 11be8: ebf5c4d9 bl 0xffd82f54 + 11bec: ea00001c b 0x11c64 + 11bf0: ebf5c8e2 bl 0xffd83f80 + 11bf4: 08000388 stmeqda r0, {r3, r7, r8, r9} + 11bf8: e3a00e45 mov r0, #1104 ; 0x450 + 11bfc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11c00: ebf5c744 bl 0xffd83918 + 11c04: 0800038c stmeqda r0, {r2, r3, r7, r8, r9} + 11c08: e1a03000 mov r3, r0 + 11c0c: ebf5c8db bl 0xffd83f80 + 11c10: 0800038a stmeqda r0, {r1, r3, r7, r8, r9} + 11c14: e2830000 add r0, r3, #0 ; 0x0 + 11c18: ebf5c73e bl 0xffd83918 + 11c1c: 0800038e stmeqda r0, {r1, r2, r3, r7, r8, r9} + 11c20: e1a03000 mov r3, r0 + 11c24: ebf5c8d5 bl 0xffd83f80 + 11c28: 0800038c stmeqda r0, {r2, r3, r7, r8, r9} + 11c2c: ebf5c8d3 bl 0xffd83f80 + 11c30: 0800038e stmeqda r0, {r1, r2, r3, r7, r8, r9} + 11c34: e3a00091 mov r0, #145 ; 0x91 + 11c38: e3800c03 orr r0, r0, #768 ; 0x300 + 11c3c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11c40: e58d0438 str r0, [sp, #1080] + 11c44: e28cc010 add ip, ip, #16 ; 0x10 + 11c48: e1a00fac mov r0, ip, lsr #31 + 11c4c: e08ff100 add pc, pc, r0, lsl #2 + 11c50: 080016f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip} + 11c54: ebf5c4be bl 0xffd82f54 + 11c58: ea00002c b 0x11d10 + 11c5c: 080c2f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp, sp} + 11c60: 00000000 andeq r0, r0, r0 + 11c64: ebf5c8c5 bl 0xffd83f80 + 11c68: 080c2f34 stmeqda ip, {r2, r4, r5, r8, r9, sl, fp, sp} + 11c6c: e3a00fd1 mov r0, #836 ; 0x344 + 11c70: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 11c74: e3800703 orr r0, r0, #786432 ; 0xc0000 + 11c78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11c7c: ebf5c725 bl 0xffd83918 + 11c80: 080c2f38 stmeqda ip, {r3, r4, r5, r8, r9, sl, fp, sp} + 11c84: e1a06000 mov r6, r0 + 11c88: ebf5c8bc bl 0xffd83f80 + 11c8c: 080c2f36 stmeqda ip, {r1, r2, r4, r5, r8, r9, sl, fp, sp} + 11c90: e3b05000 movs r5, #0 ; 0x0 + 11c94: ebf5c8b9 bl 0xffd83f80 + 11c98: 080c2f38 stmeqda ip, {r3, r4, r5, r8, r9, sl, fp, sp} + 11c9c: e2860000 add r0, r6, #0 ; 0x0 + 11ca0: e1a01005 mov r1, r5 + 11ca4: ebf5c609 bl 0xffd834d0 + 11ca8: 080c2f3a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, fp, sp} + 11cac: ebf5c8b3 bl 0xffd83f80 + 11cb0: 080c2f3a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, fp, sp} + 11cb4: e3a00fd2 mov r0, #840 ; 0x348 + 11cb8: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 11cbc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 11cc0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11cc4: ebf5c713 bl 0xffd83918 + 11cc8: 080c2f3e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, fp, sp} + 11ccc: e1a04000 mov r4, r0 + 11cd0: ebf5c8aa bl 0xffd83f80 + 11cd4: 080c2f3c stmeqda ip, {r2, r3, r4, r5, r8, r9, sl, fp, sp} + 11cd8: e1a00004 mov r0, r4 + 11cdc: e58d0434 str r0, [sp, #1076] + 11ce0: ebf5c8a6 bl 0xffd83f80 + 11ce4: 080c2f3e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, fp, sp} + 11ce8: ebf5c58b bl 0xffd8331c + 11cec: 080c2f40 stmeqda ip, {r6, r8, r9, sl, fp, sp} + 11cf0: e28cc017 add ip, ip, #23 ; 0x17 + 11cf4: e1a00fac mov r0, ip, lsr #31 + 11cf8: e08ff100 add pc, pc, r0, lsl #2 + 11cfc: 00000008 andeq r0, r0, r8 + 11d00: ebf5c45d bl 0xffd82e7c + 11d04: ea2ab8bd b 0xac0000 + 11d08: 080016f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip} + 11d0c: 00000000 andeq r0, r0, r0 + 11d10: ebf5c89a bl 0xffd83f80 + 11d14: 080016f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip} + 11d18: e59d9434 ldr r9, [sp, #1076] + 11d1c: e3c99003 bic r9, r9, #3 ; 0x3 + 11d20: e2499004 sub r9, r9, #4 ; 0x4 + 11d24: e58d9434 str r9, [sp, #1076] + 11d28: e2890000 add r0, r9, #0 ; 0x0 + 11d2c: e59d1438 ldr r1, [sp, #1080] + 11d30: ebf5c645 bl 0xffd8364c + 11d34: ebf5c891 bl 0xffd83f80 + 11d38: 080016fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl, ip} + 11d3c: e1a01003 mov r1, r3 + 11d40: e2935000 adds r5, r3, #0 ; 0x0 + 11d44: ebf5c88d bl 0xffd83f80 + 11d48: 080016fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, ip} + 11d4c: e2850002 add r0, r5, #2 ; 0x2 + 11d50: ebf5c6c4 bl 0xffd83868 + 11d54: 08001700 stmeqda r0, {r8, r9, sl, ip} + 11d58: e1a04000 mov r4, r0 + 11d5c: ebf5c887 bl 0xffd83f80 + 11d60: 080016fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sl, ip} + 11d64: e3b03080 movs r3, #128 ; 0x80 + 11d68: ebf5c884 bl 0xffd83f80 + 11d6c: 08001700 stmeqda r0, {r8, r9, sl, ip} + 11d70: e1b03203 movs r3, r3, lsl #4 + 11d74: ebf5c881 bl 0xffd83f80 + 11d78: 08001702 stmeqda r0, {r1, r8, r9, sl, ip} + 11d7c: e1a01003 mov r1, r3 + 11d80: e0133004 ands r3, r3, r4 + 11d84: ebf5c87d bl 0xffd83f80 + 11d88: 08001704 stmeqda r0, {r2, r8, r9, sl, ip} + 11d8c: e3530000 cmp r3, #0 ; 0x0 + 11d90: ebf5c87a bl 0xffd83f80 + 11d94: 08001706 stmeqda r0, {r1, r2, r8, r9, sl, ip} + 11d98: e28cc01a add ip, ip, #26 ; 0x1a + 11d9c: 1a000004 bne 0x11db4 + 11da0: e1a00fac mov r0, ip, lsr #31 + 11da4: e08ff100 add pc, pc, r0, lsl #2 + 11da8: 08001718 stmeqda r0, {r3, r4, r8, r9, sl, ip} + 11dac: ebf5c468 bl 0xffd82f54 + 11db0: ea000029 b 0x11e5c + 11db4: ebf5c871 bl 0xffd83f80 + 11db8: 08001708 stmeqda r0, {r3, r8, r9, sl, ip} + 11dbc: e2850022 add r0, r5, #34 ; 0x22 + 11dc0: ebf5c6a8 bl 0xffd83868 + 11dc4: 0800170c stmeqda r0, {r2, r3, r8, r9, sl, ip} + 11dc8: e1a03000 mov r3, r0 + 11dcc: ebf5c86b bl 0xffd83f80 + 11dd0: 0800170a stmeqda r0, {r1, r3, r8, r9, sl, ip} + 11dd4: e1a01003 mov r1, r3 + 11dd8: e2933001 adds r3, r3, #1 ; 0x1 + 11ddc: ebf5c867 bl 0xffd83f80 + 11de0: 0800170c stmeqda r0, {r2, r3, r8, r9, sl, ip} + 11de4: e2850022 add r0, r5, #34 ; 0x22 + 11de8: e1a01003 mov r1, r3 + 11dec: ebf5c5d6 bl 0xffd8354c + 11df0: 0800170e stmeqda r0, {r1, r2, r3, r8, r9, sl, ip} + 11df4: ebf5c861 bl 0xffd83f80 + 11df8: 0800170e stmeqda r0, {r1, r2, r3, r8, r9, sl, ip} + 11dfc: e2850014 add r0, r5, #20 ; 0x14 + 11e00: ebf5c6c4 bl 0xffd83918 + 11e04: 08001712 stmeqda r0, {r1, r4, r8, r9, sl, ip} + 11e08: e1a04000 mov r4, r0 + 11e0c: ebf5c85b bl 0xffd83f80 + 11e10: 08001710 stmeqda r0, {r4, r8, r9, sl, ip} + 11e14: e1a01005 mov r1, r5 + 11e18: e2953000 adds r3, r5, #0 ; 0x0 + 11e1c: ebf5c857 bl 0xffd83f80 + 11e20: 08001712 stmeqda r0, {r1, r4, r8, r9, sl, ip} + 11e24: ebf5c855 bl 0xffd83f80 + 11e28: 08001714 stmeqda r0, {r2, r4, r8, r9, sl, ip} + 11e2c: e3a00017 mov r0, #23 ; 0x17 + 11e30: e3800c17 orr r0, r0, #5888 ; 0x1700 + 11e34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11e38: e58d0438 str r0, [sp, #1080] + 11e3c: e28cc01a add ip, ip, #26 ; 0x1a + 11e40: e1a00fac mov r0, ip, lsr #31 + 11e44: e08ff100 add pc, pc, r0, lsl #2 + 11e48: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 11e4c: ebf5c440 bl 0xffd82f54 + 11e50: eaffcc0d b 0x4e8c + 11e54: 08001718 stmeqda r0, {r3, r4, r8, r9, sl, ip} + 11e58: 00000000 andeq r0, r0, r0 + 11e5c: ebf5c847 bl 0xffd83f80 + 11e60: 08001718 stmeqda r0, {r3, r4, r8, r9, sl, ip} + 11e64: e2850000 add r0, r5, #0 ; 0x0 + 11e68: ebf5c67e bl 0xffd83868 + 11e6c: 0800171c stmeqda r0, {r2, r3, r4, r8, r9, sl, ip} + 11e70: e1a04000 mov r4, r0 + 11e74: ebf5c841 bl 0xffd83f80 + 11e78: 0800171a stmeqda r0, {r1, r3, r4, r8, r9, sl, ip} + 11e7c: e3a00e73 mov r0, #1840 ; 0x730 + 11e80: e3800a01 orr r0, r0, #4096 ; 0x1000 + 11e84: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11e88: ebf5c6a2 bl 0xffd83918 + 11e8c: 0800171e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, ip} + 11e90: e1a03000 mov r3, r0 + 11e94: ebf5c839 bl 0xffd83f80 + 11e98: 0800171c stmeqda r0, {r2, r3, r4, r8, r9, sl, ip} + 11e9c: e1a01003 mov r1, r3 + 11ea0: e0133004 ands r3, r3, r4 + 11ea4: ebf5c835 bl 0xffd83f80 + 11ea8: 0800171e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, ip} + 11eac: e1b03103 movs r3, r3, lsl #2 + 11eb0: ebf5c832 bl 0xffd83f80 + 11eb4: 08001720 stmeqda r0, {r5, r8, r9, sl, ip} + 11eb8: e3a00fcd mov r0, #820 ; 0x334 + 11ebc: e3800b05 orr r0, r0, #5120 ; 0x1400 + 11ec0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11ec4: ebf5c693 bl 0xffd83918 + 11ec8: 08001724 stmeqda r0, {r2, r5, r8, r9, sl, ip} + 11ecc: e1a04000 mov r4, r0 + 11ed0: ebf5c82a bl 0xffd83f80 + 11ed4: 08001722 stmeqda r0, {r1, r5, r8, r9, sl, ip} + 11ed8: e1a01003 mov r1, r3 + 11edc: e0933004 adds r3, r3, r4 + 11ee0: ebf5c826 bl 0xffd83f80 + 11ee4: 08001724 stmeqda r0, {r2, r5, r8, r9, sl, ip} + 11ee8: e2830000 add r0, r3, #0 ; 0x0 + 11eec: ebf5c689 bl 0xffd83918 + 11ef0: 08001728 stmeqda r0, {r3, r5, r8, r9, sl, ip} + 11ef4: e1a04000 mov r4, r0 + 11ef8: ebf5c820 bl 0xffd83f80 + 11efc: 08001726 stmeqda r0, {r1, r2, r5, r8, r9, sl, ip} + 11f00: e1a01005 mov r1, r5 + 11f04: e2953000 adds r3, r5, #0 ; 0x0 + 11f08: ebf5c81c bl 0xffd83f80 + 11f0c: 08001728 stmeqda r0, {r3, r5, r8, r9, sl, ip} + 11f10: ebf5c81a bl 0xffd83f80 + 11f14: 0800172a stmeqda r0, {r1, r3, r5, r8, r9, sl, ip} + 11f18: e3a0002d mov r0, #45 ; 0x2d + 11f1c: e3800c17 orr r0, r0, #5888 ; 0x1700 + 11f20: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 11f24: e58d0438 str r0, [sp, #1080] + 11f28: e28cc026 add ip, ip, #38 ; 0x26 + 11f2c: e1a00fac mov r0, ip, lsr #31 + 11f30: e08ff100 add pc, pc, r0, lsl #2 + 11f34: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 11f38: ebf5c405 bl 0xffd82f54 + 11f3c: eaffcbd2 b 0x4e8c + 11f40: 08002c08 stmeqda r0, {r3, sl, fp, sp} + 11f44: 00000000 andeq r0, r0, r0 + 11f48: ebf5c80c bl 0xffd83f80 + 11f4c: 08002c08 stmeqda r0, {r3, sl, fp, sp} + 11f50: e59d9434 ldr r9, [sp, #1076] + 11f54: e3c99003 bic r9, r9, #3 ; 0x3 + 11f58: e2499008 sub r9, r9, #8 ; 0x8 + 11f5c: e58d9434 str r9, [sp, #1076] + 11f60: e2890000 add r0, r9, #0 ; 0x0 + 11f64: e1a01007 mov r1, r7 + 11f68: ebf5c5b7 bl 0xffd8364c + 11f6c: e2890004 add r0, r9, #4 ; 0x4 + 11f70: e59d1438 ldr r1, [sp, #1080] + 11f74: ebf5c5b4 bl 0xffd8364c + 11f78: ebf5c800 bl 0xffd83f80 + 11f7c: 08002c0a stmeqda r0, {r1, r3, sl, fp, sp} + 11f80: e1a01003 mov r1, r3 + 11f84: e2937000 adds r7, r3, #0 ; 0x0 + 11f88: ebf5c7fc bl 0xffd83f80 + 11f8c: 08002c0c stmeqda r0, {r2, r3, sl, fp, sp} + 11f90: e2870002 add r0, r7, #2 ; 0x2 + 11f94: ebf5c633 bl 0xffd83868 + 11f98: 08002c10 stmeqda r0, {r4, sl, fp, sp} + 11f9c: e1a04000 mov r4, r0 + 11fa0: ebf5c7f6 bl 0xffd83f80 + 11fa4: 08002c0e stmeqda r0, {r1, r2, r3, sl, fp, sp} + 11fa8: e3b03080 movs r3, #128 ; 0x80 + 11fac: ebf5c7f3 bl 0xffd83f80 + 11fb0: 08002c10 stmeqda r0, {r4, sl, fp, sp} + 11fb4: e1b03403 movs r3, r3, lsl #8 + 11fb8: ebf5c7f0 bl 0xffd83f80 + 11fbc: 08002c12 stmeqda r0, {r1, r4, sl, fp, sp} + 11fc0: e1a01003 mov r1, r3 + 11fc4: e0133004 ands r3, r3, r4 + 11fc8: ebf5c7ec bl 0xffd83f80 + 11fcc: 08002c14 stmeqda r0, {r2, r4, sl, fp, sp} + 11fd0: e3530000 cmp r3, #0 ; 0x0 + 11fd4: ebf5c7e9 bl 0xffd83f80 + 11fd8: 08002c16 stmeqda r0, {r1, r2, r4, sl, fp, sp} + 11fdc: e28cc01b add ip, ip, #27 ; 0x1b + 11fe0: 1a000004 bne 0x11ff8 + 11fe4: e1a00fac mov r0, ip, lsr #31 + 11fe8: e08ff100 add pc, pc, r0, lsl #2 + 11fec: 08002c48 stmeqda r0, {r3, r6, sl, fp, sp} + 11ff0: ebf5c3d7 bl 0xffd82f54 + 11ff4: ea00003a b 0x120e4 + 11ff8: ebf5c7e0 bl 0xffd83f80 + 11ffc: 08002c18 stmeqda r0, {r3, r4, sl, fp, sp} + 12000: e2870004 add r0, r7, #4 ; 0x4 + 12004: ebf5c617 bl 0xffd83868 + 12008: 08002c1c stmeqda r0, {r2, r3, r4, sl, fp, sp} + 1200c: e1a03000 mov r3, r0 + 12010: ebf5c7da bl 0xffd83f80 + 12014: 08002c1a stmeqda r0, {r1, r3, r4, sl, fp, sp} + 12018: e3530000 cmp r3, #0 ; 0x0 + 1201c: ebf5c7d7 bl 0xffd83f80 + 12020: 08002c1c stmeqda r0, {r2, r3, r4, sl, fp, sp} + 12024: e28cc00b add ip, ip, #11 ; 0xb + 12028: 1a000004 bne 0x12040 + 1202c: e1a00fac mov r0, ip, lsr #31 + 12030: e08ff100 add pc, pc, r0, lsl #2 + 12034: 08002c40 stmeqda r0, {r6, sl, fp, sp} + 12038: ebf5c3c5 bl 0xffd82f54 + 1203c: ea000052 b 0x1218c + 12040: ebf5c7ce bl 0xffd83f80 + 12044: 08002c1e stmeqda r0, {r1, r2, r3, r4, sl, fp, sp} + 12048: e1a01003 mov r1, r3 + 1204c: e2533001 subs r3, r3, #1 ; 0x1 + 12050: ebf5c7ca bl 0xffd83f80 + 12054: 08002c20 stmeqda r0, {r5, sl, fp, sp} + 12058: e2870004 add r0, r7, #4 ; 0x4 + 1205c: e1a01003 mov r1, r3 + 12060: ebf5c539 bl 0xffd8354c + 12064: 08002c22 stmeqda r0, {r1, r5, sl, fp, sp} + 12068: ebf5c7c4 bl 0xffd83f80 + 1206c: 08002c22 stmeqda r0, {r1, r5, sl, fp, sp} + 12070: e1b03803 movs r3, r3, lsl #16 + 12074: ebf5c7c1 bl 0xffd83f80 + 12078: 08002c24 stmeqda r0, {r2, r5, sl, fp, sp} + 1207c: e3530000 cmp r3, #0 ; 0x0 + 12080: ebf5c7be bl 0xffd83f80 + 12084: 08002c26 stmeqda r0, {r1, r2, r5, sl, fp, sp} + 12088: e28cc010 add ip, ip, #16 ; 0x10 + 1208c: 0a000004 beq 0x120a4 + 12090: e1a00fac mov r0, ip, lsr #31 + 12094: e08ff100 add pc, pc, r0, lsl #2 + 12098: 08002c56 stmeqda r0, {r1, r2, r4, r6, sl, fp, sp} + 1209c: ebf5c3ac bl 0xffd82f54 + 120a0: ea000052 b 0x121f0 + 120a4: ebf5c7b5 bl 0xffd83f80 + 120a8: 08002c28 stmeqda r0, {r3, r5, sl, fp, sp} + 120ac: ebf5c7b3 bl 0xffd83f80 + 120b0: 08002c2a stmeqda r0, {r1, r3, r5, sl, fp, sp} + 120b4: e3a0002d mov r0, #45 ; 0x2d + 120b8: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 120bc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 120c0: e58d0438 str r0, [sp, #1080] + 120c4: e28cc006 add ip, ip, #6 ; 0x6 + 120c8: e1a00fac mov r0, ip, lsr #31 + 120cc: e08ff100 add pc, pc, r0, lsl #2 + 120d0: 08000f50 stmeqda r0, {r4, r6, r8, r9, sl, fp} + 120d4: ebf5c39e bl 0xffd82f54 + 120d8: ea00005f b 0x1225c + 120dc: 08002c48 stmeqda r0, {r3, r6, sl, fp, sp} + 120e0: 00000000 andeq r0, r0, r0 + 120e4: ebf5c7a5 bl 0xffd83f80 + 120e8: 08002c48 stmeqda r0, {r3, r6, sl, fp, sp} + 120ec: e2870022 add r0, r7, #34 ; 0x22 + 120f0: ebf5c5dc bl 0xffd83868 + 120f4: 08002c4c stmeqda r0, {r2, r3, r6, sl, fp, sp} + 120f8: e1a03000 mov r3, r0 + 120fc: ebf5c79f bl 0xffd83f80 + 12100: 08002c4a stmeqda r0, {r1, r3, r6, sl, fp, sp} + 12104: e1a01003 mov r1, r3 + 12108: e2933001 adds r3, r3, #1 ; 0x1 + 1210c: ebf5c79b bl 0xffd83f80 + 12110: 08002c4c stmeqda r0, {r2, r3, r6, sl, fp, sp} + 12114: e2870022 add r0, r7, #34 ; 0x22 + 12118: e1a01003 mov r1, r3 + 1211c: ebf5c50a bl 0xffd8354c + 12120: 08002c4e stmeqda r0, {r1, r2, r3, r6, sl, fp, sp} + 12124: ebf5c795 bl 0xffd83f80 + 12128: 08002c4e stmeqda r0, {r1, r2, r3, r6, sl, fp, sp} + 1212c: e2870014 add r0, r7, #20 ; 0x14 + 12130: ebf5c5f8 bl 0xffd83918 + 12134: 08002c52 stmeqda r0, {r1, r4, r6, sl, fp, sp} + 12138: e1a04000 mov r4, r0 + 1213c: ebf5c78f bl 0xffd83f80 + 12140: 08002c50 stmeqda r0, {r4, r6, sl, fp, sp} + 12144: e1a01007 mov r1, r7 + 12148: e2973000 adds r3, r7, #0 ; 0x0 + 1214c: ebf5c78b bl 0xffd83f80 + 12150: 08002c52 stmeqda r0, {r1, r4, r6, sl, fp, sp} + 12154: ebf5c789 bl 0xffd83f80 + 12158: 08002c54 stmeqda r0, {r2, r4, r6, sl, fp, sp} + 1215c: e3a00057 mov r0, #87 ; 0x57 + 12160: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 12164: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12168: e58d0438 str r0, [sp, #1080] + 1216c: e28cc01a add ip, ip, #26 ; 0x1a + 12170: e1a00fac mov r0, ip, lsr #31 + 12174: e08ff100 add pc, pc, r0, lsl #2 + 12178: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 1217c: ebf5c374 bl 0xffd82f54 + 12180: eaffcb41 b 0x4e8c + 12184: 08002c40 stmeqda r0, {r6, sl, fp, sp} + 12188: 00000000 andeq r0, r0, r0 + 1218c: ebf5c77b bl 0xffd83f80 + 12190: 08002c40 stmeqda r0, {r6, sl, fp, sp} + 12194: e3b04038 movs r4, #56 ; 0x38 + 12198: ebf5c778 bl 0xffd83f80 + 1219c: 08002c42 stmeqda r0, {r1, r6, sl, fp, sp} + 121a0: e0870004 add r0, r7, r4 + 121a4: ebf5c5c4 bl 0xffd838bc + 121a8: 08002c46 stmeqda r0, {r1, r2, r6, sl, fp, sp} + 121ac: e1a03000 mov r3, r0 + 121b0: ebf5c772 bl 0xffd83f80 + 121b4: 08002c44 stmeqda r0, {r2, r6, sl, fp, sp} + 121b8: ebf5c770 bl 0xffd83f80 + 121bc: 08002c46 stmeqda r0, {r1, r2, r6, sl, fp, sp} + 121c0: e3a00049 mov r0, #73 ; 0x49 + 121c4: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 121c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 121cc: e58d0438 str r0, [sp, #1080] + 121d0: e28cc00e add ip, ip, #14 ; 0xe + 121d4: e1a00fac mov r0, ip, lsr #31 + 121d8: e08ff100 add pc, pc, r0, lsl #2 + 121dc: 08002b80 stmeqda r0, {r7, r8, r9, fp, sp} + 121e0: ebf5c35b bl 0xffd82f54 + 121e4: eafff679 b 0xfbd0 + 121e8: 08002c56 stmeqda r0, {r1, r2, r4, r6, sl, fp, sp} + 121ec: 00000000 andeq r0, r0, r0 + 121f0: ebf5c762 bl 0xffd83f80 + 121f4: 08002c56 stmeqda r0, {r1, r2, r4, r6, sl, fp, sp} + 121f8: e59d9434 ldr r9, [sp, #1076] + 121fc: e3c99003 bic r9, r9, #3 ; 0x3 + 12200: e2890004 add r0, r9, #4 ; 0x4 + 12204: e58d0434 str r0, [sp, #1076] + 12208: e2890000 add r0, r9, #0 ; 0x0 + 1220c: ebf5c5c1 bl 0xffd83918 + 12210: 08002c5a stmeqda r0, {r1, r3, r4, r6, sl, fp, sp} + 12214: e1a07000 mov r7, r0 + 12218: ebf5c758 bl 0xffd83f80 + 1221c: 08002c58 stmeqda r0, {r3, r4, r6, sl, fp, sp} + 12220: e59d9434 ldr r9, [sp, #1076] + 12224: e3c99003 bic r9, r9, #3 ; 0x3 + 12228: e2890004 add r0, r9, #4 ; 0x4 + 1222c: e58d0434 str r0, [sp, #1076] + 12230: e2890000 add r0, r9, #0 ; 0x0 + 12234: ebf5c5b7 bl 0xffd83918 + 12238: 08002c5c stmeqda r0, {r2, r3, r4, r6, sl, fp, sp} + 1223c: e1a03000 mov r3, r0 + 12240: ebf5c74e bl 0xffd83f80 + 12244: 08002c5a stmeqda r0, {r1, r3, r4, r6, sl, fp, sp} + 12248: e1a00003 mov r0, r3 + 1224c: e28cc00b add ip, ip, #11 ; 0xb + 12250: eaf5c39e b 0xffd830d0 + 12254: 08000f50 stmeqda r0, {r4, r6, r8, r9, sl, fp} + 12258: 00000000 andeq r0, r0, r0 + 1225c: ebf5c747 bl 0xffd83f80 + 12260: 08000f50 stmeqda r0, {r4, r6, r8, r9, sl, fp} + 12264: e3a00fd7 mov r0, #860 ; 0x35c + 12268: e3800b03 orr r0, r0, #3072 ; 0xc00 + 1226c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12270: ebf5c5a8 bl 0xffd83918 + 12274: 08000f54 stmeqda r0, {r2, r4, r6, r8, r9, sl, fp} + 12278: e1a03000 mov r3, r0 + 1227c: ebf5c73f bl 0xffd83f80 + 12280: 08000f52 stmeqda r0, {r1, r4, r6, r8, r9, sl, fp} + 12284: e2830000 add r0, r3, #0 ; 0x0 + 12288: ebf5c5a2 bl 0xffd83918 + 1228c: 08000f56 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, fp} + 12290: e1a04000 mov r4, r0 + 12294: ebf5c739 bl 0xffd83f80 + 12298: 08000f54 stmeqda r0, {r2, r4, r6, r8, r9, sl, fp} + 1229c: e3a00ef6 mov r0, #3936 ; 0xf60 + 122a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 122a4: ebf5c59b bl 0xffd83918 + 122a8: 08000f58 stmeqda r0, {r3, r4, r6, r8, r9, sl, fp} + 122ac: e1a05000 mov r5, r0 + 122b0: ebf5c732 bl 0xffd83f80 + 122b4: 08000f56 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, fp} + 122b8: e1a01004 mov r1, r4 + 122bc: e0144005 ands r4, r4, r5 + 122c0: ebf5c72e bl 0xffd83f80 + 122c4: 08000f58 stmeqda r0, {r3, r4, r6, r8, r9, sl, fp} + 122c8: e2830000 add r0, r3, #0 ; 0x0 + 122cc: e1a01004 mov r1, r4 + 122d0: ebf5c4bd bl 0xffd835cc + 122d4: 08000f5a stmeqda r0, {r1, r3, r4, r6, r8, r9, sl, fp} + 122d8: ebf5c728 bl 0xffd83f80 + 122dc: 08000f5a stmeqda r0, {r1, r3, r4, r6, r8, r9, sl, fp} + 122e0: e59d0438 ldr r0, [sp, #1080] + 122e4: e28cc019 add ip, ip, #25 ; 0x19 + 122e8: eaf5c378 b 0xffd830d0 + 122ec: 08002c5c stmeqda r0, {r2, r3, r4, r6, sl, fp, sp} + 122f0: 00000000 andeq r0, r0, r0 + 122f4: ebf5c721 bl 0xffd83f80 + 122f8: 08002c5c stmeqda r0, {r2, r3, r4, r6, sl, fp, sp} + 122fc: e59d9434 ldr r9, [sp, #1076] + 12300: e3c99003 bic r9, r9, #3 ; 0x3 + 12304: e2499004 sub r9, r9, #4 ; 0x4 + 12308: e58d9434 str r9, [sp, #1076] + 1230c: e2890000 add r0, r9, #0 ; 0x0 + 12310: e59d1438 ldr r1, [sp, #1080] + 12314: ebf5c4cc bl 0xffd8364c + 12318: ebf5c718 bl 0xffd83f80 + 1231c: 08002c5e stmeqda r0, {r1, r2, r3, r4, r6, sl, fp, sp} + 12320: e3a00ec7 mov r0, #3184 ; 0xc70 + 12324: e3800a02 orr r0, r0, #8192 ; 0x2000 + 12328: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1232c: ebf5c579 bl 0xffd83918 + 12330: 08002c62 stmeqda r0, {r1, r5, r6, sl, fp, sp} + 12334: e1a05000 mov r5, r0 + 12338: ebf5c710 bl 0xffd83f80 + 1233c: 08002c60 stmeqda r0, {r5, r6, sl, fp, sp} + 12340: e2830014 add r0, r3, #20 ; 0x14 + 12344: e1a01005 mov r1, r5 + 12348: ebf5c49f bl 0xffd835cc + 1234c: 08002c62 stmeqda r0, {r1, r5, r6, sl, fp, sp} + 12350: ebf5c70a bl 0xffd83f80 + 12354: 08002c62 stmeqda r0, {r1, r5, r6, sl, fp, sp} + 12358: e2830022 add r0, r3, #34 ; 0x22 + 1235c: ebf5c541 bl 0xffd83868 + 12360: 08002c66 stmeqda r0, {r1, r2, r5, r6, sl, fp, sp} + 12364: e1a04000 mov r4, r0 + 12368: ebf5c704 bl 0xffd83f80 + 1236c: 08002c64 stmeqda r0, {r2, r5, r6, sl, fp, sp} + 12370: e1a01004 mov r1, r4 + 12374: e2944001 adds r4, r4, #1 ; 0x1 + 12378: ebf5c700 bl 0xffd83f80 + 1237c: 08002c66 stmeqda r0, {r1, r2, r5, r6, sl, fp, sp} + 12380: e2830022 add r0, r3, #34 ; 0x22 + 12384: e1a01004 mov r1, r4 + 12388: ebf5c46f bl 0xffd8354c + 1238c: 08002c68 stmeqda r0, {r3, r5, r6, sl, fp, sp} + 12390: ebf5c6fa bl 0xffd83f80 + 12394: 08002c68 stmeqda r0, {r3, r5, r6, sl, fp, sp} + 12398: ebf5c6f8 bl 0xffd83f80 + 1239c: 08002c6a stmeqda r0, {r1, r3, r5, r6, sl, fp, sp} + 123a0: e3a0006d mov r0, #109 ; 0x6d + 123a4: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 123a8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 123ac: e58d0438 str r0, [sp, #1080] + 123b0: e28cc01e add ip, ip, #30 ; 0x1e + 123b4: e1a00fac mov r0, ip, lsr #31 + 123b8: e08ff100 add pc, pc, r0, lsl #2 + 123bc: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 123c0: ebf5c2e3 bl 0xffd82f54 + 123c4: ea000001 b 0x123d0 + 123c8: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 123cc: 00000000 andeq r0, r0, r0 + 123d0: ebf5c6ea bl 0xffd83f80 + 123d4: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 123d8: e1a00005 mov r0, r5 + 123dc: e28cc003 add ip, ip, #3 ; 0x3 + 123e0: eaf5c33a b 0xffd830d0 + 123e4: 08002c74 stmeqda r0, {r2, r4, r5, r6, sl, fp, sp} + 123e8: 00000000 andeq r0, r0, r0 + 123ec: ebf5c6e3 bl 0xffd83f80 + 123f0: 08002c74 stmeqda r0, {r2, r4, r5, r6, sl, fp, sp} + 123f4: e59d9434 ldr r9, [sp, #1076] + 123f8: e3c99003 bic r9, r9, #3 ; 0x3 + 123fc: e2499008 sub r9, r9, #8 ; 0x8 + 12400: e58d9434 str r9, [sp, #1076] + 12404: e2890000 add r0, r9, #0 ; 0x0 + 12408: e1a01007 mov r1, r7 + 1240c: ebf5c48e bl 0xffd8364c + 12410: e2890004 add r0, r9, #4 ; 0x4 + 12414: e59d1438 ldr r1, [sp, #1080] + 12418: ebf5c48b bl 0xffd8364c + 1241c: ebf5c6d7 bl 0xffd83f80 + 12420: 08002c76 stmeqda r0, {r1, r2, r4, r5, r6, sl, fp, sp} + 12424: e1a01003 mov r1, r3 + 12428: e2937000 adds r7, r3, #0 ; 0x0 + 1242c: ebf5c6d3 bl 0xffd83f80 + 12430: 08002c78 stmeqda r0, {r3, r4, r5, r6, sl, fp, sp} + 12434: ebf5c6d1 bl 0xffd83f80 + 12438: 08002c7a stmeqda r0, {r1, r3, r4, r5, r6, sl, fp, sp} + 1243c: e3a0007d mov r0, #125 ; 0x7d + 12440: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 12444: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12448: e58d0438 str r0, [sp, #1080] + 1244c: e28cc00d add ip, ip, #13 ; 0xd + 12450: e1a00fac mov r0, ip, lsr #31 + 12454: e08ff100 add pc, pc, r0, lsl #2 + 12458: 08002e34 stmeqda r0, {r2, r4, r5, r9, sl, fp, sp} + 1245c: ebf5c2bc bl 0xffd82f54 + 12460: ea000001 b 0x1246c + 12464: 08002e34 stmeqda r0, {r2, r4, r5, r9, sl, fp, sp} + 12468: 00000000 andeq r0, r0, r0 + 1246c: ebf5c6c3 bl 0xffd83f80 + 12470: 08002e34 stmeqda r0, {r2, r4, r5, r9, sl, fp, sp} + 12474: e59d9434 ldr r9, [sp, #1076] + 12478: e3c99003 bic r9, r9, #3 ; 0x3 + 1247c: e249900c sub r9, r9, #12 ; 0xc + 12480: e58d9434 str r9, [sp, #1076] + 12484: e2890000 add r0, r9, #0 ; 0x0 + 12488: e1a01007 mov r1, r7 + 1248c: ebf5c46e bl 0xffd8364c + 12490: e2890004 add r0, r9, #4 ; 0x4 + 12494: e1a01008 mov r1, r8 + 12498: ebf5c46b bl 0xffd8364c + 1249c: e2890008 add r0, r9, #8 ; 0x8 + 124a0: e59d1438 ldr r1, [sp, #1080] + 124a4: ebf5c468 bl 0xffd8364c + 124a8: ebf5c6b4 bl 0xffd83f80 + 124ac: 08002e36 stmeqda r0, {r1, r2, r4, r5, r9, sl, fp, sp} + 124b0: e3a00f97 mov r0, #604 ; 0x25c + 124b4: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 124b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 124bc: ebf5c515 bl 0xffd83918 + 124c0: 08002e3a stmeqda r0, {r1, r3, r4, r5, r9, sl, fp, sp} + 124c4: e1a03000 mov r3, r0 + 124c8: ebf5c6ac bl 0xffd83f80 + 124cc: 08002e38 stmeqda r0, {r3, r4, r5, r9, sl, fp, sp} + 124d0: e3b040aa movs r4, #170 ; 0xaa + 124d4: ebf5c6a9 bl 0xffd83f80 + 124d8: 08002e3a stmeqda r0, {r1, r3, r4, r5, r9, sl, fp, sp} + 124dc: e1b04184 movs r4, r4, lsl #3 + 124e0: ebf5c6a6 bl 0xffd83f80 + 124e4: 08002e3c stmeqda r0, {r2, r3, r4, r5, r9, sl, fp, sp} + 124e8: e1a01003 mov r1, r3 + 124ec: e0933004 adds r3, r3, r4 + 124f0: ebf5c6a2 bl 0xffd83f80 + 124f4: 08002e3e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, fp, sp} + 124f8: e2830000 add r0, r3, #0 ; 0x0 + 124fc: ebf5c505 bl 0xffd83918 + 12500: 08002e42 stmeqda r0, {r1, r6, r9, sl, fp, sp} + 12504: e1a08000 mov r8, r0 + 12508: ebf5c69c bl 0xffd83f80 + 1250c: 08002e40 stmeqda r0, {r6, r9, sl, fp, sp} + 12510: e3580000 cmp r8, #0 ; 0x0 + 12514: ebf5c699 bl 0xffd83f80 + 12518: 08002e42 stmeqda r0, {r1, r6, r9, sl, fp, sp} + 1251c: e28cc01e add ip, ip, #30 ; 0x1e + 12520: 1a000004 bne 0x12538 + 12524: e1a00fac mov r0, ip, lsr #31 + 12528: e08ff100 add pc, pc, r0, lsl #2 + 1252c: 08002e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp, sp} + 12530: ebf5c287 bl 0xffd82f54 + 12534: ea00003d b 0x12630 + 12538: ebf5c690 bl 0xffd83f80 + 1253c: 08002e44 stmeqda r0, {r2, r6, r9, sl, fp, sp} + 12540: e2880004 add r0, r8, #4 ; 0x4 + 12544: ebf5c4f3 bl 0xffd83918 + 12548: 08002e48 stmeqda r0, {r3, r6, r9, sl, fp, sp} + 1254c: e1a07000 mov r7, r0 + 12550: ebf5c68a bl 0xffd83f80 + 12554: 08002e46 stmeqda r0, {r1, r2, r6, r9, sl, fp, sp} + 12558: e2870004 add r0, r7, #4 ; 0x4 + 1255c: ebf5c4ed bl 0xffd83918 + 12560: 08002e4a stmeqda r0, {r1, r3, r6, r9, sl, fp, sp} + 12564: e1a03000 mov r3, r0 + 12568: ebf5c684 bl 0xffd83f80 + 1256c: 08002e48 stmeqda r0, {r3, r6, r9, sl, fp, sp} + 12570: e1a01003 mov r1, r3 + 12574: e2533001 subs r3, r3, #1 ; 0x1 + 12578: ebf5c680 bl 0xffd83f80 + 1257c: 08002e4a stmeqda r0, {r1, r3, r6, r9, sl, fp, sp} + 12580: e2870004 add r0, r7, #4 ; 0x4 + 12584: e1a01003 mov r1, r3 + 12588: ebf5c40f bl 0xffd835cc + 1258c: 08002e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, sp} + 12590: ebf5c67a bl 0xffd83f80 + 12594: 08002e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, sp} + 12598: e3530000 cmp r3, #0 ; 0x0 + 1259c: ebf5c677 bl 0xffd83f80 + 125a0: 08002e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp, sp} + 125a4: e28cc017 add ip, ip, #23 ; 0x17 + 125a8: 0a000004 beq 0x125c0 + 125ac: e1a00fac mov r0, ip, lsr #31 + 125b0: e08ff100 add pc, pc, r0, lsl #2 + 125b4: 08002e96 stmeqda r0, {r1, r2, r4, r7, r9, sl, fp, sp} + 125b8: ebf5c265 bl 0xffd82f54 + 125bc: ea000104 b 0x129d4 + 125c0: ebf5c66e bl 0xffd83f80 + 125c4: 08002e50 stmeqda r0, {r4, r6, r9, sl, fp, sp} + 125c8: e3a00ee6 mov r0, #3680 ; 0xe60 + 125cc: e3800a02 orr r0, r0, #8192 ; 0x2000 + 125d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 125d4: ebf5c4cf bl 0xffd83918 + 125d8: 08002e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, sp} + 125dc: e1a03000 mov r3, r0 + 125e0: ebf5c666 bl 0xffd83f80 + 125e4: 08002e52 stmeqda r0, {r1, r4, r6, r9, sl, fp, sp} + 125e8: e1a01007 mov r1, r7 + 125ec: e2974000 adds r4, r7, #0 ; 0x0 + 125f0: ebf5c662 bl 0xffd83f80 + 125f4: 08002e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, sp} + 125f8: ebf5c660 bl 0xffd83f80 + 125fc: 08002e56 stmeqda r0, {r1, r2, r4, r6, r9, sl, fp, sp} + 12600: e3a00059 mov r0, #89 ; 0x59 + 12604: e3800c2e orr r0, r0, #11776 ; 0x2e00 + 12608: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1260c: e58d0438 str r0, [sp, #1080] + 12610: e28cc00e add ip, ip, #14 ; 0xe + 12614: e1a00fac mov r0, ip, lsr #31 + 12618: e08ff100 add pc, pc, r0, lsl #2 + 1261c: 08000ce4 stmeqda r0, {r2, r5, r6, r7, sl, fp} + 12620: ebf5c24b bl 0xffd82f54 + 12624: ea00014a b 0x12b54 + 12628: 08002e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp, sp} + 1262c: 00000000 andeq r0, r0, r0 + 12630: ebf5c652 bl 0xffd83f80 + 12634: 08002e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp, sp} + 12638: ebf5c650 bl 0xffd83f80 + 1263c: 08002e9e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, fp, sp} + 12640: e3a000a1 mov r0, #161 ; 0xa1 + 12644: e3800c2e orr r0, r0, #11776 ; 0x2e00 + 12648: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1264c: e58d0438 str r0, [sp, #1080] + 12650: e28cc006 add ip, ip, #6 ; 0x6 + 12654: e1a00fac mov r0, ip, lsr #31 + 12658: e08ff100 add pc, pc, r0, lsl #2 + 1265c: 08001448 stmeqda r0, {r3, r6, sl, ip} + 12660: ebf5c23b bl 0xffd82f54 + 12664: ea000001 b 0x12670 + 12668: 08001448 stmeqda r0, {r3, r6, sl, ip} + 1266c: 00000000 andeq r0, r0, r0 + 12670: ebf5c642 bl 0xffd83f80 + 12674: 08001448 stmeqda r0, {r3, r6, sl, ip} + 12678: e59d9434 ldr r9, [sp, #1076] + 1267c: e3c99003 bic r9, r9, #3 ; 0x3 + 12680: e249900c sub r9, r9, #12 ; 0xc + 12684: e58d9434 str r9, [sp, #1076] + 12688: e2890000 add r0, r9, #0 ; 0x0 + 1268c: e1a01007 mov r1, r7 + 12690: ebf5c3ed bl 0xffd8364c + 12694: e2890004 add r0, r9, #4 ; 0x4 + 12698: e1a01008 mov r1, r8 + 1269c: ebf5c3ea bl 0xffd8364c + 126a0: e2890008 add r0, r9, #8 ; 0x8 + 126a4: e59d1438 ldr r1, [sp, #1080] + 126a8: ebf5c3e7 bl 0xffd8364c + 126ac: ebf5c633 bl 0xffd83f80 + 126b0: 0800144a stmeqda r0, {r1, r3, r6, sl, ip} + 126b4: e3a00f17 mov r0, #92 ; 0x5c + 126b8: e3800b05 orr r0, r0, #5120 ; 0x1400 + 126bc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 126c0: ebf5c494 bl 0xffd83918 + 126c4: 0800144e stmeqda r0, {r1, r2, r3, r6, sl, ip} + 126c8: e1a03000 mov r3, r0 + 126cc: ebf5c62b bl 0xffd83f80 + 126d0: 0800144c stmeqda r0, {r2, r3, r6, sl, ip} + 126d4: e2830000 add r0, r3, #0 ; 0x0 + 126d8: ebf5c48e bl 0xffd83918 + 126dc: 08001450 stmeqda r0, {r4, r6, sl, ip} + 126e0: e1a05000 mov r5, r0 + 126e4: ebf5c625 bl 0xffd83f80 + 126e8: 0800144e stmeqda r0, {r1, r2, r3, r6, sl, ip} + 126ec: e1a01005 mov r1, r5 + 126f0: e2954000 adds r4, r5, #0 ; 0x0 + 126f4: ebf5c621 bl 0xffd83f80 + 126f8: 08001450 stmeqda r0, {r4, r6, sl, ip} + 126fc: e1a01004 mov r1, r4 + 12700: e25440bc subs r4, r4, #188 ; 0xbc + 12704: ebf5c61d bl 0xffd83f80 + 12708: 08001452 stmeqda r0, {r1, r4, r6, sl, ip} + 1270c: e3a00e46 mov r0, #1120 ; 0x460 + 12710: e3800a01 orr r0, r0, #4096 ; 0x1000 + 12714: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12718: ebf5c47e bl 0xffd83918 + 1271c: 08001456 stmeqda r0, {r1, r2, r4, r6, sl, ip} + 12720: e1a03000 mov r3, r0 + 12724: ebf5c615 bl 0xffd83f80 + 12728: 08001454 stmeqda r0, {r2, r4, r6, sl, ip} + 1272c: e2830000 add r0, r3, #0 ; 0x0 + 12730: ebf5c478 bl 0xffd83918 + 12734: 08001458 stmeqda r0, {r3, r4, r6, sl, ip} + 12738: e1a06000 mov r6, r0 + 1273c: ebf5c60f bl 0xffd83f80 + 12740: 08001456 stmeqda r0, {r1, r2, r4, r6, sl, ip} + 12744: e3a00f19 mov r0, #100 ; 0x64 + 12748: e3800b05 orr r0, r0, #5120 ; 0x1400 + 1274c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12750: ebf5c470 bl 0xffd83918 + 12754: 0800145a stmeqda r0, {r1, r3, r4, r6, sl, ip} + 12758: e1a07000 mov r7, r0 + 1275c: ebf5c607 bl 0xffd83f80 + 12760: 08001458 stmeqda r0, {r3, r4, r6, sl, ip} + 12764: e28cc027 add ip, ip, #39 ; 0x27 + 12768: e1a00fac mov r0, ip, lsr #31 + 1276c: e08ff100 add pc, pc, r0, lsl #2 + 12770: 0800146c stmeqda r0, {r2, r3, r5, r6, sl, ip} + 12774: ebf5c1f6 bl 0xffd82f54 + 12778: ea000001 b 0x12784 + 1277c: 0800146c stmeqda r0, {r2, r3, r5, r6, sl, ip} + 12780: 00000000 andeq r0, r0, r0 + 12784: ebf5c5fd bl 0xffd83f80 + 12788: 0800146c stmeqda r0, {r2, r3, r5, r6, sl, ip} + 1278c: e1560004 cmp r6, r4 + 12790: ebf5c5fa bl 0xffd83f80 + 12794: 0800146e stmeqda r0, {r1, r2, r3, r5, r6, sl, ip} + 12798: e28cc006 add ip, ip, #6 ; 0x6 + 1279c: 9a000004 bls 0x127b4 + 127a0: e1a00fac mov r0, ip, lsr #31 + 127a4: e08ff100 add pc, pc, r0, lsl #2 + 127a8: 08001478 stmeqda r0, {r3, r4, r5, r6, sl, ip} + 127ac: ebf5c1e8 bl 0xffd82f54 + 127b0: ea000014 b 0x12808 + 127b4: ebf5c5f1 bl 0xffd83f80 + 127b8: 08001470 stmeqda r0, {r4, r5, r6, sl, ip} + 127bc: e3b08000 movs r8, #0 ; 0x0 + 127c0: ebf5c5ee bl 0xffd83f80 + 127c4: 08001472 stmeqda r0, {r1, r4, r5, r6, sl, ip} + 127c8: e0840008 add r0, r4, r8 + 127cc: ebf5c43a bl 0xffd838bc + 127d0: 08001476 stmeqda r0, {r1, r2, r4, r5, r6, sl, ip} + 127d4: e1a03000 mov r3, r0 + 127d8: ebf5c5e8 bl 0xffd83f80 + 127dc: 08001474 stmeqda r0, {r2, r4, r5, r6, sl, ip} + 127e0: e3530000 cmp r3, #0 ; 0x0 + 127e4: ebf5c5e5 bl 0xffd83f80 + 127e8: 08001476 stmeqda r0, {r1, r2, r4, r5, r6, sl, ip} + 127ec: e28cc00e add ip, ip, #14 ; 0xe + 127f0: 1a000004 bne 0x12808 + 127f4: e1a00fac mov r0, ip, lsr #31 + 127f8: e08ff100 add pc, pc, r0, lsl #2 + 127fc: 08001468 stmeqda r0, {r3, r5, r6, sl, ip} + 12800: ebf5c1d3 bl 0xffd82f54 + 12804: ea000024 b 0x1289c + 12808: ebf5c5dc bl 0xffd83f80 + 1280c: 08001478 stmeqda r0, {r3, r4, r5, r6, sl, ip} + 12810: e2870000 add r0, r7, #0 ; 0x0 + 12814: e1a01005 mov r1, r5 + 12818: ebf5c36b bl 0xffd835cc + 1281c: 0800147a stmeqda r0, {r1, r3, r4, r5, r6, sl, ip} + 12820: ebf5c5d6 bl 0xffd83f80 + 12824: 0800147a stmeqda r0, {r1, r3, r4, r5, r6, sl, ip} + 12828: e59d9434 ldr r9, [sp, #1076] + 1282c: e3c99003 bic r9, r9, #3 ; 0x3 + 12830: e2890008 add r0, r9, #8 ; 0x8 + 12834: e58d0434 str r0, [sp, #1076] + 12838: e2890000 add r0, r9, #0 ; 0x0 + 1283c: ebf5c435 bl 0xffd83918 + 12840: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 12844: e1a07000 mov r7, r0 + 12848: e2890004 add r0, r9, #4 ; 0x4 + 1284c: ebf5c431 bl 0xffd83918 + 12850: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 12854: e1a08000 mov r8, r0 + 12858: ebf5c5c8 bl 0xffd83f80 + 1285c: 0800147c stmeqda r0, {r2, r3, r4, r5, r6, sl, ip} + 12860: e59d9434 ldr r9, [sp, #1076] + 12864: e3c99003 bic r9, r9, #3 ; 0x3 + 12868: e2890004 add r0, r9, #4 ; 0x4 + 1286c: e58d0434 str r0, [sp, #1076] + 12870: e2890000 add r0, r9, #0 ; 0x0 + 12874: ebf5c427 bl 0xffd83918 + 12878: 08001480 stmeqda r0, {r7, sl, ip} + 1287c: e1a03000 mov r3, r0 + 12880: ebf5c5be bl 0xffd83f80 + 12884: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 12888: e1a00003 mov r0, r3 + 1288c: e28cc010 add ip, ip, #16 ; 0x10 + 12890: eaf5c20e b 0xffd830d0 + 12894: 08001468 stmeqda r0, {r3, r5, r6, sl, ip} + 12898: 00000000 andeq r0, r0, r0 + 1289c: ebf5c5b7 bl 0xffd83f80 + 128a0: 08001468 stmeqda r0, {r3, r5, r6, sl, ip} + 128a4: e1a01004 mov r1, r4 + 128a8: e2945000 adds r5, r4, #0 ; 0x0 + 128ac: ebf5c5b3 bl 0xffd83f80 + 128b0: 0800146a stmeqda r0, {r1, r3, r5, r6, sl, ip} + 128b4: e1a01004 mov r1, r4 + 128b8: e25440bc subs r4, r4, #188 ; 0xbc + 128bc: ebf5c5af bl 0xffd83f80 + 128c0: 0800146c stmeqda r0, {r2, r3, r5, r6, sl, ip} + 128c4: e1560004 cmp r6, r4 + 128c8: ebf5c5ac bl 0xffd83f80 + 128cc: 0800146e stmeqda r0, {r1, r2, r3, r5, r6, sl, ip} + 128d0: e28cc00c add ip, ip, #12 ; 0xc + 128d4: 9a000004 bls 0x128ec + 128d8: e1a00fac mov r0, ip, lsr #31 + 128dc: e08ff100 add pc, pc, r0, lsl #2 + 128e0: 08001478 stmeqda r0, {r3, r4, r5, r6, sl, ip} + 128e4: ebf5c19a bl 0xffd82f54 + 128e8: ea000014 b 0x12940 + 128ec: ebf5c5a3 bl 0xffd83f80 + 128f0: 08001470 stmeqda r0, {r4, r5, r6, sl, ip} + 128f4: e3b08000 movs r8, #0 ; 0x0 + 128f8: ebf5c5a0 bl 0xffd83f80 + 128fc: 08001472 stmeqda r0, {r1, r4, r5, r6, sl, ip} + 12900: e0840008 add r0, r4, r8 + 12904: ebf5c3ec bl 0xffd838bc + 12908: 08001476 stmeqda r0, {r1, r2, r4, r5, r6, sl, ip} + 1290c: e1a03000 mov r3, r0 + 12910: ebf5c59a bl 0xffd83f80 + 12914: 08001474 stmeqda r0, {r2, r4, r5, r6, sl, ip} + 12918: e3530000 cmp r3, #0 ; 0x0 + 1291c: ebf5c597 bl 0xffd83f80 + 12920: 08001476 stmeqda r0, {r1, r2, r4, r5, r6, sl, ip} + 12924: e28cc00e add ip, ip, #14 ; 0xe + 12928: 1a000004 bne 0x12940 + 1292c: e1a00fac mov r0, ip, lsr #31 + 12930: e08ff100 add pc, pc, r0, lsl #2 + 12934: 08001468 stmeqda r0, {r3, r5, r6, sl, ip} + 12938: ebf5c185 bl 0xffd82f54 + 1293c: eaffffd6 b 0x1289c + 12940: ebf5c58e bl 0xffd83f80 + 12944: 08001478 stmeqda r0, {r3, r4, r5, r6, sl, ip} + 12948: e2870000 add r0, r7, #0 ; 0x0 + 1294c: e1a01005 mov r1, r5 + 12950: ebf5c31d bl 0xffd835cc + 12954: 0800147a stmeqda r0, {r1, r3, r4, r5, r6, sl, ip} + 12958: ebf5c588 bl 0xffd83f80 + 1295c: 0800147a stmeqda r0, {r1, r3, r4, r5, r6, sl, ip} + 12960: e59d9434 ldr r9, [sp, #1076] + 12964: e3c99003 bic r9, r9, #3 ; 0x3 + 12968: e2890008 add r0, r9, #8 ; 0x8 + 1296c: e58d0434 str r0, [sp, #1076] + 12970: e2890000 add r0, r9, #0 ; 0x0 + 12974: ebf5c3e7 bl 0xffd83918 + 12978: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 1297c: e1a07000 mov r7, r0 + 12980: e2890004 add r0, r9, #4 ; 0x4 + 12984: ebf5c3e3 bl 0xffd83918 + 12988: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 1298c: e1a08000 mov r8, r0 + 12990: ebf5c57a bl 0xffd83f80 + 12994: 0800147c stmeqda r0, {r2, r3, r4, r5, r6, sl, ip} + 12998: e59d9434 ldr r9, [sp, #1076] + 1299c: e3c99003 bic r9, r9, #3 ; 0x3 + 129a0: e2890004 add r0, r9, #4 ; 0x4 + 129a4: e58d0434 str r0, [sp, #1076] + 129a8: e2890000 add r0, r9, #0 ; 0x0 + 129ac: ebf5c3d9 bl 0xffd83918 + 129b0: 08001480 stmeqda r0, {r7, sl, ip} + 129b4: e1a03000 mov r3, r0 + 129b8: ebf5c570 bl 0xffd83f80 + 129bc: 0800147e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, ip} + 129c0: e1a00003 mov r0, r3 + 129c4: e28cc010 add ip, ip, #16 ; 0x10 + 129c8: eaf5c1c0 b 0xffd830d0 + 129cc: 08002e96 stmeqda r0, {r1, r2, r4, r7, r9, sl, fp, sp} + 129d0: 00000000 andeq r0, r0, r0 + 129d4: ebf5c569 bl 0xffd83f80 + 129d8: 08002e96 stmeqda r0, {r1, r2, r4, r7, r9, sl, fp, sp} + 129dc: e2880000 add r0, r8, #0 ; 0x0 + 129e0: ebf5c3cc bl 0xffd83918 + 129e4: 08002e9a stmeqda r0, {r1, r3, r4, r7, r9, sl, fp, sp} + 129e8: e1a08000 mov r8, r0 + 129ec: ebf5c563 bl 0xffd83f80 + 129f0: 08002e98 stmeqda r0, {r3, r4, r7, r9, sl, fp, sp} + 129f4: e3580000 cmp r8, #0 ; 0x0 + 129f8: ebf5c560 bl 0xffd83f80 + 129fc: 08002e9a stmeqda r0, {r1, r3, r4, r7, r9, sl, fp, sp} + 12a00: e28cc00b add ip, ip, #11 ; 0xb + 12a04: 0a000004 beq 0x12a1c + 12a08: e1a00fac mov r0, ip, lsr #31 + 12a0c: e08ff100 add pc, pc, r0, lsl #2 + 12a10: 08002e44 stmeqda r0, {r2, r6, r9, sl, fp, sp} + 12a14: ebf5c14e bl 0xffd82f54 + 12a18: ea00000f b 0x12a5c + 12a1c: ebf5c557 bl 0xffd83f80 + 12a20: 08002e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp, sp} + 12a24: ebf5c555 bl 0xffd83f80 + 12a28: 08002e9e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, fp, sp} + 12a2c: e3a000a1 mov r0, #161 ; 0xa1 + 12a30: e3800c2e orr r0, r0, #11776 ; 0x2e00 + 12a34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12a38: e58d0438 str r0, [sp, #1080] + 12a3c: e28cc006 add ip, ip, #6 ; 0x6 + 12a40: e1a00fac mov r0, ip, lsr #31 + 12a44: e08ff100 add pc, pc, r0, lsl #2 + 12a48: 08001448 stmeqda r0, {r3, r6, sl, ip} + 12a4c: ebf5c140 bl 0xffd82f54 + 12a50: eaffff06 b 0x12670 + 12a54: 08002e44 stmeqda r0, {r2, r6, r9, sl, fp, sp} + 12a58: 00000000 andeq r0, r0, r0 + 12a5c: ebf5c547 bl 0xffd83f80 + 12a60: 08002e44 stmeqda r0, {r2, r6, r9, sl, fp, sp} + 12a64: e2880004 add r0, r8, #4 ; 0x4 + 12a68: ebf5c3aa bl 0xffd83918 + 12a6c: 08002e48 stmeqda r0, {r3, r6, r9, sl, fp, sp} + 12a70: e1a07000 mov r7, r0 + 12a74: ebf5c541 bl 0xffd83f80 + 12a78: 08002e46 stmeqda r0, {r1, r2, r6, r9, sl, fp, sp} + 12a7c: e2870004 add r0, r7, #4 ; 0x4 + 12a80: ebf5c3a4 bl 0xffd83918 + 12a84: 08002e4a stmeqda r0, {r1, r3, r6, r9, sl, fp, sp} + 12a88: e1a03000 mov r3, r0 + 12a8c: ebf5c53b bl 0xffd83f80 + 12a90: 08002e48 stmeqda r0, {r3, r6, r9, sl, fp, sp} + 12a94: e1a01003 mov r1, r3 + 12a98: e2533001 subs r3, r3, #1 ; 0x1 + 12a9c: ebf5c537 bl 0xffd83f80 + 12aa0: 08002e4a stmeqda r0, {r1, r3, r6, r9, sl, fp, sp} + 12aa4: e2870004 add r0, r7, #4 ; 0x4 + 12aa8: e1a01003 mov r1, r3 + 12aac: ebf5c2c6 bl 0xffd835cc + 12ab0: 08002e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, sp} + 12ab4: ebf5c531 bl 0xffd83f80 + 12ab8: 08002e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, sp} + 12abc: e3530000 cmp r3, #0 ; 0x0 + 12ac0: ebf5c52e bl 0xffd83f80 + 12ac4: 08002e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp, sp} + 12ac8: e28cc017 add ip, ip, #23 ; 0x17 + 12acc: 0a000004 beq 0x12ae4 + 12ad0: e1a00fac mov r0, ip, lsr #31 + 12ad4: e08ff100 add pc, pc, r0, lsl #2 + 12ad8: 08002e96 stmeqda r0, {r1, r2, r4, r7, r9, sl, fp, sp} + 12adc: ebf5c11c bl 0xffd82f54 + 12ae0: eaffffbb b 0x129d4 + 12ae4: ebf5c525 bl 0xffd83f80 + 12ae8: 08002e50 stmeqda r0, {r4, r6, r9, sl, fp, sp} + 12aec: e3a00ee6 mov r0, #3680 ; 0xe60 + 12af0: e3800a02 orr r0, r0, #8192 ; 0x2000 + 12af4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12af8: ebf5c386 bl 0xffd83918 + 12afc: 08002e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, sp} + 12b00: e1a03000 mov r3, r0 + 12b04: ebf5c51d bl 0xffd83f80 + 12b08: 08002e52 stmeqda r0, {r1, r4, r6, r9, sl, fp, sp} + 12b0c: e1a01007 mov r1, r7 + 12b10: e2974000 adds r4, r7, #0 ; 0x0 + 12b14: ebf5c519 bl 0xffd83f80 + 12b18: 08002e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, sp} + 12b1c: ebf5c517 bl 0xffd83f80 + 12b20: 08002e56 stmeqda r0, {r1, r2, r4, r6, r9, sl, fp, sp} + 12b24: e3a00059 mov r0, #89 ; 0x59 + 12b28: e3800c2e orr r0, r0, #11776 ; 0x2e00 + 12b2c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12b30: e58d0438 str r0, [sp, #1080] + 12b34: e28cc00e add ip, ip, #14 ; 0xe + 12b38: e1a00fac mov r0, ip, lsr #31 + 12b3c: e08ff100 add pc, pc, r0, lsl #2 + 12b40: 08000ce4 stmeqda r0, {r2, r5, r6, r7, sl, fp} + 12b44: ebf5c102 bl 0xffd82f54 + 12b48: ea000001 b 0x12b54 + 12b4c: 08000ce4 stmeqda r0, {r2, r5, r6, r7, sl, fp} + 12b50: 00000000 andeq r0, r0, r0 + 12b54: ebf5c509 bl 0xffd83f80 + 12b58: 08000ce4 stmeqda r0, {r2, r5, r6, r7, sl, fp} + 12b5c: e1a01003 mov r1, r3 + 12b60: e2935000 adds r5, r3, #0 ; 0x0 + 12b64: ebf5c505 bl 0xffd83f80 + 12b68: 08000ce6 stmeqda r0, {r1, r2, r5, r6, r7, sl, fp} + 12b6c: e2850000 add r0, r5, #0 ; 0x0 + 12b70: ebf5c368 bl 0xffd83918 + 12b74: 08000cea stmeqda r0, {r1, r3, r5, r6, r7, sl, fp} + 12b78: e1a03000 mov r3, r0 + 12b7c: ebf5c4ff bl 0xffd83f80 + 12b80: 08000ce8 stmeqda r0, {r3, r5, r6, r7, sl, fp} + 12b84: e3530000 cmp r3, #0 ; 0x0 + 12b88: ebf5c4fc bl 0xffd83f80 + 12b8c: 08000cea stmeqda r0, {r1, r3, r5, r6, r7, sl, fp} + 12b90: e28cc00e add ip, ip, #14 ; 0xe + 12b94: 0a000004 beq 0x12bac + 12b98: e1a00fac mov r0, ip, lsr #31 + 12b9c: e08ff100 add pc, pc, r0, lsl #2 + 12ba0: 08000cfa stmeqda r0, {r1, r3, r4, r5, r6, r7, sl, fp} + 12ba4: ebf5c0ea bl 0xffd82f54 + 12ba8: ea000009 b 0x12bd4 + 12bac: ebf5c4f3 bl 0xffd83f80 + 12bb0: 08000cec stmeqda r0, {r2, r3, r5, r6, r7, sl, fp} + 12bb4: e28cc003 add ip, ip, #3 ; 0x3 + 12bb8: e1a00fac mov r0, ip, lsr #31 + 12bbc: e08ff100 add pc, pc, r0, lsl #2 + 12bc0: 08000d0c stmeqda r0, {r2, r3, r8, sl, fp} + 12bc4: ebf5c0e2 bl 0xffd82f54 + 12bc8: ea000065 b 0x12d64 + 12bcc: 08000cfa stmeqda r0, {r1, r3, r4, r5, r6, r7, sl, fp} + 12bd0: 00000000 andeq r0, r0, r0 + 12bd4: ebf5c4e9 bl 0xffd83f80 + 12bd8: 08000cfa stmeqda r0, {r1, r3, r4, r5, r6, r7, sl, fp} + 12bdc: e1a01005 mov r1, r5 + 12be0: e2956000 adds r6, r5, #0 ; 0x0 + 12be4: ebf5c4e5 bl 0xffd83f80 + 12be8: 08000cfc stmeqda r0, {r2, r3, r4, r5, r6, r7, sl, fp} + 12bec: e1a01003 mov r1, r3 + 12bf0: e2935000 adds r5, r3, #0 ; 0x0 + 12bf4: e28cc006 add ip, ip, #6 ; 0x6 + 12bf8: ebf5c4e0 bl 0xffd83f80 + 12bfc: 08000cfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, sl, fp} + 12c00: e2850004 add r0, r5, #4 ; 0x4 + 12c04: ebf5c343 bl 0xffd83918 + 12c08: 08000d02 stmeqda r0, {r1, r8, sl, fp} + 12c0c: e1a03000 mov r3, r0 + 12c10: ebf5c4da bl 0xffd83f80 + 12c14: 08000d00 stmeqda r0, {r8, sl, fp} + 12c18: e1530004 cmp r3, r4 + 12c1c: ebf5c4d7 bl 0xffd83f80 + 12c20: 08000d02 stmeqda r0, {r1, r8, sl, fp} + 12c24: e28cc00b add ip, ip, #11 ; 0xb + 12c28: 1a000004 bne 0x12c40 + 12c2c: e1a00fac mov r0, ip, lsr #31 + 12c30: e08ff100 add pc, pc, r0, lsl #2 + 12c34: 08000cee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, fp} + 12c38: ebf5c0c5 bl 0xffd82f54 + 12c3c: ea00001f b 0x12cc0 + 12c40: ebf5c4ce bl 0xffd83f80 + 12c44: 08000d04 stmeqda r0, {r2, r8, sl, fp} + 12c48: e1a01005 mov r1, r5 + 12c4c: e2956000 adds r6, r5, #0 ; 0x0 + 12c50: ebf5c4ca bl 0xffd83f80 + 12c54: 08000d06 stmeqda r0, {r1, r2, r8, sl, fp} + 12c58: e2850000 add r0, r5, #0 ; 0x0 + 12c5c: ebf5c32d bl 0xffd83918 + 12c60: 08000d0a stmeqda r0, {r1, r3, r8, sl, fp} + 12c64: e1a05000 mov r5, r0 + 12c68: ebf5c4c4 bl 0xffd83f80 + 12c6c: 08000d08 stmeqda r0, {r3, r8, sl, fp} + 12c70: e3550000 cmp r5, #0 ; 0x0 + 12c74: ebf5c4c1 bl 0xffd83f80 + 12c78: 08000d0a stmeqda r0, {r1, r3, r8, sl, fp} + 12c7c: e28cc00e add ip, ip, #14 ; 0xe + 12c80: 0a000004 beq 0x12c98 + 12c84: e1a00fac mov r0, ip, lsr #31 + 12c88: e08ff100 add pc, pc, r0, lsl #2 + 12c8c: 08000cfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, sl, fp} + 12c90: ebf5c0af bl 0xffd82f54 + 12c94: eaffffd7 b 0x12bf8 + 12c98: ebf5c4b8 bl 0xffd83f80 + 12c9c: 08000d0c stmeqda r0, {r2, r3, r8, sl, fp} + 12ca0: e3b03000 movs r3, #0 ; 0x0 + 12ca4: ebf5c4b5 bl 0xffd83f80 + 12ca8: 08000d0e stmeqda r0, {r1, r2, r3, r8, sl, fp} + 12cac: e59d0438 ldr r0, [sp, #1080] + 12cb0: e28cc006 add ip, ip, #6 ; 0x6 + 12cb4: eaf5c105 b 0xffd830d0 + 12cb8: 08000cee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, fp} + 12cbc: 00000000 andeq r0, r0, r0 + 12cc0: ebf5c4ae bl 0xffd83f80 + 12cc4: 08000cee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, fp} + 12cc8: e2850000 add r0, r5, #0 ; 0x0 + 12ccc: ebf5c311 bl 0xffd83918 + 12cd0: 08000cf2 stmeqda r0, {r1, r4, r5, r6, r7, sl, fp} + 12cd4: e1a03000 mov r3, r0 + 12cd8: ebf5c4a8 bl 0xffd83f80 + 12cdc: 08000cf0 stmeqda r0, {r4, r5, r6, r7, sl, fp} + 12ce0: e2860000 add r0, r6, #0 ; 0x0 + 12ce4: e1a01003 mov r1, r3 + 12ce8: ebf5c237 bl 0xffd835cc + 12cec: 08000cf2 stmeqda r0, {r1, r4, r5, r6, r7, sl, fp} + 12cf0: ebf5c4a2 bl 0xffd83f80 + 12cf4: 08000cf2 stmeqda r0, {r1, r4, r5, r6, r7, sl, fp} + 12cf8: e3b03000 movs r3, #0 ; 0x0 + 12cfc: ebf5c49f bl 0xffd83f80 + 12d00: 08000cf4 stmeqda r0, {r2, r4, r5, r6, r7, sl, fp} + 12d04: e2850004 add r0, r5, #4 ; 0x4 + 12d08: e1a01003 mov r1, r3 + 12d0c: ebf5c22e bl 0xffd835cc + 12d10: 08000cf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, sl, fp} + 12d14: ebf5c499 bl 0xffd83f80 + 12d18: 08000cf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, sl, fp} + 12d1c: e3b03001 movs r3, #1 ; 0x1 + 12d20: ebf5c496 bl 0xffd83f80 + 12d24: 08000cf8 stmeqda r0, {r3, r4, r5, r6, r7, sl, fp} + 12d28: e28cc016 add ip, ip, #22 ; 0x16 + 12d2c: e1a00fac mov r0, ip, lsr #31 + 12d30: e08ff100 add pc, pc, r0, lsl #2 + 12d34: 08000d0e stmeqda r0, {r1, r2, r3, r8, sl, fp} + 12d38: ebf5c085 bl 0xffd82f54 + 12d3c: ea000001 b 0x12d48 + 12d40: 08000d0e stmeqda r0, {r1, r2, r3, r8, sl, fp} + 12d44: 00000000 andeq r0, r0, r0 + 12d48: ebf5c48c bl 0xffd83f80 + 12d4c: 08000d0e stmeqda r0, {r1, r2, r3, r8, sl, fp} + 12d50: e59d0438 ldr r0, [sp, #1080] + 12d54: e28cc003 add ip, ip, #3 ; 0x3 + 12d58: eaf5c0dc b 0xffd830d0 + 12d5c: 08000d0c stmeqda r0, {r2, r3, r8, sl, fp} + 12d60: 00000000 andeq r0, r0, r0 + 12d64: ebf5c485 bl 0xffd83f80 + 12d68: 08000d0c stmeqda r0, {r2, r3, r8, sl, fp} + 12d6c: e3b03000 movs r3, #0 ; 0x0 + 12d70: ebf5c482 bl 0xffd83f80 + 12d74: 08000d0e stmeqda r0, {r1, r2, r3, r8, sl, fp} + 12d78: e59d0438 ldr r0, [sp, #1080] + 12d7c: e28cc006 add ip, ip, #6 ; 0x6 + 12d80: eaf5c0d2 b 0xffd830d0 + 12d84: 08002ea0 stmeqda r0, {r5, r7, r9, sl, fp, sp} + 12d88: 00000000 andeq r0, r0, r0 + 12d8c: ebf5c47b bl 0xffd83f80 + 12d90: 08002ea0 stmeqda r0, {r5, r7, r9, sl, fp, sp} + 12d94: e59d9434 ldr r9, [sp, #1076] + 12d98: e3c99003 bic r9, r9, #3 ; 0x3 + 12d9c: e2890008 add r0, r9, #8 ; 0x8 + 12da0: e58d0434 str r0, [sp, #1076] + 12da4: e2890000 add r0, r9, #0 ; 0x0 + 12da8: ebf5c2da bl 0xffd83918 + 12dac: 08002ea4 stmeqda r0, {r2, r5, r7, r9, sl, fp, sp} + 12db0: e1a07000 mov r7, r0 + 12db4: e2890004 add r0, r9, #4 ; 0x4 + 12db8: ebf5c2d6 bl 0xffd83918 + 12dbc: 08002ea4 stmeqda r0, {r2, r5, r7, r9, sl, fp, sp} + 12dc0: e1a08000 mov r8, r0 + 12dc4: ebf5c46d bl 0xffd83f80 + 12dc8: 08002ea2 stmeqda r0, {r1, r5, r7, r9, sl, fp, sp} + 12dcc: e59d9434 ldr r9, [sp, #1076] + 12dd0: e3c99003 bic r9, r9, #3 ; 0x3 + 12dd4: e2890004 add r0, r9, #4 ; 0x4 + 12dd8: e58d0434 str r0, [sp, #1076] + 12ddc: e2890000 add r0, r9, #0 ; 0x0 + 12de0: ebf5c2cc bl 0xffd83918 + 12de4: 08002ea6 stmeqda r0, {r1, r2, r5, r7, r9, sl, fp, sp} + 12de8: e1a03000 mov r3, r0 + 12dec: ebf5c463 bl 0xffd83f80 + 12df0: 08002ea4 stmeqda r0, {r2, r5, r7, r9, sl, fp, sp} + 12df4: e1a00003 mov r0, r3 + 12df8: e28cc00c add ip, ip, #12 ; 0xc + 12dfc: eaf5c0b3 b 0xffd830d0 + 12e00: 08002c7c stmeqda r0, {r2, r3, r4, r5, r6, sl, fp, sp} + 12e04: 00000000 andeq r0, r0, r0 + 12e08: ebf5c45c bl 0xffd83f80 + 12e0c: 08002c7c stmeqda r0, {r2, r3, r4, r5, r6, sl, fp, sp} + 12e10: e287004c add r0, r7, #76 ; 0x4c + 12e14: ebf5c2bf bl 0xffd83918 + 12e18: 08002c80 stmeqda r0, {r7, sl, fp, sp} + 12e1c: e1a03000 mov r3, r0 + 12e20: ebf5c456 bl 0xffd83f80 + 12e24: 08002c7e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, fp, sp} + 12e28: ebf5c454 bl 0xffd83f80 + 12e2c: 08002c80 stmeqda r0, {r7, sl, fp, sp} + 12e30: e3a00083 mov r0, #131 ; 0x83 + 12e34: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 12e38: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12e3c: e58d0438 str r0, [sp, #1080] + 12e40: e28cc00b add ip, ip, #11 ; 0xb + 12e44: e1a00fac mov r0, ip, lsr #31 + 12e48: e08ff100 add pc, pc, r0, lsl #2 + 12e4c: 08001738 stmeqda r0, {r3, r4, r5, r8, r9, sl, ip} + 12e50: ebf5c03f bl 0xffd82f54 + 12e54: ea000001 b 0x12e60 + 12e58: 08001738 stmeqda r0, {r3, r4, r5, r8, r9, sl, ip} + 12e5c: 00000000 andeq r0, r0, r0 + 12e60: ebf5c446 bl 0xffd83f80 + 12e64: 08001738 stmeqda r0, {r3, r4, r5, r8, r9, sl, ip} + 12e68: e59d9434 ldr r9, [sp, #1076] + 12e6c: e3c99003 bic r9, r9, #3 ; 0x3 + 12e70: e249900c sub r9, r9, #12 ; 0xc + 12e74: e58d9434 str r9, [sp, #1076] + 12e78: e2890000 add r0, r9, #0 ; 0x0 + 12e7c: e1a01007 mov r1, r7 + 12e80: ebf5c1f1 bl 0xffd8364c + 12e84: e2890004 add r0, r9, #4 ; 0x4 + 12e88: e1a01008 mov r1, r8 + 12e8c: ebf5c1ee bl 0xffd8364c + 12e90: e2890008 add r0, r9, #8 ; 0x8 + 12e94: e59d1438 ldr r1, [sp, #1080] + 12e98: ebf5c1eb bl 0xffd8364c + 12e9c: ebf5c437 bl 0xffd83f80 + 12ea0: 0800173a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, ip} + 12ea4: e1a01003 mov r1, r3 + 12ea8: e2937000 adds r7, r3, #0 ; 0x0 + 12eac: ebf5c433 bl 0xffd83f80 + 12eb0: 0800173c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, ip} + 12eb4: e1a01007 mov r1, r7 + 12eb8: e2978000 adds r8, r7, #0 ; 0x0 + 12ebc: ebf5c42f bl 0xffd83f80 + 12ec0: 0800173e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, ip} + 12ec4: e28cc00e add ip, ip, #14 ; 0xe + 12ec8: e1a00fac mov r0, ip, lsr #31 + 12ecc: e08ff100 add pc, pc, r0, lsl #2 + 12ed0: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 12ed4: ebf5c01e bl 0xffd82f54 + 12ed8: ea000001 b 0x12ee4 + 12edc: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 12ee0: 00000000 andeq r0, r0, r0 + 12ee4: ebf5c425 bl 0xffd83f80 + 12ee8: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 12eec: e3b04000 movs r4, #0 ; 0x0 + 12ef0: ebf5c422 bl 0xffd83f80 + 12ef4: 08001744 stmeqda r0, {r2, r6, r8, r9, sl, ip} + 12ef8: e0870004 add r0, r7, r4 + 12efc: ebf5c26e bl 0xffd838bc + 12f00: 08001748 stmeqda r0, {r3, r6, r8, r9, sl, ip} + 12f04: e1a03000 mov r3, r0 + 12f08: ebf5c41c bl 0xffd83f80 + 12f0c: 08001746 stmeqda r0, {r1, r2, r6, r8, r9, sl, ip} + 12f10: e3530000 cmp r3, #0 ; 0x0 + 12f14: ebf5c419 bl 0xffd83f80 + 12f18: 08001748 stmeqda r0, {r3, r6, r8, r9, sl, ip} + 12f1c: e28cc00e add ip, ip, #14 ; 0xe + 12f20: ca000004 bgt 0x12f38 + 12f24: e1a00fac mov r0, ip, lsr #31 + 12f28: e08ff100 add pc, pc, r0, lsl #2 + 12f2c: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 12f30: ebf5c007 bl 0xffd82f54 + 12f34: ea000011 b 0x12f80 + 12f38: ebf5c410 bl 0xffd83f80 + 12f3c: 0800174a stmeqda r0, {r1, r3, r6, r8, r9, sl, ip} + 12f40: e1a01007 mov r1, r7 + 12f44: e2973000 adds r3, r7, #0 ; 0x0 + 12f48: ebf5c40c bl 0xffd83f80 + 12f4c: 0800174c stmeqda r0, {r2, r3, r6, r8, r9, sl, ip} + 12f50: ebf5c40a bl 0xffd83f80 + 12f54: 0800174e stmeqda r0, {r1, r2, r3, r6, r8, r9, sl, ip} + 12f58: e3a00051 mov r0, #81 ; 0x51 + 12f5c: e3800c17 orr r0, r0, #5888 ; 0x1700 + 12f60: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 12f64: e58d0438 str r0, [sp, #1080] + 12f68: e28cc009 add ip, ip, #9 ; 0x9 + 12f6c: e1a00fac mov r0, ip, lsr #31 + 12f70: e08ff100 add pc, pc, r0, lsl #2 + 12f74: 080016f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip} + 12f78: ebf5bff5 bl 0xffd82f54 + 12f7c: eafffb63 b 0x11d10 + 12f80: ebf5c3fe bl 0xffd83f80 + 12f84: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 12f88: e2870030 add r0, r7, #48 ; 0x30 + 12f8c: ebf5c261 bl 0xffd83918 + 12f90: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 12f94: e1a03000 mov r3, r0 + 12f98: ebf5c3f8 bl 0xffd83f80 + 12f9c: 08001752 stmeqda r0, {r1, r4, r6, r8, r9, sl, ip} + 12fa0: e3530000 cmp r3, #0 ; 0x0 + 12fa4: ebf5c3f5 bl 0xffd83f80 + 12fa8: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 12fac: e28cc00b add ip, ip, #11 ; 0xb + 12fb0: 0a000004 beq 0x12fc8 + 12fb4: e1a00fac mov r0, ip, lsr #31 + 12fb8: e08ff100 add pc, pc, r0, lsl #2 + 12fbc: 08001740 stmeqda r0, {r6, r8, r9, sl, ip} + 12fc0: ebf5bfe3 bl 0xffd82f54 + 12fc4: ea000009 b 0x12ff0 + 12fc8: ebf5c3ec bl 0xffd83f80 + 12fcc: 08001756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, ip} + 12fd0: e28cc003 add ip, ip, #3 ; 0x3 + 12fd4: e1a00fac mov r0, ip, lsr #31 + 12fd8: e08ff100 add pc, pc, r0, lsl #2 + 12fdc: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 12fe0: ebf5bfdb bl 0xffd82f54 + 12fe4: ea00004a b 0x13114 + 12fe8: 08001740 stmeqda r0, {r6, r8, r9, sl, ip} + 12fec: 00000000 andeq r0, r0, r0 + 12ff0: ebf5c3e2 bl 0xffd83f80 + 12ff4: 08001740 stmeqda r0, {r6, r8, r9, sl, ip} + 12ff8: e2870030 add r0, r7, #48 ; 0x30 + 12ffc: ebf5c245 bl 0xffd83918 + 13000: 08001744 stmeqda r0, {r2, r6, r8, r9, sl, ip} + 13004: e1a07000 mov r7, r0 + 13008: ebf5c3dc bl 0xffd83f80 + 1300c: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 13010: e3b04000 movs r4, #0 ; 0x0 + 13014: ebf5c3d9 bl 0xffd83f80 + 13018: 08001744 stmeqda r0, {r2, r6, r8, r9, sl, ip} + 1301c: e0870004 add r0, r7, r4 + 13020: ebf5c225 bl 0xffd838bc + 13024: 08001748 stmeqda r0, {r3, r6, r8, r9, sl, ip} + 13028: e1a03000 mov r3, r0 + 1302c: ebf5c3d3 bl 0xffd83f80 + 13030: 08001746 stmeqda r0, {r1, r2, r6, r8, r9, sl, ip} + 13034: e3530000 cmp r3, #0 ; 0x0 + 13038: ebf5c3d0 bl 0xffd83f80 + 1303c: 08001748 stmeqda r0, {r3, r6, r8, r9, sl, ip} + 13040: e28cc013 add ip, ip, #19 ; 0x13 + 13044: ca000004 bgt 0x1305c + 13048: e1a00fac mov r0, ip, lsr #31 + 1304c: e08ff100 add pc, pc, r0, lsl #2 + 13050: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 13054: ebf5bfbe bl 0xffd82f54 + 13058: ea000011 b 0x130a4 + 1305c: ebf5c3c7 bl 0xffd83f80 + 13060: 0800174a stmeqda r0, {r1, r3, r6, r8, r9, sl, ip} + 13064: e1a01007 mov r1, r7 + 13068: e2973000 adds r3, r7, #0 ; 0x0 + 1306c: ebf5c3c3 bl 0xffd83f80 + 13070: 0800174c stmeqda r0, {r2, r3, r6, r8, r9, sl, ip} + 13074: ebf5c3c1 bl 0xffd83f80 + 13078: 0800174e stmeqda r0, {r1, r2, r3, r6, r8, r9, sl, ip} + 1307c: e3a00051 mov r0, #81 ; 0x51 + 13080: e3800c17 orr r0, r0, #5888 ; 0x1700 + 13084: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13088: e58d0438 str r0, [sp, #1080] + 1308c: e28cc009 add ip, ip, #9 ; 0x9 + 13090: e1a00fac mov r0, ip, lsr #31 + 13094: e08ff100 add pc, pc, r0, lsl #2 + 13098: 080016f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, ip} + 1309c: ebf5bfac bl 0xffd82f54 + 130a0: eafffb1a b 0x11d10 + 130a4: ebf5c3b5 bl 0xffd83f80 + 130a8: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 130ac: e2870030 add r0, r7, #48 ; 0x30 + 130b0: ebf5c218 bl 0xffd83918 + 130b4: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 130b8: e1a03000 mov r3, r0 + 130bc: ebf5c3af bl 0xffd83f80 + 130c0: 08001752 stmeqda r0, {r1, r4, r6, r8, r9, sl, ip} + 130c4: e3530000 cmp r3, #0 ; 0x0 + 130c8: ebf5c3ac bl 0xffd83f80 + 130cc: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 130d0: e28cc00b add ip, ip, #11 ; 0xb + 130d4: 0a000004 beq 0x130ec + 130d8: e1a00fac mov r0, ip, lsr #31 + 130dc: e08ff100 add pc, pc, r0, lsl #2 + 130e0: 08001740 stmeqda r0, {r6, r8, r9, sl, ip} + 130e4: ebf5bf9a bl 0xffd82f54 + 130e8: eaffffc0 b 0x12ff0 + 130ec: ebf5c3a3 bl 0xffd83f80 + 130f0: 08001756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, ip} + 130f4: e28cc003 add ip, ip, #3 ; 0x3 + 130f8: e1a00fac mov r0, ip, lsr #31 + 130fc: e08ff100 add pc, pc, r0, lsl #2 + 13100: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 13104: ebf5bf92 bl 0xffd82f54 + 13108: ea000001 b 0x13114 + 1310c: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 13110: 00000000 andeq r0, r0, r0 + 13114: ebf5c399 bl 0xffd83f80 + 13118: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 1311c: e1570008 cmp r7, r8 + 13120: ebf5c396 bl 0xffd83f80 + 13124: 08001762 stmeqda r0, {r1, r5, r6, r8, r9, sl, ip} + 13128: e28cc006 add ip, ip, #6 ; 0x6 + 1312c: 1a000004 bne 0x13144 + 13130: e1a00fac mov r0, ip, lsr #31 + 13134: e08ff100 add pc, pc, r0, lsl #2 + 13138: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 1313c: ebf5bf84 bl 0xffd82f54 + 13140: ea00001f b 0x131c4 + 13144: ebf5c38d bl 0xffd83f80 + 13148: 08001764 stmeqda r0, {r2, r5, r6, r8, r9, sl, ip} + 1314c: e287002c add r0, r7, #44 ; 0x2c + 13150: ebf5c1f0 bl 0xffd83918 + 13154: 08001768 stmeqda r0, {r3, r5, r6, r8, r9, sl, ip} + 13158: e1a03000 mov r3, r0 + 1315c: ebf5c387 bl 0xffd83f80 + 13160: 08001766 stmeqda r0, {r1, r2, r5, r6, r8, r9, sl, ip} + 13164: e3530000 cmp r3, #0 ; 0x0 + 13168: ebf5c384 bl 0xffd83f80 + 1316c: 08001768 stmeqda r0, {r3, r5, r6, r8, r9, sl, ip} + 13170: e28cc00b add ip, ip, #11 ; 0xb + 13174: 1a000004 bne 0x1318c + 13178: e1a00fac mov r0, ip, lsr #31 + 1317c: e08ff100 add pc, pc, r0, lsl #2 + 13180: 08001758 stmeqda r0, {r3, r4, r6, r8, r9, sl, ip} + 13184: ebf5bf72 bl 0xffd82f54 + 13188: ea00002c b 0x13240 + 1318c: ebf5c37b bl 0xffd83f80 + 13190: 0800176a stmeqda r0, {r1, r3, r5, r6, r8, r9, sl, ip} + 13194: e287002c add r0, r7, #44 ; 0x2c + 13198: ebf5c1de bl 0xffd83918 + 1319c: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 131a0: e1a07000 mov r7, r0 + 131a4: ebf5c375 bl 0xffd83f80 + 131a8: 0800176c stmeqda r0, {r2, r3, r5, r6, r8, r9, sl, ip} + 131ac: e28cc008 add ip, ip, #8 ; 0x8 + 131b0: e1a00fac mov r0, ip, lsr #31 + 131b4: e08ff100 add pc, pc, r0, lsl #2 + 131b8: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 131bc: ebf5bf64 bl 0xffd82f54 + 131c0: eaffff47 b 0x12ee4 + 131c4: ebf5c36d bl 0xffd83f80 + 131c8: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 131cc: e59d9434 ldr r9, [sp, #1076] + 131d0: e3c99003 bic r9, r9, #3 ; 0x3 + 131d4: e2890008 add r0, r9, #8 ; 0x8 + 131d8: e58d0434 str r0, [sp, #1076] + 131dc: e2890000 add r0, r9, #0 ; 0x0 + 131e0: ebf5c1cc bl 0xffd83918 + 131e4: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 131e8: e1a07000 mov r7, r0 + 131ec: e2890004 add r0, r9, #4 ; 0x4 + 131f0: ebf5c1c8 bl 0xffd83918 + 131f4: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 131f8: e1a08000 mov r8, r0 + 131fc: ebf5c35f bl 0xffd83f80 + 13200: 08001770 stmeqda r0, {r4, r5, r6, r8, r9, sl, ip} + 13204: e59d9434 ldr r9, [sp, #1076] + 13208: e3c99003 bic r9, r9, #3 ; 0x3 + 1320c: e2890004 add r0, r9, #4 ; 0x4 + 13210: e58d0434 str r0, [sp, #1076] + 13214: e2890000 add r0, r9, #0 ; 0x0 + 13218: ebf5c1be bl 0xffd83918 + 1321c: 08001774 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl, ip} + 13220: e1a03000 mov r3, r0 + 13224: ebf5c355 bl 0xffd83f80 + 13228: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 1322c: e1a00003 mov r0, r3 + 13230: e28cc00c add ip, ip, #12 ; 0xc + 13234: eaf5bfa5 b 0xffd830d0 + 13238: 08001758 stmeqda r0, {r3, r4, r6, r8, r9, sl, ip} + 1323c: 00000000 andeq r0, r0, r0 + 13240: ebf5c34e bl 0xffd83f80 + 13244: 08001758 stmeqda r0, {r3, r4, r6, r8, r9, sl, ip} + 13248: e2870028 add r0, r7, #40 ; 0x28 + 1324c: ebf5c1b1 bl 0xffd83918 + 13250: 0800175c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl, ip} + 13254: e1a03000 mov r3, r0 + 13258: ebf5c348 bl 0xffd83f80 + 1325c: 0800175a stmeqda r0, {r1, r3, r4, r6, r8, r9, sl, ip} + 13260: e3530000 cmp r3, #0 ; 0x0 + 13264: ebf5c345 bl 0xffd83f80 + 13268: 0800175c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl, ip} + 1326c: e28cc00b add ip, ip, #11 ; 0xb + 13270: 1a000004 bne 0x13288 + 13274: e1a00fac mov r0, ip, lsr #31 + 13278: e08ff100 add pc, pc, r0, lsl #2 + 1327c: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 13280: ebf5bf33 bl 0xffd82f54 + 13284: ea00002f b 0x13348 + 13288: ebf5c33c bl 0xffd83f80 + 1328c: 0800175e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, sl, ip} + 13290: e1a01003 mov r1, r3 + 13294: e2937000 adds r7, r3, #0 ; 0x0 + 13298: ebf5c338 bl 0xffd83f80 + 1329c: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 132a0: e1570008 cmp r7, r8 + 132a4: ebf5c335 bl 0xffd83f80 + 132a8: 08001762 stmeqda r0, {r1, r5, r6, r8, r9, sl, ip} + 132ac: e28cc009 add ip, ip, #9 ; 0x9 + 132b0: 1a000004 bne 0x132c8 + 132b4: e1a00fac mov r0, ip, lsr #31 + 132b8: e08ff100 add pc, pc, r0, lsl #2 + 132bc: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 132c0: ebf5bf23 bl 0xffd82f54 + 132c4: ea00001f b 0x13348 + 132c8: ebf5c32c bl 0xffd83f80 + 132cc: 08001764 stmeqda r0, {r2, r5, r6, r8, r9, sl, ip} + 132d0: e287002c add r0, r7, #44 ; 0x2c + 132d4: ebf5c18f bl 0xffd83918 + 132d8: 08001768 stmeqda r0, {r3, r5, r6, r8, r9, sl, ip} + 132dc: e1a03000 mov r3, r0 + 132e0: ebf5c326 bl 0xffd83f80 + 132e4: 08001766 stmeqda r0, {r1, r2, r5, r6, r8, r9, sl, ip} + 132e8: e3530000 cmp r3, #0 ; 0x0 + 132ec: ebf5c323 bl 0xffd83f80 + 132f0: 08001768 stmeqda r0, {r3, r5, r6, r8, r9, sl, ip} + 132f4: e28cc00b add ip, ip, #11 ; 0xb + 132f8: 1a000004 bne 0x13310 + 132fc: e1a00fac mov r0, ip, lsr #31 + 13300: e08ff100 add pc, pc, r0, lsl #2 + 13304: 08001758 stmeqda r0, {r3, r4, r6, r8, r9, sl, ip} + 13308: ebf5bf11 bl 0xffd82f54 + 1330c: eaffffcb b 0x13240 + 13310: ebf5c31a bl 0xffd83f80 + 13314: 0800176a stmeqda r0, {r1, r3, r5, r6, r8, r9, sl, ip} + 13318: e287002c add r0, r7, #44 ; 0x2c + 1331c: ebf5c17d bl 0xffd83918 + 13320: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 13324: e1a07000 mov r7, r0 + 13328: ebf5c314 bl 0xffd83f80 + 1332c: 0800176c stmeqda r0, {r2, r3, r5, r6, r8, r9, sl, ip} + 13330: e28cc008 add ip, ip, #8 ; 0x8 + 13334: e1a00fac mov r0, ip, lsr #31 + 13338: e08ff100 add pc, pc, r0, lsl #2 + 1333c: 08001742 stmeqda r0, {r1, r6, r8, r9, sl, ip} + 13340: ebf5bf03 bl 0xffd82f54 + 13344: eafffee6 b 0x12ee4 + 13348: ebf5c30c bl 0xffd83f80 + 1334c: 0800176e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, ip} + 13350: e59d9434 ldr r9, [sp, #1076] + 13354: e3c99003 bic r9, r9, #3 ; 0x3 + 13358: e2890008 add r0, r9, #8 ; 0x8 + 1335c: e58d0434 str r0, [sp, #1076] + 13360: e2890000 add r0, r9, #0 ; 0x0 + 13364: ebf5c16b bl 0xffd83918 + 13368: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 1336c: e1a07000 mov r7, r0 + 13370: e2890004 add r0, r9, #4 ; 0x4 + 13374: ebf5c167 bl 0xffd83918 + 13378: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 1337c: e1a08000 mov r8, r0 + 13380: ebf5c2fe bl 0xffd83f80 + 13384: 08001770 stmeqda r0, {r4, r5, r6, r8, r9, sl, ip} + 13388: e59d9434 ldr r9, [sp, #1076] + 1338c: e3c99003 bic r9, r9, #3 ; 0x3 + 13390: e2890004 add r0, r9, #4 ; 0x4 + 13394: e58d0434 str r0, [sp, #1076] + 13398: e2890000 add r0, r9, #0 ; 0x0 + 1339c: ebf5c15d bl 0xffd83918 + 133a0: 08001774 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl, ip} + 133a4: e1a03000 mov r3, r0 + 133a8: ebf5c2f4 bl 0xffd83f80 + 133ac: 08001772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, ip} + 133b0: e1a00003 mov r0, r3 + 133b4: e28cc00c add ip, ip, #12 ; 0xc + 133b8: eaf5bf44 b 0xffd830d0 + 133bc: 080104c0 stmeqda r1, {r6, r7, sl} + 133c0: 00000000 andeq r0, r0, r0 + 133c4: ebf5c2ed bl 0xffd83f80 + 133c8: 080104c0 stmeqda r1, {r6, r7, sl} + 133cc: e59d9434 ldr r9, [sp, #1076] + 133d0: e3c99003 bic r9, r9, #3 ; 0x3 + 133d4: e2499008 sub r9, r9, #8 ; 0x8 + 133d8: e58d9434 str r9, [sp, #1076] + 133dc: e2890000 add r0, r9, #0 ; 0x0 + 133e0: e1a01007 mov r1, r7 + 133e4: ebf5c098 bl 0xffd8364c + 133e8: e2890004 add r0, r9, #4 ; 0x4 + 133ec: e59d1438 ldr r1, [sp, #1080] + 133f0: ebf5c095 bl 0xffd8364c + 133f4: ebf5c2e1 bl 0xffd83f80 + 133f8: 080104c2 stmeqda r1, {r1, r6, r7, sl} + 133fc: e1a01003 mov r1, r3 + 13400: e2937000 adds r7, r3, #0 ; 0x0 + 13404: ebf5c2dd bl 0xffd83f80 + 13408: 080104c4 stmeqda r1, {r2, r6, r7, sl} + 1340c: e3a00f41 mov r0, #260 ; 0x104 + 13410: e3800b41 orr r0, r0, #66560 ; 0x10400 + 13414: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13418: ebf5c13e bl 0xffd83918 + 1341c: 080104c8 stmeqda r1, {r3, r6, r7, sl} + 13420: e1a03000 mov r3, r0 + 13424: ebf5c2d5 bl 0xffd83f80 + 13428: 080104c6 stmeqda r1, {r1, r2, r6, r7, sl} + 1342c: e2870014 add r0, r7, #20 ; 0x14 + 13430: e1a01003 mov r1, r3 + 13434: ebf5c064 bl 0xffd835cc + 13438: 080104c8 stmeqda r1, {r3, r6, r7, sl} + 1343c: ebf5c2cf bl 0xffd83f80 + 13440: 080104c8 stmeqda r1, {r3, r6, r7, sl} + 13444: e2870022 add r0, r7, #34 ; 0x22 + 13448: ebf5c106 bl 0xffd83868 + 1344c: 080104cc stmeqda r1, {r2, r3, r6, r7, sl} + 13450: e1a03000 mov r3, r0 + 13454: ebf5c2c9 bl 0xffd83f80 + 13458: 080104ca stmeqda r1, {r1, r3, r6, r7, sl} + 1345c: e1a01003 mov r1, r3 + 13460: e2933001 adds r3, r3, #1 ; 0x1 + 13464: ebf5c2c5 bl 0xffd83f80 + 13468: 080104cc stmeqda r1, {r2, r3, r6, r7, sl} + 1346c: e2870022 add r0, r7, #34 ; 0x22 + 13470: e1a01003 mov r1, r3 + 13474: ebf5c034 bl 0xffd8354c + 13478: 080104ce stmeqda r1, {r1, r2, r3, r6, r7, sl} + 1347c: ebf5c2bf bl 0xffd83f80 + 13480: 080104ce stmeqda r1, {r1, r2, r3, r6, r7, sl} + 13484: e3b03022 movs r3, #34 ; 0x22 + 13488: ebf5c2bc bl 0xffd83f80 + 1348c: 080104d0 stmeqda r1, {r4, r6, r7, sl} + 13490: e0870003 add r0, r7, r3 + 13494: ebf5c108 bl 0xffd838bc + 13498: 080104d4 stmeqda r1, {r2, r4, r6, r7, sl} + 1349c: e1a04000 mov r4, r0 + 134a0: ebf5c2b6 bl 0xffd83f80 + 134a4: 080104d2 stmeqda r1, {r1, r4, r6, r7, sl} + 134a8: e1b04084 movs r4, r4, lsl #1 + 134ac: ebf5c2b3 bl 0xffd83f80 + 134b0: 080104d4 stmeqda r1, {r2, r4, r6, r7, sl} + 134b4: e1a01004 mov r1, r4 + 134b8: e0944007 adds r4, r4, r7 + 134bc: ebf5c2af bl 0xffd83f80 + 134c0: 080104d6 stmeqda r1, {r1, r2, r4, r6, r7, sl} + 134c4: e2840019 add r0, r4, #25 ; 0x19 + 134c8: ebf5c0bb bl 0xffd837bc + 134cc: 080104da stmeqda r1, {r1, r3, r4, r6, r7, sl} + 134d0: e1a03000 mov r3, r0 + 134d4: ebf5c2a9 bl 0xffd83f80 + 134d8: 080104d8 stmeqda r1, {r3, r4, r6, r7, sl} + 134dc: e1a01003 mov r1, r3 + 134e0: e2933001 adds r3, r3, #1 ; 0x1 + 134e4: ebf5c2a5 bl 0xffd83f80 + 134e8: 080104da stmeqda r1, {r1, r3, r4, r6, r7, sl} + 134ec: e2840019 add r0, r4, #25 ; 0x19 + 134f0: e1a01003 mov r1, r3 + 134f4: ebf5bff5 bl 0xffd834d0 + 134f8: 080104dc stmeqda r1, {r2, r3, r4, r6, r7, sl} + 134fc: ebf5c29f bl 0xffd83f80 + 13500: 080104dc stmeqda r1, {r2, r3, r4, r6, r7, sl} + 13504: e3b03022 movs r3, #34 ; 0x22 + 13508: ebf5c29c bl 0xffd83f80 + 1350c: 080104de stmeqda r1, {r1, r2, r3, r4, r6, r7, sl} + 13510: e0870003 add r0, r7, r3 + 13514: ebf5c0e8 bl 0xffd838bc + 13518: 080104e2 stmeqda r1, {r1, r5, r6, r7, sl} + 1351c: e1a04000 mov r4, r0 + 13520: ebf5c296 bl 0xffd83f80 + 13524: 080104e0 stmeqda r1, {r5, r6, r7, sl} + 13528: e1b04084 movs r4, r4, lsl #1 + 1352c: ebf5c293 bl 0xffd83f80 + 13530: 080104e2 stmeqda r1, {r1, r5, r6, r7, sl} + 13534: e1a01007 mov r1, r7 + 13538: e2973000 adds r3, r7, #0 ; 0x0 + 1353c: ebf5c28f bl 0xffd83f80 + 13540: 080104e4 stmeqda r1, {r2, r5, r6, r7, sl} + 13544: e1a01003 mov r1, r3 + 13548: e2933018 adds r3, r3, #24 ; 0x18 + 1354c: ebf5c28b bl 0xffd83f80 + 13550: 080104e6 stmeqda r1, {r1, r2, r5, r6, r7, sl} + 13554: e1a01003 mov r1, r3 + 13558: e0933004 adds r3, r3, r4 + 1355c: ebf5c287 bl 0xffd83f80 + 13560: 080104e8 stmeqda r1, {r3, r5, r6, r7, sl} + 13564: e2830000 add r0, r3, #0 ; 0x0 + 13568: ebf5c093 bl 0xffd837bc + 1356c: 080104ec stmeqda r1, {r2, r3, r5, r6, r7, sl} + 13570: e1a03000 mov r3, r0 + 13574: ebf5c281 bl 0xffd83f80 + 13578: 080104ea stmeqda r1, {r1, r3, r5, r6, r7, sl} + 1357c: e2870014 add r0, r7, #20 ; 0x14 + 13580: ebf5c0e4 bl 0xffd83918 + 13584: 080104ee stmeqda r1, {r1, r2, r3, r5, r6, r7, sl} + 13588: e1a04000 mov r4, r0 + 1358c: ebf5c27b bl 0xffd83f80 + 13590: 080104ec stmeqda r1, {r2, r3, r5, r6, r7, sl} + 13594: e1b03103 movs r3, r3, lsl #2 + 13598: ebf5c278 bl 0xffd83f80 + 1359c: 080104ee stmeqda r1, {r1, r2, r3, r5, r6, r7, sl} + 135a0: e1a01003 mov r1, r3 + 135a4: e0933004 adds r3, r3, r4 + 135a8: ebf5c274 bl 0xffd83f80 + 135ac: 080104f0 stmeqda r1, {r4, r5, r6, r7, sl} + 135b0: e2830000 add r0, r3, #0 ; 0x0 + 135b4: ebf5c0d7 bl 0xffd83918 + 135b8: 080104f4 stmeqda r1, {r2, r4, r5, r6, r7, sl} + 135bc: e1a04000 mov r4, r0 + 135c0: ebf5c26e bl 0xffd83f80 + 135c4: 080104f2 stmeqda r1, {r1, r4, r5, r6, r7, sl} + 135c8: e1a01007 mov r1, r7 + 135cc: e2973000 adds r3, r7, #0 ; 0x0 + 135d0: ebf5c26a bl 0xffd83f80 + 135d4: 080104f4 stmeqda r1, {r2, r4, r5, r6, r7, sl} + 135d8: ebf5c268 bl 0xffd83f80 + 135dc: 080104f6 stmeqda r1, {r1, r2, r4, r5, r6, r7, sl} + 135e0: e3a000f9 mov r0, #249 ; 0xf9 + 135e4: e3800b41 orr r0, r0, #66560 ; 0x10400 + 135e8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 135ec: e58d0438 str r0, [sp, #1080] + 135f0: e28cc068 add ip, ip, #104 ; 0x68 + 135f4: e1a00fac mov r0, ip, lsr #31 + 135f8: e08ff100 add pc, pc, r0, lsl #2 + 135fc: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 13600: ebf5be53 bl 0xffd82f54 + 13604: eaffc620 b 0x4e8c + 13608: 08010508 stmeqda r1, {r3, r8, sl} + 1360c: 00000000 andeq r0, r0, r0 + 13610: ebf5c25a bl 0xffd83f80 + 13614: 08010508 stmeqda r1, {r3, r8, sl} + 13618: e59d9434 ldr r9, [sp, #1076] + 1361c: e3c99003 bic r9, r9, #3 ; 0x3 + 13620: e2499008 sub r9, r9, #8 ; 0x8 + 13624: e58d9434 str r9, [sp, #1076] + 13628: e2890000 add r0, r9, #0 ; 0x0 + 1362c: e1a01007 mov r1, r7 + 13630: ebf5c005 bl 0xffd8364c + 13634: e2890004 add r0, r9, #4 ; 0x4 + 13638: e59d1438 ldr r1, [sp, #1080] + 1363c: ebf5c002 bl 0xffd8364c + 13640: ebf5c24e bl 0xffd83f80 + 13644: 0801050a stmeqda r1, {r1, r3, r8, sl} + 13648: e1a01003 mov r1, r3 + 1364c: e2937000 adds r7, r3, #0 ; 0x0 + 13650: ebf5c24a bl 0xffd83f80 + 13654: 0801050c stmeqda r1, {r2, r3, r8, sl} + 13658: e3a00f53 mov r0, #332 ; 0x14c + 1365c: e3800b41 orr r0, r0, #66560 ; 0x10400 + 13660: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13664: ebf5c0ab bl 0xffd83918 + 13668: 08010510 stmeqda r1, {r4, r8, sl} + 1366c: e1a03000 mov r3, r0 + 13670: ebf5c242 bl 0xffd83f80 + 13674: 0801050e stmeqda r1, {r1, r2, r3, r8, sl} + 13678: e2870014 add r0, r7, #20 ; 0x14 + 1367c: e1a01003 mov r1, r3 + 13680: ebf5bfd1 bl 0xffd835cc + 13684: 08010510 stmeqda r1, {r4, r8, sl} + 13688: ebf5c23c bl 0xffd83f80 + 1368c: 08010510 stmeqda r1, {r4, r8, sl} + 13690: e2870022 add r0, r7, #34 ; 0x22 + 13694: ebf5c073 bl 0xffd83868 + 13698: 08010514 stmeqda r1, {r2, r4, r8, sl} + 1369c: e1a03000 mov r3, r0 + 136a0: ebf5c236 bl 0xffd83f80 + 136a4: 08010512 stmeqda r1, {r1, r4, r8, sl} + 136a8: e1a01003 mov r1, r3 + 136ac: e2933001 adds r3, r3, #1 ; 0x1 + 136b0: ebf5c232 bl 0xffd83f80 + 136b4: 08010514 stmeqda r1, {r2, r4, r8, sl} + 136b8: e2870022 add r0, r7, #34 ; 0x22 + 136bc: e1a01003 mov r1, r3 + 136c0: ebf5bfa1 bl 0xffd8354c + 136c4: 08010516 stmeqda r1, {r1, r2, r4, r8, sl} + 136c8: ebf5c22c bl 0xffd83f80 + 136cc: 08010516 stmeqda r1, {r1, r2, r4, r8, sl} + 136d0: e3b03022 movs r3, #34 ; 0x22 + 136d4: ebf5c229 bl 0xffd83f80 + 136d8: 08010518 stmeqda r1, {r3, r4, r8, sl} + 136dc: e0870003 add r0, r7, r3 + 136e0: ebf5c075 bl 0xffd838bc + 136e4: 0801051c stmeqda r1, {r2, r3, r4, r8, sl} + 136e8: e1a04000 mov r4, r0 + 136ec: ebf5c223 bl 0xffd83f80 + 136f0: 0801051a stmeqda r1, {r1, r3, r4, r8, sl} + 136f4: e1b04084 movs r4, r4, lsl #1 + 136f8: ebf5c220 bl 0xffd83f80 + 136fc: 0801051c stmeqda r1, {r2, r3, r4, r8, sl} + 13700: e1a01004 mov r1, r4 + 13704: e0944007 adds r4, r4, r7 + 13708: ebf5c21c bl 0xffd83f80 + 1370c: 0801051e stmeqda r1, {r1, r2, r3, r4, r8, sl} + 13710: e2840019 add r0, r4, #25 ; 0x19 + 13714: ebf5c028 bl 0xffd837bc + 13718: 08010522 stmeqda r1, {r1, r5, r8, sl} + 1371c: e1a03000 mov r3, r0 + 13720: ebf5c216 bl 0xffd83f80 + 13724: 08010520 stmeqda r1, {r5, r8, sl} + 13728: e1a01003 mov r1, r3 + 1372c: e2933001 adds r3, r3, #1 ; 0x1 + 13730: ebf5c212 bl 0xffd83f80 + 13734: 08010522 stmeqda r1, {r1, r5, r8, sl} + 13738: e2840019 add r0, r4, #25 ; 0x19 + 1373c: e1a01003 mov r1, r3 + 13740: ebf5bf62 bl 0xffd834d0 + 13744: 08010524 stmeqda r1, {r2, r5, r8, sl} + 13748: ebf5c20c bl 0xffd83f80 + 1374c: 08010524 stmeqda r1, {r2, r5, r8, sl} + 13750: e3b03022 movs r3, #34 ; 0x22 + 13754: ebf5c209 bl 0xffd83f80 + 13758: 08010526 stmeqda r1, {r1, r2, r5, r8, sl} + 1375c: e0870003 add r0, r7, r3 + 13760: ebf5c055 bl 0xffd838bc + 13764: 0801052a stmeqda r1, {r1, r3, r5, r8, sl} + 13768: e1a04000 mov r4, r0 + 1376c: ebf5c203 bl 0xffd83f80 + 13770: 08010528 stmeqda r1, {r3, r5, r8, sl} + 13774: e1b04084 movs r4, r4, lsl #1 + 13778: ebf5c200 bl 0xffd83f80 + 1377c: 0801052a stmeqda r1, {r1, r3, r5, r8, sl} + 13780: e1a01007 mov r1, r7 + 13784: e2973000 adds r3, r7, #0 ; 0x0 + 13788: ebf5c1fc bl 0xffd83f80 + 1378c: 0801052c stmeqda r1, {r2, r3, r5, r8, sl} + 13790: e1a01003 mov r1, r3 + 13794: e2933018 adds r3, r3, #24 ; 0x18 + 13798: ebf5c1f8 bl 0xffd83f80 + 1379c: 0801052e stmeqda r1, {r1, r2, r3, r5, r8, sl} + 137a0: e1a01003 mov r1, r3 + 137a4: e0933004 adds r3, r3, r4 + 137a8: ebf5c1f4 bl 0xffd83f80 + 137ac: 08010530 stmeqda r1, {r4, r5, r8, sl} + 137b0: e2830000 add r0, r3, #0 ; 0x0 + 137b4: ebf5c000 bl 0xffd837bc + 137b8: 08010534 stmeqda r1, {r2, r4, r5, r8, sl} + 137bc: e1a03000 mov r3, r0 + 137c0: ebf5c1ee bl 0xffd83f80 + 137c4: 08010532 stmeqda r1, {r1, r4, r5, r8, sl} + 137c8: e2870014 add r0, r7, #20 ; 0x14 + 137cc: ebf5c051 bl 0xffd83918 + 137d0: 08010536 stmeqda r1, {r1, r2, r4, r5, r8, sl} + 137d4: e1a04000 mov r4, r0 + 137d8: ebf5c1e8 bl 0xffd83f80 + 137dc: 08010534 stmeqda r1, {r2, r4, r5, r8, sl} + 137e0: e1b03103 movs r3, r3, lsl #2 + 137e4: ebf5c1e5 bl 0xffd83f80 + 137e8: 08010536 stmeqda r1, {r1, r2, r4, r5, r8, sl} + 137ec: e1a01003 mov r1, r3 + 137f0: e0933004 adds r3, r3, r4 + 137f4: ebf5c1e1 bl 0xffd83f80 + 137f8: 08010538 stmeqda r1, {r3, r4, r5, r8, sl} + 137fc: e2830000 add r0, r3, #0 ; 0x0 + 13800: ebf5c044 bl 0xffd83918 + 13804: 0801053c stmeqda r1, {r2, r3, r4, r5, r8, sl} + 13808: e1a04000 mov r4, r0 + 1380c: ebf5c1db bl 0xffd83f80 + 13810: 0801053a stmeqda r1, {r1, r3, r4, r5, r8, sl} + 13814: e1a01007 mov r1, r7 + 13818: e2973000 adds r3, r7, #0 ; 0x0 + 1381c: ebf5c1d7 bl 0xffd83f80 + 13820: 0801053c stmeqda r1, {r2, r3, r4, r5, r8, sl} + 13824: ebf5c1d5 bl 0xffd83f80 + 13828: 0801053e stmeqda r1, {r1, r2, r3, r4, r5, r8, sl} + 1382c: e3a00041 mov r0, #65 ; 0x41 + 13830: e3800c05 orr r0, r0, #1280 ; 0x500 + 13834: e3800801 orr r0, r0, #65536 ; 0x10000 + 13838: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1383c: e58d0438 str r0, [sp, #1080] + 13840: e28cc068 add ip, ip, #104 ; 0x68 + 13844: e1a00fac mov r0, ip, lsr #31 + 13848: e08ff100 add pc, pc, r0, lsl #2 + 1384c: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 13850: ebf5bdbf bl 0xffd82f54 + 13854: eaffc58c b 0x4e8c + 13858: 08010550 stmeqda r1, {r4, r6, r8, sl} + 1385c: 00000000 andeq r0, r0, r0 + 13860: ebf5c1c6 bl 0xffd83f80 + 13864: 08010550 stmeqda r1, {r4, r6, r8, sl} + 13868: e59d9434 ldr r9, [sp, #1076] + 1386c: e3c99003 bic r9, r9, #3 ; 0x3 + 13870: e249900c sub r9, r9, #12 ; 0xc + 13874: e58d9434 str r9, [sp, #1076] + 13878: e2890000 add r0, r9, #0 ; 0x0 + 1387c: e1a01007 mov r1, r7 + 13880: ebf5bf71 bl 0xffd8364c + 13884: e2890004 add r0, r9, #4 ; 0x4 + 13888: e1a01008 mov r1, r8 + 1388c: ebf5bf6e bl 0xffd8364c + 13890: e2890008 add r0, r9, #8 ; 0x8 + 13894: e59d1438 ldr r1, [sp, #1080] + 13898: ebf5bf6b bl 0xffd8364c + 1389c: ebf5c1b7 bl 0xffd83f80 + 138a0: 08010552 stmeqda r1, {r1, r4, r6, r8, sl} + 138a4: e1a01003 mov r1, r3 + 138a8: e2937000 adds r7, r3, #0 ; 0x0 + 138ac: ebf5c1b3 bl 0xffd83f80 + 138b0: 08010554 stmeqda r1, {r2, r4, r6, r8, sl} + 138b4: e3b04003 movs r4, #3 ; 0x3 + 138b8: ebf5c1b0 bl 0xffd83f80 + 138bc: 08010556 stmeqda r1, {r1, r2, r4, r6, r8, sl} + 138c0: ebf5c1ae bl 0xffd83f80 + 138c4: 08010558 stmeqda r1, {r3, r4, r6, r8, sl} + 138c8: e3a0005b mov r0, #91 ; 0x5b + 138cc: e3800c05 orr r0, r0, #1280 ; 0x500 + 138d0: e3800801 orr r0, r0, #65536 ; 0x10000 + 138d4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 138d8: e58d0438 str r0, [sp, #1080] + 138dc: e28cc011 add ip, ip, #17 ; 0x11 + 138e0: e1a00fac mov r0, ip, lsr #31 + 138e4: e08ff100 add pc, pc, r0, lsl #2 + 138e8: 08001480 stmeqda r0, {r7, sl, ip} + 138ec: ebf5bd98 bl 0xffd82f54 + 138f0: eafff450 b 0x10a38 + 138f4: 0801055a stmeqda r1, {r1, r3, r4, r6, r8, sl} + 138f8: 00000000 andeq r0, r0, r0 + 138fc: ebf5c19f bl 0xffd83f80 + 13900: 0801055a stmeqda r1, {r1, r3, r4, r6, r8, sl} + 13904: e3b04022 movs r4, #34 ; 0x22 + 13908: ebf5c19c bl 0xffd83f80 + 1390c: 0801055c stmeqda r1, {r2, r3, r4, r6, r8, sl} + 13910: e0870004 add r0, r7, r4 + 13914: ebf5bfe8 bl 0xffd838bc + 13918: 08010560 stmeqda r1, {r5, r6, r8, sl} + 1391c: e1a03000 mov r3, r0 + 13920: ebf5c196 bl 0xffd83f80 + 13924: 0801055e stmeqda r1, {r1, r2, r3, r4, r6, r8, sl} + 13928: e1b03083 movs r3, r3, lsl #1 + 1392c: ebf5c193 bl 0xffd83f80 + 13930: 08010560 stmeqda r1, {r5, r6, r8, sl} + 13934: e1a01003 mov r1, r3 + 13938: e0933007 adds r3, r3, r7 + 1393c: ebf5c18f bl 0xffd83f80 + 13940: 08010562 stmeqda r1, {r1, r5, r6, r8, sl} + 13944: e3b04000 movs r4, #0 ; 0x0 + 13948: ebf5c18c bl 0xffd83f80 + 1394c: 08010564 stmeqda r1, {r2, r5, r6, r8, sl} + 13950: e2830019 add r0, r3, #25 ; 0x19 + 13954: e1a01004 mov r1, r4 + 13958: ebf5bedc bl 0xffd834d0 + 1395c: 08010566 stmeqda r1, {r1, r2, r5, r6, r8, sl} + 13960: ebf5c186 bl 0xffd83f80 + 13964: 08010566 stmeqda r1, {r1, r2, r5, r6, r8, sl} + 13968: e3a00f69 mov r0, #420 ; 0x1a4 + 1396c: e3800b41 orr r0, r0, #66560 ; 0x10400 + 13970: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13974: ebf5bfe7 bl 0xffd83918 + 13978: 0801056a stmeqda r1, {r1, r3, r5, r6, r8, sl} + 1397c: e1a03000 mov r3, r0 + 13980: ebf5c17e bl 0xffd83f80 + 13984: 08010568 stmeqda r1, {r3, r5, r6, r8, sl} + 13988: e1a01007 mov r1, r7 + 1398c: e2978000 adds r8, r7, #0 ; 0x0 + 13990: ebf5c17a bl 0xffd83f80 + 13994: 0801056a stmeqda r1, {r1, r3, r5, r6, r8, sl} + 13998: e1a01008 mov r1, r8 + 1399c: e2988018 adds r8, r8, #24 ; 0x18 + 139a0: ebf5c176 bl 0xffd83f80 + 139a4: 0801056c stmeqda r1, {r2, r3, r5, r6, r8, sl} + 139a8: e1a01007 mov r1, r7 + 139ac: e2974000 adds r4, r7, #0 ; 0x0 + 139b0: ebf5c172 bl 0xffd83f80 + 139b4: 0801056e stmeqda r1, {r1, r2, r3, r5, r6, r8, sl} + 139b8: e1a01004 mov r1, r4 + 139bc: e2944022 adds r4, r4, #34 ; 0x22 + 139c0: ebf5c16e bl 0xffd83f80 + 139c4: 08010570 stmeqda r1, {r4, r5, r6, r8, sl} + 139c8: e2830000 add r0, r3, #0 ; 0x0 + 139cc: ebf5bfd1 bl 0xffd83918 + 139d0: 08010574 stmeqda r1, {r2, r4, r5, r6, r8, sl} + 139d4: e1a05000 mov r5, r0 + 139d8: ebf5c168 bl 0xffd83f80 + 139dc: 08010572 stmeqda r1, {r1, r4, r5, r6, r8, sl} + 139e0: e1a01008 mov r1, r8 + 139e4: e2983000 adds r3, r8, #0 ; 0x0 + 139e8: ebf5c164 bl 0xffd83f80 + 139ec: 08010574 stmeqda r1, {r2, r4, r5, r6, r8, sl} + 139f0: ebf5c162 bl 0xffd83f80 + 139f4: 08010576 stmeqda r1, {r1, r2, r4, r5, r6, r8, sl} + 139f8: e3a00079 mov r0, #121 ; 0x79 + 139fc: e3800c05 orr r0, r0, #1280 ; 0x500 + 13a00: e3800801 orr r0, r0, #65536 ; 0x10000 + 13a04: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13a08: e58d0438 str r0, [sp, #1080] + 13a0c: e28cc034 add ip, ip, #52 ; 0x34 + 13a10: e1a00fac mov r0, ip, lsr #31 + 13a14: e08ff100 add pc, pc, r0, lsl #2 + 13a18: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 13a1c: ebf5bd4c bl 0xffd82f54 + 13a20: eafffa6a b 0x123d0 + 13a24: 08010578 stmeqda r1, {r3, r4, r5, r6, r8, sl} + 13a28: 00000000 andeq r0, r0, r0 + 13a2c: ebf5c153 bl 0xffd83f80 + 13a30: 08010578 stmeqda r1, {r3, r4, r5, r6, r8, sl} + 13a34: e3b03022 movs r3, #34 ; 0x22 + 13a38: ebf5c150 bl 0xffd83f80 + 13a3c: 0801057a stmeqda r1, {r1, r3, r4, r5, r6, r8, sl} + 13a40: e0870003 add r0, r7, r3 + 13a44: ebf5bf9c bl 0xffd838bc + 13a48: 0801057e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8, sl} + 13a4c: e1a04000 mov r4, r0 + 13a50: ebf5c14a bl 0xffd83f80 + 13a54: 0801057c stmeqda r1, {r2, r3, r4, r5, r6, r8, sl} + 13a58: e1b04084 movs r4, r4, lsl #1 + 13a5c: ebf5c147 bl 0xffd83f80 + 13a60: 0801057e stmeqda r1, {r1, r2, r3, r4, r5, r6, r8, sl} + 13a64: e1a01004 mov r1, r4 + 13a68: e0944007 adds r4, r4, r7 + 13a6c: ebf5c143 bl 0xffd83f80 + 13a70: 08010580 stmeqda r1, {r7, r8, sl} + 13a74: e2840019 add r0, r4, #25 ; 0x19 + 13a78: ebf5bf4f bl 0xffd837bc + 13a7c: 08010584 stmeqda r1, {r2, r7, r8, sl} + 13a80: e1a03000 mov r3, r0 + 13a84: ebf5c13d bl 0xffd83f80 + 13a88: 08010582 stmeqda r1, {r1, r7, r8, sl} + 13a8c: e1a01003 mov r1, r3 + 13a90: e2933001 adds r3, r3, #1 ; 0x1 + 13a94: ebf5c139 bl 0xffd83f80 + 13a98: 08010584 stmeqda r1, {r2, r7, r8, sl} + 13a9c: e2840019 add r0, r4, #25 ; 0x19 + 13aa0: e1a01003 mov r1, r3 + 13aa4: ebf5be89 bl 0xffd834d0 + 13aa8: 08010586 stmeqda r1, {r1, r2, r7, r8, sl} + 13aac: ebf5c133 bl 0xffd83f80 + 13ab0: 08010586 stmeqda r1, {r1, r2, r7, r8, sl} + 13ab4: e3b04022 movs r4, #34 ; 0x22 + 13ab8: ebf5c130 bl 0xffd83f80 + 13abc: 08010588 stmeqda r1, {r3, r7, r8, sl} + 13ac0: e0870004 add r0, r7, r4 + 13ac4: ebf5bf7c bl 0xffd838bc + 13ac8: 0801058c stmeqda r1, {r2, r3, r7, r8, sl} + 13acc: e1a03000 mov r3, r0 + 13ad0: ebf5c12a bl 0xffd83f80 + 13ad4: 0801058a stmeqda r1, {r1, r3, r7, r8, sl} + 13ad8: e1b03083 movs r3, r3, lsl #1 + 13adc: ebf5c127 bl 0xffd83f80 + 13ae0: 0801058c stmeqda r1, {r2, r3, r7, r8, sl} + 13ae4: e1a01008 mov r1, r8 + 13ae8: e0988003 adds r8, r8, r3 + 13aec: ebf5c123 bl 0xffd83f80 + 13af0: 0801058e stmeqda r1, {r1, r2, r3, r7, r8, sl} + 13af4: e2880000 add r0, r8, #0 ; 0x0 + 13af8: ebf5bf2f bl 0xffd837bc + 13afc: 08010592 stmeqda r1, {r1, r4, r7, r8, sl} + 13b00: e1a03000 mov r3, r0 + 13b04: ebf5c11d bl 0xffd83f80 + 13b08: 08010590 stmeqda r1, {r4, r7, r8, sl} + 13b0c: e2870014 add r0, r7, #20 ; 0x14 + 13b10: ebf5bf80 bl 0xffd83918 + 13b14: 08010594 stmeqda r1, {r2, r4, r7, r8, sl} + 13b18: e1a04000 mov r4, r0 + 13b1c: ebf5c117 bl 0xffd83f80 + 13b20: 08010592 stmeqda r1, {r1, r4, r7, r8, sl} + 13b24: e1b03103 movs r3, r3, lsl #2 + 13b28: ebf5c114 bl 0xffd83f80 + 13b2c: 08010594 stmeqda r1, {r2, r4, r7, r8, sl} + 13b30: e1a01003 mov r1, r3 + 13b34: e0933004 adds r3, r3, r4 + 13b38: ebf5c110 bl 0xffd83f80 + 13b3c: 08010596 stmeqda r1, {r1, r2, r4, r7, r8, sl} + 13b40: e2830000 add r0, r3, #0 ; 0x0 + 13b44: ebf5bf73 bl 0xffd83918 + 13b48: 0801059a stmeqda r1, {r1, r3, r4, r7, r8, sl} + 13b4c: e1a04000 mov r4, r0 + 13b50: ebf5c10a bl 0xffd83f80 + 13b54: 08010598 stmeqda r1, {r3, r4, r7, r8, sl} + 13b58: e1a01007 mov r1, r7 + 13b5c: e2973000 adds r3, r7, #0 ; 0x0 + 13b60: ebf5c106 bl 0xffd83f80 + 13b64: 0801059a stmeqda r1, {r1, r3, r4, r7, r8, sl} + 13b68: ebf5c104 bl 0xffd83f80 + 13b6c: 0801059c stmeqda r1, {r2, r3, r4, r7, r8, sl} + 13b70: e3a0009f mov r0, #159 ; 0x9f + 13b74: e3800c05 orr r0, r0, #1280 ; 0x500 + 13b78: e3800801 orr r0, r0, #65536 ; 0x10000 + 13b7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13b80: e58d0438 str r0, [sp, #1080] + 13b84: e28cc046 add ip, ip, #70 ; 0x46 + 13b88: e1a00fac mov r0, ip, lsr #31 + 13b8c: e08ff100 add pc, pc, r0, lsl #2 + 13b90: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 13b94: ebf5bcee bl 0xffd82f54 + 13b98: eaffc4bb b 0x4e8c + 13b9c: 08010c2c stmeqda r1, {r2, r3, r5, sl, fp} + 13ba0: 00000000 andeq r0, r0, r0 + 13ba4: ebf5c0f5 bl 0xffd83f80 + 13ba8: 08010c2c stmeqda r1, {r2, r3, r5, sl, fp} + 13bac: e59d9434 ldr r9, [sp, #1076] + 13bb0: e3c99003 bic r9, r9, #3 ; 0x3 + 13bb4: e2499004 sub r9, r9, #4 ; 0x4 + 13bb8: e58d9434 str r9, [sp, #1076] + 13bbc: e2890000 add r0, r9, #0 ; 0x0 + 13bc0: e59d1438 ldr r1, [sp, #1080] + 13bc4: ebf5bea0 bl 0xffd8364c + 13bc8: ebf5c0ec bl 0xffd83f80 + 13bcc: 08010c2e stmeqda r1, {r1, r2, r3, r5, sl, fp} + 13bd0: e1a01003 mov r1, r3 + 13bd4: e2934000 adds r4, r3, #0 ; 0x0 + 13bd8: ebf5c0e8 bl 0xffd83f80 + 13bdc: 08010c30 stmeqda r1, {r4, r5, sl, fp} + 13be0: e2840030 add r0, r4, #48 ; 0x30 + 13be4: ebf5bf4b bl 0xffd83918 + 13be8: 08010c34 stmeqda r1, {r2, r4, r5, sl, fp} + 13bec: e1a05000 mov r5, r0 + 13bf0: ebf5c0e2 bl 0xffd83f80 + 13bf4: 08010c32 stmeqda r1, {r1, r4, r5, sl, fp} + 13bf8: e3550000 cmp r5, #0 ; 0x0 + 13bfc: ebf5c0df bl 0xffd83f80 + 13c00: 08010c34 stmeqda r1, {r2, r4, r5, sl, fp} + 13c04: e28cc011 add ip, ip, #17 ; 0x11 + 13c08: 0a000004 beq 0x13c20 + 13c0c: e1a00fac mov r0, ip, lsr #31 + 13c10: e08ff100 add pc, pc, r0, lsl #2 + 13c14: 08010c4e stmeqda r1, {r1, r2, r3, r6, sl, fp} + 13c18: ebf5bccd bl 0xffd82f54 + 13c1c: ea00003d b 0x13d18 + 13c20: ebf5c0d6 bl 0xffd83f80 + 13c24: 08010c36 stmeqda r1, {r1, r2, r4, r5, sl, fp} + 13c28: e3b06022 movs r6, #34 ; 0x22 + 13c2c: ebf5c0d3 bl 0xffd83f80 + 13c30: 08010c38 stmeqda r1, {r3, r4, r5, sl, fp} + 13c34: e0840006 add r0, r4, r6 + 13c38: ebf5bf1f bl 0xffd838bc + 13c3c: 08010c3c stmeqda r1, {r2, r3, r4, r5, sl, fp} + 13c40: e1a03000 mov r3, r0 + 13c44: ebf5c0cd bl 0xffd83f80 + 13c48: 08010c3a stmeqda r1, {r1, r3, r4, r5, sl, fp} + 13c4c: e1b03083 movs r3, r3, lsl #1 + 13c50: ebf5c0ca bl 0xffd83f80 + 13c54: 08010c3c stmeqda r1, {r2, r3, r4, r5, sl, fp} + 13c58: e1a01003 mov r1, r3 + 13c5c: e0933004 adds r3, r3, r4 + 13c60: ebf5c0c6 bl 0xffd83f80 + 13c64: 08010c3e stmeqda r1, {r1, r2, r3, r4, r5, sl, fp} + 13c68: e2830017 add r0, r3, #23 ; 0x17 + 13c6c: e1a01005 mov r1, r5 + 13c70: ebf5be16 bl 0xffd834d0 + 13c74: 08010c40 stmeqda r1, {r6, sl, fp} + 13c78: ebf5c0c0 bl 0xffd83f80 + 13c7c: 08010c40 stmeqda r1, {r6, sl, fp} + 13c80: e3a00f15 mov r0, #84 ; 0x54 + 13c84: e3800b43 orr r0, r0, #68608 ; 0x10c00 + 13c88: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13c8c: ebf5bf21 bl 0xffd83918 + 13c90: 08010c44 stmeqda r1, {r2, r6, sl, fp} + 13c94: e1a05000 mov r5, r0 + 13c98: ebf5c0b8 bl 0xffd83f80 + 13c9c: 08010c42 stmeqda r1, {r1, r6, sl, fp} + 13ca0: e1a01004 mov r1, r4 + 13ca4: e2943000 adds r3, r4, #0 ; 0x0 + 13ca8: ebf5c0b4 bl 0xffd83f80 + 13cac: 08010c44 stmeqda r1, {r2, r6, sl, fp} + 13cb0: e1a01003 mov r1, r3 + 13cb4: e2933018 adds r3, r3, #24 ; 0x18 + 13cb8: ebf5c0b0 bl 0xffd83f80 + 13cbc: 08010c46 stmeqda r1, {r1, r2, r6, sl, fp} + 13cc0: e1a01004 mov r1, r4 + 13cc4: e2944022 adds r4, r4, #34 ; 0x22 + 13cc8: ebf5c0ac bl 0xffd83f80 + 13ccc: 08010c48 stmeqda r1, {r3, r6, sl, fp} + 13cd0: e2850000 add r0, r5, #0 ; 0x0 + 13cd4: ebf5bf0f bl 0xffd83918 + 13cd8: 08010c4c stmeqda r1, {r2, r3, r6, sl, fp} + 13cdc: e1a05000 mov r5, r0 + 13ce0: ebf5c0a6 bl 0xffd83f80 + 13ce4: 08010c4a stmeqda r1, {r1, r3, r6, sl, fp} + 13ce8: ebf5c0a4 bl 0xffd83f80 + 13cec: 08010c4c stmeqda r1, {r2, r3, r6, sl, fp} + 13cf0: e3a0004f mov r0, #79 ; 0x4f + 13cf4: e3800b43 orr r0, r0, #68608 ; 0x10c00 + 13cf8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 13cfc: e58d0438 str r0, [sp, #1080] + 13d00: e28cc02b add ip, ip, #43 ; 0x2b + 13d04: e1a00fac mov r0, ip, lsr #31 + 13d08: e08ff100 add pc, pc, r0, lsl #2 + 13d0c: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 13d10: ebf5bc8f bl 0xffd82f54 + 13d14: eafff9ad b 0x123d0 + 13d18: ebf5c098 bl 0xffd83f80 + 13d1c: 08010c4e stmeqda r1, {r1, r2, r3, r6, sl, fp} + 13d20: e59d9434 ldr r9, [sp, #1076] + 13d24: e3c99003 bic r9, r9, #3 ; 0x3 + 13d28: e2890004 add r0, r9, #4 ; 0x4 + 13d2c: e58d0434 str r0, [sp, #1076] + 13d30: e2890000 add r0, r9, #0 ; 0x0 + 13d34: ebf5bef7 bl 0xffd83918 + 13d38: 08010c52 stmeqda r1, {r1, r4, r6, sl, fp} + 13d3c: e1a03000 mov r3, r0 + 13d40: ebf5c08e bl 0xffd83f80 + 13d44: 08010c50 stmeqda r1, {r4, r6, sl, fp} + 13d48: e1a00003 mov r0, r3 + 13d4c: e28cc007 add ip, ip, #7 ; 0x7 + 13d50: eaf5bcde b 0xffd830d0 + 13d54: 0801059e stmeqda r1, {r1, r2, r3, r4, r7, r8, sl} + 13d58: 00000000 andeq r0, r0, r0 + 13d5c: ebf5c087 bl 0xffd83f80 + 13d60: 0801059e stmeqda r1, {r1, r2, r3, r4, r7, r8, sl} + 13d64: e59d9434 ldr r9, [sp, #1076] + 13d68: e3c99003 bic r9, r9, #3 ; 0x3 + 13d6c: e2890008 add r0, r9, #8 ; 0x8 + 13d70: e58d0434 str r0, [sp, #1076] + 13d74: e2890000 add r0, r9, #0 ; 0x0 + 13d78: ebf5bee6 bl 0xffd83918 + 13d7c: 080105a2 stmeqda r1, {r1, r5, r7, r8, sl} + 13d80: e1a07000 mov r7, r0 + 13d84: e2890004 add r0, r9, #4 ; 0x4 + 13d88: ebf5bee2 bl 0xffd83918 + 13d8c: 080105a2 stmeqda r1, {r1, r5, r7, r8, sl} + 13d90: e1a08000 mov r8, r0 + 13d94: ebf5c079 bl 0xffd83f80 + 13d98: 080105a0 stmeqda r1, {r5, r7, r8, sl} + 13d9c: e59d9434 ldr r9, [sp, #1076] + 13da0: e3c99003 bic r9, r9, #3 ; 0x3 + 13da4: e2890004 add r0, r9, #4 ; 0x4 + 13da8: e58d0434 str r0, [sp, #1076] + 13dac: e2890000 add r0, r9, #0 ; 0x0 + 13db0: ebf5bed8 bl 0xffd83918 + 13db4: 080105a4 stmeqda r1, {r2, r5, r7, r8, sl} + 13db8: e1a03000 mov r3, r0 + 13dbc: ebf5c06f bl 0xffd83f80 + 13dc0: 080105a2 stmeqda r1, {r1, r5, r7, r8, sl} + 13dc4: e1a00003 mov r0, r3 + 13dc8: e28cc00c add ip, ip, #12 ; 0xc + 13dcc: eaf5bcbf b 0xffd830d0 + 13dd0: 08010540 stmeqda r1, {r6, r8, sl} + 13dd4: 00000000 andeq r0, r0, r0 + 13dd8: ebf5c068 bl 0xffd83f80 + 13ddc: 08010540 stmeqda r1, {r6, r8, sl} + 13de0: e2870022 add r0, r7, #34 ; 0x22 + 13de4: ebf5be9f bl 0xffd83868 + 13de8: 08010544 stmeqda r1, {r2, r6, r8, sl} + 13dec: e1a03000 mov r3, r0 + 13df0: ebf5c062 bl 0xffd83f80 + 13df4: 08010542 stmeqda r1, {r1, r6, r8, sl} + 13df8: e1a01003 mov r1, r3 + 13dfc: e2533001 subs r3, r3, #1 ; 0x1 + 13e00: ebf5c05e bl 0xffd83f80 + 13e04: 08010544 stmeqda r1, {r2, r6, r8, sl} + 13e08: e2870022 add r0, r7, #34 ; 0x22 + 13e0c: e1a01003 mov r1, r3 + 13e10: ebf5bdcd bl 0xffd8354c + 13e14: 08010546 stmeqda r1, {r1, r2, r6, r8, sl} + 13e18: ebf5c058 bl 0xffd83f80 + 13e1c: 08010546 stmeqda r1, {r1, r2, r6, r8, sl} + 13e20: e59d9434 ldr r9, [sp, #1076] + 13e24: e3c99003 bic r9, r9, #3 ; 0x3 + 13e28: e2890004 add r0, r9, #4 ; 0x4 + 13e2c: e58d0434 str r0, [sp, #1076] + 13e30: e2890000 add r0, r9, #0 ; 0x0 + 13e34: ebf5beb7 bl 0xffd83918 + 13e38: 0801054a stmeqda r1, {r1, r3, r6, r8, sl} + 13e3c: e1a07000 mov r7, r0 + 13e40: ebf5c04e bl 0xffd83f80 + 13e44: 08010548 stmeqda r1, {r3, r6, r8, sl} + 13e48: e59d9434 ldr r9, [sp, #1076] + 13e4c: e3c99003 bic r9, r9, #3 ; 0x3 + 13e50: e2890004 add r0, r9, #4 ; 0x4 + 13e54: e58d0434 str r0, [sp, #1076] + 13e58: e2890000 add r0, r9, #0 ; 0x0 + 13e5c: ebf5bead bl 0xffd83918 + 13e60: 0801054c stmeqda r1, {r2, r3, r6, r8, sl} + 13e64: e1a03000 mov r3, r0 + 13e68: ebf5c044 bl 0xffd83f80 + 13e6c: 0801054a stmeqda r1, {r1, r3, r6, r8, sl} + 13e70: e1a00003 mov r0, r3 + 13e74: e28cc017 add ip, ip, #23 ; 0x17 + 13e78: eaf5bc94 b 0xffd830d0 + 13e7c: 080104f8 stmeqda r1, {r3, r4, r5, r6, r7, sl} + 13e80: 00000000 andeq r0, r0, r0 + 13e84: ebf5c03d bl 0xffd83f80 + 13e88: 080104f8 stmeqda r1, {r3, r4, r5, r6, r7, sl} + 13e8c: e2870022 add r0, r7, #34 ; 0x22 + 13e90: ebf5be74 bl 0xffd83868 + 13e94: 080104fc stmeqda r1, {r2, r3, r4, r5, r6, r7, sl} + 13e98: e1a03000 mov r3, r0 + 13e9c: ebf5c037 bl 0xffd83f80 + 13ea0: 080104fa stmeqda r1, {r1, r3, r4, r5, r6, r7, sl} + 13ea4: e1a01003 mov r1, r3 + 13ea8: e2533001 subs r3, r3, #1 ; 0x1 + 13eac: ebf5c033 bl 0xffd83f80 + 13eb0: 080104fc stmeqda r1, {r2, r3, r4, r5, r6, r7, sl} + 13eb4: e2870022 add r0, r7, #34 ; 0x22 + 13eb8: e1a01003 mov r1, r3 + 13ebc: ebf5bda2 bl 0xffd8354c + 13ec0: 080104fe stmeqda r1, {r1, r2, r3, r4, r5, r6, r7, sl} + 13ec4: ebf5c02d bl 0xffd83f80 + 13ec8: 080104fe stmeqda r1, {r1, r2, r3, r4, r5, r6, r7, sl} + 13ecc: e59d9434 ldr r9, [sp, #1076] + 13ed0: e3c99003 bic r9, r9, #3 ; 0x3 + 13ed4: e2890004 add r0, r9, #4 ; 0x4 + 13ed8: e58d0434 str r0, [sp, #1076] + 13edc: e2890000 add r0, r9, #0 ; 0x0 + 13ee0: ebf5be8c bl 0xffd83918 + 13ee4: 08010502 stmeqda r1, {r1, r8, sl} + 13ee8: e1a07000 mov r7, r0 + 13eec: ebf5c023 bl 0xffd83f80 + 13ef0: 08010500 stmeqda r1, {r8, sl} + 13ef4: e59d9434 ldr r9, [sp, #1076] + 13ef8: e3c99003 bic r9, r9, #3 ; 0x3 + 13efc: e2890004 add r0, r9, #4 ; 0x4 + 13f00: e58d0434 str r0, [sp, #1076] + 13f04: e2890000 add r0, r9, #0 ; 0x0 + 13f08: ebf5be82 bl 0xffd83918 + 13f0c: 08010504 stmeqda r1, {r2, r8, sl} + 13f10: e1a03000 mov r3, r0 + 13f14: ebf5c019 bl 0xffd83f80 + 13f18: 08010502 stmeqda r1, {r1, r8, sl} + 13f1c: e1a00003 mov r0, r3 + 13f20: e28cc017 add ip, ip, #23 ; 0x17 + 13f24: eaf5bc69 b 0xffd830d0 + 13f28: 0800172c stmeqda r0, {r2, r3, r5, r8, r9, sl, ip} + 13f2c: 00000000 andeq r0, r0, r0 + 13f30: ebf5c012 bl 0xffd83f80 + 13f34: 0800172c stmeqda r0, {r2, r3, r5, r8, r9, sl, ip} + 13f38: e59d9434 ldr r9, [sp, #1076] + 13f3c: e3c99003 bic r9, r9, #3 ; 0x3 + 13f40: e2890004 add r0, r9, #4 ; 0x4 + 13f44: e58d0434 str r0, [sp, #1076] + 13f48: e2890000 add r0, r9, #0 ; 0x0 + 13f4c: ebf5be71 bl 0xffd83918 + 13f50: 08001730 stmeqda r0, {r4, r5, r8, r9, sl, ip} + 13f54: e1a03000 mov r3, r0 + 13f58: ebf5c008 bl 0xffd83f80 + 13f5c: 0800172e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, ip} + 13f60: e1a00003 mov r0, r3 + 13f64: e28cc007 add ip, ip, #7 ; 0x7 + 13f68: eaf5bc58 b 0xffd830d0 + 13f6c: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 13f70: 00000000 andeq r0, r0, r0 + 13f74: ebf5c001 bl 0xffd83f80 + 13f78: 08001750 stmeqda r0, {r4, r6, r8, r9, sl, ip} + 13f7c: e2870030 add r0, r7, #48 ; 0x30 + 13f80: ebf5be64 bl 0xffd83918 + 13f84: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 13f88: e1a03000 mov r3, r0 + 13f8c: ebf5bffb bl 0xffd83f80 + 13f90: 08001752 stmeqda r0, {r1, r4, r6, r8, r9, sl, ip} + 13f94: e3530000 cmp r3, #0 ; 0x0 + 13f98: ebf5bff8 bl 0xffd83f80 + 13f9c: 08001754 stmeqda r0, {r2, r4, r6, r8, r9, sl, ip} + 13fa0: e28cc00b add ip, ip, #11 ; 0xb + 13fa4: 0a000004 beq 0x13fbc + 13fa8: e1a00fac mov r0, ip, lsr #31 + 13fac: e08ff100 add pc, pc, r0, lsl #2 + 13fb0: 08001740 stmeqda r0, {r6, r8, r9, sl, ip} + 13fb4: ebf5bbe6 bl 0xffd82f54 + 13fb8: eafffc0c b 0x12ff0 + 13fbc: ebf5bfef bl 0xffd83f80 + 13fc0: 08001756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, ip} + 13fc4: e28cc003 add ip, ip, #3 ; 0x3 + 13fc8: e1a00fac mov r0, ip, lsr #31 + 13fcc: e08ff100 add pc, pc, r0, lsl #2 + 13fd0: 08001760 stmeqda r0, {r5, r6, r8, r9, sl, ip} + 13fd4: ebf5bbde bl 0xffd82f54 + 13fd8: eafffc4d b 0x13114 + 13fdc: 08005ab0 stmeqda r0, {r4, r5, r7, r9, fp, ip, lr} + 13fe0: 00000000 andeq r0, r0, r0 + 13fe4: ebf5bfe5 bl 0xffd83f80 + 13fe8: 08005ab0 stmeqda r0, {r4, r5, r7, r9, fp, ip, lr} + 13fec: e59d9434 ldr r9, [sp, #1076] + 13ff0: e3c99003 bic r9, r9, #3 ; 0x3 + 13ff4: e2499008 sub r9, r9, #8 ; 0x8 + 13ff8: e58d9434 str r9, [sp, #1076] + 13ffc: e2890000 add r0, r9, #0 ; 0x0 + 14000: e1a01007 mov r1, r7 + 14004: ebf5bd90 bl 0xffd8364c + 14008: e2890004 add r0, r9, #4 ; 0x4 + 1400c: e59d1438 ldr r1, [sp, #1080] + 14010: ebf5bd8d bl 0xffd8364c + 14014: ebf5bfd9 bl 0xffd83f80 + 14018: 08005ab2 stmeqda r0, {r1, r4, r5, r7, r9, fp, ip, lr} + 1401c: e1a01003 mov r1, r3 + 14020: e2937000 adds r7, r3, #0 ; 0x0 + 14024: ebf5bfd5 bl 0xffd83f80 + 14028: 08005ab4 stmeqda r0, {r2, r4, r5, r7, r9, fp, ip, lr} + 1402c: e3a00fbd mov r0, #756 ; 0x2f4 + 14030: e3800b16 orr r0, r0, #22528 ; 0x5800 + 14034: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14038: ebf5be36 bl 0xffd83918 + 1403c: 08005ab8 stmeqda r0, {r3, r4, r5, r7, r9, fp, ip, lr} + 14040: e1a03000 mov r3, r0 + 14044: ebf5bfcd bl 0xffd83f80 + 14048: 08005ab6 stmeqda r0, {r1, r2, r4, r5, r7, r9, fp, ip, lr} + 1404c: e2870014 add r0, r7, #20 ; 0x14 + 14050: e1a01003 mov r1, r3 + 14054: ebf5bd5c bl 0xffd835cc + 14058: 08005ab8 stmeqda r0, {r3, r4, r5, r7, r9, fp, ip, lr} + 1405c: ebf5bfc7 bl 0xffd83f80 + 14060: 08005ab8 stmeqda r0, {r3, r4, r5, r7, r9, fp, ip, lr} + 14064: e2870022 add r0, r7, #34 ; 0x22 + 14068: ebf5bdfe bl 0xffd83868 + 1406c: 08005abc stmeqda r0, {r2, r3, r4, r5, r7, r9, fp, ip, lr} + 14070: e1a03000 mov r3, r0 + 14074: ebf5bfc1 bl 0xffd83f80 + 14078: 08005aba stmeqda r0, {r1, r3, r4, r5, r7, r9, fp, ip, lr} + 1407c: e1a01003 mov r1, r3 + 14080: e2933001 adds r3, r3, #1 ; 0x1 + 14084: ebf5bfbd bl 0xffd83f80 + 14088: 08005abc stmeqda r0, {r2, r3, r4, r5, r7, r9, fp, ip, lr} + 1408c: e2870022 add r0, r7, #34 ; 0x22 + 14090: e1a01003 mov r1, r3 + 14094: ebf5bd2c bl 0xffd8354c + 14098: 08005abe stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, fp, ip, lr} + 1409c: ebf5bfb7 bl 0xffd83f80 + 140a0: 08005abe stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, fp, ip, lr} + 140a4: e3b03022 movs r3, #34 ; 0x22 + 140a8: ebf5bfb4 bl 0xffd83f80 + 140ac: 08005ac0 stmeqda r0, {r6, r7, r9, fp, ip, lr} + 140b0: e0870003 add r0, r7, r3 + 140b4: ebf5be00 bl 0xffd838bc + 140b8: 08005ac4 stmeqda r0, {r2, r6, r7, r9, fp, ip, lr} + 140bc: e1a04000 mov r4, r0 + 140c0: ebf5bfae bl 0xffd83f80 + 140c4: 08005ac2 stmeqda r0, {r1, r6, r7, r9, fp, ip, lr} + 140c8: e1b04084 movs r4, r4, lsl #1 + 140cc: ebf5bfab bl 0xffd83f80 + 140d0: 08005ac4 stmeqda r0, {r2, r6, r7, r9, fp, ip, lr} + 140d4: e1a01004 mov r1, r4 + 140d8: e0944007 adds r4, r4, r7 + 140dc: ebf5bfa7 bl 0xffd83f80 + 140e0: 08005ac6 stmeqda r0, {r1, r2, r6, r7, r9, fp, ip, lr} + 140e4: e2840019 add r0, r4, #25 ; 0x19 + 140e8: ebf5bdb3 bl 0xffd837bc + 140ec: 08005aca stmeqda r0, {r1, r3, r6, r7, r9, fp, ip, lr} + 140f0: e1a03000 mov r3, r0 + 140f4: ebf5bfa1 bl 0xffd83f80 + 140f8: 08005ac8 stmeqda r0, {r3, r6, r7, r9, fp, ip, lr} + 140fc: e1a01003 mov r1, r3 + 14100: e2933001 adds r3, r3, #1 ; 0x1 + 14104: ebf5bf9d bl 0xffd83f80 + 14108: 08005aca stmeqda r0, {r1, r3, r6, r7, r9, fp, ip, lr} + 1410c: e2840019 add r0, r4, #25 ; 0x19 + 14110: e1a01003 mov r1, r3 + 14114: ebf5bced bl 0xffd834d0 + 14118: 08005acc stmeqda r0, {r2, r3, r6, r7, r9, fp, ip, lr} + 1411c: ebf5bf97 bl 0xffd83f80 + 14120: 08005acc stmeqda r0, {r2, r3, r6, r7, r9, fp, ip, lr} + 14124: e3b03022 movs r3, #34 ; 0x22 + 14128: ebf5bf94 bl 0xffd83f80 + 1412c: 08005ace stmeqda r0, {r1, r2, r3, r6, r7, r9, fp, ip, lr} + 14130: e0870003 add r0, r7, r3 + 14134: ebf5bde0 bl 0xffd838bc + 14138: 08005ad2 stmeqda r0, {r1, r4, r6, r7, r9, fp, ip, lr} + 1413c: e1a04000 mov r4, r0 + 14140: ebf5bf8e bl 0xffd83f80 + 14144: 08005ad0 stmeqda r0, {r4, r6, r7, r9, fp, ip, lr} + 14148: e1b04084 movs r4, r4, lsl #1 + 1414c: ebf5bf8b bl 0xffd83f80 + 14150: 08005ad2 stmeqda r0, {r1, r4, r6, r7, r9, fp, ip, lr} + 14154: e1a01007 mov r1, r7 + 14158: e2973000 adds r3, r7, #0 ; 0x0 + 1415c: ebf5bf87 bl 0xffd83f80 + 14160: 08005ad4 stmeqda r0, {r2, r4, r6, r7, r9, fp, ip, lr} + 14164: e1a01003 mov r1, r3 + 14168: e2933018 adds r3, r3, #24 ; 0x18 + 1416c: ebf5bf83 bl 0xffd83f80 + 14170: 08005ad6 stmeqda r0, {r1, r2, r4, r6, r7, r9, fp, ip, lr} + 14174: e1a01003 mov r1, r3 + 14178: e0933004 adds r3, r3, r4 + 1417c: ebf5bf7f bl 0xffd83f80 + 14180: 08005ad8 stmeqda r0, {r3, r4, r6, r7, r9, fp, ip, lr} + 14184: e2830000 add r0, r3, #0 ; 0x0 + 14188: ebf5bd8b bl 0xffd837bc + 1418c: 08005adc stmeqda r0, {r2, r3, r4, r6, r7, r9, fp, ip, lr} + 14190: e1a03000 mov r3, r0 + 14194: ebf5bf79 bl 0xffd83f80 + 14198: 08005ada stmeqda r0, {r1, r3, r4, r6, r7, r9, fp, ip, lr} + 1419c: e2870014 add r0, r7, #20 ; 0x14 + 141a0: ebf5bddc bl 0xffd83918 + 141a4: 08005ade stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, fp, ip, lr} + 141a8: e1a04000 mov r4, r0 + 141ac: ebf5bf73 bl 0xffd83f80 + 141b0: 08005adc stmeqda r0, {r2, r3, r4, r6, r7, r9, fp, ip, lr} + 141b4: e1b03103 movs r3, r3, lsl #2 + 141b8: ebf5bf70 bl 0xffd83f80 + 141bc: 08005ade stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, fp, ip, lr} + 141c0: e1a01003 mov r1, r3 + 141c4: e0933004 adds r3, r3, r4 + 141c8: ebf5bf6c bl 0xffd83f80 + 141cc: 08005ae0 stmeqda r0, {r5, r6, r7, r9, fp, ip, lr} + 141d0: e2830000 add r0, r3, #0 ; 0x0 + 141d4: ebf5bdcf bl 0xffd83918 + 141d8: 08005ae4 stmeqda r0, {r2, r5, r6, r7, r9, fp, ip, lr} + 141dc: e1a04000 mov r4, r0 + 141e0: ebf5bf66 bl 0xffd83f80 + 141e4: 08005ae2 stmeqda r0, {r1, r5, r6, r7, r9, fp, ip, lr} + 141e8: e1a01007 mov r1, r7 + 141ec: e2973000 adds r3, r7, #0 ; 0x0 + 141f0: ebf5bf62 bl 0xffd83f80 + 141f4: 08005ae4 stmeqda r0, {r2, r5, r6, r7, r9, fp, ip, lr} + 141f8: ebf5bf60 bl 0xffd83f80 + 141fc: 08005ae6 stmeqda r0, {r1, r2, r5, r6, r7, r9, fp, ip, lr} + 14200: e3a000e9 mov r0, #233 ; 0xe9 + 14204: e3800c5a orr r0, r0, #23040 ; 0x5a00 + 14208: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1420c: e58d0438 str r0, [sp, #1080] + 14210: e28cc068 add ip, ip, #104 ; 0x68 + 14214: e1a00fac mov r0, ip, lsr #31 + 14218: e08ff100 add pc, pc, r0, lsl #2 + 1421c: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 14220: ebf5bb4b bl 0xffd82f54 + 14224: eaffc318 b 0x4e8c + 14228: 08005af8 stmeqda r0, {r3, r4, r5, r6, r7, r9, fp, ip, lr} + 1422c: 00000000 andeq r0, r0, r0 + 14230: ebf5bf52 bl 0xffd83f80 + 14234: 08005af8 stmeqda r0, {r3, r4, r5, r6, r7, r9, fp, ip, lr} + 14238: e59d9434 ldr r9, [sp, #1076] + 1423c: e3c99003 bic r9, r9, #3 ; 0x3 + 14240: e2499010 sub r9, r9, #16 ; 0x10 + 14244: e58d9434 str r9, [sp, #1076] + 14248: e2890000 add r0, r9, #0 ; 0x0 + 1424c: e1a01007 mov r1, r7 + 14250: ebf5bcfd bl 0xffd8364c + 14254: e2890004 add r0, r9, #4 ; 0x4 + 14258: e1a01008 mov r1, r8 + 1425c: ebf5bcfa bl 0xffd8364c + 14260: e2890008 add r0, r9, #8 ; 0x8 + 14264: e59d1418 ldr r1, [sp, #1048] + 14268: ebf5bcf7 bl 0xffd8364c + 1426c: e289000c add r0, r9, #12 ; 0xc + 14270: e59d1438 ldr r1, [sp, #1080] + 14274: ebf5bcf4 bl 0xffd8364c + 14278: ebf5bf40 bl 0xffd83f80 + 1427c: 08005afa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, fp, ip, lr} + 14280: e59d1424 ldr r1, [sp, #1060] + 14284: e1a00001 mov r0, r1 + 14288: e58d0418 str r0, [sp, #1048] + 1428c: ebf5bf3b bl 0xffd83f80 + 14290: 08005afc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, fp, ip, lr} + 14294: e59d1420 ldr r1, [sp, #1056] + 14298: e1a08001 mov r8, r1 + 1429c: ebf5bf37 bl 0xffd83f80 + 142a0: 08005afe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, fp, ip, lr} + 142a4: e59d9434 ldr r9, [sp, #1076] + 142a8: e3c99003 bic r9, r9, #3 ; 0x3 + 142ac: e2499008 sub r9, r9, #8 ; 0x8 + 142b0: e58d9434 str r9, [sp, #1076] + 142b4: e2890000 add r0, r9, #0 ; 0x0 + 142b8: e1a01008 mov r1, r8 + 142bc: ebf5bce2 bl 0xffd8364c + 142c0: e2890004 add r0, r9, #4 ; 0x4 + 142c4: e59d1418 ldr r1, [sp, #1048] + 142c8: ebf5bcbf bl 0xffd835cc + 142cc: 08005b00 stmeqda r0, {r8, r9, fp, ip, lr} + 142d0: ebf5bf2a bl 0xffd83f80 + 142d4: 08005b00 stmeqda r0, {r8, r9, fp, ip, lr} + 142d8: e59d0434 ldr r0, [sp, #1076] + 142dc: e2400f01 sub r0, r0, #4 ; 0x4 + 142e0: e58d0434 str r0, [sp, #1076] + 142e4: ebf5bf25 bl 0xffd83f80 + 142e8: 08005b02 stmeqda r0, {r1, r8, r9, fp, ip, lr} + 142ec: e1a01003 mov r1, r3 + 142f0: e2930000 adds r0, r3, #0 ; 0x0 + 142f4: e58d0418 str r0, [sp, #1048] + 142f8: ebf5bf20 bl 0xffd83f80 + 142fc: 08005b04 stmeqda r0, {r2, r8, r9, fp, ip, lr} + 14300: e3a00ffa mov r0, #1000 ; 0x3e8 + 14304: e3800b16 orr r0, r0, #22528 ; 0x5800 + 14308: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1430c: ebf5bd81 bl 0xffd83918 + 14310: 08005b08 stmeqda r0, {r3, r8, r9, fp, ip, lr} + 14314: e1a04000 mov r4, r0 + 14318: ebf5bf18 bl 0xffd83f80 + 1431c: 08005b06 stmeqda r0, {r1, r2, r8, r9, fp, ip, lr} + 14320: e3a00ffb mov r0, #1004 ; 0x3ec + 14324: e3800b16 orr r0, r0, #22528 ; 0x5800 + 14328: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1432c: ebf5bd79 bl 0xffd83918 + 14330: 08005b0a stmeqda r0, {r1, r3, r8, r9, fp, ip, lr} + 14334: e1a05000 mov r5, r0 + 14338: ebf5bf10 bl 0xffd83f80 + 1433c: 08005b08 stmeqda r0, {r3, r8, r9, fp, ip, lr} + 14340: e1a01004 mov r1, r4 + 14344: e0943005 adds r3, r4, r5 + 14348: ebf5bf0c bl 0xffd83f80 + 1434c: 08005b0a stmeqda r0, {r1, r3, r8, r9, fp, ip, lr} + 14350: e3b06000 movs r6, #0 ; 0x0 + 14354: ebf5bf09 bl 0xffd83f80 + 14358: 08005b0c stmeqda r0, {r2, r3, r8, r9, fp, ip, lr} + 1435c: e2830000 add r0, r3, #0 ; 0x0 + 14360: e1a01006 mov r1, r6 + 14364: ebf5bc98 bl 0xffd835cc + 14368: 08005b0e stmeqda r0, {r1, r2, r3, r8, r9, fp, ip, lr} + 1436c: ebf5bf03 bl 0xffd83f80 + 14370: 08005b0e stmeqda r0, {r1, r2, r3, r8, r9, fp, ip, lr} + 14374: e3a00ebf mov r0, #3056 ; 0xbf0 + 14378: e3800a05 orr r0, r0, #20480 ; 0x5000 + 1437c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14380: ebf5bd64 bl 0xffd83918 + 14384: 08005b12 stmeqda r0, {r1, r4, r8, r9, fp, ip, lr} + 14388: e1a08000 mov r8, r0 + 1438c: ebf5befb bl 0xffd83f80 + 14390: 08005b10 stmeqda r0, {r4, r8, r9, fp, ip, lr} + 14394: e1a00008 mov r0, r8 + 14398: e58d0420 str r0, [sp, #1056] + 1439c: ebf5bef7 bl 0xffd83f80 + 143a0: 08005b12 stmeqda r0, {r1, r4, r8, r9, fp, ip, lr} + 143a4: e2880000 add r0, r8, #0 ; 0x0 + 143a8: ebf5bd2e bl 0xffd83868 + 143ac: 08005b16 stmeqda r0, {r1, r2, r4, r8, r9, fp, ip, lr} + 143b0: e1a05000 mov r5, r0 + 143b4: ebf5bef1 bl 0xffd83f80 + 143b8: 08005b14 stmeqda r0, {r2, r4, r8, r9, fp, ip, lr} + 143bc: e3a00ffd mov r0, #1012 ; 0x3f4 + 143c0: e3800b16 orr r0, r0, #22528 ; 0x5800 + 143c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 143c8: ebf5bd52 bl 0xffd83918 + 143cc: 08005b18 stmeqda r0, {r3, r4, r8, r9, fp, ip, lr} + 143d0: e1a03000 mov r3, r0 + 143d4: ebf5bee9 bl 0xffd83f80 + 143d8: 08005b16 stmeqda r0, {r1, r2, r4, r8, r9, fp, ip, lr} + 143dc: e1a01003 mov r1, r3 + 143e0: e0133005 ands r3, r3, r5 + 143e4: ebf5bee5 bl 0xffd83f80 + 143e8: 08005b18 stmeqda r0, {r3, r4, r8, r9, fp, ip, lr} + 143ec: e3b05000 movs r5, #0 ; 0x0 + 143f0: ebf5bee2 bl 0xffd83f80 + 143f4: 08005b1a stmeqda r0, {r1, r3, r4, r8, r9, fp, ip, lr} + 143f8: e1a00005 mov r0, r5 + 143fc: e58d0424 str r0, [sp, #1060] + 14400: ebf5bede bl 0xffd83f80 + 14404: 08005b1c stmeqda r0, {r2, r3, r4, r8, r9, fp, ip, lr} + 14408: e2880000 add r0, r8, #0 ; 0x0 + 1440c: e1a01003 mov r1, r3 + 14410: ebf5bc4d bl 0xffd8354c + 14414: 08005b1e stmeqda r0, {r1, r2, r3, r4, r8, r9, fp, ip, lr} + 14418: ebf5bed8 bl 0xffd83f80 + 1441c: 08005b1e stmeqda r0, {r1, r2, r3, r4, r8, r9, fp, ip, lr} + 14420: e3b08093 movs r8, #147 ; 0x93 + 14424: ebf5bed5 bl 0xffd83f80 + 14428: 08005b20 stmeqda r0, {r5, r8, r9, fp, ip, lr} + 1442c: e1b08288 movs r8, r8, lsl #5 + 14430: ebf5bed2 bl 0xffd83f80 + 14434: 08005b22 stmeqda r0, {r1, r5, r8, r9, fp, ip, lr} + 14438: e1a01004 mov r1, r4 + 1443c: e0945008 adds r5, r4, r8 + 14440: ebf5bece bl 0xffd83f80 + 14444: 08005b24 stmeqda r0, {r2, r5, r8, r9, fp, ip, lr} + 14448: e3b030d8 movs r3, #216 ; 0xd8 + 1444c: ebf5becb bl 0xffd83f80 + 14450: 08005b26 stmeqda r0, {r1, r2, r5, r8, r9, fp, ip, lr} + 14454: e1b03403 movs r3, r3, lsl #8 + 14458: ebf5bec8 bl 0xffd83f80 + 1445c: 08005b28 stmeqda r0, {r3, r5, r8, r9, fp, ip, lr} + 14460: e2850000 add r0, r5, #0 ; 0x0 + 14464: e1a01003 mov r1, r3 + 14468: ebf5bc37 bl 0xffd8354c + 1446c: 08005b2a stmeqda r0, {r1, r3, r5, r8, r9, fp, ip, lr} + 14470: ebf5bec2 bl 0xffd83f80 + 14474: 08005b2a stmeqda r0, {r1, r3, r5, r8, r9, fp, ip, lr} + 14478: e3b03095 movs r3, #149 ; 0x95 + 1447c: ebf5bebf bl 0xffd83f80 + 14480: 08005b2c stmeqda r0, {r2, r3, r5, r8, r9, fp, ip, lr} + 14484: e1b03283 movs r3, r3, lsl #5 + 14488: ebf5bebc bl 0xffd83f80 + 1448c: 08005b2e stmeqda r0, {r1, r2, r3, r5, r8, r9, fp, ip, lr} + 14490: e1a01004 mov r1, r4 + 14494: e0945003 adds r5, r4, r3 + 14498: ebf5beb8 bl 0xffd83f80 + 1449c: 08005b30 stmeqda r0, {r4, r5, r8, r9, fp, ip, lr} + 144a0: e3b030f8 movs r3, #248 ; 0xf8 + 144a4: ebf5beb5 bl 0xffd83f80 + 144a8: 08005b32 stmeqda r0, {r1, r4, r5, r8, r9, fp, ip, lr} + 144ac: e1b03403 movs r3, r3, lsl #8 + 144b0: ebf5beb2 bl 0xffd83f80 + 144b4: 08005b34 stmeqda r0, {r2, r4, r5, r8, r9, fp, ip, lr} + 144b8: e2850000 add r0, r5, #0 ; 0x0 + 144bc: e1a01003 mov r1, r3 + 144c0: ebf5bc21 bl 0xffd8354c + 144c4: 08005b36 stmeqda r0, {r1, r2, r4, r5, r8, r9, fp, ip, lr} + 144c8: ebf5beac bl 0xffd83f80 + 144cc: 08005b36 stmeqda r0, {r1, r2, r4, r5, r8, r9, fp, ip, lr} + 144d0: e3b05099 movs r5, #153 ; 0x99 + 144d4: ebf5bea9 bl 0xffd83f80 + 144d8: 08005b38 stmeqda r0, {r3, r4, r5, r8, r9, fp, ip, lr} + 144dc: e1b05285 movs r5, r5, lsl #5 + 144e0: ebf5bea6 bl 0xffd83f80 + 144e4: 08005b3a stmeqda r0, {r1, r3, r4, r5, r8, r9, fp, ip, lr} + 144e8: e1a01004 mov r1, r4 + 144ec: e0943005 adds r3, r4, r5 + 144f0: ebf5bea2 bl 0xffd83f80 + 144f4: 08005b3c stmeqda r0, {r2, r3, r4, r5, r8, r9, fp, ip, lr} + 144f8: e2830000 add r0, r3, #0 ; 0x0 + 144fc: e1a01006 mov r1, r6 + 14500: ebf5bc11 bl 0xffd8354c + 14504: 08005b3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, fp, ip, lr} + 14508: ebf5be9c bl 0xffd83f80 + 1450c: 08005b3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, fp, ip, lr} + 14510: e1a01008 mov r1, r8 + 14514: e2988080 adds r8, r8, #128 ; 0x80 + 14518: ebf5be98 bl 0xffd83f80 + 1451c: 08005b40 stmeqda r0, {r6, r8, r9, fp, ip, lr} + 14520: e1a01004 mov r1, r4 + 14524: e0943008 adds r3, r4, r8 + 14528: ebf5be94 bl 0xffd83f80 + 1452c: 08005b42 stmeqda r0, {r1, r6, r8, r9, fp, ip, lr} + 14530: e2830000 add r0, r3, #0 ; 0x0 + 14534: e1a01006 mov r1, r6 + 14538: ebf5bc03 bl 0xffd8354c + 1453c: 08005b44 stmeqda r0, {r2, r6, r8, r9, fp, ip, lr} + 14540: ebf5be8e bl 0xffd83f80 + 14544: 08005b44 stmeqda r0, {r2, r6, r8, r9, fp, ip, lr} + 14548: e3a00ffe mov r0, #1016 ; 0x3f8 + 1454c: e3800b16 orr r0, r0, #22528 ; 0x5800 + 14550: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14554: ebf5bcef bl 0xffd83918 + 14558: 08005b48 stmeqda r0, {r3, r6, r8, r9, fp, ip, lr} + 1455c: e1a03000 mov r3, r0 + 14560: ebf5be86 bl 0xffd83f80 + 14564: 08005b46 stmeqda r0, {r1, r2, r6, r8, r9, fp, ip, lr} + 14568: e1a01004 mov r1, r4 + 1456c: e0945003 adds r5, r4, r3 + 14570: ebf5be82 bl 0xffd83f80 + 14574: 08005b48 stmeqda r0, {r3, r6, r8, r9, fp, ip, lr} + 14578: e3b03084 movs r3, #132 ; 0x84 + 1457c: ebf5be7f bl 0xffd83f80 + 14580: 08005b4a stmeqda r0, {r1, r3, r6, r8, r9, fp, ip, lr} + 14584: e2850000 add r0, r5, #0 ; 0x0 + 14588: e1a01003 mov r1, r3 + 1458c: ebf5bbee bl 0xffd8354c + 14590: 08005b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, ip, lr} + 14594: ebf5be79 bl 0xffd83f80 + 14598: 08005b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, ip, lr} + 1459c: e1a01008 mov r1, r8 + 145a0: e258803e subs r8, r8, #62 ; 0x3e + 145a4: ebf5be75 bl 0xffd83f80 + 145a8: 08005b4e stmeqda r0, {r1, r2, r3, r6, r8, r9, fp, ip, lr} + 145ac: e1a01004 mov r1, r4 + 145b0: e0945008 adds r5, r4, r8 + 145b4: ebf5be71 bl 0xffd83f80 + 145b8: 08005b50 stmeqda r0, {r4, r6, r8, r9, fp, ip, lr} + 145bc: e3a00fff mov r0, #1020 ; 0x3fc + 145c0: e3800b16 orr r0, r0, #22528 ; 0x5800 + 145c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 145c8: ebf5bcd2 bl 0xffd83918 + 145cc: 08005b54 stmeqda r0, {r2, r4, r6, r8, r9, fp, ip, lr} + 145d0: e1a03000 mov r3, r0 + 145d4: ebf5be69 bl 0xffd83f80 + 145d8: 08005b52 stmeqda r0, {r1, r4, r6, r8, r9, fp, ip, lr} + 145dc: e2850000 add r0, r5, #0 ; 0x0 + 145e0: e1a01003 mov r1, r3 + 145e4: ebf5bbd8 bl 0xffd8354c + 145e8: 08005b54 stmeqda r0, {r2, r4, r6, r8, r9, fp, ip, lr} + 145ec: ebf5be63 bl 0xffd83f80 + 145f0: 08005b54 stmeqda r0, {r2, r4, r6, r8, r9, fp, ip, lr} + 145f4: e3a00b17 mov r0, #23552 ; 0x5c00 + 145f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 145fc: ebf5bcc5 bl 0xffd83918 + 14600: 08005b58 stmeqda r0, {r3, r4, r6, r8, r9, fp, ip, lr} + 14604: e1a03000 mov r3, r0 + 14608: ebf5be5c bl 0xffd83f80 + 1460c: 08005b56 stmeqda r0, {r1, r2, r4, r6, r8, r9, fp, ip, lr} + 14610: e1a01004 mov r1, r4 + 14614: e0947003 adds r7, r4, r3 + 14618: ebf5be58 bl 0xffd83f80 + 1461c: 08005b58 stmeqda r0, {r3, r4, r6, r8, r9, fp, ip, lr} + 14620: e1a01008 mov r1, r8 + 14624: e2588026 subs r8, r8, #38 ; 0x26 + 14628: ebf5be54 bl 0xffd83f80 + 1462c: 08005b5a stmeqda r0, {r1, r3, r4, r6, r8, r9, fp, ip, lr} + 14630: e1a01004 mov r1, r4 + 14634: e0945008 adds r5, r4, r8 + 14638: ebf5be50 bl 0xffd83f80 + 1463c: 08005b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, ip, lr} + 14640: e1a01008 mov r1, r8 + 14644: e298803c adds r8, r8, #60 ; 0x3c + 14648: ebf5be4c bl 0xffd83f80 + 1464c: 08005b5e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, fp, ip, lr} + 14650: e1a01004 mov r1, r4 + 14654: e0943008 adds r3, r4, r8 + 14658: ebf5be48 bl 0xffd83f80 + 1465c: 08005b60 stmeqda r0, {r5, r6, r8, r9, fp, ip, lr} + 14660: e1a01008 mov r1, r8 + 14664: e2988004 adds r8, r8, #4 ; 0x4 + 14668: ebf5be44 bl 0xffd83f80 + 1466c: 08005b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, ip, lr} + 14670: e1a01004 mov r1, r4 + 14674: e0944008 adds r4, r4, r8 + 14678: ebf5be40 bl 0xffd83f80 + 1467c: 08005b64 stmeqda r0, {r2, r5, r6, r8, r9, fp, ip, lr} + 14680: e2840000 add r0, r4, #0 ; 0x0 + 14684: e1a01006 mov r1, r6 + 14688: ebf5bbcf bl 0xffd835cc + 1468c: 08005b66 stmeqda r0, {r1, r2, r5, r6, r8, r9, fp, ip, lr} + 14690: ebf5be3a bl 0xffd83f80 + 14694: 08005b66 stmeqda r0, {r1, r2, r5, r6, r8, r9, fp, ip, lr} + 14698: e2830000 add r0, r3, #0 ; 0x0 + 1469c: e1a01006 mov r1, r6 + 146a0: ebf5bbc9 bl 0xffd835cc + 146a4: 08005b68 stmeqda r0, {r3, r5, r6, r8, r9, fp, ip, lr} + 146a8: ebf5be34 bl 0xffd83f80 + 146ac: 08005b68 stmeqda r0, {r3, r5, r6, r8, r9, fp, ip, lr} + 146b0: e2850000 add r0, r5, #0 ; 0x0 + 146b4: e1a01006 mov r1, r6 + 146b8: ebf5bbc3 bl 0xffd835cc + 146bc: 08005b6a stmeqda r0, {r1, r3, r5, r6, r8, r9, fp, ip, lr} + 146c0: ebf5be2e bl 0xffd83f80 + 146c4: 08005b6a stmeqda r0, {r1, r3, r5, r6, r8, r9, fp, ip, lr} + 146c8: e2870000 add r0, r7, #0 ; 0x0 + 146cc: e1a01006 mov r1, r6 + 146d0: ebf5bbbd bl 0xffd835cc + 146d4: 08005b6c stmeqda r0, {r2, r3, r5, r6, r8, r9, fp, ip, lr} + 146d8: ebf5be28 bl 0xffd83f80 + 146dc: 08005b6c stmeqda r0, {r2, r3, r5, r6, r8, r9, fp, ip, lr} + 146e0: e3a00f01 mov r0, #4 ; 0x4 + 146e4: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 146e8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 146ec: ebf5bc89 bl 0xffd83918 + 146f0: 08005b70 stmeqda r0, {r4, r5, r6, r8, r9, fp, ip, lr} + 146f4: e1a04000 mov r4, r0 + 146f8: ebf5be20 bl 0xffd83f80 + 146fc: 08005b6e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, fp, ip, lr} + 14700: e3a00f02 mov r0, #8 ; 0x8 + 14704: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 14708: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1470c: ebf5bc81 bl 0xffd83918 + 14710: 08005b72 stmeqda r0, {r1, r4, r5, r6, r8, r9, fp, ip, lr} + 14714: e1a05000 mov r5, r0 + 14718: ebf5be18 bl 0xffd83f80 + 1471c: 08005b70 stmeqda r0, {r4, r5, r6, r8, r9, fp, ip, lr} + 14720: e3a00f03 mov r0, #12 ; 0xc + 14724: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 14728: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1472c: ebf5bc79 bl 0xffd83918 + 14730: 08005b74 stmeqda r0, {r2, r4, r5, r6, r8, r9, fp, ip, lr} + 14734: e1a06000 mov r6, r0 + 14738: ebf5be10 bl 0xffd83f80 + 1473c: 08005b72 stmeqda r0, {r1, r4, r5, r6, r8, r9, fp, ip, lr} + 14740: e3b07010 movs r7, #16 ; 0x10 + 14744: ebf5be0d bl 0xffd83f80 + 14748: 08005b74 stmeqda r0, {r2, r4, r5, r6, r8, r9, fp, ip, lr} + 1474c: e59d0434 ldr r0, [sp, #1076] + 14750: e2800f00 add r0, r0, #0 ; 0x0 + 14754: e1a01007 mov r1, r7 + 14758: ebf5bb9b bl 0xffd835cc + 1475c: 08005b76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, fp, ip, lr} + 14760: ebf5be06 bl 0xffd83f80 + 14764: 08005b76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, fp, ip, lr} + 14768: e3b03001 movs r3, #1 ; 0x1 + 1476c: ebf5be03 bl 0xffd83f80 + 14770: 08005b78 stmeqda r0, {r3, r4, r5, r6, r8, r9, fp, ip, lr} + 14774: ebf5be01 bl 0xffd83f80 + 14778: 08005b7a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, fp, ip, lr} + 1477c: e3a0007d mov r0, #125 ; 0x7d + 14780: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 14784: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14788: e58d0438 str r0, [sp, #1080] + 1478c: e28cc0ee add ip, ip, #238 ; 0xee + 14790: e1a00fac mov r0, ip, lsr #31 + 14794: e08ff100 add pc, pc, r0, lsl #2 + 14798: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 1479c: ebf5b9ec bl 0xffd82f54 + 147a0: ea000001 b 0x147ac + 147a4: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 147a8: 00000000 andeq r0, r0, r0 + 147ac: ebf5bdf3 bl 0xffd83f80 + 147b0: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 147b4: e59d9434 ldr r9, [sp, #1076] + 147b8: e3c99003 bic r9, r9, #3 ; 0x3 + 147bc: e2499010 sub r9, r9, #16 ; 0x10 + 147c0: e58d9434 str r9, [sp, #1076] + 147c4: e2890000 add r0, r9, #0 ; 0x0 + 147c8: e1a01007 mov r1, r7 + 147cc: ebf5bb9e bl 0xffd8364c + 147d0: e2890004 add r0, r9, #4 ; 0x4 + 147d4: e1a01008 mov r1, r8 + 147d8: ebf5bb9b bl 0xffd8364c + 147dc: e2890008 add r0, r9, #8 ; 0x8 + 147e0: e59d1418 ldr r1, [sp, #1048] + 147e4: ebf5bb98 bl 0xffd8364c + 147e8: e289000c add r0, r9, #12 ; 0xc + 147ec: e59d1438 ldr r1, [sp, #1080] + 147f0: ebf5bb95 bl 0xffd8364c + 147f4: ebf5bde1 bl 0xffd83f80 + 147f8: 08000e9a stmeqda r0, {r1, r3, r4, r7, r9, sl, fp} + 147fc: e59d1420 ldr r1, [sp, #1056] + 14800: e1a00001 mov r0, r1 + 14804: e58d0418 str r0, [sp, #1048] + 14808: ebf5bddc bl 0xffd83f80 + 1480c: 08000e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp} + 14810: e59d9434 ldr r9, [sp, #1076] + 14814: e3c99003 bic r9, r9, #3 ; 0x3 + 14818: e2499004 sub r9, r9, #4 ; 0x4 + 1481c: e58d9434 str r9, [sp, #1076] + 14820: e2890000 add r0, r9, #0 ; 0x0 + 14824: e59d1418 ldr r1, [sp, #1048] + 14828: ebf5bb67 bl 0xffd835cc + 1482c: 08000e9e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, fp} + 14830: ebf5bdd2 bl 0xffd83f80 + 14834: 08000e9e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, fp} + 14838: e1a01003 mov r1, r3 + 1483c: e2938000 adds r8, r3, #0 ; 0x0 + 14840: ebf5bdce bl 0xffd83f80 + 14844: 08000ea0 stmeqda r0, {r5, r7, r9, sl, fp} + 14848: e1a01004 mov r1, r4 + 1484c: e2940000 adds r0, r4, #0 ; 0x0 + 14850: e58d0418 str r0, [sp, #1048] + 14854: ebf5bdc9 bl 0xffd83f80 + 14858: 08000ea2 stmeqda r0, {r1, r5, r7, r9, sl, fp} + 1485c: e1a00005 mov r0, r5 + 14860: e58d0420 str r0, [sp, #1056] + 14864: ebf5bdc5 bl 0xffd83f80 + 14868: 08000ea4 stmeqda r0, {r2, r5, r7, r9, sl, fp} + 1486c: e1a01006 mov r1, r6 + 14870: e2963000 adds r3, r6, #0 ; 0x0 + 14874: ebf5bdc1 bl 0xffd83f80 + 14878: 08000ea6 stmeqda r0, {r1, r2, r5, r7, r9, sl, fp} + 1487c: e59d0434 ldr r0, [sp, #1076] + 14880: e2800f05 add r0, r0, #20 ; 0x14 + 14884: ebf5bc23 bl 0xffd83918 + 14888: 08000eaa stmeqda r0, {r1, r3, r5, r7, r9, sl, fp} + 1488c: e1a04000 mov r4, r0 + 14890: ebf5bdba bl 0xffd83f80 + 14894: 08000ea8 stmeqda r0, {r3, r5, r7, r9, sl, fp} + 14898: e3b07080 movs r7, #128 ; 0x80 + 1489c: ebf5bdb7 bl 0xffd83f80 + 148a0: 08000eaa stmeqda r0, {r1, r3, r5, r7, r9, sl, fp} + 148a4: e1b07c07 movs r7, r7, lsl #24 + 148a8: ebf5bdb4 bl 0xffd83f80 + 148ac: 08000eac stmeqda r0, {r2, r3, r5, r7, r9, sl, fp} + 148b0: e3a00fb6 mov r0, #728 ; 0x2d8 + 148b4: e3800b03 orr r0, r0, #3072 ; 0xc00 + 148b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 148bc: ebf5bc15 bl 0xffd83918 + 148c0: 08000eb0 stmeqda r0, {r4, r5, r7, r9, sl, fp} + 148c4: e1a06000 mov r6, r0 + 148c8: ebf5bdac bl 0xffd83f80 + 148cc: 08000eae stmeqda r0, {r1, r2, r3, r5, r7, r9, sl, fp} + 148d0: e1b052c4 movs r5, r4, asr #5 + 148d4: ebf5bda9 bl 0xffd83f80 + 148d8: 08000eb0 stmeqda r0, {r4, r5, r7, r9, sl, fp} + 148dc: e1b05105 movs r5, r5, lsl #2 + 148e0: ebf5bda6 bl 0xffd83f80 + 148e4: 08000eb2 stmeqda r0, {r1, r4, r5, r7, r9, sl, fp} + 148e8: e1a01005 mov r1, r5 + 148ec: e0955006 adds r5, r5, r6 + 148f0: ebf5bda2 bl 0xffd83f80 + 148f4: 08000eb4 stmeqda r0, {r2, r4, r5, r7, r9, sl, fp} + 148f8: e2850000 add r0, r5, #0 ; 0x0 + 148fc: ebf5bc05 bl 0xffd83918 + 14900: 08000eb8 stmeqda r0, {r3, r4, r5, r7, r9, sl, fp} + 14904: e1a05000 mov r5, r0 + 14908: ebf5bd9c bl 0xffd83f80 + 1490c: 08000eb6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sl, fp} + 14910: e1a01007 mov r1, r7 + 14914: e1977005 orrs r7, r7, r5 + 14918: ebf5bd98 bl 0xffd83f80 + 1491c: 08000eb8 stmeqda r0, {r3, r4, r5, r7, r9, sl, fp} + 14920: e1b041c4 movs r4, r4, asr #3 + 14924: ebf5bd95 bl 0xffd83f80 + 14928: 08000eba stmeqda r0, {r1, r3, r4, r5, r7, r9, sl, fp} + 1492c: ebf5bd93 bl 0xffd83f80 + 14930: 08000ebc stmeqda r0, {r2, r3, r4, r5, r7, r9, sl, fp} + 14934: e3a000bf mov r0, #191 ; 0xbf + 14938: e3800c0e orr r0, r0, #3584 ; 0xe00 + 1493c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14940: e58d0438 str r0, [sp, #1080] + 14944: e28cc043 add ip, ip, #67 ; 0x43 + 14948: e1a00fac mov r0, ip, lsr #31 + 1494c: e08ff100 add pc, pc, r0, lsl #2 + 14950: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 14954: ebf5b97e bl 0xffd82f54 + 14958: eaffb668 b 0x2300 + 1495c: 08000ebe stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sl, fp} + 14960: 00000000 andeq r0, r0, r0 + 14964: ebf5bd85 bl 0xffd83f80 + 14968: 08000ebe stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sl, fp} + 1496c: e1a01007 mov r1, r7 + 14970: e1977003 orrs r7, r7, r3 + 14974: ebf5bd81 bl 0xffd83f80 + 14978: 08000ec0 stmeqda r0, {r6, r7, r9, sl, fp} + 1497c: e1a01008 mov r1, r8 + 14980: e2983000 adds r3, r8, #0 ; 0x0 + 14984: ebf5bd7d bl 0xffd83f80 + 14988: 08000ec2 stmeqda r0, {r1, r6, r7, r9, sl, fp} + 1498c: e59d1418 ldr r1, [sp, #1048] + 14990: e59d1418 ldr r1, [sp, #1048] + 14994: e2914000 adds r4, r1, #0 ; 0x0 + 14998: ebf5bd78 bl 0xffd83f80 + 1499c: 08000ec4 stmeqda r0, {r2, r6, r7, r9, sl, fp} + 149a0: e59d1420 ldr r1, [sp, #1056] + 149a4: e1a05001 mov r5, r1 + 149a8: ebf5bd74 bl 0xffd83f80 + 149ac: 08000ec6 stmeqda r0, {r1, r2, r6, r7, r9, sl, fp} + 149b0: e1a01007 mov r1, r7 + 149b4: e2976000 adds r6, r7, #0 ; 0x0 + 149b8: ebf5bd70 bl 0xffd83f80 + 149bc: 08000ec8 stmeqda r0, {r3, r6, r7, r9, sl, fp} + 149c0: ebf5bd6e bl 0xffd83f80 + 149c4: 08000eca stmeqda r0, {r1, r3, r6, r7, r9, sl, fp} + 149c8: e3a000cd mov r0, #205 ; 0xcd + 149cc: e3800c0e orr r0, r0, #3584 ; 0xe00 + 149d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 149d4: e58d0438 str r0, [sp, #1080] + 149d8: e28cc015 add ip, ip, #21 ; 0x15 + 149dc: e1a00fac mov r0, ip, lsr #31 + 149e0: e08ff100 add pc, pc, r0, lsl #2 + 149e4: 08000df8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, fp} + 149e8: ebf5b959 bl 0xffd82f54 + 149ec: ea000001 b 0x149f8 + 149f0: 08000df8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, fp} + 149f4: 00000000 andeq r0, r0, r0 + 149f8: ebf5bd60 bl 0xffd83f80 + 149fc: 08000df8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, fp} + 14a00: e59d9434 ldr r9, [sp, #1076] + 14a04: e3c99003 bic r9, r9, #3 ; 0x3 + 14a08: e2499014 sub r9, r9, #20 ; 0x14 + 14a0c: e58d9434 str r9, [sp, #1076] + 14a10: e2890000 add r0, r9, #0 ; 0x0 + 14a14: e1a01007 mov r1, r7 + 14a18: ebf5bb0b bl 0xffd8364c + 14a1c: e2890004 add r0, r9, #4 ; 0x4 + 14a20: e1a01008 mov r1, r8 + 14a24: ebf5bb08 bl 0xffd8364c + 14a28: e2890008 add r0, r9, #8 ; 0x8 + 14a2c: e59d1418 ldr r1, [sp, #1048] + 14a30: ebf5bb05 bl 0xffd8364c + 14a34: e289000c add r0, r9, #12 ; 0xc + 14a38: e59d141c ldr r1, [sp, #1052] + 14a3c: ebf5bb02 bl 0xffd8364c + 14a40: e2890010 add r0, r9, #16 ; 0x10 + 14a44: e59d1438 ldr r1, [sp, #1080] + 14a48: ebf5baff bl 0xffd8364c + 14a4c: ebf5bd4b bl 0xffd83f80 + 14a50: 08000dfa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, sl, fp} + 14a54: e59d1424 ldr r1, [sp, #1060] + 14a58: e1a00001 mov r0, r1 + 14a5c: e58d041c str r0, [sp, #1052] + 14a60: ebf5bd46 bl 0xffd83f80 + 14a64: 08000dfc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl, fp} + 14a68: e59d1420 ldr r1, [sp, #1056] + 14a6c: e1a00001 mov r0, r1 + 14a70: e58d0418 str r0, [sp, #1048] + 14a74: ebf5bd41 bl 0xffd83f80 + 14a78: 08000dfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl, fp} + 14a7c: e59d9434 ldr r9, [sp, #1076] + 14a80: e3c99003 bic r9, r9, #3 ; 0x3 + 14a84: e2499008 sub r9, r9, #8 ; 0x8 + 14a88: e58d9434 str r9, [sp, #1076] + 14a8c: e2890000 add r0, r9, #0 ; 0x0 + 14a90: e59d1418 ldr r1, [sp, #1048] + 14a94: ebf5baec bl 0xffd8364c + 14a98: e2890004 add r0, r9, #4 ; 0x4 + 14a9c: e59d141c ldr r1, [sp, #1052] + 14aa0: ebf5bac9 bl 0xffd835cc + 14aa4: 08000e00 stmeqda r0, {r9, sl, fp} + 14aa8: ebf5bd34 bl 0xffd83f80 + 14aac: 08000e00 stmeqda r0, {r9, sl, fp} + 14ab0: e1a01004 mov r1, r4 + 14ab4: e2940000 adds r0, r4, #0 ; 0x0 + 14ab8: e58d0418 str r0, [sp, #1048] + 14abc: ebf5bd2f bl 0xffd83f80 + 14ac0: 08000e02 stmeqda r0, {r1, r9, sl, fp} + 14ac4: e1a01005 mov r1, r5 + 14ac8: e2950000 adds r0, r5, #0 ; 0x0 + 14acc: e58d041c str r0, [sp, #1052] + 14ad0: ebf5bd2a bl 0xffd83f80 + 14ad4: 08000e04 stmeqda r0, {r2, r9, sl, fp} + 14ad8: e1a00006 mov r0, r6 + 14adc: e58d0420 str r0, [sp, #1056] + 14ae0: ebf5bd26 bl 0xffd83f80 + 14ae4: 08000e06 stmeqda r0, {r1, r2, r9, sl, fp} + 14ae8: e3b07003 movs r7, #3 ; 0x3 + 14aec: ebf5bd23 bl 0xffd83f80 + 14af0: 08000e08 stmeqda r0, {r3, r9, sl, fp} + 14af4: e1a01007 mov r1, r7 + 14af8: e0177003 ands r7, r7, r3 + 14afc: ebf5bd1f bl 0xffd83f80 + 14b00: 08000e0a stmeqda r0, {r1, r3, r9, sl, fp} + 14b04: e3b040c0 movs r4, #192 ; 0xc0 + 14b08: ebf5bd1c bl 0xffd83f80 + 14b0c: 08000e0c stmeqda r0, {r2, r3, r9, sl, fp} + 14b10: e1b04504 movs r4, r4, lsl #10 + 14b14: ebf5bd19 bl 0xffd83f80 + 14b18: 08000e0e stmeqda r0, {r1, r2, r3, r9, sl, fp} + 14b1c: e1a01004 mov r1, r4 + 14b20: e0144003 ands r4, r4, r3 + 14b24: ebf5bd15 bl 0xffd83f80 + 14b28: 08000e10 stmeqda r0, {r4, r9, sl, fp} + 14b2c: e1b08824 movs r8, r4, lsr #16 + 14b30: ebf5bd12 bl 0xffd83f80 + 14b34: 08000e12 stmeqda r0, {r1, r4, r9, sl, fp} + 14b38: e3a00f8a mov r0, #552 ; 0x228 + 14b3c: e3800b03 orr r0, r0, #3072 ; 0xc00 + 14b40: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14b44: ebf5bb73 bl 0xffd83918 + 14b48: 08000e16 stmeqda r0, {r1, r2, r4, r9, sl, fp} + 14b4c: e1a03000 mov r3, r0 + 14b50: ebf5bd0a bl 0xffd83f80 + 14b54: 08000e14 stmeqda r0, {r2, r4, r9, sl, fp} + 14b58: e1a00003 mov r0, r3 + 14b5c: e58d0424 str r0, [sp, #1060] + 14b60: ebf5bd06 bl 0xffd83f80 + 14b64: 08000e16 stmeqda r0, {r1, r2, r4, r9, sl, fp} + 14b68: ebf5bd04 bl 0xffd83f80 + 14b6c: 08000e18 stmeqda r0, {r3, r4, r9, sl, fp} + 14b70: e3a0001b mov r0, #27 ; 0x1b + 14b74: e3800c0e orr r0, r0, #3584 ; 0xe00 + 14b78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14b7c: e58d0438 str r0, [sp, #1080] + 14b80: e28cc03b add ip, ip, #59 ; 0x3b + 14b84: e1a00fac mov r0, ip, lsr #31 + 14b88: e08ff100 add pc, pc, r0, lsl #2 + 14b8c: 08000dc4 stmeqda r0, {r2, r6, r7, r8, sl, fp} + 14b90: ebf5b8ef bl 0xffd82f54 + 14b94: ea000001 b 0x14ba0 + 14b98: 08000dc4 stmeqda r0, {r2, r6, r7, r8, sl, fp} + 14b9c: 00000000 andeq r0, r0, r0 + 14ba0: ebf5bcf6 bl 0xffd83f80 + 14ba4: 08000dc4 stmeqda r0, {r2, r6, r7, r8, sl, fp} + 14ba8: e1a01003 mov r1, r3 + 14bac: e2935000 adds r5, r3, #0 ; 0x0 + 14bb0: ebf5bcf2 bl 0xffd83f80 + 14bb4: 08000dc6 stmeqda r0, {r1, r2, r6, r7, r8, sl, fp} + 14bb8: e2850000 add r0, r5, #0 ; 0x0 + 14bbc: ebf5bb55 bl 0xffd83918 + 14bc0: 08000dca stmeqda r0, {r1, r3, r6, r7, r8, sl, fp} + 14bc4: e1a04000 mov r4, r0 + 14bc8: ebf5bcec bl 0xffd83f80 + 14bcc: 08000dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp} + 14bd0: e3540000 cmp r4, #0 ; 0x0 + 14bd4: ebf5bce9 bl 0xffd83f80 + 14bd8: 08000dca stmeqda r0, {r1, r3, r6, r7, r8, sl, fp} + 14bdc: e28cc00e add ip, ip, #14 ; 0xe + 14be0: 1a000004 bne 0x14bf8 + 14be4: e1a00fac mov r0, ip, lsr #31 + 14be8: e08ff100 add pc, pc, r0, lsl #2 + 14bec: 08000dd4 stmeqda r0, {r2, r4, r6, r7, r8, sl, fp} + 14bf0: ebf5b8d7 bl 0xffd82f54 + 14bf4: ea000015 b 0x14c50 + 14bf8: ebf5bce0 bl 0xffd83f80 + 14bfc: 08000dcc stmeqda r0, {r2, r3, r6, r7, r8, sl, fp} + 14c00: e284000c add r0, r4, #12 ; 0xc + 14c04: ebf5bb43 bl 0xffd83918 + 14c08: 08000dd0 stmeqda r0, {r4, r6, r7, r8, sl, fp} + 14c0c: e1a03000 mov r3, r0 + 14c10: ebf5bcda bl 0xffd83f80 + 14c14: 08000dce stmeqda r0, {r1, r2, r3, r6, r7, r8, sl, fp} + 14c18: e2850000 add r0, r5, #0 ; 0x0 + 14c1c: e1a01003 mov r1, r3 + 14c20: ebf5ba69 bl 0xffd835cc + 14c24: 08000dd0 stmeqda r0, {r4, r6, r7, r8, sl, fp} + 14c28: ebf5bcd4 bl 0xffd83f80 + 14c2c: 08000dd0 stmeqda r0, {r4, r6, r7, r8, sl, fp} + 14c30: e3b03000 movs r3, #0 ; 0x0 + 14c34: ebf5bcd1 bl 0xffd83f80 + 14c38: 08000dd2 stmeqda r0, {r1, r4, r6, r7, r8, sl, fp} + 14c3c: e284000c add r0, r4, #12 ; 0xc + 14c40: e1a01003 mov r1, r3 + 14c44: ebf5ba60 bl 0xffd835cc + 14c48: 08000dd4 stmeqda r0, {r2, r4, r6, r7, r8, sl, fp} + 14c4c: e28cc010 add ip, ip, #16 ; 0x10 + 14c50: ebf5bcca bl 0xffd83f80 + 14c54: 08000dd4 stmeqda r0, {r2, r4, r6, r7, r8, sl, fp} + 14c58: e1a01004 mov r1, r4 + 14c5c: e2943000 adds r3, r4, #0 ; 0x0 + 14c60: ebf5bcc6 bl 0xffd83f80 + 14c64: 08000dd6 stmeqda r0, {r1, r2, r4, r6, r7, r8, sl, fp} + 14c68: e59d0438 ldr r0, [sp, #1080] + 14c6c: e28cc006 add ip, ip, #6 ; 0x6 + 14c70: eaf5b916 b 0xffd830d0 + 14c74: 08000e1a stmeqda r0, {r1, r3, r4, r9, sl, fp} + 14c78: 00000000 andeq r0, r0, r0 + 14c7c: ebf5bcbf bl 0xffd83f80 + 14c80: 08000e1a stmeqda r0, {r1, r3, r4, r9, sl, fp} + 14c84: e1a01003 mov r1, r3 + 14c88: e2936000 adds r6, r3, #0 ; 0x0 + 14c8c: ebf5bcbb bl 0xffd83f80 + 14c90: 08000e1c stmeqda r0, {r2, r3, r4, r9, sl, fp} + 14c94: e3560000 cmp r6, #0 ; 0x0 + 14c98: ebf5bcb8 bl 0xffd83f80 + 14c9c: 08000e1e stmeqda r0, {r1, r2, r3, r4, r9, sl, fp} + 14ca0: e28cc009 add ip, ip, #9 ; 0x9 + 14ca4: 0a000004 beq 0x14cbc + 14ca8: e1a00fac mov r0, ip, lsr #31 + 14cac: e08ff100 add pc, pc, r0, lsl #2 + 14cb0: 08000e2c stmeqda r0, {r2, r3, r5, r9, sl, fp} + 14cb4: ebf5b8a6 bl 0xffd82f54 + 14cb8: ea000010 b 0x14d00 + 14cbc: ebf5bcaf bl 0xffd83f80 + 14cc0: 08000e20 stmeqda r0, {r5, r9, sl, fp} + 14cc4: e3b03001 movs r3, #1 ; 0x1 + 14cc8: ebf5bcac bl 0xffd83f80 + 14ccc: 08000e22 stmeqda r0, {r1, r5, r9, sl, fp} + 14cd0: e3a01000 mov r1, #0 ; 0x0 + 14cd4: e0513003 subs r3, r1, r3 + 14cd8: ebf5bca8 bl 0xffd83f80 + 14cdc: 08000e24 stmeqda r0, {r2, r5, r9, sl, fp} + 14ce0: e28cc009 add ip, ip, #9 ; 0x9 + 14ce4: e1a00fac mov r0, ip, lsr #31 + 14ce8: e08ff100 add pc, pc, r0, lsl #2 + 14cec: 08000e48 stmeqda r0, {r3, r6, r9, sl, fp} + 14cf0: ebf5b897 bl 0xffd82f54 + 14cf4: ea0000bb b 0x14fe8 + 14cf8: 08000e2c stmeqda r0, {r2, r3, r5, r9, sl, fp} + 14cfc: 00000000 andeq r0, r0, r0 + 14d00: ebf5bc9e bl 0xffd83f80 + 14d04: 08000e2c stmeqda r0, {r2, r3, r5, r9, sl, fp} + 14d08: e2860000 add r0, r6, #0 ; 0x0 + 14d0c: e59d1418 ldr r1, [sp, #1048] + 14d10: ebf5ba2d bl 0xffd835cc + 14d14: 08000e2e stmeqda r0, {r1, r2, r3, r5, r9, sl, fp} + 14d18: ebf5bc98 bl 0xffd83f80 + 14d1c: 08000e2e stmeqda r0, {r1, r2, r3, r5, r9, sl, fp} + 14d20: e2860004 add r0, r6, #4 ; 0x4 + 14d24: e59d141c ldr r1, [sp, #1052] + 14d28: ebf5ba27 bl 0xffd835cc + 14d2c: 08000e30 stmeqda r0, {r4, r5, r9, sl, fp} + 14d30: ebf5bc92 bl 0xffd83f80 + 14d34: 08000e30 stmeqda r0, {r4, r5, r9, sl, fp} + 14d38: e59d1420 ldr r1, [sp, #1056] + 14d3c: e1a03001 mov r3, r1 + 14d40: ebf5bc8e bl 0xffd83f80 + 14d44: 08000e32 stmeqda r0, {r1, r4, r5, r9, sl, fp} + 14d48: e2860008 add r0, r6, #8 ; 0x8 + 14d4c: e1a01003 mov r1, r3 + 14d50: ebf5ba1d bl 0xffd835cc + 14d54: 08000e34 stmeqda r0, {r2, r4, r5, r9, sl, fp} + 14d58: ebf5bc88 bl 0xffd83f80 + 14d5c: 08000e34 stmeqda r0, {r2, r4, r5, r9, sl, fp} + 14d60: e1b03187 movs r3, r7, lsl #3 + 14d64: ebf5bc85 bl 0xffd83f80 + 14d68: 08000e36 stmeqda r0, {r1, r2, r4, r5, r9, sl, fp} + 14d6c: e1b04108 movs r4, r8, lsl #2 + 14d70: ebf5bc82 bl 0xffd83f80 + 14d74: 08000e38 stmeqda r0, {r3, r4, r5, r9, sl, fp} + 14d78: e59d1424 ldr r1, [sp, #1060] + 14d7c: e1a05001 mov r5, r1 + 14d80: ebf5bc7e bl 0xffd83f80 + 14d84: 08000e3a stmeqda r0, {r1, r3, r4, r5, r9, sl, fp} + 14d88: e1a01005 mov r1, r5 + 14d8c: e2955004 adds r5, r5, #4 ; 0x4 + 14d90: ebf5bc7a bl 0xffd83f80 + 14d94: 08000e3c stmeqda r0, {r2, r3, r4, r5, r9, sl, fp} + 14d98: e1a01004 mov r1, r4 + 14d9c: e0944005 adds r4, r4, r5 + 14da0: ebf5bc76 bl 0xffd83f80 + 14da4: 08000e3e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, fp} + 14da8: e1a01003 mov r1, r3 + 14dac: e0933004 adds r3, r3, r4 + 14db0: ebf5bc72 bl 0xffd83f80 + 14db4: 08000e40 stmeqda r0, {r6, r9, sl, fp} + 14db8: e1a01006 mov r1, r6 + 14dbc: e2964000 adds r4, r6, #0 ; 0x0 + 14dc0: ebf5bc6e bl 0xffd83f80 + 14dc4: 08000e42 stmeqda r0, {r1, r6, r9, sl, fp} + 14dc8: ebf5bc6c bl 0xffd83f80 + 14dcc: 08000e44 stmeqda r0, {r2, r6, r9, sl, fp} + 14dd0: e3a00047 mov r0, #71 ; 0x47 + 14dd4: e3800c0e orr r0, r0, #3584 ; 0xe00 + 14dd8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 14ddc: e58d0438 str r0, [sp, #1080] + 14de0: e28cc02a add ip, ip, #42 ; 0x2a + 14de4: e1a00fac mov r0, ip, lsr #31 + 14de8: e08ff100 add pc, pc, r0, lsl #2 + 14dec: 08000de0 stmeqda r0, {r5, r6, r7, r8, sl, fp} + 14df0: ebf5b857 bl 0xffd82f54 + 14df4: ea000001 b 0x14e00 + 14df8: 08000de0 stmeqda r0, {r5, r6, r7, r8, sl, fp} + 14dfc: 00000000 andeq r0, r0, r0 + 14e00: ebf5bc5e bl 0xffd83f80 + 14e04: 08000de0 stmeqda r0, {r5, r6, r7, r8, sl, fp} + 14e08: e2830000 add r0, r3, #0 ; 0x0 + 14e0c: ebf5bac1 bl 0xffd83918 + 14e10: 08000de4 stmeqda r0, {r2, r5, r6, r7, r8, sl, fp} + 14e14: e1a05000 mov r5, r0 + 14e18: ebf5bc58 bl 0xffd83f80 + 14e1c: 08000de2 stmeqda r0, {r1, r5, r6, r7, r8, sl, fp} + 14e20: e3550000 cmp r5, #0 ; 0x0 + 14e24: ebf5bc55 bl 0xffd83f80 + 14e28: 08000de4 stmeqda r0, {r2, r5, r6, r7, r8, sl, fp} + 14e2c: e28cc00b add ip, ip, #11 ; 0xb + 14e30: 1a000004 bne 0x14e48 + 14e34: e1a00fac mov r0, ip, lsr #31 + 14e38: e08ff100 add pc, pc, r0, lsl #2 + 14e3c: 08000df4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, fp} + 14e40: ebf5b843 bl 0xffd82f54 + 14e44: ea000009 b 0x14e70 + 14e48: ebf5bc4c bl 0xffd83f80 + 14e4c: 08000de6 stmeqda r0, {r1, r2, r5, r6, r7, r8, sl, fp} + 14e50: e28cc003 add ip, ip, #3 ; 0x3 + 14e54: e1a00fac mov r0, ip, lsr #31 + 14e58: e08ff100 add pc, pc, r0, lsl #2 + 14e5c: 08000dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp} + 14e60: ebf5b83b bl 0xffd82f54 + 14e64: ea00000e b 0x14ea4 + 14e68: 08000df4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, fp} + 14e6c: 00000000 andeq r0, r0, r0 + 14e70: ebf5bc42 bl 0xffd83f80 + 14e74: 08000df4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, fp} + 14e78: e2830000 add r0, r3, #0 ; 0x0 + 14e7c: e1a01004 mov r1, r4 + 14e80: ebf5b9d1 bl 0xffd835cc + 14e84: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14e88: ebf5bc3c bl 0xffd83f80 + 14e8c: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14e90: e59d0438 ldr r0, [sp, #1080] + 14e94: e28cc007 add ip, ip, #7 ; 0x7 + 14e98: eaf5b88c b 0xffd830d0 + 14e9c: 08000dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp} + 14ea0: 00000000 andeq r0, r0, r0 + 14ea4: ebf5bc35 bl 0xffd83f80 + 14ea8: 08000dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp} + 14eac: e285000c add r0, r5, #12 ; 0xc + 14eb0: ebf5ba98 bl 0xffd83918 + 14eb4: 08000dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp} + 14eb8: e1a03000 mov r3, r0 + 14ebc: ebf5bc2f bl 0xffd83f80 + 14ec0: 08000dec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl, fp} + 14ec4: e3530000 cmp r3, #0 ; 0x0 + 14ec8: ebf5bc2c bl 0xffd83f80 + 14ecc: 08000dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp} + 14ed0: e28cc00b add ip, ip, #11 ; 0xb + 14ed4: 0a000004 beq 0x14eec + 14ed8: e1a00fac mov r0, ip, lsr #31 + 14edc: e08ff100 add pc, pc, r0, lsl #2 + 14ee0: 08000de8 stmeqda r0, {r3, r5, r6, r7, r8, sl, fp} + 14ee4: ebf5b81a bl 0xffd82f54 + 14ee8: ea00000f b 0x14f2c + 14eec: ebf5bc23 bl 0xffd83f80 + 14ef0: 08000df0 stmeqda r0, {r4, r5, r6, r7, r8, sl, fp} + 14ef4: e285000c add r0, r5, #12 ; 0xc + 14ef8: e1a01004 mov r1, r4 + 14efc: ebf5b9b2 bl 0xffd835cc + 14f00: 08000df2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, fp} + 14f04: ebf5bc1d bl 0xffd83f80 + 14f08: 08000df2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, fp} + 14f0c: e28cc007 add ip, ip, #7 ; 0x7 + 14f10: e1a00fac mov r0, ip, lsr #31 + 14f14: e08ff100 add pc, pc, r0, lsl #2 + 14f18: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14f1c: ebf5b80c bl 0xffd82f54 + 14f20: ea000029 b 0x14fcc + 14f24: 08000de8 stmeqda r0, {r3, r5, r6, r7, r8, sl, fp} + 14f28: 00000000 andeq r0, r0, r0 + 14f2c: ebf5bc13 bl 0xffd83f80 + 14f30: 08000de8 stmeqda r0, {r3, r5, r6, r7, r8, sl, fp} + 14f34: e285000c add r0, r5, #12 ; 0xc + 14f38: ebf5ba76 bl 0xffd83918 + 14f3c: 08000dec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl, fp} + 14f40: e1a05000 mov r5, r0 + 14f44: ebf5bc0d bl 0xffd83f80 + 14f48: 08000dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp} + 14f4c: e285000c add r0, r5, #12 ; 0xc + 14f50: ebf5ba70 bl 0xffd83918 + 14f54: 08000dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp} + 14f58: e1a03000 mov r3, r0 + 14f5c: ebf5bc07 bl 0xffd83f80 + 14f60: 08000dec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl, fp} + 14f64: e3530000 cmp r3, #0 ; 0x0 + 14f68: ebf5bc04 bl 0xffd83f80 + 14f6c: 08000dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp} + 14f70: e28cc010 add ip, ip, #16 ; 0x10 + 14f74: 0a000004 beq 0x14f8c + 14f78: e1a00fac mov r0, ip, lsr #31 + 14f7c: e08ff100 add pc, pc, r0, lsl #2 + 14f80: 08000de8 stmeqda r0, {r3, r5, r6, r7, r8, sl, fp} + 14f84: ebf5b7f2 bl 0xffd82f54 + 14f88: eaffffe7 b 0x14f2c + 14f8c: ebf5bbfb bl 0xffd83f80 + 14f90: 08000df0 stmeqda r0, {r4, r5, r6, r7, r8, sl, fp} + 14f94: e285000c add r0, r5, #12 ; 0xc + 14f98: e1a01004 mov r1, r4 + 14f9c: ebf5b98a bl 0xffd835cc + 14fa0: 08000df2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, fp} + 14fa4: ebf5bbf5 bl 0xffd83f80 + 14fa8: 08000df2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, fp} + 14fac: e28cc007 add ip, ip, #7 ; 0x7 + 14fb0: e1a00fac mov r0, ip, lsr #31 + 14fb4: e08ff100 add pc, pc, r0, lsl #2 + 14fb8: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14fbc: ebf5b7e4 bl 0xffd82f54 + 14fc0: ea000001 b 0x14fcc + 14fc4: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14fc8: 00000000 andeq r0, r0, r0 + 14fcc: ebf5bbeb bl 0xffd83f80 + 14fd0: 08000df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp} + 14fd4: e59d0438 ldr r0, [sp, #1080] + 14fd8: e28cc003 add ip, ip, #3 ; 0x3 + 14fdc: eaf5b83b b 0xffd830d0 + 14fe0: 08000e48 stmeqda r0, {r3, r6, r9, sl, fp} + 14fe4: 00000000 andeq r0, r0, r0 + 14fe8: ebf5bbe4 bl 0xffd83f80 + 14fec: 08000e48 stmeqda r0, {r3, r6, r9, sl, fp} + 14ff0: e59d9434 ldr r9, [sp, #1076] + 14ff4: e3c99003 bic r9, r9, #3 ; 0x3 + 14ff8: e2890008 add r0, r9, #8 ; 0x8 + 14ffc: e58d0434 str r0, [sp, #1076] + 15000: e2890000 add r0, r9, #0 ; 0x0 + 15004: ebf5ba43 bl 0xffd83918 + 15008: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 1500c: e1a06000 mov r6, r0 + 15010: e2890004 add r0, r9, #4 ; 0x4 + 15014: ebf5ba3f bl 0xffd83918 + 15018: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 1501c: e1a07000 mov r7, r0 + 15020: ebf5bbd6 bl 0xffd83f80 + 15024: 08000e4a stmeqda r0, {r1, r3, r6, r9, sl, fp} + 15028: e1a00006 mov r0, r6 + 1502c: e58d0420 str r0, [sp, #1056] + 15030: ebf5bbd2 bl 0xffd83f80 + 15034: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 15038: e1a00007 mov r0, r7 + 1503c: e58d0424 str r0, [sp, #1060] + 15040: ebf5bbce bl 0xffd83f80 + 15044: 08000e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp} + 15048: e59d9434 ldr r9, [sp, #1076] + 1504c: e3c99003 bic r9, r9, #3 ; 0x3 + 15050: e2890010 add r0, r9, #16 ; 0x10 + 15054: e58d0434 str r0, [sp, #1076] + 15058: e2890000 add r0, r9, #0 ; 0x0 + 1505c: ebf5ba2d bl 0xffd83918 + 15060: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15064: e1a07000 mov r7, r0 + 15068: e2890004 add r0, r9, #4 ; 0x4 + 1506c: ebf5ba29 bl 0xffd83918 + 15070: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15074: e1a08000 mov r8, r0 + 15078: e2890008 add r0, r9, #8 ; 0x8 + 1507c: ebf5ba25 bl 0xffd83918 + 15080: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15084: e58d0418 str r0, [sp, #1048] + 15088: e289000c add r0, r9, #12 ; 0xc + 1508c: ebf5ba21 bl 0xffd83918 + 15090: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15094: e58d041c str r0, [sp, #1052] + 15098: ebf5bbb8 bl 0xffd83f80 + 1509c: 08000e50 stmeqda r0, {r4, r6, r9, sl, fp} + 150a0: e59d9434 ldr r9, [sp, #1076] + 150a4: e3c99003 bic r9, r9, #3 ; 0x3 + 150a8: e2890004 add r0, r9, #4 ; 0x4 + 150ac: e58d0434 str r0, [sp, #1076] + 150b0: e2890000 add r0, r9, #0 ; 0x0 + 150b4: ebf5ba17 bl 0xffd83918 + 150b8: 08000e54 stmeqda r0, {r2, r4, r6, r9, sl, fp} + 150bc: e1a04000 mov r4, r0 + 150c0: ebf5bbae bl 0xffd83f80 + 150c4: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 150c8: e1a00004 mov r0, r4 + 150cc: e28cc019 add ip, ip, #25 ; 0x19 + 150d0: eaf5b7fe b 0xffd830d0 + 150d4: 08000e46 stmeqda r0, {r1, r2, r6, r9, sl, fp} + 150d8: 00000000 andeq r0, r0, r0 + 150dc: ebf5bba7 bl 0xffd83f80 + 150e0: 08000e46 stmeqda r0, {r1, r2, r6, r9, sl, fp} + 150e4: e3b03000 movs r3, #0 ; 0x0 + 150e8: ebf5bba4 bl 0xffd83f80 + 150ec: 08000e48 stmeqda r0, {r3, r6, r9, sl, fp} + 150f0: e59d9434 ldr r9, [sp, #1076] + 150f4: e3c99003 bic r9, r9, #3 ; 0x3 + 150f8: e2890008 add r0, r9, #8 ; 0x8 + 150fc: e58d0434 str r0, [sp, #1076] + 15100: e2890000 add r0, r9, #0 ; 0x0 + 15104: ebf5ba03 bl 0xffd83918 + 15108: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 1510c: e1a06000 mov r6, r0 + 15110: e2890004 add r0, r9, #4 ; 0x4 + 15114: ebf5b9ff bl 0xffd83918 + 15118: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 1511c: e1a07000 mov r7, r0 + 15120: ebf5bb96 bl 0xffd83f80 + 15124: 08000e4a stmeqda r0, {r1, r3, r6, r9, sl, fp} + 15128: e1a00006 mov r0, r6 + 1512c: e58d0420 str r0, [sp, #1056] + 15130: ebf5bb92 bl 0xffd83f80 + 15134: 08000e4c stmeqda r0, {r2, r3, r6, r9, sl, fp} + 15138: e1a00007 mov r0, r7 + 1513c: e58d0424 str r0, [sp, #1060] + 15140: ebf5bb8e bl 0xffd83f80 + 15144: 08000e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp} + 15148: e59d9434 ldr r9, [sp, #1076] + 1514c: e3c99003 bic r9, r9, #3 ; 0x3 + 15150: e2890010 add r0, r9, #16 ; 0x10 + 15154: e58d0434 str r0, [sp, #1076] + 15158: e2890000 add r0, r9, #0 ; 0x0 + 1515c: ebf5b9ed bl 0xffd83918 + 15160: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15164: e1a07000 mov r7, r0 + 15168: e2890004 add r0, r9, #4 ; 0x4 + 1516c: ebf5b9e9 bl 0xffd83918 + 15170: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15174: e1a08000 mov r8, r0 + 15178: e2890008 add r0, r9, #8 ; 0x8 + 1517c: ebf5b9e5 bl 0xffd83918 + 15180: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15184: e58d0418 str r0, [sp, #1048] + 15188: e289000c add r0, r9, #12 ; 0xc + 1518c: ebf5b9e1 bl 0xffd83918 + 15190: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 15194: e58d041c str r0, [sp, #1052] + 15198: ebf5bb78 bl 0xffd83f80 + 1519c: 08000e50 stmeqda r0, {r4, r6, r9, sl, fp} + 151a0: e59d9434 ldr r9, [sp, #1076] + 151a4: e3c99003 bic r9, r9, #3 ; 0x3 + 151a8: e2890004 add r0, r9, #4 ; 0x4 + 151ac: e58d0434 str r0, [sp, #1076] + 151b0: e2890000 add r0, r9, #0 ; 0x0 + 151b4: ebf5b9d7 bl 0xffd83918 + 151b8: 08000e54 stmeqda r0, {r2, r4, r6, r9, sl, fp} + 151bc: e1a04000 mov r4, r0 + 151c0: ebf5bb6e bl 0xffd83f80 + 151c4: 08000e52 stmeqda r0, {r1, r4, r6, r9, sl, fp} + 151c8: e1a00004 mov r0, r4 + 151cc: e28cc01c add ip, ip, #28 ; 0x1c + 151d0: eaf5b7be b 0xffd830d0 + 151d4: 08000ecc stmeqda r0, {r2, r3, r6, r7, r9, sl, fp} + 151d8: 00000000 andeq r0, r0, r0 + 151dc: ebf5bb67 bl 0xffd83f80 + 151e0: 08000ecc stmeqda r0, {r2, r3, r6, r7, r9, sl, fp} + 151e4: e59d9434 ldr r9, [sp, #1076] + 151e8: e3c99003 bic r9, r9, #3 ; 0x3 + 151ec: e2890004 add r0, r9, #4 ; 0x4 + 151f0: e58d0434 str r0, [sp, #1076] + 151f4: e2890000 add r0, r9, #0 ; 0x0 + 151f8: ebf5b9c6 bl 0xffd83918 + 151fc: 08000ed0 stmeqda r0, {r4, r6, r7, r9, sl, fp} + 15200: e1a06000 mov r6, r0 + 15204: ebf5bb5d bl 0xffd83f80 + 15208: 08000ece stmeqda r0, {r1, r2, r3, r6, r7, r9, sl, fp} + 1520c: e1a00006 mov r0, r6 + 15210: e58d0420 str r0, [sp, #1056] + 15214: ebf5bb59 bl 0xffd83f80 + 15218: 08000ed0 stmeqda r0, {r4, r6, r7, r9, sl, fp} + 1521c: e59d9434 ldr r9, [sp, #1076] + 15220: e3c99003 bic r9, r9, #3 ; 0x3 + 15224: e289000c add r0, r9, #12 ; 0xc + 15228: e58d0434 str r0, [sp, #1076] + 1522c: e2890000 add r0, r9, #0 ; 0x0 + 15230: ebf5b9b8 bl 0xffd83918 + 15234: 08000ed4 stmeqda r0, {r2, r4, r6, r7, r9, sl, fp} + 15238: e1a07000 mov r7, r0 + 1523c: e2890004 add r0, r9, #4 ; 0x4 + 15240: ebf5b9b4 bl 0xffd83918 + 15244: 08000ed4 stmeqda r0, {r2, r4, r6, r7, r9, sl, fp} + 15248: e1a08000 mov r8, r0 + 1524c: e2890008 add r0, r9, #8 ; 0x8 + 15250: ebf5b9b0 bl 0xffd83918 + 15254: 08000ed4 stmeqda r0, {r2, r4, r6, r7, r9, sl, fp} + 15258: e58d0418 str r0, [sp, #1048] + 1525c: ebf5bb47 bl 0xffd83f80 + 15260: 08000ed2 stmeqda r0, {r1, r4, r6, r7, r9, sl, fp} + 15264: e59d9434 ldr r9, [sp, #1076] + 15268: e3c99003 bic r9, r9, #3 ; 0x3 + 1526c: e2890004 add r0, r9, #4 ; 0x4 + 15270: e58d0434 str r0, [sp, #1076] + 15274: e2890000 add r0, r9, #0 ; 0x0 + 15278: ebf5b9a6 bl 0xffd83918 + 1527c: 08000ed6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl, fp} + 15280: e1a04000 mov r4, r0 + 15284: ebf5bb3d bl 0xffd83f80 + 15288: 08000ed4 stmeqda r0, {r2, r4, r6, r7, r9, sl, fp} + 1528c: e1a00004 mov r0, r4 + 15290: e28cc014 add ip, ip, #20 ; 0x14 + 15294: eaf5b78d b 0xffd830d0 + 15298: 08005b7c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, fp, ip, lr} + 1529c: 00000000 andeq r0, r0, r0 + 152a0: ebf5bb36 bl 0xffd83f80 + 152a4: 08005b7c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, fp, ip, lr} + 152a8: e3a00ec1 mov r0, #3088 ; 0xc10 + 152ac: e3800a05 orr r0, r0, #20480 ; 0x5000 + 152b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 152b4: ebf5b997 bl 0xffd83918 + 152b8: 08005b80 stmeqda r0, {r7, r8, r9, fp, ip, lr} + 152bc: e1a04000 mov r4, r0 + 152c0: ebf5bb2e bl 0xffd83f80 + 152c4: 08005b7e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, fp, ip, lr} + 152c8: e3b050a0 movs r5, #160 ; 0xa0 + 152cc: ebf5bb2b bl 0xffd83f80 + 152d0: 08005b80 stmeqda r0, {r7, r8, r9, fp, ip, lr} + 152d4: e1b05985 movs r5, r5, lsl #19 + 152d8: ebf5bb28 bl 0xffd83f80 + 152dc: 08005b82 stmeqda r0, {r1, r7, r8, r9, fp, ip, lr} + 152e0: e3b060e9 movs r6, #233 ; 0xe9 + 152e4: ebf5bb25 bl 0xffd83f80 + 152e8: 08005b84 stmeqda r0, {r2, r7, r8, r9, fp, ip, lr} + 152ec: e1b06086 movs r6, r6, lsl #1 + 152f0: ebf5bb22 bl 0xffd83f80 + 152f4: 08005b86 stmeqda r0, {r1, r2, r7, r8, r9, fp, ip, lr} + 152f8: e59d0434 ldr r0, [sp, #1076] + 152fc: e2800f00 add r0, r0, #0 ; 0x0 + 15300: e1a01007 mov r1, r7 + 15304: ebf5b8b0 bl 0xffd835cc + 15308: 08005b88 stmeqda r0, {r3, r7, r8, r9, fp, ip, lr} + 1530c: ebf5bb1b bl 0xffd83f80 + 15310: 08005b88 stmeqda r0, {r3, r7, r8, r9, fp, ip, lr} + 15314: e3b03001 movs r3, #1 ; 0x1 + 15318: ebf5bb18 bl 0xffd83f80 + 1531c: 08005b8a stmeqda r0, {r1, r3, r7, r8, r9, fp, ip, lr} + 15320: ebf5bb16 bl 0xffd83f80 + 15324: 08005b8c stmeqda r0, {r2, r3, r7, r8, r9, fp, ip, lr} + 15328: e3a0008f mov r0, #143 ; 0x8f + 1532c: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 15330: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15334: e58d0438 str r0, [sp, #1080] + 15338: e28cc01e add ip, ip, #30 ; 0x1e + 1533c: e1a00fac mov r0, ip, lsr #31 + 15340: e08ff100 add pc, pc, r0, lsl #2 + 15344: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 15348: ebf5b701 bl 0xffd82f54 + 1534c: eafffd16 b 0x147ac + 15350: 08005b8e stmeqda r0, {r1, r2, r3, r7, r8, r9, fp, ip, lr} + 15354: 00000000 andeq r0, r0, r0 + 15358: ebf5bb08 bl 0xffd83f80 + 1535c: 08005b8e stmeqda r0, {r1, r2, r3, r7, r8, r9, fp, ip, lr} + 15360: e3a00f05 mov r0, #20 ; 0x14 + 15364: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 15368: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1536c: ebf5b969 bl 0xffd83918 + 15370: 08005b92 stmeqda r0, {r1, r4, r7, r8, r9, fp, ip, lr} + 15374: e1a04000 mov r4, r0 + 15378: ebf5bb00 bl 0xffd83f80 + 1537c: 08005b90 stmeqda r0, {r4, r7, r8, r9, fp, ip, lr} + 15380: e3b050c0 movs r5, #192 ; 0xc0 + 15384: ebf5bafd bl 0xffd83f80 + 15388: 08005b92 stmeqda r0, {r1, r4, r7, r8, r9, fp, ip, lr} + 1538c: e1b05985 movs r5, r5, lsl #19 + 15390: ebf5bafa bl 0xffd83f80 + 15394: 08005b94 stmeqda r0, {r2, r4, r7, r8, r9, fp, ip, lr} + 15398: e3b080a0 movs r8, #160 ; 0xa0 + 1539c: ebf5baf7 bl 0xffd83f80 + 153a0: 08005b96 stmeqda r0, {r1, r2, r4, r7, r8, r9, fp, ip, lr} + 153a4: e1b08188 movs r8, r8, lsl #3 + 153a8: ebf5baf4 bl 0xffd83f80 + 153ac: 08005b98 stmeqda r0, {r3, r4, r7, r8, r9, fp, ip, lr} + 153b0: e59d0434 ldr r0, [sp, #1076] + 153b4: e2800f00 add r0, r0, #0 ; 0x0 + 153b8: e1a01007 mov r1, r7 + 153bc: ebf5b882 bl 0xffd835cc + 153c0: 08005b9a stmeqda r0, {r1, r3, r4, r7, r8, r9, fp, ip, lr} + 153c4: ebf5baed bl 0xffd83f80 + 153c8: 08005b9a stmeqda r0, {r1, r3, r4, r7, r8, r9, fp, ip, lr} + 153cc: e3b03001 movs r3, #1 ; 0x1 + 153d0: ebf5baea bl 0xffd83f80 + 153d4: 08005b9c stmeqda r0, {r2, r3, r4, r7, r8, r9, fp, ip, lr} + 153d8: e1a01008 mov r1, r8 + 153dc: e2986000 adds r6, r8, #0 ; 0x0 + 153e0: ebf5bae6 bl 0xffd83f80 + 153e4: 08005b9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, fp, ip, lr} + 153e8: ebf5bae4 bl 0xffd83f80 + 153ec: 08005ba0 stmeqda r0, {r5, r7, r8, r9, fp, ip, lr} + 153f0: e3a000a3 mov r0, #163 ; 0xa3 + 153f4: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 153f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 153fc: e58d0438 str r0, [sp, #1080] + 15400: e28cc021 add ip, ip, #33 ; 0x21 + 15404: e1a00fac mov r0, ip, lsr #31 + 15408: e08ff100 add pc, pc, r0, lsl #2 + 1540c: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 15410: ebf5b6cf bl 0xffd82f54 + 15414: eafffce4 b 0x147ac + 15418: 08005ba2 stmeqda r0, {r1, r5, r7, r8, r9, fp, ip, lr} + 1541c: 00000000 andeq r0, r0, r0 + 15420: ebf5bad6 bl 0xffd83f80 + 15424: 08005ba2 stmeqda r0, {r1, r5, r7, r8, r9, fp, ip, lr} + 15428: e3a00f06 mov r0, #24 ; 0x18 + 1542c: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 15430: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15434: ebf5b937 bl 0xffd83918 + 15438: 08005ba6 stmeqda r0, {r1, r2, r5, r7, r8, r9, fp, ip, lr} + 1543c: e1a04000 mov r4, r0 + 15440: ebf5bace bl 0xffd83f80 + 15444: 08005ba4 stmeqda r0, {r2, r5, r7, r8, r9, fp, ip, lr} + 15448: e3a00f07 mov r0, #28 ; 0x1c + 1544c: e3800b17 orr r0, r0, #23552 ; 0x5c00 + 15450: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15454: ebf5b92f bl 0xffd83918 + 15458: 08005ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, ip, lr} + 1545c: e1a05000 mov r5, r0 + 15460: ebf5bac6 bl 0xffd83f80 + 15464: 08005ba6 stmeqda r0, {r1, r2, r5, r7, r8, r9, fp, ip, lr} + 15468: e59d0434 ldr r0, [sp, #1076] + 1546c: e2800f00 add r0, r0, #0 ; 0x0 + 15470: e1a01007 mov r1, r7 + 15474: ebf5b854 bl 0xffd835cc + 15478: 08005ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, ip, lr} + 1547c: ebf5babf bl 0xffd83f80 + 15480: 08005ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, ip, lr} + 15484: e3b03001 movs r3, #1 ; 0x1 + 15488: ebf5babc bl 0xffd83f80 + 1548c: 08005baa stmeqda r0, {r1, r3, r5, r7, r8, r9, fp, ip, lr} + 15490: e1a01008 mov r1, r8 + 15494: e2986000 adds r6, r8, #0 ; 0x0 + 15498: ebf5bab8 bl 0xffd83f80 + 1549c: 08005bac stmeqda r0, {r2, r3, r5, r7, r8, r9, fp, ip, lr} + 154a0: ebf5bab6 bl 0xffd83f80 + 154a4: 08005bae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, fp, ip, lr} + 154a8: e3a000b1 mov r0, #177 ; 0xb1 + 154ac: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 154b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 154b4: e58d0438 str r0, [sp, #1080] + 154b8: e28cc01a add ip, ip, #26 ; 0x1a + 154bc: e1a00fac mov r0, ip, lsr #31 + 154c0: e08ff100 add pc, pc, r0, lsl #2 + 154c4: 08000e98 stmeqda r0, {r3, r4, r7, r9, sl, fp} + 154c8: ebf5b6a1 bl 0xffd82f54 + 154cc: eafffcb6 b 0x147ac + 154d0: 08005bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, ip, lr} + 154d4: 00000000 andeq r0, r0, r0 + 154d8: ebf5baa8 bl 0xffd83f80 + 154dc: 08005bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, ip, lr} + 154e0: e3b030bf movs r3, #191 ; 0xbf + 154e4: ebf5baa5 bl 0xffd83f80 + 154e8: 08005bb2 stmeqda r0, {r1, r4, r5, r7, r8, r9, fp, ip, lr} + 154ec: e59d1420 ldr r1, [sp, #1056] + 154f0: e1a04001 mov r4, r1 + 154f4: ebf5baa1 bl 0xffd83f80 + 154f8: 08005bb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, fp, ip, lr} + 154fc: e2840004 add r0, r4, #4 ; 0x4 + 15500: e1a01003 mov r1, r3 + 15504: ebf5b810 bl 0xffd8354c + 15508: 08005bb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, fp, ip, lr} + 1550c: ebf5ba9b bl 0xffd83f80 + 15510: 08005bb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, fp, ip, lr} + 15514: e2840008 add r0, r4, #8 ; 0x8 + 15518: e1a01007 mov r1, r7 + 1551c: ebf5b80a bl 0xffd8354c + 15520: 08005bb8 stmeqda r0, {r3, r4, r5, r7, r8, r9, fp, ip, lr} + 15524: ebf5ba95 bl 0xffd83f80 + 15528: 08005bb8 stmeqda r0, {r3, r4, r5, r7, r8, r9, fp, ip, lr} + 1552c: ebf5ba93 bl 0xffd83f80 + 15530: 08005bba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, fp, ip, lr} + 15534: e3a000bd mov r0, #189 ; 0xbd + 15538: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 1553c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15540: e58d0438 str r0, [sp, #1080] + 15544: e28cc014 add ip, ip, #20 ; 0x14 + 15548: e1a00fac mov r0, ip, lsr #31 + 1554c: e08ff100 add pc, pc, r0, lsl #2 + 15550: 080c0574 stmeqda ip, {r2, r4, r5, r6, r8, sl} + 15554: ebf5b67e bl 0xffd82f54 + 15558: ea000001 b 0x15564 + 1555c: 080c0574 stmeqda ip, {r2, r4, r5, r6, r8, sl} + 15560: 00000000 andeq r0, r0, r0 + 15564: ebf5ba85 bl 0xffd83f80 + 15568: 080c0574 stmeqda ip, {r2, r4, r5, r6, r8, sl} + 1556c: e59d9434 ldr r9, [sp, #1076] + 15570: e3c99003 bic r9, r9, #3 ; 0x3 + 15574: e249900c sub r9, r9, #12 ; 0xc + 15578: e58d9434 str r9, [sp, #1076] + 1557c: e2890000 add r0, r9, #0 ; 0x0 + 15580: e1a01007 mov r1, r7 + 15584: ebf5b830 bl 0xffd8364c + 15588: e2890004 add r0, r9, #4 ; 0x4 + 1558c: e1a01008 mov r1, r8 + 15590: ebf5b82d bl 0xffd8364c + 15594: e2890008 add r0, r9, #8 ; 0x8 + 15598: e59d1438 ldr r1, [sp, #1080] + 1559c: ebf5b82a bl 0xffd8364c + 155a0: ebf5ba76 bl 0xffd83f80 + 155a4: 080c0576 stmeqda ip, {r1, r2, r4, r5, r6, r8, sl} + 155a8: e3a00f66 mov r0, #408 ; 0x198 + 155ac: e3800b01 orr r0, r0, #1024 ; 0x400 + 155b0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 155b4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 155b8: ebf5b8d6 bl 0xffd83918 + 155bc: 080c057a stmeqda ip, {r1, r3, r4, r5, r6, r8, sl} + 155c0: e1a03000 mov r3, r0 + 155c4: ebf5ba6d bl 0xffd83f80 + 155c8: 080c0578 stmeqda ip, {r3, r4, r5, r6, r8, sl} + 155cc: e1b03803 movs r3, r3, lsl #16 + 155d0: ebf5ba6a bl 0xffd83f80 + 155d4: 080c057a stmeqda ip, {r1, r3, r4, r5, r6, r8, sl} + 155d8: e1b03823 movs r3, r3, lsr #16 + 155dc: ebf5ba67 bl 0xffd83f80 + 155e0: 080c057c stmeqda ip, {r2, r3, r4, r5, r6, r8, sl} + 155e4: e3530000 cmp r3, #0 ; 0x0 + 155e8: ebf5ba64 bl 0xffd83f80 + 155ec: 080c057e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, sl} + 155f0: e28cc016 add ip, ip, #22 ; 0x16 + 155f4: 1a000004 bne 0x1560c + 155f8: e1a00fac mov r0, ip, lsr #31 + 155fc: e08ff100 add pc, pc, r0, lsl #2 + 15600: 080c0592 stmeqda ip, {r1, r4, r7, r8, sl} + 15604: ebf5b652 bl 0xffd82f54 + 15608: ea000023 b 0x1569c + 1560c: ebf5ba5b bl 0xffd83f80 + 15610: 080c0580 stmeqda ip, {r7, r8, sl} + 15614: e3a00f67 mov r0, #412 ; 0x19c + 15618: e3800b01 orr r0, r0, #1024 ; 0x400 + 1561c: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15620: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15624: ebf5b8bb bl 0xffd83918 + 15628: 080c0584 stmeqda ip, {r2, r7, r8, sl} + 1562c: e1a08000 mov r8, r0 + 15630: ebf5ba52 bl 0xffd83f80 + 15634: 080c0582 stmeqda ip, {r1, r7, r8, sl} + 15638: e1a01003 mov r1, r3 + 1563c: e2937000 adds r7, r3, #0 ; 0x0 + 15640: ebf5ba4e bl 0xffd83f80 + 15644: 080c0584 stmeqda ip, {r2, r7, r8, sl} + 15648: e2880000 add r0, r8, #0 ; 0x0 + 1564c: ebf5b8b1 bl 0xffd83918 + 15650: 080c0588 stmeqda ip, {r3, r7, r8, sl} + 15654: e1a03000 mov r3, r0 + 15658: ebf5ba48 bl 0xffd83f80 + 1565c: 080c0586 stmeqda ip, {r1, r2, r7, r8, sl} + 15660: ebf5ba46 bl 0xffd83f80 + 15664: 080c0588 stmeqda ip, {r3, r7, r8, sl} + 15668: e3a0008b mov r0, #139 ; 0x8b + 1566c: e3800c05 orr r0, r0, #1280 ; 0x500 + 15670: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15674: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15678: e58d0438 str r0, [sp, #1080] + 1567c: e28cc013 add ip, ip, #19 ; 0x13 + 15680: e1a00fac mov r0, ip, lsr #31 + 15684: e08ff100 add pc, pc, r0, lsl #2 + 15688: 080c0b70 stmeqda ip, {r4, r5, r6, r8, r9, fp} + 1568c: ebf5b630 bl 0xffd82f54 + 15690: ea000020 b 0x15718 + 15694: 080c0592 stmeqda ip, {r1, r4, r7, r8, sl} + 15698: 00000000 andeq r0, r0, r0 + 1569c: ebf5ba37 bl 0xffd83f80 + 156a0: 080c0592 stmeqda ip, {r1, r4, r7, r8, sl} + 156a4: e59d9434 ldr r9, [sp, #1076] + 156a8: e3c99003 bic r9, r9, #3 ; 0x3 + 156ac: e2890008 add r0, r9, #8 ; 0x8 + 156b0: e58d0434 str r0, [sp, #1076] + 156b4: e2890000 add r0, r9, #0 ; 0x0 + 156b8: ebf5b896 bl 0xffd83918 + 156bc: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 156c0: e1a07000 mov r7, r0 + 156c4: e2890004 add r0, r9, #4 ; 0x4 + 156c8: ebf5b892 bl 0xffd83918 + 156cc: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 156d0: e1a08000 mov r8, r0 + 156d4: ebf5ba29 bl 0xffd83f80 + 156d8: 080c0594 stmeqda ip, {r2, r4, r7, r8, sl} + 156dc: e59d9434 ldr r9, [sp, #1076] + 156e0: e3c99003 bic r9, r9, #3 ; 0x3 + 156e4: e2890004 add r0, r9, #4 ; 0x4 + 156e8: e58d0434 str r0, [sp, #1076] + 156ec: e2890000 add r0, r9, #0 ; 0x0 + 156f0: ebf5b888 bl 0xffd83918 + 156f4: 080c0598 stmeqda ip, {r3, r4, r7, r8, sl} + 156f8: e1a03000 mov r3, r0 + 156fc: ebf5ba1f bl 0xffd83f80 + 15700: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 15704: e1a00003 mov r0, r3 + 15708: e28cc00c add ip, ip, #12 ; 0xc + 1570c: eaf5b66f b 0xffd830d0 + 15710: 080c0b70 stmeqda ip, {r4, r5, r6, r8, r9, fp} + 15714: 00000000 andeq r0, r0, r0 + 15718: ebf5ba18 bl 0xffd83f80 + 1571c: 080c0b70 stmeqda ip, {r4, r5, r6, r8, r9, fp} + 15720: e59d9434 ldr r9, [sp, #1076] + 15724: e3c99003 bic r9, r9, #3 ; 0x3 + 15728: e2499010 sub r9, r9, #16 ; 0x10 + 1572c: e58d9434 str r9, [sp, #1076] + 15730: e2890000 add r0, r9, #0 ; 0x0 + 15734: e1a01007 mov r1, r7 + 15738: ebf5b7c3 bl 0xffd8364c + 1573c: e2890004 add r0, r9, #4 ; 0x4 + 15740: e1a01008 mov r1, r8 + 15744: ebf5b7c0 bl 0xffd8364c + 15748: e2890008 add r0, r9, #8 ; 0x8 + 1574c: e59d1418 ldr r1, [sp, #1048] + 15750: ebf5b7bd bl 0xffd8364c + 15754: e289000c add r0, r9, #12 ; 0xc + 15758: e59d1438 ldr r1, [sp, #1080] + 1575c: ebf5b7ba bl 0xffd8364c + 15760: ebf5ba06 bl 0xffd83f80 + 15764: 080c0b72 stmeqda ip, {r1, r4, r5, r6, r8, r9, fp} + 15768: e1a01003 mov r1, r3 + 1576c: e2930000 adds r0, r3, #0 ; 0x0 + 15770: e58d0418 str r0, [sp, #1048] + 15774: ebf5ba01 bl 0xffd83f80 + 15778: 080c0b74 stmeqda ip, {r2, r4, r5, r6, r8, r9, fp} + 1577c: e59d0418 ldr r0, [sp, #1048] + 15780: e2800034 add r0, r0, #52 ; 0x34 + 15784: ebf5b863 bl 0xffd83918 + 15788: 080c0b78 stmeqda ip, {r3, r4, r5, r6, r8, r9, fp} + 1578c: e1a04000 mov r4, r0 + 15790: ebf5b9fa bl 0xffd83f80 + 15794: 080c0b76 stmeqda ip, {r1, r2, r4, r5, r6, r8, r9, fp} + 15798: e3a00feb mov r0, #940 ; 0x3ac + 1579c: e3800b02 orr r0, r0, #2048 ; 0x800 + 157a0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 157a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 157a8: ebf5b85a bl 0xffd83918 + 157ac: 080c0b7a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, fp} + 157b0: e1a03000 mov r3, r0 + 157b4: ebf5b9f1 bl 0xffd83f80 + 157b8: 080c0b78 stmeqda ip, {r3, r4, r5, r6, r8, r9, fp} + 157bc: e1540003 cmp r4, r3 + 157c0: ebf5b9ee bl 0xffd83f80 + 157c4: 080c0b7a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, fp} + 157c8: e28cc019 add ip, ip, #25 ; 0x19 + 157cc: 0a000004 beq 0x157e4 + 157d0: e1a00fac mov r0, ip, lsr #31 + 157d4: e08ff100 add pc, pc, r0, lsl #2 + 157d8: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 157dc: ebf5b5dc bl 0xffd82f54 + 157e0: ea000056 b 0x15940 + 157e4: ebf5b9e5 bl 0xffd83f80 + 157e8: 080c0b7c stmeqda ip, {r2, r3, r4, r5, r6, r8, r9, fp} + 157ec: e1a01004 mov r1, r4 + 157f0: e2943001 adds r3, r4, #1 ; 0x1 + 157f4: ebf5b9e1 bl 0xffd83f80 + 157f8: 080c0b7e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, r9, fp} + 157fc: e59d0418 ldr r0, [sp, #1048] + 15800: e2800034 add r0, r0, #52 ; 0x34 + 15804: e1a01003 mov r1, r3 + 15808: ebf5b76f bl 0xffd835cc + 1580c: 080c0b80 stmeqda ip, {r7, r8, r9, fp} + 15810: ebf5b9da bl 0xffd83f80 + 15814: 080c0b80 stmeqda ip, {r7, r8, r9, fp} + 15818: e59d0418 ldr r0, [sp, #1048] + 1581c: e2800004 add r0, r0, #4 ; 0x4 + 15820: ebf5b83c bl 0xffd83918 + 15824: 080c0b84 stmeqda ip, {r2, r7, r8, r9, fp} + 15828: e1a03000 mov r3, r0 + 1582c: ebf5b9d3 bl 0xffd83f80 + 15830: 080c0b82 stmeqda ip, {r1, r7, r8, r9, fp} + 15834: e3b04080 movs r4, #128 ; 0x80 + 15838: ebf5b9d0 bl 0xffd83f80 + 1583c: 080c0b84 stmeqda ip, {r2, r7, r8, r9, fp} + 15840: e1b04c04 movs r4, r4, lsl #24 + 15844: ebf5b9cd bl 0xffd83f80 + 15848: 080c0b86 stmeqda ip, {r1, r2, r7, r8, r9, fp} + 1584c: e1a01003 mov r1, r3 + 15850: e1933004 orrs r3, r3, r4 + 15854: ebf5b9c9 bl 0xffd83f80 + 15858: 080c0b88 stmeqda ip, {r3, r7, r8, r9, fp} + 1585c: e59d0418 ldr r0, [sp, #1048] + 15860: e2800004 add r0, r0, #4 ; 0x4 + 15864: e1a01003 mov r1, r3 + 15868: ebf5b757 bl 0xffd835cc + 1586c: 080c0b8a stmeqda ip, {r1, r3, r7, r8, r9, fp} + 15870: ebf5b9c2 bl 0xffd83f80 + 15874: 080c0b8a stmeqda ip, {r1, r3, r7, r8, r9, fp} + 15878: e59d0418 ldr r0, [sp, #1048] + 1587c: e2800008 add r0, r0, #8 ; 0x8 + 15880: ebf5b7cd bl 0xffd837bc + 15884: 080c0b8e stmeqda ip, {r1, r2, r3, r7, r8, r9, fp} + 15888: e1a07000 mov r7, r0 + 1588c: ebf5b9bb bl 0xffd83f80 + 15890: 080c0b8c stmeqda ip, {r2, r3, r7, r8, r9, fp} + 15894: e59d0418 ldr r0, [sp, #1048] + 15898: e280002c add r0, r0, #44 ; 0x2c + 1589c: ebf5b81d bl 0xffd83918 + 158a0: 080c0b90 stmeqda ip, {r4, r7, r8, r9, fp} + 158a4: e1a08000 mov r8, r0 + 158a8: ebf5b9b4 bl 0xffd83f80 + 158ac: 080c0b8e stmeqda ip, {r1, r2, r3, r7, r8, r9, fp} + 158b0: e3570000 cmp r7, #0 ; 0x0 + 158b4: ebf5b9b1 bl 0xffd83f80 + 158b8: 080c0b90 stmeqda ip, {r4, r7, r8, r9, fp} + 158bc: e28cc029 add ip, ip, #41 ; 0x29 + 158c0: ca000004 bgt 0x158d8 + 158c4: e1a00fac mov r0, ip, lsr #31 + 158c8: e08ff100 add pc, pc, r0, lsl #2 + 158cc: 080c0ba2 stmeqda ip, {r1, r5, r7, r8, r9, fp} + 158d0: ebf5b59f bl 0xffd82f54 + 158d4: ea00003c b 0x159cc + 158d8: ebf5b9a8 bl 0xffd83f80 + 158dc: 080c0b92 stmeqda ip, {r1, r4, r7, r8, r9, fp} + 158e0: e59d1418 ldr r1, [sp, #1048] + 158e4: e59d1418 ldr r1, [sp, #1048] + 158e8: e2913000 adds r3, r1, #0 ; 0x0 + 158ec: ebf5b9a3 bl 0xffd83f80 + 158f0: 080c0b94 stmeqda ip, {r2, r4, r7, r8, r9, fp} + 158f4: e1a01008 mov r1, r8 + 158f8: e2984000 adds r4, r8, #0 ; 0x0 + 158fc: ebf5b99f bl 0xffd83f80 + 15900: 080c0b96 stmeqda ip, {r1, r2, r4, r7, r8, r9, fp} + 15904: ebf5b99d bl 0xffd83f80 + 15908: 080c0b98 stmeqda ip, {r3, r4, r7, r8, r9, fp} + 1590c: e3a0009b mov r0, #155 ; 0x9b + 15910: e3800c0b orr r0, r0, #2816 ; 0xb00 + 15914: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15918: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1591c: e58d0438 str r0, [sp, #1080] + 15920: e28cc00c add ip, ip, #12 ; 0xc + 15924: e1a00fac mov r0, ip, lsr #31 + 15928: e08ff100 add pc, pc, r0, lsl #2 + 1592c: 080c0020 stmeqda ip, {r5} + 15930: ebf5b587 bl 0xffd82f54 + 15934: eaffd6e4 b 0xb4cc + 15938: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 1593c: 00000000 andeq r0, r0, r0 + 15940: ebf5b98e bl 0xffd83f80 + 15944: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15948: e59d9434 ldr r9, [sp, #1076] + 1594c: e3c99003 bic r9, r9, #3 ; 0x3 + 15950: e289000c add r0, r9, #12 ; 0xc + 15954: e58d0434 str r0, [sp, #1076] + 15958: e2890000 add r0, r9, #0 ; 0x0 + 1595c: ebf5b7ed bl 0xffd83918 + 15960: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15964: e1a07000 mov r7, r0 + 15968: e2890004 add r0, r9, #4 ; 0x4 + 1596c: ebf5b7e9 bl 0xffd83918 + 15970: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15974: e1a08000 mov r8, r0 + 15978: e2890008 add r0, r9, #8 ; 0x8 + 1597c: ebf5b7e5 bl 0xffd83918 + 15980: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15984: e58d0418 str r0, [sp, #1048] + 15988: ebf5b97c bl 0xffd83f80 + 1598c: 080c0ba8 stmeqda ip, {r3, r5, r7, r8, r9, fp} + 15990: e59d9434 ldr r9, [sp, #1076] + 15994: e3c99003 bic r9, r9, #3 ; 0x3 + 15998: e2890004 add r0, r9, #4 ; 0x4 + 1599c: e58d0434 str r0, [sp, #1076] + 159a0: e2890000 add r0, r9, #0 ; 0x0 + 159a4: ebf5b7db bl 0xffd83918 + 159a8: 080c0bac stmeqda ip, {r2, r3, r5, r7, r8, r9, fp} + 159ac: e1a03000 mov r3, r0 + 159b0: ebf5b972 bl 0xffd83f80 + 159b4: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 159b8: e1a00003 mov r0, r3 + 159bc: e28cc00d add ip, ip, #13 ; 0xd + 159c0: eaf5b5c2 b 0xffd830d0 + 159c4: 080c0ba2 stmeqda ip, {r1, r5, r7, r8, r9, fp} + 159c8: 00000000 andeq r0, r0, r0 + 159cc: ebf5b96b bl 0xffd83f80 + 159d0: 080c0ba2 stmeqda ip, {r1, r5, r7, r8, r9, fp} + 159d4: e3a00feb mov r0, #940 ; 0x3ac + 159d8: e3800b02 orr r0, r0, #2048 ; 0x800 + 159dc: e3800703 orr r0, r0, #786432 ; 0xc0000 + 159e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 159e4: ebf5b7cb bl 0xffd83918 + 159e8: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 159ec: e1a03000 mov r3, r0 + 159f0: ebf5b962 bl 0xffd83f80 + 159f4: 080c0ba4 stmeqda ip, {r2, r5, r7, r8, r9, fp} + 159f8: e59d0418 ldr r0, [sp, #1048] + 159fc: e2800034 add r0, r0, #52 ; 0x34 + 15a00: e1a01003 mov r1, r3 + 15a04: ebf5b6f0 bl 0xffd835cc + 15a08: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15a0c: ebf5b95b bl 0xffd83f80 + 15a10: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15a14: e59d9434 ldr r9, [sp, #1076] + 15a18: e3c99003 bic r9, r9, #3 ; 0x3 + 15a1c: e289000c add r0, r9, #12 ; 0xc + 15a20: e58d0434 str r0, [sp, #1076] + 15a24: e2890000 add r0, r9, #0 ; 0x0 + 15a28: ebf5b7ba bl 0xffd83918 + 15a2c: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15a30: e1a07000 mov r7, r0 + 15a34: e2890004 add r0, r9, #4 ; 0x4 + 15a38: ebf5b7b6 bl 0xffd83918 + 15a3c: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15a40: e1a08000 mov r8, r0 + 15a44: e2890008 add r0, r9, #8 ; 0x8 + 15a48: ebf5b7b2 bl 0xffd83918 + 15a4c: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15a50: e58d0418 str r0, [sp, #1048] + 15a54: ebf5b949 bl 0xffd83f80 + 15a58: 080c0ba8 stmeqda ip, {r3, r5, r7, r8, r9, fp} + 15a5c: e59d9434 ldr r9, [sp, #1076] + 15a60: e3c99003 bic r9, r9, #3 ; 0x3 + 15a64: e2890004 add r0, r9, #4 ; 0x4 + 15a68: e58d0434 str r0, [sp, #1076] + 15a6c: e2890000 add r0, r9, #0 ; 0x0 + 15a70: ebf5b7a8 bl 0xffd83918 + 15a74: 080c0bac stmeqda ip, {r2, r3, r5, r7, r8, r9, fp} + 15a78: e1a03000 mov r3, r0 + 15a7c: ebf5b93f bl 0xffd83f80 + 15a80: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15a84: e1a00003 mov r0, r3 + 15a88: e28cc016 add ip, ip, #22 ; 0x16 + 15a8c: eaf5b58f b 0xffd830d0 + 15a90: 080c0b9a stmeqda ip, {r1, r3, r4, r7, r8, r9, fp} + 15a94: 00000000 andeq r0, r0, r0 + 15a98: ebf5b938 bl 0xffd83f80 + 15a9c: 080c0b9a stmeqda ip, {r1, r3, r4, r7, r8, r9, fp} + 15aa0: e1a01007 mov r1, r7 + 15aa4: e2577001 subs r7, r7, #1 ; 0x1 + 15aa8: ebf5b934 bl 0xffd83f80 + 15aac: 080c0b9c stmeqda ip, {r2, r3, r4, r7, r8, r9, fp} + 15ab0: e1a01008 mov r1, r8 + 15ab4: e2988050 adds r8, r8, #80 ; 0x50 + 15ab8: ebf5b930 bl 0xffd83f80 + 15abc: 080c0b9e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, fp} + 15ac0: e3570000 cmp r7, #0 ; 0x0 + 15ac4: ebf5b92d bl 0xffd83f80 + 15ac8: 080c0ba0 stmeqda ip, {r5, r7, r8, r9, fp} + 15acc: e28cc00c add ip, ip, #12 ; 0xc + 15ad0: da000004 ble 0x15ae8 + 15ad4: e1a00fac mov r0, ip, lsr #31 + 15ad8: e08ff100 add pc, pc, r0, lsl #2 + 15adc: 080c0b92 stmeqda ip, {r1, r4, r7, r8, r9, fp} + 15ae0: ebf5b51b bl 0xffd82f54 + 15ae4: ea000032 b 0x15bb4 + 15ae8: ebf5b924 bl 0xffd83f80 + 15aec: 080c0ba2 stmeqda ip, {r1, r5, r7, r8, r9, fp} + 15af0: e3a00feb mov r0, #940 ; 0x3ac + 15af4: e3800b02 orr r0, r0, #2048 ; 0x800 + 15af8: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15afc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15b00: ebf5b784 bl 0xffd83918 + 15b04: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15b08: e1a03000 mov r3, r0 + 15b0c: ebf5b91b bl 0xffd83f80 + 15b10: 080c0ba4 stmeqda ip, {r2, r5, r7, r8, r9, fp} + 15b14: e59d0418 ldr r0, [sp, #1048] + 15b18: e2800034 add r0, r0, #52 ; 0x34 + 15b1c: e1a01003 mov r1, r3 + 15b20: ebf5b6a9 bl 0xffd835cc + 15b24: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15b28: ebf5b914 bl 0xffd83f80 + 15b2c: 080c0ba6 stmeqda ip, {r1, r2, r5, r7, r8, r9, fp} + 15b30: e59d9434 ldr r9, [sp, #1076] + 15b34: e3c99003 bic r9, r9, #3 ; 0x3 + 15b38: e289000c add r0, r9, #12 ; 0xc + 15b3c: e58d0434 str r0, [sp, #1076] + 15b40: e2890000 add r0, r9, #0 ; 0x0 + 15b44: ebf5b773 bl 0xffd83918 + 15b48: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15b4c: e1a07000 mov r7, r0 + 15b50: e2890004 add r0, r9, #4 ; 0x4 + 15b54: ebf5b76f bl 0xffd83918 + 15b58: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15b5c: e1a08000 mov r8, r0 + 15b60: e2890008 add r0, r9, #8 ; 0x8 + 15b64: ebf5b76b bl 0xffd83918 + 15b68: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15b6c: e58d0418 str r0, [sp, #1048] + 15b70: ebf5b902 bl 0xffd83f80 + 15b74: 080c0ba8 stmeqda ip, {r3, r5, r7, r8, r9, fp} + 15b78: e59d9434 ldr r9, [sp, #1076] + 15b7c: e3c99003 bic r9, r9, #3 ; 0x3 + 15b80: e2890004 add r0, r9, #4 ; 0x4 + 15b84: e58d0434 str r0, [sp, #1076] + 15b88: e2890000 add r0, r9, #0 ; 0x0 + 15b8c: ebf5b761 bl 0xffd83918 + 15b90: 080c0bac stmeqda ip, {r2, r3, r5, r7, r8, r9, fp} + 15b94: e1a03000 mov r3, r0 + 15b98: ebf5b8f8 bl 0xffd83f80 + 15b9c: 080c0baa stmeqda ip, {r1, r3, r5, r7, r8, r9, fp} + 15ba0: e1a00003 mov r0, r3 + 15ba4: e28cc016 add ip, ip, #22 ; 0x16 + 15ba8: eaf5b548 b 0xffd830d0 + 15bac: 080c0b92 stmeqda ip, {r1, r4, r7, r8, r9, fp} + 15bb0: 00000000 andeq r0, r0, r0 + 15bb4: ebf5b8f1 bl 0xffd83f80 + 15bb8: 080c0b92 stmeqda ip, {r1, r4, r7, r8, r9, fp} + 15bbc: e59d1418 ldr r1, [sp, #1048] + 15bc0: e59d1418 ldr r1, [sp, #1048] + 15bc4: e2913000 adds r3, r1, #0 ; 0x0 + 15bc8: ebf5b8ec bl 0xffd83f80 + 15bcc: 080c0b94 stmeqda ip, {r2, r4, r7, r8, r9, fp} + 15bd0: e1a01008 mov r1, r8 + 15bd4: e2984000 adds r4, r8, #0 ; 0x0 + 15bd8: ebf5b8e8 bl 0xffd83f80 + 15bdc: 080c0b96 stmeqda ip, {r1, r2, r4, r7, r8, r9, fp} + 15be0: ebf5b8e6 bl 0xffd83f80 + 15be4: 080c0b98 stmeqda ip, {r3, r4, r7, r8, r9, fp} + 15be8: e3a0009b mov r0, #155 ; 0x9b + 15bec: e3800c0b orr r0, r0, #2816 ; 0xb00 + 15bf0: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15bf4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15bf8: e58d0438 str r0, [sp, #1080] + 15bfc: e28cc00c add ip, ip, #12 ; 0xc + 15c00: e1a00fac mov r0, ip, lsr #31 + 15c04: e08ff100 add pc, pc, r0, lsl #2 + 15c08: 080c0020 stmeqda ip, {r5} + 15c0c: ebf5b4d0 bl 0xffd82f54 + 15c10: eaffd62d b 0xb4cc + 15c14: 080c058a stmeqda ip, {r1, r3, r7, r8, sl} + 15c18: 00000000 andeq r0, r0, r0 + 15c1c: ebf5b8d7 bl 0xffd83f80 + 15c20: 080c058a stmeqda ip, {r1, r3, r7, r8, sl} + 15c24: e1a01008 mov r1, r8 + 15c28: e298800c adds r8, r8, #12 ; 0xc + 15c2c: ebf5b8d3 bl 0xffd83f80 + 15c30: 080c058c stmeqda ip, {r2, r3, r7, r8, sl} + 15c34: e1a01007 mov r1, r7 + 15c38: e2577001 subs r7, r7, #1 ; 0x1 + 15c3c: ebf5b8cf bl 0xffd83f80 + 15c40: 080c058e stmeqda ip, {r1, r2, r3, r7, r8, sl} + 15c44: e3570000 cmp r7, #0 ; 0x0 + 15c48: ebf5b8cc bl 0xffd83f80 + 15c4c: 080c0590 stmeqda ip, {r4, r7, r8, sl} + 15c50: e28cc00c add ip, ip, #12 ; 0xc + 15c54: 0a000004 beq 0x15c6c + 15c58: e1a00fac mov r0, ip, lsr #31 + 15c5c: e08ff100 add pc, pc, r0, lsl #2 + 15c60: 080c0584 stmeqda ip, {r2, r7, r8, sl} + 15c64: ebf5b4ba bl 0xffd82f54 + 15c68: ea00001e b 0x15ce8 + 15c6c: ebf5b8c3 bl 0xffd83f80 + 15c70: 080c0592 stmeqda ip, {r1, r4, r7, r8, sl} + 15c74: e59d9434 ldr r9, [sp, #1076] + 15c78: e3c99003 bic r9, r9, #3 ; 0x3 + 15c7c: e2890008 add r0, r9, #8 ; 0x8 + 15c80: e58d0434 str r0, [sp, #1076] + 15c84: e2890000 add r0, r9, #0 ; 0x0 + 15c88: ebf5b722 bl 0xffd83918 + 15c8c: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 15c90: e1a07000 mov r7, r0 + 15c94: e2890004 add r0, r9, #4 ; 0x4 + 15c98: ebf5b71e bl 0xffd83918 + 15c9c: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 15ca0: e1a08000 mov r8, r0 + 15ca4: ebf5b8b5 bl 0xffd83f80 + 15ca8: 080c0594 stmeqda ip, {r2, r4, r7, r8, sl} + 15cac: e59d9434 ldr r9, [sp, #1076] + 15cb0: e3c99003 bic r9, r9, #3 ; 0x3 + 15cb4: e2890004 add r0, r9, #4 ; 0x4 + 15cb8: e58d0434 str r0, [sp, #1076] + 15cbc: e2890000 add r0, r9, #0 ; 0x0 + 15cc0: ebf5b714 bl 0xffd83918 + 15cc4: 080c0598 stmeqda ip, {r3, r4, r7, r8, sl} + 15cc8: e1a03000 mov r3, r0 + 15ccc: ebf5b8ab bl 0xffd83f80 + 15cd0: 080c0596 stmeqda ip, {r1, r2, r4, r7, r8, sl} + 15cd4: e1a00003 mov r0, r3 + 15cd8: e28cc00c add ip, ip, #12 ; 0xc + 15cdc: eaf5b4fb b 0xffd830d0 + 15ce0: 080c0584 stmeqda ip, {r2, r7, r8, sl} + 15ce4: 00000000 andeq r0, r0, r0 + 15ce8: ebf5b8a4 bl 0xffd83f80 + 15cec: 080c0584 stmeqda ip, {r2, r7, r8, sl} + 15cf0: e2880000 add r0, r8, #0 ; 0x0 + 15cf4: ebf5b707 bl 0xffd83918 + 15cf8: 080c0588 stmeqda ip, {r3, r7, r8, sl} + 15cfc: e1a03000 mov r3, r0 + 15d00: ebf5b89e bl 0xffd83f80 + 15d04: 080c0586 stmeqda ip, {r1, r2, r7, r8, sl} + 15d08: ebf5b89c bl 0xffd83f80 + 15d0c: 080c0588 stmeqda ip, {r3, r7, r8, sl} + 15d10: e3a0008b mov r0, #139 ; 0x8b + 15d14: e3800c05 orr r0, r0, #1280 ; 0x500 + 15d18: e3800703 orr r0, r0, #786432 ; 0xc0000 + 15d1c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15d20: e58d0438 str r0, [sp, #1080] + 15d24: e28cc00b add ip, ip, #11 ; 0xb + 15d28: e1a00fac mov r0, ip, lsr #31 + 15d2c: e08ff100 add pc, pc, r0, lsl #2 + 15d30: 080c0b70 stmeqda ip, {r4, r5, r6, r8, r9, fp} + 15d34: ebf5b486 bl 0xffd82f54 + 15d38: eafffe76 b 0x15718 + 15d3c: 08005bbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, fp, ip, lr} + 15d40: 00000000 andeq r0, r0, r0 + 15d44: ebf5b88d bl 0xffd83f80 + 15d48: 08005bbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, fp, ip, lr} + 15d4c: e3b05022 movs r5, #34 ; 0x22 + 15d50: ebf5b88a bl 0xffd83f80 + 15d54: 08005bbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, lr} + 15d58: e59d0418 ldr r0, [sp, #1048] + 15d5c: e0800005 add r0, r0, r5 + 15d60: ebf5b6d5 bl 0xffd838bc + 15d64: 08005bc2 stmeqda r0, {r1, r6, r7, r8, r9, fp, ip, lr} + 15d68: e1a03000 mov r3, r0 + 15d6c: ebf5b883 bl 0xffd83f80 + 15d70: 08005bc0 stmeqda r0, {r6, r7, r8, r9, fp, ip, lr} + 15d74: e1b03083 movs r3, r3, lsl #1 + 15d78: ebf5b880 bl 0xffd83f80 + 15d7c: 08005bc2 stmeqda r0, {r1, r6, r7, r8, r9, fp, ip, lr} + 15d80: e1a01003 mov r1, r3 + 15d84: e59d0418 ldr r0, [sp, #1048] + 15d88: e0933000 adds r3, r3, r0 + 15d8c: ebf5b87b bl 0xffd83f80 + 15d90: 08005bc4 stmeqda r0, {r2, r6, r7, r8, r9, fp, ip, lr} + 15d94: e59d1424 ldr r1, [sp, #1060] + 15d98: e1a08001 mov r8, r1 + 15d9c: ebf5b877 bl 0xffd83f80 + 15da0: 08005bc6 stmeqda r0, {r1, r2, r6, r7, r8, r9, fp, ip, lr} + 15da4: e2830019 add r0, r3, #25 ; 0x19 + 15da8: e1a01008 mov r1, r8 + 15dac: ebf5b5c7 bl 0xffd834d0 + 15db0: 08005bc8 stmeqda r0, {r3, r6, r7, r8, r9, fp, ip, lr} + 15db4: ebf5b871 bl 0xffd83f80 + 15db8: 08005bc8 stmeqda r0, {r3, r6, r7, r8, r9, fp, ip, lr} + 15dbc: e3a00ec2 mov r0, #3104 ; 0xc20 + 15dc0: e3800a05 orr r0, r0, #20480 ; 0x5000 + 15dc4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15dc8: ebf5b6d2 bl 0xffd83918 + 15dcc: 08005bcc stmeqda r0, {r2, r3, r6, r7, r8, r9, fp, ip, lr} + 15dd0: e1a04000 mov r4, r0 + 15dd4: ebf5b869 bl 0xffd83f80 + 15dd8: 08005bca stmeqda r0, {r1, r3, r6, r7, r8, r9, fp, ip, lr} + 15ddc: e59d1418 ldr r1, [sp, #1048] + 15de0: e59d1418 ldr r1, [sp, #1048] + 15de4: e2913000 adds r3, r1, #0 ; 0x0 + 15de8: ebf5b864 bl 0xffd83f80 + 15dec: 08005bcc stmeqda r0, {r2, r3, r6, r7, r8, r9, fp, ip, lr} + 15df0: e1a01003 mov r1, r3 + 15df4: e2933018 adds r3, r3, #24 ; 0x18 + 15df8: ebf5b860 bl 0xffd83f80 + 15dfc: 08005bce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, fp, ip, lr} + 15e00: e59d1418 ldr r1, [sp, #1048] + 15e04: e59d1418 ldr r1, [sp, #1048] + 15e08: e2910022 adds r0, r1, #34 ; 0x22 + 15e0c: e58d0418 str r0, [sp, #1048] + 15e10: ebf5b85a bl 0xffd83f80 + 15e14: 08005bd0 stmeqda r0, {r4, r6, r7, r8, r9, fp, ip, lr} + 15e18: e2840000 add r0, r4, #0 ; 0x0 + 15e1c: ebf5b6bd bl 0xffd83918 + 15e20: 08005bd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, fp, ip, lr} + 15e24: e1a05000 mov r5, r0 + 15e28: ebf5b854 bl 0xffd83f80 + 15e2c: 08005bd2 stmeqda r0, {r1, r4, r6, r7, r8, r9, fp, ip, lr} + 15e30: e59d1418 ldr r1, [sp, #1048] + 15e34: e59d1418 ldr r1, [sp, #1048] + 15e38: e2914000 adds r4, r1, #0 ; 0x0 + 15e3c: ebf5b84f bl 0xffd83f80 + 15e40: 08005bd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, fp, ip, lr} + 15e44: ebf5b84d bl 0xffd83f80 + 15e48: 08005bd6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, fp, ip, lr} + 15e4c: e3a000d9 mov r0, #217 ; 0xd9 + 15e50: e3800c5b orr r0, r0, #23296 ; 0x5b00 + 15e54: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 15e58: e58d0438 str r0, [sp, #1080] + 15e5c: e28cc031 add ip, ip, #49 ; 0x31 + 15e60: e1a00fac mov r0, ip, lsr #31 + 15e64: e08ff100 add pc, pc, r0, lsl #2 + 15e68: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 15e6c: ebf5b438 bl 0xffd82f54 + 15e70: eafff156 b 0x123d0 + 15e74: 08005bd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15e78: 00000000 andeq r0, r0, r0 + 15e7c: ebf5b83f bl 0xffd83f80 + 15e80: 08005bd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15e84: e59d0434 ldr r0, [sp, #1076] + 15e88: e2800f01 add r0, r0, #4 ; 0x4 + 15e8c: e58d0434 str r0, [sp, #1076] + 15e90: ebf5b83a bl 0xffd83f80 + 15e94: 08005bda stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15e98: e59d9434 ldr r9, [sp, #1076] + 15e9c: e3c99003 bic r9, r9, #3 ; 0x3 + 15ea0: e2890008 add r0, r9, #8 ; 0x8 + 15ea4: e58d0434 str r0, [sp, #1076] + 15ea8: e2890000 add r0, r9, #0 ; 0x0 + 15eac: ebf5b699 bl 0xffd83918 + 15eb0: 08005bde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15eb4: e1a06000 mov r6, r0 + 15eb8: e2890004 add r0, r9, #4 ; 0x4 + 15ebc: ebf5b695 bl 0xffd83918 + 15ec0: 08005bde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15ec4: e1a07000 mov r7, r0 + 15ec8: ebf5b82c bl 0xffd83f80 + 15ecc: 08005bdc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15ed0: e1a00006 mov r0, r6 + 15ed4: e58d0420 str r0, [sp, #1056] + 15ed8: ebf5b828 bl 0xffd83f80 + 15edc: 08005bde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, lr} + 15ee0: e1a00007 mov r0, r7 + 15ee4: e58d0424 str r0, [sp, #1060] + 15ee8: ebf5b824 bl 0xffd83f80 + 15eec: 08005be0 stmeqda r0, {r5, r6, r7, r8, r9, fp, ip, lr} + 15ef0: e59d9434 ldr r9, [sp, #1076] + 15ef4: e3c99003 bic r9, r9, #3 ; 0x3 + 15ef8: e289000c add r0, r9, #12 ; 0xc + 15efc: e58d0434 str r0, [sp, #1076] + 15f00: e2890000 add r0, r9, #0 ; 0x0 + 15f04: ebf5b683 bl 0xffd83918 + 15f08: 08005be4 stmeqda r0, {r2, r5, r6, r7, r8, r9, fp, ip, lr} + 15f0c: e1a07000 mov r7, r0 + 15f10: e2890004 add r0, r9, #4 ; 0x4 + 15f14: ebf5b67f bl 0xffd83918 + 15f18: 08005be4 stmeqda r0, {r2, r5, r6, r7, r8, r9, fp, ip, lr} + 15f1c: e1a08000 mov r8, r0 + 15f20: e2890008 add r0, r9, #8 ; 0x8 + 15f24: ebf5b67b bl 0xffd83918 + 15f28: 08005be4 stmeqda r0, {r2, r5, r6, r7, r8, r9, fp, ip, lr} + 15f2c: e58d0418 str r0, [sp, #1048] + 15f30: ebf5b812 bl 0xffd83f80 + 15f34: 08005be2 stmeqda r0, {r1, r5, r6, r7, r8, r9, fp, ip, lr} + 15f38: e59d9434 ldr r9, [sp, #1076] + 15f3c: e3c99003 bic r9, r9, #3 ; 0x3 + 15f40: e2890004 add r0, r9, #4 ; 0x4 + 15f44: e58d0434 str r0, [sp, #1076] + 15f48: e2890000 add r0, r9, #0 ; 0x0 + 15f4c: ebf5b671 bl 0xffd83918 + 15f50: 08005be6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, fp, ip, lr} + 15f54: e1a03000 mov r3, r0 + 15f58: ebf5b808 bl 0xffd83f80 + 15f5c: 08005be4 stmeqda r0, {r2, r5, r6, r7, r8, r9, fp, ip, lr} + 15f60: e1a00003 mov r0, r3 + 15f64: e28cc01b add ip, ip, #27 ; 0x1b + 15f68: eaf5b458 b 0xffd830d0 + 15f6c: 08005ae8 stmeqda r0, {r3, r5, r6, r7, r9, fp, ip, lr} + 15f70: 00000000 andeq r0, r0, r0 + 15f74: ebf5b801 bl 0xffd83f80 + 15f78: 08005ae8 stmeqda r0, {r3, r5, r6, r7, r9, fp, ip, lr} + 15f7c: e2870022 add r0, r7, #34 ; 0x22 + 15f80: ebf5b638 bl 0xffd83868 + 15f84: 08005aec stmeqda r0, {r2, r3, r5, r6, r7, r9, fp, ip, lr} + 15f88: e1a03000 mov r3, r0 + 15f8c: ebf5b7fb bl 0xffd83f80 + 15f90: 08005aea stmeqda r0, {r1, r3, r5, r6, r7, r9, fp, ip, lr} + 15f94: e1a01003 mov r1, r3 + 15f98: e2533001 subs r3, r3, #1 ; 0x1 + 15f9c: ebf5b7f7 bl 0xffd83f80 + 15fa0: 08005aec stmeqda r0, {r2, r3, r5, r6, r7, r9, fp, ip, lr} + 15fa4: e2870022 add r0, r7, #34 ; 0x22 + 15fa8: e1a01003 mov r1, r3 + 15fac: ebf5b566 bl 0xffd8354c + 15fb0: 08005aee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, fp, ip, lr} + 15fb4: ebf5b7f1 bl 0xffd83f80 + 15fb8: 08005aee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, fp, ip, lr} + 15fbc: e59d9434 ldr r9, [sp, #1076] + 15fc0: e3c99003 bic r9, r9, #3 ; 0x3 + 15fc4: e2890004 add r0, r9, #4 ; 0x4 + 15fc8: e58d0434 str r0, [sp, #1076] + 15fcc: e2890000 add r0, r9, #0 ; 0x0 + 15fd0: ebf5b650 bl 0xffd83918 + 15fd4: 08005af2 stmeqda r0, {r1, r4, r5, r6, r7, r9, fp, ip, lr} + 15fd8: e1a07000 mov r7, r0 + 15fdc: ebf5b7e7 bl 0xffd83f80 + 15fe0: 08005af0 stmeqda r0, {r4, r5, r6, r7, r9, fp, ip, lr} + 15fe4: e59d9434 ldr r9, [sp, #1076] + 15fe8: e3c99003 bic r9, r9, #3 ; 0x3 + 15fec: e2890004 add r0, r9, #4 ; 0x4 + 15ff0: e58d0434 str r0, [sp, #1076] + 15ff4: e2890000 add r0, r9, #0 ; 0x0 + 15ff8: ebf5b646 bl 0xffd83918 + 15ffc: 08005af4 stmeqda r0, {r2, r4, r5, r6, r7, r9, fp, ip, lr} + 16000: e1a03000 mov r3, r0 + 16004: ebf5b7dd bl 0xffd83f80 + 16008: 08005af2 stmeqda r0, {r1, r4, r5, r6, r7, r9, fp, ip, lr} + 1600c: e1a00003 mov r0, r3 + 16010: e28cc017 add ip, ip, #23 ; 0x17 + 16014: eaf5b42d b 0xffd830d0 + 16018: 08002c82 stmeqda r0, {r1, r7, sl, fp, sp} + 1601c: 00000000 andeq r0, r0, r0 + 16020: ebf5b7d6 bl 0xffd83f80 + 16024: 08002c82 stmeqda r0, {r1, r7, sl, fp, sp} + 16028: ebf5b7d4 bl 0xffd83f80 + 1602c: 08002c84 stmeqda r0, {r2, r7, sl, fp, sp} + 16030: e3a00087 mov r0, #135 ; 0x87 + 16034: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 16038: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1603c: e58d0438 str r0, [sp, #1080] + 16040: e28cc006 add ip, ip, #6 ; 0x6 + 16044: e1a00fac mov r0, ip, lsr #31 + 16048: e08ff100 add pc, pc, r0, lsl #2 + 1604c: 08003ac8 stmeqda r0, {r3, r6, r7, r9, fp, ip, sp} + 16050: ebf5b3bf bl 0xffd82f54 + 16054: ea000001 b 0x16060 + 16058: 08003ac8 stmeqda r0, {r3, r6, r7, r9, fp, ip, sp} + 1605c: 00000000 andeq r0, r0, r0 + 16060: ebf5b7c6 bl 0xffd83f80 + 16064: 08003ac8 stmeqda r0, {r3, r6, r7, r9, fp, ip, sp} + 16068: e59d9434 ldr r9, [sp, #1076] + 1606c: e3c99003 bic r9, r9, #3 ; 0x3 + 16070: e2499014 sub r9, r9, #20 ; 0x14 + 16074: e58d9434 str r9, [sp, #1076] + 16078: e2890000 add r0, r9, #0 ; 0x0 + 1607c: e1a01007 mov r1, r7 + 16080: ebf5b571 bl 0xffd8364c + 16084: e2890004 add r0, r9, #4 ; 0x4 + 16088: e1a01008 mov r1, r8 + 1608c: ebf5b56e bl 0xffd8364c + 16090: e2890008 add r0, r9, #8 ; 0x8 + 16094: e59d1418 ldr r1, [sp, #1048] + 16098: ebf5b56b bl 0xffd8364c + 1609c: e289000c add r0, r9, #12 ; 0xc + 160a0: e59d141c ldr r1, [sp, #1052] + 160a4: ebf5b568 bl 0xffd8364c + 160a8: e2890010 add r0, r9, #16 ; 0x10 + 160ac: e59d1438 ldr r1, [sp, #1080] + 160b0: ebf5b565 bl 0xffd8364c + 160b4: ebf5b7b1 bl 0xffd83f80 + 160b8: 08003aca stmeqda r0, {r1, r3, r6, r7, r9, fp, ip, sp} + 160bc: e59d1428 ldr r1, [sp, #1064] + 160c0: e1a00001 mov r0, r1 + 160c4: e58d041c str r0, [sp, #1052] + 160c8: ebf5b7ac bl 0xffd83f80 + 160cc: 08003acc stmeqda r0, {r2, r3, r6, r7, r9, fp, ip, sp} + 160d0: e59d1424 ldr r1, [sp, #1060] + 160d4: e1a00001 mov r0, r1 + 160d8: e58d0418 str r0, [sp, #1048] + 160dc: ebf5b7a7 bl 0xffd83f80 + 160e0: 08003ace stmeqda r0, {r1, r2, r3, r6, r7, r9, fp, ip, sp} + 160e4: e59d1420 ldr r1, [sp, #1056] + 160e8: e1a08001 mov r8, r1 + 160ec: ebf5b7a3 bl 0xffd83f80 + 160f0: 08003ad0 stmeqda r0, {r4, r6, r7, r9, fp, ip, sp} + 160f4: e59d9434 ldr r9, [sp, #1076] + 160f8: e3c99003 bic r9, r9, #3 ; 0x3 + 160fc: e249900c sub r9, r9, #12 ; 0xc + 16100: e58d9434 str r9, [sp, #1076] + 16104: e2890000 add r0, r9, #0 ; 0x0 + 16108: e1a01008 mov r1, r8 + 1610c: ebf5b54e bl 0xffd8364c + 16110: e2890004 add r0, r9, #4 ; 0x4 + 16114: e59d1418 ldr r1, [sp, #1048] + 16118: ebf5b54b bl 0xffd8364c + 1611c: e2890008 add r0, r9, #8 ; 0x8 + 16120: e59d141c ldr r1, [sp, #1052] + 16124: ebf5b528 bl 0xffd835cc + 16128: 08003ad2 stmeqda r0, {r1, r4, r6, r7, r9, fp, ip, sp} + 1612c: ebf5b793 bl 0xffd83f80 + 16130: 08003ad2 stmeqda r0, {r1, r4, r6, r7, r9, fp, ip, sp} + 16134: e59d0434 ldr r0, [sp, #1076] + 16138: e2400f01 sub r0, r0, #4 ; 0x4 + 1613c: e58d0434 str r0, [sp, #1076] + 16140: ebf5b78e bl 0xffd83f80 + 16144: 08003ad4 stmeqda r0, {r2, r4, r6, r7, r9, fp, ip, sp} + 16148: e3a00fbb mov r0, #748 ; 0x2ec + 1614c: e3800b0e orr r0, r0, #14336 ; 0x3800 + 16150: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16154: ebf5b5ef bl 0xffd83918 + 16158: 08003ad8 stmeqda r0, {r3, r4, r6, r7, r9, fp, ip, sp} + 1615c: e1a07000 mov r7, r0 + 16160: ebf5b786 bl 0xffd83f80 + 16164: 08003ad6 stmeqda r0, {r1, r2, r4, r6, r7, r9, fp, ip, sp} + 16168: e3a00eaf mov r0, #2800 ; 0xaf0 + 1616c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 16170: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16174: ebf5b5e7 bl 0xffd83918 + 16178: 08003ada stmeqda r0, {r1, r3, r4, r6, r7, r9, fp, ip, sp} + 1617c: e1a04000 mov r4, r0 + 16180: ebf5b77e bl 0xffd83f80 + 16184: 08003ad8 stmeqda r0, {r3, r4, r6, r7, r9, fp, ip, sp} + 16188: e1a01007 mov r1, r7 + 1618c: e0973004 adds r3, r7, r4 + 16190: ebf5b77a bl 0xffd83f80 + 16194: 08003ada stmeqda r0, {r1, r3, r4, r6, r7, r9, fp, ip, sp} + 16198: e2830000 add r0, r3, #0 ; 0x0 + 1619c: ebf5b5dd bl 0xffd83918 + 161a0: 08003ade stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, fp, ip, sp} + 161a4: e1a05000 mov r5, r0 + 161a8: ebf5b774 bl 0xffd83f80 + 161ac: 08003adc stmeqda r0, {r2, r3, r4, r6, r7, r9, fp, ip, sp} + 161b0: e3550000 cmp r5, #0 ; 0x0 + 161b4: ebf5b771 bl 0xffd83f80 + 161b8: 08003ade stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, fp, ip, sp} + 161bc: e28cc031 add ip, ip, #49 ; 0x31 + 161c0: ba000004 blt 0x161d8 + 161c4: e1a00fac mov r0, ip, lsr #31 + 161c8: e08ff100 add pc, pc, r0, lsl #2 + 161cc: 08003afc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, fp, ip, sp} + 161d0: ebf5b35f bl 0xffd82f54 + 161d4: ea000029 b 0x16280 + 161d8: ebf5b768 bl 0xffd83f80 + 161dc: 08003ae0 stmeqda r0, {r5, r6, r7, r9, fp, ip, sp} + 161e0: e3a00fbd mov r0, #756 ; 0x2f4 + 161e4: e3800b0e orr r0, r0, #14336 ; 0x3800 + 161e8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 161ec: ebf5b5c9 bl 0xffd83918 + 161f0: 08003ae4 stmeqda r0, {r2, r5, r6, r7, r9, fp, ip, sp} + 161f4: e1a05000 mov r5, r0 + 161f8: ebf5b760 bl 0xffd83f80 + 161fc: 08003ae2 stmeqda r0, {r1, r5, r6, r7, r9, fp, ip, sp} + 16200: e2850000 add r0, r5, #0 ; 0x0 + 16204: ebf5b597 bl 0xffd83868 + 16208: 08003ae6 stmeqda r0, {r1, r2, r5, r6, r7, r9, fp, ip, sp} + 1620c: e1a04000 mov r4, r0 + 16210: ebf5b75a bl 0xffd83f80 + 16214: 08003ae4 stmeqda r0, {r2, r5, r6, r7, r9, fp, ip, sp} + 16218: e3a00fbe mov r0, #760 ; 0x2f8 + 1621c: e3800b0e orr r0, r0, #14336 ; 0x3800 + 16220: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16224: ebf5b5bb bl 0xffd83918 + 16228: 08003ae8 stmeqda r0, {r3, r5, r6, r7, r9, fp, ip, sp} + 1622c: e1a03000 mov r3, r0 + 16230: ebf5b752 bl 0xffd83f80 + 16234: 08003ae6 stmeqda r0, {r1, r2, r5, r6, r7, r9, fp, ip, sp} + 16238: e1a01003 mov r1, r3 + 1623c: e0133004 ands r3, r3, r4 + 16240: ebf5b74e bl 0xffd83f80 + 16244: 08003ae8 stmeqda r0, {r3, r5, r6, r7, r9, fp, ip, sp} + 16248: e2850000 add r0, r5, #0 ; 0x0 + 1624c: e1a01003 mov r1, r3 + 16250: ebf5b4bd bl 0xffd8354c + 16254: 08003aea stmeqda r0, {r1, r3, r5, r6, r7, r9, fp, ip, sp} + 16258: ebf5b748 bl 0xffd83f80 + 1625c: 08003aea stmeqda r0, {r1, r3, r5, r6, r7, r9, fp, ip, sp} + 16260: e28cc019 add ip, ip, #25 ; 0x19 + 16264: e1a00fac mov r0, ip, lsr #31 + 16268: e08ff100 add pc, pc, r0, lsl #2 + 1626c: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 16270: ebf5b337 bl 0xffd82f54 + 16274: ea0000d9 b 0x165e0 + 16278: 08003afc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, fp, ip, sp} + 1627c: 00000000 andeq r0, r0, r0 + 16280: ebf5b73e bl 0xffd83f80 + 16284: 08003afc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, fp, ip, sp} + 16288: e3a00fd5 mov r0, #852 ; 0x354 + 1628c: e3800b0e orr r0, r0, #14336 ; 0x3800 + 16290: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16294: ebf5b59f bl 0xffd83918 + 16298: 08003b00 stmeqda r0, {r8, r9, fp, ip, sp} + 1629c: e1a06000 mov r6, r0 + 162a0: ebf5b736 bl 0xffd83f80 + 162a4: 08003afe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, fp, ip, sp} + 162a8: e2860000 add r0, r6, #0 ; 0x0 + 162ac: ebf5b56d bl 0xffd83868 + 162b0: 08003b02 stmeqda r0, {r1, r8, r9, fp, ip, sp} + 162b4: e1a03000 mov r3, r0 + 162b8: ebf5b730 bl 0xffd83f80 + 162bc: 08003b00 stmeqda r0, {r8, r9, fp, ip, sp} + 162c0: e3a00fd6 mov r0, #856 ; 0x358 + 162c4: e3800b0e orr r0, r0, #14336 ; 0x3800 + 162c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 162cc: ebf5b591 bl 0xffd83918 + 162d0: 08003b04 stmeqda r0, {r2, r8, r9, fp, ip, sp} + 162d4: e1a04000 mov r4, r0 + 162d8: ebf5b728 bl 0xffd83f80 + 162dc: 08003b02 stmeqda r0, {r1, r8, r9, fp, ip, sp} + 162e0: e1a01004 mov r1, r4 + 162e4: e0144003 ands r4, r4, r3 + 162e8: ebf5b724 bl 0xffd83f80 + 162ec: 08003b04 stmeqda r0, {r2, r8, r9, fp, ip, sp} + 162f0: e1a01005 mov r1, r5 + 162f4: e1955004 orrs r5, r5, r4 + 162f8: ebf5b720 bl 0xffd83f80 + 162fc: 08003b06 stmeqda r0, {r1, r2, r8, r9, fp, ip, sp} + 16300: e2860000 add r0, r6, #0 ; 0x0 + 16304: e1a01005 mov r1, r5 + 16308: ebf5b48f bl 0xffd8354c + 1630c: 08003b08 stmeqda r0, {r3, r8, r9, fp, ip, sp} + 16310: ebf5b71a bl 0xffd83f80 + 16314: 08003b08 stmeqda r0, {r3, r8, r9, fp, ip, sp} + 16318: e3b05093 movs r5, #147 ; 0x93 + 1631c: ebf5b717 bl 0xffd83f80 + 16320: 08003b0a stmeqda r0, {r1, r3, r8, r9, fp, ip, sp} + 16324: e1b05285 movs r5, r5, lsl #5 + 16328: ebf5b714 bl 0xffd83f80 + 1632c: 08003b0c stmeqda r0, {r2, r3, r8, r9, fp, ip, sp} + 16330: e1a01005 mov r1, r5 + 16334: e0955007 adds r5, r5, r7 + 16338: ebf5b710 bl 0xffd83f80 + 1633c: 08003b0e stmeqda r0, {r1, r2, r3, r8, r9, fp, ip, sp} + 16340: e1a00005 mov r0, r5 + 16344: e58d0420 str r0, [sp, #1056] + 16348: ebf5b70c bl 0xffd83f80 + 1634c: 08003b10 stmeqda r0, {r4, r8, r9, fp, ip, sp} + 16350: e3b00000 movs r0, #0 ; 0x0 + 16354: e58d041c str r0, [sp, #1052] + 16358: ebf5b708 bl 0xffd83f80 + 1635c: 08003b12 stmeqda r0, {r1, r4, r8, r9, fp, ip, sp} + 16360: e59d0434 ldr r0, [sp, #1076] + 16364: e2800f00 add r0, r0, #0 ; 0x0 + 16368: e59d141c ldr r1, [sp, #1052] + 1636c: ebf5b496 bl 0xffd835cc + 16370: 08003b14 stmeqda r0, {r2, r4, r8, r9, fp, ip, sp} + 16374: ebf5b701 bl 0xffd83f80 + 16378: 08003b14 stmeqda r0, {r2, r4, r8, r9, fp, ip, sp} + 1637c: e3b0409b movs r4, #155 ; 0x9b + 16380: ebf5b6fe bl 0xffd83f80 + 16384: 08003b16 stmeqda r0, {r1, r2, r4, r8, r9, fp, ip, sp} + 16388: e1b04284 movs r4, r4, lsl #5 + 1638c: ebf5b6fb bl 0xffd83f80 + 16390: 08003b18 stmeqda r0, {r3, r4, r8, r9, fp, ip, sp} + 16394: e1a01007 mov r1, r7 + 16398: e0973004 adds r3, r7, r4 + 1639c: ebf5b6f7 bl 0xffd83f80 + 163a0: 08003b1a stmeqda r0, {r1, r3, r4, r8, r9, fp, ip, sp} + 163a4: e59d0420 ldr r0, [sp, #1056] + 163a8: e1500003 cmp r0, r3 + 163ac: ebf5b6f3 bl 0xffd83f80 + 163b0: 08003b1c stmeqda r0, {r2, r3, r4, r8, r9, fp, ip, sp} + 163b4: e28cc03b add ip, ip, #59 ; 0x3b + 163b8: 2a000004 bcs 0x163d0 + 163bc: e1a00fac mov r0, ip, lsr #31 + 163c0: e08ff100 add pc, pc, r0, lsl #2 + 163c4: 08003b20 stmeqda r0, {r5, r8, r9, fp, ip, sp} + 163c8: ebf5b2e1 bl 0xffd82f54 + 163cc: ea000007 b 0x163f0 + 163d0: ebf5b6ea bl 0xffd83f80 + 163d4: 08003b1e stmeqda r0, {r1, r2, r3, r4, r8, r9, fp, ip, sp} + 163d8: e28cc003 add ip, ip, #3 ; 0x3 + 163dc: e1a00fac mov r0, ip, lsr #31 + 163e0: e08ff100 add pc, pc, r0, lsl #2 + 163e4: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 163e8: ebf5b2d9 bl 0xffd82f54 + 163ec: ea00007b b 0x165e0 + 163f0: ebf5b6e2 bl 0xffd83f80 + 163f4: 08003b20 stmeqda r0, {r5, r8, r9, fp, ip, sp} + 163f8: e1a00006 mov r0, r6 + 163fc: e58d0428 str r0, [sp, #1064] + 16400: ebf5b6de bl 0xffd83f80 + 16404: 08003b22 stmeqda r0, {r1, r5, r8, r9, fp, ip, sp} + 16408: e59d1420 ldr r1, [sp, #1056] + 1640c: e1a05001 mov r5, r1 + 16410: ebf5b6da bl 0xffd83f80 + 16414: 08003b24 stmeqda r0, {r2, r5, r8, r9, fp, ip, sp} + 16418: e2850000 add r0, r5, #0 ; 0x0 + 1641c: ebf5b511 bl 0xffd83868 + 16420: 08003b28 stmeqda r0, {r3, r5, r8, r9, fp, ip, sp} + 16424: e1a04000 mov r4, r0 + 16428: ebf5b6d4 bl 0xffd83f80 + 1642c: 08003b26 stmeqda r0, {r1, r2, r5, r8, r9, fp, ip, sp} + 16430: e3b06080 movs r6, #128 ; 0x80 + 16434: ebf5b6d1 bl 0xffd83f80 + 16438: 08003b28 stmeqda r0, {r3, r5, r8, r9, fp, ip, sp} + 1643c: e1b06406 movs r6, r6, lsl #8 + 16440: ebf5b6ce bl 0xffd83f80 + 16444: 08003b2a stmeqda r0, {r1, r3, r5, r8, r9, fp, ip, sp} + 16448: e1a01006 mov r1, r6 + 1644c: e2963000 adds r3, r6, #0 ; 0x0 + 16450: ebf5b6ca bl 0xffd83f80 + 16454: 08003b2c stmeqda r0, {r2, r3, r5, r8, r9, fp, ip, sp} + 16458: e1a01003 mov r1, r3 + 1645c: e0133004 ands r3, r3, r4 + 16460: ebf5b6c6 bl 0xffd83f80 + 16464: 08003b2e stmeqda r0, {r1, r2, r3, r5, r8, r9, fp, ip, sp} + 16468: e3530000 cmp r3, #0 ; 0x0 + 1646c: ebf5b6c3 bl 0xffd83f80 + 16470: 08003b30 stmeqda r0, {r4, r5, r8, r9, fp, ip, sp} + 16474: e28cc01d add ip, ip, #29 ; 0x1d + 16478: 0a000004 beq 0x16490 + 1647c: e1a00fac mov r0, ip, lsr #31 + 16480: e08ff100 add pc, pc, r0, lsl #2 + 16484: 08003b34 stmeqda r0, {r2, r4, r5, r8, r9, fp, ip, sp} + 16488: ebf5b2b1 bl 0xffd82f54 + 1648c: ea000007 b 0x164b0 + 16490: ebf5b6ba bl 0xffd83f80 + 16494: 08003b32 stmeqda r0, {r1, r4, r5, r8, r9, fp, ip, sp} + 16498: e28cc003 add ip, ip, #3 ; 0x3 + 1649c: e1a00fac mov r0, ip, lsr #31 + 164a0: e08ff100 add pc, pc, r0, lsl #2 + 164a4: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 164a8: ebf5b2a9 bl 0xffd82f54 + 164ac: ea000095 b 0x16708 + 164b0: ebf5b6b2 bl 0xffd83f80 + 164b4: 08003b34 stmeqda r0, {r2, r4, r5, r8, r9, fp, ip, sp} + 164b8: e3b07080 movs r7, #128 ; 0x80 + 164bc: ebf5b6af bl 0xffd83f80 + 164c0: 08003b36 stmeqda r0, {r1, r2, r4, r5, r8, r9, fp, ip, sp} + 164c4: e1b07287 movs r7, r7, lsl #5 + 164c8: ebf5b6ac bl 0xffd83f80 + 164cc: 08003b38 stmeqda r0, {r3, r4, r5, r8, r9, fp, ip, sp} + 164d0: e1a01007 mov r1, r7 + 164d4: e2973000 adds r3, r7, #0 ; 0x0 + 164d8: ebf5b6a8 bl 0xffd83f80 + 164dc: 08003b3a stmeqda r0, {r1, r3, r4, r5, r8, r9, fp, ip, sp} + 164e0: e1a01003 mov r1, r3 + 164e4: e0133004 ands r3, r3, r4 + 164e8: ebf5b6a4 bl 0xffd83f80 + 164ec: 08003b3c stmeqda r0, {r2, r3, r4, r5, r8, r9, fp, ip, sp} + 164f0: e3530000 cmp r3, #0 ; 0x0 + 164f4: ebf5b6a1 bl 0xffd83f80 + 164f8: 08003b3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, fp, ip, sp} + 164fc: e28cc012 add ip, ip, #18 ; 0x12 + 16500: 0a000004 beq 0x16518 + 16504: e1a00fac mov r0, ip, lsr #31 + 16508: e08ff100 add pc, pc, r0, lsl #2 + 1650c: 08003b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, ip, sp} + 16510: ebf5b28f bl 0xffd82f54 + 16514: ea000174 b 0x16aec + 16518: ebf5b698 bl 0xffd83f80 + 1651c: 08003b40 stmeqda r0, {r6, r8, r9, fp, ip, sp} + 16520: e3b00080 movs r0, #128 ; 0x80 + 16524: e58d041c str r0, [sp, #1052] + 16528: ebf5b694 bl 0xffd83f80 + 1652c: 08003b42 stmeqda r0, {r1, r6, r8, r9, fp, ip, sp} + 16530: e59de41c ldr lr, [sp, #1052] + 16534: e1b0038e movs r0, lr, lsl #7 + 16538: e58d041c str r0, [sp, #1052] + 1653c: ebf5b68f bl 0xffd83f80 + 16540: 08003b44 stmeqda r0, {r2, r6, r8, r9, fp, ip, sp} + 16544: e59d141c ldr r1, [sp, #1052] + 16548: e59d141c ldr r1, [sp, #1052] + 1654c: e2913000 adds r3, r1, #0 ; 0x0 + 16550: ebf5b68a bl 0xffd83f80 + 16554: 08003b46 stmeqda r0, {r1, r2, r6, r8, r9, fp, ip, sp} + 16558: e1a01003 mov r1, r3 + 1655c: e0133004 ands r3, r3, r4 + 16560: ebf5b686 bl 0xffd83f80 + 16564: 08003b48 stmeqda r0, {r3, r6, r8, r9, fp, ip, sp} + 16568: e3530000 cmp r3, #0 ; 0x0 + 1656c: ebf5b683 bl 0xffd83f80 + 16570: 08003b4a stmeqda r0, {r1, r3, r6, r8, r9, fp, ip, sp} + 16574: e28cc012 add ip, ip, #18 ; 0x12 + 16578: 0a000004 beq 0x16590 + 1657c: e1a00fac mov r0, ip, lsr #31 + 16580: e08ff100 add pc, pc, r0, lsl #2 + 16584: 08003b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, ip, sp} + 16588: ebf5b271 bl 0xffd82f54 + 1658c: ea00039d b 0x17408 + 16590: ebf5b67a bl 0xffd83f80 + 16594: 08003b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, ip, sp} + 16598: e59d1420 ldr r1, [sp, #1056] + 1659c: e1a03001 mov r3, r1 + 165a0: ebf5b676 bl 0xffd83f80 + 165a4: 08003b4e stmeqda r0, {r1, r2, r3, r6, r8, r9, fp, ip, sp} + 165a8: ebf5b674 bl 0xffd83f80 + 165ac: 08003b50 stmeqda r0, {r4, r6, r8, r9, fp, ip, sp} + 165b0: e3a00053 mov r0, #83 ; 0x53 + 165b4: e3800c3b orr r0, r0, #15104 ; 0x3b00 + 165b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 165bc: e58d0438 str r0, [sp, #1080] + 165c0: e28cc009 add ip, ip, #9 ; 0x9 + 165c4: e1a00fac mov r0, ip, lsr #31 + 165c8: e08ff100 add pc, pc, r0, lsl #2 + 165cc: 08003ddc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp} + 165d0: ebf5b25f bl 0xffd82f54 + 165d4: ea00136c b 0x1b38c + 165d8: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 165dc: 00000000 andeq r0, r0, r0 + 165e0: ebf5b666 bl 0xffd83f80 + 165e4: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 165e8: e59d0434 ldr r0, [sp, #1076] + 165ec: e2800f01 add r0, r0, #4 ; 0x4 + 165f0: e58d0434 str r0, [sp, #1076] + 165f4: ebf5b661 bl 0xffd83f80 + 165f8: 08003dbc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 165fc: e59d9434 ldr r9, [sp, #1076] + 16600: e3c99003 bic r9, r9, #3 ; 0x3 + 16604: e289000c add r0, r9, #12 ; 0xc + 16608: e58d0434 str r0, [sp, #1076] + 1660c: e2890000 add r0, r9, #0 ; 0x0 + 16610: ebf5b4c0 bl 0xffd83918 + 16614: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 16618: e1a06000 mov r6, r0 + 1661c: e2890004 add r0, r9, #4 ; 0x4 + 16620: ebf5b4bc bl 0xffd83918 + 16624: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 16628: e1a07000 mov r7, r0 + 1662c: e2890008 add r0, r9, #8 ; 0x8 + 16630: ebf5b4b8 bl 0xffd83918 + 16634: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 16638: e1a08000 mov r8, r0 + 1663c: ebf5b64f bl 0xffd83f80 + 16640: 08003dbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 16644: e1a00006 mov r0, r6 + 16648: e58d0420 str r0, [sp, #1056] + 1664c: ebf5b64b bl 0xffd83f80 + 16650: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 16654: e1a00007 mov r0, r7 + 16658: e58d0424 str r0, [sp, #1060] + 1665c: ebf5b647 bl 0xffd83f80 + 16660: 08003dc2 stmeqda r0, {r1, r6, r7, r8, sl, fp, ip, sp} + 16664: e1a00008 mov r0, r8 + 16668: e58d0428 str r0, [sp, #1064] + 1666c: ebf5b643 bl 0xffd83f80 + 16670: 08003dc4 stmeqda r0, {r2, r6, r7, r8, sl, fp, ip, sp} + 16674: e59d9434 ldr r9, [sp, #1076] + 16678: e3c99003 bic r9, r9, #3 ; 0x3 + 1667c: e2890010 add r0, r9, #16 ; 0x10 + 16680: e58d0434 str r0, [sp, #1076] + 16684: e2890000 add r0, r9, #0 ; 0x0 + 16688: ebf5b4a2 bl 0xffd83918 + 1668c: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 16690: e1a07000 mov r7, r0 + 16694: e2890004 add r0, r9, #4 ; 0x4 + 16698: ebf5b49e bl 0xffd83918 + 1669c: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 166a0: e1a08000 mov r8, r0 + 166a4: e2890008 add r0, r9, #8 ; 0x8 + 166a8: ebf5b49a bl 0xffd83918 + 166ac: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 166b0: e58d0418 str r0, [sp, #1048] + 166b4: e289000c add r0, r9, #12 ; 0xc + 166b8: ebf5b496 bl 0xffd83918 + 166bc: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 166c0: e58d041c str r0, [sp, #1052] + 166c4: ebf5b62d bl 0xffd83f80 + 166c8: 08003dc6 stmeqda r0, {r1, r2, r6, r7, r8, sl, fp, ip, sp} + 166cc: e59d9434 ldr r9, [sp, #1076] + 166d0: e3c99003 bic r9, r9, #3 ; 0x3 + 166d4: e2890004 add r0, r9, #4 ; 0x4 + 166d8: e58d0434 str r0, [sp, #1076] + 166dc: e2890000 add r0, r9, #0 ; 0x0 + 166e0: ebf5b48c bl 0xffd83918 + 166e4: 08003dca stmeqda r0, {r1, r3, r6, r7, r8, sl, fp, ip, sp} + 166e8: e1a03000 mov r3, r0 + 166ec: ebf5b623 bl 0xffd83f80 + 166f0: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 166f4: e1a00003 mov r0, r3 + 166f8: e28cc020 add ip, ip, #32 ; 0x20 + 166fc: eaf5b273 b 0xffd830d0 + 16700: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 16704: 00000000 andeq r0, r0, r0 + 16708: ebf5b61c bl 0xffd83f80 + 1670c: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 16710: e3b03040 movs r3, #64 ; 0x40 + 16714: ebf5b619 bl 0xffd83f80 + 16718: 08003daa stmeqda r0, {r1, r3, r5, r7, r8, sl, fp, ip, sp} + 1671c: e59d0420 ldr r0, [sp, #1056] + 16720: e0800003 add r0, r0, r3 + 16724: e58d0420 str r0, [sp, #1056] + 16728: ebf5b614 bl 0xffd83f80 + 1672c: 08003dac stmeqda r0, {r2, r3, r5, r7, r8, sl, fp, ip, sp} + 16730: e59d0434 ldr r0, [sp, #1076] + 16734: e2800f00 add r0, r0, #0 ; 0x0 + 16738: ebf5b476 bl 0xffd83918 + 1673c: 08003db0 stmeqda r0, {r4, r5, r7, r8, sl, fp, ip, sp} + 16740: e1a04000 mov r4, r0 + 16744: ebf5b60d bl 0xffd83f80 + 16748: 08003dae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, fp, ip, sp} + 1674c: e1a01004 mov r1, r4 + 16750: e2944001 adds r4, r4, #1 ; 0x1 + 16754: ebf5b609 bl 0xffd83f80 + 16758: 08003db0 stmeqda r0, {r4, r5, r7, r8, sl, fp, ip, sp} + 1675c: e59d0434 ldr r0, [sp, #1076] + 16760: e2800f00 add r0, r0, #0 ; 0x0 + 16764: e1a01004 mov r1, r4 + 16768: ebf5b397 bl 0xffd835cc + 1676c: 08003db2 stmeqda r0, {r1, r4, r5, r7, r8, sl, fp, ip, sp} + 16770: ebf5b602 bl 0xffd83f80 + 16774: 08003db2 stmeqda r0, {r1, r4, r5, r7, r8, sl, fp, ip, sp} + 16778: e3a00f76 mov r0, #472 ; 0x1d8 + 1677c: e3800b0f orr r0, r0, #15360 ; 0x3c00 + 16780: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16784: ebf5b463 bl 0xffd83918 + 16788: 08003db6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl, fp, ip, sp} + 1678c: e1a03000 mov r3, r0 + 16790: ebf5b5fa bl 0xffd83f80 + 16794: 08003db4 stmeqda r0, {r2, r4, r5, r7, r8, sl, fp, ip, sp} + 16798: e59d0420 ldr r0, [sp, #1056] + 1679c: e1500003 cmp r0, r3 + 167a0: ebf5b5f6 bl 0xffd83f80 + 167a4: 08003db6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl, fp, ip, sp} + 167a8: e28cc01d add ip, ip, #29 ; 0x1d + 167ac: 3a000004 bcc 0x167c4 + 167b0: e1a00fac mov r0, ip, lsr #31 + 167b4: e08ff100 add pc, pc, r0, lsl #2 + 167b8: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 167bc: ebf5b1e4 bl 0xffd82f54 + 167c0: ea000007 b 0x167e4 + 167c4: ebf5b5ed bl 0xffd83f80 + 167c8: 08003db8 stmeqda r0, {r3, r4, r5, r7, r8, sl, fp, ip, sp} + 167cc: e28cc003 add ip, ip, #3 ; 0x3 + 167d0: e1a00fac mov r0, ip, lsr #31 + 167d4: e08ff100 add pc, pc, r0, lsl #2 + 167d8: 08003b22 stmeqda r0, {r1, r5, r8, r9, fp, ip, sp} + 167dc: ebf5b1dc bl 0xffd82f54 + 167e0: ea000049 b 0x1690c + 167e4: ebf5b5e5 bl 0xffd83f80 + 167e8: 08003dba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 167ec: e59d0434 ldr r0, [sp, #1076] + 167f0: e2800f01 add r0, r0, #4 ; 0x4 + 167f4: e58d0434 str r0, [sp, #1076] + 167f8: ebf5b5e0 bl 0xffd83f80 + 167fc: 08003dbc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 16800: e59d9434 ldr r9, [sp, #1076] + 16804: e3c99003 bic r9, r9, #3 ; 0x3 + 16808: e289000c add r0, r9, #12 ; 0xc + 1680c: e58d0434 str r0, [sp, #1076] + 16810: e2890000 add r0, r9, #0 ; 0x0 + 16814: ebf5b43f bl 0xffd83918 + 16818: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 1681c: e1a06000 mov r6, r0 + 16820: e2890004 add r0, r9, #4 ; 0x4 + 16824: ebf5b43b bl 0xffd83918 + 16828: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 1682c: e1a07000 mov r7, r0 + 16830: e2890008 add r0, r9, #8 ; 0x8 + 16834: ebf5b437 bl 0xffd83918 + 16838: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 1683c: e1a08000 mov r8, r0 + 16840: ebf5b5ce bl 0xffd83f80 + 16844: 08003dbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, fp, ip, sp} + 16848: e1a00006 mov r0, r6 + 1684c: e58d0420 str r0, [sp, #1056] + 16850: ebf5b5ca bl 0xffd83f80 + 16854: 08003dc0 stmeqda r0, {r6, r7, r8, sl, fp, ip, sp} + 16858: e1a00007 mov r0, r7 + 1685c: e58d0424 str r0, [sp, #1060] + 16860: ebf5b5c6 bl 0xffd83f80 + 16864: 08003dc2 stmeqda r0, {r1, r6, r7, r8, sl, fp, ip, sp} + 16868: e1a00008 mov r0, r8 + 1686c: e58d0428 str r0, [sp, #1064] + 16870: ebf5b5c2 bl 0xffd83f80 + 16874: 08003dc4 stmeqda r0, {r2, r6, r7, r8, sl, fp, ip, sp} + 16878: e59d9434 ldr r9, [sp, #1076] + 1687c: e3c99003 bic r9, r9, #3 ; 0x3 + 16880: e2890010 add r0, r9, #16 ; 0x10 + 16884: e58d0434 str r0, [sp, #1076] + 16888: e2890000 add r0, r9, #0 ; 0x0 + 1688c: ebf5b421 bl 0xffd83918 + 16890: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 16894: e1a07000 mov r7, r0 + 16898: e2890004 add r0, r9, #4 ; 0x4 + 1689c: ebf5b41d bl 0xffd83918 + 168a0: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 168a4: e1a08000 mov r8, r0 + 168a8: e2890008 add r0, r9, #8 ; 0x8 + 168ac: ebf5b419 bl 0xffd83918 + 168b0: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 168b4: e58d0418 str r0, [sp, #1048] + 168b8: e289000c add r0, r9, #12 ; 0xc + 168bc: ebf5b415 bl 0xffd83918 + 168c0: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 168c4: e58d041c str r0, [sp, #1052] + 168c8: ebf5b5ac bl 0xffd83f80 + 168cc: 08003dc6 stmeqda r0, {r1, r2, r6, r7, r8, sl, fp, ip, sp} + 168d0: e59d9434 ldr r9, [sp, #1076] + 168d4: e3c99003 bic r9, r9, #3 ; 0x3 + 168d8: e2890004 add r0, r9, #4 ; 0x4 + 168dc: e58d0434 str r0, [sp, #1076] + 168e0: e2890000 add r0, r9, #0 ; 0x0 + 168e4: ebf5b40b bl 0xffd83918 + 168e8: 08003dca stmeqda r0, {r1, r3, r6, r7, r8, sl, fp, ip, sp} + 168ec: e1a03000 mov r3, r0 + 168f0: ebf5b5a2 bl 0xffd83f80 + 168f4: 08003dc8 stmeqda r0, {r3, r6, r7, r8, sl, fp, ip, sp} + 168f8: e1a00003 mov r0, r3 + 168fc: e28cc020 add ip, ip, #32 ; 0x20 + 16900: eaf5b1f2 b 0xffd830d0 + 16904: 08003b22 stmeqda r0, {r1, r5, r8, r9, fp, ip, sp} + 16908: 00000000 andeq r0, r0, r0 + 1690c: ebf5b59b bl 0xffd83f80 + 16910: 08003b22 stmeqda r0, {r1, r5, r8, r9, fp, ip, sp} + 16914: e59d1420 ldr r1, [sp, #1056] + 16918: e1a05001 mov r5, r1 + 1691c: ebf5b597 bl 0xffd83f80 + 16920: 08003b24 stmeqda r0, {r2, r5, r8, r9, fp, ip, sp} + 16924: e2850000 add r0, r5, #0 ; 0x0 + 16928: ebf5b3ce bl 0xffd83868 + 1692c: 08003b28 stmeqda r0, {r3, r5, r8, r9, fp, ip, sp} + 16930: e1a04000 mov r4, r0 + 16934: ebf5b591 bl 0xffd83f80 + 16938: 08003b26 stmeqda r0, {r1, r2, r5, r8, r9, fp, ip, sp} + 1693c: e3b06080 movs r6, #128 ; 0x80 + 16940: ebf5b58e bl 0xffd83f80 + 16944: 08003b28 stmeqda r0, {r3, r5, r8, r9, fp, ip, sp} + 16948: e1b06406 movs r6, r6, lsl #8 + 1694c: ebf5b58b bl 0xffd83f80 + 16950: 08003b2a stmeqda r0, {r1, r3, r5, r8, r9, fp, ip, sp} + 16954: e1a01006 mov r1, r6 + 16958: e2963000 adds r3, r6, #0 ; 0x0 + 1695c: ebf5b587 bl 0xffd83f80 + 16960: 08003b2c stmeqda r0, {r2, r3, r5, r8, r9, fp, ip, sp} + 16964: e1a01003 mov r1, r3 + 16968: e0133004 ands r3, r3, r4 + 1696c: ebf5b583 bl 0xffd83f80 + 16970: 08003b2e stmeqda r0, {r1, r2, r3, r5, r8, r9, fp, ip, sp} + 16974: e3530000 cmp r3, #0 ; 0x0 + 16978: ebf5b580 bl 0xffd83f80 + 1697c: 08003b30 stmeqda r0, {r4, r5, r8, r9, fp, ip, sp} + 16980: e28cc01a add ip, ip, #26 ; 0x1a + 16984: 0a000004 beq 0x1699c + 16988: e1a00fac mov r0, ip, lsr #31 + 1698c: e08ff100 add pc, pc, r0, lsl #2 + 16990: 08003b34 stmeqda r0, {r2, r4, r5, r8, r9, fp, ip, sp} + 16994: ebf5b16e bl 0xffd82f54 + 16998: ea000007 b 0x169bc + 1699c: ebf5b577 bl 0xffd83f80 + 169a0: 08003b32 stmeqda r0, {r1, r4, r5, r8, r9, fp, ip, sp} + 169a4: e28cc003 add ip, ip, #3 ; 0x3 + 169a8: e1a00fac mov r0, ip, lsr #31 + 169ac: e08ff100 add pc, pc, r0, lsl #2 + 169b0: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 169b4: ebf5b166 bl 0xffd82f54 + 169b8: eaffff52 b 0x16708 + 169bc: ebf5b56f bl 0xffd83f80 + 169c0: 08003b34 stmeqda r0, {r2, r4, r5, r8, r9, fp, ip, sp} + 169c4: e3b07080 movs r7, #128 ; 0x80 + 169c8: ebf5b56c bl 0xffd83f80 + 169cc: 08003b36 stmeqda r0, {r1, r2, r4, r5, r8, r9, fp, ip, sp} + 169d0: e1b07287 movs r7, r7, lsl #5 + 169d4: ebf5b569 bl 0xffd83f80 + 169d8: 08003b38 stmeqda r0, {r3, r4, r5, r8, r9, fp, ip, sp} + 169dc: e1a01007 mov r1, r7 + 169e0: e2973000 adds r3, r7, #0 ; 0x0 + 169e4: ebf5b565 bl 0xffd83f80 + 169e8: 08003b3a stmeqda r0, {r1, r3, r4, r5, r8, r9, fp, ip, sp} + 169ec: e1a01003 mov r1, r3 + 169f0: e0133004 ands r3, r3, r4 + 169f4: ebf5b561 bl 0xffd83f80 + 169f8: 08003b3c stmeqda r0, {r2, r3, r4, r5, r8, r9, fp, ip, sp} + 169fc: e3530000 cmp r3, #0 ; 0x0 + 16a00: ebf5b55e bl 0xffd83f80 + 16a04: 08003b3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, fp, ip, sp} + 16a08: e28cc012 add ip, ip, #18 ; 0x12 + 16a0c: 0a000004 beq 0x16a24 + 16a10: e1a00fac mov r0, ip, lsr #31 + 16a14: e08ff100 add pc, pc, r0, lsl #2 + 16a18: 08003b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, ip, sp} + 16a1c: ebf5b14c bl 0xffd82f54 + 16a20: ea000031 b 0x16aec + 16a24: ebf5b555 bl 0xffd83f80 + 16a28: 08003b40 stmeqda r0, {r6, r8, r9, fp, ip, sp} + 16a2c: e3b00080 movs r0, #128 ; 0x80 + 16a30: e58d041c str r0, [sp, #1052] + 16a34: ebf5b551 bl 0xffd83f80 + 16a38: 08003b42 stmeqda r0, {r1, r6, r8, r9, fp, ip, sp} + 16a3c: e59de41c ldr lr, [sp, #1052] + 16a40: e1b0038e movs r0, lr, lsl #7 + 16a44: e58d041c str r0, [sp, #1052] + 16a48: ebf5b54c bl 0xffd83f80 + 16a4c: 08003b44 stmeqda r0, {r2, r6, r8, r9, fp, ip, sp} + 16a50: e59d141c ldr r1, [sp, #1052] + 16a54: e59d141c ldr r1, [sp, #1052] + 16a58: e2913000 adds r3, r1, #0 ; 0x0 + 16a5c: ebf5b547 bl 0xffd83f80 + 16a60: 08003b46 stmeqda r0, {r1, r2, r6, r8, r9, fp, ip, sp} + 16a64: e1a01003 mov r1, r3 + 16a68: e0133004 ands r3, r3, r4 + 16a6c: ebf5b543 bl 0xffd83f80 + 16a70: 08003b48 stmeqda r0, {r3, r6, r8, r9, fp, ip, sp} + 16a74: e3530000 cmp r3, #0 ; 0x0 + 16a78: ebf5b540 bl 0xffd83f80 + 16a7c: 08003b4a stmeqda r0, {r1, r3, r6, r8, r9, fp, ip, sp} + 16a80: e28cc012 add ip, ip, #18 ; 0x12 + 16a84: 0a000004 beq 0x16a9c + 16a88: e1a00fac mov r0, ip, lsr #31 + 16a8c: e08ff100 add pc, pc, r0, lsl #2 + 16a90: 08003b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, ip, sp} + 16a94: ebf5b12e bl 0xffd82f54 + 16a98: ea00025a b 0x17408 + 16a9c: ebf5b537 bl 0xffd83f80 + 16aa0: 08003b4c stmeqda r0, {r2, r3, r6, r8, r9, fp, ip, sp} + 16aa4: e59d1420 ldr r1, [sp, #1056] + 16aa8: e1a03001 mov r3, r1 + 16aac: ebf5b533 bl 0xffd83f80 + 16ab0: 08003b4e stmeqda r0, {r1, r2, r3, r6, r8, r9, fp, ip, sp} + 16ab4: ebf5b531 bl 0xffd83f80 + 16ab8: 08003b50 stmeqda r0, {r4, r6, r8, r9, fp, ip, sp} + 16abc: e3a00053 mov r0, #83 ; 0x53 + 16ac0: e3800c3b orr r0, r0, #15104 ; 0x3b00 + 16ac4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16ac8: e58d0438 str r0, [sp, #1080] + 16acc: e28cc009 add ip, ip, #9 ; 0x9 + 16ad0: e1a00fac mov r0, ip, lsr #31 + 16ad4: e08ff100 add pc, pc, r0, lsl #2 + 16ad8: 08003ddc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp} + 16adc: ebf5b11c bl 0xffd82f54 + 16ae0: ea001229 b 0x1b38c + 16ae4: 08003b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, ip, sp} + 16ae8: 00000000 andeq r0, r0, r0 + 16aec: ebf5b523 bl 0xffd83f80 + 16af0: 08003b62 stmeqda r0, {r1, r5, r6, r8, r9, fp, ip, sp} + 16af4: e59d1420 ldr r1, [sp, #1056] + 16af8: e1a03001 mov r3, r1 + 16afc: ebf5b51f bl 0xffd83f80 + 16b00: 08003b64 stmeqda r0, {r2, r5, r6, r8, r9, fp, ip, sp} + 16b04: e2830018 add r0, r3, #24 ; 0x18 + 16b08: ebf5b382 bl 0xffd83918 + 16b0c: 08003b68 stmeqda r0, {r3, r5, r6, r8, r9, fp, ip, sp} + 16b10: e1a04000 mov r4, r0 + 16b14: ebf5b519 bl 0xffd83f80 + 16b18: 08003b66 stmeqda r0, {r1, r2, r5, r6, r8, r9, fp, ip, sp} + 16b1c: e3b05080 movs r5, #128 ; 0x80 + 16b20: ebf5b516 bl 0xffd83f80 + 16b24: 08003b68 stmeqda r0, {r3, r5, r6, r8, r9, fp, ip, sp} + 16b28: e1b05405 movs r5, r5, lsl #8 + 16b2c: ebf5b513 bl 0xffd83f80 + 16b30: 08003b6a stmeqda r0, {r1, r3, r5, r6, r8, r9, fp, ip, sp} + 16b34: e1a01004 mov r1, r4 + 16b38: e0944005 adds r4, r4, r5 + 16b3c: ebf5b50f bl 0xffd83f80 + 16b40: 08003b6c stmeqda r0, {r2, r3, r5, r6, r8, r9, fp, ip, sp} + 16b44: e1b04844 movs r4, r4, asr #16 + 16b48: ebf5b50c bl 0xffd83f80 + 16b4c: 08003b6e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, fp, ip, sp} + 16b50: e3b06024 movs r6, #36 ; 0x24 + 16b54: ebf5b509 bl 0xffd83f80 + 16b58: 08003b70 stmeqda r0, {r4, r5, r6, r8, r9, fp, ip, sp} + 16b5c: e0830006 add r0, r3, r6 + 16b60: ebf5b355 bl 0xffd838bc + 16b64: 08003b74 stmeqda r0, {r2, r4, r5, r6, r8, r9, fp, ip, sp} + 16b68: e1a03000 mov r3, r0 + 16b6c: ebf5b503 bl 0xffd83f80 + 16b70: 08003b72 stmeqda r0, {r1, r4, r5, r6, r8, r9, fp, ip, sp} + 16b74: e1a01004 mov r1, r4 + 16b78: e0547003 subs r7, r4, r3 + 16b7c: ebf5b4ff bl 0xffd83f80 + 16b80: 08003b74 stmeqda r0, {r2, r4, r5, r6, r8, r9, fp, ip, sp} + 16b84: e59d1420 ldr r1, [sp, #1056] + 16b88: e1a00001 mov r0, r1 + 16b8c: e58d041c str r0, [sp, #1052] + 16b90: ebf5b4fa bl 0xffd83f80 + 16b94: 08003b76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, fp, ip, sp} + 16b98: e59d041c ldr r0, [sp, #1052] + 16b9c: e280001c add r0, r0, #28 ; 0x1c + 16ba0: ebf5b35c bl 0xffd83918 + 16ba4: 08003b7a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, fp, ip, sp} + 16ba8: e1a03000 mov r3, r0 + 16bac: ebf5b4f3 bl 0xffd83f80 + 16bb0: 08003b78 stmeqda r0, {r3, r4, r5, r6, r8, r9, fp, ip, sp} + 16bb4: e1a01003 mov r1, r3 + 16bb8: e0933005 adds r3, r3, r5 + 16bbc: ebf5b4ef bl 0xffd83f80 + 16bc0: 08003b7a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, fp, ip, sp} + 16bc4: e1b03843 movs r3, r3, asr #16 + 16bc8: ebf5b4ec bl 0xffd83f80 + 16bcc: 08003b7c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, fp, ip, sp} + 16bd0: e3b05026 movs r5, #38 ; 0x26 + 16bd4: ebf5b4e9 bl 0xffd83f80 + 16bd8: 08003b7e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, fp, ip, sp} + 16bdc: e59d041c ldr r0, [sp, #1052] + 16be0: e0800005 add r0, r0, r5 + 16be4: ebf5b334 bl 0xffd838bc + 16be8: 08003b82 stmeqda r0, {r1, r7, r8, r9, fp, ip, sp} + 16bec: e1a04000 mov r4, r0 + 16bf0: ebf5b4e2 bl 0xffd83f80 + 16bf4: 08003b80 stmeqda r0, {r7, r8, r9, fp, ip, sp} + 16bf8: e1a01003 mov r1, r3 + 16bfc: e0535004 subs r5, r3, r4 + 16c00: ebf5b4de bl 0xffd83f80 + 16c04: 08003b82 stmeqda r0, {r1, r7, r8, r9, fp, ip, sp} + 16c08: e59d041c ldr r0, [sp, #1052] + 16c0c: e2800000 add r0, r0, #0 ; 0x0 + 16c10: ebf5b314 bl 0xffd83868 + 16c14: 08003b86 stmeqda r0, {r1, r2, r7, r8, r9, fp, ip, sp} + 16c18: e1a03000 mov r3, r0 + 16c1c: ebf5b4d7 bl 0xffd83f80 + 16c20: 08003b84 stmeqda r0, {r2, r7, r8, r9, fp, ip, sp} + 16c24: e3b06080 movs r6, #128 ; 0x80 + 16c28: ebf5b4d4 bl 0xffd83f80 + 16c2c: 08003b86 stmeqda r0, {r1, r2, r7, r8, r9, fp, ip, sp} + 16c30: e1b06306 movs r6, r6, lsl #6 + 16c34: ebf5b4d1 bl 0xffd83f80 + 16c38: 08003b88 stmeqda r0, {r3, r7, r8, r9, fp, ip, sp} + 16c3c: e1a01006 mov r1, r6 + 16c40: e2964000 adds r4, r6, #0 ; 0x0 + 16c44: ebf5b4cd bl 0xffd83f80 + 16c48: 08003b8a stmeqda r0, {r1, r3, r7, r8, r9, fp, ip, sp} + 16c4c: e1a01003 mov r1, r3 + 16c50: e0133004 ands r3, r3, r4 + 16c54: ebf5b4c9 bl 0xffd83f80 + 16c58: 08003b8c stmeqda r0, {r2, r3, r7, r8, r9, fp, ip, sp} + 16c5c: e3530000 cmp r3, #0 ; 0x0 + 16c60: ebf5b4c6 bl 0xffd83f80 + 16c64: 08003b8e stmeqda r0, {r1, r2, r3, r7, r8, r9, fp, ip, sp} + 16c68: e28cc04f add ip, ip, #79 ; 0x4f + 16c6c: 1a000004 bne 0x16c84 + 16c70: e1a00fac mov r0, ip, lsr #31 + 16c74: e08ff100 add pc, pc, r0, lsl #2 + 16c78: 08003ba0 stmeqda r0, {r5, r7, r8, r9, fp, ip, sp} + 16c7c: ebf5b0b4 bl 0xffd82f54 + 16c80: ea000026 b 0x16d20 + 16c84: ebf5b4bd bl 0xffd83f80 + 16c88: 08003b90 stmeqda r0, {r4, r7, r8, r9, fp, ip, sp} + 16c8c: e3b04080 movs r4, #128 ; 0x80 + 16c90: ebf5b4ba bl 0xffd83f80 + 16c94: 08003b92 stmeqda r0, {r1, r4, r7, r8, r9, fp, ip, sp} + 16c98: e1b04084 movs r4, r4, lsl #1 + 16c9c: ebf5b4b7 bl 0xffd83f80 + 16ca0: 08003b94 stmeqda r0, {r2, r4, r7, r8, r9, fp, ip, sp} + 16ca4: e59d0434 ldr r0, [sp, #1076] + 16ca8: e2800f00 add r0, r0, #0 ; 0x0 + 16cac: ebf5b319 bl 0xffd83918 + 16cb0: 08003b98 stmeqda r0, {r3, r4, r7, r8, r9, fp, ip, sp} + 16cb4: e58d041c str r0, [sp, #1052] + 16cb8: ebf5b4b0 bl 0xffd83f80 + 16cbc: 08003b96 stmeqda r0, {r1, r2, r4, r7, r8, r9, fp, ip, sp} + 16cc0: e59de41c ldr lr, [sp, #1052] + 16cc4: e1b04e14 movs r4, r4, lsl lr + 16cc8: ebf5b4ac bl 0xffd83f80 + 16ccc: 08003b98 stmeqda r0, {r3, r4, r7, r8, r9, fp, ip, sp} + 16cd0: e59d1428 ldr r1, [sp, #1064] + 16cd4: e1a06001 mov r6, r1 + 16cd8: ebf5b4a8 bl 0xffd83f80 + 16cdc: 08003b9a stmeqda r0, {r1, r3, r4, r7, r8, r9, fp, ip, sp} + 16ce0: e2860000 add r0, r6, #0 ; 0x0 + 16ce4: ebf5b2df bl 0xffd83868 + 16ce8: 08003b9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, fp, ip, sp} + 16cec: e1a03000 mov r3, r0 + 16cf0: ebf5b4a2 bl 0xffd83f80 + 16cf4: 08003b9c stmeqda r0, {r2, r3, r4, r7, r8, r9, fp, ip, sp} + 16cf8: e1a01003 mov r1, r3 + 16cfc: e1d33004 bics r3, r3, r4 + 16d00: ebf5b49e bl 0xffd83f80 + 16d04: 08003b9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, fp, ip, sp} + 16d08: e28cc01c add ip, ip, #28 ; 0x1c + 16d0c: e1a00fac mov r0, ip, lsr #31 + 16d10: e08ff100 add pc, pc, r0, lsl #2 + 16d14: 08003bae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, fp, ip, sp} + 16d18: ebf5b08d bl 0xffd82f54 + 16d1c: ea00001f b 0x16da0 + 16d20: ebf5b496 bl 0xffd83f80 + 16d24: 08003ba0 stmeqda r0, {r5, r7, r8, r9, fp, ip, sp} + 16d28: e3b03080 movs r3, #128 ; 0x80 + 16d2c: ebf5b493 bl 0xffd83f80 + 16d30: 08003ba2 stmeqda r0, {r1, r5, r7, r8, r9, fp, ip, sp} + 16d34: e1b03083 movs r3, r3, lsl #1 + 16d38: ebf5b490 bl 0xffd83f80 + 16d3c: 08003ba4 stmeqda r0, {r2, r5, r7, r8, r9, fp, ip, sp} + 16d40: e59d0434 ldr r0, [sp, #1076] + 16d44: e2800f00 add r0, r0, #0 ; 0x0 + 16d48: ebf5b2f2 bl 0xffd83918 + 16d4c: 08003ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, ip, sp} + 16d50: e58d041c str r0, [sp, #1052] + 16d54: ebf5b489 bl 0xffd83f80 + 16d58: 08003ba6 stmeqda r0, {r1, r2, r5, r7, r8, r9, fp, ip, sp} + 16d5c: e59de41c ldr lr, [sp, #1052] + 16d60: e1b03e13 movs r3, r3, lsl lr + 16d64: ebf5b485 bl 0xffd83f80 + 16d68: 08003ba8 stmeqda r0, {r3, r5, r7, r8, r9, fp, ip, sp} + 16d6c: e59d1428 ldr r1, [sp, #1064] + 16d70: e1a06001 mov r6, r1 + 16d74: ebf5b481 bl 0xffd83f80 + 16d78: 08003baa stmeqda r0, {r1, r3, r5, r7, r8, r9, fp, ip, sp} + 16d7c: e2860000 add r0, r6, #0 ; 0x0 + 16d80: ebf5b2b8 bl 0xffd83868 + 16d84: 08003bae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, fp, ip, sp} + 16d88: e1a04000 mov r4, r0 + 16d8c: ebf5b47b bl 0xffd83f80 + 16d90: 08003bac stmeqda r0, {r2, r3, r5, r7, r8, r9, fp, ip, sp} + 16d94: e1a01003 mov r1, r3 + 16d98: e1933004 orrs r3, r3, r4 + 16d9c: e28cc019 add ip, ip, #25 ; 0x19 + 16da0: ebf5b476 bl 0xffd83f80 + 16da4: 08003bae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, fp, ip, sp} + 16da8: e2860000 add r0, r6, #0 ; 0x0 + 16dac: e1a01003 mov r1, r3 + 16db0: ebf5b1e5 bl 0xffd8354c + 16db4: 08003bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, ip, sp} + 16db8: ebf5b470 bl 0xffd83f80 + 16dbc: 08003bb0 stmeqda r0, {r4, r5, r7, r8, r9, fp, ip, sp} + 16dc0: e3a00ff1 mov r0, #964 ; 0x3c4 + 16dc4: e3800b0e orr r0, r0, #14336 ; 0x3800 + 16dc8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 16dcc: ebf5b2d1 bl 0xffd83918 + 16dd0: 08003bb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, fp, ip, sp} + 16dd4: e58d0418 str r0, [sp, #1048] + 16dd8: ebf5b468 bl 0xffd83f80 + 16ddc: 08003bb2 stmeqda r0, {r1, r4, r5, r7, r8, r9, fp, ip, sp} + 16de0: e59d0434 ldr r0, [sp, #1076] + 16de4: e2800f00 add r0, r0, #0 ; 0x0 + 16de8: ebf5b2ca bl 0xffd83918 + 16dec: 08003bb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, fp, ip, sp} + 16df0: e58d041c str r0, [sp, #1052] + 16df4: ebf5b461 bl 0xffd83f80 + 16df8: 08003bb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, fp, ip, sp} + 16dfc: e59d141c ldr r1, [sp, #1052] + 16e00: e3510001 cmp r1, #1 ; 0x1 + 16e04: ebf5b45d bl 0xffd83f80 + 16e08: 08003bb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, fp, ip, sp} + 16e0c: e28cc014 add ip, ip, #20 ; 0x14 + 16e10: 1a000004 bne 0x16e28 + 16e14: e1a00fac mov r0, ip, lsr #31 + 16e18: e08ff100 add pc, pc, r0, lsl #2 + 16e1c: 08003be2 stmeqda r0, {r1, r5, r6, r7, r8, r9, fp, ip, sp} + 16e20: ebf5b04b bl 0xffd82f54 + 16e24: ea000023 b 0x16eb8 + 16e28: ebf5b454 bl 0xffd83f80 + 16e2c: 08003bb8 stmeqda r0, {r3, r4, r5, r7, r8, r9, fp, ip, sp} + 16e30: e59d141c ldr r1, [sp, #1052] + 16e34: e3510001 cmp r1, #1 ; 0x1 + 16e38: ebf5b450 bl 0xffd83f80 + 16e3c: 08003bba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, fp, ip, sp} + 16e40: e28cc006 add ip, ip, #6 ; 0x6 + 16e44: da000004 ble 0x16e5c + 16e48: e1a00fac mov r0, ip, lsr #31 + 16e4c: e08ff100 add pc, pc, r0, lsl #2 + 16e50: 08003bc8 stmeqda r0, {r3, r6, r7, r8, r9, fp, ip, sp} + 16e54: ebf5b03e bl 0xffd82f54 + 16e58: ea000042 b 0x16f68 + 16e5c: ebf5b447 bl 0xffd83f80 + 16e60: 08003bbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, fp, ip, sp} + 16e64: e59d141c ldr r1, [sp, #1052] + 16e68: e3510000 cmp r1, #0 ; 0x0 + 16e6c: ebf5b443 bl 0xffd83f80 + 16e70: 08003bbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, fp, ip, sp} + 16e74: e28cc006 add ip, ip, #6 ; 0x6 + 16e78: 1a000004 bne 0x16e90 + 16e7c: e1a00fac mov r0, ip, lsr #31 + 16e80: e08ff100 add pc, pc, r0, lsl #2 + 16e84: 08003bd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, fp, ip, sp} + 16e88: ebf5b031 bl 0xffd82f54 + 16e8c: ea000133 b 0x17360 + 16e90: ebf5b43a bl 0xffd83f80 + 16e94: 08003bc0 stmeqda r0, {r6, r7, r8, r9, fp, ip, sp} + 16e98: e28cc003 add ip, ip, #3 ; 0x3 + 16e9c: e1a00fac mov r0, ip, lsr #31 + 16ea0: e08ff100 add pc, pc, r0, lsl #2 + 16ea4: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 16ea8: ebf5b029 bl 0xffd82f54 + 16eac: eafffe15 b 0x16708 + 16eb0: 08003be2 stmeqda r0, {r1, r5, r6, r7, r8, r9, fp, ip, sp} + 16eb4: 00000000 andeq r0, r0, r0 + 16eb8: ebf5b430 bl 0xffd83f80 + 16ebc: 08003be2 stmeqda r0, {r1, r5, r6, r7, r8, r9, fp, ip, sp} + 16ec0: e59d1420 ldr r1, [sp, #1056] + 16ec4: e1a00001 mov r0, r1 + 16ec8: e58d041c str r0, [sp, #1052] + 16ecc: ebf5b42b bl 0xffd83f80 + 16ed0: 08003be4 stmeqda r0, {r2, r5, r6, r7, r8, r9, fp, ip, sp} + 16ed4: e59d041c ldr r0, [sp, #1052] + 16ed8: e2800002 add r0, r0, #2 ; 0x2 + 16edc: ebf5b261 bl 0xffd83868 + 16ee0: 08003be8 stmeqda r0, {r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16ee4: e1a03000 mov r3, r0 + 16ee8: ebf5b424 bl 0xffd83f80 + 16eec: 08003be6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, fp, ip, sp} + 16ef0: e59d1428 ldr r1, [sp, #1064] + 16ef4: e1a04001 mov r4, r1 + 16ef8: ebf5b420 bl 0xffd83f80 + 16efc: 08003be8 stmeqda r0, {r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f00: e2840018 add r0, r4, #24 ; 0x18 + 16f04: e1a01003 mov r1, r3 + 16f08: ebf5b18f bl 0xffd8354c + 16f0c: 08003bea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f10: ebf5b41a bl 0xffd83f80 + 16f14: 08003bea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f18: e2840022 add r0, r4, #34 ; 0x22 + 16f1c: e1a01007 mov r1, r7 + 16f20: ebf5b189 bl 0xffd8354c + 16f24: 08003bec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f28: ebf5b414 bl 0xffd83f80 + 16f2c: 08003bec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f30: e2840024 add r0, r4, #36 ; 0x24 + 16f34: e1a01005 mov r1, r5 + 16f38: ebf5b183 bl 0xffd8354c + 16f3c: 08003bee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f40: ebf5b40e bl 0xffd83f80 + 16f44: 08003bee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, fp, ip, sp} + 16f48: e28cc01a add ip, ip, #26 ; 0x1a + 16f4c: e1a00fac mov r0, ip, lsr #31 + 16f50: e08ff100 add pc, pc, r0, lsl #2 + 16f54: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 16f58: ebf5affd bl 0xffd82f54 + 16f5c: eafffde9 b 0x16708 + 16f60: 08003bc8 stmeqda r0, {r3, r6, r7, r8, r9, fp, ip, sp} + 16f64: 00000000 andeq r0, r0, r0 + 16f68: ebf5b404 bl 0xffd83f80 + 16f6c: 08003bc8 stmeqda r0, {r3, r6, r7, r8, r9, fp, ip, sp} + 16f70: e59d0434 ldr r0, [sp, #1076] + 16f74: e2800f00 add r0, r0, #0 ; 0x0 + 16f78: ebf5b266 bl 0xffd83918 + 16f7c: 08003bcc stmeqda r0, {r2, r3, r6, r7, r8, r9, fp, ip, sp} + 16f80: e1a03000 mov r3, r0 + 16f84: ebf5b3fd bl 0xffd83f80 + 16f88: 08003bca stmeqda r0, {r1, r3, r6, r7, r8, r9, fp, ip, sp} + 16f8c: e3530002 cmp r3, #2 ; 0x2 + 16f90: ebf5b3fa bl 0xffd83f80 + 16f94: 08003bcc stmeqda r0, {r2, r3, r6, r7, r8, r9, fp, ip, sp} + 16f98: e28cc00b add ip, ip, #11 ; 0xb + 16f9c: 1a000004 bne 0x16fb4 + 16fa0: e1a00fac mov r0, ip, lsr #31 + 16fa4: e08ff100 add pc, pc, r0, lsl #2 + 16fa8: 08003bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp, ip, sp} + 16fac: ebf5afe8 bl 0xffd82f54 + 16fb0: ea000015 b 0x1700c + 16fb4: ebf5b3f1 bl 0xffd83f80 + 16fb8: 08003bce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, fp, ip, sp} + 16fbc: e3530003 cmp r3, #3 ; 0x3 + 16fc0: ebf5b3ee bl 0xffd83f80 + 16fc4: 08003bd0 stmeqda r0, {r4, r6, r7, r8, r9, fp, ip, sp} + 16fc8: e28cc006 add ip, ip, #6 ; 0x6 + 16fcc: 1a000004 bne 0x16fe4 + 16fd0: e1a00fac mov r0, ip, lsr #31 + 16fd4: e08ff100 add pc, pc, r0, lsl #2 + 16fd8: 08003cc4 stmeqda r0, {r2, r6, r7, sl, fp, ip, sp} + 16fdc: ebf5afdc bl 0xffd82f54 + 16fe0: ea000078 b 0x171c8 + 16fe4: ebf5b3e5 bl 0xffd83f80 + 16fe8: 08003bd2 stmeqda r0, {r1, r4, r6, r7, r8, r9, fp, ip, sp} + 16fec: e28cc003 add ip, ip, #3 ; 0x3 + 16ff0: e1a00fac mov r0, ip, lsr #31 + 16ff4: e08ff100 add pc, pc, r0, lsl #2 + 16ff8: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 16ffc: ebf5afd4 bl 0xffd82f54 + 17000: eafffdc0 b 0x16708 + 17004: 08003bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17008: 00000000 andeq r0, r0, r0 + 1700c: ebf5b3db bl 0xffd83f80 + 17010: 08003bf0 stmeqda r0, {r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17014: e59d1420 ldr r1, [sp, #1056] + 17018: e1a06001 mov r6, r1 + 1701c: ebf5b3d7 bl 0xffd83f80 + 17020: 08003bf2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17024: e2860002 add r0, r6, #2 ; 0x2 + 17028: ebf5b20e bl 0xffd83868 + 1702c: 08003bf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17030: e1a03000 mov r3, r0 + 17034: ebf5b3d1 bl 0xffd83f80 + 17038: 08003bf4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 1703c: e59d0418 ldr r0, [sp, #1048] + 17040: e280001a add r0, r0, #26 ; 0x1a + 17044: e1a01003 mov r1, r3 + 17048: ebf5b13f bl 0xffd8354c + 1704c: 08003bf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17050: ebf5b3ca bl 0xffd83f80 + 17054: 08003bf6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17058: e59d0418 ldr r0, [sp, #1048] + 1705c: e2800026 add r0, r0, #38 ; 0x26 + 17060: e1a01007 mov r1, r7 + 17064: ebf5b138 bl 0xffd8354c + 17068: 08003bf8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 1706c: ebf5b3c3 bl 0xffd83f80 + 17070: 08003bf8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17074: e59d0418 ldr r0, [sp, #1048] + 17078: e2800028 add r0, r0, #40 ; 0x28 + 1707c: e1a01005 mov r1, r5 + 17080: ebf5b131 bl 0xffd8354c + 17084: 08003bfa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17088: ebf5b3bc bl 0xffd83f80 + 1708c: 08003bfa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 17090: e2860000 add r0, r6, #0 ; 0x0 + 17094: ebf5b1f3 bl 0xffd83868 + 17098: 08003bfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 1709c: e1a04000 mov r4, r0 + 170a0: ebf5b3b6 bl 0xffd83f80 + 170a4: 08003bfc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 170a8: e3b07090 movs r7, #144 ; 0x90 + 170ac: ebf5b3b3 bl 0xffd83f80 + 170b0: 08003bfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, fp, ip, sp} + 170b4: e1b07207 movs r7, r7, lsl #4 + 170b8: ebf5b3b0 bl 0xffd83f80 + 170bc: 08003c00 stmeqda r0, {sl, fp, ip, sp} + 170c0: e1a01007 mov r1, r7 + 170c4: e2973000 adds r3, r7, #0 ; 0x0 + 170c8: ebf5b3ac bl 0xffd83f80 + 170cc: 08003c02 stmeqda r0, {r1, sl, fp, ip, sp} + 170d0: e1a01003 mov r1, r3 + 170d4: e0133004 ands r3, r3, r4 + 170d8: ebf5b3a8 bl 0xffd83f80 + 170dc: 08003c04 stmeqda r0, {r2, sl, fp, ip, sp} + 170e0: e3b00080 movs r0, #128 ; 0x80 + 170e4: e58d041c str r0, [sp, #1052] + 170e8: ebf5b3a4 bl 0xffd83f80 + 170ec: 08003c06 stmeqda r0, {r1, r2, sl, fp, ip, sp} + 170f0: e59de41c ldr lr, [sp, #1052] + 170f4: e1b0008e movs r0, lr, lsl #1 + 170f8: e58d041c str r0, [sp, #1052] + 170fc: ebf5b39f bl 0xffd83f80 + 17100: 08003c08 stmeqda r0, {r3, sl, fp, ip, sp} + 17104: e59de41c ldr lr, [sp, #1052] + 17108: e1b0780e movs r7, lr, lsl #16 + 1710c: ebf5b39b bl 0xffd83f80 + 17110: 08003c0a stmeqda r0, {r1, r3, sl, fp, ip, sp} + 17114: e59d041c ldr r0, [sp, #1052] + 17118: e1530000 cmp r3, r0 + 1711c: ebf5b397 bl 0xffd83f80 + 17120: 08003c0c stmeqda r0, {r2, r3, sl, fp, ip, sp} + 17124: e28cc034 add ip, ip, #52 ; 0x34 + 17128: 1a000004 bne 0x17140 + 1712c: e1a00fac mov r0, ip, lsr #31 + 17130: e08ff100 add pc, pc, r0, lsl #2 + 17134: 08003c10 stmeqda r0, {r4, sl, fp, ip, sp} + 17138: ebf5af85 bl 0xffd82f54 + 1713c: ea000007 b 0x17160 + 17140: ebf5b38e bl 0xffd83f80 + 17144: 08003c0e stmeqda r0, {r1, r2, r3, sl, fp, ip, sp} + 17148: e28cc003 add ip, ip, #3 ; 0x3 + 1714c: e1a00fac mov r0, ip, lsr #31 + 17150: e08ff100 add pc, pc, r0, lsl #2 + 17154: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 17158: ebf5af7d bl 0xffd82f54 + 1715c: eafffd69 b 0x16708 + 17160: ebf5b386 bl 0xffd83f80 + 17164: 08003c10 stmeqda r0, {r4, sl, fp, ip, sp} + 17168: e2860028 add r0, r6, #40 ; 0x28 + 1716c: ebf5b1e9 bl 0xffd83918 + 17170: 08003c14 stmeqda r0, {r2, r4, sl, fp, ip, sp} + 17174: e1a04000 mov r4, r0 + 17178: ebf5b380 bl 0xffd83f80 + 1717c: 08003c12 stmeqda r0, {r1, r4, sl, fp, ip, sp} + 17180: e1a01007 mov r1, r7 + 17184: e2973000 adds r3, r7, #0 ; 0x0 + 17188: ebf5b37c bl 0xffd83f80 + 1718c: 08003c14 stmeqda r0, {r2, r4, sl, fp, ip, sp} + 17190: ebf5b37a bl 0xffd83f80 + 17194: 08003c16 stmeqda r0, {r1, r2, r4, sl, fp, ip, sp} + 17198: e3a00019 mov r0, #25 ; 0x19 + 1719c: e3800b0f orr r0, r0, #15360 ; 0x3c00 + 171a0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 171a4: e58d0438 str r0, [sp, #1080] + 171a8: e28cc00e add ip, ip, #14 ; 0xe + 171ac: e1a00fac mov r0, ip, lsr #31 + 171b0: e08ff100 add pc, pc, r0, lsl #2 + 171b4: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 171b8: ebf5af65 bl 0xffd82f54 + 171bc: eaffac4f b 0x2300 + 171c0: 08003cc4 stmeqda r0, {r2, r6, r7, sl, fp, ip, sp} + 171c4: 00000000 andeq r0, r0, r0 + 171c8: ebf5b36c bl 0xffd83f80 + 171cc: 08003cc4 stmeqda r0, {r2, r6, r7, sl, fp, ip, sp} + 171d0: e59d1420 ldr r1, [sp, #1056] + 171d4: e1a00001 mov r0, r1 + 171d8: e58d041c str r0, [sp, #1052] + 171dc: ebf5b367 bl 0xffd83f80 + 171e0: 08003cc6 stmeqda r0, {r1, r2, r6, r7, sl, fp, ip, sp} + 171e4: e59d041c ldr r0, [sp, #1052] + 171e8: e2800002 add r0, r0, #2 ; 0x2 + 171ec: ebf5b19d bl 0xffd83868 + 171f0: 08003cca stmeqda r0, {r1, r3, r6, r7, sl, fp, ip, sp} + 171f4: e1a03000 mov r3, r0 + 171f8: ebf5b360 bl 0xffd83f80 + 171fc: 08003cc8 stmeqda r0, {r3, r6, r7, sl, fp, ip, sp} + 17200: e59d0418 ldr r0, [sp, #1048] + 17204: e280001c add r0, r0, #28 ; 0x1c + 17208: e1a01003 mov r1, r3 + 1720c: ebf5b0ce bl 0xffd8354c + 17210: 08003cca stmeqda r0, {r1, r3, r6, r7, sl, fp, ip, sp} + 17214: ebf5b359 bl 0xffd83f80 + 17218: 08003cca stmeqda r0, {r1, r3, r6, r7, sl, fp, ip, sp} + 1721c: e59d0418 ldr r0, [sp, #1048] + 17220: e280002a add r0, r0, #42 ; 0x2a + 17224: e1a01007 mov r1, r7 + 17228: ebf5b0c7 bl 0xffd8354c + 1722c: 08003ccc stmeqda r0, {r2, r3, r6, r7, sl, fp, ip, sp} + 17230: ebf5b352 bl 0xffd83f80 + 17234: 08003ccc stmeqda r0, {r2, r3, r6, r7, sl, fp, ip, sp} + 17238: e59d0418 ldr r0, [sp, #1048] + 1723c: e280002c add r0, r0, #44 ; 0x2c + 17240: e1a01005 mov r1, r5 + 17244: ebf5b0c0 bl 0xffd8354c + 17248: 08003cce stmeqda r0, {r1, r2, r3, r6, r7, sl, fp, ip, sp} + 1724c: ebf5b34b bl 0xffd83f80 + 17250: 08003cce stmeqda r0, {r1, r2, r3, r6, r7, sl, fp, ip, sp} + 17254: e59d041c ldr r0, [sp, #1052] + 17258: e2800000 add r0, r0, #0 ; 0x0 + 1725c: ebf5b181 bl 0xffd83868 + 17260: 08003cd2 stmeqda r0, {r1, r4, r6, r7, sl, fp, ip, sp} + 17264: e1a04000 mov r4, r0 + 17268: ebf5b344 bl 0xffd83f80 + 1726c: 08003cd0 stmeqda r0, {r4, r6, r7, sl, fp, ip, sp} + 17270: e3b05090 movs r5, #144 ; 0x90 + 17274: ebf5b341 bl 0xffd83f80 + 17278: 08003cd2 stmeqda r0, {r1, r4, r6, r7, sl, fp, ip, sp} + 1727c: e1b05205 movs r5, r5, lsl #4 + 17280: ebf5b33e bl 0xffd83f80 + 17284: 08003cd4 stmeqda r0, {r2, r4, r6, r7, sl, fp, ip, sp} + 17288: e1a01005 mov r1, r5 + 1728c: e2953000 adds r3, r5, #0 ; 0x0 + 17290: ebf5b33a bl 0xffd83f80 + 17294: 08003cd6 stmeqda r0, {r1, r2, r4, r6, r7, sl, fp, ip, sp} + 17298: e1a01003 mov r1, r3 + 1729c: e0133004 ands r3, r3, r4 + 172a0: ebf5b336 bl 0xffd83f80 + 172a4: 08003cd8 stmeqda r0, {r3, r4, r6, r7, sl, fp, ip, sp} + 172a8: e3b06080 movs r6, #128 ; 0x80 + 172ac: ebf5b333 bl 0xffd83f80 + 172b0: 08003cda stmeqda r0, {r1, r3, r4, r6, r7, sl, fp, ip, sp} + 172b4: e1b06086 movs r6, r6, lsl #1 + 172b8: ebf5b330 bl 0xffd83f80 + 172bc: 08003cdc stmeqda r0, {r2, r3, r4, r6, r7, sl, fp, ip, sp} + 172c0: e1b07806 movs r7, r6, lsl #16 + 172c4: ebf5b32d bl 0xffd83f80 + 172c8: 08003cde stmeqda r0, {r1, r2, r3, r4, r6, r7, sl, fp, ip, sp} + 172cc: e1530006 cmp r3, r6 + 172d0: ebf5b32a bl 0xffd83f80 + 172d4: 08003ce0 stmeqda r0, {r5, r6, r7, sl, fp, ip, sp} + 172d8: e28cc034 add ip, ip, #52 ; 0x34 + 172dc: 0a000004 beq 0x172f4 + 172e0: e1a00fac mov r0, ip, lsr #31 + 172e4: e08ff100 add pc, pc, r0, lsl #2 + 172e8: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 172ec: ebf5af18 bl 0xffd82f54 + 172f0: eafffd04 b 0x16708 + 172f4: ebf5b321 bl 0xffd83f80 + 172f8: 08003ce2 stmeqda r0, {r1, r5, r6, r7, sl, fp, ip, sp} + 172fc: e59d041c ldr r0, [sp, #1052] + 17300: e2800028 add r0, r0, #40 ; 0x28 + 17304: ebf5b183 bl 0xffd83918 + 17308: 08003ce6 stmeqda r0, {r1, r2, r5, r6, r7, sl, fp, ip, sp} + 1730c: e1a04000 mov r4, r0 + 17310: ebf5b31a bl 0xffd83f80 + 17314: 08003ce4 stmeqda r0, {r2, r5, r6, r7, sl, fp, ip, sp} + 17318: e1a01007 mov r1, r7 + 1731c: e2973000 adds r3, r7, #0 ; 0x0 + 17320: ebf5b316 bl 0xffd83f80 + 17324: 08003ce6 stmeqda r0, {r1, r2, r5, r6, r7, sl, fp, ip, sp} + 17328: ebf5b314 bl 0xffd83f80 + 1732c: 08003ce8 stmeqda r0, {r3, r5, r6, r7, sl, fp, ip, sp} + 17330: e3a000eb mov r0, #235 ; 0xeb + 17334: e3800b0f orr r0, r0, #15360 ; 0x3c00 + 17338: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1733c: e58d0438 str r0, [sp, #1080] + 17340: e28cc00e add ip, ip, #14 ; 0xe + 17344: e1a00fac mov r0, ip, lsr #31 + 17348: e08ff100 add pc, pc, r0, lsl #2 + 1734c: 080c364c stmeqda ip, {r2, r3, r6, r9, sl, ip, sp} + 17350: ebf5aeff bl 0xffd82f54 + 17354: eaffabe9 b 0x2300 + 17358: 08003bd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, fp, ip, sp} + 1735c: 00000000 andeq r0, r0, r0 + 17360: ebf5b306 bl 0xffd83f80 + 17364: 08003bd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, fp, ip, sp} + 17368: e59d1420 ldr r1, [sp, #1056] + 1736c: e1a04001 mov r4, r1 + 17370: ebf5b302 bl 0xffd83f80 + 17374: 08003bd6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, fp, ip, sp} + 17378: e2840002 add r0, r4, #2 ; 0x2 + 1737c: ebf5b139 bl 0xffd83868 + 17380: 08003bda stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 17384: e1a03000 mov r3, r0 + 17388: ebf5b2fc bl 0xffd83f80 + 1738c: 08003bd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, fp, ip, sp} + 17390: e59d1428 ldr r1, [sp, #1064] + 17394: e1a06001 mov r6, r1 + 17398: ebf5b2f8 bl 0xffd83f80 + 1739c: 08003bda stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 173a0: e2860016 add r0, r6, #22 ; 0x16 + 173a4: e1a01003 mov r1, r3 + 173a8: ebf5b067 bl 0xffd8354c + 173ac: 08003bdc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 173b0: ebf5b2f2 bl 0xffd83f80 + 173b4: 08003bdc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 173b8: e286001e add r0, r6, #30 ; 0x1e + 173bc: e1a01007 mov r1, r7 + 173c0: ebf5b061 bl 0xffd8354c + 173c4: 08003bde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 173c8: ebf5b2ec bl 0xffd83f80 + 173cc: 08003bde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, fp, ip, sp} + 173d0: e2860020 add r0, r6, #32 ; 0x20 + 173d4: e1a01005 mov r1, r5 + 173d8: ebf5b05b bl 0xffd8354c + 173dc: 08003be0 stmeqda r0, {r5, r6, r7, r8, r9, fp, ip, sp} + 173e0: ebf5b2e6 bl 0xffd83f80 + 173e4: 08003be0 stmeqda r0, {r5, r6, r7, r8, r9, fp, ip, sp} + 173e8: e28cc01a add ip, ip, #26 ; 0x1a + 173ec: e1a00fac mov r0, ip, lsr #31 + 173f0: e08ff100 add pc, pc, r0, lsl #2 + 173f4: 08003da8 stmeqda r0, {r3, r5, r7, r8, sl, fp, ip, sp} + 173f8: ebf5aed5 bl 0xffd82f54 + 173fc: eafffcc1 b 0x16708 + 17400: 08003b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, ip, sp} + 17404: 00000000 andeq r0, r0, r0 + 17408: ebf5b2dc bl 0xffd83f80 + 1740c: 08003b5c stmeqda r0, {r2, r3, r4, r6, r8, r9, fp, ip, sp} + 17410: e59d1420 ldr r1, [sp, #1056] + 17414: e1a03001 mov r3, r1 + 17418: ebf5b2d8 bl 0xffd83f80 + 1741c: 08003b5e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, fp, ip, sp} + 17420: ebf5b2d6 bl 0xffd83f80 + 17424: 08003b60 stmeqda r0, {r5, r6, r8, r9, fp, ip, sp} + 17428: e3a00063 mov r0, #99 ; 0x63 + 1742c: e3800c3b orr r0, r0, #15104 ; 0x3b00 + 17430: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 17434: e58d0438 str r0, [sp, #1080] + 17438: e28cc009 add ip, ip, #9 ; 0x9 + 1743c: e1a00fac mov r0, ip, lsr #31 + 17440: e08ff100 add pc, pc, r0, lsl #2 + 17444: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 17448: ebf5aec1 bl 0xffd82f54 + 1744c: ea000001 b 0x17458 + 17450: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 17454: 00000000 andeq r0, r0, r0 + 17458: ebf5b2c8 bl 0xffd83f80 + 1745c: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 17460: e59d9434 ldr r9, [sp, #1076] + 17464: e3c99003 bic r9, r9, #3 ; 0x3 + 17468: e2499014 sub r9, r9, #20 ; 0x14 + 1746c: e58d9434 str r9, [sp, #1076] + 17470: e2890000 add r0, r9, #0 ; 0x0 + 17474: e1a01007 mov r1, r7 + 17478: ebf5b073 bl 0xffd8364c + 1747c: e2890004 add r0, r9, #4 ; 0x4 + 17480: e1a01008 mov r1, r8 + 17484: ebf5b070 bl 0xffd8364c + 17488: e2890008 add r0, r9, #8 ; 0x8 + 1748c: e59d1418 ldr r1, [sp, #1048] + 17490: ebf5b06d bl 0xffd8364c + 17494: e289000c add r0, r9, #12 ; 0xc + 17498: e59d141c ldr r1, [sp, #1052] + 1749c: ebf5b06a bl 0xffd8364c + 174a0: e2890010 add r0, r9, #16 ; 0x10 + 174a4: e59d1438 ldr r1, [sp, #1080] + 174a8: ebf5b067 bl 0xffd8364c + 174ac: ebf5b2b3 bl 0xffd83f80 + 174b0: 08004316 stmeqda r0, {r1, r2, r4, r8, r9, lr} + 174b4: e59d1428 ldr r1, [sp, #1064] + 174b8: e1a00001 mov r0, r1 + 174bc: e58d041c str r0, [sp, #1052] + 174c0: ebf5b2ae bl 0xffd83f80 + 174c4: 08004318 stmeqda r0, {r3, r4, r8, r9, lr} + 174c8: e59d1424 ldr r1, [sp, #1060] + 174cc: e1a00001 mov r0, r1 + 174d0: e58d0418 str r0, [sp, #1048] + 174d4: ebf5b2a9 bl 0xffd83f80 + 174d8: 0800431a stmeqda r0, {r1, r3, r4, r8, r9, lr} + 174dc: e59d1420 ldr r1, [sp, #1056] + 174e0: e1a08001 mov r8, r1 + 174e4: ebf5b2a5 bl 0xffd83f80 + 174e8: 0800431c stmeqda r0, {r2, r3, r4, r8, r9, lr} + 174ec: e59d9434 ldr r9, [sp, #1076] + 174f0: e3c99003 bic r9, r9, #3 ; 0x3 + 174f4: e249900c sub r9, r9, #12 ; 0xc + 174f8: e58d9434 str r9, [sp, #1076] + 174fc: e2890000 add r0, r9, #0 ; 0x0 + 17500: e1a01008 mov r1, r8 + 17504: ebf5b050 bl 0xffd8364c + 17508: e2890004 add r0, r9, #4 ; 0x4 + 1750c: e59d1418 ldr r1, [sp, #1048] + 17510: ebf5b04d bl 0xffd8364c + 17514: e2890008 add r0, r9, #8 ; 0x8 + 17518: e59d141c ldr r1, [sp, #1052] + 1751c: ebf5b02a bl 0xffd835cc + 17520: 0800431e stmeqda r0, {r1, r2, r3, r4, r8, r9, lr} + 17524: ebf5b295 bl 0xffd83f80 + 17528: 0800431e stmeqda r0, {r1, r2, r3, r4, r8, r9, lr} + 1752c: e59d0434 ldr r0, [sp, #1076] + 17530: e2400f09 sub r0, r0, #36 ; 0x24 + 17534: e58d0434 str r0, [sp, #1076] + 17538: ebf5b290 bl 0xffd83f80 + 1753c: 08004320 stmeqda r0, {r5, r8, r9, lr} + 17540: e1a01003 mov r1, r3 + 17544: e2937000 adds r7, r3, #0 ; 0x0 + 17548: ebf5b28c bl 0xffd83f80 + 1754c: 08004322 stmeqda r0, {r1, r5, r8, r9, lr} + 17550: e2870018 add r0, r7, #24 ; 0x18 + 17554: ebf5b0ef bl 0xffd83918 + 17558: 08004326 stmeqda r0, {r1, r2, r5, r8, r9, lr} + 1755c: e1a03000 mov r3, r0 + 17560: ebf5b286 bl 0xffd83f80 + 17564: 08004324 stmeqda r0, {r2, r5, r8, r9, lr} + 17568: e3b04080 movs r4, #128 ; 0x80 + 1756c: ebf5b283 bl 0xffd83f80 + 17570: 08004326 stmeqda r0, {r1, r2, r5, r8, r9, lr} + 17574: e1b04404 movs r4, r4, lsl #8 + 17578: ebf5b280 bl 0xffd83f80 + 1757c: 08004328 stmeqda r0, {r3, r5, r8, r9, lr} + 17580: e1a01003 mov r1, r3 + 17584: e0930004 adds r0, r3, r4 + 17588: e58d0418 str r0, [sp, #1048] + 1758c: ebf5b27b bl 0xffd83f80 + 17590: 0800432a stmeqda r0, {r1, r3, r5, r8, r9, lr} + 17594: e59de418 ldr lr, [sp, #1048] + 17598: e1b0384e movs r3, lr, asr #16 + 1759c: ebf5b277 bl 0xffd83f80 + 175a0: 0800432c stmeqda r0, {r2, r3, r5, r8, r9, lr} + 175a4: e59d0434 ldr r0, [sp, #1076] + 175a8: e2800f01 add r0, r0, #4 ; 0x4 + 175ac: e1a01003 mov r1, r3 + 175b0: ebf5b005 bl 0xffd835cc + 175b4: 0800432e stmeqda r0, {r1, r2, r3, r5, r8, r9, lr} + 175b8: ebf5b270 bl 0xffd83f80 + 175bc: 0800432e stmeqda r0, {r1, r2, r3, r5, r8, r9, lr} + 175c0: e287001c add r0, r7, #28 ; 0x1c + 175c4: ebf5b0d3 bl 0xffd83918 + 175c8: 08004332 stmeqda r0, {r1, r4, r5, r8, r9, lr} + 175cc: e1a03000 mov r3, r0 + 175d0: ebf5b26a bl 0xffd83f80 + 175d4: 08004330 stmeqda r0, {r4, r5, r8, r9, lr} + 175d8: e1a01003 mov r1, r3 + 175dc: e0938004 adds r8, r3, r4 + 175e0: ebf5b266 bl 0xffd83f80 + 175e4: 08004332 stmeqda r0, {r1, r4, r5, r8, r9, lr} + 175e8: e1b04848 movs r4, r8, asr #16 + 175ec: ebf5b263 bl 0xffd83f80 + 175f0: 08004334 stmeqda r0, {r2, r4, r5, r8, r9, lr} + 175f4: e59d0434 ldr r0, [sp, #1076] + 175f8: e2800f02 add r0, r0, #8 ; 0x8 + 175fc: e1a01004 mov r1, r4 + 17600: ebf5aff1 bl 0xffd835cc + 17604: 08004336 stmeqda r0, {r1, r2, r4, r5, r8, r9, lr} + 17608: ebf5b25c bl 0xffd83f80 + 1760c: 08004336 stmeqda r0, {r1, r2, r4, r5, r8, r9, lr} + 17610: e3b0003c movs r0, #60 ; 0x3c + 17614: e58d041c str r0, [sp, #1052] + 17618: ebf5b258 bl 0xffd83f80 + 1761c: 08004338 stmeqda r0, {r3, r4, r5, r8, r9, lr} + 17620: e59d141c ldr r1, [sp, #1052] + 17624: e0870001 add r0, r7, r1 + 17628: ebf5b0a3 bl 0xffd838bc + 1762c: 0800433c stmeqda r0, {r2, r3, r4, r5, r8, r9, lr} + 17630: e1a05000 mov r5, r0 + 17634: ebf5b251 bl 0xffd83f80 + 17638: 0800433a stmeqda r0, {r1, r3, r4, r5, r8, r9, lr} + 1763c: e1a00005 mov r0, r5 + 17640: e58d0430 str r0, [sp, #1072] + 17644: ebf5b24d bl 0xffd83f80 + 17648: 0800433c stmeqda r0, {r2, r3, r4, r5, r8, r9, lr} + 1764c: e59d0434 ldr r0, [sp, #1076] + 17650: e2800f01 add r0, r0, #4 ; 0x4 + 17654: ebf5b0af bl 0xffd83918 + 17658: 08004340 stmeqda r0, {r6, r8, r9, lr} + 1765c: e1a03000 mov r3, r0 + 17660: ebf5b246 bl 0xffd83f80 + 17664: 0800433e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, lr} + 17668: e59d1430 ldr r1, [sp, #1072] + 1766c: e1530001 cmp r3, r1 + 17670: ebf5b242 bl 0xffd83f80 + 17674: 08004340 stmeqda r0, {r6, r8, r9, lr} + 17678: e28cc056 add ip, ip, #86 ; 0x56 + 1767c: 0a000004 beq 0x17694 + 17680: e1a00fac mov r0, ip, lsr #31 + 17684: e08ff100 add pc, pc, r0, lsl #2 + 17688: 0800434e stmeqda r0, {r1, r2, r3, r6, r8, r9, lr} + 1768c: ebf5ae30 bl 0xffd82f54 + 17690: ea000023 b 0x17724 + 17694: ebf5b239 bl 0xffd83f80 + 17698: 08004342 stmeqda r0, {r1, r6, r8, r9, lr} + 1769c: e3b0403e movs r4, #62 ; 0x3e + 176a0: ebf5b236 bl 0xffd83f80 + 176a4: 08004344 stmeqda r0, {r2, r6, r8, r9, lr} + 176a8: e0870004 add r0, r7, r4 + 176ac: ebf5b082 bl 0xffd838bc + 176b0: 08004348 stmeqda r0, {r3, r6, r8, r9, lr} + 176b4: e1a03000 mov r3, r0 + 176b8: ebf5b230 bl 0xffd83f80 + 176bc: 08004346 stmeqda r0, {r1, r2, r6, r8, r9, lr} + 176c0: e59d0434 ldr r0, [sp, #1076] + 176c4: e2800f02 add r0, r0, #8 ; 0x8 + 176c8: ebf5b092 bl 0xffd83918 + 176cc: 0800434a stmeqda r0, {r1, r3, r6, r8, r9, lr} + 176d0: e1a05000 mov r5, r0 + 176d4: ebf5b229 bl 0xffd83f80 + 176d8: 08004348 stmeqda r0, {r3, r6, r8, r9, lr} + 176dc: e1550003 cmp r5, r3 + 176e0: ebf5b226 bl 0xffd83f80 + 176e4: 0800434a stmeqda r0, {r1, r3, r6, r8, r9, lr} + 176e8: e28cc013 add ip, ip, #19 ; 0x13 + 176ec: 0a000004 beq 0x17704 + 176f0: e1a00fac mov r0, ip, lsr #31 + 176f4: e08ff100 add pc, pc, r0, lsl #2 + 176f8: 0800434e stmeqda r0, {r1, r2, r3, r6, r8, r9, lr} + 176fc: ebf5ae14 bl 0xffd82f54 + 17700: ea000007 b 0x17724 + 17704: ebf5b21d bl 0xffd83f80 + 17708: 0800434c stmeqda r0, {r2, r3, r6, r8, r9, lr} + 1770c: e28cc003 add ip, ip, #3 ; 0x3 + 17710: e1a00fac mov r0, ip, lsr #31 + 17714: e08ff100 add pc, pc, r0, lsl #2 + 17718: 08004472 stmeqda r0, {r1, r4, r5, r6, sl, lr} + 1771c: ebf5ae0c bl 0xffd82f54 + 17720: ea00030b b 0x18354 + 17724: ebf5b215 bl 0xffd83f80 + 17728: 0800434e stmeqda r0, {r1, r2, r3, r6, r8, r9, lr} + 1772c: e3b00020 movs r0, #32 ; 0x20 + 17730: e58d041c str r0, [sp, #1052] + 17734: ebf5b211 bl 0xffd83f80 + 17738: 08004350 stmeqda r0, {r4, r6, r8, r9, lr} + 1773c: e59d141c ldr r1, [sp, #1052] + 17740: e0870001 add r0, r7, r1 + 17744: ebf5b05c bl 0xffd838bc + 17748: 08004354 stmeqda r0, {r2, r4, r6, r8, r9, lr} + 1774c: e1a05000 mov r5, r0 + 17750: ebf5b20a bl 0xffd83f80 + 17754: 08004352 stmeqda r0, {r1, r4, r6, r8, r9, lr} + 17758: e59d0434 ldr r0, [sp, #1076] + 1775c: e2800f01 add r0, r0, #4 ; 0x4 + 17760: ebf5b06c bl 0xffd83918 + 17764: 08004356 stmeqda r0, {r1, r2, r4, r6, r8, r9, lr} + 17768: e1a03000 mov r3, r0 + 1776c: ebf5b203 bl 0xffd83f80 + 17770: 08004354 stmeqda r0, {r2, r4, r6, r8, r9, lr} + 17774: e1a01003 mov r1, r3 + 17778: e0934005 adds r4, r3, r5 + 1777c: ebf5b1ff bl 0xffd83f80 + 17780: 08004356 stmeqda r0, {r1, r2, r4, r6, r8, r9, lr} + 17784: e1a01004 mov r1, r4 + 17788: e2544001 subs r4, r4, #1 ; 0x1 + 1778c: ebf5b1fb bl 0xffd83f80 + 17790: 08004358 stmeqda r0, {r3, r4, r6, r8, r9, lr} + 17794: e3b00022 movs r0, #34 ; 0x22 + 17798: e58d041c str r0, [sp, #1052] + 1779c: ebf5b1f7 bl 0xffd83f80 + 177a0: 0800435a stmeqda r0, {r1, r3, r4, r6, r8, r9, lr} + 177a4: e59d141c ldr r1, [sp, #1052] + 177a8: e0870001 add r0, r7, r1 + 177ac: ebf5b042 bl 0xffd838bc + 177b0: 0800435e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, lr} + 177b4: e1a06000 mov r6, r0 + 177b8: ebf5b1f0 bl 0xffd83f80 + 177bc: 0800435c stmeqda r0, {r2, r3, r4, r6, r8, r9, lr} + 177c0: e59d0434 ldr r0, [sp, #1076] + 177c4: e2800f02 add r0, r0, #8 ; 0x8 + 177c8: ebf5b052 bl 0xffd83918 + 177cc: 08004360 stmeqda r0, {r5, r6, r8, r9, lr} + 177d0: e58d041c str r0, [sp, #1052] + 177d4: ebf5b1e9 bl 0xffd83f80 + 177d8: 0800435e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, lr} + 177dc: e59d141c ldr r1, [sp, #1052] + 177e0: e59d141c ldr r1, [sp, #1052] + 177e4: e0913006 adds r3, r1, r6 + 177e8: ebf5b1e4 bl 0xffd83f80 + 177ec: 08004360 stmeqda r0, {r5, r6, r8, r9, lr} + 177f0: e1a01003 mov r1, r3 + 177f4: e2533001 subs r3, r3, #1 ; 0x1 + 177f8: ebf5b1e0 bl 0xffd83f80 + 177fc: 08004362 stmeqda r0, {r1, r5, r6, r8, r9, lr} + 17800: e59de418 ldr lr, [sp, #1048] + 17804: e1b009ce movs r0, lr, asr #19 + 17808: e58d0418 str r0, [sp, #1048] + 1780c: ebf5b1db bl 0xffd83f80 + 17810: 08004364 stmeqda r0, {r2, r5, r6, r8, r9, lr} + 17814: e59d1418 ldr r1, [sp, #1048] + 17818: e1a00001 mov r0, r1 + 1781c: e58d0420 str r0, [sp, #1056] + 17820: ebf5b1d6 bl 0xffd83f80 + 17824: 08004366 stmeqda r0, {r1, r2, r5, r6, r8, r9, lr} + 17828: e1b089c8 movs r8, r8, asr #19 + 1782c: ebf5b1d3 bl 0xffd83f80 + 17830: 08004368 stmeqda r0, {r3, r5, r6, r8, r9, lr} + 17834: e59d0434 ldr r0, [sp, #1076] + 17838: e2800f03 add r0, r0, #12 ; 0xc + 1783c: e1a01008 mov r1, r8 + 17840: ebf5af61 bl 0xffd835cc + 17844: 0800436a stmeqda r0, {r1, r3, r5, r6, r8, r9, lr} + 17848: ebf5b1cc bl 0xffd83f80 + 1784c: 0800436a stmeqda r0, {r1, r3, r5, r6, r8, r9, lr} + 17850: e1b041c4 movs r4, r4, asr #3 + 17854: ebf5b1c9 bl 0xffd83f80 + 17858: 0800436c stmeqda r0, {r2, r3, r5, r6, r8, r9, lr} + 1785c: e1a00004 mov r0, r4 + 17860: e58d0424 str r0, [sp, #1060] + 17864: ebf5b1c5 bl 0xffd83f80 + 17868: 0800436e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, lr} + 1786c: e1b031c3 movs r3, r3, asr #3 + 17870: ebf5b1c2 bl 0xffd83f80 + 17874: 08004370 stmeqda r0, {r4, r5, r6, r8, r9, lr} + 17878: e59d0434 ldr r0, [sp, #1076] + 1787c: e2800f04 add r0, r0, #16 ; 0x10 + 17880: e1a01003 mov r1, r3 + 17884: ebf5af50 bl 0xffd835cc + 17888: 08004372 stmeqda r0, {r1, r4, r5, r6, r8, r9, lr} + 1788c: ebf5b1bb bl 0xffd83f80 + 17890: 08004372 stmeqda r0, {r1, r4, r5, r6, r8, r9, lr} + 17894: e287003c add r0, r7, #60 ; 0x3c + 17898: ebf5aff2 bl 0xffd83868 + 1789c: 08004376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, lr} + 178a0: e1a03000 mov r3, r0 + 178a4: ebf5b1b5 bl 0xffd83f80 + 178a8: 08004374 stmeqda r0, {r2, r4, r5, r6, r8, r9, lr} + 178ac: e1b03803 movs r3, r3, lsl #16 + 178b0: ebf5b1b2 bl 0xffd83f80 + 178b4: 08004376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, lr} + 178b8: e1b039c3 movs r3, r3, asr #19 + 178bc: ebf5b1af bl 0xffd83f80 + 178c0: 08004378 stmeqda r0, {r3, r4, r5, r6, r8, r9, lr} + 178c4: e1a00003 mov r0, r3 + 178c8: e58d0428 str r0, [sp, #1064] + 178cc: ebf5b1ab bl 0xffd83f80 + 178d0: 0800437a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, lr} + 178d4: e287003e add r0, r7, #62 ; 0x3e + 178d8: ebf5afe2 bl 0xffd83868 + 178dc: 0800437e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, lr} + 178e0: e1a03000 mov r3, r0 + 178e4: ebf5b1a5 bl 0xffd83f80 + 178e8: 0800437c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, lr} + 178ec: e1b03803 movs r3, r3, lsl #16 + 178f0: ebf5b1a2 bl 0xffd83f80 + 178f4: 0800437e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, lr} + 178f8: e1b039c3 movs r3, r3, asr #19 + 178fc: ebf5b19f bl 0xffd83f80 + 17900: 08004380 stmeqda r0, {r7, r8, r9, lr} + 17904: e59d0434 ldr r0, [sp, #1076] + 17908: e2800f05 add r0, r0, #20 ; 0x14 + 1790c: e1a01003 mov r1, r3 + 17910: ebf5af2d bl 0xffd835cc + 17914: 08004382 stmeqda r0, {r1, r7, r8, r9, lr} + 17918: ebf5b198 bl 0xffd83f80 + 1791c: 08004382 stmeqda r0, {r1, r7, r8, r9, lr} + 17920: e59d1430 ldr r1, [sp, #1072] + 17924: e0855001 add r5, r5, r1 + 17928: ebf5b194 bl 0xffd83f80 + 1792c: 08004384 stmeqda r0, {r2, r7, r8, r9, lr} + 17930: e1a01005 mov r1, r5 + 17934: e2555001 subs r5, r5, #1 ; 0x1 + 17938: ebf5b190 bl 0xffd83f80 + 1793c: 08004386 stmeqda r0, {r1, r2, r7, r8, r9, lr} + 17940: e1b051c5 movs r5, r5, asr #3 + 17944: ebf5b18d bl 0xffd83f80 + 17948: 08004388 stmeqda r0, {r3, r7, r8, r9, lr} + 1794c: e1a00005 mov r0, r5 + 17950: e58d0430 str r0, [sp, #1072] + 17954: ebf5b189 bl 0xffd83f80 + 17958: 0800438a stmeqda r0, {r1, r3, r7, r8, r9, lr} + 1795c: e3b0403e movs r4, #62 ; 0x3e + 17960: ebf5b186 bl 0xffd83f80 + 17964: 0800438c stmeqda r0, {r2, r3, r7, r8, r9, lr} + 17968: e0870004 add r0, r7, r4 + 1796c: ebf5afd2 bl 0xffd838bc + 17970: 08004390 stmeqda r0, {r4, r7, r8, r9, lr} + 17974: e1a03000 mov r3, r0 + 17978: ebf5b180 bl 0xffd83f80 + 1797c: 0800438e stmeqda r0, {r1, r2, r3, r7, r8, r9, lr} + 17980: e1a01003 mov r1, r3 + 17984: e0933006 adds r3, r3, r6 + 17988: ebf5b17c bl 0xffd83f80 + 1798c: 08004390 stmeqda r0, {r4, r7, r8, r9, lr} + 17990: e1a01003 mov r1, r3 + 17994: e2533001 subs r3, r3, #1 ; 0x1 + 17998: ebf5b178 bl 0xffd83f80 + 1799c: 08004392 stmeqda r0, {r1, r4, r7, r8, r9, lr} + 179a0: e1b031c3 movs r3, r3, asr #3 + 179a4: ebf5b175 bl 0xffd83f80 + 179a8: 08004394 stmeqda r0, {r2, r4, r7, r8, r9, lr} + 179ac: e59d0434 ldr r0, [sp, #1076] + 179b0: e2800f06 add r0, r0, #24 ; 0x18 + 179b4: e1a01003 mov r1, r3 + 179b8: ebf5af03 bl 0xffd835cc + 179bc: 08004396 stmeqda r0, {r1, r2, r4, r7, r8, r9, lr} + 179c0: ebf5b16e bl 0xffd83f80 + 179c4: 08004396 stmeqda r0, {r1, r2, r4, r7, r8, r9, lr} + 179c8: e2870000 add r0, r7, #0 ; 0x0 + 179cc: ebf5afa5 bl 0xffd83868 + 179d0: 0800439a stmeqda r0, {r1, r3, r4, r7, r8, r9, lr} + 179d4: e1a04000 mov r4, r0 + 179d8: ebf5b168 bl 0xffd83f80 + 179dc: 08004398 stmeqda r0, {r3, r4, r7, r8, r9, lr} + 179e0: e3b03080 movs r3, #128 ; 0x80 + 179e4: ebf5b165 bl 0xffd83f80 + 179e8: 0800439a stmeqda r0, {r1, r3, r4, r7, r8, r9, lr} + 179ec: e1b03083 movs r3, r3, lsl #1 + 179f0: ebf5b162 bl 0xffd83f80 + 179f4: 0800439c stmeqda r0, {r2, r3, r4, r7, r8, r9, lr} + 179f8: e1a01003 mov r1, r3 + 179fc: e0133004 ands r3, r3, r4 + 17a00: ebf5b15e bl 0xffd83f80 + 17a04: 0800439e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, lr} + 17a08: e3530000 cmp r3, #0 ; 0x0 + 17a0c: ebf5b15b bl 0xffd83f80 + 17a10: 080043a0 stmeqda r0, {r5, r7, r8, r9, lr} + 17a14: e28cc092 add ip, ip, #146 ; 0x92 + 17a18: 1a000004 bne 0x17a30 + 17a1c: e1a00fac mov r0, ip, lsr #31 + 17a20: e08ff100 add pc, pc, r0, lsl #2 + 17a24: 080043c2 stmeqda r0, {r1, r6, r7, r8, r9, lr} + 17a28: ebf5ad49 bl 0xffd82f54 + 17a2c: ea000045 b 0x17b48 + 17a30: ebf5b152 bl 0xffd83f80 + 17a34: 080043a2 stmeqda r0, {r1, r5, r7, r8, r9, lr} + 17a38: e3b03002 movs r3, #2 ; 0x2 + 17a3c: ebf5b14f bl 0xffd83f80 + 17a40: 080043a4 stmeqda r0, {r2, r5, r7, r8, r9, lr} + 17a44: e3a01000 mov r1, #0 ; 0x0 + 17a48: e0513003 subs r3, r1, r3 + 17a4c: ebf5b14b bl 0xffd83f80 + 17a50: 080043a6 stmeqda r0, {r1, r2, r5, r7, r8, r9, lr} + 17a54: e59d1420 ldr r1, [sp, #1056] + 17a58: e1a05001 mov r5, r1 + 17a5c: ebf5b147 bl 0xffd83f80 + 17a60: 080043a8 stmeqda r0, {r3, r5, r7, r8, r9, lr} + 17a64: e1a01005 mov r1, r5 + 17a68: e0155003 ands r5, r5, r3 + 17a6c: ebf5b143 bl 0xffd83f80 + 17a70: 080043aa stmeqda r0, {r1, r3, r5, r7, r8, r9, lr} + 17a74: e1a00005 mov r0, r5 + 17a78: e58d0420 str r0, [sp, #1056] + 17a7c: ebf5b13f bl 0xffd83f80 + 17a80: 080043ac stmeqda r0, {r2, r3, r5, r7, r8, r9, lr} + 17a84: e59d1424 ldr r1, [sp, #1060] + 17a88: e1a08001 mov r8, r1 + 17a8c: ebf5b13b bl 0xffd83f80 + 17a90: 080043ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, lr} + 17a94: e1a01008 mov r1, r8 + 17a98: e0188003 ands r8, r8, r3 + 17a9c: ebf5b137 bl 0xffd83f80 + 17aa0: 080043b0 stmeqda r0, {r4, r5, r7, r8, r9, lr} + 17aa4: e1a00008 mov r0, r8 + 17aa8: e58d0424 str r0, [sp, #1060] + 17aac: ebf5b133 bl 0xffd83f80 + 17ab0: 080043b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, lr} + 17ab4: e59d1428 ldr r1, [sp, #1064] + 17ab8: e1a00001 mov r0, r1 + 17abc: e58d041c str r0, [sp, #1052] + 17ac0: ebf5b12e bl 0xffd83f80 + 17ac4: 080043b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, lr} + 17ac8: e59d141c ldr r1, [sp, #1052] + 17acc: e59d141c ldr r1, [sp, #1052] + 17ad0: e0110003 ands r0, r1, r3 + 17ad4: e58d041c str r0, [sp, #1052] + 17ad8: ebf5b128 bl 0xffd83f80 + 17adc: 080043b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, lr} + 17ae0: e59d141c ldr r1, [sp, #1052] + 17ae4: e1a00001 mov r0, r1 + 17ae8: e58d0428 str r0, [sp, #1064] + 17aec: ebf5b123 bl 0xffd83f80 + 17af0: 080043b8 stmeqda r0, {r3, r4, r5, r7, r8, r9, lr} + 17af4: e59d1430 ldr r1, [sp, #1072] + 17af8: e1a04001 mov r4, r1 + 17afc: ebf5b11f bl 0xffd83f80 + 17b00: 080043ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, lr} + 17b04: e1a01004 mov r1, r4 + 17b08: e0144003 ands r4, r4, r3 + 17b0c: ebf5b11b bl 0xffd83f80 + 17b10: 080043bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, lr} + 17b14: e1a00004 mov r0, r4 + 17b18: e58d0430 str r0, [sp, #1072] + 17b1c: ebf5b117 bl 0xffd83f80 + 17b20: 080043be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, lr} + 17b24: e3b03002 movs r3, #2 ; 0x2 + 17b28: ebf5b114 bl 0xffd83f80 + 17b2c: 080043c0 stmeqda r0, {r6, r7, r8, r9, lr} + 17b30: e28cc030 add ip, ip, #48 ; 0x30 + 17b34: e1a00fac mov r0, ip, lsr #31 + 17b38: e08ff100 add pc, pc, r0, lsl #2 + 17b3c: 080043c4 stmeqda r0, {r2, r6, r7, r8, r9, lr} + 17b40: ebf5ad03 bl 0xffd82f54 + 17b44: ea000003 b 0x17b58 + 17b48: ebf5b10c bl 0xffd83f80 + 17b4c: 080043c2 stmeqda r0, {r1, r6, r7, r8, r9, lr} + 17b50: e3b03001 movs r3, #1 ; 0x1 + 17b54: e28cc003 add ip, ip, #3 ; 0x3 + 17b58: ebf5b108 bl 0xffd83f80 + 17b5c: 080043c4 stmeqda r0, {r2, r6, r7, r8, r9, lr} + 17b60: e3b0503c movs r5, #60 ; 0x3c + 17b64: ebf5b105 bl 0xffd83f80 + 17b68: 080043c6 stmeqda r0, {r1, r2, r6, r7, r8, r9, lr} + 17b6c: e0870005 add r0, r7, r5 + 17b70: ebf5af51 bl 0xffd838bc + 17b74: 080043ca stmeqda r0, {r1, r3, r6, r7, r8, r9, lr} + 17b78: e1a04000 mov r4, r0 + 17b7c: ebf5b0ff bl 0xffd83f80 + 17b80: 080043c8 stmeqda r0, {r3, r6, r7, r8, r9, lr} + 17b84: e59d0434 ldr r0, [sp, #1076] + 17b88: e2800f01 add r0, r0, #4 ; 0x4 + 17b8c: ebf5af61 bl 0xffd83918 + 17b90: 080043cc stmeqda r0, {r2, r3, r6, r7, r8, r9, lr} + 17b94: e1a08000 mov r8, r0 + 17b98: ebf5b0f8 bl 0xffd83f80 + 17b9c: 080043ca stmeqda r0, {r1, r3, r6, r7, r8, r9, lr} + 17ba0: e1580004 cmp r8, r4 + 17ba4: ebf5b0f5 bl 0xffd83f80 + 17ba8: 080043cc stmeqda r0, {r2, r3, r6, r7, r8, r9, lr} + 17bac: e28cc013 add ip, ip, #19 ; 0x13 + 17bb0: 1a000004 bne 0x17bc8 + 17bb4: e1a00fac mov r0, ip, lsr #31 + 17bb8: e08ff100 add pc, pc, r0, lsl #2 + 17bbc: 080043e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, lr} + 17bc0: ebf5ace3 bl 0xffd82f54 + 17bc4: ea000044 b 0x17cdc + 17bc8: ebf5b0ec bl 0xffd83f80 + 17bcc: 080043ce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, lr} + 17bd0: e1580004 cmp r8, r4 + 17bd4: ebf5b0e9 bl 0xffd83f80 + 17bd8: 080043d0 stmeqda r0, {r4, r6, r7, r8, r9, lr} + 17bdc: e28cc006 add ip, ip, #6 ; 0x6 + 17be0: ba000004 blt 0x17bf8 + 17be4: e1a00fac mov r0, ip, lsr #31 + 17be8: e08ff100 add pc, pc, r0, lsl #2 + 17bec: 080043da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, lr} + 17bf0: ebf5acd7 bl 0xffd82f54 + 17bf4: ea000015 b 0x17c50 + 17bf8: ebf5b0e0 bl 0xffd83f80 + 17bfc: 080043d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, lr} + 17c00: e59d1420 ldr r1, [sp, #1056] + 17c04: e1a05001 mov r5, r1 + 17c08: ebf5b0dc bl 0xffd83f80 + 17c0c: 080043d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, lr} + 17c10: e59d1428 ldr r1, [sp, #1064] + 17c14: e1a00001 mov r0, r1 + 17c18: e58d041c str r0, [sp, #1052] + 17c1c: ebf5b0d7 bl 0xffd83f80 + 17c20: 080043d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, lr} + 17c24: e59d141c ldr r1, [sp, #1052] + 17c28: e59d141c ldr r1, [sp, #1052] + 17c2c: e0516003 subs r6, r1, r3 + 17c30: ebf5b0d2 bl 0xffd83f80 + 17c34: 080043d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, lr} + 17c38: e28cc00c add ip, ip, #12 ; 0xc + 17c3c: e1a00fac mov r0, ip, lsr #31 + 17c40: e08ff100 add pc, pc, r0, lsl #2 + 17c44: 080043e0 stmeqda r0, {r5, r6, r7, r8, r9, lr} + 17c48: ebf5acc1 bl 0xffd82f54 + 17c4c: ea00000c b 0x17c84 + 17c50: ebf5b0ca bl 0xffd83f80 + 17c54: 080043da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, lr} + 17c58: e59d1430 ldr r1, [sp, #1072] + 17c5c: e1a04001 mov r4, r1 + 17c60: ebf5b0c6 bl 0xffd83f80 + 17c64: 080043dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, lr} + 17c68: e1a01004 mov r1, r4 + 17c6c: e0945003 adds r5, r4, r3 + 17c70: ebf5b0c2 bl 0xffd83f80 + 17c74: 080043de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, lr} + 17c78: e59d1424 ldr r1, [sp, #1060] + 17c7c: e1a06001 mov r6, r1 + 17c80: e28cc009 add ip, ip, #9 ; 0x9 + 17c84: ebf5b0bd bl 0xffd83f80 + 17c88: 080043e0 stmeqda r0, {r5, r6, r7, r8, r9, lr} + 17c8c: e59d0434 ldr r0, [sp, #1076] + 17c90: e2800f03 add r0, r0, #12 ; 0xc + 17c94: ebf5af1f bl 0xffd83918 + 17c98: 080043e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, lr} + 17c9c: e58d041c str r0, [sp, #1052] + 17ca0: ebf5b0b6 bl 0xffd83f80 + 17ca4: 080043e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, lr} + 17ca8: e59d0434 ldr r0, [sp, #1076] + 17cac: e2800f04 add r0, r0, #16 ; 0x10 + 17cb0: ebf5af18 bl 0xffd83918 + 17cb4: 080043e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, lr} + 17cb8: e1a04000 mov r4, r0 + 17cbc: ebf5b0af bl 0xffd83f80 + 17cc0: 080043e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, lr} + 17cc4: e28cc00d add ip, ip, #13 ; 0xd + 17cc8: e1a00fac mov r0, ip, lsr #31 + 17ccc: e08ff100 add pc, pc, r0, lsl #2 + 17cd0: 080043ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, lr} + 17cd4: ebf5ac9e bl 0xffd82f54 + 17cd8: ea00000d b 0x17d14 + 17cdc: ebf5b0a7 bl 0xffd83f80 + 17ce0: 080043e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, lr} + 17ce4: e3b04000 movs r4, #0 ; 0x0 + 17ce8: ebf5b0a4 bl 0xffd83f80 + 17cec: 080043e8 stmeqda r0, {r3, r5, r6, r7, r8, r9, lr} + 17cf0: e3b00000 movs r0, #0 ; 0x0 + 17cf4: e58d041c str r0, [sp, #1052] + 17cf8: ebf5b0a0 bl 0xffd83f80 + 17cfc: 080043ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, lr} + 17d00: e3b06000 movs r6, #0 ; 0x0 + 17d04: ebf5b09d bl 0xffd83f80 + 17d08: 080043ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, lr} + 17d0c: e3b05000 movs r5, #0 ; 0x0 + 17d10: e28cc00c add ip, ip, #12 ; 0xc + 17d14: ebf5b099 bl 0xffd83f80 + 17d18: 080043ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, lr} + 17d1c: e59d1420 ldr r1, [sp, #1056] + 17d20: e1a08001 mov r8, r1 + 17d24: ebf5b095 bl 0xffd83f80 + 17d28: 080043f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, lr} + 17d2c: e59d0434 ldr r0, [sp, #1076] + 17d30: e2800f07 add r0, r0, #28 ; 0x1c + 17d34: e1a01008 mov r1, r8 + 17d38: ebf5ae23 bl 0xffd835cc + 17d3c: 080043f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, lr} + 17d40: ebf5b08e bl 0xffd83f80 + 17d44: 080043f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, lr} + 17d48: e59d1424 ldr r1, [sp, #1060] + 17d4c: e1a03001 mov r3, r1 + 17d50: ebf5b08a bl 0xffd83f80 + 17d54: 080043f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, lr} + 17d58: e59d0434 ldr r0, [sp, #1076] + 17d5c: e2800f08 add r0, r0, #32 ; 0x20 + 17d60: e1a01003 mov r1, r3 + 17d64: ebf5ae18 bl 0xffd835cc + 17d68: 080043f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, lr} + 17d6c: ebf5b083 bl 0xffd83f80 + 17d70: 080043f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, lr} + 17d74: e3b0803e movs r8, #62 ; 0x3e + 17d78: ebf5b080 bl 0xffd83f80 + 17d7c: 080043f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, lr} + 17d80: e0870008 add r0, r7, r8 + 17d84: ebf5aecc bl 0xffd838bc + 17d88: 080043fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, lr} + 17d8c: e1a03000 mov r3, r0 + 17d90: ebf5b07a bl 0xffd83f80 + 17d94: 080043fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, lr} + 17d98: e59d0434 ldr r0, [sp, #1076] + 17d9c: e2800f02 add r0, r0, #8 ; 0x8 + 17da0: ebf5aedc bl 0xffd83918 + 17da4: 080043fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, lr} + 17da8: e1a08000 mov r8, r0 + 17dac: ebf5b073 bl 0xffd83f80 + 17db0: 080043fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, lr} + 17db4: e1580003 cmp r8, r3 + 17db8: ebf5b070 bl 0xffd83f80 + 17dbc: 080043fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, lr} + 17dc0: e28cc021 add ip, ip, #33 ; 0x21 + 17dc4: 1a000004 bne 0x17ddc + 17dc8: e1a00fac mov r0, ip, lsr #31 + 17dcc: e08ff100 add pc, pc, r0, lsl #2 + 17dd0: 0800441c stmeqda r0, {r2, r3, r4, sl, lr} + 17dd4: ebf5ac5e bl 0xffd82f54 + 17dd8: ea000059 b 0x17f44 + 17ddc: ebf5b067 bl 0xffd83f80 + 17de0: 08004400 stmeqda r0, {sl, lr} + 17de4: e1580003 cmp r8, r3 + 17de8: ebf5b064 bl 0xffd83f80 + 17dec: 08004402 stmeqda r0, {r1, sl, lr} + 17df0: e28cc006 add ip, ip, #6 ; 0x6 + 17df4: ba000004 blt 0x17e0c + 17df8: e1a00fac mov r0, ip, lsr #31 + 17dfc: e08ff100 add pc, pc, r0, lsl #2 + 17e00: 08004410 stmeqda r0, {r4, sl, lr} + 17e04: ebf5ac52 bl 0xffd82f54 + 17e08: ea000025 b 0x17ea4 + 17e0c: ebf5b05b bl 0xffd83f80 + 17e10: 08004404 stmeqda r0, {r2, sl, lr} + 17e14: e59d0434 ldr r0, [sp, #1076] + 17e18: e2800f05 add r0, r0, #20 ; 0x14 + 17e1c: ebf5aebd bl 0xffd83918 + 17e20: 08004408 stmeqda r0, {r3, sl, lr} + 17e24: e58d041c str r0, [sp, #1052] + 17e28: ebf5b054 bl 0xffd83f80 + 17e2c: 08004406 stmeqda r0, {r1, r2, sl, lr} + 17e30: e59d0434 ldr r0, [sp, #1076] + 17e34: e2800f04 add r0, r0, #16 ; 0x10 + 17e38: ebf5aeb6 bl 0xffd83918 + 17e3c: 0800440a stmeqda r0, {r1, r3, sl, lr} + 17e40: e1a04000 mov r4, r0 + 17e44: ebf5b04d bl 0xffd83f80 + 17e48: 08004408 stmeqda r0, {r3, sl, lr} + 17e4c: e59d0434 ldr r0, [sp, #1076] + 17e50: e2800f03 add r0, r0, #12 ; 0xc + 17e54: ebf5aeaf bl 0xffd83918 + 17e58: 0800440c stmeqda r0, {r2, r3, sl, lr} + 17e5c: e58d0418 str r0, [sp, #1048] + 17e60: ebf5b046 bl 0xffd83f80 + 17e64: 0800440a stmeqda r0, {r1, r3, sl, lr} + 17e68: e59d141c ldr r1, [sp, #1052] + 17e6c: e59d141c ldr r1, [sp, #1052] + 17e70: e2918000 adds r8, r1, #0 ; 0x0 + 17e74: ebf5b041 bl 0xffd83f80 + 17e78: 0800440c stmeqda r0, {r2, r3, sl, lr} + 17e7c: e1a01008 mov r1, r8 + 17e80: e2588001 subs r8, r8, #1 ; 0x1 + 17e84: ebf5b03d bl 0xffd83f80 + 17e88: 0800440e stmeqda r0, {r1, r2, r3, sl, lr} + 17e8c: e28cc018 add ip, ip, #24 ; 0x18 + 17e90: e1a00fac mov r0, ip, lsr #31 + 17e94: e08ff100 add pc, pc, r0, lsl #2 + 17e98: 08004420 stmeqda r0, {r5, sl, lr} + 17e9c: ebf5ac2c bl 0xffd82f54 + 17ea0: ea00002f b 0x17f64 + 17ea4: ebf5b035 bl 0xffd83f80 + 17ea8: 08004410 stmeqda r0, {r4, sl, lr} + 17eac: e59d0434 ldr r0, [sp, #1076] + 17eb0: e2800f03 add r0, r0, #12 ; 0xc + 17eb4: ebf5ae97 bl 0xffd83918 + 17eb8: 08004414 stmeqda r0, {r2, r4, sl, lr} + 17ebc: e58d041c str r0, [sp, #1052] + 17ec0: ebf5b02e bl 0xffd83f80 + 17ec4: 08004412 stmeqda r0, {r1, r4, sl, lr} + 17ec8: e59d0434 ldr r0, [sp, #1076] + 17ecc: e2800f06 add r0, r0, #24 ; 0x18 + 17ed0: ebf5ae90 bl 0xffd83918 + 17ed4: 08004416 stmeqda r0, {r1, r2, r4, sl, lr} + 17ed8: e1a04000 mov r4, r0 + 17edc: ebf5b027 bl 0xffd83f80 + 17ee0: 08004414 stmeqda r0, {r2, r4, sl, lr} + 17ee4: e1a01004 mov r1, r4 + 17ee8: e2940000 adds r0, r4, #0 ; 0x0 + 17eec: e58d0418 str r0, [sp, #1048] + 17ef0: ebf5b022 bl 0xffd83f80 + 17ef4: 08004416 stmeqda r0, {r1, r2, r4, sl, lr} + 17ef8: e59d1418 ldr r1, [sp, #1048] + 17efc: e59d1418 ldr r1, [sp, #1048] + 17f00: e2910001 adds r0, r1, #1 ; 0x1 + 17f04: e58d0418 str r0, [sp, #1048] + 17f08: ebf5b01c bl 0xffd83f80 + 17f0c: 08004418 stmeqda r0, {r3, r4, sl, lr} + 17f10: e59d0434 ldr r0, [sp, #1076] + 17f14: e2800f04 add r0, r0, #16 ; 0x10 + 17f18: ebf5ae7e bl 0xffd83918 + 17f1c: 0800441c stmeqda r0, {r2, r3, r4, sl, lr} + 17f20: e1a08000 mov r8, r0 + 17f24: ebf5b015 bl 0xffd83f80 + 17f28: 0800441a stmeqda r0, {r1, r3, r4, sl, lr} + 17f2c: e28cc018 add ip, ip, #24 ; 0x18 + 17f30: e1a00fac mov r0, ip, lsr #31 + 17f34: e08ff100 add pc, pc, r0, lsl #2 + 17f38: 08004420 stmeqda r0, {r5, sl, lr} + 17f3c: ebf5ac04 bl 0xffd82f54 + 17f40: ea000007 b 0x17f64 + 17f44: ebf5b00d bl 0xffd83f80 + 17f48: 0800441c stmeqda r0, {r2, r3, r4, sl, lr} + 17f4c: e3b08000 movs r8, #0 ; 0x0 + 17f50: ebf5b00a bl 0xffd83f80 + 17f54: 0800441e stmeqda r0, {r1, r2, r3, r4, sl, lr} + 17f58: e3b00000 movs r0, #0 ; 0x0 + 17f5c: e58d0418 str r0, [sp, #1048] + 17f60: e28cc006 add ip, ip, #6 ; 0x6 + 17f64: ebf5b005 bl 0xffd83f80 + 17f68: 08004420 stmeqda r0, {r5, sl, lr} + 17f6c: e59d0420 ldr r0, [sp, #1056] + 17f70: e59d1428 ldr r1, [sp, #1064] + 17f74: e1500001 cmp r0, r1 + 17f78: ebf5b000 bl 0xffd83f80 + 17f7c: 08004422 stmeqda r0, {r1, r5, sl, lr} + 17f80: e28cc006 add ip, ip, #6 ; 0x6 + 17f84: 0a000004 beq 0x17f9c + 17f88: e1a00fac mov r0, ip, lsr #31 + 17f8c: e08ff100 add pc, pc, r0, lsl #2 + 17f90: 08004428 stmeqda r0, {r3, r5, sl, lr} + 17f94: ebf5abee bl 0xffd82f54 + 17f98: ea00000d b 0x17fd4 + 17f9c: ebf5aff7 bl 0xffd83f80 + 17fa0: 08004424 stmeqda r0, {r2, r5, sl, lr} + 17fa4: e59d0424 ldr r0, [sp, #1060] + 17fa8: e59d1430 ldr r1, [sp, #1072] + 17fac: e1500001 cmp r0, r1 + 17fb0: ebf5aff2 bl 0xffd83f80 + 17fb4: 08004426 stmeqda r0, {r1, r2, r5, sl, lr} + 17fb8: e28cc006 add ip, ip, #6 ; 0x6 + 17fbc: 1a000004 bne 0x17fd4 + 17fc0: e1a00fac mov r0, ip, lsr #31 + 17fc4: e08ff100 add pc, pc, r0, lsl #2 + 17fc8: 0800443e stmeqda r0, {r1, r2, r3, r4, r5, sl, lr} + 17fcc: ebf5abe0 bl 0xffd82f54 + 17fd0: ea00003d b 0x180cc + 17fd4: ebf5afe9 bl 0xffd83f80 + 17fd8: 08004428 stmeqda r0, {r3, r5, sl, lr} + 17fdc: e1550006 cmp r5, r6 + 17fe0: ebf5afe6 bl 0xffd83f80 + 17fe4: 0800442a stmeqda r0, {r1, r3, r5, sl, lr} + 17fe8: e28cc006 add ip, ip, #6 ; 0x6 + 17fec: da000004 ble 0x18004 + 17ff0: e1a00fac mov r0, ip, lsr #31 + 17ff4: e08ff100 add pc, pc, r0, lsl #2 + 17ff8: 0800443e stmeqda r0, {r1, r2, r3, r4, r5, sl, lr} + 17ffc: ebf5abd4 bl 0xffd82f54 + 18000: ea000031 b 0x180cc + 18004: ebf5afdd bl 0xffd83f80 + 18008: 0800442c stmeqda r0, {r2, r3, r5, sl, lr} + 1800c: e1a01006 mov r1, r6 + 18010: e0563005 subs r3, r6, r5 + 18014: ebf5afd9 bl 0xffd83f80 + 18018: 0800442e stmeqda r0, {r1, r2, r3, r5, sl, lr} + 1801c: e353001d cmp r3, #29 ; 0x1d + 18020: ebf5afd6 bl 0xffd83f80 + 18024: 08004430 stmeqda r0, {r4, r5, sl, lr} + 18028: e28cc009 add ip, ip, #9 ; 0x9 + 1802c: da000004 ble 0x18044 + 18030: e1a00fac mov r0, ip, lsr #31 + 18034: e08ff100 add pc, pc, r0, lsl #2 + 18038: 0800443e stmeqda r0, {r1, r2, r3, r4, r5, sl, lr} + 1803c: ebf5abc4 bl 0xffd82f54 + 18040: ea000021 b 0x180cc + 18044: ebf5afcd bl 0xffd83f80 + 18048: 08004432 stmeqda r0, {r1, r4, r5, sl, lr} + 1804c: e59d0434 ldr r0, [sp, #1076] + 18050: e2800f00 add r0, r0, #0 ; 0x0 + 18054: e1a01004 mov r1, r4 + 18058: ebf5ad5b bl 0xffd835cc + 1805c: 08004434 stmeqda r0, {r2, r4, r5, sl, lr} + 18060: ebf5afc6 bl 0xffd83f80 + 18064: 08004434 stmeqda r0, {r2, r4, r5, sl, lr} + 18068: e1a01007 mov r1, r7 + 1806c: e2973000 adds r3, r7, #0 ; 0x0 + 18070: ebf5afc2 bl 0xffd83f80 + 18074: 08004436 stmeqda r0, {r1, r2, r4, r5, sl, lr} + 18078: e1a01005 mov r1, r5 + 1807c: e2954000 adds r4, r5, #0 ; 0x0 + 18080: ebf5afbe bl 0xffd83f80 + 18084: 08004438 stmeqda r0, {r3, r4, r5, sl, lr} + 18088: e59d141c ldr r1, [sp, #1052] + 1808c: e59d141c ldr r1, [sp, #1052] + 18090: e2915000 adds r5, r1, #0 ; 0x0 + 18094: ebf5afb9 bl 0xffd83f80 + 18098: 0800443a stmeqda r0, {r1, r3, r4, r5, sl, lr} + 1809c: ebf5afb7 bl 0xffd83f80 + 180a0: 0800443c stmeqda r0, {r2, r3, r4, r5, sl, lr} + 180a4: e3a0003f mov r0, #63 ; 0x3f + 180a8: e3800b11 orr r0, r0, #17408 ; 0x4400 + 180ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 180b0: e58d0438 str r0, [sp, #1080] + 180b4: e28cc013 add ip, ip, #19 ; 0x13 + 180b8: e1a00fac mov r0, ip, lsr #31 + 180bc: e08ff100 add pc, pc, r0, lsl #2 + 180c0: 08004484 stmeqda r0, {r2, r7, sl, lr} + 180c4: ebf5aba2 bl 0xffd82f54 + 180c8: ea0000eb b 0x1847c + 180cc: ebf5afab bl 0xffd83f80 + 180d0: 0800443e stmeqda r0, {r1, r2, r3, r4, r5, sl, lr} + 180d4: e59d0434 ldr r0, [sp, #1076] + 180d8: e2800f03 add r0, r0, #12 ; 0xc + 180dc: ebf5ae0d bl 0xffd83918 + 180e0: 08004442 stmeqda r0, {r1, r6, sl, lr} + 180e4: e58d041c str r0, [sp, #1052] + 180e8: ebf5afa4 bl 0xffd83f80 + 180ec: 08004440 stmeqda r0, {r6, sl, lr} + 180f0: e59d0434 ldr r0, [sp, #1076] + 180f4: e2800f05 add r0, r0, #20 ; 0x14 + 180f8: ebf5ae06 bl 0xffd83918 + 180fc: 08004444 stmeqda r0, {r2, r6, sl, lr} + 18100: e1a03000 mov r3, r0 + 18104: ebf5af9d bl 0xffd83f80 + 18108: 08004442 stmeqda r0, {r1, r6, sl, lr} + 1810c: e59d141c ldr r1, [sp, #1052] + 18110: e1510003 cmp r1, r3 + 18114: ebf5af99 bl 0xffd83f80 + 18118: 08004444 stmeqda r0, {r2, r6, sl, lr} + 1811c: e28cc010 add ip, ip, #16 ; 0x10 + 18120: 0a000004 beq 0x18138 + 18124: e1a00fac mov r0, ip, lsr #31 + 18128: e08ff100 add pc, pc, r0, lsl #2 + 1812c: 0800444e stmeqda r0, {r1, r2, r3, r6, sl, lr} + 18130: ebf5ab87 bl 0xffd82f54 + 18134: ea000019 b 0x181a0 + 18138: ebf5af90 bl 0xffd83f80 + 1813c: 08004446 stmeqda r0, {r1, r2, r6, sl, lr} + 18140: e59d0434 ldr r0, [sp, #1076] + 18144: e2800f04 add r0, r0, #16 ; 0x10 + 18148: ebf5adf2 bl 0xffd83918 + 1814c: 0800444a stmeqda r0, {r1, r3, r6, sl, lr} + 18150: e1a04000 mov r4, r0 + 18154: ebf5af89 bl 0xffd83f80 + 18158: 08004448 stmeqda r0, {r3, r6, sl, lr} + 1815c: e59d0434 ldr r0, [sp, #1076] + 18160: e2800f06 add r0, r0, #24 ; 0x18 + 18164: ebf5adeb bl 0xffd83918 + 18168: 0800444c stmeqda r0, {r2, r3, r6, sl, lr} + 1816c: e1a05000 mov r5, r0 + 18170: ebf5af82 bl 0xffd83f80 + 18174: 0800444a stmeqda r0, {r1, r3, r6, sl, lr} + 18178: e1540005 cmp r4, r5 + 1817c: ebf5af7f bl 0xffd83f80 + 18180: 0800444c stmeqda r0, {r2, r3, r6, sl, lr} + 18184: e28cc010 add ip, ip, #16 ; 0x10 + 18188: 1a000004 bne 0x181a0 + 1818c: e1a00fac mov r0, ip, lsr #31 + 18190: e08ff100 add pc, pc, r0, lsl #2 + 18194: 08004466 stmeqda r0, {r1, r2, r5, r6, sl, lr} + 18198: ebf5ab6d bl 0xffd82f54 + 1819c: ea000049 b 0x182c8 + 181a0: ebf5af76 bl 0xffd83f80 + 181a4: 0800444e stmeqda r0, {r1, r2, r3, r6, sl, lr} + 181a8: e59d1418 ldr r1, [sp, #1048] + 181ac: e1510008 cmp r1, r8 + 181b0: ebf5af72 bl 0xffd83f80 + 181b4: 08004450 stmeqda r0, {r4, r6, sl, lr} + 181b8: e28cc006 add ip, ip, #6 ; 0x6 + 181bc: da000004 ble 0x181d4 + 181c0: e1a00fac mov r0, ip, lsr #31 + 181c4: e08ff100 add pc, pc, r0, lsl #2 + 181c8: 08004466 stmeqda r0, {r1, r2, r5, r6, sl, lr} + 181cc: ebf5ab60 bl 0xffd82f54 + 181d0: ea00003c b 0x182c8 + 181d4: ebf5af69 bl 0xffd83f80 + 181d8: 08004452 stmeqda r0, {r1, r4, r6, sl, lr} + 181dc: e1a01008 mov r1, r8 + 181e0: e59d0418 ldr r0, [sp, #1048] + 181e4: e0583000 subs r3, r8, r0 + 181e8: ebf5af64 bl 0xffd83f80 + 181ec: 08004454 stmeqda r0, {r2, r4, r6, sl, lr} + 181f0: e3530013 cmp r3, #19 ; 0x13 + 181f4: ebf5af61 bl 0xffd83f80 + 181f8: 08004456 stmeqda r0, {r1, r2, r4, r6, sl, lr} + 181fc: e28cc009 add ip, ip, #9 ; 0x9 + 18200: da000004 ble 0x18218 + 18204: e1a00fac mov r0, ip, lsr #31 + 18208: e08ff100 add pc, pc, r0, lsl #2 + 1820c: 08004466 stmeqda r0, {r1, r2, r5, r6, sl, lr} + 18210: ebf5ab4f bl 0xffd82f54 + 18214: ea00002b b 0x182c8 + 18218: ebf5af58 bl 0xffd83f80 + 1821c: 08004458 stmeqda r0, {r3, r4, r6, sl, lr} + 18220: e59d0434 ldr r0, [sp, #1076] + 18224: e2800f00 add r0, r0, #0 ; 0x0 + 18228: e1a01008 mov r1, r8 + 1822c: ebf5ace6 bl 0xffd835cc + 18230: 0800445a stmeqda r0, {r1, r3, r4, r6, sl, lr} + 18234: ebf5af51 bl 0xffd83f80 + 18238: 0800445a stmeqda r0, {r1, r3, r4, r6, sl, lr} + 1823c: e1a01007 mov r1, r7 + 18240: e2973000 adds r3, r7, #0 ; 0x0 + 18244: ebf5af4d bl 0xffd83f80 + 18248: 0800445c stmeqda r0, {r2, r3, r4, r6, sl, lr} + 1824c: e59d0434 ldr r0, [sp, #1076] + 18250: e2800f07 add r0, r0, #28 ; 0x1c + 18254: ebf5adaf bl 0xffd83918 + 18258: 08004460 stmeqda r0, {r5, r6, sl, lr} + 1825c: e1a04000 mov r4, r0 + 18260: ebf5af46 bl 0xffd83f80 + 18264: 0800445e stmeqda r0, {r1, r2, r3, r4, r6, sl, lr} + 18268: e59d1418 ldr r1, [sp, #1048] + 1826c: e59d1418 ldr r1, [sp, #1048] + 18270: e2915000 adds r5, r1, #0 ; 0x0 + 18274: ebf5af41 bl 0xffd83f80 + 18278: 08004460 stmeqda r0, {r5, r6, sl, lr} + 1827c: e59d0434 ldr r0, [sp, #1076] + 18280: e2800f08 add r0, r0, #32 ; 0x20 + 18284: ebf5ada3 bl 0xffd83918 + 18288: 08004464 stmeqda r0, {r2, r5, r6, sl, lr} + 1828c: e1a06000 mov r6, r0 + 18290: ebf5af3a bl 0xffd83f80 + 18294: 08004462 stmeqda r0, {r1, r5, r6, sl, lr} + 18298: ebf5af38 bl 0xffd83f80 + 1829c: 08004464 stmeqda r0, {r2, r5, r6, sl, lr} + 182a0: e3a00067 mov r0, #103 ; 0x67 + 182a4: e3800b11 orr r0, r0, #17408 ; 0x4400 + 182a8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 182ac: e58d0438 str r0, [sp, #1080] + 182b0: e28cc01a add ip, ip, #26 ; 0x1a + 182b4: e1a00fac mov r0, ip, lsr #31 + 182b8: e08ff100 add pc, pc, r0, lsl #2 + 182bc: 08004484 stmeqda r0, {r2, r7, sl, lr} + 182c0: ebf5ab23 bl 0xffd82f54 + 182c4: ea00006c b 0x1847c + 182c8: ebf5af2c bl 0xffd83f80 + 182cc: 08004466 stmeqda r0, {r1, r2, r5, r6, sl, lr} + 182d0: e59d1434 ldr r1, [sp, #1076] + 182d4: e1a08001 mov r8, r1 + 182d8: ebf5af28 bl 0xffd83f80 + 182dc: 08004468 stmeqda r0, {r3, r5, r6, sl, lr} + 182e0: e2880004 add r0, r8, #4 ; 0x4 + 182e4: ebf5ad5f bl 0xffd83868 + 182e8: 0800446c stmeqda r0, {r2, r3, r5, r6, sl, lr} + 182ec: e1a08000 mov r8, r0 + 182f0: ebf5af22 bl 0xffd83f80 + 182f4: 0800446a stmeqda r0, {r1, r3, r5, r6, sl, lr} + 182f8: e287003c add r0, r7, #60 ; 0x3c + 182fc: e1a01008 mov r1, r8 + 18300: ebf5ac91 bl 0xffd8354c + 18304: 0800446c stmeqda r0, {r2, r3, r5, r6, sl, lr} + 18308: ebf5af1c bl 0xffd83f80 + 1830c: 0800446c stmeqda r0, {r2, r3, r5, r6, sl, lr} + 18310: e59d1434 ldr r1, [sp, #1076] + 18314: e1a00001 mov r0, r1 + 18318: e58d041c str r0, [sp, #1052] + 1831c: ebf5af17 bl 0xffd83f80 + 18320: 0800446e stmeqda r0, {r1, r2, r3, r5, r6, sl, lr} + 18324: e59d041c ldr r0, [sp, #1052] + 18328: e2800008 add r0, r0, #8 ; 0x8 + 1832c: ebf5ad4d bl 0xffd83868 + 18330: 08004472 stmeqda r0, {r1, r4, r5, r6, sl, lr} + 18334: e58d041c str r0, [sp, #1052] + 18338: ebf5af10 bl 0xffd83f80 + 1833c: 08004470 stmeqda r0, {r4, r5, r6, sl, lr} + 18340: e287003e add r0, r7, #62 ; 0x3e + 18344: e59d141c ldr r1, [sp, #1052] + 18348: ebf5ac7f bl 0xffd8354c + 1834c: 08004472 stmeqda r0, {r1, r4, r5, r6, sl, lr} + 18350: e28cc018 add ip, ip, #24 ; 0x18 + 18354: ebf5af09 bl 0xffd83f80 + 18358: 08004472 stmeqda r0, {r1, r4, r5, r6, sl, lr} + 1835c: e59d0434 ldr r0, [sp, #1076] + 18360: e2800f09 add r0, r0, #36 ; 0x24 + 18364: e58d0434 str r0, [sp, #1076] + 18368: ebf5af04 bl 0xffd83f80 + 1836c: 08004474 stmeqda r0, {r2, r4, r5, r6, sl, lr} + 18370: e59d9434 ldr r9, [sp, #1076] + 18374: e3c99003 bic r9, r9, #3 ; 0x3 + 18378: e289000c add r0, r9, #12 ; 0xc + 1837c: e58d0434 str r0, [sp, #1076] + 18380: e2890000 add r0, r9, #0 ; 0x0 + 18384: ebf5ad63 bl 0xffd83918 + 18388: 08004478 stmeqda r0, {r3, r4, r5, r6, sl, lr} + 1838c: e1a06000 mov r6, r0 + 18390: e2890004 add r0, r9, #4 ; 0x4 + 18394: ebf5ad5f bl 0xffd83918 + 18398: 08004478 stmeqda r0, {r3, r4, r5, r6, sl, lr} + 1839c: e1a07000 mov r7, r0 + 183a0: e2890008 add r0, r9, #8 ; 0x8 + 183a4: ebf5ad5b bl 0xffd83918 + 183a8: 08004478 stmeqda r0, {r3, r4, r5, r6, sl, lr} + 183ac: e1a08000 mov r8, r0 + 183b0: ebf5aef2 bl 0xffd83f80 + 183b4: 08004476 stmeqda r0, {r1, r2, r4, r5, r6, sl, lr} + 183b8: e1a00006 mov r0, r6 + 183bc: e58d0420 str r0, [sp, #1056] + 183c0: ebf5aeee bl 0xffd83f80 + 183c4: 08004478 stmeqda r0, {r3, r4, r5, r6, sl, lr} + 183c8: e1a00007 mov r0, r7 + 183cc: e58d0424 str r0, [sp, #1060] + 183d0: ebf5aeea bl 0xffd83f80 + 183d4: 0800447a stmeqda r0, {r1, r3, r4, r5, r6, sl, lr} + 183d8: e1a00008 mov r0, r8 + 183dc: e58d0428 str r0, [sp, #1064] + 183e0: ebf5aee6 bl 0xffd83f80 + 183e4: 0800447c stmeqda r0, {r2, r3, r4, r5, r6, sl, lr} + 183e8: e59d9434 ldr r9, [sp, #1076] + 183ec: e3c99003 bic r9, r9, #3 ; 0x3 + 183f0: e2890010 add r0, r9, #16 ; 0x10 + 183f4: e58d0434 str r0, [sp, #1076] + 183f8: e2890000 add r0, r9, #0 ; 0x0 + 183fc: ebf5ad45 bl 0xffd83918 + 18400: 08004480 stmeqda r0, {r7, sl, lr} + 18404: e1a07000 mov r7, r0 + 18408: e2890004 add r0, r9, #4 ; 0x4 + 1840c: ebf5ad41 bl 0xffd83918 + 18410: 08004480 stmeqda r0, {r7, sl, lr} + 18414: e1a08000 mov r8, r0 + 18418: e2890008 add r0, r9, #8 ; 0x8 + 1841c: ebf5ad3d bl 0xffd83918 + 18420: 08004480 stmeqda r0, {r7, sl, lr} + 18424: e58d0418 str r0, [sp, #1048] + 18428: e289000c add r0, r9, #12 ; 0xc + 1842c: ebf5ad39 bl 0xffd83918 + 18430: 08004480 stmeqda r0, {r7, sl, lr} + 18434: e58d041c str r0, [sp, #1052] + 18438: ebf5aed0 bl 0xffd83f80 + 1843c: 0800447e stmeqda r0, {r1, r2, r3, r4, r5, r6, sl, lr} + 18440: e59d9434 ldr r9, [sp, #1076] + 18444: e3c99003 bic r9, r9, #3 ; 0x3 + 18448: e2890004 add r0, r9, #4 ; 0x4 + 1844c: e58d0434 str r0, [sp, #1076] + 18450: e2890000 add r0, r9, #0 ; 0x0 + 18454: ebf5ad2f bl 0xffd83918 + 18458: 08004482 stmeqda r0, {r1, r7, sl, lr} + 1845c: e1a03000 mov r3, r0 + 18460: ebf5aec6 bl 0xffd83f80 + 18464: 08004480 stmeqda r0, {r7, sl, lr} + 18468: e1a00003 mov r0, r3 + 1846c: e28cc020 add ip, ip, #32 ; 0x20 + 18470: eaf5ab16 b 0xffd830d0 + 18474: 08004484 stmeqda r0, {r2, r7, sl, lr} + 18478: 00000000 andeq r0, r0, r0 + 1847c: ebf5aebf bl 0xffd83f80 + 18480: 08004484 stmeqda r0, {r2, r7, sl, lr} + 18484: e59d9434 ldr r9, [sp, #1076] + 18488: e3c99003 bic r9, r9, #3 ; 0x3 + 1848c: e2499014 sub r9, r9, #20 ; 0x14 + 18490: e58d9434 str r9, [sp, #1076] + 18494: e2890000 add r0, r9, #0 ; 0x0 + 18498: e1a01007 mov r1, r7 + 1849c: ebf5ac6a bl 0xffd8364c + 184a0: e2890004 add r0, r9, #4 ; 0x4 + 184a4: e1a01008 mov r1, r8 + 184a8: ebf5ac67 bl 0xffd8364c + 184ac: e2890008 add r0, r9, #8 ; 0x8 + 184b0: e59d1418 ldr r1, [sp, #1048] + 184b4: ebf5ac64 bl 0xffd8364c + 184b8: e289000c add r0, r9, #12 ; 0xc + 184bc: e59d141c ldr r1, [sp, #1052] + 184c0: ebf5ac61 bl 0xffd8364c + 184c4: e2890010 add r0, r9, #16 ; 0x10 + 184c8: e59d1438 ldr r1, [sp, #1080] + 184cc: ebf5ac5e bl 0xffd8364c + 184d0: ebf5aeaa bl 0xffd83f80 + 184d4: 08004486 stmeqda r0, {r1, r2, r7, sl, lr} + 184d8: e59d1428 ldr r1, [sp, #1064] + 184dc: e1a00001 mov r0, r1 + 184e0: e58d041c str r0, [sp, #1052] + 184e4: ebf5aea5 bl 0xffd83f80 + 184e8: 08004488 stmeqda r0, {r3, r7, sl, lr} + 184ec: e59d1424 ldr r1, [sp, #1060] + 184f0: e1a00001 mov r0, r1 + 184f4: e58d0418 str r0, [sp, #1048] + 184f8: ebf5aea0 bl 0xffd83f80 + 184fc: 0800448a stmeqda r0, {r1, r3, r7, sl, lr} + 18500: e59d1420 ldr r1, [sp, #1056] + 18504: e1a08001 mov r8, r1 + 18508: ebf5ae9c bl 0xffd83f80 + 1850c: 0800448c stmeqda r0, {r2, r3, r7, sl, lr} + 18510: e59d9434 ldr r9, [sp, #1076] + 18514: e3c99003 bic r9, r9, #3 ; 0x3 + 18518: e249900c sub r9, r9, #12 ; 0xc + 1851c: e58d9434 str r9, [sp, #1076] + 18520: e2890000 add r0, r9, #0 ; 0x0 + 18524: e1a01008 mov r1, r8 + 18528: ebf5ac47 bl 0xffd8364c + 1852c: e2890004 add r0, r9, #4 ; 0x4 + 18530: e59d1418 ldr r1, [sp, #1048] + 18534: ebf5ac44 bl 0xffd8364c + 18538: e2890008 add r0, r9, #8 ; 0x8 + 1853c: e59d141c ldr r1, [sp, #1052] + 18540: ebf5ac21 bl 0xffd835cc + 18544: 0800448e stmeqda r0, {r1, r2, r3, r7, sl, lr} + 18548: ebf5ae8c bl 0xffd83f80 + 1854c: 0800448e stmeqda r0, {r1, r2, r3, r7, sl, lr} + 18550: e59d0434 ldr r0, [sp, #1076] + 18554: e2400f0d sub r0, r0, #52 ; 0x34 + 18558: e58d0434 str r0, [sp, #1076] + 1855c: ebf5ae87 bl 0xffd83f80 + 18560: 08004490 stmeqda r0, {r4, r7, sl, lr} + 18564: e1a01003 mov r1, r3 + 18568: e2930000 adds r0, r3, #0 ; 0x0 + 1856c: e58d041c str r0, [sp, #1052] + 18570: ebf5ae82 bl 0xffd83f80 + 18574: 08004492 stmeqda r0, {r1, r4, r7, sl, lr} + 18578: e59d0434 ldr r0, [sp, #1076] + 1857c: e2800f00 add r0, r0, #0 ; 0x0 + 18580: e1a01004 mov r1, r4 + 18584: ebf5ac10 bl 0xffd835cc + 18588: 08004494 stmeqda r0, {r2, r4, r7, sl, lr} + 1858c: ebf5ae7b bl 0xffd83f80 + 18590: 08004494 stmeqda r0, {r2, r4, r7, sl, lr} + 18594: e59d0434 ldr r0, [sp, #1076] + 18598: e2800f01 add r0, r0, #4 ; 0x4 + 1859c: e1a01006 mov r1, r6 + 185a0: ebf5ac09 bl 0xffd835cc + 185a4: 08004496 stmeqda r0, {r1, r2, r4, r7, sl, lr} + 185a8: ebf5ae74 bl 0xffd83f80 + 185ac: 08004496 stmeqda r0, {r1, r2, r4, r7, sl, lr} + 185b0: e59d041c ldr r0, [sp, #1052] + 185b4: e2800000 add r0, r0, #0 ; 0x0 + 185b8: ebf5acaa bl 0xffd83868 + 185bc: 0800449a stmeqda r0, {r1, r3, r4, r7, sl, lr} + 185c0: e1a04000 mov r4, r0 + 185c4: ebf5ae6d bl 0xffd83f80 + 185c8: 08004498 stmeqda r0, {r3, r4, r7, sl, lr} + 185cc: e3b03080 movs r3, #128 ; 0x80 + 185d0: ebf5ae6a bl 0xffd83f80 + 185d4: 0800449a stmeqda r0, {r1, r3, r4, r7, sl, lr} + 185d8: e1b03083 movs r3, r3, lsl #1 + 185dc: ebf5ae67 bl 0xffd83f80 + 185e0: 0800449c stmeqda r0, {r2, r3, r4, r7, sl, lr} + 185e4: e1a01003 mov r1, r3 + 185e8: e0133004 ands r3, r3, r4 + 185ec: ebf5ae63 bl 0xffd83f80 + 185f0: 0800449e stmeqda r0, {r1, r2, r3, r4, r7, sl, lr} + 185f4: e3530000 cmp r3, #0 ; 0x0 + 185f8: ebf5ae60 bl 0xffd83f80 + 185fc: 080044a0 stmeqda r0, {r5, r7, sl, lr} + 18600: e28cc038 add ip, ip, #56 ; 0x38 + 18604: 0a000004 beq 0x1861c + 18608: e1a00fac mov r0, ip, lsr #31 + 1860c: e08ff100 add pc, pc, r0, lsl #2 + 18610: 080044a4 stmeqda r0, {r2, r5, r7, sl, lr} + 18614: ebf5aa4e bl 0xffd82f54 + 18618: ea000007 b 0x1863c + 1861c: ebf5ae57 bl 0xffd83f80 + 18620: 080044a2 stmeqda r0, {r1, r5, r7, sl, lr} + 18624: e28cc003 add ip, ip, #3 ; 0x3 + 18628: e1a00fac mov r0, ip, lsr #31 + 1862c: e08ff100 add pc, pc, r0, lsl #2 + 18630: 080045c6 stmeqda r0, {r1, r2, r6, r7, r8, sl, lr} + 18634: ebf5aa46 bl 0xffd82f54 + 18638: ea00009b b 0x188ac + 1863c: ebf5ae4f bl 0xffd83f80 + 18640: 080044a4 stmeqda r0, {r2, r5, r7, sl, lr} + 18644: e59d041c ldr r0, [sp, #1052] + 18648: e2800002 add r0, r0, #2 ; 0x2 + 1864c: ebf5ac85 bl 0xffd83868 + 18650: 080044a8 stmeqda r0, {r3, r5, r7, sl, lr} + 18654: e1a03000 mov r3, r0 + 18658: ebf5ae48 bl 0xffd83f80 + 1865c: 080044a6 stmeqda r0, {r1, r2, r5, r7, sl, lr} + 18660: e1b03723 movs r3, r3, lsr #14 + 18664: ebf5ae45 bl 0xffd83f80 + 18668: 080044a8 stmeqda r0, {r3, r5, r7, sl, lr} + 1866c: e3b04010 movs r4, #16 ; 0x10 + 18670: ebf5ae42 bl 0xffd83f80 + 18674: 080044aa stmeqda r0, {r1, r3, r5, r7, sl, lr} + 18678: e1b04314 movs r4, r4, lsl r3 + 1867c: ebf5ae3f bl 0xffd83f80 + 18680: 080044ac stmeqda r0, {r2, r3, r5, r7, sl, lr} + 18684: e59d0434 ldr r0, [sp, #1076] + 18688: e2800f03 add r0, r0, #12 ; 0xc + 1868c: e1a01004 mov r1, r4 + 18690: ebf5abcd bl 0xffd835cc + 18694: 080044ae stmeqda r0, {r1, r2, r3, r5, r7, sl, lr} + 18698: ebf5ae38 bl 0xffd83f80 + 1869c: 080044ae stmeqda r0, {r1, r2, r3, r5, r7, sl, lr} + 186a0: e1a01004 mov r1, r4 + 186a4: e2544001 subs r4, r4, #1 ; 0x1 + 186a8: ebf5ae34 bl 0xffd83f80 + 186ac: 080044b0 stmeqda r0, {r4, r5, r7, sl, lr} + 186b0: e59d0434 ldr r0, [sp, #1076] + 186b4: e2800f02 add r0, r0, #8 ; 0x8 + 186b8: e1a01004 mov r1, r4 + 186bc: ebf5abc2 bl 0xffd835cc + 186c0: 080044b2 stmeqda r0, {r1, r4, r5, r7, sl, lr} + 186c4: ebf5ae2d bl 0xffd83f80 + 186c8: 080044b2 stmeqda r0, {r1, r4, r5, r7, sl, lr} + 186cc: e59d041c ldr r0, [sp, #1052] + 186d0: e2800004 add r0, r0, #4 ; 0x4 + 186d4: ebf5ac8f bl 0xffd83918 + 186d8: 080044b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, lr} + 186dc: e1a07000 mov r7, r0 + 186e0: ebf5ae26 bl 0xffd83f80 + 186e4: 080044b4 stmeqda r0, {r2, r4, r5, r7, sl, lr} + 186e8: e59d0434 ldr r0, [sp, #1076] + 186ec: e2800f04 add r0, r0, #16 ; 0x10 + 186f0: e1a01007 mov r1, r7 + 186f4: ebf5abb4 bl 0xffd835cc + 186f8: 080044b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, lr} + 186fc: ebf5ae1f bl 0xffd83f80 + 18700: 080044b6 stmeqda r0, {r1, r2, r4, r5, r7, sl, lr} + 18704: e1a01005 mov r1, r5 + 18708: e2956000 adds r6, r5, #0 ; 0x0 + 1870c: ebf5ae1b bl 0xffd83f80 + 18710: 080044b8 stmeqda r0, {r3, r4, r5, r7, sl, lr} + 18714: e59d0434 ldr r0, [sp, #1076] + 18718: e2800f15 add r0, r0, #84 ; 0x54 + 1871c: ebf5ac7d bl 0xffd83918 + 18720: 080044bc stmeqda r0, {r2, r3, r4, r5, r7, sl, lr} + 18724: e1a03000 mov r3, r0 + 18728: ebf5ae14 bl 0xffd83f80 + 1872c: 080044ba stmeqda r0, {r1, r3, r4, r5, r7, sl, lr} + 18730: e1560003 cmp r6, r3 + 18734: ebf5ae11 bl 0xffd83f80 + 18738: 080044bc stmeqda r0, {r2, r3, r4, r5, r7, sl, lr} + 1873c: e28cc030 add ip, ip, #48 ; 0x30 + 18740: ca000004 bgt 0x18758 + 18744: e1a00fac mov r0, ip, lsr #31 + 18748: e08ff100 add pc, pc, r0, lsl #2 + 1874c: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 18750: ebf5a9ff bl 0xffd82f54 + 18754: ea000007 b 0x18778 + 18758: ebf5ae08 bl 0xffd83f80 + 1875c: 080044be stmeqda r0, {r1, r2, r3, r4, r5, r7, sl, lr} + 18760: e28cc003 add ip, ip, #3 ; 0x3 + 18764: e1a00fac mov r0, ip, lsr #31 + 18768: e08ff100 add pc, pc, r0, lsl #2 + 1876c: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 18770: ebf5a9f7 bl 0xffd82f54 + 18774: ea0007b0 b 0x1a63c + 18778: ebf5ae00 bl 0xffd83f80 + 1877c: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 18780: e1b05146 movs r5, r6, asr #2 + 18784: ebf5adfd bl 0xffd83f80 + 18788: 080044c2 stmeqda r0, {r1, r6, r7, sl, lr} + 1878c: e59d041c ldr r0, [sp, #1052] + 18790: e2800000 add r0, r0, #0 ; 0x0 + 18794: ebf5ac33 bl 0xffd83868 + 18798: 080044c6 stmeqda r0, {r1, r2, r6, r7, sl, lr} + 1879c: e1a03000 mov r3, r0 + 187a0: ebf5adf6 bl 0xffd83f80 + 187a4: 080044c4 stmeqda r0, {r2, r6, r7, sl, lr} + 187a8: e3b07080 movs r7, #128 ; 0x80 + 187ac: ebf5adf3 bl 0xffd83f80 + 187b0: 080044c6 stmeqda r0, {r1, r2, r6, r7, sl, lr} + 187b4: e1b07107 movs r7, r7, lsl #2 + 187b8: ebf5adf0 bl 0xffd83f80 + 187bc: 080044c8 stmeqda r0, {r3, r6, r7, sl, lr} + 187c0: e1a01007 mov r1, r7 + 187c4: e2974000 adds r4, r7, #0 ; 0x0 + 187c8: ebf5adec bl 0xffd83f80 + 187cc: 080044ca stmeqda r0, {r1, r3, r6, r7, sl, lr} + 187d0: e1a01003 mov r1, r3 + 187d4: e0133004 ands r3, r3, r4 + 187d8: ebf5ade8 bl 0xffd83f80 + 187dc: 080044cc stmeqda r0, {r2, r3, r6, r7, sl, lr} + 187e0: e3530000 cmp r3, #0 ; 0x0 + 187e4: ebf5ade5 bl 0xffd83f80 + 187e8: 080044ce stmeqda r0, {r1, r2, r3, r6, r7, sl, lr} + 187ec: e28cc01a add ip, ip, #26 ; 0x1a + 187f0: 1a000004 bne 0x18808 + 187f4: e1a00fac mov r0, ip, lsr #31 + 187f8: e08ff100 add pc, pc, r0, lsl #2 + 187fc: 080044ee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, lr} + 18800: ebf5a9d3 bl 0xffd82f54 + 18804: ea0007d6 b 0x1a764 + 18808: ebf5addc bl 0xffd83f80 + 1880c: 080044d0 stmeqda r0, {r4, r6, r7, sl, lr} + 18810: e3b03012 movs r3, #18 ; 0x12 + 18814: ebf5add9 bl 0xffd83f80 + 18818: 080044d2 stmeqda r0, {r1, r4, r6, r7, sl, lr} + 1881c: e59d041c ldr r0, [sp, #1052] + 18820: e0800003 add r0, r0, r3 + 18824: ebf5ac24 bl 0xffd838bc + 18828: 080044d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, lr} + 1882c: e1a07000 mov r7, r0 + 18830: ebf5add2 bl 0xffd83f80 + 18834: 080044d4 stmeqda r0, {r2, r4, r6, r7, sl, lr} + 18838: e1a01005 mov r1, r5 + 1883c: e2953000 adds r3, r5, #0 ; 0x0 + 18840: ebf5adce bl 0xffd83f80 + 18844: 080044d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, lr} + 18848: e1a01007 mov r1, r7 + 1884c: e2974000 adds r4, r7, #0 ; 0x0 + 18850: ebf5adca bl 0xffd83f80 + 18854: 080044d8 stmeqda r0, {r3, r4, r6, r7, sl, lr} + 18858: e59d0434 ldr r0, [sp, #1076] + 1885c: e2800f0c add r0, r0, #48 ; 0x30 + 18860: e1a01006 mov r1, r6 + 18864: ebf5ab58 bl 0xffd835cc + 18868: 080044da stmeqda r0, {r1, r3, r4, r6, r7, sl, lr} + 1886c: ebf5adc3 bl 0xffd83f80 + 18870: 080044da stmeqda r0, {r1, r3, r4, r6, r7, sl, lr} + 18874: ebf5adc1 bl 0xffd83f80 + 18878: 080044dc stmeqda r0, {r2, r3, r4, r6, r7, sl, lr} + 1887c: e3a000df mov r0, #223 ; 0xdf + 18880: e3800b11 orr r0, r0, #17408 ; 0x4400 + 18884: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 18888: e58d0438 str r0, [sp, #1080] + 1888c: e28cc018 add ip, ip, #24 ; 0x18 + 18890: e1a00fac mov r0, ip, lsr #31 + 18894: e08ff100 add pc, pc, r0, lsl #2 + 18898: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 1889c: ebf5a9ac bl 0xffd82f54 + 188a0: ea000561 b 0x19e2c + 188a4: 080045c6 stmeqda r0, {r1, r2, r6, r7, r8, sl, lr} + 188a8: 00000000 andeq r0, r0, r0 + 188ac: ebf5adb3 bl 0xffd83f80 + 188b0: 080045c6 stmeqda r0, {r1, r2, r6, r7, r8, sl, lr} + 188b4: e59d041c ldr r0, [sp, #1052] + 188b8: e2800014 add r0, r0, #20 ; 0x14 + 188bc: ebf5ac15 bl 0xffd83918 + 188c0: 080045ca stmeqda r0, {r1, r3, r6, r7, r8, sl, lr} + 188c4: e1a07000 mov r7, r0 + 188c8: ebf5adac bl 0xffd83f80 + 188cc: 080045c8 stmeqda r0, {r3, r6, r7, r8, sl, lr} + 188d0: e59d0434 ldr r0, [sp, #1076] + 188d4: e2800f05 add r0, r0, #20 ; 0x14 + 188d8: e1a01007 mov r1, r7 + 188dc: ebf5ab3a bl 0xffd835cc + 188e0: 080045ca stmeqda r0, {r1, r3, r6, r7, r8, sl, lr} + 188e4: ebf5ada5 bl 0xffd83f80 + 188e8: 080045ca stmeqda r0, {r1, r3, r6, r7, r8, sl, lr} + 188ec: e59d041c ldr r0, [sp, #1052] + 188f0: e2800004 add r0, r0, #4 ; 0x4 + 188f4: ebf5ac07 bl 0xffd83918 + 188f8: 080045ce stmeqda r0, {r1, r2, r3, r6, r7, r8, sl, lr} + 188fc: e1a03000 mov r3, r0 + 18900: ebf5ad9e bl 0xffd83f80 + 18904: 080045cc stmeqda r0, {r2, r3, r6, r7, r8, sl, lr} + 18908: e59d0434 ldr r0, [sp, #1076] + 1890c: e2800f06 add r0, r0, #24 ; 0x18 + 18910: e1a01003 mov r1, r3 + 18914: ebf5ab2c bl 0xffd835cc + 18918: 080045ce stmeqda r0, {r1, r2, r3, r6, r7, r8, sl, lr} + 1891c: ebf5ad97 bl 0xffd83f80 + 18920: 080045ce stmeqda r0, {r1, r2, r3, r6, r7, r8, sl, lr} + 18924: e59d041c ldr r0, [sp, #1052] + 18928: e2800002 add r0, r0, #2 ; 0x2 + 1892c: ebf5abcd bl 0xffd83868 + 18930: 080045d2 stmeqda r0, {r1, r4, r6, r7, r8, sl, lr} + 18934: e1a04000 mov r4, r0 + 18938: ebf5ad90 bl 0xffd83f80 + 1893c: 080045d0 stmeqda r0, {r4, r6, r7, r8, sl, lr} + 18940: e3b03080 movs r3, #128 ; 0x80 + 18944: ebf5ad8d bl 0xffd83f80 + 18948: 080045d2 stmeqda r0, {r1, r4, r6, r7, r8, sl, lr} + 1894c: e1b03383 movs r3, r3, lsl #7 + 18950: ebf5ad8a bl 0xffd83f80 + 18954: 080045d4 stmeqda r0, {r2, r4, r6, r7, r8, sl, lr} + 18958: e1a01003 mov r1, r3 + 1895c: e0133004 ands r3, r3, r4 + 18960: ebf5ad86 bl 0xffd83f80 + 18964: 080045d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, sl, lr} + 18968: e3530000 cmp r3, #0 ; 0x0 + 1896c: ebf5ad83 bl 0xffd83f80 + 18970: 080045d8 stmeqda r0, {r3, r4, r6, r7, r8, sl, lr} + 18974: e28cc026 add ip, ip, #38 ; 0x26 + 18978: 1a000004 bne 0x18990 + 1897c: e1a00fac mov r0, ip, lsr #31 + 18980: e08ff100 add pc, pc, r0, lsl #2 + 18984: 080045f0 stmeqda r0, {r4, r5, r6, r7, r8, sl, lr} + 18988: ebf5a971 bl 0xffd82f54 + 1898c: ea000034 b 0x18a64 + 18990: ebf5ad7a bl 0xffd83f80 + 18994: 080045da stmeqda r0, {r1, r3, r4, r6, r7, r8, sl, lr} + 18998: e3b07005 movs r7, #5 ; 0x5 + 1899c: ebf5ad77 bl 0xffd83f80 + 189a0: 080045dc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl, lr} + 189a4: e59d0434 ldr r0, [sp, #1076] + 189a8: e2800f07 add r0, r0, #28 ; 0x1c + 189ac: e1a01007 mov r1, r7 + 189b0: ebf5ab05 bl 0xffd835cc + 189b4: 080045de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl, lr} + 189b8: ebf5ad70 bl 0xffd83f80 + 189bc: 080045de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl, lr} + 189c0: e3b03080 movs r3, #128 ; 0x80 + 189c4: ebf5ad6d bl 0xffd83f80 + 189c8: 080045e0 stmeqda r0, {r5, r6, r7, r8, sl, lr} + 189cc: e1b03403 movs r3, r3, lsl #8 + 189d0: ebf5ad6a bl 0xffd83f80 + 189d4: 080045e2 stmeqda r0, {r1, r5, r6, r7, r8, sl, lr} + 189d8: e1a01003 mov r1, r3 + 189dc: e0133004 ands r3, r3, r4 + 189e0: ebf5ad66 bl 0xffd83f80 + 189e4: 080045e4 stmeqda r0, {r2, r5, r6, r7, r8, sl, lr} + 189e8: e3b04006 movs r4, #6 ; 0x6 + 189ec: ebf5ad63 bl 0xffd83f80 + 189f0: 080045e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, sl, lr} + 189f4: e59d0434 ldr r0, [sp, #1076] + 189f8: e2800f08 add r0, r0, #32 ; 0x20 + 189fc: e1a01004 mov r1, r4 + 18a00: ebf5aaf1 bl 0xffd835cc + 18a04: 080045e8 stmeqda r0, {r3, r5, r6, r7, r8, sl, lr} + 18a08: ebf5ad5c bl 0xffd83f80 + 18a0c: 080045e8 stmeqda r0, {r3, r5, r6, r7, r8, sl, lr} + 18a10: e3530000 cmp r3, #0 ; 0x0 + 18a14: ebf5ad59 bl 0xffd83f80 + 18a18: 080045ea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, lr} + 18a1c: e28cc01d add ip, ip, #29 ; 0x1d + 18a20: 1a000004 bne 0x18a38 + 18a24: e1a00fac mov r0, ip, lsr #31 + 18a28: e08ff100 add pc, pc, r0, lsl #2 + 18a2c: 08004606 stmeqda r0, {r1, r2, r9, sl, lr} + 18a30: ebf5a947 bl 0xffd82f54 + 18a34: ea000040 b 0x18b3c + 18a38: ebf5ad50 bl 0xffd83f80 + 18a3c: 080045ec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl, lr} + 18a40: e3b07004 movs r7, #4 ; 0x4 + 18a44: ebf5ad4d bl 0xffd83f80 + 18a48: 080045ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, lr} + 18a4c: e28cc006 add ip, ip, #6 ; 0x6 + 18a50: e1a00fac mov r0, ip, lsr #31 + 18a54: e08ff100 add pc, pc, r0, lsl #2 + 18a58: 08004604 stmeqda r0, {r2, r9, sl, lr} + 18a5c: ebf5a93c bl 0xffd82f54 + 18a60: ea00002d b 0x18b1c + 18a64: ebf5ad45 bl 0xffd83f80 + 18a68: 080045f0 stmeqda r0, {r4, r5, r6, r7, r8, sl, lr} + 18a6c: e3b03006 movs r3, #6 ; 0x6 + 18a70: ebf5ad42 bl 0xffd83f80 + 18a74: 080045f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, lr} + 18a78: e59d0434 ldr r0, [sp, #1076] + 18a7c: e2800f07 add r0, r0, #28 ; 0x1c + 18a80: e1a01003 mov r1, r3 + 18a84: ebf5aad0 bl 0xffd835cc + 18a88: 080045f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, lr} + 18a8c: ebf5ad3b bl 0xffd83f80 + 18a90: 080045f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, lr} + 18a94: e3b03080 movs r3, #128 ; 0x80 + 18a98: ebf5ad38 bl 0xffd83f80 + 18a9c: 080045f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, lr} + 18aa0: e1b03403 movs r3, r3, lsl #8 + 18aa4: ebf5ad35 bl 0xffd83f80 + 18aa8: 080045f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, lr} + 18aac: e1a01003 mov r1, r3 + 18ab0: e0133004 ands r3, r3, r4 + 18ab4: ebf5ad31 bl 0xffd83f80 + 18ab8: 080045fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, sl, lr} + 18abc: e3b04006 movs r4, #6 ; 0x6 + 18ac0: ebf5ad2e bl 0xffd83f80 + 18ac4: 080045fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl, lr} + 18ac8: e59d0434 ldr r0, [sp, #1076] + 18acc: e2800f08 add r0, r0, #32 ; 0x20 + 18ad0: e1a01004 mov r1, r4 + 18ad4: ebf5aabc bl 0xffd835cc + 18ad8: 080045fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl, lr} + 18adc: ebf5ad27 bl 0xffd83f80 + 18ae0: 080045fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl, lr} + 18ae4: e3530000 cmp r3, #0 ; 0x0 + 18ae8: ebf5ad24 bl 0xffd83f80 + 18aec: 08004600 stmeqda r0, {r9, sl, lr} + 18af0: e28cc01d add ip, ip, #29 ; 0x1d + 18af4: 1a000004 bne 0x18b0c + 18af8: e1a00fac mov r0, ip, lsr #31 + 18afc: e08ff100 add pc, pc, r0, lsl #2 + 18b00: 08004606 stmeqda r0, {r1, r2, r9, sl, lr} + 18b04: ebf5a912 bl 0xffd82f54 + 18b08: ea00000b b 0x18b3c + 18b0c: ebf5ad1b bl 0xffd83f80 + 18b10: 08004602 stmeqda r0, {r1, r9, sl, lr} + 18b14: e3b07005 movs r7, #5 ; 0x5 + 18b18: e28cc003 add ip, ip, #3 ; 0x3 + 18b1c: ebf5ad17 bl 0xffd83f80 + 18b20: 08004604 stmeqda r0, {r2, r9, sl, lr} + 18b24: e59d0434 ldr r0, [sp, #1076] + 18b28: e2800f08 add r0, r0, #32 ; 0x20 + 18b2c: e1a01007 mov r1, r7 + 18b30: ebf5aaa5 bl 0xffd835cc + 18b34: 08004606 stmeqda r0, {r1, r2, r9, sl, lr} + 18b38: e28cc004 add ip, ip, #4 ; 0x4 + 18b3c: ebf5ad0f bl 0xffd83f80 + 18b40: 08004606 stmeqda r0, {r1, r2, r9, sl, lr} + 18b44: e1a01005 mov r1, r5 + 18b48: e2956000 adds r6, r5, #0 ; 0x0 + 18b4c: ebf5ad0b bl 0xffd83f80 + 18b50: 08004608 stmeqda r0, {r3, r9, sl, lr} + 18b54: e59d041c ldr r0, [sp, #1052] + 18b58: e280000c add r0, r0, #12 ; 0xc + 18b5c: ebf5ab6d bl 0xffd83918 + 18b60: 0800460c stmeqda r0, {r2, r3, r9, sl, lr} + 18b64: e1a03000 mov r3, r0 + 18b68: ebf5ad04 bl 0xffd83f80 + 18b6c: 0800460a stmeqda r0, {r1, r3, r9, sl, lr} + 18b70: e59d0434 ldr r0, [sp, #1076] + 18b74: e2800f0a add r0, r0, #40 ; 0x28 + 18b78: e1a01003 mov r1, r3 + 18b7c: ebf5aa92 bl 0xffd835cc + 18b80: 0800460c stmeqda r0, {r2, r3, r9, sl, lr} + 18b84: ebf5acfd bl 0xffd83f80 + 18b88: 0800460c stmeqda r0, {r2, r3, r9, sl, lr} + 18b8c: e28cc00f add ip, ip, #15 ; 0xf + 18b90: e1a00fac mov r0, ip, lsr #31 + 18b94: e08ff100 add pc, pc, r0, lsl #2 + 18b98: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 18b9c: ebf5a8ec bl 0xffd82f54 + 18ba0: ea000001 b 0x18bac + 18ba4: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 18ba8: 00000000 andeq r0, r0, r0 + 18bac: ebf5acf3 bl 0xffd83f80 + 18bb0: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 18bb4: e59d0434 ldr r0, [sp, #1076] + 18bb8: e2800f15 add r0, r0, #84 ; 0x54 + 18bbc: ebf5ab55 bl 0xffd83918 + 18bc0: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 18bc4: e1a04000 mov r4, r0 + 18bc8: ebf5acec bl 0xffd83f80 + 18bcc: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 18bd0: e1560004 cmp r6, r4 + 18bd4: ebf5ace9 bl 0xffd83f80 + 18bd8: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 18bdc: e28cc00b add ip, ip, #11 ; 0xb + 18be0: da000004 ble 0x18bf8 + 18be4: e1a00fac mov r0, ip, lsr #31 + 18be8: e08ff100 add pc, pc, r0, lsl #2 + 18bec: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 18bf0: ebf5a8d7 bl 0xffd82f54 + 18bf4: ea000007 b 0x18c18 + 18bf8: ebf5ace0 bl 0xffd83f80 + 18bfc: 0800472c stmeqda r0, {r2, r3, r5, r8, r9, sl, lr} + 18c00: e28cc003 add ip, ip, #3 ; 0x3 + 18c04: e1a00fac mov r0, ip, lsr #31 + 18c08: e08ff100 add pc, pc, r0, lsl #2 + 18c0c: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 18c10: ebf5a8cf bl 0xffd82f54 + 18c14: ea000049 b 0x18d40 + 18c18: ebf5acd8 bl 0xffd83f80 + 18c1c: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 18c20: e59d0434 ldr r0, [sp, #1076] + 18c24: e2800f0d add r0, r0, #52 ; 0x34 + 18c28: e58d0434 str r0, [sp, #1076] + 18c2c: ebf5acd3 bl 0xffd83f80 + 18c30: 08004730 stmeqda r0, {r4, r5, r8, r9, sl, lr} + 18c34: e59d9434 ldr r9, [sp, #1076] + 18c38: e3c99003 bic r9, r9, #3 ; 0x3 + 18c3c: e289000c add r0, r9, #12 ; 0xc + 18c40: e58d0434 str r0, [sp, #1076] + 18c44: e2890000 add r0, r9, #0 ; 0x0 + 18c48: ebf5ab32 bl 0xffd83918 + 18c4c: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 18c50: e1a06000 mov r6, r0 + 18c54: e2890004 add r0, r9, #4 ; 0x4 + 18c58: ebf5ab2e bl 0xffd83918 + 18c5c: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 18c60: e1a07000 mov r7, r0 + 18c64: e2890008 add r0, r9, #8 ; 0x8 + 18c68: ebf5ab2a bl 0xffd83918 + 18c6c: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 18c70: e1a08000 mov r8, r0 + 18c74: ebf5acc1 bl 0xffd83f80 + 18c78: 08004732 stmeqda r0, {r1, r4, r5, r8, r9, sl, lr} + 18c7c: e1a00006 mov r0, r6 + 18c80: e58d0420 str r0, [sp, #1056] + 18c84: ebf5acbd bl 0xffd83f80 + 18c88: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 18c8c: e1a00007 mov r0, r7 + 18c90: e58d0424 str r0, [sp, #1060] + 18c94: ebf5acb9 bl 0xffd83f80 + 18c98: 08004736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, lr} + 18c9c: e1a00008 mov r0, r8 + 18ca0: e58d0428 str r0, [sp, #1064] + 18ca4: ebf5acb5 bl 0xffd83f80 + 18ca8: 08004738 stmeqda r0, {r3, r4, r5, r8, r9, sl, lr} + 18cac: e59d9434 ldr r9, [sp, #1076] + 18cb0: e3c99003 bic r9, r9, #3 ; 0x3 + 18cb4: e2890010 add r0, r9, #16 ; 0x10 + 18cb8: e58d0434 str r0, [sp, #1076] + 18cbc: e2890000 add r0, r9, #0 ; 0x0 + 18cc0: ebf5ab14 bl 0xffd83918 + 18cc4: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 18cc8: e1a07000 mov r7, r0 + 18ccc: e2890004 add r0, r9, #4 ; 0x4 + 18cd0: ebf5ab10 bl 0xffd83918 + 18cd4: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 18cd8: e1a08000 mov r8, r0 + 18cdc: e2890008 add r0, r9, #8 ; 0x8 + 18ce0: ebf5ab0c bl 0xffd83918 + 18ce4: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 18ce8: e58d0418 str r0, [sp, #1048] + 18cec: e289000c add r0, r9, #12 ; 0xc + 18cf0: ebf5ab08 bl 0xffd83918 + 18cf4: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 18cf8: e58d041c str r0, [sp, #1052] + 18cfc: ebf5ac9f bl 0xffd83f80 + 18d00: 0800473a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, lr} + 18d04: e59d9434 ldr r9, [sp, #1076] + 18d08: e3c99003 bic r9, r9, #3 ; 0x3 + 18d0c: e2890004 add r0, r9, #4 ; 0x4 + 18d10: e58d0434 str r0, [sp, #1076] + 18d14: e2890000 add r0, r9, #0 ; 0x0 + 18d18: ebf5aafe bl 0xffd83918 + 18d1c: 0800473e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, lr} + 18d20: e1a03000 mov r3, r0 + 18d24: ebf5ac95 bl 0xffd83f80 + 18d28: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 18d2c: e1a00003 mov r0, r3 + 18d30: e28cc020 add ip, ip, #32 ; 0x20 + 18d34: eaf5a8e5 b 0xffd830d0 + 18d38: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 18d3c: 00000000 andeq r0, r0, r0 + 18d40: ebf5ac8e bl 0xffd83f80 + 18d44: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 18d48: e3b05020 movs r5, #32 ; 0x20 + 18d4c: ebf5ac8b bl 0xffd83f80 + 18d50: 08004610 stmeqda r0, {r4, r9, sl, lr} + 18d54: e1a01005 mov r1, r5 + 18d58: e0155006 ands r5, r5, r6 + 18d5c: ebf5ac87 bl 0xffd83f80 + 18d60: 08004612 stmeqda r0, {r1, r4, r9, sl, lr} + 18d64: e59d0434 ldr r0, [sp, #1076] + 18d68: e2800f08 add r0, r0, #32 ; 0x20 + 18d6c: ebf5aae9 bl 0xffd83918 + 18d70: 08004616 stmeqda r0, {r1, r2, r4, r9, sl, lr} + 18d74: e1a07000 mov r7, r0 + 18d78: ebf5ac80 bl 0xffd83f80 + 18d7c: 08004614 stmeqda r0, {r2, r4, r9, sl, lr} + 18d80: e1b05755 movs r5, r5, asr r7 + 18d84: ebf5ac7d bl 0xffd83f80 + 18d88: 08004616 stmeqda r0, {r1, r2, r4, r9, sl, lr} + 18d8c: e59d0434 ldr r0, [sp, #1076] + 18d90: e2800f09 add r0, r0, #36 ; 0x24 + 18d94: e1a01005 mov r1, r5 + 18d98: ebf5aa0b bl 0xffd835cc + 18d9c: 08004618 stmeqda r0, {r3, r4, r9, sl, lr} + 18da0: ebf5ac76 bl 0xffd83f80 + 18da4: 08004618 stmeqda r0, {r3, r4, r9, sl, lr} + 18da8: e1b05146 movs r5, r6, asr #2 + 18dac: ebf5ac73 bl 0xffd83f80 + 18db0: 0800461a stmeqda r0, {r1, r3, r4, r9, sl, lr} + 18db4: e59d041c ldr r0, [sp, #1052] + 18db8: e2800000 add r0, r0, #0 ; 0x0 + 18dbc: ebf5aaa9 bl 0xffd83868 + 18dc0: 0800461e stmeqda r0, {r1, r2, r3, r4, r9, sl, lr} + 18dc4: e1a03000 mov r3, r0 + 18dc8: ebf5ac6c bl 0xffd83f80 + 18dcc: 0800461c stmeqda r0, {r2, r3, r4, r9, sl, lr} + 18dd0: e3b07080 movs r7, #128 ; 0x80 + 18dd4: ebf5ac69 bl 0xffd83f80 + 18dd8: 0800461e stmeqda r0, {r1, r2, r3, r4, r9, sl, lr} + 18ddc: e1b07107 movs r7, r7, lsl #2 + 18de0: ebf5ac66 bl 0xffd83f80 + 18de4: 08004620 stmeqda r0, {r5, r9, sl, lr} + 18de8: e1a01007 mov r1, r7 + 18dec: e2974000 adds r4, r7, #0 ; 0x0 + 18df0: ebf5ac62 bl 0xffd83f80 + 18df4: 08004622 stmeqda r0, {r1, r5, r9, sl, lr} + 18df8: e1a01003 mov r1, r3 + 18dfc: e0133004 ands r3, r3, r4 + 18e00: ebf5ac5e bl 0xffd83f80 + 18e04: 08004624 stmeqda r0, {r2, r5, r9, sl, lr} + 18e08: e3530000 cmp r3, #0 ; 0x0 + 18e0c: ebf5ac5b bl 0xffd83f80 + 18e10: 08004626 stmeqda r0, {r1, r2, r5, r9, sl, lr} + 18e14: e28cc02c add ip, ip, #44 ; 0x2c + 18e18: 1a000004 bne 0x18e30 + 18e1c: e1a00fac mov r0, ip, lsr #31 + 18e20: e08ff100 add pc, pc, r0, lsl #2 + 18e24: 08004646 stmeqda r0, {r1, r2, r6, r9, sl, lr} + 18e28: ebf5a849 bl 0xffd82f54 + 18e2c: ea000028 b 0x18ed4 + 18e30: ebf5ac52 bl 0xffd83f80 + 18e34: 08004628 stmeqda r0, {r3, r5, r9, sl, lr} + 18e38: e3b03012 movs r3, #18 ; 0x12 + 18e3c: ebf5ac4f bl 0xffd83f80 + 18e40: 0800462a stmeqda r0, {r1, r3, r5, r9, sl, lr} + 18e44: e59d041c ldr r0, [sp, #1052] + 18e48: e0800003 add r0, r0, r3 + 18e4c: ebf5aa9a bl 0xffd838bc + 18e50: 0800462e stmeqda r0, {r1, r2, r3, r5, r9, sl, lr} + 18e54: e1a07000 mov r7, r0 + 18e58: ebf5ac48 bl 0xffd83f80 + 18e5c: 0800462c stmeqda r0, {r2, r3, r5, r9, sl, lr} + 18e60: e1a01005 mov r1, r5 + 18e64: e2953000 adds r3, r5, #0 ; 0x0 + 18e68: ebf5ac44 bl 0xffd83f80 + 18e6c: 0800462e stmeqda r0, {r1, r2, r3, r5, r9, sl, lr} + 18e70: e1a01007 mov r1, r7 + 18e74: e2974000 adds r4, r7, #0 ; 0x0 + 18e78: ebf5ac40 bl 0xffd83f80 + 18e7c: 08004630 stmeqda r0, {r4, r5, r9, sl, lr} + 18e80: e59d0434 ldr r0, [sp, #1076] + 18e84: e2800f0c add r0, r0, #48 ; 0x30 + 18e88: e1a01006 mov r1, r6 + 18e8c: ebf5a9ce bl 0xffd835cc + 18e90: 08004632 stmeqda r0, {r1, r4, r5, r9, sl, lr} + 18e94: ebf5ac39 bl 0xffd83f80 + 18e98: 08004632 stmeqda r0, {r1, r4, r5, r9, sl, lr} + 18e9c: ebf5ac37 bl 0xffd83f80 + 18ea0: 08004634 stmeqda r0, {r2, r4, r5, r9, sl, lr} + 18ea4: e3a00037 mov r0, #55 ; 0x37 + 18ea8: e3800c46 orr r0, r0, #17920 ; 0x4600 + 18eac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 18eb0: e58d0438 str r0, [sp, #1080] + 18eb4: e28cc018 add ip, ip, #24 ; 0x18 + 18eb8: e1a00fac mov r0, ip, lsr #31 + 18ebc: e08ff100 add pc, pc, r0, lsl #2 + 18ec0: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 18ec4: ebf5a822 bl 0xffd82f54 + 18ec8: ea0003d7 b 0x19e2c + 18ecc: 08004646 stmeqda r0, {r1, r2, r6, r9, sl, lr} + 18ed0: 00000000 andeq r0, r0, r0 + 18ed4: ebf5ac29 bl 0xffd83f80 + 18ed8: 08004646 stmeqda r0, {r1, r2, r6, r9, sl, lr} + 18edc: e3b07000 movs r7, #0 ; 0x0 + 18ee0: ebf5ac26 bl 0xffd83f80 + 18ee4: 08004648 stmeqda r0, {r3, r6, r9, sl, lr} + 18ee8: e1a00007 mov r0, r7 + 18eec: e58d0428 str r0, [sp, #1064] + 18ef0: ebf5ac22 bl 0xffd83f80 + 18ef4: 0800464a stmeqda r0, {r1, r3, r6, r9, sl, lr} + 18ef8: e3550000 cmp r5, #0 ; 0x0 + 18efc: ebf5ac1f bl 0xffd83f80 + 18f00: 0800464c stmeqda r0, {r2, r3, r6, r9, sl, lr} + 18f04: e28cc00c add ip, ip, #12 ; 0xc + 18f08: aa000004 bge 0x18f20 + 18f0c: e1a00fac mov r0, ip, lsr #31 + 18f10: e08ff100 add pc, pc, r0, lsl #2 + 18f14: 0800465a stmeqda r0, {r1, r3, r4, r6, r9, sl, lr} + 18f18: ebf5a80d bl 0xffd82f54 + 18f1c: ea00001d b 0x18f98 + 18f20: ebf5ac16 bl 0xffd83f80 + 18f24: 0800464e stmeqda r0, {r1, r2, r3, r6, r9, sl, lr} + 18f28: e3b04012 movs r4, #18 ; 0x12 + 18f2c: ebf5ac13 bl 0xffd83f80 + 18f30: 08004650 stmeqda r0, {r4, r6, r9, sl, lr} + 18f34: e59d041c ldr r0, [sp, #1052] + 18f38: e0800004 add r0, r0, r4 + 18f3c: ebf5aa5e bl 0xffd838bc + 18f40: 08004654 stmeqda r0, {r2, r4, r6, r9, sl, lr} + 18f44: e1a03000 mov r3, r0 + 18f48: ebf5ac0c bl 0xffd83f80 + 18f4c: 08004652 stmeqda r0, {r1, r4, r6, r9, sl, lr} + 18f50: e1550003 cmp r5, r3 + 18f54: ebf5ac09 bl 0xffd83f80 + 18f58: 08004654 stmeqda r0, {r2, r4, r6, r9, sl, lr} + 18f5c: e28cc00e add ip, ip, #14 ; 0xe + 18f60: ba000004 blt 0x18f78 + 18f64: e1a00fac mov r0, ip, lsr #31 + 18f68: e08ff100 add pc, pc, r0, lsl #2 + 18f6c: 0800465a stmeqda r0, {r1, r3, r4, r6, r9, sl, lr} + 18f70: ebf5a7f7 bl 0xffd82f54 + 18f74: ea000007 b 0x18f98 + 18f78: ebf5ac00 bl 0xffd83f80 + 18f7c: 08004656 stmeqda r0, {r1, r2, r4, r6, r9, sl, lr} + 18f80: e3b07001 movs r7, #1 ; 0x1 + 18f84: ebf5abfd bl 0xffd83f80 + 18f88: 08004658 stmeqda r0, {r3, r4, r6, r9, sl, lr} + 18f8c: e1a00007 mov r0, r7 + 18f90: e58d0428 str r0, [sp, #1064] + 18f94: e28cc006 add ip, ip, #6 ; 0x6 + 18f98: ebf5abf8 bl 0xffd83f80 + 18f9c: 0800465a stmeqda r0, {r1, r3, r4, r6, r9, sl, lr} + 18fa0: e3b04010 movs r4, #16 ; 0x10 + 18fa4: ebf5abf5 bl 0xffd83f80 + 18fa8: 0800465c stmeqda r0, {r2, r3, r4, r6, r9, sl, lr} + 18fac: e59d041c ldr r0, [sp, #1052] + 18fb0: e0800004 add r0, r0, r4 + 18fb4: ebf5aa40 bl 0xffd838bc + 18fb8: 08004660 stmeqda r0, {r5, r6, r9, sl, lr} + 18fbc: e1a03000 mov r3, r0 + 18fc0: ebf5abee bl 0xffd83f80 + 18fc4: 0800465e stmeqda r0, {r1, r2, r3, r4, r6, r9, sl, lr} + 18fc8: e1a01003 mov r1, r3 + 18fcc: e0130593 muls r3, r3, r5 + 18fd0: ebf5abea bl 0xffd83f80 + 18fd4: 08004660 stmeqda r0, {r5, r6, r9, sl, lr} + 18fd8: e1b03083 movs r3, r3, lsl #1 + 18fdc: ebf5abe7 bl 0xffd83f80 + 18fe0: 08004662 stmeqda r0, {r1, r5, r6, r9, sl, lr} + 18fe4: e59d0434 ldr r0, [sp, #1076] + 18fe8: e2800f0a add r0, r0, #40 ; 0x28 + 18fec: ebf5aa49 bl 0xffd83918 + 18ff0: 08004666 stmeqda r0, {r1, r2, r5, r6, r9, sl, lr} + 18ff4: e1a05000 mov r5, r0 + 18ff8: ebf5abe0 bl 0xffd83f80 + 18ffc: 08004664 stmeqda r0, {r2, r5, r6, r9, sl, lr} + 19000: e1a01005 mov r1, r5 + 19004: e0955003 adds r5, r5, r3 + 19008: ebf5abdc bl 0xffd83f80 + 1900c: 08004666 stmeqda r0, {r1, r2, r5, r6, r9, sl, lr} + 19010: e1a00005 mov r0, r5 + 19014: e58d0420 str r0, [sp, #1056] + 19018: ebf5abd8 bl 0xffd83f80 + 1901c: 08004668 stmeqda r0, {r3, r5, r6, r9, sl, lr} + 19020: e1a01006 mov r1, r6 + 19024: e2965000 adds r5, r6, #0 ; 0x0 + 19028: ebf5abd4 bl 0xffd83f80 + 1902c: 0800466a stmeqda r0, {r1, r3, r5, r6, r9, sl, lr} + 19030: e3b07003 movs r7, #3 ; 0x3 + 19034: ebf5abd1 bl 0xffd83f80 + 19038: 0800466c stmeqda r0, {r2, r3, r5, r6, r9, sl, lr} + 1903c: e1a01005 mov r1, r5 + 19040: e0155007 ands r5, r5, r7 + 19044: ebf5abcd bl 0xffd83f80 + 19048: 0800466e stmeqda r0, {r1, r2, r3, r5, r6, r9, sl, lr} + 1904c: e59d0434 ldr r0, [sp, #1076] + 19050: e2800f00 add r0, r0, #0 ; 0x0 + 19054: ebf5aa2f bl 0xffd83918 + 19058: 08004672 stmeqda r0, {r1, r4, r5, r6, r9, sl, lr} + 1905c: e1a08000 mov r8, r0 + 19060: ebf5abc6 bl 0xffd83f80 + 19064: 08004670 stmeqda r0, {r4, r5, r6, r9, sl, lr} + 19068: e1a01006 mov r1, r6 + 1906c: e2963001 adds r3, r6, #1 ; 0x1 + 19070: ebf5abc2 bl 0xffd83f80 + 19074: 08004672 stmeqda r0, {r1, r4, r5, r6, r9, sl, lr} + 19078: e59d0434 ldr r0, [sp, #1076] + 1907c: e2800f0b add r0, r0, #44 ; 0x2c + 19080: e1a01003 mov r1, r3 + 19084: ebf5a950 bl 0xffd835cc + 19088: 08004674 stmeqda r0, {r2, r4, r5, r6, r9, sl, lr} + 1908c: ebf5abbb bl 0xffd83f80 + 19090: 08004674 stmeqda r0, {r2, r4, r5, r6, r9, sl, lr} + 19094: e59d0434 ldr r0, [sp, #1076] + 19098: e2800f01 add r0, r0, #4 ; 0x4 + 1909c: ebf5aa1d bl 0xffd83918 + 190a0: 08004678 stmeqda r0, {r3, r4, r5, r6, r9, sl, lr} + 190a4: e1a04000 mov r4, r0 + 190a8: ebf5abb4 bl 0xffd83f80 + 190ac: 08004676 stmeqda r0, {r1, r2, r4, r5, r6, r9, sl, lr} + 190b0: e1580004 cmp r8, r4 + 190b4: ebf5abb1 bl 0xffd83f80 + 190b8: 08004678 stmeqda r0, {r3, r4, r5, r6, r9, sl, lr} + 190bc: e28cc039 add ip, ip, #57 ; 0x39 + 190c0: da000004 ble 0x190d8 + 190c4: e1a00fac mov r0, ip, lsr #31 + 190c8: e08ff100 add pc, pc, r0, lsl #2 + 190cc: 08004724 stmeqda r0, {r2, r5, r8, r9, sl, lr} + 190d0: ebf5a79f bl 0xffd82f54 + 190d4: ea0000be b 0x193d4 + 190d8: ebf5aba8 bl 0xffd83f80 + 190dc: 0800467a stmeqda r0, {r1, r3, r4, r5, r6, r9, sl, lr} + 190e0: e1b05185 movs r5, r5, lsl #3 + 190e4: ebf5aba5 bl 0xffd83f80 + 190e8: 0800467c stmeqda r0, {r2, r3, r4, r5, r6, r9, sl, lr} + 190ec: e1a00005 mov r0, r5 + 190f0: e58d0424 str r0, [sp, #1060] + 190f4: ebf5aba1 bl 0xffd83f80 + 190f8: 0800467e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, lr} + 190fc: e3b04020 movs r4, #32 ; 0x20 + 19100: ebf5ab9e bl 0xffd83f80 + 19104: 08004680 stmeqda r0, {r7, r9, sl, lr} + 19108: e1a01004 mov r1, r4 + 1910c: e0144008 ands r4, r4, r8 + 19110: ebf5ab9a bl 0xffd83f80 + 19114: 08004682 stmeqda r0, {r1, r7, r9, sl, lr} + 19118: e59d0434 ldr r0, [sp, #1076] + 1911c: e2800f07 add r0, r0, #28 ; 0x1c + 19120: ebf5a9fc bl 0xffd83918 + 19124: 08004686 stmeqda r0, {r1, r2, r7, r9, sl, lr} + 19128: e1a05000 mov r5, r0 + 1912c: ebf5ab93 bl 0xffd83f80 + 19130: 08004684 stmeqda r0, {r2, r7, r9, sl, lr} + 19134: e1b04554 movs r4, r4, asr r5 + 19138: ebf5ab90 bl 0xffd83f80 + 1913c: 08004686 stmeqda r0, {r1, r2, r7, r9, sl, lr} + 19140: e59d0434 ldr r0, [sp, #1076] + 19144: e2800f09 add r0, r0, #36 ; 0x24 + 19148: ebf5a9f2 bl 0xffd83918 + 1914c: 0800468a stmeqda r0, {r1, r3, r7, r9, sl, lr} + 19150: e1a07000 mov r7, r0 + 19154: ebf5ab89 bl 0xffd83f80 + 19158: 08004688 stmeqda r0, {r3, r7, r9, sl, lr} + 1915c: e1a01007 mov r1, r7 + 19160: e0974004 adds r4, r7, r4 + 19164: ebf5ab85 bl 0xffd83f80 + 19168: 0800468a stmeqda r0, {r1, r3, r7, r9, sl, lr} + 1916c: e1b04584 movs r4, r4, lsl #11 + 19170: ebf5ab82 bl 0xffd83f80 + 19174: 0800468c stmeqda r0, {r2, r3, r7, r9, sl, lr} + 19178: e59d0434 ldr r0, [sp, #1076] + 1917c: e2800f05 add r0, r0, #20 ; 0x14 + 19180: ebf5a9e4 bl 0xffd83918 + 19184: 08004690 stmeqda r0, {r4, r7, r9, sl, lr} + 19188: e1a03000 mov r3, r0 + 1918c: ebf5ab7b bl 0xffd83f80 + 19190: 0800468e stmeqda r0, {r1, r2, r3, r7, r9, sl, lr} + 19194: e1a01003 mov r1, r3 + 19198: e0934004 adds r4, r3, r4 + 1919c: ebf5ab77 bl 0xffd83f80 + 191a0: 08004690 stmeqda r0, {r4, r7, r9, sl, lr} + 191a4: e3b0501f movs r5, #31 ; 0x1f + 191a8: ebf5ab74 bl 0xffd83f80 + 191ac: 08004692 stmeqda r0, {r1, r4, r7, r9, sl, lr} + 191b0: e1a01006 mov r1, r6 + 191b4: e2963000 adds r3, r6, #0 ; 0x0 + 191b8: ebf5ab70 bl 0xffd83f80 + 191bc: 08004694 stmeqda r0, {r2, r4, r7, r9, sl, lr} + 191c0: e1a01003 mov r1, r3 + 191c4: e0133005 ands r3, r3, r5 + 191c8: ebf5ab6c bl 0xffd83f80 + 191cc: 08004696 stmeqda r0, {r1, r2, r4, r7, r9, sl, lr} + 191d0: e1b03303 movs r3, r3, lsl #6 + 191d4: ebf5ab69 bl 0xffd83f80 + 191d8: 08004698 stmeqda r0, {r3, r4, r7, r9, sl, lr} + 191dc: e1a01004 mov r1, r4 + 191e0: e0944003 adds r4, r4, r3 + 191e4: ebf5ab65 bl 0xffd83f80 + 191e8: 0800469a stmeqda r0, {r1, r3, r4, r7, r9, sl, lr} + 191ec: e1a01008 mov r1, r8 + 191f0: e2983000 adds r3, r8, #0 ; 0x0 + 191f4: ebf5ab61 bl 0xffd83f80 + 191f8: 0800469c stmeqda r0, {r2, r3, r4, r7, r9, sl, lr} + 191fc: e1a01003 mov r1, r3 + 19200: e0133005 ands r3, r3, r5 + 19204: ebf5ab5d bl 0xffd83f80 + 19208: 0800469e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, lr} + 1920c: e1b03083 movs r3, r3, lsl #1 + 19210: ebf5ab5a bl 0xffd83f80 + 19214: 080046a0 stmeqda r0, {r5, r7, r9, sl, lr} + 19218: e1a01004 mov r1, r4 + 1921c: e0940003 adds r0, r4, r3 + 19220: e58d0418 str r0, [sp, #1048] + 19224: ebf5ab55 bl 0xffd83f80 + 19228: 080046a2 stmeqda r0, {r1, r5, r7, r9, sl, lr} + 1922c: e59d1428 ldr r1, [sp, #1064] + 19230: e1a04001 mov r4, r1 + 19234: ebf5ab51 bl 0xffd83f80 + 19238: 080046a4 stmeqda r0, {r2, r5, r7, r9, sl, lr} + 1923c: e3540000 cmp r4, #0 ; 0x0 + 19240: ebf5ab4e bl 0xffd83f80 + 19244: 080046a6 stmeqda r0, {r1, r2, r5, r7, r9, sl, lr} + 19248: e28cc04b add ip, ip, #75 ; 0x4b + 1924c: 0a000004 beq 0x19264 + 19250: e1a00fac mov r0, ip, lsr #31 + 19254: e08ff100 add pc, pc, r0, lsl #2 + 19258: 080046ac stmeqda r0, {r2, r3, r5, r7, r9, sl, lr} + 1925c: ebf5a73c bl 0xffd82f54 + 19260: ea00000e b 0x192a0 + 19264: ebf5ab45 bl 0xffd83f80 + 19268: 080046a8 stmeqda r0, {r3, r5, r7, r9, sl, lr} + 1926c: e59d0418 ldr r0, [sp, #1048] + 19270: e2800000 add r0, r0, #0 ; 0x0 + 19274: e1a01004 mov r1, r4 + 19278: ebf5a8b3 bl 0xffd8354c + 1927c: 080046aa stmeqda r0, {r1, r3, r5, r7, r9, sl, lr} + 19280: ebf5ab3e bl 0xffd83f80 + 19284: 080046aa stmeqda r0, {r1, r3, r5, r7, r9, sl, lr} + 19288: e28cc007 add ip, ip, #7 ; 0x7 + 1928c: e1a00fac mov r0, ip, lsr #31 + 19290: e08ff100 add pc, pc, r0, lsl #2 + 19294: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 19298: ebf5a72d bl 0xffd82f54 + 1929c: ea0000b8 b 0x19584 + 192a0: ebf5ab36 bl 0xffd83f80 + 192a4: 080046ac stmeqda r0, {r2, r3, r5, r7, r9, sl, lr} + 192a8: e1b05148 movs r5, r8, asr #2 + 192ac: ebf5ab33 bl 0xffd83f80 + 192b0: 080046ae stmeqda r0, {r1, r2, r3, r5, r7, r9, sl, lr} + 192b4: e59d041c ldr r0, [sp, #1052] + 192b8: e2800000 add r0, r0, #0 ; 0x0 + 192bc: ebf5a969 bl 0xffd83868 + 192c0: 080046b2 stmeqda r0, {r1, r4, r5, r7, r9, sl, lr} + 192c4: e1a03000 mov r3, r0 + 192c8: ebf5ab2c bl 0xffd83f80 + 192cc: 080046b0 stmeqda r0, {r4, r5, r7, r9, sl, lr} + 192d0: e3b07080 movs r7, #128 ; 0x80 + 192d4: ebf5ab29 bl 0xffd83f80 + 192d8: 080046b2 stmeqda r0, {r1, r4, r5, r7, r9, sl, lr} + 192dc: e1b07187 movs r7, r7, lsl #3 + 192e0: ebf5ab26 bl 0xffd83f80 + 192e4: 080046b4 stmeqda r0, {r2, r4, r5, r7, r9, sl, lr} + 192e8: e1a01007 mov r1, r7 + 192ec: e2974000 adds r4, r7, #0 ; 0x0 + 192f0: ebf5ab22 bl 0xffd83f80 + 192f4: 080046b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sl, lr} + 192f8: e1a01003 mov r1, r3 + 192fc: e0133004 ands r3, r3, r4 + 19300: ebf5ab1e bl 0xffd83f80 + 19304: 080046b8 stmeqda r0, {r3, r4, r5, r7, r9, sl, lr} + 19308: e3530000 cmp r3, #0 ; 0x0 + 1930c: ebf5ab1b bl 0xffd83f80 + 19310: 080046ba stmeqda r0, {r1, r3, r4, r5, r7, r9, sl, lr} + 19314: e28cc01a add ip, ip, #26 ; 0x1a + 19318: 1a000004 bne 0x19330 + 1931c: e1a00fac mov r0, ip, lsr #31 + 19320: e08ff100 add pc, pc, r0, lsl #2 + 19324: 080046f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, lr} + 19328: ebf5a709 bl 0xffd82f54 + 1932c: ea0001cf b 0x19a70 + 19330: ebf5ab12 bl 0xffd83f80 + 19334: 080046bc stmeqda r0, {r2, r3, r4, r5, r7, r9, sl, lr} + 19338: e3b03010 movs r3, #16 ; 0x10 + 1933c: ebf5ab0f bl 0xffd83f80 + 19340: 080046be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sl, lr} + 19344: e59d041c ldr r0, [sp, #1052] + 19348: e0800003 add r0, r0, r3 + 1934c: ebf5a95a bl 0xffd838bc + 19350: 080046c2 stmeqda r0, {r1, r6, r7, r9, sl, lr} + 19354: e1a07000 mov r7, r0 + 19358: ebf5ab08 bl 0xffd83f80 + 1935c: 080046c0 stmeqda r0, {r6, r7, r9, sl, lr} + 19360: e1a01005 mov r1, r5 + 19364: e2953000 adds r3, r5, #0 ; 0x0 + 19368: ebf5ab04 bl 0xffd83f80 + 1936c: 080046c2 stmeqda r0, {r1, r6, r7, r9, sl, lr} + 19370: e1a01007 mov r1, r7 + 19374: e2974000 adds r4, r7, #0 ; 0x0 + 19378: ebf5ab00 bl 0xffd83f80 + 1937c: 080046c4 stmeqda r0, {r2, r6, r7, r9, sl, lr} + 19380: e59d0434 ldr r0, [sp, #1076] + 19384: e2800f0c add r0, r0, #48 ; 0x30 + 19388: e1a01006 mov r1, r6 + 1938c: ebf5a88e bl 0xffd835cc + 19390: 080046c6 stmeqda r0, {r1, r2, r6, r7, r9, sl, lr} + 19394: ebf5aaf9 bl 0xffd83f80 + 19398: 080046c6 stmeqda r0, {r1, r2, r6, r7, r9, sl, lr} + 1939c: ebf5aaf7 bl 0xffd83f80 + 193a0: 080046c8 stmeqda r0, {r3, r6, r7, r9, sl, lr} + 193a4: e3a000cb mov r0, #203 ; 0xcb + 193a8: e3800c46 orr r0, r0, #17920 ; 0x4600 + 193ac: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 193b0: e58d0438 str r0, [sp, #1080] + 193b4: e28cc018 add ip, ip, #24 ; 0x18 + 193b8: e1a00fac mov r0, ip, lsr #31 + 193bc: e08ff100 add pc, pc, r0, lsl #2 + 193c0: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 193c4: ebf5a6e2 bl 0xffd82f54 + 193c8: ea000297 b 0x19e2c + 193cc: 08004724 stmeqda r0, {r2, r5, r8, r9, sl, lr} + 193d0: 00000000 andeq r0, r0, r0 + 193d4: ebf5aae9 bl 0xffd83f80 + 193d8: 08004724 stmeqda r0, {r2, r5, r8, r9, sl, lr} + 193dc: e59d0434 ldr r0, [sp, #1076] + 193e0: e2800f0b add r0, r0, #44 ; 0x2c + 193e4: ebf5a94b bl 0xffd83918 + 193e8: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 193ec: e1a06000 mov r6, r0 + 193f0: ebf5aae2 bl 0xffd83f80 + 193f4: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 193f8: e59d0434 ldr r0, [sp, #1076] + 193fc: e2800f15 add r0, r0, #84 ; 0x54 + 19400: ebf5a944 bl 0xffd83918 + 19404: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 19408: e1a04000 mov r4, r0 + 1940c: ebf5aadb bl 0xffd83f80 + 19410: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 19414: e1560004 cmp r6, r4 + 19418: ebf5aad8 bl 0xffd83f80 + 1941c: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 19420: e28cc010 add ip, ip, #16 ; 0x10 + 19424: da000004 ble 0x1943c + 19428: e1a00fac mov r0, ip, lsr #31 + 1942c: e08ff100 add pc, pc, r0, lsl #2 + 19430: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19434: ebf5a6c6 bl 0xffd82f54 + 19438: ea000007 b 0x1945c + 1943c: ebf5aacf bl 0xffd83f80 + 19440: 0800472c stmeqda r0, {r2, r3, r5, r8, r9, sl, lr} + 19444: e28cc003 add ip, ip, #3 ; 0x3 + 19448: e1a00fac mov r0, ip, lsr #31 + 1944c: e08ff100 add pc, pc, r0, lsl #2 + 19450: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 19454: ebf5a6be bl 0xffd82f54 + 19458: eafffe38 b 0x18d40 + 1945c: ebf5aac7 bl 0xffd83f80 + 19460: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19464: e59d0434 ldr r0, [sp, #1076] + 19468: e2800f0d add r0, r0, #52 ; 0x34 + 1946c: e58d0434 str r0, [sp, #1076] + 19470: ebf5aac2 bl 0xffd83f80 + 19474: 08004730 stmeqda r0, {r4, r5, r8, r9, sl, lr} + 19478: e59d9434 ldr r9, [sp, #1076] + 1947c: e3c99003 bic r9, r9, #3 ; 0x3 + 19480: e289000c add r0, r9, #12 ; 0xc + 19484: e58d0434 str r0, [sp, #1076] + 19488: e2890000 add r0, r9, #0 ; 0x0 + 1948c: ebf5a921 bl 0xffd83918 + 19490: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 19494: e1a06000 mov r6, r0 + 19498: e2890004 add r0, r9, #4 ; 0x4 + 1949c: ebf5a91d bl 0xffd83918 + 194a0: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 194a4: e1a07000 mov r7, r0 + 194a8: e2890008 add r0, r9, #8 ; 0x8 + 194ac: ebf5a919 bl 0xffd83918 + 194b0: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 194b4: e1a08000 mov r8, r0 + 194b8: ebf5aab0 bl 0xffd83f80 + 194bc: 08004732 stmeqda r0, {r1, r4, r5, r8, r9, sl, lr} + 194c0: e1a00006 mov r0, r6 + 194c4: e58d0420 str r0, [sp, #1056] + 194c8: ebf5aaac bl 0xffd83f80 + 194cc: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 194d0: e1a00007 mov r0, r7 + 194d4: e58d0424 str r0, [sp, #1060] + 194d8: ebf5aaa8 bl 0xffd83f80 + 194dc: 08004736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, lr} + 194e0: e1a00008 mov r0, r8 + 194e4: e58d0428 str r0, [sp, #1064] + 194e8: ebf5aaa4 bl 0xffd83f80 + 194ec: 08004738 stmeqda r0, {r3, r4, r5, r8, r9, sl, lr} + 194f0: e59d9434 ldr r9, [sp, #1076] + 194f4: e3c99003 bic r9, r9, #3 ; 0x3 + 194f8: e2890010 add r0, r9, #16 ; 0x10 + 194fc: e58d0434 str r0, [sp, #1076] + 19500: e2890000 add r0, r9, #0 ; 0x0 + 19504: ebf5a903 bl 0xffd83918 + 19508: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1950c: e1a07000 mov r7, r0 + 19510: e2890004 add r0, r9, #4 ; 0x4 + 19514: ebf5a8ff bl 0xffd83918 + 19518: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1951c: e1a08000 mov r8, r0 + 19520: e2890008 add r0, r9, #8 ; 0x8 + 19524: ebf5a8fb bl 0xffd83918 + 19528: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1952c: e58d0418 str r0, [sp, #1048] + 19530: e289000c add r0, r9, #12 ; 0xc + 19534: ebf5a8f7 bl 0xffd83918 + 19538: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1953c: e58d041c str r0, [sp, #1052] + 19540: ebf5aa8e bl 0xffd83f80 + 19544: 0800473a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, lr} + 19548: e59d9434 ldr r9, [sp, #1076] + 1954c: e3c99003 bic r9, r9, #3 ; 0x3 + 19550: e2890004 add r0, r9, #4 ; 0x4 + 19554: e58d0434 str r0, [sp, #1076] + 19558: e2890000 add r0, r9, #0 ; 0x0 + 1955c: ebf5a8ed bl 0xffd83918 + 19560: 0800473e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, lr} + 19564: e1a03000 mov r3, r0 + 19568: ebf5aa84 bl 0xffd83f80 + 1956c: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19570: e1a00003 mov r0, r3 + 19574: e28cc020 add ip, ip, #32 ; 0x20 + 19578: eaf5a6d4 b 0xffd830d0 + 1957c: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 19580: 00000000 andeq r0, r0, r0 + 19584: ebf5aa7d bl 0xffd83f80 + 19588: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 1958c: e1a01008 mov r1, r8 + 19590: e2988001 adds r8, r8, #1 ; 0x1 + 19594: ebf5aa79 bl 0xffd83f80 + 19598: 0800471e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, lr} + 1959c: e59d0434 ldr r0, [sp, #1076] + 195a0: e2800f01 add r0, r0, #4 ; 0x4 + 195a4: ebf5a8db bl 0xffd83918 + 195a8: 08004722 stmeqda r0, {r1, r5, r8, r9, sl, lr} + 195ac: e1a03000 mov r3, r0 + 195b0: ebf5aa72 bl 0xffd83f80 + 195b4: 08004720 stmeqda r0, {r5, r8, r9, sl, lr} + 195b8: e1580003 cmp r8, r3 + 195bc: ebf5aa6f bl 0xffd83f80 + 195c0: 08004722 stmeqda r0, {r1, r5, r8, r9, sl, lr} + 195c4: e28cc00e add ip, ip, #14 ; 0xe + 195c8: ca000004 bgt 0x195e0 + 195cc: e1a00fac mov r0, ip, lsr #31 + 195d0: e08ff100 add pc, pc, r0, lsl #2 + 195d4: 0800467e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, lr} + 195d8: ebf5a65d bl 0xffd82f54 + 195dc: ea00006b b 0x19790 + 195e0: ebf5aa66 bl 0xffd83f80 + 195e4: 08004724 stmeqda r0, {r2, r5, r8, r9, sl, lr} + 195e8: e59d0434 ldr r0, [sp, #1076] + 195ec: e2800f0b add r0, r0, #44 ; 0x2c + 195f0: ebf5a8c8 bl 0xffd83918 + 195f4: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 195f8: e1a06000 mov r6, r0 + 195fc: ebf5aa5f bl 0xffd83f80 + 19600: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 19604: e59d0434 ldr r0, [sp, #1076] + 19608: e2800f15 add r0, r0, #84 ; 0x54 + 1960c: ebf5a8c1 bl 0xffd83918 + 19610: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 19614: e1a04000 mov r4, r0 + 19618: ebf5aa58 bl 0xffd83f80 + 1961c: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 19620: e1560004 cmp r6, r4 + 19624: ebf5aa55 bl 0xffd83f80 + 19628: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 1962c: e28cc010 add ip, ip, #16 ; 0x10 + 19630: da000004 ble 0x19648 + 19634: e1a00fac mov r0, ip, lsr #31 + 19638: e08ff100 add pc, pc, r0, lsl #2 + 1963c: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19640: ebf5a643 bl 0xffd82f54 + 19644: ea000007 b 0x19668 + 19648: ebf5aa4c bl 0xffd83f80 + 1964c: 0800472c stmeqda r0, {r2, r3, r5, r8, r9, sl, lr} + 19650: e28cc003 add ip, ip, #3 ; 0x3 + 19654: e1a00fac mov r0, ip, lsr #31 + 19658: e08ff100 add pc, pc, r0, lsl #2 + 1965c: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 19660: ebf5a63b bl 0xffd82f54 + 19664: eafffdb5 b 0x18d40 + 19668: ebf5aa44 bl 0xffd83f80 + 1966c: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19670: e59d0434 ldr r0, [sp, #1076] + 19674: e2800f0d add r0, r0, #52 ; 0x34 + 19678: e58d0434 str r0, [sp, #1076] + 1967c: ebf5aa3f bl 0xffd83f80 + 19680: 08004730 stmeqda r0, {r4, r5, r8, r9, sl, lr} + 19684: e59d9434 ldr r9, [sp, #1076] + 19688: e3c99003 bic r9, r9, #3 ; 0x3 + 1968c: e289000c add r0, r9, #12 ; 0xc + 19690: e58d0434 str r0, [sp, #1076] + 19694: e2890000 add r0, r9, #0 ; 0x0 + 19698: ebf5a89e bl 0xffd83918 + 1969c: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 196a0: e1a06000 mov r6, r0 + 196a4: e2890004 add r0, r9, #4 ; 0x4 + 196a8: ebf5a89a bl 0xffd83918 + 196ac: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 196b0: e1a07000 mov r7, r0 + 196b4: e2890008 add r0, r9, #8 ; 0x8 + 196b8: ebf5a896 bl 0xffd83918 + 196bc: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 196c0: e1a08000 mov r8, r0 + 196c4: ebf5aa2d bl 0xffd83f80 + 196c8: 08004732 stmeqda r0, {r1, r4, r5, r8, r9, sl, lr} + 196cc: e1a00006 mov r0, r6 + 196d0: e58d0420 str r0, [sp, #1056] + 196d4: ebf5aa29 bl 0xffd83f80 + 196d8: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 196dc: e1a00007 mov r0, r7 + 196e0: e58d0424 str r0, [sp, #1060] + 196e4: ebf5aa25 bl 0xffd83f80 + 196e8: 08004736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, lr} + 196ec: e1a00008 mov r0, r8 + 196f0: e58d0428 str r0, [sp, #1064] + 196f4: ebf5aa21 bl 0xffd83f80 + 196f8: 08004738 stmeqda r0, {r3, r4, r5, r8, r9, sl, lr} + 196fc: e59d9434 ldr r9, [sp, #1076] + 19700: e3c99003 bic r9, r9, #3 ; 0x3 + 19704: e2890010 add r0, r9, #16 ; 0x10 + 19708: e58d0434 str r0, [sp, #1076] + 1970c: e2890000 add r0, r9, #0 ; 0x0 + 19710: ebf5a880 bl 0xffd83918 + 19714: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19718: e1a07000 mov r7, r0 + 1971c: e2890004 add r0, r9, #4 ; 0x4 + 19720: ebf5a87c bl 0xffd83918 + 19724: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19728: e1a08000 mov r8, r0 + 1972c: e2890008 add r0, r9, #8 ; 0x8 + 19730: ebf5a878 bl 0xffd83918 + 19734: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19738: e58d0418 str r0, [sp, #1048] + 1973c: e289000c add r0, r9, #12 ; 0xc + 19740: ebf5a874 bl 0xffd83918 + 19744: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19748: e58d041c str r0, [sp, #1052] + 1974c: ebf5aa0b bl 0xffd83f80 + 19750: 0800473a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, lr} + 19754: e59d9434 ldr r9, [sp, #1076] + 19758: e3c99003 bic r9, r9, #3 ; 0x3 + 1975c: e2890004 add r0, r9, #4 ; 0x4 + 19760: e58d0434 str r0, [sp, #1076] + 19764: e2890000 add r0, r9, #0 ; 0x0 + 19768: ebf5a86a bl 0xffd83918 + 1976c: 0800473e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, lr} + 19770: e1a03000 mov r3, r0 + 19774: ebf5aa01 bl 0xffd83f80 + 19778: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1977c: e1a00003 mov r0, r3 + 19780: e28cc020 add ip, ip, #32 ; 0x20 + 19784: eaf5a651 b 0xffd830d0 + 19788: 0800467e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, lr} + 1978c: 00000000 andeq r0, r0, r0 + 19790: ebf5a9fa bl 0xffd83f80 + 19794: 0800467e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, lr} + 19798: e3b04020 movs r4, #32 ; 0x20 + 1979c: ebf5a9f7 bl 0xffd83f80 + 197a0: 08004680 stmeqda r0, {r7, r9, sl, lr} + 197a4: e1a01004 mov r1, r4 + 197a8: e0144008 ands r4, r4, r8 + 197ac: ebf5a9f3 bl 0xffd83f80 + 197b0: 08004682 stmeqda r0, {r1, r7, r9, sl, lr} + 197b4: e59d0434 ldr r0, [sp, #1076] + 197b8: e2800f07 add r0, r0, #28 ; 0x1c + 197bc: ebf5a855 bl 0xffd83918 + 197c0: 08004686 stmeqda r0, {r1, r2, r7, r9, sl, lr} + 197c4: e1a05000 mov r5, r0 + 197c8: ebf5a9ec bl 0xffd83f80 + 197cc: 08004684 stmeqda r0, {r2, r7, r9, sl, lr} + 197d0: e1b04554 movs r4, r4, asr r5 + 197d4: ebf5a9e9 bl 0xffd83f80 + 197d8: 08004686 stmeqda r0, {r1, r2, r7, r9, sl, lr} + 197dc: e59d0434 ldr r0, [sp, #1076] + 197e0: e2800f09 add r0, r0, #36 ; 0x24 + 197e4: ebf5a84b bl 0xffd83918 + 197e8: 0800468a stmeqda r0, {r1, r3, r7, r9, sl, lr} + 197ec: e1a07000 mov r7, r0 + 197f0: ebf5a9e2 bl 0xffd83f80 + 197f4: 08004688 stmeqda r0, {r3, r7, r9, sl, lr} + 197f8: e1a01007 mov r1, r7 + 197fc: e0974004 adds r4, r7, r4 + 19800: ebf5a9de bl 0xffd83f80 + 19804: 0800468a stmeqda r0, {r1, r3, r7, r9, sl, lr} + 19808: e1b04584 movs r4, r4, lsl #11 + 1980c: ebf5a9db bl 0xffd83f80 + 19810: 0800468c stmeqda r0, {r2, r3, r7, r9, sl, lr} + 19814: e59d0434 ldr r0, [sp, #1076] + 19818: e2800f05 add r0, r0, #20 ; 0x14 + 1981c: ebf5a83d bl 0xffd83918 + 19820: 08004690 stmeqda r0, {r4, r7, r9, sl, lr} + 19824: e1a03000 mov r3, r0 + 19828: ebf5a9d4 bl 0xffd83f80 + 1982c: 0800468e stmeqda r0, {r1, r2, r3, r7, r9, sl, lr} + 19830: e1a01003 mov r1, r3 + 19834: e0934004 adds r4, r3, r4 + 19838: ebf5a9d0 bl 0xffd83f80 + 1983c: 08004690 stmeqda r0, {r4, r7, r9, sl, lr} + 19840: e3b0501f movs r5, #31 ; 0x1f + 19844: ebf5a9cd bl 0xffd83f80 + 19848: 08004692 stmeqda r0, {r1, r4, r7, r9, sl, lr} + 1984c: e1a01006 mov r1, r6 + 19850: e2963000 adds r3, r6, #0 ; 0x0 + 19854: ebf5a9c9 bl 0xffd83f80 + 19858: 08004694 stmeqda r0, {r2, r4, r7, r9, sl, lr} + 1985c: e1a01003 mov r1, r3 + 19860: e0133005 ands r3, r3, r5 + 19864: ebf5a9c5 bl 0xffd83f80 + 19868: 08004696 stmeqda r0, {r1, r2, r4, r7, r9, sl, lr} + 1986c: e1b03303 movs r3, r3, lsl #6 + 19870: ebf5a9c2 bl 0xffd83f80 + 19874: 08004698 stmeqda r0, {r3, r4, r7, r9, sl, lr} + 19878: e1a01004 mov r1, r4 + 1987c: e0944003 adds r4, r4, r3 + 19880: ebf5a9be bl 0xffd83f80 + 19884: 0800469a stmeqda r0, {r1, r3, r4, r7, r9, sl, lr} + 19888: e1a01008 mov r1, r8 + 1988c: e2983000 adds r3, r8, #0 ; 0x0 + 19890: ebf5a9ba bl 0xffd83f80 + 19894: 0800469c stmeqda r0, {r2, r3, r4, r7, r9, sl, lr} + 19898: e1a01003 mov r1, r3 + 1989c: e0133005 ands r3, r3, r5 + 198a0: ebf5a9b6 bl 0xffd83f80 + 198a4: 0800469e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, lr} + 198a8: e1b03083 movs r3, r3, lsl #1 + 198ac: ebf5a9b3 bl 0xffd83f80 + 198b0: 080046a0 stmeqda r0, {r5, r7, r9, sl, lr} + 198b4: e1a01004 mov r1, r4 + 198b8: e0940003 adds r0, r4, r3 + 198bc: e58d0418 str r0, [sp, #1048] + 198c0: ebf5a9ae bl 0xffd83f80 + 198c4: 080046a2 stmeqda r0, {r1, r5, r7, r9, sl, lr} + 198c8: e59d1428 ldr r1, [sp, #1064] + 198cc: e1a04001 mov r4, r1 + 198d0: ebf5a9aa bl 0xffd83f80 + 198d4: 080046a4 stmeqda r0, {r2, r5, r7, r9, sl, lr} + 198d8: e3540000 cmp r4, #0 ; 0x0 + 198dc: ebf5a9a7 bl 0xffd83f80 + 198e0: 080046a6 stmeqda r0, {r1, r2, r5, r7, r9, sl, lr} + 198e4: e28cc045 add ip, ip, #69 ; 0x45 + 198e8: 0a000004 beq 0x19900 + 198ec: e1a00fac mov r0, ip, lsr #31 + 198f0: e08ff100 add pc, pc, r0, lsl #2 + 198f4: 080046ac stmeqda r0, {r2, r3, r5, r7, r9, sl, lr} + 198f8: ebf5a595 bl 0xffd82f54 + 198fc: ea00000e b 0x1993c + 19900: ebf5a99e bl 0xffd83f80 + 19904: 080046a8 stmeqda r0, {r3, r5, r7, r9, sl, lr} + 19908: e59d0418 ldr r0, [sp, #1048] + 1990c: e2800000 add r0, r0, #0 ; 0x0 + 19910: e1a01004 mov r1, r4 + 19914: ebf5a70c bl 0xffd8354c + 19918: 080046aa stmeqda r0, {r1, r3, r5, r7, r9, sl, lr} + 1991c: ebf5a997 bl 0xffd83f80 + 19920: 080046aa stmeqda r0, {r1, r3, r5, r7, r9, sl, lr} + 19924: e28cc007 add ip, ip, #7 ; 0x7 + 19928: e1a00fac mov r0, ip, lsr #31 + 1992c: e08ff100 add pc, pc, r0, lsl #2 + 19930: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 19934: ebf5a586 bl 0xffd82f54 + 19938: eaffff11 b 0x19584 + 1993c: ebf5a98f bl 0xffd83f80 + 19940: 080046ac stmeqda r0, {r2, r3, r5, r7, r9, sl, lr} + 19944: e1b05148 movs r5, r8, asr #2 + 19948: ebf5a98c bl 0xffd83f80 + 1994c: 080046ae stmeqda r0, {r1, r2, r3, r5, r7, r9, sl, lr} + 19950: e59d041c ldr r0, [sp, #1052] + 19954: e2800000 add r0, r0, #0 ; 0x0 + 19958: ebf5a7c2 bl 0xffd83868 + 1995c: 080046b2 stmeqda r0, {r1, r4, r5, r7, r9, sl, lr} + 19960: e1a03000 mov r3, r0 + 19964: ebf5a985 bl 0xffd83f80 + 19968: 080046b0 stmeqda r0, {r4, r5, r7, r9, sl, lr} + 1996c: e3b07080 movs r7, #128 ; 0x80 + 19970: ebf5a982 bl 0xffd83f80 + 19974: 080046b2 stmeqda r0, {r1, r4, r5, r7, r9, sl, lr} + 19978: e1b07187 movs r7, r7, lsl #3 + 1997c: ebf5a97f bl 0xffd83f80 + 19980: 080046b4 stmeqda r0, {r2, r4, r5, r7, r9, sl, lr} + 19984: e1a01007 mov r1, r7 + 19988: e2974000 adds r4, r7, #0 ; 0x0 + 1998c: ebf5a97b bl 0xffd83f80 + 19990: 080046b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sl, lr} + 19994: e1a01003 mov r1, r3 + 19998: e0133004 ands r3, r3, r4 + 1999c: ebf5a977 bl 0xffd83f80 + 199a0: 080046b8 stmeqda r0, {r3, r4, r5, r7, r9, sl, lr} + 199a4: e3530000 cmp r3, #0 ; 0x0 + 199a8: ebf5a974 bl 0xffd83f80 + 199ac: 080046ba stmeqda r0, {r1, r3, r4, r5, r7, r9, sl, lr} + 199b0: e28cc01a add ip, ip, #26 ; 0x1a + 199b4: 1a000004 bne 0x199cc + 199b8: e1a00fac mov r0, ip, lsr #31 + 199bc: e08ff100 add pc, pc, r0, lsl #2 + 199c0: 080046f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, lr} + 199c4: ebf5a562 bl 0xffd82f54 + 199c8: ea000028 b 0x19a70 + 199cc: ebf5a96b bl 0xffd83f80 + 199d0: 080046bc stmeqda r0, {r2, r3, r4, r5, r7, r9, sl, lr} + 199d4: e3b03010 movs r3, #16 ; 0x10 + 199d8: ebf5a968 bl 0xffd83f80 + 199dc: 080046be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sl, lr} + 199e0: e59d041c ldr r0, [sp, #1052] + 199e4: e0800003 add r0, r0, r3 + 199e8: ebf5a7b3 bl 0xffd838bc + 199ec: 080046c2 stmeqda r0, {r1, r6, r7, r9, sl, lr} + 199f0: e1a07000 mov r7, r0 + 199f4: ebf5a961 bl 0xffd83f80 + 199f8: 080046c0 stmeqda r0, {r6, r7, r9, sl, lr} + 199fc: e1a01005 mov r1, r5 + 19a00: e2953000 adds r3, r5, #0 ; 0x0 + 19a04: ebf5a95d bl 0xffd83f80 + 19a08: 080046c2 stmeqda r0, {r1, r6, r7, r9, sl, lr} + 19a0c: e1a01007 mov r1, r7 + 19a10: e2974000 adds r4, r7, #0 ; 0x0 + 19a14: ebf5a959 bl 0xffd83f80 + 19a18: 080046c4 stmeqda r0, {r2, r6, r7, r9, sl, lr} + 19a1c: e59d0434 ldr r0, [sp, #1076] + 19a20: e2800f0c add r0, r0, #48 ; 0x30 + 19a24: e1a01006 mov r1, r6 + 19a28: ebf5a6e7 bl 0xffd835cc + 19a2c: 080046c6 stmeqda r0, {r1, r2, r6, r7, r9, sl, lr} + 19a30: ebf5a952 bl 0xffd83f80 + 19a34: 080046c6 stmeqda r0, {r1, r2, r6, r7, r9, sl, lr} + 19a38: ebf5a950 bl 0xffd83f80 + 19a3c: 080046c8 stmeqda r0, {r3, r6, r7, r9, sl, lr} + 19a40: e3a000cb mov r0, #203 ; 0xcb + 19a44: e3800c46 orr r0, r0, #17920 ; 0x4600 + 19a48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 19a4c: e58d0438 str r0, [sp, #1080] + 19a50: e28cc018 add ip, ip, #24 ; 0x18 + 19a54: e1a00fac mov r0, ip, lsr #31 + 19a58: e08ff100 add pc, pc, r0, lsl #2 + 19a5c: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 19a60: ebf5a53b bl 0xffd82f54 + 19a64: ea0000f0 b 0x19e2c + 19a68: 080046f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, lr} + 19a6c: 00000000 andeq r0, r0, r0 + 19a70: ebf5a942 bl 0xffd83f80 + 19a74: 080046f0 stmeqda r0, {r4, r5, r6, r7, r9, sl, lr} + 19a78: e3550000 cmp r5, #0 ; 0x0 + 19a7c: ebf5a93f bl 0xffd83f80 + 19a80: 080046f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sl, lr} + 19a84: e28cc006 add ip, ip, #6 ; 0x6 + 19a88: aa000004 bge 0x19aa0 + 19a8c: e1a00fac mov r0, ip, lsr #31 + 19a90: e08ff100 add pc, pc, r0, lsl #2 + 19a94: 08004718 stmeqda r0, {r3, r4, r8, r9, sl, lr} + 19a98: ebf5a52d bl 0xffd82f54 + 19a9c: ea000054 b 0x19bf4 + 19aa0: ebf5a936 bl 0xffd83f80 + 19aa4: 080046f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sl, lr} + 19aa8: e3b04010 movs r4, #16 ; 0x10 + 19aac: ebf5a933 bl 0xffd83f80 + 19ab0: 080046f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl, lr} + 19ab4: e59d041c ldr r0, [sp, #1052] + 19ab8: e0800004 add r0, r0, r4 + 19abc: ebf5a77e bl 0xffd838bc + 19ac0: 080046fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl, lr} + 19ac4: e1a03000 mov r3, r0 + 19ac8: ebf5a92c bl 0xffd83f80 + 19acc: 080046f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, lr} + 19ad0: e1550003 cmp r5, r3 + 19ad4: ebf5a929 bl 0xffd83f80 + 19ad8: 080046fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl, lr} + 19adc: e28cc00e add ip, ip, #14 ; 0xe + 19ae0: ba000004 blt 0x19af8 + 19ae4: e1a00fac mov r0, ip, lsr #31 + 19ae8: e08ff100 add pc, pc, r0, lsl #2 + 19aec: 08004718 stmeqda r0, {r3, r4, r8, r9, sl, lr} + 19af0: ebf5a517 bl 0xffd82f54 + 19af4: ea00003e b 0x19bf4 + 19af8: ebf5a920 bl 0xffd83f80 + 19afc: 080046fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, lr} + 19b00: e1b03085 movs r3, r5, lsl #1 + 19b04: ebf5a91d bl 0xffd83f80 + 19b08: 080046fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sl, lr} + 19b0c: e59d1420 ldr r1, [sp, #1056] + 19b10: e0833001 add r3, r3, r1 + 19b14: ebf5a919 bl 0xffd83f80 + 19b18: 08004700 stmeqda r0, {r8, r9, sl, lr} + 19b1c: e2830000 add r0, r3, #0 ; 0x0 + 19b20: ebf5a750 bl 0xffd83868 + 19b24: 08004704 stmeqda r0, {r2, r8, r9, sl, lr} + 19b28: e1a03000 mov r3, r0 + 19b2c: ebf5a913 bl 0xffd83f80 + 19b30: 08004702 stmeqda r0, {r1, r8, r9, sl, lr} + 19b34: e1a01008 mov r1, r8 + 19b38: e2984000 adds r4, r8, #0 ; 0x0 + 19b3c: ebf5a90f bl 0xffd83f80 + 19b40: 08004704 stmeqda r0, {r2, r8, r9, sl, lr} + 19b44: e3b05003 movs r5, #3 ; 0x3 + 19b48: ebf5a90c bl 0xffd83f80 + 19b4c: 08004706 stmeqda r0, {r1, r2, r8, r9, sl, lr} + 19b50: e1a01004 mov r1, r4 + 19b54: e0144005 ands r4, r4, r5 + 19b58: ebf5a908 bl 0xffd83f80 + 19b5c: 08004708 stmeqda r0, {r3, r8, r9, sl, lr} + 19b60: e1b04084 movs r4, r4, lsl #1 + 19b64: ebf5a905 bl 0xffd83f80 + 19b68: 0800470a stmeqda r0, {r1, r3, r8, r9, sl, lr} + 19b6c: e1b03283 movs r3, r3, lsl #5 + 19b70: ebf5a902 bl 0xffd83f80 + 19b74: 0800470c stmeqda r0, {r2, r3, r8, r9, sl, lr} + 19b78: e59d0434 ldr r0, [sp, #1076] + 19b7c: e2800f06 add r0, r0, #24 ; 0x18 + 19b80: ebf5a764 bl 0xffd83918 + 19b84: 08004710 stmeqda r0, {r4, r8, r9, sl, lr} + 19b88: e1a07000 mov r7, r0 + 19b8c: ebf5a8fb bl 0xffd83f80 + 19b90: 0800470e stmeqda r0, {r1, r2, r3, r8, r9, sl, lr} + 19b94: e1a01003 mov r1, r3 + 19b98: e0933007 adds r3, r3, r7 + 19b9c: ebf5a8f7 bl 0xffd83f80 + 19ba0: 08004710 stmeqda r0, {r4, r8, r9, sl, lr} + 19ba4: e59d1424 ldr r1, [sp, #1060] + 19ba8: e0833001 add r3, r3, r1 + 19bac: ebf5a8f3 bl 0xffd83f80 + 19bb0: 08004712 stmeqda r0, {r1, r4, r8, r9, sl, lr} + 19bb4: e1a01004 mov r1, r4 + 19bb8: e0944003 adds r4, r4, r3 + 19bbc: ebf5a8ef bl 0xffd83f80 + 19bc0: 08004714 stmeqda r0, {r2, r4, r8, r9, sl, lr} + 19bc4: e2840000 add r0, r4, #0 ; 0x0 + 19bc8: ebf5a726 bl 0xffd83868 + 19bcc: 08004718 stmeqda r0, {r3, r4, r8, r9, sl, lr} + 19bd0: e1a03000 mov r3, r0 + 19bd4: ebf5a8e9 bl 0xffd83f80 + 19bd8: 08004716 stmeqda r0, {r1, r2, r4, r8, r9, sl, lr} + 19bdc: e28cc030 add ip, ip, #48 ; 0x30 + 19be0: e1a00fac mov r0, ip, lsr #31 + 19be4: e08ff100 add pc, pc, r0, lsl #2 + 19be8: 0800471a stmeqda r0, {r1, r3, r4, r8, r9, sl, lr} + 19bec: ebf5a4d8 bl 0xffd82f54 + 19bf0: ea000003 b 0x19c04 + 19bf4: ebf5a8e1 bl 0xffd83f80 + 19bf8: 08004718 stmeqda r0, {r3, r4, r8, r9, sl, lr} + 19bfc: e3b03000 movs r3, #0 ; 0x0 + 19c00: e28cc003 add ip, ip, #3 ; 0x3 + 19c04: ebf5a8dd bl 0xffd83f80 + 19c08: 0800471a stmeqda r0, {r1, r3, r4, r8, r9, sl, lr} + 19c0c: e59d0418 ldr r0, [sp, #1048] + 19c10: e2800000 add r0, r0, #0 ; 0x0 + 19c14: e1a01003 mov r1, r3 + 19c18: ebf5a64b bl 0xffd8354c + 19c1c: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 19c20: ebf5a8d6 bl 0xffd83f80 + 19c24: 0800471c stmeqda r0, {r2, r3, r4, r8, r9, sl, lr} + 19c28: e1a01008 mov r1, r8 + 19c2c: e2988001 adds r8, r8, #1 ; 0x1 + 19c30: ebf5a8d2 bl 0xffd83f80 + 19c34: 0800471e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, lr} + 19c38: e59d0434 ldr r0, [sp, #1076] + 19c3c: e2800f01 add r0, r0, #4 ; 0x4 + 19c40: ebf5a734 bl 0xffd83918 + 19c44: 08004722 stmeqda r0, {r1, r5, r8, r9, sl, lr} + 19c48: e1a03000 mov r3, r0 + 19c4c: ebf5a8cb bl 0xffd83f80 + 19c50: 08004720 stmeqda r0, {r5, r8, r9, sl, lr} + 19c54: e1580003 cmp r8, r3 + 19c58: ebf5a8c8 bl 0xffd83f80 + 19c5c: 08004722 stmeqda r0, {r1, r5, r8, r9, sl, lr} + 19c60: e28cc012 add ip, ip, #18 ; 0x12 + 19c64: ca000004 bgt 0x19c7c + 19c68: e1a00fac mov r0, ip, lsr #31 + 19c6c: e08ff100 add pc, pc, r0, lsl #2 + 19c70: 0800467e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, lr} + 19c74: ebf5a4b6 bl 0xffd82f54 + 19c78: eafffec4 b 0x19790 + 19c7c: ebf5a8bf bl 0xffd83f80 + 19c80: 08004724 stmeqda r0, {r2, r5, r8, r9, sl, lr} + 19c84: e59d0434 ldr r0, [sp, #1076] + 19c88: e2800f0b add r0, r0, #44 ; 0x2c + 19c8c: ebf5a721 bl 0xffd83918 + 19c90: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 19c94: e1a06000 mov r6, r0 + 19c98: ebf5a8b8 bl 0xffd83f80 + 19c9c: 08004726 stmeqda r0, {r1, r2, r5, r8, r9, sl, lr} + 19ca0: e59d0434 ldr r0, [sp, #1076] + 19ca4: e2800f15 add r0, r0, #84 ; 0x54 + 19ca8: ebf5a71a bl 0xffd83918 + 19cac: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 19cb0: e1a04000 mov r4, r0 + 19cb4: ebf5a8b1 bl 0xffd83f80 + 19cb8: 08004728 stmeqda r0, {r3, r5, r8, r9, sl, lr} + 19cbc: e1560004 cmp r6, r4 + 19cc0: ebf5a8ae bl 0xffd83f80 + 19cc4: 0800472a stmeqda r0, {r1, r3, r5, r8, r9, sl, lr} + 19cc8: e28cc010 add ip, ip, #16 ; 0x10 + 19ccc: da000004 ble 0x19ce4 + 19cd0: e1a00fac mov r0, ip, lsr #31 + 19cd4: e08ff100 add pc, pc, r0, lsl #2 + 19cd8: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19cdc: ebf5a49c bl 0xffd82f54 + 19ce0: ea000007 b 0x19d04 + 19ce4: ebf5a8a5 bl 0xffd83f80 + 19ce8: 0800472c stmeqda r0, {r2, r3, r5, r8, r9, sl, lr} + 19cec: e28cc003 add ip, ip, #3 ; 0x3 + 19cf0: e1a00fac mov r0, ip, lsr #31 + 19cf4: e08ff100 add pc, pc, r0, lsl #2 + 19cf8: 0800460e stmeqda r0, {r1, r2, r3, r9, sl, lr} + 19cfc: ebf5a494 bl 0xffd82f54 + 19d00: eafffc0e b 0x18d40 + 19d04: ebf5a89d bl 0xffd83f80 + 19d08: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 19d0c: e59d0434 ldr r0, [sp, #1076] + 19d10: e2800f0d add r0, r0, #52 ; 0x34 + 19d14: e58d0434 str r0, [sp, #1076] + 19d18: ebf5a898 bl 0xffd83f80 + 19d1c: 08004730 stmeqda r0, {r4, r5, r8, r9, sl, lr} + 19d20: e59d9434 ldr r9, [sp, #1076] + 19d24: e3c99003 bic r9, r9, #3 ; 0x3 + 19d28: e289000c add r0, r9, #12 ; 0xc + 19d2c: e58d0434 str r0, [sp, #1076] + 19d30: e2890000 add r0, r9, #0 ; 0x0 + 19d34: ebf5a6f7 bl 0xffd83918 + 19d38: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 19d3c: e1a06000 mov r6, r0 + 19d40: e2890004 add r0, r9, #4 ; 0x4 + 19d44: ebf5a6f3 bl 0xffd83918 + 19d48: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 19d4c: e1a07000 mov r7, r0 + 19d50: e2890008 add r0, r9, #8 ; 0x8 + 19d54: ebf5a6ef bl 0xffd83918 + 19d58: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 19d5c: e1a08000 mov r8, r0 + 19d60: ebf5a886 bl 0xffd83f80 + 19d64: 08004732 stmeqda r0, {r1, r4, r5, r8, r9, sl, lr} + 19d68: e1a00006 mov r0, r6 + 19d6c: e58d0420 str r0, [sp, #1056] + 19d70: ebf5a882 bl 0xffd83f80 + 19d74: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 19d78: e1a00007 mov r0, r7 + 19d7c: e58d0424 str r0, [sp, #1060] + 19d80: ebf5a87e bl 0xffd83f80 + 19d84: 08004736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, lr} + 19d88: e1a00008 mov r0, r8 + 19d8c: e58d0428 str r0, [sp, #1064] + 19d90: ebf5a87a bl 0xffd83f80 + 19d94: 08004738 stmeqda r0, {r3, r4, r5, r8, r9, sl, lr} + 19d98: e59d9434 ldr r9, [sp, #1076] + 19d9c: e3c99003 bic r9, r9, #3 ; 0x3 + 19da0: e2890010 add r0, r9, #16 ; 0x10 + 19da4: e58d0434 str r0, [sp, #1076] + 19da8: e2890000 add r0, r9, #0 ; 0x0 + 19dac: ebf5a6d9 bl 0xffd83918 + 19db0: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19db4: e1a07000 mov r7, r0 + 19db8: e2890004 add r0, r9, #4 ; 0x4 + 19dbc: ebf5a6d5 bl 0xffd83918 + 19dc0: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19dc4: e1a08000 mov r8, r0 + 19dc8: e2890008 add r0, r9, #8 ; 0x8 + 19dcc: ebf5a6d1 bl 0xffd83918 + 19dd0: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19dd4: e58d0418 str r0, [sp, #1048] + 19dd8: e289000c add r0, r9, #12 ; 0xc + 19ddc: ebf5a6cd bl 0xffd83918 + 19de0: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19de4: e58d041c str r0, [sp, #1052] + 19de8: ebf5a864 bl 0xffd83f80 + 19dec: 0800473a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, lr} + 19df0: e59d9434 ldr r9, [sp, #1076] + 19df4: e3c99003 bic r9, r9, #3 ; 0x3 + 19df8: e2890004 add r0, r9, #4 ; 0x4 + 19dfc: e58d0434 str r0, [sp, #1076] + 19e00: e2890000 add r0, r9, #0 ; 0x0 + 19e04: ebf5a6c3 bl 0xffd83918 + 19e08: 0800473e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, lr} + 19e0c: e1a03000 mov r3, r0 + 19e10: ebf5a85a bl 0xffd83f80 + 19e14: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 19e18: e1a00003 mov r0, r3 + 19e1c: e28cc020 add ip, ip, #32 ; 0x20 + 19e20: eaf5a4aa b 0xffd830d0 + 19e24: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 19e28: 00000000 andeq r0, r0, r0 + 19e2c: ebf5a853 bl 0xffd83f80 + 19e30: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 19e34: e3b06001 movs r6, #1 ; 0x1 + 19e38: ebf5a850 bl 0xffd83f80 + 19e3c: 080c36e6 stmeqda ip, {r1, r2, r5, r6, r7, r9, sl, ip, sp} + 19e40: e3540000 cmp r4, #0 ; 0x0 + 19e44: ebf5a84d bl 0xffd83f80 + 19e48: 080c36e8 stmeqda ip, {r3, r5, r6, r7, r9, sl, ip, sp} + 19e4c: e28cc009 add ip, ip, #9 ; 0x9 + 19e50: 1a000004 bne 0x19e68 + 19e54: e1a00fac mov r0, ip, lsr #31 + 19e58: e08ff100 add pc, pc, r0, lsl #2 + 19e5c: 080c37a8 stmeqda ip, {r3, r5, r7, r8, r9, sl, ip, sp} + 19e60: ebf5a43b bl 0xffd82f54 + 19e64: ea0001da b 0x1a5d4 + 19e68: ebf5a844 bl 0xffd83f80 + 19e6c: 080c36ea stmeqda ip, {r1, r3, r5, r6, r7, r9, sl, ip, sp} + 19e70: e28cc003 add ip, ip, #3 ; 0x3 + 19e74: 4a000004 bmi 0x19e8c + 19e78: e1a00fac mov r0, ip, lsr #31 + 19e7c: e08ff100 add pc, pc, r0, lsl #2 + 19e80: 080c36ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r9, sl, ip, sp} + 19e84: ebf5a432 bl 0xffd82f54 + 19e88: ea000004 b 0x19ea0 + 19e8c: ebf5a83b bl 0xffd83f80 + 19e90: 080c36ec stmeqda ip, {r2, r3, r5, r6, r7, r9, sl, ip, sp} + 19e94: e3a01000 mov r1, #0 ; 0x0 + 19e98: e0514004 subs r4, r1, r4 + 19e9c: e28cc003 add ip, ip, #3 ; 0x3 + 19ea0: ebf5a836 bl 0xffd83f80 + 19ea4: 080c36ee stmeqda ip, {r1, r2, r3, r5, r6, r7, r9, sl, ip, sp} + 19ea8: e59d9434 ldr r9, [sp, #1076] + 19eac: e3c99003 bic r9, r9, #3 ; 0x3 + 19eb0: e2499004 sub r9, r9, #4 ; 0x4 + 19eb4: e58d9434 str r9, [sp, #1076] + 19eb8: e2890000 add r0, r9, #0 ; 0x0 + 19ebc: e1a01007 mov r1, r7 + 19ec0: ebf5a5c1 bl 0xffd835cc + 19ec4: 080c36f0 stmeqda ip, {r4, r5, r6, r7, r9, sl, ip, sp} + 19ec8: ebf5a82c bl 0xffd83f80 + 19ecc: 080c36f0 stmeqda ip, {r4, r5, r6, r7, r9, sl, ip, sp} + 19ed0: e59d9434 ldr r9, [sp, #1076] + 19ed4: e3c99003 bic r9, r9, #3 ; 0x3 + 19ed8: e2499004 sub r9, r9, #4 ; 0x4 + 19edc: e58d9434 str r9, [sp, #1076] + 19ee0: e2890000 add r0, r9, #0 ; 0x0 + 19ee4: e1a01003 mov r1, r3 + 19ee8: ebf5a5b7 bl 0xffd835cc + 19eec: 080c36f2 stmeqda ip, {r1, r4, r5, r6, r7, r9, sl, ip, sp} + 19ef0: ebf5a822 bl 0xffd83f80 + 19ef4: 080c36f2 stmeqda ip, {r1, r4, r5, r6, r7, r9, sl, ip, sp} + 19ef8: e3530000 cmp r3, #0 ; 0x0 + 19efc: ebf5a81f bl 0xffd83f80 + 19f00: 080c36f4 stmeqda ip, {r2, r4, r5, r6, r7, r9, sl, ip, sp} + 19f04: e28cc00e add ip, ip, #14 ; 0xe + 19f08: 4a000004 bmi 0x19f20 + 19f0c: e1a00fac mov r0, ip, lsr #31 + 19f10: e08ff100 add pc, pc, r0, lsl #2 + 19f14: 080c36f8 stmeqda ip, {r3, r4, r5, r6, r7, r9, sl, ip, sp} + 19f18: ebf5a40d bl 0xffd82f54 + 19f1c: ea000004 b 0x19f34 + 19f20: ebf5a816 bl 0xffd83f80 + 19f24: 080c36f6 stmeqda ip, {r1, r2, r4, r5, r6, r7, r9, sl, ip, sp} + 19f28: e3a01000 mov r1, #0 ; 0x0 + 19f2c: e0513003 subs r3, r1, r3 + 19f30: e28cc003 add ip, ip, #3 ; 0x3 + 19f34: ebf5a811 bl 0xffd83f80 + 19f38: 080c36f8 stmeqda ip, {r3, r4, r5, r6, r7, r9, sl, ip, sp} + 19f3c: e1530004 cmp r3, r4 + 19f40: ebf5a80e bl 0xffd83f80 + 19f44: 080c36fa stmeqda ip, {r1, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 19f48: e28cc006 add ip, ip, #6 ; 0x6 + 19f4c: 2a000004 bcs 0x19f64 + 19f50: e1a00fac mov r0, ip, lsr #31 + 19f54: e08ff100 add pc, pc, r0, lsl #2 + 19f58: 080c379c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, ip, sp} + 19f5c: ebf5a3fc bl 0xffd82f54 + 19f60: ea000170 b 0x1a528 + 19f64: ebf5a805 bl 0xffd83f80 + 19f68: 080c36fc stmeqda ip, {r2, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 19f6c: e3b07001 movs r7, #1 ; 0x1 + 19f70: ebf5a802 bl 0xffd83f80 + 19f74: 080c36fe stmeqda ip, {r1, r2, r3, r4, r5, r6, r7, r9, sl, ip, sp} + 19f78: e1b07e07 movs r7, r7, lsl #28 + 19f7c: e28cc006 add ip, ip, #6 ; 0x6 + 19f80: ebf5a7fe bl 0xffd83f80 + 19f84: 080c3700 stmeqda ip, {r8, r9, sl, ip, sp} + 19f88: e1540007 cmp r4, r7 + 19f8c: ebf5a7fb bl 0xffd83f80 + 19f90: 080c3702 stmeqda ip, {r1, r8, r9, sl, ip, sp} + 19f94: e28cc006 add ip, ip, #6 ; 0x6 + 19f98: 3a000004 bcc 0x19fb0 + 19f9c: e1a00fac mov r0, ip, lsr #31 + 19fa0: e08ff100 add pc, pc, r0, lsl #2 + 19fa4: 080c370e stmeqda ip, {r1, r2, r3, r8, r9, sl, ip, sp} + 19fa8: ebf5a3e9 bl 0xffd82f54 + 19fac: ea000019 b 0x1a018 + 19fb0: ebf5a7f2 bl 0xffd83f80 + 19fb4: 080c3704 stmeqda ip, {r2, r8, r9, sl, ip, sp} + 19fb8: e1540003 cmp r4, r3 + 19fbc: ebf5a7ef bl 0xffd83f80 + 19fc0: 080c3706 stmeqda ip, {r1, r2, r8, r9, sl, ip, sp} + 19fc4: e28cc006 add ip, ip, #6 ; 0x6 + 19fc8: 3a000004 bcc 0x19fe0 + 19fcc: e1a00fac mov r0, ip, lsr #31 + 19fd0: e08ff100 add pc, pc, r0, lsl #2 + 19fd4: 080c370e stmeqda ip, {r1, r2, r3, r8, r9, sl, ip, sp} + 19fd8: ebf5a3dd bl 0xffd82f54 + 19fdc: ea00000d b 0x1a018 + 19fe0: ebf5a7e6 bl 0xffd83f80 + 19fe4: 080c3708 stmeqda ip, {r3, r8, r9, sl, ip, sp} + 19fe8: e1b04204 movs r4, r4, lsl #4 + 19fec: ebf5a7e3 bl 0xffd83f80 + 19ff0: 080c370a stmeqda ip, {r1, r3, r8, r9, sl, ip, sp} + 19ff4: e1b06206 movs r6, r6, lsl #4 + 19ff8: ebf5a7e0 bl 0xffd83f80 + 19ffc: 080c370c stmeqda ip, {r2, r3, r8, r9, sl, ip, sp} + 1a000: e28cc009 add ip, ip, #9 ; 0x9 + 1a004: e1a00fac mov r0, ip, lsr #31 + 1a008: e08ff100 add pc, pc, r0, lsl #2 + 1a00c: 080c3700 stmeqda ip, {r8, r9, sl, ip, sp} + 1a010: ebf5a3cf bl 0xffd82f54 + 1a014: eaffffd9 b 0x19f80 + 1a018: ebf5a7d8 bl 0xffd83f80 + 1a01c: 080c370e stmeqda ip, {r1, r2, r3, r8, r9, sl, ip, sp} + 1a020: e1b07187 movs r7, r7, lsl #3 + 1a024: e28cc003 add ip, ip, #3 ; 0x3 + 1a028: ebf5a7d4 bl 0xffd83f80 + 1a02c: 080c3710 stmeqda ip, {r4, r8, r9, sl, ip, sp} + 1a030: e1540007 cmp r4, r7 + 1a034: ebf5a7d1 bl 0xffd83f80 + 1a038: 080c3712 stmeqda ip, {r1, r4, r8, r9, sl, ip, sp} + 1a03c: e28cc006 add ip, ip, #6 ; 0x6 + 1a040: 3a000004 bcc 0x1a058 + 1a044: e1a00fac mov r0, ip, lsr #31 + 1a048: e08ff100 add pc, pc, r0, lsl #2 + 1a04c: 080c371e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, ip, sp} + 1a050: ebf5a3bf bl 0xffd82f54 + 1a054: ea000019 b 0x1a0c0 + 1a058: ebf5a7c8 bl 0xffd83f80 + 1a05c: 080c3714 stmeqda ip, {r2, r4, r8, r9, sl, ip, sp} + 1a060: e1540003 cmp r4, r3 + 1a064: ebf5a7c5 bl 0xffd83f80 + 1a068: 080c3716 stmeqda ip, {r1, r2, r4, r8, r9, sl, ip, sp} + 1a06c: e28cc006 add ip, ip, #6 ; 0x6 + 1a070: 3a000004 bcc 0x1a088 + 1a074: e1a00fac mov r0, ip, lsr #31 + 1a078: e08ff100 add pc, pc, r0, lsl #2 + 1a07c: 080c371e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, ip, sp} + 1a080: ebf5a3b3 bl 0xffd82f54 + 1a084: ea00000d b 0x1a0c0 + 1a088: ebf5a7bc bl 0xffd83f80 + 1a08c: 080c3718 stmeqda ip, {r3, r4, r8, r9, sl, ip, sp} + 1a090: e1b04084 movs r4, r4, lsl #1 + 1a094: ebf5a7b9 bl 0xffd83f80 + 1a098: 080c371a stmeqda ip, {r1, r3, r4, r8, r9, sl, ip, sp} + 1a09c: e1b06086 movs r6, r6, lsl #1 + 1a0a0: ebf5a7b6 bl 0xffd83f80 + 1a0a4: 080c371c stmeqda ip, {r2, r3, r4, r8, r9, sl, ip, sp} + 1a0a8: e28cc009 add ip, ip, #9 ; 0x9 + 1a0ac: e1a00fac mov r0, ip, lsr #31 + 1a0b0: e08ff100 add pc, pc, r0, lsl #2 + 1a0b4: 080c3710 stmeqda ip, {r4, r8, r9, sl, ip, sp} + 1a0b8: ebf5a3a5 bl 0xffd82f54 + 1a0bc: eaffffd9 b 0x1a028 + 1a0c0: ebf5a7ae bl 0xffd83f80 + 1a0c4: 080c371e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, ip, sp} + 1a0c8: e3b05000 movs r5, #0 ; 0x0 + 1a0cc: ebf5a7ab bl 0xffd83f80 + 1a0d0: 080c3720 stmeqda ip, {r5, r8, r9, sl, ip, sp} + 1a0d4: e1530004 cmp r3, r4 + 1a0d8: ebf5a7a8 bl 0xffd83f80 + 1a0dc: 080c3722 stmeqda ip, {r1, r5, r8, r9, sl, ip, sp} + 1a0e0: e28cc009 add ip, ip, #9 ; 0x9 + 1a0e4: 2a000004 bcs 0x1a0fc + 1a0e8: e1a00fac mov r0, ip, lsr #31 + 1a0ec: e08ff100 add pc, pc, r0, lsl #2 + 1a0f0: 080c3726 stmeqda ip, {r1, r2, r5, r8, r9, sl, ip, sp} + 1a0f4: ebf5a396 bl 0xffd82f54 + 1a0f8: ea000004 b 0x1a110 + 1a0fc: ebf5a79f bl 0xffd83f80 + 1a100: 080c3724 stmeqda ip, {r2, r5, r8, r9, sl, ip, sp} + 1a104: e1a01003 mov r1, r3 + 1a108: e0533004 subs r3, r3, r4 + 1a10c: e28cc003 add ip, ip, #3 ; 0x3 + 1a110: ebf5a79a bl 0xffd83f80 + 1a114: 080c3726 stmeqda ip, {r1, r2, r5, r8, r9, sl, ip, sp} + 1a118: e1b070a4 movs r7, r4, lsr #1 + 1a11c: ebf5a797 bl 0xffd83f80 + 1a120: 080c3728 stmeqda ip, {r3, r5, r8, r9, sl, ip, sp} + 1a124: e1530007 cmp r3, r7 + 1a128: ebf5a794 bl 0xffd83f80 + 1a12c: 080c372a stmeqda ip, {r1, r3, r5, r8, r9, sl, ip, sp} + 1a130: e28cc009 add ip, ip, #9 ; 0x9 + 1a134: 2a000004 bcs 0x1a14c + 1a138: e1a00fac mov r0, ip, lsr #31 + 1a13c: e08ff100 add pc, pc, r0, lsl #2 + 1a140: 080c3738 stmeqda ip, {r3, r4, r5, r8, r9, sl, ip, sp} + 1a144: ebf5a382 bl 0xffd82f54 + 1a148: ea000016 b 0x1a1a8 + 1a14c: ebf5a78b bl 0xffd83f80 + 1a150: 080c372c stmeqda ip, {r2, r3, r5, r8, r9, sl, ip, sp} + 1a154: e1a01003 mov r1, r3 + 1a158: e0533007 subs r3, r3, r7 + 1a15c: ebf5a787 bl 0xffd83f80 + 1a160: 080c372e stmeqda ip, {r1, r2, r3, r5, r8, r9, sl, ip, sp} + 1a164: e1a00006 mov r0, r6 + 1a168: e58d0430 str r0, [sp, #1072] + 1a16c: ebf5a783 bl 0xffd83f80 + 1a170: 080c3730 stmeqda ip, {r4, r5, r8, r9, sl, ip, sp} + 1a174: e3b07001 movs r7, #1 ; 0x1 + 1a178: ebf5a780 bl 0xffd83f80 + 1a17c: 080c3732 stmeqda ip, {r1, r4, r5, r8, r9, sl, ip, sp} + 1a180: e1b06776 movs r6, r6, ror r7 + 1a184: ebf5a77d bl 0xffd83f80 + 1a188: 080c3734 stmeqda ip, {r2, r4, r5, r8, r9, sl, ip, sp} + 1a18c: e1a01005 mov r1, r5 + 1a190: e1955006 orrs r5, r5, r6 + 1a194: ebf5a779 bl 0xffd83f80 + 1a198: 080c3736 stmeqda ip, {r1, r2, r4, r5, r8, r9, sl, ip, sp} + 1a19c: e59d1430 ldr r1, [sp, #1072] + 1a1a0: e1a06001 mov r6, r1 + 1a1a4: e28cc012 add ip, ip, #18 ; 0x12 + 1a1a8: ebf5a774 bl 0xffd83f80 + 1a1ac: 080c3738 stmeqda ip, {r3, r4, r5, r8, r9, sl, ip, sp} + 1a1b0: e1b07124 movs r7, r4, lsr #2 + 1a1b4: ebf5a771 bl 0xffd83f80 + 1a1b8: 080c373a stmeqda ip, {r1, r3, r4, r5, r8, r9, sl, ip, sp} + 1a1bc: e1530007 cmp r3, r7 + 1a1c0: ebf5a76e bl 0xffd83f80 + 1a1c4: 080c373c stmeqda ip, {r2, r3, r4, r5, r8, r9, sl, ip, sp} + 1a1c8: e28cc009 add ip, ip, #9 ; 0x9 + 1a1cc: 2a000004 bcs 0x1a1e4 + 1a1d0: e1a00fac mov r0, ip, lsr #31 + 1a1d4: e08ff100 add pc, pc, r0, lsl #2 + 1a1d8: 080c374a stmeqda ip, {r1, r3, r6, r8, r9, sl, ip, sp} + 1a1dc: ebf5a35c bl 0xffd82f54 + 1a1e0: ea000016 b 0x1a240 + 1a1e4: ebf5a765 bl 0xffd83f80 + 1a1e8: 080c373e stmeqda ip, {r1, r2, r3, r4, r5, r8, r9, sl, ip, sp} + 1a1ec: e1a01003 mov r1, r3 + 1a1f0: e0533007 subs r3, r3, r7 + 1a1f4: ebf5a761 bl 0xffd83f80 + 1a1f8: 080c3740 stmeqda ip, {r6, r8, r9, sl, ip, sp} + 1a1fc: e1a00006 mov r0, r6 + 1a200: e58d0430 str r0, [sp, #1072] + 1a204: ebf5a75d bl 0xffd83f80 + 1a208: 080c3742 stmeqda ip, {r1, r6, r8, r9, sl, ip, sp} + 1a20c: e3b07002 movs r7, #2 ; 0x2 + 1a210: ebf5a75a bl 0xffd83f80 + 1a214: 080c3744 stmeqda ip, {r2, r6, r8, r9, sl, ip, sp} + 1a218: e1b06776 movs r6, r6, ror r7 + 1a21c: ebf5a757 bl 0xffd83f80 + 1a220: 080c3746 stmeqda ip, {r1, r2, r6, r8, r9, sl, ip, sp} + 1a224: e1a01005 mov r1, r5 + 1a228: e1955006 orrs r5, r5, r6 + 1a22c: ebf5a753 bl 0xffd83f80 + 1a230: 080c3748 stmeqda ip, {r3, r6, r8, r9, sl, ip, sp} + 1a234: e59d1430 ldr r1, [sp, #1072] + 1a238: e1a06001 mov r6, r1 + 1a23c: e28cc012 add ip, ip, #18 ; 0x12 + 1a240: ebf5a74e bl 0xffd83f80 + 1a244: 080c374a stmeqda ip, {r1, r3, r6, r8, r9, sl, ip, sp} + 1a248: e1b071a4 movs r7, r4, lsr #3 + 1a24c: ebf5a74b bl 0xffd83f80 + 1a250: 080c374c stmeqda ip, {r2, r3, r6, r8, r9, sl, ip, sp} + 1a254: e1530007 cmp r3, r7 + 1a258: ebf5a748 bl 0xffd83f80 + 1a25c: 080c374e stmeqda ip, {r1, r2, r3, r6, r8, r9, sl, ip, sp} + 1a260: e28cc009 add ip, ip, #9 ; 0x9 + 1a264: 2a000004 bcs 0x1a27c + 1a268: e1a00fac mov r0, ip, lsr #31 + 1a26c: e08ff100 add pc, pc, r0, lsl #2 + 1a270: 080c375c stmeqda ip, {r2, r3, r4, r6, r8, r9, sl, ip, sp} + 1a274: ebf5a336 bl 0xffd82f54 + 1a278: ea000016 b 0x1a2d8 + 1a27c: ebf5a73f bl 0xffd83f80 + 1a280: 080c3750 stmeqda ip, {r4, r6, r8, r9, sl, ip, sp} + 1a284: e1a01003 mov r1, r3 + 1a288: e0533007 subs r3, r3, r7 + 1a28c: ebf5a73b bl 0xffd83f80 + 1a290: 080c3752 stmeqda ip, {r1, r4, r6, r8, r9, sl, ip, sp} + 1a294: e1a00006 mov r0, r6 + 1a298: e58d0430 str r0, [sp, #1072] + 1a29c: ebf5a737 bl 0xffd83f80 + 1a2a0: 080c3754 stmeqda ip, {r2, r4, r6, r8, r9, sl, ip, sp} + 1a2a4: e3b07003 movs r7, #3 ; 0x3 + 1a2a8: ebf5a734 bl 0xffd83f80 + 1a2ac: 080c3756 stmeqda ip, {r1, r2, r4, r6, r8, r9, sl, ip, sp} + 1a2b0: e1b06776 movs r6, r6, ror r7 + 1a2b4: ebf5a731 bl 0xffd83f80 + 1a2b8: 080c3758 stmeqda ip, {r3, r4, r6, r8, r9, sl, ip, sp} + 1a2bc: e1a01005 mov r1, r5 + 1a2c0: e1955006 orrs r5, r5, r6 + 1a2c4: ebf5a72d bl 0xffd83f80 + 1a2c8: 080c375a stmeqda ip, {r1, r3, r4, r6, r8, r9, sl, ip, sp} + 1a2cc: e59d1430 ldr r1, [sp, #1072] + 1a2d0: e1a06001 mov r6, r1 + 1a2d4: e28cc012 add ip, ip, #18 ; 0x12 + 1a2d8: ebf5a728 bl 0xffd83f80 + 1a2dc: 080c375c stmeqda ip, {r2, r3, r4, r6, r8, r9, sl, ip, sp} + 1a2e0: e1a00006 mov r0, r6 + 1a2e4: e58d0430 str r0, [sp, #1072] + 1a2e8: ebf5a724 bl 0xffd83f80 + 1a2ec: 080c375e stmeqda ip, {r1, r2, r3, r4, r6, r8, r9, sl, ip, sp} + 1a2f0: e3530000 cmp r3, #0 ; 0x0 + 1a2f4: ebf5a721 bl 0xffd83f80 + 1a2f8: 080c3760 stmeqda ip, {r5, r6, r8, r9, sl, ip, sp} + 1a2fc: e28cc009 add ip, ip, #9 ; 0x9 + 1a300: 1a000004 bne 0x1a318 + 1a304: e1a00fac mov r0, ip, lsr #31 + 1a308: e08ff100 add pc, pc, r0, lsl #2 + 1a30c: 080c376a stmeqda ip, {r1, r3, r5, r6, r8, r9, sl, ip, sp} + 1a310: ebf5a30f bl 0xffd82f54 + 1a314: ea000016 b 0x1a374 + 1a318: ebf5a718 bl 0xffd83f80 + 1a31c: 080c3762 stmeqda ip, {r1, r5, r6, r8, r9, sl, ip, sp} + 1a320: e1b06226 movs r6, r6, lsr #4 + 1a324: ebf5a715 bl 0xffd83f80 + 1a328: 080c3764 stmeqda ip, {r2, r5, r6, r8, r9, sl, ip, sp} + 1a32c: e28cc006 add ip, ip, #6 ; 0x6 + 1a330: 1a000004 bne 0x1a348 + 1a334: e1a00fac mov r0, ip, lsr #31 + 1a338: e08ff100 add pc, pc, r0, lsl #2 + 1a33c: 080c376a stmeqda ip, {r1, r3, r5, r6, r8, r9, sl, ip, sp} + 1a340: ebf5a303 bl 0xffd82f54 + 1a344: ea00000a b 0x1a374 + 1a348: ebf5a70c bl 0xffd83f80 + 1a34c: 080c3766 stmeqda ip, {r1, r2, r5, r6, r8, r9, sl, ip, sp} + 1a350: e1b04224 movs r4, r4, lsr #4 + 1a354: ebf5a709 bl 0xffd83f80 + 1a358: 080c3768 stmeqda ip, {r3, r5, r6, r8, r9, sl, ip, sp} + 1a35c: e28cc006 add ip, ip, #6 ; 0x6 + 1a360: e1a00fac mov r0, ip, lsr #31 + 1a364: e08ff100 add pc, pc, r0, lsl #2 + 1a368: 080c371e stmeqda ip, {r1, r2, r3, r4, r8, r9, sl, ip, sp} + 1a36c: ebf5a2f8 bl 0xffd82f54 + 1a370: eaffff52 b 0x1a0c0 + 1a374: ebf5a701 bl 0xffd83f80 + 1a378: 080c376a stmeqda ip, {r1, r3, r5, r6, r8, r9, sl, ip, sp} + 1a37c: e3b0700e movs r7, #14 ; 0xe + 1a380: ebf5a6fe bl 0xffd83f80 + 1a384: 080c376c stmeqda ip, {r2, r3, r5, r6, r8, r9, sl, ip, sp} + 1a388: e1b07e07 movs r7, r7, lsl #28 + 1a38c: ebf5a6fb bl 0xffd83f80 + 1a390: 080c376e stmeqda ip, {r1, r2, r3, r5, r6, r8, r9, sl, ip, sp} + 1a394: e1a01005 mov r1, r5 + 1a398: e0155007 ands r5, r5, r7 + 1a39c: ebf5a6f7 bl 0xffd83f80 + 1a3a0: 080c3770 stmeqda ip, {r4, r5, r6, r8, r9, sl, ip, sp} + 1a3a4: e28cc00c add ip, ip, #12 ; 0xc + 1a3a8: 1a000004 bne 0x1a3c0 + 1a3ac: e1a00fac mov r0, ip, lsr #31 + 1a3b0: e08ff100 add pc, pc, r0, lsl #2 + 1a3b4: 080c379c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, ip, sp} + 1a3b8: ebf5a2e5 bl 0xffd82f54 + 1a3bc: ea000059 b 0x1a528 + 1a3c0: ebf5a6ee bl 0xffd83f80 + 1a3c4: 080c3772 stmeqda ip, {r1, r4, r5, r6, r8, r9, sl, ip, sp} + 1a3c8: e59d1430 ldr r1, [sp, #1072] + 1a3cc: e1a06001 mov r6, r1 + 1a3d0: ebf5a6ea bl 0xffd83f80 + 1a3d4: 080c3774 stmeqda ip, {r2, r4, r5, r6, r8, r9, sl, ip, sp} + 1a3d8: e3b07003 movs r7, #3 ; 0x3 + 1a3dc: ebf5a6e7 bl 0xffd83f80 + 1a3e0: 080c3776 stmeqda ip, {r1, r2, r4, r5, r6, r8, r9, sl, ip, sp} + 1a3e4: e1b06776 movs r6, r6, ror r7 + 1a3e8: ebf5a6e4 bl 0xffd83f80 + 1a3ec: 080c3778 stmeqda ip, {r3, r4, r5, r6, r8, r9, sl, ip, sp} + 1a3f0: e1150006 tst r5, r6 + 1a3f4: ebf5a6e1 bl 0xffd83f80 + 1a3f8: 080c377a stmeqda ip, {r1, r3, r4, r5, r6, r8, r9, sl, ip, sp} + 1a3fc: e28cc00f add ip, ip, #15 ; 0xf + 1a400: 1a000004 bne 0x1a418 + 1a404: e1a00fac mov r0, ip, lsr #31 + 1a408: e08ff100 add pc, pc, r0, lsl #2 + 1a40c: 080c3780 stmeqda ip, {r7, r8, r9, sl, ip, sp} + 1a410: ebf5a2cf bl 0xffd82f54 + 1a414: ea000007 b 0x1a438 + 1a418: ebf5a6d8 bl 0xffd83f80 + 1a41c: 080c377c stmeqda ip, {r2, r3, r4, r5, r6, r8, r9, sl, ip, sp} + 1a420: e1b071a4 movs r7, r4, lsr #3 + 1a424: ebf5a6d5 bl 0xffd83f80 + 1a428: 080c377e stmeqda ip, {r1, r2, r3, r4, r5, r6, r8, r9, sl, ip, sp} + 1a42c: e1a01003 mov r1, r3 + 1a430: e0933007 adds r3, r3, r7 + 1a434: e28cc006 add ip, ip, #6 ; 0x6 + 1a438: ebf5a6d0 bl 0xffd83f80 + 1a43c: 080c3780 stmeqda ip, {r7, r8, r9, sl, ip, sp} + 1a440: e59d1430 ldr r1, [sp, #1072] + 1a444: e1a06001 mov r6, r1 + 1a448: ebf5a6cc bl 0xffd83f80 + 1a44c: 080c3782 stmeqda ip, {r1, r7, r8, r9, sl, ip, sp} + 1a450: e3b07002 movs r7, #2 ; 0x2 + 1a454: ebf5a6c9 bl 0xffd83f80 + 1a458: 080c3784 stmeqda ip, {r2, r7, r8, r9, sl, ip, sp} + 1a45c: e1b06776 movs r6, r6, ror r7 + 1a460: ebf5a6c6 bl 0xffd83f80 + 1a464: 080c3786 stmeqda ip, {r1, r2, r7, r8, r9, sl, ip, sp} + 1a468: e1150006 tst r5, r6 + 1a46c: ebf5a6c3 bl 0xffd83f80 + 1a470: 080c3788 stmeqda ip, {r3, r7, r8, r9, sl, ip, sp} + 1a474: e28cc00f add ip, ip, #15 ; 0xf + 1a478: 1a000004 bne 0x1a490 + 1a47c: e1a00fac mov r0, ip, lsr #31 + 1a480: e08ff100 add pc, pc, r0, lsl #2 + 1a484: 080c378e stmeqda ip, {r1, r2, r3, r7, r8, r9, sl, ip, sp} + 1a488: ebf5a2b1 bl 0xffd82f54 + 1a48c: ea000007 b 0x1a4b0 + 1a490: ebf5a6ba bl 0xffd83f80 + 1a494: 080c378a stmeqda ip, {r1, r3, r7, r8, r9, sl, ip, sp} + 1a498: e1b07124 movs r7, r4, lsr #2 + 1a49c: ebf5a6b7 bl 0xffd83f80 + 1a4a0: 080c378c stmeqda ip, {r2, r3, r7, r8, r9, sl, ip, sp} + 1a4a4: e1a01003 mov r1, r3 + 1a4a8: e0933007 adds r3, r3, r7 + 1a4ac: e28cc006 add ip, ip, #6 ; 0x6 + 1a4b0: ebf5a6b2 bl 0xffd83f80 + 1a4b4: 080c378e stmeqda ip, {r1, r2, r3, r7, r8, r9, sl, ip, sp} + 1a4b8: e59d1430 ldr r1, [sp, #1072] + 1a4bc: e1a06001 mov r6, r1 + 1a4c0: ebf5a6ae bl 0xffd83f80 + 1a4c4: 080c3790 stmeqda ip, {r4, r7, r8, r9, sl, ip, sp} + 1a4c8: e3b07001 movs r7, #1 ; 0x1 + 1a4cc: ebf5a6ab bl 0xffd83f80 + 1a4d0: 080c3792 stmeqda ip, {r1, r4, r7, r8, r9, sl, ip, sp} + 1a4d4: e1b06776 movs r6, r6, ror r7 + 1a4d8: ebf5a6a8 bl 0xffd83f80 + 1a4dc: 080c3794 stmeqda ip, {r2, r4, r7, r8, r9, sl, ip, sp} + 1a4e0: e1150006 tst r5, r6 + 1a4e4: ebf5a6a5 bl 0xffd83f80 + 1a4e8: 080c3796 stmeqda ip, {r1, r2, r4, r7, r8, r9, sl, ip, sp} + 1a4ec: e28cc00f add ip, ip, #15 ; 0xf + 1a4f0: 1a000004 bne 0x1a508 + 1a4f4: e1a00fac mov r0, ip, lsr #31 + 1a4f8: e08ff100 add pc, pc, r0, lsl #2 + 1a4fc: 080c379c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, ip, sp} + 1a500: ebf5a293 bl 0xffd82f54 + 1a504: ea000007 b 0x1a528 + 1a508: ebf5a69c bl 0xffd83f80 + 1a50c: 080c3798 stmeqda ip, {r3, r4, r7, r8, r9, sl, ip, sp} + 1a510: e1b070a4 movs r7, r4, lsr #1 + 1a514: ebf5a699 bl 0xffd83f80 + 1a518: 080c379a stmeqda ip, {r1, r3, r4, r7, r8, r9, sl, ip, sp} + 1a51c: e1a01003 mov r1, r3 + 1a520: e0933007 adds r3, r3, r7 + 1a524: e28cc006 add ip, ip, #6 ; 0x6 + 1a528: ebf5a694 bl 0xffd83f80 + 1a52c: 080c379c stmeqda ip, {r2, r3, r4, r7, r8, r9, sl, ip, sp} + 1a530: e59d9434 ldr r9, [sp, #1076] + 1a534: e3c99003 bic r9, r9, #3 ; 0x3 + 1a538: e2890004 add r0, r9, #4 ; 0x4 + 1a53c: e58d0434 str r0, [sp, #1076] + 1a540: e2890000 add r0, r9, #0 ; 0x0 + 1a544: ebf5a4f3 bl 0xffd83918 + 1a548: 080c37a0 stmeqda ip, {r5, r7, r8, r9, sl, ip, sp} + 1a54c: e1a07000 mov r7, r0 + 1a550: ebf5a68a bl 0xffd83f80 + 1a554: 080c379e stmeqda ip, {r1, r2, r3, r4, r7, r8, r9, sl, ip, sp} + 1a558: e3570000 cmp r7, #0 ; 0x0 + 1a55c: ebf5a687 bl 0xffd83f80 + 1a560: 080c37a0 stmeqda ip, {r5, r7, r8, r9, sl, ip, sp} + 1a564: e28cc00a add ip, ip, #10 ; 0xa + 1a568: 4a000004 bmi 0x1a580 + 1a56c: e1a00fac mov r0, ip, lsr #31 + 1a570: e08ff100 add pc, pc, r0, lsl #2 + 1a574: 080c37a4 stmeqda ip, {r2, r5, r7, r8, r9, sl, ip, sp} + 1a578: ebf5a275 bl 0xffd82f54 + 1a57c: ea000004 b 0x1a594 + 1a580: ebf5a67e bl 0xffd83f80 + 1a584: 080c37a2 stmeqda ip, {r1, r5, r7, r8, r9, sl, ip, sp} + 1a588: e3a01000 mov r1, #0 ; 0x0 + 1a58c: e0513003 subs r3, r1, r3 + 1a590: e28cc003 add ip, ip, #3 ; 0x3 + 1a594: ebf5a679 bl 0xffd83f80 + 1a598: 080c37a4 stmeqda ip, {r2, r5, r7, r8, r9, sl, ip, sp} + 1a59c: e59d9434 ldr r9, [sp, #1076] + 1a5a0: e3c99003 bic r9, r9, #3 ; 0x3 + 1a5a4: e2890004 add r0, r9, #4 ; 0x4 + 1a5a8: e58d0434 str r0, [sp, #1076] + 1a5ac: e2890000 add r0, r9, #0 ; 0x0 + 1a5b0: ebf5a4d8 bl 0xffd83918 + 1a5b4: 080c37a8 stmeqda ip, {r3, r5, r7, r8, r9, sl, ip, sp} + 1a5b8: e1a07000 mov r7, r0 + 1a5bc: ebf5a66f bl 0xffd83f80 + 1a5c0: 080c37a6 stmeqda ip, {r1, r2, r5, r7, r8, r9, sl, ip, sp} + 1a5c4: e59d1438 ldr r1, [sp, #1080] + 1a5c8: e1a00001 mov r0, r1 + 1a5cc: e28cc007 add ip, ip, #7 ; 0x7 + 1a5d0: eaf5a29b b 0xffd83044 + 1a5d4: ebf5a669 bl 0xffd83f80 + 1a5d8: 080c37a8 stmeqda ip, {r3, r5, r7, r8, r9, sl, ip, sp} + 1a5dc: e59d9434 ldr r9, [sp, #1076] + 1a5e0: e3c99003 bic r9, r9, #3 ; 0x3 + 1a5e4: e2499004 sub r9, r9, #4 ; 0x4 + 1a5e8: e58d9434 str r9, [sp, #1076] + 1a5ec: e2890000 add r0, r9, #0 ; 0x0 + 1a5f0: e59d1438 ldr r1, [sp, #1080] + 1a5f4: ebf5a414 bl 0xffd8364c + 1a5f8: ebf5a660 bl 0xffd83f80 + 1a5fc: 080c37aa stmeqda ip, {r1, r3, r5, r7, r8, r9, sl, ip, sp} + 1a600: ebf5a65e bl 0xffd83f80 + 1a604: 080c37ac stmeqda ip, {r2, r3, r5, r7, r8, r9, sl, ip, sp} + 1a608: e3a000af mov r0, #175 ; 0xaf + 1a60c: e3800c37 orr r0, r0, #14080 ; 0x3700 + 1a610: e3800703 orr r0, r0, #786432 ; 0xc0000 + 1a614: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1a618: e58d0438 str r0, [sp, #1080] + 1a61c: e28cc009 add ip, ip, #9 ; 0x9 + 1a620: e1a00fac mov r0, ip, lsr #31 + 1a624: e08ff100 add pc, pc, r0, lsl #2 + 1a628: 080c36e0 stmeqda ip, {r5, r6, r7, r9, sl, ip, sp} + 1a62c: ebf5a248 bl 0xffd82f54 + 1a630: eaffa0ab b 0x28e4 + 1a634: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 1a638: 00000000 andeq r0, r0, r0 + 1a63c: ebf5a64f bl 0xffd83f80 + 1a640: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 1a644: e59d0434 ldr r0, [sp, #1076] + 1a648: e2800f0d add r0, r0, #52 ; 0x34 + 1a64c: e58d0434 str r0, [sp, #1076] + 1a650: ebf5a64a bl 0xffd83f80 + 1a654: 08004730 stmeqda r0, {r4, r5, r8, r9, sl, lr} + 1a658: e59d9434 ldr r9, [sp, #1076] + 1a65c: e3c99003 bic r9, r9, #3 ; 0x3 + 1a660: e289000c add r0, r9, #12 ; 0xc + 1a664: e58d0434 str r0, [sp, #1076] + 1a668: e2890000 add r0, r9, #0 ; 0x0 + 1a66c: ebf5a4a9 bl 0xffd83918 + 1a670: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 1a674: e1a06000 mov r6, r0 + 1a678: e2890004 add r0, r9, #4 ; 0x4 + 1a67c: ebf5a4a5 bl 0xffd83918 + 1a680: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 1a684: e1a07000 mov r7, r0 + 1a688: e2890008 add r0, r9, #8 ; 0x8 + 1a68c: ebf5a4a1 bl 0xffd83918 + 1a690: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 1a694: e1a08000 mov r8, r0 + 1a698: ebf5a638 bl 0xffd83f80 + 1a69c: 08004732 stmeqda r0, {r1, r4, r5, r8, r9, sl, lr} + 1a6a0: e1a00006 mov r0, r6 + 1a6a4: e58d0420 str r0, [sp, #1056] + 1a6a8: ebf5a634 bl 0xffd83f80 + 1a6ac: 08004734 stmeqda r0, {r2, r4, r5, r8, r9, sl, lr} + 1a6b0: e1a00007 mov r0, r7 + 1a6b4: e58d0424 str r0, [sp, #1060] + 1a6b8: ebf5a630 bl 0xffd83f80 + 1a6bc: 08004736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, lr} + 1a6c0: e1a00008 mov r0, r8 + 1a6c4: e58d0428 str r0, [sp, #1064] + 1a6c8: ebf5a62c bl 0xffd83f80 + 1a6cc: 08004738 stmeqda r0, {r3, r4, r5, r8, r9, sl, lr} + 1a6d0: e59d9434 ldr r9, [sp, #1076] + 1a6d4: e3c99003 bic r9, r9, #3 ; 0x3 + 1a6d8: e2890010 add r0, r9, #16 ; 0x10 + 1a6dc: e58d0434 str r0, [sp, #1076] + 1a6e0: e2890000 add r0, r9, #0 ; 0x0 + 1a6e4: ebf5a48b bl 0xffd83918 + 1a6e8: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1a6ec: e1a07000 mov r7, r0 + 1a6f0: e2890004 add r0, r9, #4 ; 0x4 + 1a6f4: ebf5a487 bl 0xffd83918 + 1a6f8: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1a6fc: e1a08000 mov r8, r0 + 1a700: e2890008 add r0, r9, #8 ; 0x8 + 1a704: ebf5a483 bl 0xffd83918 + 1a708: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1a70c: e58d0418 str r0, [sp, #1048] + 1a710: e289000c add r0, r9, #12 ; 0xc + 1a714: ebf5a47f bl 0xffd83918 + 1a718: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1a71c: e58d041c str r0, [sp, #1052] + 1a720: ebf5a616 bl 0xffd83f80 + 1a724: 0800473a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, lr} + 1a728: e59d9434 ldr r9, [sp, #1076] + 1a72c: e3c99003 bic r9, r9, #3 ; 0x3 + 1a730: e2890004 add r0, r9, #4 ; 0x4 + 1a734: e58d0434 str r0, [sp, #1076] + 1a738: e2890000 add r0, r9, #0 ; 0x0 + 1a73c: ebf5a475 bl 0xffd83918 + 1a740: 0800473e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, lr} + 1a744: e1a03000 mov r3, r0 + 1a748: ebf5a60c bl 0xffd83f80 + 1a74c: 0800473c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, lr} + 1a750: e1a00003 mov r0, r3 + 1a754: e28cc020 add ip, ip, #32 ; 0x20 + 1a758: eaf5a25c b 0xffd830d0 + 1a75c: 080044ee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, lr} + 1a760: 00000000 andeq r0, r0, r0 + 1a764: ebf5a605 bl 0xffd83f80 + 1a768: 080044ee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, lr} + 1a76c: e3b07000 movs r7, #0 ; 0x0 + 1a770: ebf5a602 bl 0xffd83f80 + 1a774: 080044f0 stmeqda r0, {r4, r5, r6, r7, sl, lr} + 1a778: e1a00007 mov r0, r7 + 1a77c: e58d0428 str r0, [sp, #1064] + 1a780: ebf5a5fe bl 0xffd83f80 + 1a784: 080044f2 stmeqda r0, {r1, r4, r5, r6, r7, sl, lr} + 1a788: e3550000 cmp r5, #0 ; 0x0 + 1a78c: ebf5a5fb bl 0xffd83f80 + 1a790: 080044f4 stmeqda r0, {r2, r4, r5, r6, r7, sl, lr} + 1a794: e28cc00c add ip, ip, #12 ; 0xc + 1a798: aa000004 bge 0x1a7b0 + 1a79c: e1a00fac mov r0, ip, lsr #31 + 1a7a0: e08ff100 add pc, pc, r0, lsl #2 + 1a7a4: 08004502 stmeqda r0, {r1, r8, sl, lr} + 1a7a8: ebf5a1e9 bl 0xffd82f54 + 1a7ac: ea00001d b 0x1a828 + 1a7b0: ebf5a5f2 bl 0xffd83f80 + 1a7b4: 080044f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, sl, lr} + 1a7b8: e3b04012 movs r4, #18 ; 0x12 + 1a7bc: ebf5a5ef bl 0xffd83f80 + 1a7c0: 080044f8 stmeqda r0, {r3, r4, r5, r6, r7, sl, lr} + 1a7c4: e59d041c ldr r0, [sp, #1052] + 1a7c8: e0800004 add r0, r0, r4 + 1a7cc: ebf5a43a bl 0xffd838bc + 1a7d0: 080044fc stmeqda r0, {r2, r3, r4, r5, r6, r7, sl, lr} + 1a7d4: e1a03000 mov r3, r0 + 1a7d8: ebf5a5e8 bl 0xffd83f80 + 1a7dc: 080044fa stmeqda r0, {r1, r3, r4, r5, r6, r7, sl, lr} + 1a7e0: e1550003 cmp r5, r3 + 1a7e4: ebf5a5e5 bl 0xffd83f80 + 1a7e8: 080044fc stmeqda r0, {r2, r3, r4, r5, r6, r7, sl, lr} + 1a7ec: e28cc00e add ip, ip, #14 ; 0xe + 1a7f0: ba000004 blt 0x1a808 + 1a7f4: e1a00fac mov r0, ip, lsr #31 + 1a7f8: e08ff100 add pc, pc, r0, lsl #2 + 1a7fc: 08004502 stmeqda r0, {r1, r8, sl, lr} + 1a800: ebf5a1d3 bl 0xffd82f54 + 1a804: ea000007 b 0x1a828 + 1a808: ebf5a5dc bl 0xffd83f80 + 1a80c: 080044fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, sl, lr} + 1a810: e3b07001 movs r7, #1 ; 0x1 + 1a814: ebf5a5d9 bl 0xffd83f80 + 1a818: 08004500 stmeqda r0, {r8, sl, lr} + 1a81c: e1a00007 mov r0, r7 + 1a820: e58d0428 str r0, [sp, #1064] + 1a824: e28cc006 add ip, ip, #6 ; 0x6 + 1a828: ebf5a5d4 bl 0xffd83f80 + 1a82c: 08004502 stmeqda r0, {r1, r8, sl, lr} + 1a830: e3b04010 movs r4, #16 ; 0x10 + 1a834: ebf5a5d1 bl 0xffd83f80 + 1a838: 08004504 stmeqda r0, {r2, r8, sl, lr} + 1a83c: e59d041c ldr r0, [sp, #1052] + 1a840: e0800004 add r0, r0, r4 + 1a844: ebf5a41c bl 0xffd838bc + 1a848: 08004508 stmeqda r0, {r3, r8, sl, lr} + 1a84c: e1a03000 mov r3, r0 + 1a850: ebf5a5ca bl 0xffd83f80 + 1a854: 08004506 stmeqda r0, {r1, r2, r8, sl, lr} + 1a858: e1a01003 mov r1, r3 + 1a85c: e0130593 muls r3, r3, r5 + 1a860: ebf5a5c6 bl 0xffd83f80 + 1a864: 08004508 stmeqda r0, {r3, r8, sl, lr} + 1a868: e1b03083 movs r3, r3, lsl #1 + 1a86c: ebf5a5c3 bl 0xffd83f80 + 1a870: 0800450a stmeqda r0, {r1, r3, r8, sl, lr} + 1a874: e59d041c ldr r0, [sp, #1052] + 1a878: e280000c add r0, r0, #12 ; 0xc + 1a87c: ebf5a425 bl 0xffd83918 + 1a880: 0800450e stmeqda r0, {r1, r2, r3, r8, sl, lr} + 1a884: e1a04000 mov r4, r0 + 1a888: ebf5a5bc bl 0xffd83f80 + 1a88c: 0800450c stmeqda r0, {r2, r3, r8, sl, lr} + 1a890: e1a01004 mov r1, r4 + 1a894: e0944003 adds r4, r4, r3 + 1a898: ebf5a5b8 bl 0xffd83f80 + 1a89c: 0800450e stmeqda r0, {r1, r2, r3, r8, sl, lr} + 1a8a0: e1a00004 mov r0, r4 + 1a8a4: e58d0420 str r0, [sp, #1056] + 1a8a8: ebf5a5b4 bl 0xffd83f80 + 1a8ac: 08004510 stmeqda r0, {r4, r8, sl, lr} + 1a8b0: e1a01006 mov r1, r6 + 1a8b4: e2963000 adds r3, r6, #0 ; 0x0 + 1a8b8: ebf5a5b0 bl 0xffd83f80 + 1a8bc: 08004512 stmeqda r0, {r1, r4, r8, sl, lr} + 1a8c0: e59d0434 ldr r0, [sp, #1076] + 1a8c4: e2800f02 add r0, r0, #8 ; 0x8 + 1a8c8: ebf5a412 bl 0xffd83918 + 1a8cc: 08004516 stmeqda r0, {r1, r2, r4, r8, sl, lr} + 1a8d0: e1a05000 mov r5, r0 + 1a8d4: ebf5a5a9 bl 0xffd83f80 + 1a8d8: 08004514 stmeqda r0, {r2, r4, r8, sl, lr} + 1a8dc: e1a01003 mov r1, r3 + 1a8e0: e0133005 ands r3, r3, r5 + 1a8e4: ebf5a5a5 bl 0xffd83f80 + 1a8e8: 08004516 stmeqda r0, {r1, r2, r4, r8, sl, lr} + 1a8ec: e59d0434 ldr r0, [sp, #1076] + 1a8f0: e2800f03 add r0, r0, #12 ; 0xc + 1a8f4: ebf5a407 bl 0xffd83918 + 1a8f8: 0800451a stmeqda r0, {r1, r3, r4, r8, sl, lr} + 1a8fc: e1a07000 mov r7, r0 + 1a900: ebf5a59e bl 0xffd83f80 + 1a904: 08004518 stmeqda r0, {r3, r4, r8, sl, lr} + 1a908: e1a01007 mov r1, r7 + 1a90c: e2974000 adds r4, r7, #0 ; 0x0 + 1a910: ebf5a59a bl 0xffd83f80 + 1a914: 0800451a stmeqda r0, {r1, r3, r4, r8, sl, lr} + 1a918: e1a01004 mov r1, r4 + 1a91c: e0140394 muls r4, r4, r3 + 1a920: ebf5a596 bl 0xffd83f80 + 1a924: 0800451c stmeqda r0, {r2, r3, r4, r8, sl, lr} + 1a928: e59d041c ldr r0, [sp, #1052] + 1a92c: e2800014 add r0, r0, #20 ; 0x14 + 1a930: ebf5a3f8 bl 0xffd83918 + 1a934: 08004520 stmeqda r0, {r5, r8, sl, lr} + 1a938: e1a03000 mov r3, r0 + 1a93c: ebf5a58f bl 0xffd83f80 + 1a940: 0800451e stmeqda r0, {r1, r2, r3, r4, r8, sl, lr} + 1a944: e1a01003 mov r1, r3 + 1a948: e0933004 adds r3, r3, r4 + 1a94c: ebf5a58b bl 0xffd83f80 + 1a950: 08004520 stmeqda r0, {r5, r8, sl, lr} + 1a954: e1a00003 mov r0, r3 + 1a958: e58d0424 str r0, [sp, #1060] + 1a95c: ebf5a587 bl 0xffd83f80 + 1a960: 08004522 stmeqda r0, {r1, r5, r8, sl, lr} + 1a964: e1a01006 mov r1, r6 + 1a968: e2965000 adds r5, r6, #0 ; 0x0 + 1a96c: ebf5a583 bl 0xffd83f80 + 1a970: 08004524 stmeqda r0, {r2, r5, r8, sl, lr} + 1a974: e3b03003 movs r3, #3 ; 0x3 + 1a978: ebf5a580 bl 0xffd83f80 + 1a97c: 08004526 stmeqda r0, {r1, r2, r5, r8, sl, lr} + 1a980: e1a01005 mov r1, r5 + 1a984: e0155003 ands r5, r5, r3 + 1a988: ebf5a57c bl 0xffd83f80 + 1a98c: 08004528 stmeqda r0, {r3, r5, r8, sl, lr} + 1a990: e59d0434 ldr r0, [sp, #1076] + 1a994: e2800f00 add r0, r0, #0 ; 0x0 + 1a998: ebf5a3de bl 0xffd83918 + 1a99c: 0800452c stmeqda r0, {r2, r3, r5, r8, sl, lr} + 1a9a0: e1a08000 mov r8, r0 + 1a9a4: ebf5a575 bl 0xffd83f80 + 1a9a8: 0800452a stmeqda r0, {r1, r3, r5, r8, sl, lr} + 1a9ac: e1a01006 mov r1, r6 + 1a9b0: e2966001 adds r6, r6, #1 ; 0x1 + 1a9b4: ebf5a571 bl 0xffd83f80 + 1a9b8: 0800452c stmeqda r0, {r2, r3, r5, r8, sl, lr} + 1a9bc: e59d0434 ldr r0, [sp, #1076] + 1a9c0: e2800f0b add r0, r0, #44 ; 0x2c + 1a9c4: e1a01006 mov r1, r6 + 1a9c8: ebf5a2ff bl 0xffd835cc + 1a9cc: 0800452e stmeqda r0, {r1, r2, r3, r5, r8, sl, lr} + 1a9d0: ebf5a56a bl 0xffd83f80 + 1a9d4: 0800452e stmeqda r0, {r1, r2, r3, r5, r8, sl, lr} + 1a9d8: e59d0434 ldr r0, [sp, #1076] + 1a9dc: e2800f01 add r0, r0, #4 ; 0x4 + 1a9e0: ebf5a3cc bl 0xffd83918 + 1a9e4: 08004532 stmeqda r0, {r1, r4, r5, r8, sl, lr} + 1a9e8: e1a04000 mov r4, r0 + 1a9ec: ebf5a563 bl 0xffd83f80 + 1a9f0: 08004530 stmeqda r0, {r4, r5, r8, sl, lr} + 1a9f4: e1580004 cmp r8, r4 + 1a9f8: ebf5a560 bl 0xffd83f80 + 1a9fc: 08004532 stmeqda r0, {r1, r4, r5, r8, sl, lr} + 1aa00: e28cc05a add ip, ip, #90 ; 0x5a + 1aa04: da000004 ble 0x1aa1c + 1aa08: e1a00fac mov r0, ip, lsr #31 + 1aa0c: e08ff100 add pc, pc, r0, lsl #2 + 1aa10: 080045ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, lr} + 1aa14: ebf5a14e bl 0xffd82f54 + 1aa18: ea000077 b 0x1abfc + 1aa1c: ebf5a557 bl 0xffd83f80 + 1aa20: 08004534 stmeqda r0, {r2, r4, r5, r8, sl, lr} + 1aa24: e1b06105 movs r6, r5, lsl #2 + 1aa28: ebf5a554 bl 0xffd83f80 + 1aa2c: 08004536 stmeqda r0, {r1, r2, r4, r5, r8, sl, lr} + 1aa30: e1a01008 mov r1, r8 + 1aa34: e2983000 adds r3, r8, #0 ; 0x0 + 1aa38: ebf5a550 bl 0xffd83f80 + 1aa3c: 08004538 stmeqda r0, {r3, r4, r5, r8, sl, lr} + 1aa40: e59d0434 ldr r0, [sp, #1076] + 1aa44: e2800f02 add r0, r0, #8 ; 0x8 + 1aa48: ebf5a3b2 bl 0xffd83918 + 1aa4c: 0800453c stmeqda r0, {r2, r3, r4, r5, r8, sl, lr} + 1aa50: e1a05000 mov r5, r0 + 1aa54: ebf5a549 bl 0xffd83f80 + 1aa58: 0800453a stmeqda r0, {r1, r3, r4, r5, r8, sl, lr} + 1aa5c: e1a01003 mov r1, r3 + 1aa60: e0133005 ands r3, r3, r5 + 1aa64: ebf5a545 bl 0xffd83f80 + 1aa68: 0800453c stmeqda r0, {r2, r3, r4, r5, r8, sl, lr} + 1aa6c: e59d1424 ldr r1, [sp, #1060] + 1aa70: e1a07001 mov r7, r1 + 1aa74: ebf5a541 bl 0xffd83f80 + 1aa78: 0800453e stmeqda r0, {r1, r2, r3, r4, r5, r8, sl, lr} + 1aa7c: e1a01007 mov r1, r7 + 1aa80: e0970003 adds r0, r7, r3 + 1aa84: e58d0418 str r0, [sp, #1048] + 1aa88: ebf5a53c bl 0xffd83f80 + 1aa8c: 08004540 stmeqda r0, {r6, r8, sl, lr} + 1aa90: e59d1428 ldr r1, [sp, #1064] + 1aa94: e1a03001 mov r3, r1 + 1aa98: ebf5a538 bl 0xffd83f80 + 1aa9c: 08004542 stmeqda r0, {r1, r6, r8, sl, lr} + 1aaa0: e3530000 cmp r3, #0 ; 0x0 + 1aaa4: ebf5a535 bl 0xffd83f80 + 1aaa8: 08004544 stmeqda r0, {r2, r6, r8, sl, lr} + 1aaac: e28cc01d add ip, ip, #29 ; 0x1d + 1aab0: 1a000004 bne 0x1aac8 + 1aab4: e1a00fac mov r0, ip, lsr #31 + 1aab8: e08ff100 add pc, pc, r0, lsl #2 + 1aabc: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1aac0: ebf5a123 bl 0xffd82f54 + 1aac4: ea0000c5 b 0x1ade0 + 1aac8: ebf5a52c bl 0xffd83f80 + 1aacc: 08004546 stmeqda r0, {r1, r2, r6, r8, sl, lr} + 1aad0: e1b05148 movs r5, r8, asr #2 + 1aad4: ebf5a529 bl 0xffd83f80 + 1aad8: 08004548 stmeqda r0, {r3, r6, r8, sl, lr} + 1aadc: e59d041c ldr r0, [sp, #1052] + 1aae0: e2800000 add r0, r0, #0 ; 0x0 + 1aae4: ebf5a35f bl 0xffd83868 + 1aae8: 0800454c stmeqda r0, {r2, r3, r6, r8, sl, lr} + 1aaec: e1a03000 mov r3, r0 + 1aaf0: ebf5a522 bl 0xffd83f80 + 1aaf4: 0800454a stmeqda r0, {r1, r3, r6, r8, sl, lr} + 1aaf8: e3b07080 movs r7, #128 ; 0x80 + 1aafc: ebf5a51f bl 0xffd83f80 + 1ab00: 0800454c stmeqda r0, {r2, r3, r6, r8, sl, lr} + 1ab04: e1b07187 movs r7, r7, lsl #3 + 1ab08: ebf5a51c bl 0xffd83f80 + 1ab0c: 0800454e stmeqda r0, {r1, r2, r3, r6, r8, sl, lr} + 1ab10: e1a01007 mov r1, r7 + 1ab14: e2974000 adds r4, r7, #0 ; 0x0 + 1ab18: ebf5a518 bl 0xffd83f80 + 1ab1c: 08004550 stmeqda r0, {r4, r6, r8, sl, lr} + 1ab20: e1a01003 mov r1, r3 + 1ab24: e0133004 ands r3, r3, r4 + 1ab28: ebf5a514 bl 0xffd83f80 + 1ab2c: 08004552 stmeqda r0, {r1, r4, r6, r8, sl, lr} + 1ab30: e3530000 cmp r3, #0 ; 0x0 + 1ab34: ebf5a511 bl 0xffd83f80 + 1ab38: 08004554 stmeqda r0, {r2, r4, r6, r8, sl, lr} + 1ab3c: e28cc01a add ip, ip, #26 ; 0x1a + 1ab40: 1a000004 bne 0x1ab58 + 1ab44: e1a00fac mov r0, ip, lsr #31 + 1ab48: e08ff100 add pc, pc, r0, lsl #2 + 1ab4c: 08004588 stmeqda r0, {r3, r7, r8, sl, lr} + 1ab50: ebf5a0ff bl 0xffd82f54 + 1ab54: ea000160 b 0x1b0dc + 1ab58: ebf5a508 bl 0xffd83f80 + 1ab5c: 08004556 stmeqda r0, {r1, r2, r4, r6, r8, sl, lr} + 1ab60: e3b03010 movs r3, #16 ; 0x10 + 1ab64: ebf5a505 bl 0xffd83f80 + 1ab68: 08004558 stmeqda r0, {r3, r4, r6, r8, sl, lr} + 1ab6c: e59d041c ldr r0, [sp, #1052] + 1ab70: e0800003 add r0, r0, r3 + 1ab74: ebf5a350 bl 0xffd838bc + 1ab78: 0800455c stmeqda r0, {r2, r3, r4, r6, r8, sl, lr} + 1ab7c: e1a07000 mov r7, r0 + 1ab80: ebf5a4fe bl 0xffd83f80 + 1ab84: 0800455a stmeqda r0, {r1, r3, r4, r6, r8, sl, lr} + 1ab88: e1a01005 mov r1, r5 + 1ab8c: e2953000 adds r3, r5, #0 ; 0x0 + 1ab90: ebf5a4fa bl 0xffd83f80 + 1ab94: 0800455c stmeqda r0, {r2, r3, r4, r6, r8, sl, lr} + 1ab98: e1a01007 mov r1, r7 + 1ab9c: e2974000 adds r4, r7, #0 ; 0x0 + 1aba0: ebf5a4f6 bl 0xffd83f80 + 1aba4: 0800455e stmeqda r0, {r1, r2, r3, r4, r6, r8, sl, lr} + 1aba8: e59d0434 ldr r0, [sp, #1076] + 1abac: e2800f0c add r0, r0, #48 ; 0x30 + 1abb0: e1a01006 mov r1, r6 + 1abb4: ebf5a284 bl 0xffd835cc + 1abb8: 08004560 stmeqda r0, {r5, r6, r8, sl, lr} + 1abbc: ebf5a4ef bl 0xffd83f80 + 1abc0: 08004560 stmeqda r0, {r5, r6, r8, sl, lr} + 1abc4: ebf5a4ed bl 0xffd83f80 + 1abc8: 08004562 stmeqda r0, {r1, r5, r6, r8, sl, lr} + 1abcc: e3a00065 mov r0, #101 ; 0x65 + 1abd0: e3800c45 orr r0, r0, #17664 ; 0x4500 + 1abd4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1abd8: e58d0438 str r0, [sp, #1080] + 1abdc: e28cc018 add ip, ip, #24 ; 0x18 + 1abe0: e1a00fac mov r0, ip, lsr #31 + 1abe4: e08ff100 add pc, pc, r0, lsl #2 + 1abe8: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 1abec: ebf5a0d8 bl 0xffd82f54 + 1abf0: eafffc8d b 0x19e2c + 1abf4: 080045ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, lr} + 1abf8: 00000000 andeq r0, r0, r0 + 1abfc: ebf5a4df bl 0xffd83f80 + 1ac00: 080045ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, lr} + 1ac04: e59d0434 ldr r0, [sp, #1076] + 1ac08: e2800f0b add r0, r0, #44 ; 0x2c + 1ac0c: ebf5a341 bl 0xffd83918 + 1ac10: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1ac14: e1a06000 mov r6, r0 + 1ac18: ebf5a4d8 bl 0xffd83f80 + 1ac1c: 080045bc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl, lr} + 1ac20: e59d0434 ldr r0, [sp, #1076] + 1ac24: e2800f15 add r0, r0, #84 ; 0x54 + 1ac28: ebf5a33a bl 0xffd83918 + 1ac2c: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1ac30: e1a04000 mov r4, r0 + 1ac34: ebf5a4d1 bl 0xffd83f80 + 1ac38: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1ac3c: e1560004 cmp r6, r4 + 1ac40: ebf5a4ce bl 0xffd83f80 + 1ac44: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1ac48: e28cc010 add ip, ip, #16 ; 0x10 + 1ac4c: da000004 ble 0x1ac64 + 1ac50: e1a00fac mov r0, ip, lsr #31 + 1ac54: e08ff100 add pc, pc, r0, lsl #2 + 1ac58: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1ac5c: ebf5a0bc bl 0xffd82f54 + 1ac60: ea000007 b 0x1ac84 + 1ac64: ebf5a4c5 bl 0xffd83f80 + 1ac68: 080045c2 stmeqda r0, {r1, r6, r7, r8, sl, lr} + 1ac6c: e28cc003 add ip, ip, #3 ; 0x3 + 1ac70: e1a00fac mov r0, ip, lsr #31 + 1ac74: e08ff100 add pc, pc, r0, lsl #2 + 1ac78: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 1ac7c: ebf5a0b4 bl 0xffd82f54 + 1ac80: ea000009 b 0x1acac + 1ac84: ebf5a4bd bl 0xffd83f80 + 1ac88: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1ac8c: e28cc003 add ip, ip, #3 ; 0x3 + 1ac90: e1a00fac mov r0, ip, lsr #31 + 1ac94: e08ff100 add pc, pc, r0, lsl #2 + 1ac98: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 1ac9c: ebf5a0ac bl 0xffd82f54 + 1aca0: eafffe65 b 0x1a63c + 1aca4: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 1aca8: 00000000 andeq r0, r0, r0 + 1acac: ebf5a4b3 bl 0xffd83f80 + 1acb0: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 1acb4: e1b05146 movs r5, r6, asr #2 + 1acb8: ebf5a4b0 bl 0xffd83f80 + 1acbc: 080044c2 stmeqda r0, {r1, r6, r7, sl, lr} + 1acc0: e59d041c ldr r0, [sp, #1052] + 1acc4: e2800000 add r0, r0, #0 ; 0x0 + 1acc8: ebf5a2e6 bl 0xffd83868 + 1accc: 080044c6 stmeqda r0, {r1, r2, r6, r7, sl, lr} + 1acd0: e1a03000 mov r3, r0 + 1acd4: ebf5a4a9 bl 0xffd83f80 + 1acd8: 080044c4 stmeqda r0, {r2, r6, r7, sl, lr} + 1acdc: e3b07080 movs r7, #128 ; 0x80 + 1ace0: ebf5a4a6 bl 0xffd83f80 + 1ace4: 080044c6 stmeqda r0, {r1, r2, r6, r7, sl, lr} + 1ace8: e1b07107 movs r7, r7, lsl #2 + 1acec: ebf5a4a3 bl 0xffd83f80 + 1acf0: 080044c8 stmeqda r0, {r3, r6, r7, sl, lr} + 1acf4: e1a01007 mov r1, r7 + 1acf8: e2974000 adds r4, r7, #0 ; 0x0 + 1acfc: ebf5a49f bl 0xffd83f80 + 1ad00: 080044ca stmeqda r0, {r1, r3, r6, r7, sl, lr} + 1ad04: e1a01003 mov r1, r3 + 1ad08: e0133004 ands r3, r3, r4 + 1ad0c: ebf5a49b bl 0xffd83f80 + 1ad10: 080044cc stmeqda r0, {r2, r3, r6, r7, sl, lr} + 1ad14: e3530000 cmp r3, #0 ; 0x0 + 1ad18: ebf5a498 bl 0xffd83f80 + 1ad1c: 080044ce stmeqda r0, {r1, r2, r3, r6, r7, sl, lr} + 1ad20: e28cc01a add ip, ip, #26 ; 0x1a + 1ad24: 1a000004 bne 0x1ad3c + 1ad28: e1a00fac mov r0, ip, lsr #31 + 1ad2c: e08ff100 add pc, pc, r0, lsl #2 + 1ad30: 080044ee stmeqda r0, {r1, r2, r3, r5, r6, r7, sl, lr} + 1ad34: ebf5a086 bl 0xffd82f54 + 1ad38: eafffe89 b 0x1a764 + 1ad3c: ebf5a48f bl 0xffd83f80 + 1ad40: 080044d0 stmeqda r0, {r4, r6, r7, sl, lr} + 1ad44: e3b03012 movs r3, #18 ; 0x12 + 1ad48: ebf5a48c bl 0xffd83f80 + 1ad4c: 080044d2 stmeqda r0, {r1, r4, r6, r7, sl, lr} + 1ad50: e59d041c ldr r0, [sp, #1052] + 1ad54: e0800003 add r0, r0, r3 + 1ad58: ebf5a2d7 bl 0xffd838bc + 1ad5c: 080044d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, lr} + 1ad60: e1a07000 mov r7, r0 + 1ad64: ebf5a485 bl 0xffd83f80 + 1ad68: 080044d4 stmeqda r0, {r2, r4, r6, r7, sl, lr} + 1ad6c: e1a01005 mov r1, r5 + 1ad70: e2953000 adds r3, r5, #0 ; 0x0 + 1ad74: ebf5a481 bl 0xffd83f80 + 1ad78: 080044d6 stmeqda r0, {r1, r2, r4, r6, r7, sl, lr} + 1ad7c: e1a01007 mov r1, r7 + 1ad80: e2974000 adds r4, r7, #0 ; 0x0 + 1ad84: ebf5a47d bl 0xffd83f80 + 1ad88: 080044d8 stmeqda r0, {r3, r4, r6, r7, sl, lr} + 1ad8c: e59d0434 ldr r0, [sp, #1076] + 1ad90: e2800f0c add r0, r0, #48 ; 0x30 + 1ad94: e1a01006 mov r1, r6 + 1ad98: ebf5a20b bl 0xffd835cc + 1ad9c: 080044da stmeqda r0, {r1, r3, r4, r6, r7, sl, lr} + 1ada0: ebf5a476 bl 0xffd83f80 + 1ada4: 080044da stmeqda r0, {r1, r3, r4, r6, r7, sl, lr} + 1ada8: ebf5a474 bl 0xffd83f80 + 1adac: 080044dc stmeqda r0, {r2, r3, r4, r6, r7, sl, lr} + 1adb0: e3a000df mov r0, #223 ; 0xdf + 1adb4: e3800b11 orr r0, r0, #17408 ; 0x4400 + 1adb8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1adbc: e58d0438 str r0, [sp, #1080] + 1adc0: e28cc018 add ip, ip, #24 ; 0x18 + 1adc4: e1a00fac mov r0, ip, lsr #31 + 1adc8: e08ff100 add pc, pc, r0, lsl #2 + 1adcc: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 1add0: ebf5a05f bl 0xffd82f54 + 1add4: eafffc14 b 0x19e2c + 1add8: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1addc: 00000000 andeq r0, r0, r0 + 1ade0: ebf5a466 bl 0xffd83f80 + 1ade4: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1ade8: e59d0418 ldr r0, [sp, #1048] + 1adec: e2800000 add r0, r0, #0 ; 0x0 + 1adf0: e1a01003 mov r1, r3 + 1adf4: ebf5a1d4 bl 0xffd8354c + 1adf8: 080045b2 stmeqda r0, {r1, r4, r5, r7, r8, sl, lr} + 1adfc: ebf5a45f bl 0xffd83f80 + 1ae00: 080045b2 stmeqda r0, {r1, r4, r5, r7, r8, sl, lr} + 1ae04: e1a01008 mov r1, r8 + 1ae08: e2988002 adds r8, r8, #2 ; 0x2 + 1ae0c: ebf5a45b bl 0xffd83f80 + 1ae10: 080045b4 stmeqda r0, {r2, r4, r5, r7, r8, sl, lr} + 1ae14: e59d0434 ldr r0, [sp, #1076] + 1ae18: e2800f01 add r0, r0, #4 ; 0x4 + 1ae1c: ebf5a2bd bl 0xffd83918 + 1ae20: 080045b8 stmeqda r0, {r3, r4, r5, r7, r8, sl, lr} + 1ae24: e1a03000 mov r3, r0 + 1ae28: ebf5a454 bl 0xffd83f80 + 1ae2c: 080045b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl, lr} + 1ae30: e1580003 cmp r8, r3 + 1ae34: ebf5a451 bl 0xffd83f80 + 1ae38: 080045b8 stmeqda r0, {r3, r4, r5, r7, r8, sl, lr} + 1ae3c: e28cc012 add ip, ip, #18 ; 0x12 + 1ae40: ca000004 bgt 0x1ae58 + 1ae44: e1a00fac mov r0, ip, lsr #31 + 1ae48: e08ff100 add pc, pc, r0, lsl #2 + 1ae4c: 08004536 stmeqda r0, {r1, r2, r4, r5, r8, sl, lr} + 1ae50: ebf5a03f bl 0xffd82f54 + 1ae54: ea00002b b 0x1af08 + 1ae58: ebf5a448 bl 0xffd83f80 + 1ae5c: 080045ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, lr} + 1ae60: e59d0434 ldr r0, [sp, #1076] + 1ae64: e2800f0b add r0, r0, #44 ; 0x2c + 1ae68: ebf5a2aa bl 0xffd83918 + 1ae6c: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1ae70: e1a06000 mov r6, r0 + 1ae74: ebf5a441 bl 0xffd83f80 + 1ae78: 080045bc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl, lr} + 1ae7c: e59d0434 ldr r0, [sp, #1076] + 1ae80: e2800f15 add r0, r0, #84 ; 0x54 + 1ae84: ebf5a2a3 bl 0xffd83918 + 1ae88: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1ae8c: e1a04000 mov r4, r0 + 1ae90: ebf5a43a bl 0xffd83f80 + 1ae94: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1ae98: e1560004 cmp r6, r4 + 1ae9c: ebf5a437 bl 0xffd83f80 + 1aea0: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1aea4: e28cc010 add ip, ip, #16 ; 0x10 + 1aea8: da000004 ble 0x1aec0 + 1aeac: e1a00fac mov r0, ip, lsr #31 + 1aeb0: e08ff100 add pc, pc, r0, lsl #2 + 1aeb4: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1aeb8: ebf5a025 bl 0xffd82f54 + 1aebc: ea000007 b 0x1aee0 + 1aec0: ebf5a42e bl 0xffd83f80 + 1aec4: 080045c2 stmeqda r0, {r1, r6, r7, r8, sl, lr} + 1aec8: e28cc003 add ip, ip, #3 ; 0x3 + 1aecc: e1a00fac mov r0, ip, lsr #31 + 1aed0: e08ff100 add pc, pc, r0, lsl #2 + 1aed4: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 1aed8: ebf5a01d bl 0xffd82f54 + 1aedc: eaffff72 b 0x1acac + 1aee0: ebf5a426 bl 0xffd83f80 + 1aee4: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1aee8: e28cc003 add ip, ip, #3 ; 0x3 + 1aeec: e1a00fac mov r0, ip, lsr #31 + 1aef0: e08ff100 add pc, pc, r0, lsl #2 + 1aef4: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 1aef8: ebf5a015 bl 0xffd82f54 + 1aefc: eafffdce b 0x1a63c + 1af00: 08004536 stmeqda r0, {r1, r2, r4, r5, r8, sl, lr} + 1af04: 00000000 andeq r0, r0, r0 + 1af08: ebf5a41c bl 0xffd83f80 + 1af0c: 08004536 stmeqda r0, {r1, r2, r4, r5, r8, sl, lr} + 1af10: e1a01008 mov r1, r8 + 1af14: e2983000 adds r3, r8, #0 ; 0x0 + 1af18: ebf5a418 bl 0xffd83f80 + 1af1c: 08004538 stmeqda r0, {r3, r4, r5, r8, sl, lr} + 1af20: e59d0434 ldr r0, [sp, #1076] + 1af24: e2800f02 add r0, r0, #8 ; 0x8 + 1af28: ebf5a27a bl 0xffd83918 + 1af2c: 0800453c stmeqda r0, {r2, r3, r4, r5, r8, sl, lr} + 1af30: e1a05000 mov r5, r0 + 1af34: ebf5a411 bl 0xffd83f80 + 1af38: 0800453a stmeqda r0, {r1, r3, r4, r5, r8, sl, lr} + 1af3c: e1a01003 mov r1, r3 + 1af40: e0133005 ands r3, r3, r5 + 1af44: ebf5a40d bl 0xffd83f80 + 1af48: 0800453c stmeqda r0, {r2, r3, r4, r5, r8, sl, lr} + 1af4c: e59d1424 ldr r1, [sp, #1060] + 1af50: e1a07001 mov r7, r1 + 1af54: ebf5a409 bl 0xffd83f80 + 1af58: 0800453e stmeqda r0, {r1, r2, r3, r4, r5, r8, sl, lr} + 1af5c: e1a01007 mov r1, r7 + 1af60: e0970003 adds r0, r7, r3 + 1af64: e58d0418 str r0, [sp, #1048] + 1af68: ebf5a404 bl 0xffd83f80 + 1af6c: 08004540 stmeqda r0, {r6, r8, sl, lr} + 1af70: e59d1428 ldr r1, [sp, #1064] + 1af74: e1a03001 mov r3, r1 + 1af78: ebf5a400 bl 0xffd83f80 + 1af7c: 08004542 stmeqda r0, {r1, r6, r8, sl, lr} + 1af80: e3530000 cmp r3, #0 ; 0x0 + 1af84: ebf5a3fd bl 0xffd83f80 + 1af88: 08004544 stmeqda r0, {r2, r6, r8, sl, lr} + 1af8c: e28cc01a add ip, ip, #26 ; 0x1a + 1af90: 1a000004 bne 0x1afa8 + 1af94: e1a00fac mov r0, ip, lsr #31 + 1af98: e08ff100 add pc, pc, r0, lsl #2 + 1af9c: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1afa0: ebf59feb bl 0xffd82f54 + 1afa4: eaffff8d b 0x1ade0 + 1afa8: ebf5a3f4 bl 0xffd83f80 + 1afac: 08004546 stmeqda r0, {r1, r2, r6, r8, sl, lr} + 1afb0: e1b05148 movs r5, r8, asr #2 + 1afb4: ebf5a3f1 bl 0xffd83f80 + 1afb8: 08004548 stmeqda r0, {r3, r6, r8, sl, lr} + 1afbc: e59d041c ldr r0, [sp, #1052] + 1afc0: e2800000 add r0, r0, #0 ; 0x0 + 1afc4: ebf5a227 bl 0xffd83868 + 1afc8: 0800454c stmeqda r0, {r2, r3, r6, r8, sl, lr} + 1afcc: e1a03000 mov r3, r0 + 1afd0: ebf5a3ea bl 0xffd83f80 + 1afd4: 0800454a stmeqda r0, {r1, r3, r6, r8, sl, lr} + 1afd8: e3b07080 movs r7, #128 ; 0x80 + 1afdc: ebf5a3e7 bl 0xffd83f80 + 1afe0: 0800454c stmeqda r0, {r2, r3, r6, r8, sl, lr} + 1afe4: e1b07187 movs r7, r7, lsl #3 + 1afe8: ebf5a3e4 bl 0xffd83f80 + 1afec: 0800454e stmeqda r0, {r1, r2, r3, r6, r8, sl, lr} + 1aff0: e1a01007 mov r1, r7 + 1aff4: e2974000 adds r4, r7, #0 ; 0x0 + 1aff8: ebf5a3e0 bl 0xffd83f80 + 1affc: 08004550 stmeqda r0, {r4, r6, r8, sl, lr} + 1b000: e1a01003 mov r1, r3 + 1b004: e0133004 ands r3, r3, r4 + 1b008: ebf5a3dc bl 0xffd83f80 + 1b00c: 08004552 stmeqda r0, {r1, r4, r6, r8, sl, lr} + 1b010: e3530000 cmp r3, #0 ; 0x0 + 1b014: ebf5a3d9 bl 0xffd83f80 + 1b018: 08004554 stmeqda r0, {r2, r4, r6, r8, sl, lr} + 1b01c: e28cc01a add ip, ip, #26 ; 0x1a + 1b020: 1a000004 bne 0x1b038 + 1b024: e1a00fac mov r0, ip, lsr #31 + 1b028: e08ff100 add pc, pc, r0, lsl #2 + 1b02c: 08004588 stmeqda r0, {r3, r7, r8, sl, lr} + 1b030: ebf59fc7 bl 0xffd82f54 + 1b034: ea000028 b 0x1b0dc + 1b038: ebf5a3d0 bl 0xffd83f80 + 1b03c: 08004556 stmeqda r0, {r1, r2, r4, r6, r8, sl, lr} + 1b040: e3b03010 movs r3, #16 ; 0x10 + 1b044: ebf5a3cd bl 0xffd83f80 + 1b048: 08004558 stmeqda r0, {r3, r4, r6, r8, sl, lr} + 1b04c: e59d041c ldr r0, [sp, #1052] + 1b050: e0800003 add r0, r0, r3 + 1b054: ebf5a218 bl 0xffd838bc + 1b058: 0800455c stmeqda r0, {r2, r3, r4, r6, r8, sl, lr} + 1b05c: e1a07000 mov r7, r0 + 1b060: ebf5a3c6 bl 0xffd83f80 + 1b064: 0800455a stmeqda r0, {r1, r3, r4, r6, r8, sl, lr} + 1b068: e1a01005 mov r1, r5 + 1b06c: e2953000 adds r3, r5, #0 ; 0x0 + 1b070: ebf5a3c2 bl 0xffd83f80 + 1b074: 0800455c stmeqda r0, {r2, r3, r4, r6, r8, sl, lr} + 1b078: e1a01007 mov r1, r7 + 1b07c: e2974000 adds r4, r7, #0 ; 0x0 + 1b080: ebf5a3be bl 0xffd83f80 + 1b084: 0800455e stmeqda r0, {r1, r2, r3, r4, r6, r8, sl, lr} + 1b088: e59d0434 ldr r0, [sp, #1076] + 1b08c: e2800f0c add r0, r0, #48 ; 0x30 + 1b090: e1a01006 mov r1, r6 + 1b094: ebf5a14c bl 0xffd835cc + 1b098: 08004560 stmeqda r0, {r5, r6, r8, sl, lr} + 1b09c: ebf5a3b7 bl 0xffd83f80 + 1b0a0: 08004560 stmeqda r0, {r5, r6, r8, sl, lr} + 1b0a4: ebf5a3b5 bl 0xffd83f80 + 1b0a8: 08004562 stmeqda r0, {r1, r5, r6, r8, sl, lr} + 1b0ac: e3a00065 mov r0, #101 ; 0x65 + 1b0b0: e3800c45 orr r0, r0, #17664 ; 0x4500 + 1b0b4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1b0b8: e58d0438 str r0, [sp, #1080] + 1b0bc: e28cc018 add ip, ip, #24 ; 0x18 + 1b0c0: e1a00fac mov r0, ip, lsr #31 + 1b0c4: e08ff100 add pc, pc, r0, lsl #2 + 1b0c8: 080c36e4 stmeqda ip, {r2, r5, r6, r7, r9, sl, ip, sp} + 1b0cc: ebf59fa0 bl 0xffd82f54 + 1b0d0: eafffb55 b 0x19e2c + 1b0d4: 08004588 stmeqda r0, {r3, r7, r8, sl, lr} + 1b0d8: 00000000 andeq r0, r0, r0 + 1b0dc: ebf5a3a7 bl 0xffd83f80 + 1b0e0: 08004588 stmeqda r0, {r3, r7, r8, sl, lr} + 1b0e4: e3550000 cmp r5, #0 ; 0x0 + 1b0e8: ebf5a3a4 bl 0xffd83f80 + 1b0ec: 0800458a stmeqda r0, {r1, r3, r7, r8, sl, lr} + 1b0f0: e28cc006 add ip, ip, #6 ; 0x6 + 1b0f4: aa000004 bge 0x1b10c + 1b0f8: e1a00fac mov r0, ip, lsr #31 + 1b0fc: e08ff100 add pc, pc, r0, lsl #2 + 1b100: 080045ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, lr} + 1b104: ebf59f92 bl 0xffd82f54 + 1b108: ea000051 b 0x1b254 + 1b10c: ebf5a39b bl 0xffd83f80 + 1b110: 0800458c stmeqda r0, {r2, r3, r7, r8, sl, lr} + 1b114: e3b04010 movs r4, #16 ; 0x10 + 1b118: ebf5a398 bl 0xffd83f80 + 1b11c: 0800458e stmeqda r0, {r1, r2, r3, r7, r8, sl, lr} + 1b120: e59d041c ldr r0, [sp, #1052] + 1b124: e0800004 add r0, r0, r4 + 1b128: ebf5a1e3 bl 0xffd838bc + 1b12c: 08004592 stmeqda r0, {r1, r4, r7, r8, sl, lr} + 1b130: e1a03000 mov r3, r0 + 1b134: ebf5a391 bl 0xffd83f80 + 1b138: 08004590 stmeqda r0, {r4, r7, r8, sl, lr} + 1b13c: e1550003 cmp r5, r3 + 1b140: ebf5a38e bl 0xffd83f80 + 1b144: 08004592 stmeqda r0, {r1, r4, r7, r8, sl, lr} + 1b148: e28cc00e add ip, ip, #14 ; 0xe + 1b14c: ba000004 blt 0x1b164 + 1b150: e1a00fac mov r0, ip, lsr #31 + 1b154: e08ff100 add pc, pc, r0, lsl #2 + 1b158: 080045ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, lr} + 1b15c: ebf59f7c bl 0xffd82f54 + 1b160: ea00003b b 0x1b254 + 1b164: ebf5a385 bl 0xffd83f80 + 1b168: 08004594 stmeqda r0, {r2, r4, r7, r8, sl, lr} + 1b16c: e1b03085 movs r3, r5, lsl #1 + 1b170: ebf5a382 bl 0xffd83f80 + 1b174: 08004596 stmeqda r0, {r1, r2, r4, r7, r8, sl, lr} + 1b178: e59d1420 ldr r1, [sp, #1056] + 1b17c: e0833001 add r3, r3, r1 + 1b180: ebf5a37e bl 0xffd83f80 + 1b184: 08004598 stmeqda r0, {r3, r4, r7, r8, sl, lr} + 1b188: e2830000 add r0, r3, #0 ; 0x0 + 1b18c: ebf5a1b5 bl 0xffd83868 + 1b190: 0800459c stmeqda r0, {r2, r3, r4, r7, r8, sl, lr} + 1b194: e1a03000 mov r3, r0 + 1b198: ebf5a378 bl 0xffd83f80 + 1b19c: 0800459a stmeqda r0, {r1, r3, r4, r7, r8, sl, lr} + 1b1a0: e1a01008 mov r1, r8 + 1b1a4: e2984000 adds r4, r8, #0 ; 0x0 + 1b1a8: ebf5a374 bl 0xffd83f80 + 1b1ac: 0800459c stmeqda r0, {r2, r3, r4, r7, r8, sl, lr} + 1b1b0: e3b05003 movs r5, #3 ; 0x3 + 1b1b4: ebf5a371 bl 0xffd83f80 + 1b1b8: 0800459e stmeqda r0, {r1, r2, r3, r4, r7, r8, sl, lr} + 1b1bc: e1a01004 mov r1, r4 + 1b1c0: e0144005 ands r4, r4, r5 + 1b1c4: ebf5a36d bl 0xffd83f80 + 1b1c8: 080045a0 stmeqda r0, {r5, r7, r8, sl, lr} + 1b1cc: e1b03203 movs r3, r3, lsl #4 + 1b1d0: ebf5a36a bl 0xffd83f80 + 1b1d4: 080045a2 stmeqda r0, {r1, r5, r7, r8, sl, lr} + 1b1d8: e59d0434 ldr r0, [sp, #1076] + 1b1dc: e2800f04 add r0, r0, #16 ; 0x10 + 1b1e0: ebf5a1cc bl 0xffd83918 + 1b1e4: 080045a6 stmeqda r0, {r1, r2, r5, r7, r8, sl, lr} + 1b1e8: e1a07000 mov r7, r0 + 1b1ec: ebf5a363 bl 0xffd83f80 + 1b1f0: 080045a4 stmeqda r0, {r2, r5, r7, r8, sl, lr} + 1b1f4: e1a01003 mov r1, r3 + 1b1f8: e0933007 adds r3, r3, r7 + 1b1fc: ebf5a35f bl 0xffd83f80 + 1b200: 080045a6 stmeqda r0, {r1, r2, r5, r7, r8, sl, lr} + 1b204: e1a01006 mov r1, r6 + 1b208: e0963003 adds r3, r6, r3 + 1b20c: ebf5a35b bl 0xffd83f80 + 1b210: 080045a8 stmeqda r0, {r3, r5, r7, r8, sl, lr} + 1b214: e1a01003 mov r1, r3 + 1b218: e0933004 adds r3, r3, r4 + 1b21c: ebf5a357 bl 0xffd83f80 + 1b220: 080045aa stmeqda r0, {r1, r3, r5, r7, r8, sl, lr} + 1b224: e2830000 add r0, r3, #0 ; 0x0 + 1b228: ebf5a18e bl 0xffd83868 + 1b22c: 080045ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, lr} + 1b230: e1a03000 mov r3, r0 + 1b234: ebf5a351 bl 0xffd83f80 + 1b238: 080045ac stmeqda r0, {r2, r3, r5, r7, r8, sl, lr} + 1b23c: e28cc02d add ip, ip, #45 ; 0x2d + 1b240: e1a00fac mov r0, ip, lsr #31 + 1b244: e08ff100 add pc, pc, r0, lsl #2 + 1b248: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1b24c: ebf59f40 bl 0xffd82f54 + 1b250: ea000003 b 0x1b264 + 1b254: ebf5a349 bl 0xffd83f80 + 1b258: 080045ae stmeqda r0, {r1, r2, r3, r5, r7, r8, sl, lr} + 1b25c: e3b03000 movs r3, #0 ; 0x0 + 1b260: e28cc003 add ip, ip, #3 ; 0x3 + 1b264: ebf5a345 bl 0xffd83f80 + 1b268: 080045b0 stmeqda r0, {r4, r5, r7, r8, sl, lr} + 1b26c: e59d0418 ldr r0, [sp, #1048] + 1b270: e2800000 add r0, r0, #0 ; 0x0 + 1b274: e1a01003 mov r1, r3 + 1b278: ebf5a0b3 bl 0xffd8354c + 1b27c: 080045b2 stmeqda r0, {r1, r4, r5, r7, r8, sl, lr} + 1b280: ebf5a33e bl 0xffd83f80 + 1b284: 080045b2 stmeqda r0, {r1, r4, r5, r7, r8, sl, lr} + 1b288: e1a01008 mov r1, r8 + 1b28c: e2988002 adds r8, r8, #2 ; 0x2 + 1b290: ebf5a33a bl 0xffd83f80 + 1b294: 080045b4 stmeqda r0, {r2, r4, r5, r7, r8, sl, lr} + 1b298: e59d0434 ldr r0, [sp, #1076] + 1b29c: e2800f01 add r0, r0, #4 ; 0x4 + 1b2a0: ebf5a19c bl 0xffd83918 + 1b2a4: 080045b8 stmeqda r0, {r3, r4, r5, r7, r8, sl, lr} + 1b2a8: e1a03000 mov r3, r0 + 1b2ac: ebf5a333 bl 0xffd83f80 + 1b2b0: 080045b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, sl, lr} + 1b2b4: e1580003 cmp r8, r3 + 1b2b8: ebf5a330 bl 0xffd83f80 + 1b2bc: 080045b8 stmeqda r0, {r3, r4, r5, r7, r8, sl, lr} + 1b2c0: e28cc012 add ip, ip, #18 ; 0x12 + 1b2c4: ca000004 bgt 0x1b2dc + 1b2c8: e1a00fac mov r0, ip, lsr #31 + 1b2cc: e08ff100 add pc, pc, r0, lsl #2 + 1b2d0: 08004536 stmeqda r0, {r1, r2, r4, r5, r8, sl, lr} + 1b2d4: ebf59f1e bl 0xffd82f54 + 1b2d8: eaffff0a b 0x1af08 + 1b2dc: ebf5a327 bl 0xffd83f80 + 1b2e0: 080045ba stmeqda r0, {r1, r3, r4, r5, r7, r8, sl, lr} + 1b2e4: e59d0434 ldr r0, [sp, #1076] + 1b2e8: e2800f0b add r0, r0, #44 ; 0x2c + 1b2ec: ebf5a189 bl 0xffd83918 + 1b2f0: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1b2f4: e1a06000 mov r6, r0 + 1b2f8: ebf5a320 bl 0xffd83f80 + 1b2fc: 080045bc stmeqda r0, {r2, r3, r4, r5, r7, r8, sl, lr} + 1b300: e59d0434 ldr r0, [sp, #1076] + 1b304: e2800f15 add r0, r0, #84 ; 0x54 + 1b308: ebf5a182 bl 0xffd83918 + 1b30c: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1b310: e1a04000 mov r4, r0 + 1b314: ebf5a319 bl 0xffd83f80 + 1b318: 080045be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, sl, lr} + 1b31c: e1560004 cmp r6, r4 + 1b320: ebf5a316 bl 0xffd83f80 + 1b324: 080045c0 stmeqda r0, {r6, r7, r8, sl, lr} + 1b328: e28cc010 add ip, ip, #16 ; 0x10 + 1b32c: da000004 ble 0x1b344 + 1b330: e1a00fac mov r0, ip, lsr #31 + 1b334: e08ff100 add pc, pc, r0, lsl #2 + 1b338: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1b33c: ebf59f04 bl 0xffd82f54 + 1b340: ea000007 b 0x1b364 + 1b344: ebf5a30d bl 0xffd83f80 + 1b348: 080045c2 stmeqda r0, {r1, r6, r7, r8, sl, lr} + 1b34c: e28cc003 add ip, ip, #3 ; 0x3 + 1b350: e1a00fac mov r0, ip, lsr #31 + 1b354: e08ff100 add pc, pc, r0, lsl #2 + 1b358: 080044c0 stmeqda r0, {r6, r7, sl, lr} + 1b35c: ebf59efc bl 0xffd82f54 + 1b360: eafffe51 b 0x1acac + 1b364: ebf5a305 bl 0xffd83f80 + 1b368: 080045c4 stmeqda r0, {r2, r6, r7, r8, sl, lr} + 1b36c: e28cc003 add ip, ip, #3 ; 0x3 + 1b370: e1a00fac mov r0, ip, lsr #31 + 1b374: e08ff100 add pc, pc, r0, lsl #2 + 1b378: 0800472e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, lr} + 1b37c: ebf59ef4 bl 0xffd82f54 + 1b380: eafffcad b 0x1a63c + 1b384: 08003ddc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp} + 1b388: 00000000 andeq r0, r0, r0 + 1b38c: ebf5a2fb bl 0xffd83f80 + 1b390: 08003ddc stmeqda r0, {r2, r3, r4, r6, r7, r8, sl, fp, ip, sp} + 1b394: e59d9434 ldr r9, [sp, #1076] + 1b398: e3c99003 bic r9, r9, #3 ; 0x3 + 1b39c: e2499014 sub r9, r9, #20 ; 0x14 + 1b3a0: e58d9434 str r9, [sp, #1076] + 1b3a4: e2890000 add r0, r9, #0 ; 0x0 + 1b3a8: e1a01007 mov r1, r7 + 1b3ac: ebf5a0a6 bl 0xffd8364c + 1b3b0: e2890004 add r0, r9, #4 ; 0x4 + 1b3b4: e1a01008 mov r1, r8 + 1b3b8: ebf5a0a3 bl 0xffd8364c + 1b3bc: e2890008 add r0, r9, #8 ; 0x8 + 1b3c0: e59d1418 ldr r1, [sp, #1048] + 1b3c4: ebf5a0a0 bl 0xffd8364c + 1b3c8: e289000c add r0, r9, #12 ; 0xc + 1b3cc: e59d141c ldr r1, [sp, #1052] + 1b3d0: ebf5a09d bl 0xffd8364c + 1b3d4: e2890010 add r0, r9, #16 ; 0x10 + 1b3d8: e59d1438 ldr r1, [sp, #1080] + 1b3dc: ebf5a09a bl 0xffd8364c + 1b3e0: ebf5a2e6 bl 0xffd83f80 + 1b3e4: 08003dde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, sl, fp, ip, sp} + 1b3e8: e59d1428 ldr r1, [sp, #1064] + 1b3ec: e1a00001 mov r0, r1 + 1b3f0: e58d041c str r0, [sp, #1052] + 1b3f4: ebf5a2e1 bl 0xffd83f80 + 1b3f8: 08003de0 stmeqda r0, {r5, r6, r7, r8, sl, fp, ip, sp} + 1b3fc: e59d1424 ldr r1, [sp, #1060] + 1b400: e1a00001 mov r0, r1 + 1b404: e58d0418 str r0, [sp, #1048] + 1b408: ebf5a2dc bl 0xffd83f80 + 1b40c: 08003de2 stmeqda r0, {r1, r5, r6, r7, r8, sl, fp, ip, sp} + 1b410: e59d1420 ldr r1, [sp, #1056] + 1b414: e1a08001 mov r8, r1 + 1b418: ebf5a2d8 bl 0xffd83f80 + 1b41c: 08003de4 stmeqda r0, {r2, r5, r6, r7, r8, sl, fp, ip, sp} + 1b420: e59d9434 ldr r9, [sp, #1076] + 1b424: e3c99003 bic r9, r9, #3 ; 0x3 + 1b428: e249900c sub r9, r9, #12 ; 0xc + 1b42c: e58d9434 str r9, [sp, #1076] + 1b430: e2890000 add r0, r9, #0 ; 0x0 + 1b434: e1a01008 mov r1, r8 + 1b438: ebf5a083 bl 0xffd8364c + 1b43c: e2890004 add r0, r9, #4 ; 0x4 + 1b440: e59d1418 ldr r1, [sp, #1048] + 1b444: ebf5a080 bl 0xffd8364c + 1b448: e2890008 add r0, r9, #8 ; 0x8 + 1b44c: e59d141c ldr r1, [sp, #1052] + 1b450: ebf5a05d bl 0xffd835cc + 1b454: 08003de6 stmeqda r0, {r1, r2, r5, r6, r7, r8, sl, fp, ip, sp} + 1b458: ebf5a2c8 bl 0xffd83f80 + 1b45c: 08003de6 stmeqda r0, {r1, r2, r5, r6, r7, r8, sl, fp, ip, sp} + 1b460: e59d0434 ldr r0, [sp, #1076] + 1b464: e2400f0c sub r0, r0, #48 ; 0x30 + 1b468: e58d0434 str r0, [sp, #1076] + 1b46c: ebf5a2c3 bl 0xffd83f80 + 1b470: 08003de8 stmeqda r0, {r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b474: e59d0434 ldr r0, [sp, #1076] + 1b478: e2800f00 add r0, r0, #0 ; 0x0 + 1b47c: e1a01003 mov r1, r3 + 1b480: ebf5a051 bl 0xffd835cc + 1b484: 08003dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b488: ebf5a2bc bl 0xffd83f80 + 1b48c: 08003dea stmeqda r0, {r1, r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b490: e2830018 add r0, r3, #24 ; 0x18 + 1b494: ebf5a11f bl 0xffd83918 + 1b498: 08003dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b49c: e1a07000 mov r7, r0 + 1b4a0: ebf5a2b6 bl 0xffd83f80 + 1b4a4: 08003dec stmeqda r0, {r2, r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4a8: e3b00080 movs r0, #128 ; 0x80 + 1b4ac: e58d0418 str r0, [sp, #1048] + 1b4b0: ebf5a2b2 bl 0xffd83f80 + 1b4b4: 08003dee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4b8: e59de418 ldr lr, [sp, #1048] + 1b4bc: e1b0040e movs r0, lr, lsl #8 + 1b4c0: e58d0418 str r0, [sp, #1048] + 1b4c4: ebf5a2ad bl 0xffd83f80 + 1b4c8: 08003df0 stmeqda r0, {r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4cc: e1a01007 mov r1, r7 + 1b4d0: e59d0418 ldr r0, [sp, #1048] + 1b4d4: e0977000 adds r7, r7, r0 + 1b4d8: ebf5a2a8 bl 0xffd83f80 + 1b4dc: 08003df2 stmeqda r0, {r1, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4e0: e1b05847 movs r5, r7, asr #16 + 1b4e4: ebf5a2a5 bl 0xffd83f80 + 1b4e8: 08003df4 stmeqda r0, {r2, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4ec: e283001c add r0, r3, #28 ; 0x1c + 1b4f0: ebf5a108 bl 0xffd83918 + 1b4f4: 08003df8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b4f8: e1a06000 mov r6, r0 + 1b4fc: ebf5a29f bl 0xffd83f80 + 1b500: 08003df6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b504: e1a01006 mov r1, r6 + 1b508: e59d0418 ldr r0, [sp, #1048] + 1b50c: e0966000 adds r6, r6, r0 + 1b510: ebf5a29a bl 0xffd83f80 + 1b514: 08003df8 stmeqda r0, {r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b518: e1b04846 movs r4, r6, asr #16 + 1b51c: ebf5a297 bl 0xffd83f80 + 1b520: 08003dfa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b524: e283003c add r0, r3, #60 ; 0x3c + 1b528: e1a01005 mov r1, r5 + 1b52c: ebf5a006 bl 0xffd8354c + 1b530: 08003dfc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b534: ebf5a291 bl 0xffd83f80 + 1b538: 08003dfc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b53c: e59d0434 ldr r0, [sp, #1076] + 1b540: e2800f00 add r0, r0, #0 ; 0x0 + 1b544: ebf5a0f3 bl 0xffd83918 + 1b548: 08003e00 stmeqda r0, {r9, sl, fp, ip, sp} + 1b54c: e1a03000 mov r3, r0 + 1b550: ebf5a28a bl 0xffd83f80 + 1b554: 08003dfe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, sl, fp, ip, sp} + 1b558: e283003e add r0, r3, #62 ; 0x3e + 1b55c: e1a01004 mov r1, r4 + 1b560: ebf59ff9 bl 0xffd8354c + 1b564: 08003e00 stmeqda r0, {r9, sl, fp, ip, sp} + 1b568: ebf5a284 bl 0xffd83f80 + 1b56c: 08003e00 stmeqda r0, {r9, sl, fp, ip, sp} + 1b570: e3b08020 movs r8, #32 ; 0x20 + 1b574: ebf5a281 bl 0xffd83f80 + 1b578: 08003e02 stmeqda r0, {r1, r9, sl, fp, ip, sp} + 1b57c: e0830008 add r0, r3, r8 + 1b580: ebf5a0cd bl 0xffd838bc + 1b584: 08003e06 stmeqda r0, {r1, r2, r9, sl, fp, ip, sp} + 1b588: e1a03000 mov r3, r0 + 1b58c: ebf5a27b bl 0xffd83f80 + 1b590: 08003e04 stmeqda r0, {r2, r9, sl, fp, ip, sp} + 1b594: e1a01005 mov r1, r5 + 1b598: e0955003 adds r5, r5, r3 + 1b59c: ebf5a277 bl 0xffd83f80 + 1b5a0: 08003e06 stmeqda r0, {r1, r2, r9, sl, fp, ip, sp} + 1b5a4: e1a01005 mov r1, r5 + 1b5a8: e2555001 subs r5, r5, #1 ; 0x1 + 1b5ac: ebf5a273 bl 0xffd83f80 + 1b5b0: 08003e08 stmeqda r0, {r3, r9, sl, fp, ip, sp} + 1b5b4: e59d0434 ldr r0, [sp, #1076] + 1b5b8: e2800f00 add r0, r0, #0 ; 0x0 + 1b5bc: ebf5a0d5 bl 0xffd83918 + 1b5c0: 08003e0c stmeqda r0, {r2, r3, r9, sl, fp, ip, sp} + 1b5c4: e58d041c str r0, [sp, #1052] + 1b5c8: ebf5a26c bl 0xffd83f80 + 1b5cc: 08003e0a stmeqda r0, {r1, r3, r9, sl, fp, ip, sp} + 1b5d0: e3b08022 movs r8, #34 ; 0x22 + 1b5d4: ebf5a269 bl 0xffd83f80 + 1b5d8: 08003e0c stmeqda r0, {r2, r3, r9, sl, fp, ip, sp} + 1b5dc: e59d041c ldr r0, [sp, #1052] + 1b5e0: e0800008 add r0, r0, r8 + 1b5e4: ebf5a0b4 bl 0xffd838bc + 1b5e8: 08003e10 stmeqda r0, {r4, r9, sl, fp, ip, sp} + 1b5ec: e1a03000 mov r3, r0 + 1b5f0: ebf5a262 bl 0xffd83f80 + 1b5f4: 08003e0e stmeqda r0, {r1, r2, r3, r9, sl, fp, ip, sp} + 1b5f8: e1a01004 mov r1, r4 + 1b5fc: e0944003 adds r4, r4, r3 + 1b600: ebf5a25e bl 0xffd83f80 + 1b604: 08003e10 stmeqda r0, {r4, r9, sl, fp, ip, sp} + 1b608: e1a01004 mov r1, r4 + 1b60c: e2544001 subs r4, r4, #1 ; 0x1 + 1b610: ebf5a25a bl 0xffd83f80 + 1b614: 08003e12 stmeqda r0, {r1, r4, r9, sl, fp, ip, sp} + 1b618: e1b079c7 movs r7, r7, asr #19 + 1b61c: ebf5a257 bl 0xffd83f80 + 1b620: 08003e14 stmeqda r0, {r2, r4, r9, sl, fp, ip, sp} + 1b624: e3b08004 movs r8, #4 ; 0x4 + 1b628: ebf5a254 bl 0xffd83f80 + 1b62c: 08003e16 stmeqda r0, {r1, r2, r4, r9, sl, fp, ip, sp} + 1b630: e3a01000 mov r1, #0 ; 0x0 + 1b634: e0518008 subs r8, r1, r8 + 1b638: ebf5a250 bl 0xffd83f80 + 1b63c: 08003e18 stmeqda r0, {r3, r4, r9, sl, fp, ip, sp} + 1b640: e1a01007 mov r1, r7 + 1b644: e0177008 ands r7, r7, r8 + 1b648: ebf5a24c bl 0xffd83f80 + 1b64c: 08003e1a stmeqda r0, {r1, r3, r4, r9, sl, fp, ip, sp} + 1b650: e59d0434 ldr r0, [sp, #1076] + 1b654: e2800f01 add r0, r0, #4 ; 0x4 + 1b658: e1a01007 mov r1, r7 + 1b65c: ebf59fda bl 0xffd835cc + 1b660: 08003e1c stmeqda r0, {r2, r3, r4, r9, sl, fp, ip, sp} + 1b664: ebf5a245 bl 0xffd83f80 + 1b668: 08003e1c stmeqda r0, {r2, r3, r4, r9, sl, fp, ip, sp} + 1b66c: e1b069c6 movs r6, r6, asr #19 + 1b670: ebf5a242 bl 0xffd83f80 + 1b674: 08003e1e stmeqda r0, {r1, r2, r3, r4, r9, sl, fp, ip, sp} + 1b678: e1a01006 mov r1, r6 + 1b67c: e0166008 ands r6, r6, r8 + 1b680: ebf5a23e bl 0xffd83f80 + 1b684: 08003e20 stmeqda r0, {r5, r9, sl, fp, ip, sp} + 1b688: e59d0434 ldr r0, [sp, #1076] + 1b68c: e2800f02 add r0, r0, #8 ; 0x8 + 1b690: e1a01006 mov r1, r6 + 1b694: ebf59fcc bl 0xffd835cc + 1b698: 08003e22 stmeqda r0, {r1, r5, r9, sl, fp, ip, sp} + 1b69c: ebf5a237 bl 0xffd83f80 + 1b6a0: 08003e22 stmeqda r0, {r1, r5, r9, sl, fp, ip, sp} + 1b6a4: e1b051c5 movs r5, r5, asr #3 + 1b6a8: ebf5a234 bl 0xffd83f80 + 1b6ac: 08003e24 stmeqda r0, {r2, r5, r9, sl, fp, ip, sp} + 1b6b0: e1a00005 mov r0, r5 + 1b6b4: e58d0424 str r0, [sp, #1060] + 1b6b8: ebf5a230 bl 0xffd83f80 + 1b6bc: 08003e26 stmeqda r0, {r1, r2, r5, r9, sl, fp, ip, sp} + 1b6c0: e59d1424 ldr r1, [sp, #1060] + 1b6c4: e1a00001 mov r0, r1 + 1b6c8: e58d041c str r0, [sp, #1052] + 1b6cc: ebf5a22b bl 0xffd83f80 + 1b6d0: 08003e28 stmeqda r0, {r3, r5, r9, sl, fp, ip, sp} + 1b6d4: e59d141c ldr r1, [sp, #1052] + 1b6d8: e59d141c ldr r1, [sp, #1052] + 1b6dc: e0110008 ands r0, r1, r8 + 1b6e0: e58d041c str r0, [sp, #1052] + 1b6e4: ebf5a225 bl 0xffd83f80 + 1b6e8: 08003e2a stmeqda r0, {r1, r3, r5, r9, sl, fp, ip, sp} + 1b6ec: e59d141c ldr r1, [sp, #1052] + 1b6f0: e1a00001 mov r0, r1 + 1b6f4: e58d0424 str r0, [sp, #1060] + 1b6f8: ebf5a220 bl 0xffd83f80 + 1b6fc: 08003e2c stmeqda r0, {r2, r3, r5, r9, sl, fp, ip, sp} + 1b700: e1b041c4 movs r4, r4, asr #3 + 1b704: ebf5a21d bl 0xffd83f80 + 1b708: 08003e2e stmeqda r0, {r1, r2, r3, r5, r9, sl, fp, ip, sp} + 1b70c: e1a01004 mov r1, r4 + 1b710: e0144008 ands r4, r4, r8 + 1b714: ebf5a219 bl 0xffd83f80 + 1b718: 08003e30 stmeqda r0, {r4, r5, r9, sl, fp, ip, sp} + 1b71c: e59d0434 ldr r0, [sp, #1076] + 1b720: e2800f03 add r0, r0, #12 ; 0xc + 1b724: e1a01004 mov r1, r4 + 1b728: ebf59fa7 bl 0xffd835cc + 1b72c: 08003e32 stmeqda r0, {r1, r4, r5, r9, sl, fp, ip, sp} + 1b730: ebf5a212 bl 0xffd83f80 + 1b734: 08003e32 stmeqda r0, {r1, r4, r5, r9, sl, fp, ip, sp} + 1b738: e59d0434 ldr r0, [sp, #1076] + 1b73c: e2800f00 add r0, r0, #0 ; 0x0 + 1b740: ebf5a074 bl 0xffd83918 + 1b744: 08003e36 stmeqda r0, {r1, r2, r4, r5, r9, sl, fp, ip, sp} + 1b748: e1a03000 mov r3, r0 + 1b74c: ebf5a20b bl 0xffd83f80 + 1b750: 08003e34 stmeqda r0, {r2, r4, r5, r9, sl, fp, ip, sp} + 1b754: e2830000 add r0, r3, #0 ; 0x0 + 1b758: ebf5a042 bl 0xffd83868 + 1b75c: 08003e38 stmeqda r0, {r3, r4, r5, r9, sl, fp, ip, sp} + 1b760: e1a04000 mov r4, r0 + 1b764: ebf5a205 bl 0xffd83f80 + 1b768: 08003e36 stmeqda r0, {r1, r2, r4, r5, r9, sl, fp, ip, sp} + 1b76c: e3b03080 movs r3, #128 ; 0x80 + 1b770: ebf5a202 bl 0xffd83f80 + 1b774: 08003e38 stmeqda r0, {r3, r4, r5, r9, sl, fp, ip, sp} + 1b778: e1b03083 movs r3, r3, lsl #1 + 1b77c: ebf5a1ff bl 0xffd83f80 + 1b780: 08003e3a stmeqda r0, {r1, r3, r4, r5, r9, sl, fp, ip, sp} + 1b784: e1a01003 mov r1, r3 + 1b788: e0133004 ands r3, r3, r4 + 1b78c: ebf5a1fb bl 0xffd83f80 + 1b790: 08003e3c stmeqda r0, {r2, r3, r4, r5, r9, sl, fp, ip, sp} + 1b794: e3530000 cmp r3, #0 ; 0x0 + 1b798: ebf5a1f8 bl 0xffd83f80 + 1b79c: 08003e3e stmeqda r0, {r1, r2, r3, r4, r5, r9, sl, fp, ip, sp} + 1b7a0: e28cc0b3 add ip, ip, #179 ; 0xb3 + 1b7a4: 0a000004 beq 0x1b7bc + 1b7a8: e1a00fac mov r0, ip, lsr #31 + 1b7ac: e08ff100 add pc, pc, r0, lsl #2 + 1b7b0: 08003e42 stmeqda r0, {r1, r6, r9, sl, fp, ip, sp} + 1b7b4: ebf59de6 bl 0xffd82f54 + 1b7b8: ea000007 b 0x1b7dc + 1b7bc: ebf5a1ef bl 0xffd83f80 + 1b7c0: 08003e40 stmeqda r0, {r6, r9, sl, fp, ip, sp} + 1b7c4: e28cc003 add ip, ip, #3 ; 0x3 + 1b7c8: e1a00fac mov r0, ip, lsr #31 + 1b7cc: e08ff100 add pc, pc, r0, lsl #2 + 1b7d0: 08004030 stmeqda r0, {r4, r5, lr} + 1b7d4: ebf59dde bl 0xffd82f54 + 1b7d8: ea00051a b 0x1cc48 + 1b7dc: ebf5a1e7 bl 0xffd83f80 + 1b7e0: 08003e42 stmeqda r0, {r1, r6, r9, sl, fp, ip, sp} + 1b7e4: e59d0434 ldr r0, [sp, #1076] + 1b7e8: e2800f00 add r0, r0, #0 ; 0x0 + 1b7ec: ebf5a049 bl 0xffd83918 + 1b7f0: 08003e46 stmeqda r0, {r1, r2, r6, r9, sl, fp, ip, sp} + 1b7f4: e1a04000 mov r4, r0 + 1b7f8: ebf5a1e0 bl 0xffd83f80 + 1b7fc: 08003e44 stmeqda r0, {r2, r6, r9, sl, fp, ip, sp} + 1b800: e2840014 add r0, r4, #20 ; 0x14 + 1b804: ebf5a043 bl 0xffd83918 + 1b808: 08003e48 stmeqda r0, {r3, r6, r9, sl, fp, ip, sp} + 1b80c: e1a04000 mov r4, r0 + 1b810: ebf5a1da bl 0xffd83f80 + 1b814: 08003e46 stmeqda r0, {r1, r2, r6, r9, sl, fp, ip, sp} + 1b818: e59d0434 ldr r0, [sp, #1076] + 1b81c: e2800f04 add r0, r0, #16 ; 0x10 + 1b820: e1a01004 mov r1, r4 + 1b824: ebf59f68 bl 0xffd835cc + 1b828: 08003e48 stmeqda r0, {r3, r6, r9, sl, fp, ip, sp} + 1b82c: ebf5a1d3 bl 0xffd83f80 + 1b830: 08003e48 stmeqda r0, {r3, r6, r9, sl, fp, ip, sp} + 1b834: e59d0434 ldr r0, [sp, #1076] + 1b838: e2800f00 add r0, r0, #0 ; 0x0 + 1b83c: ebf5a035 bl 0xffd83918 + 1b840: 08003e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, ip, sp} + 1b844: e1a05000 mov r5, r0 + 1b848: ebf5a1cc bl 0xffd83f80 + 1b84c: 08003e4a stmeqda r0, {r1, r3, r6, r9, sl, fp, ip, sp} + 1b850: e2850004 add r0, r5, #4 ; 0x4 + 1b854: ebf5a02f bl 0xffd83918 + 1b858: 08003e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp, ip, sp} + 1b85c: e1a05000 mov r5, r0 + 1b860: ebf5a1c6 bl 0xffd83f80 + 1b864: 08003e4c stmeqda r0, {r2, r3, r6, r9, sl, fp, ip, sp} + 1b868: e59d0434 ldr r0, [sp, #1076] + 1b86c: e2800f05 add r0, r0, #20 ; 0x14 + 1b870: e1a01005 mov r1, r5 + 1b874: ebf59f54 bl 0xffd835cc + 1b878: 08003e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp, ip, sp} + 1b87c: ebf5a1bf bl 0xffd83f80 + 1b880: 08003e4e stmeqda r0, {r1, r2, r3, r6, r9, sl, fp, ip, sp} + 1b884: e59d0434 ldr r0, [sp, #1076] + 1b888: e2800f00 add r0, r0, #0 ; 0x0 + 1b88c: ebf5a021 bl 0xffd83918 + 1b890: 08003e52 stmeqda r0, {r1, r4, r6, r9, sl, fp, ip, sp} + 1b894: e1a06000 mov r6, r0 + 1b898: ebf5a1b8 bl 0xffd83f80 + 1b89c: 08003e50 stmeqda r0, {r4, r6, r9, sl, fp, ip, sp} + 1b8a0: e2860002 add r0, r6, #2 ; 0x2 + 1b8a4: ebf59fef bl 0xffd83868 + 1b8a8: 08003e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, ip, sp} + 1b8ac: e1a03000 mov r3, r0 + 1b8b0: ebf5a1b2 bl 0xffd83f80 + 1b8b4: 08003e52 stmeqda r0, {r1, r4, r6, r9, sl, fp, ip, sp} + 1b8b8: e1b03723 movs r3, r3, lsr #14 + 1b8bc: ebf5a1af bl 0xffd83f80 + 1b8c0: 08003e54 stmeqda r0, {r2, r4, r6, r9, sl, fp, ip, sp} + 1b8c4: e3b07010 movs r7, #16 ; 0x10 + 1b8c8: ebf5a1ac bl 0xffd83f80 + 1b8cc: 08003e56 stmeqda r0, {r1, r2, r4, r6, r9, sl, fp, ip, sp} + 1b8d0: e1a00007 mov r0, r7 + 1b8d4: e58d0428 str r0, [sp, #1064] + 1b8d8: ebf5a1a8 bl 0xffd83f80 + 1b8dc: 08003e58 stmeqda r0, {r3, r4, r6, r9, sl, fp, ip, sp} + 1b8e0: e59d1428 ldr r1, [sp, #1064] + 1b8e4: e1a00001 mov r0, r1 + 1b8e8: e58d041c str r0, [sp, #1052] + 1b8ec: ebf5a1a3 bl 0xffd83f80 + 1b8f0: 08003e5a stmeqda r0, {r1, r3, r4, r6, r9, sl, fp, ip, sp} + 1b8f4: e59d041c ldr r0, [sp, #1052] + 1b8f8: e1b00310 movs r0, r0, lsl r3 + 1b8fc: e58d041c str r0, [sp, #1052] + 1b900: ebf5a19e bl 0xffd83f80 + 1b904: 08003e5c stmeqda r0, {r2, r3, r4, r6, r9, sl, fp, ip, sp} + 1b908: e59d141c ldr r1, [sp, #1052] + 1b90c: e1a00001 mov r0, r1 + 1b910: e58d0428 str r0, [sp, #1064] + 1b914: ebf5a199 bl 0xffd83f80 + 1b918: 08003e5e stmeqda r0, {r1, r2, r3, r4, r6, r9, sl, fp, ip, sp} + 1b91c: e59d1428 ldr r1, [sp, #1064] + 1b920: e1a07001 mov r7, r1 + 1b924: ebf5a195 bl 0xffd83f80 + 1b928: 08003e60 stmeqda r0, {r5, r6, r9, sl, fp, ip, sp} + 1b92c: e1a01007 mov r1, r7 + 1b930: e2577001 subs r7, r7, #1 ; 0x1 + 1b934: ebf5a191 bl 0xffd83f80 + 1b938: 08003e62 stmeqda r0, {r1, r5, r6, r9, sl, fp, ip, sp} + 1b93c: e286000c add r0, r6, #12 ; 0xc + 1b940: ebf59ff4 bl 0xffd83918 + 1b944: 08003e66 stmeqda r0, {r1, r2, r5, r6, r9, sl, fp, ip, sp} + 1b948: e1a03000 mov r3, r0 + 1b94c: ebf5a18b bl 0xffd83f80 + 1b950: 08003e64 stmeqda r0, {r2, r5, r6, r9, sl, fp, ip, sp} + 1b954: e59d0434 ldr r0, [sp, #1076] + 1b958: e2800f09 add r0, r0, #36 ; 0x24 + 1b95c: e1a01003 mov r1, r3 + 1b960: ebf59f19 bl 0xffd835cc + 1b964: 08003e66 stmeqda r0, {r1, r2, r5, r6, r9, sl, fp, ip, sp} + 1b968: ebf5a184 bl 0xffd83f80 + 1b96c: 08003e66 stmeqda r0, {r1, r2, r5, r6, r9, sl, fp, ip, sp} + 1b970: e59d0434 ldr r0, [sp, #1076] + 1b974: e2800f02 add r0, r0, #8 ; 0x8 + 1b978: ebf59fe6 bl 0xffd83918 + 1b97c: 08003e6a stmeqda r0, {r1, r3, r5, r6, r9, sl, fp, ip, sp} + 1b980: e1a04000 mov r4, r0 + 1b984: ebf5a17d bl 0xffd83f80 + 1b988: 08003e68 stmeqda r0, {r3, r5, r6, r9, sl, fp, ip, sp} + 1b98c: e3540000 cmp r4, #0 ; 0x0 + 1b990: ebf5a17a bl 0xffd83f80 + 1b994: 08003e6a stmeqda r0, {r1, r3, r5, r6, r9, sl, fp, ip, sp} + 1b998: e28cc052 add ip, ip, #82 ; 0x52 + 1b99c: ba000004 blt 0x1b9b4 + 1b9a0: e1a00fac mov r0, ip, lsr #31 + 1b9a4: e08ff100 add pc, pc, r0, lsl #2 + 1b9a8: 08003eb0 stmeqda r0, {r4, r5, r7, r9, sl, fp, ip, sp} + 1b9ac: ebf59d68 bl 0xffd82f54 + 1b9b0: ea0000ac b 0x1bc68 + 1b9b4: ebf5a171 bl 0xffd83f80 + 1b9b8: 08003e6c stmeqda r0, {r2, r3, r5, r6, r9, sl, fp, ip, sp} + 1b9bc: e1540008 cmp r4, r8 + 1b9c0: ebf5a16e bl 0xffd83f80 + 1b9c4: 08003e6e stmeqda r0, {r1, r2, r3, r5, r6, r9, sl, fp, ip, sp} + 1b9c8: e28cc006 add ip, ip, #6 ; 0x6 + 1b9cc: da000004 ble 0x1b9e4 + 1b9d0: e1a00fac mov r0, ip, lsr #31 + 1b9d4: e08ff100 add pc, pc, r0, lsl #2 + 1b9d8: 08003eac stmeqda r0, {r2, r3, r5, r7, r9, sl, fp, ip, sp} + 1b9dc: ebf59d5c bl 0xffd82f54 + 1b9e0: ea000094 b 0x1bc38 + 1b9e4: ebf5a165 bl 0xffd83f80 + 1b9e8: 08003e70 stmeqda r0, {r4, r5, r6, r9, sl, fp, ip, sp} + 1b9ec: e59d0434 ldr r0, [sp, #1076] + 1b9f0: e2800f01 add r0, r0, #4 ; 0x4 + 1b9f4: ebf59fc7 bl 0xffd83918 + 1b9f8: 08003e74 stmeqda r0, {r2, r4, r5, r6, r9, sl, fp, ip, sp} + 1b9fc: e1a05000 mov r5, r0 + 1ba00: ebf5a15e bl 0xffd83f80 + 1ba04: 08003e72 stmeqda r0, {r1, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba08: e1a01004 mov r1, r4 + 1ba0c: e2946004 adds r6, r4, #4 ; 0x4 + 1ba10: ebf5a15a bl 0xffd83f80 + 1ba14: 08003e74 stmeqda r0, {r2, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba18: e1a00006 mov r0, r6 + 1ba1c: e58d0430 str r0, [sp, #1072] + 1ba20: ebf5a156 bl 0xffd83f80 + 1ba24: 08003e76 stmeqda r0, {r1, r2, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba28: e59d1424 ldr r1, [sp, #1060] + 1ba2c: e1550001 cmp r5, r1 + 1ba30: ebf5a152 bl 0xffd83f80 + 1ba34: 08003e78 stmeqda r0, {r3, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba38: e28cc011 add ip, ip, #17 ; 0x11 + 1ba3c: da000004 ble 0x1ba54 + 1ba40: e1a00fac mov r0, ip, lsr #31 + 1ba44: e08ff100 add pc, pc, r0, lsl #2 + 1ba48: 08003ea2 stmeqda r0, {r1, r5, r7, r9, sl, fp, ip, sp} + 1ba4c: ebf59d40 bl 0xffd82f54 + 1ba50: ea000061 b 0x1bbdc + 1ba54: ebf5a149 bl 0xffd83f80 + 1ba58: 08003e7a stmeqda r0, {r1, r3, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba5c: e1a01004 mov r1, r4 + 1ba60: e0144007 ands r4, r4, r7 + 1ba64: ebf5a145 bl 0xffd83f80 + 1ba68: 08003e7c stmeqda r0, {r2, r3, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba6c: e59d1428 ldr r1, [sp, #1064] + 1ba70: e1a03001 mov r3, r1 + 1ba74: ebf5a141 bl 0xffd83f80 + 1ba78: 08003e7e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, sl, fp, ip, sp} + 1ba7c: e1a01003 mov r1, r3 + 1ba80: e0130493 muls r3, r3, r4 + 1ba84: ebf5a13d bl 0xffd83f80 + 1ba88: 08003e80 stmeqda r0, {r7, r9, sl, fp, ip, sp} + 1ba8c: e59d0434 ldr r0, [sp, #1076] + 1ba90: e2800f04 add r0, r0, #16 ; 0x10 + 1ba94: ebf59f9f bl 0xffd83918 + 1ba98: 08003e84 stmeqda r0, {r2, r7, r9, sl, fp, ip, sp} + 1ba9c: e1a08000 mov r8, r0 + 1baa0: ebf5a136 bl 0xffd83f80 + 1baa4: 08003e82 stmeqda r0, {r1, r7, r9, sl, fp, ip, sp} + 1baa8: e1a01008 mov r1, r8 + 1baac: e0980003 adds r0, r8, r3 + 1bab0: e58d0418 str r0, [sp, #1048] + 1bab4: ebf5a131 bl 0xffd83f80 + 1bab8: 08003e84 stmeqda r0, {r2, r7, r9, sl, fp, ip, sp} + 1babc: e3b06000 movs r6, #0 ; 0x0 + 1bac0: e28cc014 add ip, ip, #20 ; 0x14 + 1bac4: ebf5a12d bl 0xffd83f80 + 1bac8: 08003e86 stmeqda r0, {r1, r2, r7, r9, sl, fp, ip, sp} + 1bacc: e1a01005 mov r1, r5 + 1bad0: e2953000 adds r3, r5, #0 ; 0x0 + 1bad4: ebf5a129 bl 0xffd83f80 + 1bad8: 08003e88 stmeqda r0, {r3, r7, r9, sl, fp, ip, sp} + 1badc: e1a01003 mov r1, r3 + 1bae0: e0133007 ands r3, r3, r7 + 1bae4: ebf5a125 bl 0xffd83f80 + 1bae8: 08003e8a stmeqda r0, {r1, r3, r7, r9, sl, fp, ip, sp} + 1baec: e59d1418 ldr r1, [sp, #1048] + 1baf0: e59d1418 ldr r1, [sp, #1048] + 1baf4: e0914003 adds r4, r1, r3 + 1baf8: ebf5a120 bl 0xffd83f80 + 1bafc: 08003e8c stmeqda r0, {r2, r3, r7, r9, sl, fp, ip, sp} + 1bb00: e1a01005 mov r1, r5 + 1bb04: e2958004 adds r8, r5, #4 ; 0x4 + 1bb08: ebf5a11c bl 0xffd83f80 + 1bb0c: 08003e8e stmeqda r0, {r1, r2, r3, r7, r9, sl, fp, ip, sp} + 1bb10: e3b05003 movs r5, #3 ; 0x3 + 1bb14: e28cc00f add ip, ip, #15 ; 0xf + 1bb18: ebf5a118 bl 0xffd83f80 + 1bb1c: 08003e90 stmeqda r0, {r4, r7, r9, sl, fp, ip, sp} + 1bb20: e2840002 add r0, r4, #2 ; 0x2 + 1bb24: e1a01006 mov r1, r6 + 1bb28: ebf59e87 bl 0xffd8354c + 1bb2c: 08003e92 stmeqda r0, {r1, r4, r7, r9, sl, fp, ip, sp} + 1bb30: ebf5a112 bl 0xffd83f80 + 1bb34: 08003e92 stmeqda r0, {r1, r4, r7, r9, sl, fp, ip, sp} + 1bb38: e2840000 add r0, r4, #0 ; 0x0 + 1bb3c: e1a01006 mov r1, r6 + 1bb40: ebf59e81 bl 0xffd8354c + 1bb44: 08003e94 stmeqda r0, {r2, r4, r7, r9, sl, fp, ip, sp} + 1bb48: ebf5a10c bl 0xffd83f80 + 1bb4c: 08003e94 stmeqda r0, {r2, r4, r7, r9, sl, fp, ip, sp} + 1bb50: e59d1428 ldr r1, [sp, #1064] + 1bb54: e0844001 add r4, r4, r1 + 1bb58: ebf5a108 bl 0xffd83f80 + 1bb5c: 08003e96 stmeqda r0, {r1, r2, r4, r7, r9, sl, fp, ip, sp} + 1bb60: e1a01005 mov r1, r5 + 1bb64: e2555001 subs r5, r5, #1 ; 0x1 + 1bb68: ebf5a104 bl 0xffd83f80 + 1bb6c: 08003e98 stmeqda r0, {r3, r4, r7, r9, sl, fp, ip, sp} + 1bb70: e3550000 cmp r5, #0 ; 0x0 + 1bb74: ebf5a101 bl 0xffd83f80 + 1bb78: 08003e9a stmeqda r0, {r1, r3, r4, r7, r9, sl, fp, ip, sp} + 1bb7c: e28cc014 add ip, ip, #20 ; 0x14 + 1bb80: ba000004 blt 0x1bb98 + 1bb84: e1a00fac mov r0, ip, lsr #31 + 1bb88: e08ff100 add pc, pc, r0, lsl #2 + 1bb8c: 08003e90 stmeqda r0, {r4, r7, r9, sl, fp, ip, sp} + 1bb90: ebf59cef bl 0xffd82f54 + 1bb94: eaffffdf b 0x1bb18 + 1bb98: ebf5a0f8 bl 0xffd83f80 + 1bb9c: 08003e9c stmeqda r0, {r2, r3, r4, r7, r9, sl, fp, ip, sp} + 1bba0: e1a01008 mov r1, r8 + 1bba4: e2985000 adds r5, r8, #0 ; 0x0 + 1bba8: ebf5a0f4 bl 0xffd83f80 + 1bbac: 08003e9e stmeqda r0, {r1, r2, r3, r4, r7, r9, sl, fp, ip, sp} + 1bbb0: e59d1424 ldr r1, [sp, #1060] + 1bbb4: e1550001 cmp r5, r1 + 1bbb8: ebf5a0f0 bl 0xffd83f80 + 1bbbc: 08003ea0 stmeqda r0, {r5, r7, r9, sl, fp, ip, sp} + 1bbc0: e28cc009 add ip, ip, #9 ; 0x9 + 1bbc4: ca000004 bgt 0x1bbdc + 1bbc8: e1a00fac mov r0, ip, lsr #31 + 1bbcc: e08ff100 add pc, pc, r0, lsl #2 + 1bbd0: 08003e86 stmeqda r0, {r1, r2, r7, r9, sl, fp, ip, sp} + 1bbd4: ebf59cde bl 0xffd82f54 + 1bbd8: eaffffb9 b 0x1bac4 + 1bbdc: ebf5a0e7 bl 0xffd83f80 + 1bbe0: 08003ea2 stmeqda r0, {r1, r5, r7, r9, sl, fp, ip, sp} + 1bbe4: e59d1430 ldr r1, [sp, #1072] + 1bbe8: e1a04001 mov r4, r1 + 1bbec: ebf5a0e3 bl 0xffd83f80 + 1bbf0: 08003ea4 stmeqda r0, {r2, r5, r7, r9, sl, fp, ip, sp} + 1bbf4: e3b03004 movs r3, #4 ; 0x4 + 1bbf8: ebf5a0e0 bl 0xffd83f80 + 1bbfc: 08003ea6 stmeqda r0, {r1, r2, r5, r7, r9, sl, fp, ip, sp} + 1bc00: e3a01000 mov r1, #0 ; 0x0 + 1bc04: e0513003 subs r3, r1, r3 + 1bc08: ebf5a0dc bl 0xffd83f80 + 1bc0c: 08003ea8 stmeqda r0, {r3, r5, r7, r9, sl, fp, ip, sp} + 1bc10: e1540003 cmp r4, r3 + 1bc14: ebf5a0d9 bl 0xffd83f80 + 1bc18: 08003eaa stmeqda r0, {r1, r3, r5, r7, r9, sl, fp, ip, sp} + 1bc1c: e28cc00f add ip, ip, #15 ; 0xf + 1bc20: ca000004 bgt 0x1bc38 + 1bc24: e1a00fac mov r0, ip, lsr #31 + 1bc28: e08ff100 add pc, pc, r0, lsl #2 + 1bc2c: 08003e70 stmeqda r0, {r4, r5, r6, r9, sl, fp, ip, sp} + 1bc30: ebf59cc7 bl 0xffd82f54 + 1bc34: eaffff6a b 0x1b9e4 + 1bc38: ebf5a0d0 bl 0xffd83f80 + 1bc3c: 08003eac stmeqda r0, {r2, r3, r5, r7, r9, sl, fp, ip, sp} + 1bc40: e3b00000 movs r0, #0 ; 0x0 + 1bc44: e58d041c str r0, [sp, #1052] + 1bc48: ebf5a0cc bl 0xffd83f80 + 1bc4c: 08003eae stmeqda r0, {r1, r2, r3, r5, r7, r9, sl, fp, ip, sp} + 1bc50: e59d0434 ldr r0, [sp, #1076] + 1bc54: e2800f02 add r0, r0, #8 ; 0x8 + 1bc58: e59d141c ldr r1, [sp, #1052] + 1bc5c: ebf59e5a bl 0xffd835cc + 1bc60: 08003eb0 stmeqda r0, {r4, r5, r7, r9, sl, fp, ip, sp} + 1bc64: e28cc007 add ip, ip, #7 ; 0x7 + 1bc68: ebf5a0c4 bl 0xffd83f80 + 1bc6c: 08003eb0 stmeqda r0, {r4, r5, r7, r9, sl, fp, ip, sp} + 1bc70: e59d0434 ldr r0, [sp, #1076] + 1bc74: e2800f00 add r0, r0, #0 ; 0x0 + 1bc78: ebf59f26 bl 0xffd83918 + 1bc7c: 08003eb4 stmeqda r0, {r2, r4, r5, r7, r9, sl, fp, ip, sp} + 1bc80: e1a04000 mov r4, r0 + 1bc84: ebf5a0bd bl 0xffd83f80 + 1bc88: 08003eb2 stmeqda r0, {r1, r4, r5, r7, r9, sl, fp, ip, sp} + 1bc8c: e3b05012 movs r5, #18 ; 0x12 + 1bc90: ebf5a0ba bl 0xffd83f80 + 1bc94: 08003eb4 stmeqda r0, {r2, r4, r5, r7, r9, sl, fp, ip, sp} + 1bc98: e0840005 add r0, r4, r5 + 1bc9c: ebf59f06 bl 0xffd838bc + 1bca0: 08003eb8 stmeqda r0, {r3, r4, r5, r7, r9, sl, fp, ip, sp} + 1bca4: e1a03000 mov r3, r0 + 1bca8: ebf5a0b4 bl 0xffd83f80 + 1bcac: 08003eb6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sl, fp, ip, sp} + 1bcb0: e1a01003 mov r1, r3 + 1bcb4: e2533001 subs r3, r3, #1 ; 0x1 + 1bcb8: ebf5a0b0 bl 0xffd83f80 + 1bcbc: 08003eb8 stmeqda r0, {r3, r4, r5, r7, r9, sl, fp, ip, sp} + 1bcc0: e1b03103 movs r3, r3, lsl #2 + 1bcc4: ebf5a0ad bl 0xffd83f80 + 1bcc8: 08003eba stmeqda r0, {r1, r3, r4, r5, r7, r9, sl, fp, ip, sp} + 1bccc: e1a00003 mov r0, r3 + 1bcd0: e58d0420 str r0, [sp, #1056] + 1bcd4: ebf5a0a9 bl 0xffd83f80 + 1bcd8: 08003ebc stmeqda r0, {r2, r3, r4, r5, r7, r9, sl, fp, ip, sp} + 1bcdc: e59d0434 ldr r0, [sp, #1076] + 1bce0: e2800f02 add r0, r0, #8 ; 0x8 + 1bce4: ebf59f0b bl 0xffd83918 + 1bce8: 08003ec0 stmeqda r0, {r6, r7, r9, sl, fp, ip, sp} + 1bcec: e1a06000 mov r6, r0 + 1bcf0: ebf5a0a2 bl 0xffd83f80 + 1bcf4: 08003ebe stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sl, fp, ip, sp} + 1bcf8: e1b06146 movs r6, r6, asr #2 + 1bcfc: ebf5a09f bl 0xffd83f80 + 1bd00: 08003ec0 stmeqda r0, {r6, r7, r9, sl, fp, ip, sp} + 1bd04: e59d0434 ldr r0, [sp, #1076] + 1bd08: e2800f0b add r0, r0, #44 ; 0x2c + 1bd0c: e1a01006 mov r1, r6 + 1bd10: ebf59e2d bl 0xffd835cc + 1bd14: 08003ec2 stmeqda r0, {r1, r6, r7, r9, sl, fp, ip, sp} + 1bd18: ebf5a098 bl 0xffd83f80 + 1bd1c: 08003ec2 stmeqda r0, {r1, r6, r7, r9, sl, fp, ip, sp} + 1bd20: e59d0434 ldr r0, [sp, #1076] + 1bd24: e2800f03 add r0, r0, #12 ; 0xc + 1bd28: ebf59efa bl 0xffd83918 + 1bd2c: 08003ec6 stmeqda r0, {r1, r2, r6, r7, r9, sl, fp, ip, sp} + 1bd30: e1a08000 mov r8, r0 + 1bd34: ebf5a091 bl 0xffd83f80 + 1bd38: 08003ec4 stmeqda r0, {r2, r6, r7, r9, sl, fp, ip, sp} + 1bd3c: e59d0420 ldr r0, [sp, #1056] + 1bd40: e1500008 cmp r0, r8 + 1bd44: ebf5a08d bl 0xffd83f80 + 1bd48: 08003ec6 stmeqda r0, {r1, r2, r6, r7, r9, sl, fp, ip, sp} + 1bd4c: e28cc02d add ip, ip, #45 ; 0x2d + 1bd50: ba000004 blt 0x1bd68 + 1bd54: e1a00fac mov r0, ip, lsr #31 + 1bd58: e08ff100 add pc, pc, r0, lsl #2 + 1bd5c: 08003f08 stmeqda r0, {r3, r8, r9, sl, fp, ip, sp} + 1bd60: ebf59c7b bl 0xffd82f54 + 1bd64: ea0000a8 b 0x1c00c + 1bd68: ebf5a084 bl 0xffd83f80 + 1bd6c: 08003ec8 stmeqda r0, {r3, r6, r7, r9, sl, fp, ip, sp} + 1bd70: e59d1420 ldr r1, [sp, #1056] + 1bd74: e1a04001 mov r4, r1 + 1bd78: e28cc003 add ip, ip, #3 ; 0x3 + 1bd7c: ebf5a07f bl 0xffd83f80 + 1bd80: 08003eca stmeqda r0, {r1, r3, r6, r7, r9, sl, fp, ip, sp} + 1bd84: e59d0434 ldr r0, [sp, #1076] + 1bd88: e2800f01 add r0, r0, #4 ; 0x4 + 1bd8c: ebf59ee1 bl 0xffd83918 + 1bd90: 08003ece stmeqda r0, {r1, r2, r3, r6, r7, r9, sl, fp, ip, sp} + 1bd94: e1a05000 mov r5, r0 + 1bd98: ebf5a078 bl 0xffd83f80 + 1bd9c: 08003ecc stmeqda r0, {r2, r3, r6, r7, r9, sl, fp, ip, sp} + 1bda0: e1a01004 mov r1, r4 + 1bda4: e2940004 adds r0, r4, #4 ; 0x4 + 1bda8: e58d041c str r0, [sp, #1052] + 1bdac: ebf5a073 bl 0xffd83f80 + 1bdb0: 08003ece stmeqda r0, {r1, r2, r3, r6, r7, r9, sl, fp, ip, sp} + 1bdb4: e59d141c ldr r1, [sp, #1052] + 1bdb8: e1a00001 mov r0, r1 + 1bdbc: e58d0430 str r0, [sp, #1072] + 1bdc0: ebf5a06e bl 0xffd83f80 + 1bdc4: 08003ed0 stmeqda r0, {r4, r6, r7, r9, sl, fp, ip, sp} + 1bdc8: e59d1424 ldr r1, [sp, #1060] + 1bdcc: e1550001 cmp r5, r1 + 1bdd0: ebf5a06a bl 0xffd83f80 + 1bdd4: 08003ed2 stmeqda r0, {r1, r4, r6, r7, r9, sl, fp, ip, sp} + 1bdd8: e28cc011 add ip, ip, #17 ; 0x11 + 1bddc: da000004 ble 0x1bdf4 + 1bde0: e1a00fac mov r0, ip, lsr #31 + 1bde4: e08ff100 add pc, pc, r0, lsl #2 + 1bde8: 08003efc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bdec: ebf59c58 bl 0xffd82f54 + 1bdf0: ea000062 b 0x1bf80 + 1bdf4: ebf5a061 bl 0xffd83f80 + 1bdf8: 08003ed4 stmeqda r0, {r2, r4, r6, r7, r9, sl, fp, ip, sp} + 1bdfc: e1a01004 mov r1, r4 + 1be00: e0144007 ands r4, r4, r7 + 1be04: ebf5a05d bl 0xffd83f80 + 1be08: 08003ed6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl, fp, ip, sp} + 1be0c: e59d1428 ldr r1, [sp, #1064] + 1be10: e1a03001 mov r3, r1 + 1be14: ebf5a059 bl 0xffd83f80 + 1be18: 08003ed8 stmeqda r0, {r3, r4, r6, r7, r9, sl, fp, ip, sp} + 1be1c: e1a01003 mov r1, r3 + 1be20: e0130493 muls r3, r3, r4 + 1be24: ebf5a055 bl 0xffd83f80 + 1be28: 08003eda stmeqda r0, {r1, r3, r4, r6, r7, r9, sl, fp, ip, sp} + 1be2c: e59d0434 ldr r0, [sp, #1076] + 1be30: e2800f04 add r0, r0, #16 ; 0x10 + 1be34: ebf59eb7 bl 0xffd83918 + 1be38: 08003ede stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl, fp, ip, sp} + 1be3c: e1a04000 mov r4, r0 + 1be40: ebf5a04e bl 0xffd83f80 + 1be44: 08003edc stmeqda r0, {r2, r3, r4, r6, r7, r9, sl, fp, ip, sp} + 1be48: e1a01004 mov r1, r4 + 1be4c: e0940003 adds r0, r4, r3 + 1be50: e58d041c str r0, [sp, #1052] + 1be54: ebf5a049 bl 0xffd83f80 + 1be58: 08003ede stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl, fp, ip, sp} + 1be5c: e3b00000 movs r0, #0 ; 0x0 + 1be60: e58d0418 str r0, [sp, #1048] + 1be64: e28cc014 add ip, ip, #20 ; 0x14 + 1be68: ebf5a044 bl 0xffd83f80 + 1be6c: 08003ee0 stmeqda r0, {r5, r6, r7, r9, sl, fp, ip, sp} + 1be70: e1a01005 mov r1, r5 + 1be74: e2953000 adds r3, r5, #0 ; 0x0 + 1be78: ebf5a040 bl 0xffd83f80 + 1be7c: 08003ee2 stmeqda r0, {r1, r5, r6, r7, r9, sl, fp, ip, sp} + 1be80: e1a01003 mov r1, r3 + 1be84: e0133007 ands r3, r3, r7 + 1be88: ebf5a03c bl 0xffd83f80 + 1be8c: 08003ee4 stmeqda r0, {r2, r5, r6, r7, r9, sl, fp, ip, sp} + 1be90: e59d141c ldr r1, [sp, #1052] + 1be94: e59d141c ldr r1, [sp, #1052] + 1be98: e0914003 adds r4, r1, r3 + 1be9c: ebf5a037 bl 0xffd83f80 + 1bea0: 08003ee6 stmeqda r0, {r1, r2, r5, r6, r7, r9, sl, fp, ip, sp} + 1bea4: e1a01005 mov r1, r5 + 1bea8: e2958004 adds r8, r5, #4 ; 0x4 + 1beac: ebf5a033 bl 0xffd83f80 + 1beb0: 08003ee8 stmeqda r0, {r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1beb4: e3b05003 movs r5, #3 ; 0x3 + 1beb8: e28cc00f add ip, ip, #15 ; 0xf + 1bebc: ebf5a02f bl 0xffd83f80 + 1bec0: 08003eea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1bec4: e2840002 add r0, r4, #2 ; 0x2 + 1bec8: e59d1418 ldr r1, [sp, #1048] + 1becc: ebf59d9e bl 0xffd8354c + 1bed0: 08003eec stmeqda r0, {r2, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1bed4: ebf5a029 bl 0xffd83f80 + 1bed8: 08003eec stmeqda r0, {r2, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1bedc: e2840000 add r0, r4, #0 ; 0x0 + 1bee0: e59d1418 ldr r1, [sp, #1048] + 1bee4: ebf59d98 bl 0xffd8354c + 1bee8: 08003eee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1beec: ebf5a023 bl 0xffd83f80 + 1bef0: 08003eee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1bef4: e59d1428 ldr r1, [sp, #1064] + 1bef8: e0844001 add r4, r4, r1 + 1befc: ebf5a01f bl 0xffd83f80 + 1bf00: 08003ef0 stmeqda r0, {r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf04: e1a01005 mov r1, r5 + 1bf08: e2555001 subs r5, r5, #1 ; 0x1 + 1bf0c: ebf5a01b bl 0xffd83f80 + 1bf10: 08003ef2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf14: e3550000 cmp r5, #0 ; 0x0 + 1bf18: ebf5a018 bl 0xffd83f80 + 1bf1c: 08003ef4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf20: e28cc014 add ip, ip, #20 ; 0x14 + 1bf24: ba000004 blt 0x1bf3c + 1bf28: e1a00fac mov r0, ip, lsr #31 + 1bf2c: e08ff100 add pc, pc, r0, lsl #2 + 1bf30: 08003eea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf34: ebf59c06 bl 0xffd82f54 + 1bf38: eaffffdf b 0x1bebc + 1bf3c: ebf5a00f bl 0xffd83f80 + 1bf40: 08003ef6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf44: e1a01008 mov r1, r8 + 1bf48: e2985000 adds r5, r8, #0 ; 0x0 + 1bf4c: ebf5a00b bl 0xffd83f80 + 1bf50: 08003ef8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf54: e59d1424 ldr r1, [sp, #1060] + 1bf58: e1550001 cmp r5, r1 + 1bf5c: ebf5a007 bl 0xffd83f80 + 1bf60: 08003efa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf64: e28cc009 add ip, ip, #9 ; 0x9 + 1bf68: ca000004 bgt 0x1bf80 + 1bf6c: e1a00fac mov r0, ip, lsr #31 + 1bf70: e08ff100 add pc, pc, r0, lsl #2 + 1bf74: 08003ee0 stmeqda r0, {r5, r6, r7, r9, sl, fp, ip, sp} + 1bf78: ebf59bf5 bl 0xffd82f54 + 1bf7c: eaffffb9 b 0x1be68 + 1bf80: ebf59ffe bl 0xffd83f80 + 1bf84: 08003efc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf88: e59d1430 ldr r1, [sp, #1072] + 1bf8c: e1a04001 mov r4, r1 + 1bf90: ebf59ffa bl 0xffd83f80 + 1bf94: 08003efe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sl, fp, ip, sp} + 1bf98: e59d0434 ldr r0, [sp, #1076] + 1bf9c: e2800f03 add r0, r0, #12 ; 0xc + 1bfa0: ebf59e5c bl 0xffd83918 + 1bfa4: 08003f02 stmeqda r0, {r1, r8, r9, sl, fp, ip, sp} + 1bfa8: e1a05000 mov r5, r0 + 1bfac: ebf59ff3 bl 0xffd83f80 + 1bfb0: 08003f00 stmeqda r0, {r8, r9, sl, fp, ip, sp} + 1bfb4: e1540005 cmp r4, r5 + 1bfb8: ebf59ff0 bl 0xffd83f80 + 1bfbc: 08003f02 stmeqda r0, {r1, r8, r9, sl, fp, ip, sp} + 1bfc0: e28cc00e add ip, ip, #14 ; 0xe + 1bfc4: ca000004 bgt 0x1bfdc + 1bfc8: e1a00fac mov r0, ip, lsr #31 + 1bfcc: e08ff100 add pc, pc, r0, lsl #2 + 1bfd0: 08003eca stmeqda r0, {r1, r3, r6, r7, r9, sl, fp, ip, sp} + 1bfd4: ebf59bde bl 0xffd82f54 + 1bfd8: eaffff67 b 0x1bd7c + 1bfdc: ebf59fe7 bl 0xffd83f80 + 1bfe0: 08003f04 stmeqda r0, {r2, r8, r9, sl, fp, ip, sp} + 1bfe4: e59d1420 ldr r1, [sp, #1056] + 1bfe8: e1a06001 mov r6, r1 + 1bfec: ebf59fe3 bl 0xffd83f80 + 1bff0: 08003f06 stmeqda r0, {r1, r2, r8, r9, sl, fp, ip, sp} + 1bff4: e59d0434 ldr r0, [sp, #1076] + 1bff8: e2800f03 add r0, r0, #12 ; 0xc + 1bffc: e1a01006 mov r1, r6 + 1c000: ebf59d71 bl 0xffd835cc + 1c004: 08003f08 stmeqda r0, {r3, r8, r9, sl, fp, ip, sp} + 1c008: e28cc007 add ip, ip, #7 ; 0x7 + 1c00c: ebf59fdb bl 0xffd83f80 + 1c010: 08003f08 stmeqda r0, {r3, r8, r9, sl, fp, ip, sp} + 1c014: e59d0434 ldr r0, [sp, #1076] + 1c018: e2800f01 add r0, r0, #4 ; 0x4 + 1c01c: ebf59e3d bl 0xffd83918 + 1c020: 08003f0c stmeqda r0, {r2, r3, r8, r9, sl, fp, ip, sp} + 1c024: e1a08000 mov r8, r0 + 1c028: ebf59fd4 bl 0xffd83f80 + 1c02c: 08003f0a stmeqda r0, {r1, r3, r8, r9, sl, fp, ip, sp} + 1c030: e3580000 cmp r8, #0 ; 0x0 + 1c034: ebf59fd1 bl 0xffd83f80 + 1c038: 08003f0c stmeqda r0, {r2, r3, r8, r9, sl, fp, ip, sp} + 1c03c: e28cc00b add ip, ip, #11 ; 0xb + 1c040: ba000004 blt 0x1c058 + 1c044: e1a00fac mov r0, ip, lsr #31 + 1c048: e08ff100 add pc, pc, r0, lsl #2 + 1c04c: 08003f58 stmeqda r0, {r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c050: ebf59bbf bl 0xffd82f54 + 1c054: ea0000c1 b 0x1c360 + 1c058: ebf59fc8 bl 0xffd83f80 + 1c05c: 08003f0e stmeqda r0, {r1, r2, r3, r8, r9, sl, fp, ip, sp} + 1c060: e59d0434 ldr r0, [sp, #1076] + 1c064: e2800f02 add r0, r0, #8 ; 0x8 + 1c068: ebf59e2a bl 0xffd83918 + 1c06c: 08003f12 stmeqda r0, {r1, r4, r8, r9, sl, fp, ip, sp} + 1c070: e1a04000 mov r4, r0 + 1c074: ebf59fc1 bl 0xffd83f80 + 1c078: 08003f10 stmeqda r0, {r4, r8, r9, sl, fp, ip, sp} + 1c07c: e59d0434 ldr r0, [sp, #1076] + 1c080: e2800f03 add r0, r0, #12 ; 0xc + 1c084: ebf59e23 bl 0xffd83918 + 1c088: 08003f14 stmeqda r0, {r2, r4, r8, r9, sl, fp, ip, sp} + 1c08c: e58d041c str r0, [sp, #1052] + 1c090: ebf59fba bl 0xffd83f80 + 1c094: 08003f12 stmeqda r0, {r1, r4, r8, r9, sl, fp, ip, sp} + 1c098: e59d041c ldr r0, [sp, #1052] + 1c09c: e1540000 cmp r4, r0 + 1c0a0: ebf59fb6 bl 0xffd83f80 + 1c0a4: 08003f14 stmeqda r0, {r2, r4, r8, r9, sl, fp, ip, sp} + 1c0a8: e28cc010 add ip, ip, #16 ; 0x10 + 1c0ac: da000004 ble 0x1c0c4 + 1c0b0: e1a00fac mov r0, ip, lsr #31 + 1c0b4: e08ff100 add pc, pc, r0, lsl #2 + 1c0b8: 08003f54 stmeqda r0, {r2, r4, r6, r8, r9, sl, fp, ip, sp} + 1c0bc: ebf59ba4 bl 0xffd82f54 + 1c0c0: ea00009b b 0x1c334 + 1c0c4: ebf59fad bl 0xffd83f80 + 1c0c8: 08003f16 stmeqda r0, {r1, r2, r4, r8, r9, sl, fp, ip, sp} + 1c0cc: e3b06004 movs r6, #4 ; 0x4 + 1c0d0: ebf59faa bl 0xffd83f80 + 1c0d4: 08003f18 stmeqda r0, {r3, r4, r8, r9, sl, fp, ip, sp} + 1c0d8: e3a01000 mov r1, #0 ; 0x0 + 1c0dc: e0516006 subs r6, r1, r6 + 1c0e0: e28cc006 add ip, ip, #6 ; 0x6 + 1c0e4: ebf59fa5 bl 0xffd83f80 + 1c0e8: 08003f1a stmeqda r0, {r1, r3, r4, r8, r9, sl, fp, ip, sp} + 1c0ec: e59d0434 ldr r0, [sp, #1076] + 1c0f0: e2800f01 add r0, r0, #4 ; 0x4 + 1c0f4: ebf59e07 bl 0xffd83918 + 1c0f8: 08003f1e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, fp, ip, sp} + 1c0fc: e1a05000 mov r5, r0 + 1c100: ebf59f9e bl 0xffd83f80 + 1c104: 08003f1c stmeqda r0, {r2, r3, r4, r8, r9, sl, fp, ip, sp} + 1c108: e1a01004 mov r1, r4 + 1c10c: e2943004 adds r3, r4, #4 ; 0x4 + 1c110: ebf59f9a bl 0xffd83f80 + 1c114: 08003f1e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl, fp, ip, sp} + 1c118: e1a00003 mov r0, r3 + 1c11c: e58d0430 str r0, [sp, #1072] + 1c120: ebf59f96 bl 0xffd83f80 + 1c124: 08003f20 stmeqda r0, {r5, r8, r9, sl, fp, ip, sp} + 1c128: e1550006 cmp r5, r6 + 1c12c: ebf59f93 bl 0xffd83f80 + 1c130: 08003f22 stmeqda r0, {r1, r5, r8, r9, sl, fp, ip, sp} + 1c134: e28cc011 add ip, ip, #17 ; 0x11 + 1c138: da000004 ble 0x1c150 + 1c13c: e1a00fac mov r0, ip, lsr #31 + 1c140: e08ff100 add pc, pc, r0, lsl #2 + 1c144: 08003f4c stmeqda r0, {r2, r3, r6, r8, r9, sl, fp, ip, sp} + 1c148: ebf59b81 bl 0xffd82f54 + 1c14c: ea000061 b 0x1c2d8 + 1c150: ebf59f8a bl 0xffd83f80 + 1c154: 08003f24 stmeqda r0, {r2, r5, r8, r9, sl, fp, ip, sp} + 1c158: e1a01004 mov r1, r4 + 1c15c: e0144007 ands r4, r4, r7 + 1c160: ebf59f86 bl 0xffd83f80 + 1c164: 08003f26 stmeqda r0, {r1, r2, r5, r8, r9, sl, fp, ip, sp} + 1c168: e59d1428 ldr r1, [sp, #1064] + 1c16c: e1a03001 mov r3, r1 + 1c170: ebf59f82 bl 0xffd83f80 + 1c174: 08003f28 stmeqda r0, {r3, r5, r8, r9, sl, fp, ip, sp} + 1c178: e1a01003 mov r1, r3 + 1c17c: e0130493 muls r3, r3, r4 + 1c180: ebf59f7e bl 0xffd83f80 + 1c184: 08003f2a stmeqda r0, {r1, r3, r5, r8, r9, sl, fp, ip, sp} + 1c188: e59d0434 ldr r0, [sp, #1076] + 1c18c: e2800f04 add r0, r0, #16 ; 0x10 + 1c190: ebf59de0 bl 0xffd83918 + 1c194: 08003f2e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, fp, ip, sp} + 1c198: e1a04000 mov r4, r0 + 1c19c: ebf59f77 bl 0xffd83f80 + 1c1a0: 08003f2c stmeqda r0, {r2, r3, r5, r8, r9, sl, fp, ip, sp} + 1c1a4: e1a01004 mov r1, r4 + 1c1a8: e0940003 adds r0, r4, r3 + 1c1ac: e58d041c str r0, [sp, #1052] + 1c1b0: ebf59f72 bl 0xffd83f80 + 1c1b4: 08003f2e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl, fp, ip, sp} + 1c1b8: e3b00000 movs r0, #0 ; 0x0 + 1c1bc: e58d0418 str r0, [sp, #1048] + 1c1c0: e28cc014 add ip, ip, #20 ; 0x14 + 1c1c4: ebf59f6d bl 0xffd83f80 + 1c1c8: 08003f30 stmeqda r0, {r4, r5, r8, r9, sl, fp, ip, sp} + 1c1cc: e1a01005 mov r1, r5 + 1c1d0: e2953000 adds r3, r5, #0 ; 0x0 + 1c1d4: ebf59f69 bl 0xffd83f80 + 1c1d8: 08003f32 stmeqda r0, {r1, r4, r5, r8, r9, sl, fp, ip, sp} + 1c1dc: e1a01003 mov r1, r3 + 1c1e0: e0133007 ands r3, r3, r7 + 1c1e4: ebf59f65 bl 0xffd83f80 + 1c1e8: 08003f34 stmeqda r0, {r2, r4, r5, r8, r9, sl, fp, ip, sp} + 1c1ec: e59d141c ldr r1, [sp, #1052] + 1c1f0: e59d141c ldr r1, [sp, #1052] + 1c1f4: e0914003 adds r4, r1, r3 + 1c1f8: ebf59f60 bl 0xffd83f80 + 1c1fc: 08003f36 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl, fp, ip, sp} + 1c200: e1a01005 mov r1, r5 + 1c204: e2958004 adds r8, r5, #4 ; 0x4 + 1c208: ebf59f5c bl 0xffd83f80 + 1c20c: 08003f38 stmeqda r0, {r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c210: e3b05003 movs r5, #3 ; 0x3 + 1c214: e28cc00f add ip, ip, #15 ; 0xf + 1c218: ebf59f58 bl 0xffd83f80 + 1c21c: 08003f3a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c220: e2840002 add r0, r4, #2 ; 0x2 + 1c224: e59d1418 ldr r1, [sp, #1048] + 1c228: ebf59cc7 bl 0xffd8354c + 1c22c: 08003f3c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c230: ebf59f52 bl 0xffd83f80 + 1c234: 08003f3c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c238: e2840000 add r0, r4, #0 ; 0x0 + 1c23c: e59d1418 ldr r1, [sp, #1048] + 1c240: ebf59cc1 bl 0xffd8354c + 1c244: 08003f3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c248: ebf59f4c bl 0xffd83f80 + 1c24c: 08003f3e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c250: e59d1428 ldr r1, [sp, #1064] + 1c254: e0844001 add r4, r4, r1 + 1c258: ebf59f48 bl 0xffd83f80 + 1c25c: 08003f40 stmeqda r0, {r6, r8, r9, sl, fp, ip, sp} + 1c260: e1a01005 mov r1, r5 + 1c264: e2555001 subs r5, r5, #1 ; 0x1 + 1c268: ebf59f44 bl 0xffd83f80 + 1c26c: 08003f42 stmeqda r0, {r1, r6, r8, r9, sl, fp, ip, sp} + 1c270: e3550000 cmp r5, #0 ; 0x0 + 1c274: ebf59f41 bl 0xffd83f80 + 1c278: 08003f44 stmeqda r0, {r2, r6, r8, r9, sl, fp, ip, sp} + 1c27c: e28cc014 add ip, ip, #20 ; 0x14 + 1c280: ba000004 blt 0x1c298 + 1c284: e1a00fac mov r0, ip, lsr #31 + 1c288: e08ff100 add pc, pc, r0, lsl #2 + 1c28c: 08003f3a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl, fp, ip, sp} + 1c290: ebf59b2f bl 0xffd82f54 + 1c294: eaffffdf b 0x1c218 + 1c298: ebf59f38 bl 0xffd83f80 + 1c29c: 08003f46 stmeqda r0, {r1, r2, r6, r8, r9, sl, fp, ip, sp} + 1c2a0: e1a01008 mov r1, r8 + 1c2a4: e2985000 adds r5, r8, #0 ; 0x0 + 1c2a8: ebf59f34 bl 0xffd83f80 + 1c2ac: 08003f48 stmeqda r0, {r3, r6, r8, r9, sl, fp, ip, sp} + 1c2b0: e1550006 cmp r5, r6 + 1c2b4: ebf59f31 bl 0xffd83f80 + 1c2b8: 08003f4a stmeqda r0, {r1, r3, r6, r8, r9, sl, fp, ip, sp} + 1c2bc: e28cc009 add ip, ip, #9 ; 0x9 + 1c2c0: ca000004 bgt 0x1c2d8 + 1c2c4: e1a00fac mov r0, ip, lsr #31 + 1c2c8: e08ff100 add pc, pc, r0, lsl #2 + 1c2cc: 08003f30 stmeqda r0, {r4, r5, r8, r9, sl, fp, ip, sp} + 1c2d0: ebf59b1f bl 0xffd82f54 + 1c2d4: eaffffba b 0x1c1c4 + 1c2d8: ebf59f28 bl 0xffd83f80 + 1c2dc: 08003f4c stmeqda r0, {r2, r3, r6, r8, r9, sl, fp, ip, sp} + 1c2e0: e59d1430 ldr r1, [sp, #1072] + 1c2e4: e1a04001 mov r4, r1 + 1c2e8: ebf59f24 bl 0xffd83f80 + 1c2ec: 08003f4e stmeqda r0, {r1, r2, r3, r6, r8, r9, sl, fp, ip, sp} + 1c2f0: e59d0434 ldr r0, [sp, #1076] + 1c2f4: e2800f03 add r0, r0, #12 ; 0xc + 1c2f8: ebf59d86 bl 0xffd83918 + 1c2fc: 08003f52 stmeqda r0, {r1, r4, r6, r8, r9, sl, fp, ip, sp} + 1c300: e1a05000 mov r5, r0 + 1c304: ebf59f1d bl 0xffd83f80 + 1c308: 08003f50 stmeqda r0, {r4, r6, r8, r9, sl, fp, ip, sp} + 1c30c: e1540005 cmp r4, r5 + 1c310: ebf59f1a bl 0xffd83f80 + 1c314: 08003f52 stmeqda r0, {r1, r4, r6, r8, r9, sl, fp, ip, sp} + 1c318: e28cc00e add ip, ip, #14 ; 0xe + 1c31c: ca000004 bgt 0x1c334 + 1c320: e1a00fac mov r0, ip, lsr #31 + 1c324: e08ff100 add pc, pc, r0, lsl #2 + 1c328: 08003f1a stmeqda r0, {r1, r3, r4, r8, r9, sl, fp, ip, sp} + 1c32c: ebf59b08 bl 0xffd82f54 + 1c330: eaffff6b b 0x1c0e4 + 1c334: ebf59f11 bl 0xffd83f80 + 1c338: 08003f54 stmeqda r0, {r2, r4, r6, r8, r9, sl, fp, ip, sp} + 1c33c: e3b06000 movs r6, #0 ; 0x0 + 1c340: ebf59f0e bl 0xffd83f80 + 1c344: 08003f56 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl, fp, ip, sp} + 1c348: e59d0434 ldr r0, [sp, #1076] + 1c34c: e2800f01 add r0, r0, #4 ; 0x4 + 1c350: e1a01006 mov r1, r6 + 1c354: ebf59c9c bl 0xffd835cc + 1c358: 08003f58 stmeqda r0, {r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c35c: e28cc007 add ip, ip, #7 ; 0x7 + 1c360: ebf59f06 bl 0xffd83f80 + 1c364: 08003f58 stmeqda r0, {r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c368: e59d0434 ldr r0, [sp, #1076] + 1c36c: e2800f00 add r0, r0, #0 ; 0x0 + 1c370: ebf59d68 bl 0xffd83918 + 1c374: 08003f5c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c378: e1a08000 mov r8, r0 + 1c37c: ebf59eff bl 0xffd83f80 + 1c380: 08003f5a stmeqda r0, {r1, r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c384: e3b00010 movs r0, #16 ; 0x10 + 1c388: e58d041c str r0, [sp, #1052] + 1c38c: ebf59efb bl 0xffd83f80 + 1c390: 08003f5c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c394: e59d141c ldr r1, [sp, #1052] + 1c398: e0880001 add r0, r8, r1 + 1c39c: ebf59d46 bl 0xffd838bc + 1c3a0: 08003f60 stmeqda r0, {r5, r6, r8, r9, sl, fp, ip, sp} + 1c3a4: e1a03000 mov r3, r0 + 1c3a8: ebf59ef4 bl 0xffd83f80 + 1c3ac: 08003f5e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, sl, fp, ip, sp} + 1c3b0: e1a01003 mov r1, r3 + 1c3b4: e2533001 subs r3, r3, #1 ; 0x1 + 1c3b8: ebf59ef0 bl 0xffd83f80 + 1c3bc: 08003f60 stmeqda r0, {r5, r6, r8, r9, sl, fp, ip, sp} + 1c3c0: e1b03103 movs r3, r3, lsl #2 + 1c3c4: ebf59eed bl 0xffd83f80 + 1c3c8: 08003f62 stmeqda r0, {r1, r5, r6, r8, r9, sl, fp, ip, sp} + 1c3cc: e1a00003 mov r0, r3 + 1c3d0: e58d0420 str r0, [sp, #1056] + 1c3d4: ebf59ee9 bl 0xffd83f80 + 1c3d8: 08003f64 stmeqda r0, {r2, r5, r6, r8, r9, sl, fp, ip, sp} + 1c3dc: e59d0434 ldr r0, [sp, #1076] + 1c3e0: e2800f01 add r0, r0, #4 ; 0x4 + 1c3e4: ebf59d4b bl 0xffd83918 + 1c3e8: 08003f68 stmeqda r0, {r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c3ec: e1a03000 mov r3, r0 + 1c3f0: ebf59ee2 bl 0xffd83f80 + 1c3f4: 08003f66 stmeqda r0, {r1, r2, r5, r6, r8, r9, sl, fp, ip, sp} + 1c3f8: e1b03143 movs r3, r3, asr #2 + 1c3fc: ebf59edf bl 0xffd83f80 + 1c400: 08003f68 stmeqda r0, {r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c404: e59d0434 ldr r0, [sp, #1076] + 1c408: e2800f0a add r0, r0, #40 ; 0x28 + 1c40c: e1a01003 mov r1, r3 + 1c410: ebf59c6d bl 0xffd835cc + 1c414: 08003f6a stmeqda r0, {r1, r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c418: ebf59ed8 bl 0xffd83f80 + 1c41c: 08003f6a stmeqda r0, {r1, r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c420: e59d0420 ldr r0, [sp, #1056] + 1c424: e59d1424 ldr r1, [sp, #1060] + 1c428: e1500001 cmp r0, r1 + 1c42c: ebf59ed3 bl 0xffd83f80 + 1c430: 08003f6c stmeqda r0, {r2, r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c434: e28cc028 add ip, ip, #40 ; 0x28 + 1c438: ba000004 blt 0x1c450 + 1c43c: e1a00fac mov r0, ip, lsr #31 + 1c440: e08ff100 add pc, pc, r0, lsl #2 + 1c444: 08003fb2 stmeqda r0, {r1, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c448: ebf59ac1 bl 0xffd82f54 + 1c44c: ea0000b3 b 0x1c720 + 1c450: ebf59eca bl 0xffd83f80 + 1c454: 08003f6e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl, fp, ip, sp} + 1c458: e59d0434 ldr r0, [sp, #1076] + 1c45c: e2800f02 add r0, r0, #8 ; 0x8 + 1c460: ebf59d2c bl 0xffd83918 + 1c464: 08003f72 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c468: e1a04000 mov r4, r0 + 1c46c: ebf59ec3 bl 0xffd83f80 + 1c470: 08003f70 stmeqda r0, {r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c474: e59d0434 ldr r0, [sp, #1076] + 1c478: e2800f03 add r0, r0, #12 ; 0xc + 1c47c: ebf59d25 bl 0xffd83918 + 1c480: 08003f74 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c484: e1a05000 mov r5, r0 + 1c488: ebf59ebc bl 0xffd83f80 + 1c48c: 08003f72 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c490: e1540005 cmp r4, r5 + 1c494: ebf59eb9 bl 0xffd83f80 + 1c498: 08003f74 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c49c: e28cc010 add ip, ip, #16 ; 0x10 + 1c4a0: da000004 ble 0x1c4b8 + 1c4a4: e1a00fac mov r0, ip, lsr #31 + 1c4a8: e08ff100 add pc, pc, r0, lsl #2 + 1c4ac: 08003fb0 stmeqda r0, {r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c4b0: ebf59aa7 bl 0xffd82f54 + 1c4b4: ea000093 b 0x1c708 + 1c4b8: ebf59eb0 bl 0xffd83f80 + 1c4bc: 08003f76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c4c0: e59d1420 ldr r1, [sp, #1056] + 1c4c4: e1a05001 mov r5, r1 + 1c4c8: ebf59eac bl 0xffd83f80 + 1c4cc: 08003f78 stmeqda r0, {r3, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c4d0: e1a01004 mov r1, r4 + 1c4d4: e2946004 adds r6, r4, #4 ; 0x4 + 1c4d8: ebf59ea8 bl 0xffd83f80 + 1c4dc: 08003f7a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c4e0: e1a00006 mov r0, r6 + 1c4e4: e58d0430 str r0, [sp, #1072] + 1c4e8: ebf59ea4 bl 0xffd83f80 + 1c4ec: 08003f7c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c4f0: e59d1424 ldr r1, [sp, #1060] + 1c4f4: e1550001 cmp r5, r1 + 1c4f8: ebf59ea0 bl 0xffd83f80 + 1c4fc: 08003f7e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c500: e28cc00f add ip, ip, #15 ; 0xf + 1c504: da000004 ble 0x1c51c + 1c508: e1a00fac mov r0, ip, lsr #31 + 1c50c: e08ff100 add pc, pc, r0, lsl #2 + 1c510: 08003fa8 stmeqda r0, {r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c514: ebf59a8e bl 0xffd82f54 + 1c518: ea000062 b 0x1c6a8 + 1c51c: ebf59e97 bl 0xffd83f80 + 1c520: 08003f80 stmeqda r0, {r7, r8, r9, sl, fp, ip, sp} + 1c524: e1a01004 mov r1, r4 + 1c528: e0144007 ands r4, r4, r7 + 1c52c: ebf59e93 bl 0xffd83f80 + 1c530: 08003f82 stmeqda r0, {r1, r7, r8, r9, sl, fp, ip, sp} + 1c534: e59d1428 ldr r1, [sp, #1064] + 1c538: e1a03001 mov r3, r1 + 1c53c: ebf59e8f bl 0xffd83f80 + 1c540: 08003f84 stmeqda r0, {r2, r7, r8, r9, sl, fp, ip, sp} + 1c544: e1a01003 mov r1, r3 + 1c548: e0130493 muls r3, r3, r4 + 1c54c: ebf59e8b bl 0xffd83f80 + 1c550: 08003f86 stmeqda r0, {r1, r2, r7, r8, r9, sl, fp, ip, sp} + 1c554: e59d0434 ldr r0, [sp, #1076] + 1c558: e2800f04 add r0, r0, #16 ; 0x10 + 1c55c: ebf59ced bl 0xffd83918 + 1c560: 08003f8a stmeqda r0, {r1, r3, r7, r8, r9, sl, fp, ip, sp} + 1c564: e1a08000 mov r8, r0 + 1c568: ebf59e84 bl 0xffd83f80 + 1c56c: 08003f88 stmeqda r0, {r3, r7, r8, r9, sl, fp, ip, sp} + 1c570: e1a01008 mov r1, r8 + 1c574: e0980003 adds r0, r8, r3 + 1c578: e58d041c str r0, [sp, #1052] + 1c57c: ebf59e7f bl 0xffd83f80 + 1c580: 08003f8a stmeqda r0, {r1, r3, r7, r8, r9, sl, fp, ip, sp} + 1c584: e3b00000 movs r0, #0 ; 0x0 + 1c588: e58d0418 str r0, [sp, #1048] + 1c58c: e28cc014 add ip, ip, #20 ; 0x14 + 1c590: ebf59e7a bl 0xffd83f80 + 1c594: 08003f8c stmeqda r0, {r2, r3, r7, r8, r9, sl, fp, ip, sp} + 1c598: e1a01005 mov r1, r5 + 1c59c: e2953000 adds r3, r5, #0 ; 0x0 + 1c5a0: ebf59e76 bl 0xffd83f80 + 1c5a4: 08003f8e stmeqda r0, {r1, r2, r3, r7, r8, r9, sl, fp, ip, sp} + 1c5a8: e1a01003 mov r1, r3 + 1c5ac: e0133007 ands r3, r3, r7 + 1c5b0: ebf59e72 bl 0xffd83f80 + 1c5b4: 08003f90 stmeqda r0, {r4, r7, r8, r9, sl, fp, ip, sp} + 1c5b8: e59d141c ldr r1, [sp, #1052] + 1c5bc: e59d141c ldr r1, [sp, #1052] + 1c5c0: e0914003 adds r4, r1, r3 + 1c5c4: ebf59e6d bl 0xffd83f80 + 1c5c8: 08003f92 stmeqda r0, {r1, r4, r7, r8, r9, sl, fp, ip, sp} + 1c5cc: e1a01005 mov r1, r5 + 1c5d0: e2958004 adds r8, r5, #4 ; 0x4 + 1c5d4: ebf59e69 bl 0xffd83f80 + 1c5d8: 08003f94 stmeqda r0, {r2, r4, r7, r8, r9, sl, fp, ip, sp} + 1c5dc: e3b05003 movs r5, #3 ; 0x3 + 1c5e0: e28cc00f add ip, ip, #15 ; 0xf + 1c5e4: ebf59e65 bl 0xffd83f80 + 1c5e8: 08003f96 stmeqda r0, {r1, r2, r4, r7, r8, r9, sl, fp, ip, sp} + 1c5ec: e2840002 add r0, r4, #2 ; 0x2 + 1c5f0: e59d1418 ldr r1, [sp, #1048] + 1c5f4: ebf59bd4 bl 0xffd8354c + 1c5f8: 08003f98 stmeqda r0, {r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c5fc: ebf59e5f bl 0xffd83f80 + 1c600: 08003f98 stmeqda r0, {r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c604: e2840000 add r0, r4, #0 ; 0x0 + 1c608: e59d1418 ldr r1, [sp, #1048] + 1c60c: ebf59bce bl 0xffd8354c + 1c610: 08003f9a stmeqda r0, {r1, r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c614: ebf59e59 bl 0xffd83f80 + 1c618: 08003f9a stmeqda r0, {r1, r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c61c: e59d1428 ldr r1, [sp, #1064] + 1c620: e0844001 add r4, r4, r1 + 1c624: ebf59e55 bl 0xffd83f80 + 1c628: 08003f9c stmeqda r0, {r2, r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c62c: e1a01005 mov r1, r5 + 1c630: e2555001 subs r5, r5, #1 ; 0x1 + 1c634: ebf59e51 bl 0xffd83f80 + 1c638: 08003f9e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, sl, fp, ip, sp} + 1c63c: e3550000 cmp r5, #0 ; 0x0 + 1c640: ebf59e4e bl 0xffd83f80 + 1c644: 08003fa0 stmeqda r0, {r5, r7, r8, r9, sl, fp, ip, sp} + 1c648: e28cc014 add ip, ip, #20 ; 0x14 + 1c64c: ba000004 blt 0x1c664 + 1c650: e1a00fac mov r0, ip, lsr #31 + 1c654: e08ff100 add pc, pc, r0, lsl #2 + 1c658: 08003f96 stmeqda r0, {r1, r2, r4, r7, r8, r9, sl, fp, ip, sp} + 1c65c: ebf59a3c bl 0xffd82f54 + 1c660: eaffffdf b 0x1c5e4 + 1c664: ebf59e45 bl 0xffd83f80 + 1c668: 08003fa2 stmeqda r0, {r1, r5, r7, r8, r9, sl, fp, ip, sp} + 1c66c: e1a01008 mov r1, r8 + 1c670: e2985000 adds r5, r8, #0 ; 0x0 + 1c674: ebf59e41 bl 0xffd83f80 + 1c678: 08003fa4 stmeqda r0, {r2, r5, r7, r8, r9, sl, fp, ip, sp} + 1c67c: e59d1424 ldr r1, [sp, #1060] + 1c680: e1550001 cmp r5, r1 + 1c684: ebf59e3d bl 0xffd83f80 + 1c688: 08003fa6 stmeqda r0, {r1, r2, r5, r7, r8, r9, sl, fp, ip, sp} + 1c68c: e28cc009 add ip, ip, #9 ; 0x9 + 1c690: ca000004 bgt 0x1c6a8 + 1c694: e1a00fac mov r0, ip, lsr #31 + 1c698: e08ff100 add pc, pc, r0, lsl #2 + 1c69c: 08003f8c stmeqda r0, {r2, r3, r7, r8, r9, sl, fp, ip, sp} + 1c6a0: ebf59a2b bl 0xffd82f54 + 1c6a4: eaffffb9 b 0x1c590 + 1c6a8: ebf59e34 bl 0xffd83f80 + 1c6ac: 08003fa8 stmeqda r0, {r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c6b0: e59d1430 ldr r1, [sp, #1072] + 1c6b4: e1a04001 mov r4, r1 + 1c6b8: ebf59e30 bl 0xffd83f80 + 1c6bc: 08003faa stmeqda r0, {r1, r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c6c0: e59d0434 ldr r0, [sp, #1076] + 1c6c4: e2800f03 add r0, r0, #12 ; 0xc + 1c6c8: ebf59c92 bl 0xffd83918 + 1c6cc: 08003fae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c6d0: e58d041c str r0, [sp, #1052] + 1c6d4: ebf59e29 bl 0xffd83f80 + 1c6d8: 08003fac stmeqda r0, {r2, r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c6dc: e59d041c ldr r0, [sp, #1052] + 1c6e0: e1540000 cmp r4, r0 + 1c6e4: ebf59e25 bl 0xffd83f80 + 1c6e8: 08003fae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, sl, fp, ip, sp} + 1c6ec: e28cc00e add ip, ip, #14 ; 0xe + 1c6f0: ca000004 bgt 0x1c708 + 1c6f4: e1a00fac mov r0, ip, lsr #31 + 1c6f8: e08ff100 add pc, pc, r0, lsl #2 + 1c6fc: 08003f76 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sl, fp, ip, sp} + 1c700: ebf59a13 bl 0xffd82f54 + 1c704: eaffff6b b 0x1c4b8 + 1c708: ebf59e1c bl 0xffd83f80 + 1c70c: 08003fb0 stmeqda r0, {r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c710: e59d1420 ldr r1, [sp, #1056] + 1c714: e1a00001 mov r0, r1 + 1c718: e58d0424 str r0, [sp, #1060] + 1c71c: e28cc003 add ip, ip, #3 ; 0x3 + 1c720: ebf59e16 bl 0xffd83f80 + 1c724: 08003fb2 stmeqda r0, {r1, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c728: e59d0434 ldr r0, [sp, #1076] + 1c72c: e2800f00 add r0, r0, #0 ; 0x0 + 1c730: ebf59c78 bl 0xffd83918 + 1c734: 08003fb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c738: e1a04000 mov r4, r0 + 1c73c: ebf59e0f bl 0xffd83f80 + 1c740: 08003fb4 stmeqda r0, {r2, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c744: e3b05010 movs r5, #16 ; 0x10 + 1c748: ebf59e0c bl 0xffd83f80 + 1c74c: 08003fb6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c750: e0840005 add r0, r4, r5 + 1c754: ebf59c58 bl 0xffd838bc + 1c758: 08003fba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c75c: e1a03000 mov r3, r0 + 1c760: ebf59e06 bl 0xffd83f80 + 1c764: 08003fb8 stmeqda r0, {r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c768: e59d0434 ldr r0, [sp, #1076] + 1c76c: e2800f0b add r0, r0, #44 ; 0x2c + 1c770: ebf59c68 bl 0xffd83918 + 1c774: 08003fbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c778: e1a06000 mov r6, r0 + 1c77c: ebf59dff bl 0xffd83f80 + 1c780: 08003fba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c784: e1a01003 mov r1, r3 + 1c788: e0130693 muls r3, r3, r6 + 1c78c: ebf59dfb bl 0xffd83f80 + 1c790: 08003fbc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c794: e1b03083 movs r3, r3, lsl #1 + 1c798: ebf59df8 bl 0xffd83f80 + 1c79c: 08003fbe stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sl, fp, ip, sp} + 1c7a0: e59d0434 ldr r0, [sp, #1076] + 1c7a4: e2800f09 add r0, r0, #36 ; 0x24 + 1c7a8: ebf59c5a bl 0xffd83918 + 1c7ac: 08003fc2 stmeqda r0, {r1, r6, r7, r8, r9, sl, fp, ip, sp} + 1c7b0: e1a08000 mov r8, r0 + 1c7b4: ebf59df1 bl 0xffd83f80 + 1c7b8: 08003fc0 stmeqda r0, {r6, r7, r8, r9, sl, fp, ip, sp} + 1c7bc: e1a01008 mov r1, r8 + 1c7c0: e0983003 adds r3, r8, r3 + 1c7c4: ebf59ded bl 0xffd83f80 + 1c7c8: 08003fc2 stmeqda r0, {r1, r6, r7, r8, r9, sl, fp, ip, sp} + 1c7cc: e59d0434 ldr r0, [sp, #1076] + 1c7d0: e2800f0a add r0, r0, #40 ; 0x28 + 1c7d4: ebf59c4f bl 0xffd83918 + 1c7d8: 08003fc6 stmeqda r0, {r1, r2, r6, r7, r8, r9, sl, fp, ip, sp} + 1c7dc: e58d041c str r0, [sp, #1052] + 1c7e0: ebf59de6 bl 0xffd83f80 + 1c7e4: 08003fc4 stmeqda r0, {r2, r6, r7, r8, r9, sl, fp, ip, sp} + 1c7e8: e59de41c ldr lr, [sp, #1052] + 1c7ec: e1b0408e movs r4, lr, lsl #1 + 1c7f0: ebf59de2 bl 0xffd83f80 + 1c7f4: 08003fc6 stmeqda r0, {r1, r2, r6, r7, r8, r9, sl, fp, ip, sp} + 1c7f8: e1a01003 mov r1, r3 + 1c7fc: e0933004 adds r3, r3, r4 + 1c800: ebf59dde bl 0xffd83f80 + 1c804: 08003fc8 stmeqda r0, {r3, r6, r7, r8, r9, sl, fp, ip, sp} + 1c808: e1a00003 mov r0, r3 + 1c80c: e58d0420 str r0, [sp, #1056] + 1c810: ebf59dda bl 0xffd83f80 + 1c814: 08003fca stmeqda r0, {r1, r3, r6, r7, r8, r9, sl, fp, ip, sp} + 1c818: e59d0434 ldr r0, [sp, #1076] + 1c81c: e2800f02 add r0, r0, #8 ; 0x8 + 1c820: ebf59c3c bl 0xffd83918 + 1c824: 08003fce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, sl, fp, ip, sp} + 1c828: e1a04000 mov r4, r0 + 1c82c: ebf59dd3 bl 0xffd83f80 + 1c830: 08003fcc stmeqda r0, {r2, r3, r6, r7, r8, r9, sl, fp, ip, sp} + 1c834: e59d0434 ldr r0, [sp, #1076] + 1c838: e2800f03 add r0, r0, #12 ; 0xc + 1c83c: ebf59c35 bl 0xffd83918 + 1c840: 08003fd0 stmeqda r0, {r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c844: e1a03000 mov r3, r0 + 1c848: ebf59dcc bl 0xffd83f80 + 1c84c: 08003fce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, sl, fp, ip, sp} + 1c850: e1540003 cmp r4, r3 + 1c854: ebf59dc9 bl 0xffd83f80 + 1c858: 08003fd0 stmeqda r0, {r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c85c: e28cc03e add ip, ip, #62 ; 0x3e + 1c860: ca000004 bgt 0x1c878 + 1c864: e1a00fac mov r0, ip, lsr #31 + 1c868: e08ff100 add pc, pc, r0, lsl #2 + 1c86c: 08003fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c870: ebf599b7 bl 0xffd82f54 + 1c874: ea000007 b 0x1c898 + 1c878: ebf59dc0 bl 0xffd83f80 + 1c87c: 08003fd2 stmeqda r0, {r1, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c880: e28cc003 add ip, ip, #3 ; 0x3 + 1c884: e1a00fac mov r0, ip, lsr #31 + 1c888: e08ff100 add pc, pc, r0, lsl #2 + 1c88c: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1c890: ebf599af bl 0xffd82f54 + 1c894: ea0006ad b 0x1e350 + 1c898: ebf59db8 bl 0xffd83f80 + 1c89c: 08003fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8a0: e59d0434 ldr r0, [sp, #1076] + 1c8a4: e2800f01 add r0, r0, #4 ; 0x4 + 1c8a8: ebf59c1a bl 0xffd83918 + 1c8ac: 08003fd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8b0: e1a05000 mov r5, r0 + 1c8b4: ebf59db1 bl 0xffd83f80 + 1c8b8: 08003fd6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8bc: e3b06000 movs r6, #0 ; 0x0 + 1c8c0: ebf59dae bl 0xffd83f80 + 1c8c4: 08003fd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8c8: e1a01004 mov r1, r4 + 1c8cc: e2948004 adds r8, r4, #4 ; 0x4 + 1c8d0: ebf59daa bl 0xffd83f80 + 1c8d4: 08003fda stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8d8: e1a00008 mov r0, r8 + 1c8dc: e58d0430 str r0, [sp, #1072] + 1c8e0: ebf59da6 bl 0xffd83f80 + 1c8e4: 08003fdc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8e8: e59d1424 ldr r1, [sp, #1060] + 1c8ec: e1550001 cmp r5, r1 + 1c8f0: ebf59da2 bl 0xffd83f80 + 1c8f4: 08003fde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1c8f8: e28cc014 add ip, ip, #20 ; 0x14 + 1c8fc: da000004 ble 0x1c914 + 1c900: e1a00fac mov r0, ip, lsr #31 + 1c904: e08ff100 add pc, pc, r0, lsl #2 + 1c908: 0800401c stmeqda r0, {r2, r3, r4, lr} + 1c90c: ebf59990 bl 0xffd82f54 + 1c910: ea000094 b 0x1cb68 + 1c914: ebf59d99 bl 0xffd83f80 + 1c918: 08003fe0 stmeqda r0, {r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c91c: e1a01004 mov r1, r4 + 1c920: e0144007 ands r4, r4, r7 + 1c924: ebf59d95 bl 0xffd83f80 + 1c928: 08003fe2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c92c: e59d1428 ldr r1, [sp, #1064] + 1c930: e1a03001 mov r3, r1 + 1c934: ebf59d91 bl 0xffd83f80 + 1c938: 08003fe4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c93c: e1a01003 mov r1, r3 + 1c940: e0130493 muls r3, r3, r4 + 1c944: ebf59d8d bl 0xffd83f80 + 1c948: 08003fe6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c94c: e59d0434 ldr r0, [sp, #1076] + 1c950: e2800f04 add r0, r0, #16 ; 0x10 + 1c954: ebf59bef bl 0xffd83918 + 1c958: 08003fea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c95c: e58d041c str r0, [sp, #1052] + 1c960: ebf59d86 bl 0xffd83f80 + 1c964: 08003fe8 stmeqda r0, {r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c968: e59d141c ldr r1, [sp, #1052] + 1c96c: e59d141c ldr r1, [sp, #1052] + 1c970: e0910003 adds r0, r1, r3 + 1c974: e58d0418 str r0, [sp, #1048] + 1c978: e28cc011 add ip, ip, #17 ; 0x11 + 1c97c: ebf59d7f bl 0xffd83f80 + 1c980: 08003fea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c984: e1a01005 mov r1, r5 + 1c988: e2953000 adds r3, r5, #0 ; 0x0 + 1c98c: ebf59d7b bl 0xffd83f80 + 1c990: 08003fec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c994: e1a01003 mov r1, r3 + 1c998: e0133007 ands r3, r3, r7 + 1c99c: ebf59d77 bl 0xffd83f80 + 1c9a0: 08003fee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9a4: e59d1418 ldr r1, [sp, #1048] + 1c9a8: e59d1418 ldr r1, [sp, #1048] + 1c9ac: e0914003 adds r4, r1, r3 + 1c9b0: ebf59d72 bl 0xffd83f80 + 1c9b4: 08003ff0 stmeqda r0, {r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9b8: e1b03086 movs r3, r6, lsl #1 + 1c9bc: ebf59d6f bl 0xffd83f80 + 1c9c0: 08003ff2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9c4: e59d1420 ldr r1, [sp, #1056] + 1c9c8: e0833001 add r3, r3, r1 + 1c9cc: ebf59d6b bl 0xffd83f80 + 1c9d0: 08003ff4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9d4: e2830000 add r0, r3, #0 ; 0x0 + 1c9d8: ebf59ba2 bl 0xffd83868 + 1c9dc: 08003ff8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9e0: e1a03000 mov r3, r0 + 1c9e4: ebf59d65 bl 0xffd83f80 + 1c9e8: 08003ff6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9ec: e1a01005 mov r1, r5 + 1c9f0: e2958004 adds r8, r5, #4 ; 0x4 + 1c9f4: ebf59d61 bl 0xffd83f80 + 1c9f8: 08003ff8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1c9fc: e1a01006 mov r1, r6 + 1ca00: e2960001 adds r0, r6, #1 ; 0x1 + 1ca04: e58d041c str r0, [sp, #1052] + 1ca08: ebf59d5c bl 0xffd83f80 + 1ca0c: 08003ffa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1ca10: e1b03203 movs r3, r3, lsl #4 + 1ca14: ebf59d59 bl 0xffd83f80 + 1ca18: 08003ffc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1ca1c: e59d0434 ldr r0, [sp, #1076] + 1ca20: e2800f05 add r0, r0, #20 ; 0x14 + 1ca24: ebf59bbb bl 0xffd83918 + 1ca28: 08004000 stmeqda r0, {lr} + 1ca2c: e1a05000 mov r5, r0 + 1ca30: ebf59d52 bl 0xffd83f80 + 1ca34: 08003ffe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1ca38: e1a01005 mov r1, r5 + 1ca3c: e0956003 adds r6, r5, r3 + 1ca40: ebf59d4e bl 0xffd83f80 + 1ca44: 08004000 stmeqda r0, {lr} + 1ca48: e3b05003 movs r5, #3 ; 0x3 + 1ca4c: e28cc028 add ip, ip, #40 ; 0x28 + 1ca50: ebf59d4a bl 0xffd83f80 + 1ca54: 08004002 stmeqda r0, {r1, lr} + 1ca58: e2860000 add r0, r6, #0 ; 0x0 + 1ca5c: ebf59b81 bl 0xffd83868 + 1ca60: 08004006 stmeqda r0, {r1, r2, lr} + 1ca64: e1a03000 mov r3, r0 + 1ca68: ebf59d44 bl 0xffd83f80 + 1ca6c: 08004004 stmeqda r0, {r2, lr} + 1ca70: e2840000 add r0, r4, #0 ; 0x0 + 1ca74: e1a01003 mov r1, r3 + 1ca78: ebf59ab3 bl 0xffd8354c + 1ca7c: 08004006 stmeqda r0, {r1, r2, lr} + 1ca80: ebf59d3e bl 0xffd83f80 + 1ca84: 08004006 stmeqda r0, {r1, r2, lr} + 1ca88: e2860002 add r0, r6, #2 ; 0x2 + 1ca8c: ebf59b75 bl 0xffd83868 + 1ca90: 0800400a stmeqda r0, {r1, r3, lr} + 1ca94: e1a03000 mov r3, r0 + 1ca98: ebf59d38 bl 0xffd83f80 + 1ca9c: 08004008 stmeqda r0, {r3, lr} + 1caa0: e2840002 add r0, r4, #2 ; 0x2 + 1caa4: e1a01003 mov r1, r3 + 1caa8: ebf59aa7 bl 0xffd8354c + 1caac: 0800400a stmeqda r0, {r1, r3, lr} + 1cab0: ebf59d32 bl 0xffd83f80 + 1cab4: 0800400a stmeqda r0, {r1, r3, lr} + 1cab8: e59d1428 ldr r1, [sp, #1064] + 1cabc: e0844001 add r4, r4, r1 + 1cac0: ebf59d2e bl 0xffd83f80 + 1cac4: 0800400c stmeqda r0, {r2, r3, lr} + 1cac8: e1a01006 mov r1, r6 + 1cacc: e2966004 adds r6, r6, #4 ; 0x4 + 1cad0: ebf59d2a bl 0xffd83f80 + 1cad4: 0800400e stmeqda r0, {r1, r2, r3, lr} + 1cad8: e1a01005 mov r1, r5 + 1cadc: e2555001 subs r5, r5, #1 ; 0x1 + 1cae0: ebf59d26 bl 0xffd83f80 + 1cae4: 08004010 stmeqda r0, {r4, lr} + 1cae8: e3550000 cmp r5, #0 ; 0x0 + 1caec: ebf59d23 bl 0xffd83f80 + 1caf0: 08004012 stmeqda r0, {r1, r4, lr} + 1caf4: e28cc021 add ip, ip, #33 ; 0x21 + 1caf8: ba000004 blt 0x1cb10 + 1cafc: e1a00fac mov r0, ip, lsr #31 + 1cb00: e08ff100 add pc, pc, r0, lsl #2 + 1cb04: 08004002 stmeqda r0, {r1, lr} + 1cb08: ebf59911 bl 0xffd82f54 + 1cb0c: eaffffcf b 0x1ca50 + 1cb10: ebf59d1a bl 0xffd83f80 + 1cb14: 08004014 stmeqda r0, {r2, r4, lr} + 1cb18: e1a01008 mov r1, r8 + 1cb1c: e2985000 adds r5, r8, #0 ; 0x0 + 1cb20: ebf59d16 bl 0xffd83f80 + 1cb24: 08004016 stmeqda r0, {r1, r2, r4, lr} + 1cb28: e59d141c ldr r1, [sp, #1052] + 1cb2c: e59d141c ldr r1, [sp, #1052] + 1cb30: e2916000 adds r6, r1, #0 ; 0x0 + 1cb34: ebf59d11 bl 0xffd83f80 + 1cb38: 08004018 stmeqda r0, {r3, r4, lr} + 1cb3c: e59d1424 ldr r1, [sp, #1060] + 1cb40: e1550001 cmp r5, r1 + 1cb44: ebf59d0d bl 0xffd83f80 + 1cb48: 0800401a stmeqda r0, {r1, r3, r4, lr} + 1cb4c: e28cc00c add ip, ip, #12 ; 0xc + 1cb50: ca000004 bgt 0x1cb68 + 1cb54: e1a00fac mov r0, ip, lsr #31 + 1cb58: e08ff100 add pc, pc, r0, lsl #2 + 1cb5c: 08003fea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl, fp, ip, sp} + 1cb60: ebf598fb bl 0xffd82f54 + 1cb64: eaffff84 b 0x1c97c + 1cb68: ebf59d04 bl 0xffd83f80 + 1cb6c: 0800401c stmeqda r0, {r2, r3, r4, lr} + 1cb70: e59d1430 ldr r1, [sp, #1072] + 1cb74: e1a04001 mov r4, r1 + 1cb78: ebf59d00 bl 0xffd83f80 + 1cb7c: 0800401e stmeqda r0, {r1, r2, r3, r4, lr} + 1cb80: e59d0434 ldr r0, [sp, #1076] + 1cb84: e2800f00 add r0, r0, #0 ; 0x0 + 1cb88: ebf59b62 bl 0xffd83918 + 1cb8c: 08004022 stmeqda r0, {r1, r5, lr} + 1cb90: e1a06000 mov r6, r0 + 1cb94: ebf59cf9 bl 0xffd83f80 + 1cb98: 08004020 stmeqda r0, {r5, lr} + 1cb9c: e3b08010 movs r8, #16 ; 0x10 + 1cba0: ebf59cf6 bl 0xffd83f80 + 1cba4: 08004022 stmeqda r0, {r1, r5, lr} + 1cba8: e0860008 add r0, r6, r8 + 1cbac: ebf59b42 bl 0xffd838bc + 1cbb0: 08004026 stmeqda r0, {r1, r2, r5, lr} + 1cbb4: e1a03000 mov r3, r0 + 1cbb8: ebf59cf0 bl 0xffd83f80 + 1cbbc: 08004024 stmeqda r0, {r2, r5, lr} + 1cbc0: e1b03083 movs r3, r3, lsl #1 + 1cbc4: ebf59ced bl 0xffd83f80 + 1cbc8: 08004026 stmeqda r0, {r1, r2, r5, lr} + 1cbcc: e59d0420 ldr r0, [sp, #1056] + 1cbd0: e0800003 add r0, r0, r3 + 1cbd4: e58d0420 str r0, [sp, #1056] + 1cbd8: ebf59ce8 bl 0xffd83f80 + 1cbdc: 08004028 stmeqda r0, {r3, r5, lr} + 1cbe0: e59d0434 ldr r0, [sp, #1076] + 1cbe4: e2800f03 add r0, r0, #12 ; 0xc + 1cbe8: ebf59b4a bl 0xffd83918 + 1cbec: 0800402c stmeqda r0, {r2, r3, r5, lr} + 1cbf0: e58d041c str r0, [sp, #1052] + 1cbf4: ebf59ce1 bl 0xffd83f80 + 1cbf8: 0800402a stmeqda r0, {r1, r3, r5, lr} + 1cbfc: e59d041c ldr r0, [sp, #1052] + 1cc00: e1540000 cmp r4, r0 + 1cc04: ebf59cdd bl 0xffd83f80 + 1cc08: 0800402c stmeqda r0, {r2, r3, r5, lr} + 1cc0c: e28cc021 add ip, ip, #33 ; 0x21 + 1cc10: ca000004 bgt 0x1cc28 + 1cc14: e1a00fac mov r0, ip, lsr #31 + 1cc18: e08ff100 add pc, pc, r0, lsl #2 + 1cc1c: 08003fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, ip, sp} + 1cc20: ebf598cb bl 0xffd82f54 + 1cc24: eaffff1b b 0x1c898 + 1cc28: ebf59cd4 bl 0xffd83f80 + 1cc2c: 0800402e stmeqda r0, {r1, r2, r3, r5, lr} + 1cc30: e28cc003 add ip, ip, #3 ; 0x3 + 1cc34: e1a00fac mov r0, ip, lsr #31 + 1cc38: e08ff100 add pc, pc, r0, lsl #2 + 1cc3c: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1cc40: ebf598c3 bl 0xffd82f54 + 1cc44: ea0005c1 b 0x1e350 + 1cc48: ebf59ccc bl 0xffd83f80 + 1cc4c: 08004030 stmeqda r0, {r4, r5, lr} + 1cc50: e59d0434 ldr r0, [sp, #1076] + 1cc54: e2800f00 add r0, r0, #0 ; 0x0 + 1cc58: ebf59b2e bl 0xffd83918 + 1cc5c: 08004034 stmeqda r0, {r2, r4, r5, lr} + 1cc60: e1a03000 mov r3, r0 + 1cc64: ebf59cc5 bl 0xffd83f80 + 1cc68: 08004032 stmeqda r0, {r1, r4, r5, lr} + 1cc6c: e2830014 add r0, r3, #20 ; 0x14 + 1cc70: ebf59b28 bl 0xffd83918 + 1cc74: 08004036 stmeqda r0, {r1, r2, r4, r5, lr} + 1cc78: e1a03000 mov r3, r0 + 1cc7c: ebf59cbf bl 0xffd83f80 + 1cc80: 08004034 stmeqda r0, {r2, r4, r5, lr} + 1cc84: e1a00003 mov r0, r3 + 1cc88: e58d0428 str r0, [sp, #1064] + 1cc8c: ebf59cbb bl 0xffd83f80 + 1cc90: 08004036 stmeqda r0, {r1, r2, r4, r5, lr} + 1cc94: e59d0434 ldr r0, [sp, #1076] + 1cc98: e2800f00 add r0, r0, #0 ; 0x0 + 1cc9c: ebf59b1d bl 0xffd83918 + 1cca0: 0800403a stmeqda r0, {r1, r3, r4, r5, lr} + 1cca4: e1a04000 mov r4, r0 + 1cca8: ebf59cb4 bl 0xffd83f80 + 1ccac: 08004038 stmeqda r0, {r3, r4, r5, lr} + 1ccb0: e2840004 add r0, r4, #4 ; 0x4 + 1ccb4: ebf59b17 bl 0xffd83918 + 1ccb8: 0800403c stmeqda r0, {r2, r3, r4, r5, lr} + 1ccbc: e1a04000 mov r4, r0 + 1ccc0: ebf59cae bl 0xffd83f80 + 1ccc4: 0800403a stmeqda r0, {r1, r3, r4, r5, lr} + 1ccc8: e59d0434 ldr r0, [sp, #1076] + 1cccc: e2800f06 add r0, r0, #24 ; 0x18 + 1ccd0: e1a01004 mov r1, r4 + 1ccd4: ebf59a3c bl 0xffd835cc + 1ccd8: 0800403c stmeqda r0, {r2, r3, r4, r5, lr} + 1ccdc: ebf59ca7 bl 0xffd83f80 + 1cce0: 0800403c stmeqda r0, {r2, r3, r4, r5, lr} + 1cce4: e59d0434 ldr r0, [sp, #1076] + 1cce8: e2800f00 add r0, r0, #0 ; 0x0 + 1ccec: ebf59b09 bl 0xffd83918 + 1ccf0: 08004040 stmeqda r0, {r6, lr} + 1ccf4: e1a05000 mov r5, r0 + 1ccf8: ebf59ca0 bl 0xffd83f80 + 1ccfc: 0800403e stmeqda r0, {r1, r2, r3, r4, r5, lr} + 1cd00: e2850002 add r0, r5, #2 ; 0x2 + 1cd04: ebf59ad7 bl 0xffd83868 + 1cd08: 08004042 stmeqda r0, {r1, r6, lr} + 1cd0c: e1a04000 mov r4, r0 + 1cd10: ebf59c9a bl 0xffd83f80 + 1cd14: 08004040 stmeqda r0, {r6, lr} + 1cd18: e3b03080 movs r3, #128 ; 0x80 + 1cd1c: ebf59c97 bl 0xffd83f80 + 1cd20: 08004042 stmeqda r0, {r1, r6, lr} + 1cd24: e1b03383 movs r3, r3, lsl #7 + 1cd28: ebf59c94 bl 0xffd83f80 + 1cd2c: 08004044 stmeqda r0, {r2, r6, lr} + 1cd30: e1a01003 mov r1, r3 + 1cd34: e0133004 ands r3, r3, r4 + 1cd38: ebf59c90 bl 0xffd83f80 + 1cd3c: 08004046 stmeqda r0, {r1, r2, r6, lr} + 1cd40: e3530000 cmp r3, #0 ; 0x0 + 1cd44: ebf59c8d bl 0xffd83f80 + 1cd48: 08004048 stmeqda r0, {r3, r6, lr} + 1cd4c: e28cc034 add ip, ip, #52 ; 0x34 + 1cd50: 1a000004 bne 0x1cd68 + 1cd54: e1a00fac mov r0, ip, lsr #31 + 1cd58: e08ff100 add pc, pc, r0, lsl #2 + 1cd5c: 08004060 stmeqda r0, {r5, r6, lr} + 1cd60: ebf5987b bl 0xffd82f54 + 1cd64: ea00003a b 0x1ce54 + 1cd68: ebf59c84 bl 0xffd83f80 + 1cd6c: 0800404a stmeqda r0, {r1, r3, r6, lr} + 1cd70: e3b06005 movs r6, #5 ; 0x5 + 1cd74: ebf59c81 bl 0xffd83f80 + 1cd78: 0800404c stmeqda r0, {r2, r3, r6, lr} + 1cd7c: e59d0434 ldr r0, [sp, #1076] + 1cd80: e2800f07 add r0, r0, #28 ; 0x1c + 1cd84: e1a01006 mov r1, r6 + 1cd88: ebf59a0f bl 0xffd835cc + 1cd8c: 0800404e stmeqda r0, {r1, r2, r3, r6, lr} + 1cd90: ebf59c7a bl 0xffd83f80 + 1cd94: 0800404e stmeqda r0, {r1, r2, r3, r6, lr} + 1cd98: e59d1418 ldr r1, [sp, #1048] + 1cd9c: e59d1418 ldr r1, [sp, #1048] + 1cda0: e2913000 adds r3, r1, #0 ; 0x0 + 1cda4: ebf59c75 bl 0xffd83f80 + 1cda8: 08004050 stmeqda r0, {r4, r6, lr} + 1cdac: e1a01003 mov r1, r3 + 1cdb0: e0133004 ands r3, r3, r4 + 1cdb4: ebf59c71 bl 0xffd83f80 + 1cdb8: 08004052 stmeqda r0, {r1, r4, r6, lr} + 1cdbc: e3b07006 movs r7, #6 ; 0x6 + 1cdc0: ebf59c6e bl 0xffd83f80 + 1cdc4: 08004054 stmeqda r0, {r2, r4, r6, lr} + 1cdc8: e59d0434 ldr r0, [sp, #1076] + 1cdcc: e2800f08 add r0, r0, #32 ; 0x20 + 1cdd0: e1a01007 mov r1, r7 + 1cdd4: ebf599fc bl 0xffd835cc + 1cdd8: 08004056 stmeqda r0, {r1, r2, r4, r6, lr} + 1cddc: ebf59c67 bl 0xffd83f80 + 1cde0: 08004056 stmeqda r0, {r1, r2, r4, r6, lr} + 1cde4: e3530000 cmp r3, #0 ; 0x0 + 1cde8: ebf59c64 bl 0xffd83f80 + 1cdec: 08004058 stmeqda r0, {r3, r4, r6, lr} + 1cdf0: e28cc01a add ip, ip, #26 ; 0x1a + 1cdf4: 1a000004 bne 0x1ce0c + 1cdf8: e1a00fac mov r0, ip, lsr #31 + 1cdfc: e08ff100 add pc, pc, r0, lsl #2 + 1ce00: 08004074 stmeqda r0, {r2, r4, r5, r6, lr} + 1ce04: ebf59852 bl 0xffd82f54 + 1ce08: ea000046 b 0x1cf28 + 1ce0c: ebf59c5b bl 0xffd83f80 + 1ce10: 0800405a stmeqda r0, {r1, r3, r4, r6, lr} + 1ce14: e3b08004 movs r8, #4 ; 0x4 + 1ce18: ebf59c58 bl 0xffd83f80 + 1ce1c: 0800405c stmeqda r0, {r2, r3, r4, r6, lr} + 1ce20: e59d0434 ldr r0, [sp, #1076] + 1ce24: e2800f08 add r0, r0, #32 ; 0x20 + 1ce28: e1a01008 mov r1, r8 + 1ce2c: ebf599e6 bl 0xffd835cc + 1ce30: 0800405e stmeqda r0, {r1, r2, r3, r4, r6, lr} + 1ce34: ebf59c51 bl 0xffd83f80 + 1ce38: 0800405e stmeqda r0, {r1, r2, r3, r4, r6, lr} + 1ce3c: e28cc00a add ip, ip, #10 ; 0xa + 1ce40: e1a00fac mov r0, ip, lsr #31 + 1ce44: e08ff100 add pc, pc, r0, lsl #2 + 1ce48: 08004074 stmeqda r0, {r2, r4, r5, r6, lr} + 1ce4c: ebf59840 bl 0xffd82f54 + 1ce50: ea000034 b 0x1cf28 + 1ce54: ebf59c49 bl 0xffd83f80 + 1ce58: 08004060 stmeqda r0, {r5, r6, lr} + 1ce5c: e3b00006 movs r0, #6 ; 0x6 + 1ce60: e58d041c str r0, [sp, #1052] + 1ce64: ebf59c45 bl 0xffd83f80 + 1ce68: 08004062 stmeqda r0, {r1, r5, r6, lr} + 1ce6c: e59d0434 ldr r0, [sp, #1076] + 1ce70: e2800f07 add r0, r0, #28 ; 0x1c + 1ce74: e59d141c ldr r1, [sp, #1052] + 1ce78: ebf599d3 bl 0xffd835cc + 1ce7c: 08004064 stmeqda r0, {r2, r5, r6, lr} + 1ce80: ebf59c3e bl 0xffd83f80 + 1ce84: 08004064 stmeqda r0, {r2, r5, r6, lr} + 1ce88: e59d1418 ldr r1, [sp, #1048] + 1ce8c: e59d1418 ldr r1, [sp, #1048] + 1ce90: e2913000 adds r3, r1, #0 ; 0x0 + 1ce94: ebf59c39 bl 0xffd83f80 + 1ce98: 08004066 stmeqda r0, {r1, r2, r5, r6, lr} + 1ce9c: e1a01003 mov r1, r3 + 1cea0: e0133004 ands r3, r3, r4 + 1cea4: ebf59c35 bl 0xffd83f80 + 1cea8: 08004068 stmeqda r0, {r3, r5, r6, lr} + 1ceac: e3b04006 movs r4, #6 ; 0x6 + 1ceb0: ebf59c32 bl 0xffd83f80 + 1ceb4: 0800406a stmeqda r0, {r1, r3, r5, r6, lr} + 1ceb8: e59d0434 ldr r0, [sp, #1076] + 1cebc: e2800f08 add r0, r0, #32 ; 0x20 + 1cec0: e1a01004 mov r1, r4 + 1cec4: ebf599c0 bl 0xffd835cc + 1cec8: 0800406c stmeqda r0, {r2, r3, r5, r6, lr} + 1cecc: ebf59c2b bl 0xffd83f80 + 1ced0: 0800406c stmeqda r0, {r2, r3, r5, r6, lr} + 1ced4: e3530000 cmp r3, #0 ; 0x0 + 1ced8: ebf59c28 bl 0xffd83f80 + 1cedc: 0800406e stmeqda r0, {r1, r2, r3, r5, r6, lr} + 1cee0: e28cc01a add ip, ip, #26 ; 0x1a + 1cee4: 1a000004 bne 0x1cefc + 1cee8: e1a00fac mov r0, ip, lsr #31 + 1ceec: e08ff100 add pc, pc, r0, lsl #2 + 1cef0: 08004074 stmeqda r0, {r2, r4, r5, r6, lr} + 1cef4: ebf59816 bl 0xffd82f54 + 1cef8: ea00000a b 0x1cf28 + 1cefc: ebf59c1f bl 0xffd83f80 + 1cf00: 08004070 stmeqda r0, {r4, r5, r6, lr} + 1cf04: e3b05005 movs r5, #5 ; 0x5 + 1cf08: ebf59c1c bl 0xffd83f80 + 1cf0c: 08004072 stmeqda r0, {r1, r4, r5, r6, lr} + 1cf10: e59d0434 ldr r0, [sp, #1076] + 1cf14: e2800f08 add r0, r0, #32 ; 0x20 + 1cf18: e1a01005 mov r1, r5 + 1cf1c: ebf599aa bl 0xffd835cc + 1cf20: 08004074 stmeqda r0, {r2, r4, r5, r6, lr} + 1cf24: e28cc007 add ip, ip, #7 ; 0x7 + 1cf28: ebf59c14 bl 0xffd83f80 + 1cf2c: 08004074 stmeqda r0, {r2, r4, r5, r6, lr} + 1cf30: e59d0434 ldr r0, [sp, #1076] + 1cf34: e2800f00 add r0, r0, #0 ; 0x0 + 1cf38: ebf59a76 bl 0xffd83918 + 1cf3c: 08004078 stmeqda r0, {r3, r4, r5, r6, lr} + 1cf40: e1a06000 mov r6, r0 + 1cf44: ebf59c0d bl 0xffd83f80 + 1cf48: 08004076 stmeqda r0, {r1, r2, r4, r5, r6, lr} + 1cf4c: e286000c add r0, r6, #12 ; 0xc + 1cf50: ebf59a70 bl 0xffd83918 + 1cf54: 0800407a stmeqda r0, {r1, r3, r4, r5, r6, lr} + 1cf58: e1a06000 mov r6, r0 + 1cf5c: ebf59c07 bl 0xffd83f80 + 1cf60: 08004078 stmeqda r0, {r3, r4, r5, r6, lr} + 1cf64: e59d0434 ldr r0, [sp, #1076] + 1cf68: e2800f09 add r0, r0, #36 ; 0x24 + 1cf6c: e1a01006 mov r1, r6 + 1cf70: ebf59995 bl 0xffd835cc + 1cf74: 0800407a stmeqda r0, {r1, r3, r4, r5, r6, lr} + 1cf78: ebf59c00 bl 0xffd83f80 + 1cf7c: 0800407a stmeqda r0, {r1, r3, r4, r5, r6, lr} + 1cf80: e59d0434 ldr r0, [sp, #1076] + 1cf84: e2800f02 add r0, r0, #8 ; 0x8 + 1cf88: ebf59a62 bl 0xffd83918 + 1cf8c: 0800407e stmeqda r0, {r1, r2, r3, r4, r5, r6, lr} + 1cf90: e1a07000 mov r7, r0 + 1cf94: ebf59bf9 bl 0xffd83f80 + 1cf98: 0800407c stmeqda r0, {r2, r3, r4, r5, r6, lr} + 1cf9c: e3570000 cmp r7, #0 ; 0x0 + 1cfa0: ebf59bf6 bl 0xffd83f80 + 1cfa4: 0800407e stmeqda r0, {r1, r2, r3, r4, r5, r6, lr} + 1cfa8: e28cc019 add ip, ip, #25 ; 0x19 + 1cfac: ba000004 blt 0x1cfc4 + 1cfb0: e1a00fac mov r0, ip, lsr #31 + 1cfb4: e08ff100 add pc, pc, r0, lsl #2 + 1cfb8: 080040f0 stmeqda r0, {r4, r5, r6, r7, lr} + 1cfbc: ebf597e4 bl 0xffd82f54 + 1cfc0: ea00010a b 0x1d3f0 + 1cfc4: ebf59bed bl 0xffd83f80 + 1cfc8: 08004080 stmeqda r0, {r7, lr} + 1cfcc: e1a01007 mov r1, r7 + 1cfd0: e2974000 adds r4, r7, #0 ; 0x0 + 1cfd4: ebf59be9 bl 0xffd83f80 + 1cfd8: 08004082 stmeqda r0, {r1, r7, lr} + 1cfdc: e3b03004 movs r3, #4 ; 0x4 + 1cfe0: ebf59be6 bl 0xffd83f80 + 1cfe4: 08004084 stmeqda r0, {r2, r7, lr} + 1cfe8: e3a01000 mov r1, #0 ; 0x0 + 1cfec: e0513003 subs r3, r1, r3 + 1cff0: ebf59be2 bl 0xffd83f80 + 1cff4: 08004086 stmeqda r0, {r1, r2, r7, lr} + 1cff8: e1540003 cmp r4, r3 + 1cffc: ebf59bdf bl 0xffd83f80 + 1d000: 08004088 stmeqda r0, {r3, r7, lr} + 1d004: e28cc00f add ip, ip, #15 ; 0xf + 1d008: da000004 ble 0x1d020 + 1d00c: e1a00fac mov r0, ip, lsr #31 + 1d010: e08ff100 add pc, pc, r0, lsl #2 + 1d014: 080040ec stmeqda r0, {r2, r3, r5, r6, r7, lr} + 1d018: ebf597cd bl 0xffd82f54 + 1d01c: ea0000e8 b 0x1d3c4 + 1d020: ebf59bd6 bl 0xffd83f80 + 1d024: 0800408a stmeqda r0, {r1, r3, r7, lr} + 1d028: e3b0801c movs r8, #28 ; 0x1c + 1d02c: ebf59bd3 bl 0xffd83f80 + 1d030: 0800408c stmeqda r0, {r2, r3, r7, lr} + 1d034: e1a00008 mov r0, r8 + 1d038: e58d0420 str r0, [sp, #1056] + 1d03c: e28cc006 add ip, ip, #6 ; 0x6 + 1d040: ebf59bce bl 0xffd83f80 + 1d044: 0800408e stmeqda r0, {r1, r2, r3, r7, lr} + 1d048: e1a01004 mov r1, r4 + 1d04c: e2940000 adds r0, r4, #0 ; 0x0 + 1d050: e58d0418 str r0, [sp, #1048] + 1d054: ebf59bc9 bl 0xffd83f80 + 1d058: 08004090 stmeqda r0, {r4, r7, lr} + 1d05c: e3b00020 movs r0, #32 ; 0x20 + 1d060: e58d041c str r0, [sp, #1052] + 1d064: ebf59bc5 bl 0xffd83f80 + 1d068: 08004092 stmeqda r0, {r1, r4, r7, lr} + 1d06c: e59d1418 ldr r1, [sp, #1048] + 1d070: e59d1418 ldr r1, [sp, #1048] + 1d074: e59d041c ldr r0, [sp, #1052] + 1d078: e0110000 ands r0, r1, r0 + 1d07c: e58d0418 str r0, [sp, #1048] + 1d080: ebf59bbe bl 0xffd83f80 + 1d084: 08004094 stmeqda r0, {r2, r4, r7, lr} + 1d088: e59d0434 ldr r0, [sp, #1076] + 1d08c: e2800f08 add r0, r0, #32 ; 0x20 + 1d090: ebf59a20 bl 0xffd83918 + 1d094: 08004098 stmeqda r0, {r3, r4, r7, lr} + 1d098: e1a03000 mov r3, r0 + 1d09c: ebf59bb7 bl 0xffd83f80 + 1d0a0: 08004096 stmeqda r0, {r1, r2, r4, r7, lr} + 1d0a4: e59d0418 ldr r0, [sp, #1048] + 1d0a8: e1b00350 movs r0, r0, asr r3 + 1d0ac: e58d0418 str r0, [sp, #1048] + 1d0b0: ebf59bb2 bl 0xffd83f80 + 1d0b4: 08004098 stmeqda r0, {r3, r4, r7, lr} + 1d0b8: e1a01004 mov r1, r4 + 1d0bc: e2947000 adds r7, r4, #0 ; 0x0 + 1d0c0: ebf59bae bl 0xffd83f80 + 1d0c4: 0800409a stmeqda r0, {r1, r3, r4, r7, lr} + 1d0c8: e59d1420 ldr r1, [sp, #1056] + 1d0cc: e1a05001 mov r5, r1 + 1d0d0: ebf59baa bl 0xffd83f80 + 1d0d4: 0800409c stmeqda r0, {r2, r3, r4, r7, lr} + 1d0d8: e1a01007 mov r1, r7 + 1d0dc: e0177005 ands r7, r7, r5 + 1d0e0: ebf59ba6 bl 0xffd83f80 + 1d0e4: 0800409e stmeqda r0, {r1, r2, r3, r4, r7, lr} + 1d0e8: e59d0434 ldr r0, [sp, #1076] + 1d0ec: e2800f01 add r0, r0, #4 ; 0x4 + 1d0f0: ebf59a08 bl 0xffd83918 + 1d0f4: 080040a2 stmeqda r0, {r1, r5, r7, lr} + 1d0f8: e1a05000 mov r5, r0 + 1d0fc: ebf59b9f bl 0xffd83f80 + 1d100: 080040a0 stmeqda r0, {r5, r7, lr} + 1d104: e1a01004 mov r1, r4 + 1d108: e2944004 adds r4, r4, #4 ; 0x4 + 1d10c: ebf59b9b bl 0xffd83f80 + 1d110: 080040a2 stmeqda r0, {r1, r5, r7, lr} + 1d114: e1a00004 mov r0, r4 + 1d118: e58d0430 str r0, [sp, #1072] + 1d11c: ebf59b97 bl 0xffd83f80 + 1d120: 080040a4 stmeqda r0, {r2, r5, r7, lr} + 1d124: e59d1424 ldr r1, [sp, #1060] + 1d128: e1550001 cmp r5, r1 + 1d12c: ebf59b93 bl 0xffd83f80 + 1d130: 080040a6 stmeqda r0, {r1, r2, r5, r7, lr} + 1d134: e28cc02b add ip, ip, #43 ; 0x2b + 1d138: da000004 ble 0x1d150 + 1d13c: e1a00fac mov r0, ip, lsr #31 + 1d140: e08ff100 add pc, pc, r0, lsl #2 + 1d144: 080040e2 stmeqda r0, {r1, r5, r6, r7, lr} + 1d148: ebf59781 bl 0xffd82f54 + 1d14c: ea000085 b 0x1d368 + 1d150: ebf59b8a bl 0xffd83f80 + 1d154: 080040a8 stmeqda r0, {r3, r5, r7, lr} + 1d158: e3b06000 movs r6, #0 ; 0x0 + 1d15c: ebf59b87 bl 0xffd83f80 + 1d160: 080040aa stmeqda r0, {r1, r3, r5, r7, lr} + 1d164: e1b00307 movs r0, r7, lsl #6 + 1d168: e58d041c str r0, [sp, #1052] + 1d16c: e28cc006 add ip, ip, #6 ; 0x6 + 1d170: ebf59b82 bl 0xffd83f80 + 1d174: 080040ac stmeqda r0, {r2, r3, r5, r7, lr} + 1d178: e1a01005 mov r1, r5 + 1d17c: e2954000 adds r4, r5, #0 ; 0x0 + 1d180: ebf59b7e bl 0xffd83f80 + 1d184: 080040ae stmeqda r0, {r1, r2, r3, r5, r7, lr} + 1d188: e3b07020 movs r7, #32 ; 0x20 + 1d18c: ebf59b7b bl 0xffd83f80 + 1d190: 080040b0 stmeqda r0, {r4, r5, r7, lr} + 1d194: e1a01004 mov r1, r4 + 1d198: e0144007 ands r4, r4, r7 + 1d19c: ebf59b77 bl 0xffd83f80 + 1d1a0: 080040b2 stmeqda r0, {r1, r4, r5, r7, lr} + 1d1a4: e59d0434 ldr r0, [sp, #1076] + 1d1a8: e2800f07 add r0, r0, #28 ; 0x1c + 1d1ac: ebf599d9 bl 0xffd83918 + 1d1b0: 080040b6 stmeqda r0, {r1, r2, r4, r5, r7, lr} + 1d1b4: e1a08000 mov r8, r0 + 1d1b8: ebf59b70 bl 0xffd83f80 + 1d1bc: 080040b4 stmeqda r0, {r2, r4, r5, r7, lr} + 1d1c0: e1b04854 movs r4, r4, asr r8 + 1d1c4: ebf59b6d bl 0xffd83f80 + 1d1c8: 080040b6 stmeqda r0, {r1, r2, r4, r5, r7, lr} + 1d1cc: e59d1418 ldr r1, [sp, #1048] + 1d1d0: e59d1418 ldr r1, [sp, #1048] + 1d1d4: e0914004 adds r4, r1, r4 + 1d1d8: ebf59b68 bl 0xffd83f80 + 1d1dc: 080040b8 stmeqda r0, {r3, r4, r5, r7, lr} + 1d1e0: e1b04584 movs r4, r4, lsl #11 + 1d1e4: ebf59b65 bl 0xffd83f80 + 1d1e8: 080040ba stmeqda r0, {r1, r3, r4, r5, r7, lr} + 1d1ec: e59d1428 ldr r1, [sp, #1064] + 1d1f0: e0844001 add r4, r4, r1 + 1d1f4: ebf59b61 bl 0xffd83f80 + 1d1f8: 080040bc stmeqda r0, {r2, r3, r4, r5, r7, lr} + 1d1fc: e1a01004 mov r1, r4 + 1d200: e59d041c ldr r0, [sp, #1052] + 1d204: e0944000 adds r4, r4, r0 + 1d208: ebf59b5c bl 0xffd83f80 + 1d20c: 080040be stmeqda r0, {r1, r2, r3, r4, r5, r7, lr} + 1d210: e1a01005 mov r1, r5 + 1d214: e2953000 adds r3, r5, #0 ; 0x0 + 1d218: ebf59b58 bl 0xffd83f80 + 1d21c: 080040c0 stmeqda r0, {r6, r7, lr} + 1d220: e59d1420 ldr r1, [sp, #1056] + 1d224: e1a07001 mov r7, r1 + 1d228: ebf59b54 bl 0xffd83f80 + 1d22c: 080040c2 stmeqda r0, {r1, r6, r7, lr} + 1d230: e1a01003 mov r1, r3 + 1d234: e0133007 ands r3, r3, r7 + 1d238: ebf59b50 bl 0xffd83f80 + 1d23c: 080040c4 stmeqda r0, {r2, r6, r7, lr} + 1d240: e1b03083 movs r3, r3, lsl #1 + 1d244: ebf59b4d bl 0xffd83f80 + 1d248: 080040c6 stmeqda r0, {r1, r2, r6, r7, lr} + 1d24c: e1a01004 mov r1, r4 + 1d250: e0944003 adds r4, r4, r3 + 1d254: ebf59b49 bl 0xffd83f80 + 1d258: 080040c8 stmeqda r0, {r3, r6, r7, lr} + 1d25c: e1a01005 mov r1, r5 + 1d260: e2958004 adds r8, r5, #4 ; 0x4 + 1d264: ebf59b45 bl 0xffd83f80 + 1d268: 080040ca stmeqda r0, {r1, r3, r6, r7, lr} + 1d26c: e3b05003 movs r5, #3 ; 0x3 + 1d270: e28cc032 add ip, ip, #50 ; 0x32 + 1d274: ebf59b41 bl 0xffd83f80 + 1d278: 080040cc stmeqda r0, {r2, r3, r6, r7, lr} + 1d27c: e2840006 add r0, r4, #6 ; 0x6 + 1d280: e1a01006 mov r1, r6 + 1d284: ebf598b0 bl 0xffd8354c + 1d288: 080040ce stmeqda r0, {r1, r2, r3, r6, r7, lr} + 1d28c: ebf59b3b bl 0xffd83f80 + 1d290: 080040ce stmeqda r0, {r1, r2, r3, r6, r7, lr} + 1d294: e2840004 add r0, r4, #4 ; 0x4 + 1d298: e1a01006 mov r1, r6 + 1d29c: ebf598aa bl 0xffd8354c + 1d2a0: 080040d0 stmeqda r0, {r4, r6, r7, lr} + 1d2a4: ebf59b35 bl 0xffd83f80 + 1d2a8: 080040d0 stmeqda r0, {r4, r6, r7, lr} + 1d2ac: e2840002 add r0, r4, #2 ; 0x2 + 1d2b0: e1a01006 mov r1, r6 + 1d2b4: ebf598a4 bl 0xffd8354c + 1d2b8: 080040d2 stmeqda r0, {r1, r4, r6, r7, lr} + 1d2bc: ebf59b2f bl 0xffd83f80 + 1d2c0: 080040d2 stmeqda r0, {r1, r4, r6, r7, lr} + 1d2c4: e2840000 add r0, r4, #0 ; 0x0 + 1d2c8: e1a01006 mov r1, r6 + 1d2cc: ebf5989e bl 0xffd8354c + 1d2d0: 080040d4 stmeqda r0, {r2, r4, r6, r7, lr} + 1d2d4: ebf59b29 bl 0xffd83f80 + 1d2d8: 080040d4 stmeqda r0, {r2, r4, r6, r7, lr} + 1d2dc: e1a01004 mov r1, r4 + 1d2e0: e2944040 adds r4, r4, #64 ; 0x40 + 1d2e4: ebf59b25 bl 0xffd83f80 + 1d2e8: 080040d6 stmeqda r0, {r1, r2, r4, r6, r7, lr} + 1d2ec: e1a01005 mov r1, r5 + 1d2f0: e2555001 subs r5, r5, #1 ; 0x1 + 1d2f4: ebf59b21 bl 0xffd83f80 + 1d2f8: 080040d8 stmeqda r0, {r3, r4, r6, r7, lr} + 1d2fc: e3550000 cmp r5, #0 ; 0x0 + 1d300: ebf59b1e bl 0xffd83f80 + 1d304: 080040da stmeqda r0, {r1, r3, r4, r6, r7, lr} + 1d308: e28cc01c add ip, ip, #28 ; 0x1c + 1d30c: ba000004 blt 0x1d324 + 1d310: e1a00fac mov r0, ip, lsr #31 + 1d314: e08ff100 add pc, pc, r0, lsl #2 + 1d318: 080040cc stmeqda r0, {r2, r3, r6, r7, lr} + 1d31c: ebf5970c bl 0xffd82f54 + 1d320: eaffffd3 b 0x1d274 + 1d324: ebf59b15 bl 0xffd83f80 + 1d328: 080040dc stmeqda r0, {r2, r3, r4, r6, r7, lr} + 1d32c: e1a01008 mov r1, r8 + 1d330: e2985000 adds r5, r8, #0 ; 0x0 + 1d334: ebf59b11 bl 0xffd83f80 + 1d338: 080040de stmeqda r0, {r1, r2, r3, r4, r6, r7, lr} + 1d33c: e59d1424 ldr r1, [sp, #1060] + 1d340: e1550001 cmp r5, r1 + 1d344: ebf59b0d bl 0xffd83f80 + 1d348: 080040e0 stmeqda r0, {r5, r6, r7, lr} + 1d34c: e28cc009 add ip, ip, #9 ; 0x9 + 1d350: ca000004 bgt 0x1d368 + 1d354: e1a00fac mov r0, ip, lsr #31 + 1d358: e08ff100 add pc, pc, r0, lsl #2 + 1d35c: 080040ac stmeqda r0, {r2, r3, r5, r7, lr} + 1d360: ebf596fb bl 0xffd82f54 + 1d364: eaffff81 b 0x1d170 + 1d368: ebf59b04 bl 0xffd83f80 + 1d36c: 080040e2 stmeqda r0, {r1, r5, r6, r7, lr} + 1d370: e59d1430 ldr r1, [sp, #1072] + 1d374: e1a04001 mov r4, r1 + 1d378: ebf59b00 bl 0xffd83f80 + 1d37c: 080040e4 stmeqda r0, {r2, r5, r6, r7, lr} + 1d380: e3b03004 movs r3, #4 ; 0x4 + 1d384: ebf59afd bl 0xffd83f80 + 1d388: 080040e6 stmeqda r0, {r1, r2, r5, r6, r7, lr} + 1d38c: e3a01000 mov r1, #0 ; 0x0 + 1d390: e0513003 subs r3, r1, r3 + 1d394: ebf59af9 bl 0xffd83f80 + 1d398: 080040e8 stmeqda r0, {r3, r5, r6, r7, lr} + 1d39c: e1540003 cmp r4, r3 + 1d3a0: ebf59af6 bl 0xffd83f80 + 1d3a4: 080040ea stmeqda r0, {r1, r3, r5, r6, r7, lr} + 1d3a8: e28cc00f add ip, ip, #15 ; 0xf + 1d3ac: ca000004 bgt 0x1d3c4 + 1d3b0: e1a00fac mov r0, ip, lsr #31 + 1d3b4: e08ff100 add pc, pc, r0, lsl #2 + 1d3b8: 0800408e stmeqda r0, {r1, r2, r3, r7, lr} + 1d3bc: ebf596e4 bl 0xffd82f54 + 1d3c0: eaffff1e b 0x1d040 + 1d3c4: ebf59aed bl 0xffd83f80 + 1d3c8: 080040ec stmeqda r0, {r2, r3, r5, r6, r7, lr} + 1d3cc: e3b08000 movs r8, #0 ; 0x0 + 1d3d0: ebf59aea bl 0xffd83f80 + 1d3d4: 080040ee stmeqda r0, {r1, r2, r3, r5, r6, r7, lr} + 1d3d8: e59d0434 ldr r0, [sp, #1076] + 1d3dc: e2800f02 add r0, r0, #8 ; 0x8 + 1d3e0: e1a01008 mov r1, r8 + 1d3e4: ebf59878 bl 0xffd835cc + 1d3e8: 080040f0 stmeqda r0, {r4, r5, r6, r7, lr} + 1d3ec: e28cc007 add ip, ip, #7 ; 0x7 + 1d3f0: ebf59ae2 bl 0xffd83f80 + 1d3f4: 080040f0 stmeqda r0, {r4, r5, r6, r7, lr} + 1d3f8: e59d0434 ldr r0, [sp, #1076] + 1d3fc: e2800f00 add r0, r0, #0 ; 0x0 + 1d400: ebf59944 bl 0xffd83918 + 1d404: 080040f4 stmeqda r0, {r2, r4, r5, r6, r7, lr} + 1d408: e58d041c str r0, [sp, #1052] + 1d40c: ebf59adb bl 0xffd83f80 + 1d410: 080040f2 stmeqda r0, {r1, r4, r5, r6, r7, lr} + 1d414: e3b04012 movs r4, #18 ; 0x12 + 1d418: ebf59ad8 bl 0xffd83f80 + 1d41c: 080040f4 stmeqda r0, {r2, r4, r5, r6, r7, lr} + 1d420: e59d041c ldr r0, [sp, #1052] + 1d424: e0800004 add r0, r0, r4 + 1d428: ebf59923 bl 0xffd838bc + 1d42c: 080040f8 stmeqda r0, {r3, r4, r5, r6, r7, lr} + 1d430: e1a03000 mov r3, r0 + 1d434: ebf59ad1 bl 0xffd83f80 + 1d438: 080040f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, lr} + 1d43c: e1a01003 mov r1, r3 + 1d440: e2533001 subs r3, r3, #1 ; 0x1 + 1d444: ebf59acd bl 0xffd83f80 + 1d448: 080040f8 stmeqda r0, {r3, r4, r5, r6, r7, lr} + 1d44c: e1b03103 movs r3, r3, lsl #2 + 1d450: ebf59aca bl 0xffd83f80 + 1d454: 080040fa stmeqda r0, {r1, r3, r4, r5, r6, r7, lr} + 1d458: e1a00003 mov r0, r3 + 1d45c: e58d0420 str r0, [sp, #1056] + 1d460: ebf59ac6 bl 0xffd83f80 + 1d464: 080040fc stmeqda r0, {r2, r3, r4, r5, r6, r7, lr} + 1d468: e59d0434 ldr r0, [sp, #1076] + 1d46c: e2800f02 add r0, r0, #8 ; 0x8 + 1d470: ebf59928 bl 0xffd83918 + 1d474: 08004100 stmeqda r0, {r8, lr} + 1d478: e1a05000 mov r5, r0 + 1d47c: ebf59abf bl 0xffd83f80 + 1d480: 080040fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, lr} + 1d484: e1b05145 movs r5, r5, asr #2 + 1d488: ebf59abc bl 0xffd83f80 + 1d48c: 08004100 stmeqda r0, {r8, lr} + 1d490: e59d0434 ldr r0, [sp, #1076] + 1d494: e2800f0b add r0, r0, #44 ; 0x2c + 1d498: e1a01005 mov r1, r5 + 1d49c: ebf5984a bl 0xffd835cc + 1d4a0: 08004102 stmeqda r0, {r1, r8, lr} + 1d4a4: ebf59ab5 bl 0xffd83f80 + 1d4a8: 08004102 stmeqda r0, {r1, r8, lr} + 1d4ac: e59d0434 ldr r0, [sp, #1076] + 1d4b0: e2800f03 add r0, r0, #12 ; 0xc + 1d4b4: ebf59917 bl 0xffd83918 + 1d4b8: 08004106 stmeqda r0, {r1, r2, r8, lr} + 1d4bc: e1a06000 mov r6, r0 + 1d4c0: ebf59aae bl 0xffd83f80 + 1d4c4: 08004104 stmeqda r0, {r2, r8, lr} + 1d4c8: e59d0420 ldr r0, [sp, #1056] + 1d4cc: e1500006 cmp r0, r6 + 1d4d0: ebf59aaa bl 0xffd83f80 + 1d4d4: 08004106 stmeqda r0, {r1, r2, r8, lr} + 1d4d8: e28cc02d add ip, ip, #45 ; 0x2d + 1d4dc: ba000004 blt 0x1d4f4 + 1d4e0: e1a00fac mov r0, ip, lsr #31 + 1d4e4: e08ff100 add pc, pc, r0, lsl #2 + 1d4e8: 0800416a stmeqda r0, {r1, r3, r5, r6, r8, lr} + 1d4ec: ebf59698 bl 0xffd82f54 + 1d4f0: ea0000f0 b 0x1d8b8 + 1d4f4: ebf59aa1 bl 0xffd83f80 + 1d4f8: 08004108 stmeqda r0, {r3, r8, lr} + 1d4fc: e59d1420 ldr r1, [sp, #1056] + 1d500: e1a04001 mov r4, r1 + 1d504: e28cc003 add ip, ip, #3 ; 0x3 + 1d508: ebf59a9c bl 0xffd83f80 + 1d50c: 0800410a stmeqda r0, {r1, r3, r8, lr} + 1d510: e1a01004 mov r1, r4 + 1d514: e2940000 adds r0, r4, #0 ; 0x0 + 1d518: e58d0418 str r0, [sp, #1048] + 1d51c: ebf59a97 bl 0xffd83f80 + 1d520: 0800410c stmeqda r0, {r2, r3, r8, lr} + 1d524: e3b07020 movs r7, #32 ; 0x20 + 1d528: ebf59a94 bl 0xffd83f80 + 1d52c: 0800410e stmeqda r0, {r1, r2, r3, r8, lr} + 1d530: e59d1418 ldr r1, [sp, #1048] + 1d534: e59d1418 ldr r1, [sp, #1048] + 1d538: e0110007 ands r0, r1, r7 + 1d53c: e58d0418 str r0, [sp, #1048] + 1d540: ebf59a8e bl 0xffd83f80 + 1d544: 08004110 stmeqda r0, {r4, r8, lr} + 1d548: e59d0434 ldr r0, [sp, #1076] + 1d54c: e2800f08 add r0, r0, #32 ; 0x20 + 1d550: ebf598f0 bl 0xffd83918 + 1d554: 08004114 stmeqda r0, {r2, r4, r8, lr} + 1d558: e1a08000 mov r8, r0 + 1d55c: ebf59a87 bl 0xffd83f80 + 1d560: 08004112 stmeqda r0, {r1, r4, r8, lr} + 1d564: e59d0418 ldr r0, [sp, #1048] + 1d568: e1b00850 movs r0, r0, asr r8 + 1d56c: e58d0418 str r0, [sp, #1048] + 1d570: ebf59a82 bl 0xffd83f80 + 1d574: 08004114 stmeqda r0, {r2, r4, r8, lr} + 1d578: e1a01004 mov r1, r4 + 1d57c: e2947000 adds r7, r4, #0 ; 0x0 + 1d580: ebf59a7e bl 0xffd83f80 + 1d584: 08004116 stmeqda r0, {r1, r2, r4, r8, lr} + 1d588: e3b0001c movs r0, #28 ; 0x1c + 1d58c: e58d041c str r0, [sp, #1052] + 1d590: ebf59a7a bl 0xffd83f80 + 1d594: 08004118 stmeqda r0, {r3, r4, r8, lr} + 1d598: e1a01007 mov r1, r7 + 1d59c: e59d041c ldr r0, [sp, #1052] + 1d5a0: e0177000 ands r7, r7, r0 + 1d5a4: ebf59a75 bl 0xffd83f80 + 1d5a8: 0800411a stmeqda r0, {r1, r3, r4, r8, lr} + 1d5ac: e59d0434 ldr r0, [sp, #1076] + 1d5b0: e2800f01 add r0, r0, #4 ; 0x4 + 1d5b4: ebf598d7 bl 0xffd83918 + 1d5b8: 0800411e stmeqda r0, {r1, r2, r3, r4, r8, lr} + 1d5bc: e1a05000 mov r5, r0 + 1d5c0: ebf59a6e bl 0xffd83f80 + 1d5c4: 0800411c stmeqda r0, {r2, r3, r4, r8, lr} + 1d5c8: e1a01004 mov r1, r4 + 1d5cc: e2944004 adds r4, r4, #4 ; 0x4 + 1d5d0: ebf59a6a bl 0xffd83f80 + 1d5d4: 0800411e stmeqda r0, {r1, r2, r3, r4, r8, lr} + 1d5d8: e1a00004 mov r0, r4 + 1d5dc: e58d0430 str r0, [sp, #1072] + 1d5e0: ebf59a66 bl 0xffd83f80 + 1d5e4: 08004120 stmeqda r0, {r5, r8, lr} + 1d5e8: e59d1424 ldr r1, [sp, #1060] + 1d5ec: e1550001 cmp r5, r1 + 1d5f0: ebf59a62 bl 0xffd83f80 + 1d5f4: 08004122 stmeqda r0, {r1, r5, r8, lr} + 1d5f8: e28cc02b add ip, ip, #43 ; 0x2b + 1d5fc: da000004 ble 0x1d614 + 1d600: e1a00fac mov r0, ip, lsr #31 + 1d604: e08ff100 add pc, pc, r0, lsl #2 + 1d608: 0800415e stmeqda r0, {r1, r2, r3, r4, r6, r8, lr} + 1d60c: ebf59650 bl 0xffd82f54 + 1d610: ea000084 b 0x1d828 + 1d614: ebf59a59 bl 0xffd83f80 + 1d618: 08004124 stmeqda r0, {r2, r5, r8, lr} + 1d61c: e3b06000 movs r6, #0 ; 0x0 + 1d620: ebf59a56 bl 0xffd83f80 + 1d624: 08004126 stmeqda r0, {r1, r2, r5, r8, lr} + 1d628: e1b00307 movs r0, r7, lsl #6 + 1d62c: e58d041c str r0, [sp, #1052] + 1d630: e28cc006 add ip, ip, #6 ; 0x6 + 1d634: ebf59a51 bl 0xffd83f80 + 1d638: 08004128 stmeqda r0, {r3, r5, r8, lr} + 1d63c: e1a01005 mov r1, r5 + 1d640: e2954000 adds r4, r5, #0 ; 0x0 + 1d644: ebf59a4d bl 0xffd83f80 + 1d648: 0800412a stmeqda r0, {r1, r3, r5, r8, lr} + 1d64c: e3b03020 movs r3, #32 ; 0x20 + 1d650: ebf59a4a bl 0xffd83f80 + 1d654: 0800412c stmeqda r0, {r2, r3, r5, r8, lr} + 1d658: e1a01004 mov r1, r4 + 1d65c: e0144003 ands r4, r4, r3 + 1d660: ebf59a46 bl 0xffd83f80 + 1d664: 0800412e stmeqda r0, {r1, r2, r3, r5, r8, lr} + 1d668: e59d0434 ldr r0, [sp, #1076] + 1d66c: e2800f07 add r0, r0, #28 ; 0x1c + 1d670: ebf598a8 bl 0xffd83918 + 1d674: 08004132 stmeqda r0, {r1, r4, r5, r8, lr} + 1d678: e1a07000 mov r7, r0 + 1d67c: ebf59a3f bl 0xffd83f80 + 1d680: 08004130 stmeqda r0, {r4, r5, r8, lr} + 1d684: e1b04754 movs r4, r4, asr r7 + 1d688: ebf59a3c bl 0xffd83f80 + 1d68c: 08004132 stmeqda r0, {r1, r4, r5, r8, lr} + 1d690: e59d1418 ldr r1, [sp, #1048] + 1d694: e59d1418 ldr r1, [sp, #1048] + 1d698: e0914004 adds r4, r1, r4 + 1d69c: ebf59a37 bl 0xffd83f80 + 1d6a0: 08004134 stmeqda r0, {r2, r4, r5, r8, lr} + 1d6a4: e1b04584 movs r4, r4, lsl #11 + 1d6a8: ebf59a34 bl 0xffd83f80 + 1d6ac: 08004136 stmeqda r0, {r1, r2, r4, r5, r8, lr} + 1d6b0: e59d1428 ldr r1, [sp, #1064] + 1d6b4: e0844001 add r4, r4, r1 + 1d6b8: ebf59a30 bl 0xffd83f80 + 1d6bc: 08004138 stmeqda r0, {r3, r4, r5, r8, lr} + 1d6c0: e1a01004 mov r1, r4 + 1d6c4: e59d041c ldr r0, [sp, #1052] + 1d6c8: e0944000 adds r4, r4, r0 + 1d6cc: ebf59a2b bl 0xffd83f80 + 1d6d0: 0800413a stmeqda r0, {r1, r3, r4, r5, r8, lr} + 1d6d4: e1a01005 mov r1, r5 + 1d6d8: e2953000 adds r3, r5, #0 ; 0x0 + 1d6dc: ebf59a27 bl 0xffd83f80 + 1d6e0: 0800413c stmeqda r0, {r2, r3, r4, r5, r8, lr} + 1d6e4: e3b0801c movs r8, #28 ; 0x1c + 1d6e8: ebf59a24 bl 0xffd83f80 + 1d6ec: 0800413e stmeqda r0, {r1, r2, r3, r4, r5, r8, lr} + 1d6f0: e1a01003 mov r1, r3 + 1d6f4: e0133008 ands r3, r3, r8 + 1d6f8: ebf59a20 bl 0xffd83f80 + 1d6fc: 08004140 stmeqda r0, {r6, r8, lr} + 1d700: e1b03083 movs r3, r3, lsl #1 + 1d704: ebf59a1d bl 0xffd83f80 + 1d708: 08004142 stmeqda r0, {r1, r6, r8, lr} + 1d70c: e1a01004 mov r1, r4 + 1d710: e0944003 adds r4, r4, r3 + 1d714: ebf59a19 bl 0xffd83f80 + 1d718: 08004144 stmeqda r0, {r2, r6, r8, lr} + 1d71c: e1a01005 mov r1, r5 + 1d720: e2958004 adds r8, r5, #4 ; 0x4 + 1d724: ebf59a15 bl 0xffd83f80 + 1d728: 08004146 stmeqda r0, {r1, r2, r6, r8, lr} + 1d72c: e3b05003 movs r5, #3 ; 0x3 + 1d730: e28cc032 add ip, ip, #50 ; 0x32 + 1d734: ebf59a11 bl 0xffd83f80 + 1d738: 08004148 stmeqda r0, {r3, r6, r8, lr} + 1d73c: e2840006 add r0, r4, #6 ; 0x6 + 1d740: e1a01006 mov r1, r6 + 1d744: ebf59780 bl 0xffd8354c + 1d748: 0800414a stmeqda r0, {r1, r3, r6, r8, lr} + 1d74c: ebf59a0b bl 0xffd83f80 + 1d750: 0800414a stmeqda r0, {r1, r3, r6, r8, lr} + 1d754: e2840004 add r0, r4, #4 ; 0x4 + 1d758: e1a01006 mov r1, r6 + 1d75c: ebf5977a bl 0xffd8354c + 1d760: 0800414c stmeqda r0, {r2, r3, r6, r8, lr} + 1d764: ebf59a05 bl 0xffd83f80 + 1d768: 0800414c stmeqda r0, {r2, r3, r6, r8, lr} + 1d76c: e2840002 add r0, r4, #2 ; 0x2 + 1d770: e1a01006 mov r1, r6 + 1d774: ebf59774 bl 0xffd8354c + 1d778: 0800414e stmeqda r0, {r1, r2, r3, r6, r8, lr} + 1d77c: ebf599ff bl 0xffd83f80 + 1d780: 0800414e stmeqda r0, {r1, r2, r3, r6, r8, lr} + 1d784: e2840000 add r0, r4, #0 ; 0x0 + 1d788: e1a01006 mov r1, r6 + 1d78c: ebf5976e bl 0xffd8354c + 1d790: 08004150 stmeqda r0, {r4, r6, r8, lr} + 1d794: ebf599f9 bl 0xffd83f80 + 1d798: 08004150 stmeqda r0, {r4, r6, r8, lr} + 1d79c: e1a01004 mov r1, r4 + 1d7a0: e2944040 adds r4, r4, #64 ; 0x40 + 1d7a4: ebf599f5 bl 0xffd83f80 + 1d7a8: 08004152 stmeqda r0, {r1, r4, r6, r8, lr} + 1d7ac: e1a01005 mov r1, r5 + 1d7b0: e2555001 subs r5, r5, #1 ; 0x1 + 1d7b4: ebf599f1 bl 0xffd83f80 + 1d7b8: 08004154 stmeqda r0, {r2, r4, r6, r8, lr} + 1d7bc: e3550000 cmp r5, #0 ; 0x0 + 1d7c0: ebf599ee bl 0xffd83f80 + 1d7c4: 08004156 stmeqda r0, {r1, r2, r4, r6, r8, lr} + 1d7c8: e28cc01c add ip, ip, #28 ; 0x1c + 1d7cc: ba000004 blt 0x1d7e4 + 1d7d0: e1a00fac mov r0, ip, lsr #31 + 1d7d4: e08ff100 add pc, pc, r0, lsl #2 + 1d7d8: 08004148 stmeqda r0, {r3, r6, r8, lr} + 1d7dc: ebf595dc bl 0xffd82f54 + 1d7e0: eaffffd3 b 0x1d734 + 1d7e4: ebf599e5 bl 0xffd83f80 + 1d7e8: 08004158 stmeqda r0, {r3, r4, r6, r8, lr} + 1d7ec: e1a01008 mov r1, r8 + 1d7f0: e2985000 adds r5, r8, #0 ; 0x0 + 1d7f4: ebf599e1 bl 0xffd83f80 + 1d7f8: 0800415a stmeqda r0, {r1, r3, r4, r6, r8, lr} + 1d7fc: e59d1424 ldr r1, [sp, #1060] + 1d800: e1550001 cmp r5, r1 + 1d804: ebf599dd bl 0xffd83f80 + 1d808: 0800415c stmeqda r0, {r2, r3, r4, r6, r8, lr} + 1d80c: e28cc009 add ip, ip, #9 ; 0x9 + 1d810: ca000004 bgt 0x1d828 + 1d814: e1a00fac mov r0, ip, lsr #31 + 1d818: e08ff100 add pc, pc, r0, lsl #2 + 1d81c: 08004128 stmeqda r0, {r3, r5, r8, lr} + 1d820: ebf595cb bl 0xffd82f54 + 1d824: eaffff82 b 0x1d634 + 1d828: ebf599d4 bl 0xffd83f80 + 1d82c: 0800415e stmeqda r0, {r1, r2, r3, r4, r6, r8, lr} + 1d830: e59d1430 ldr r1, [sp, #1072] + 1d834: e1a04001 mov r4, r1 + 1d838: ebf599d0 bl 0xffd83f80 + 1d83c: 08004160 stmeqda r0, {r5, r6, r8, lr} + 1d840: e59d0434 ldr r0, [sp, #1076] + 1d844: e2800f03 add r0, r0, #12 ; 0xc + 1d848: ebf59832 bl 0xffd83918 + 1d84c: 08004164 stmeqda r0, {r2, r5, r6, r8, lr} + 1d850: e58d041c str r0, [sp, #1052] + 1d854: ebf599c9 bl 0xffd83f80 + 1d858: 08004162 stmeqda r0, {r1, r5, r6, r8, lr} + 1d85c: e59d041c ldr r0, [sp, #1052] + 1d860: e1540000 cmp r4, r0 + 1d864: ebf599c5 bl 0xffd83f80 + 1d868: 08004164 stmeqda r0, {r2, r5, r6, r8, lr} + 1d86c: e28cc00e add ip, ip, #14 ; 0xe + 1d870: ca000004 bgt 0x1d888 + 1d874: e1a00fac mov r0, ip, lsr #31 + 1d878: e08ff100 add pc, pc, r0, lsl #2 + 1d87c: 0800410a stmeqda r0, {r1, r3, r8, lr} + 1d880: ebf595b3 bl 0xffd82f54 + 1d884: eaffff1f b 0x1d508 + 1d888: ebf599bc bl 0xffd83f80 + 1d88c: 08004166 stmeqda r0, {r1, r2, r5, r6, r8, lr} + 1d890: e59d1420 ldr r1, [sp, #1056] + 1d894: e1a03001 mov r3, r1 + 1d898: ebf599b8 bl 0xffd83f80 + 1d89c: 08004168 stmeqda r0, {r3, r5, r6, r8, lr} + 1d8a0: e59d0434 ldr r0, [sp, #1076] + 1d8a4: e2800f03 add r0, r0, #12 ; 0xc + 1d8a8: e1a01003 mov r1, r3 + 1d8ac: ebf59746 bl 0xffd835cc + 1d8b0: 0800416a stmeqda r0, {r1, r3, r5, r6, r8, lr} + 1d8b4: e28cc007 add ip, ip, #7 ; 0x7 + 1d8b8: ebf599b0 bl 0xffd83f80 + 1d8bc: 0800416a stmeqda r0, {r1, r3, r5, r6, r8, lr} + 1d8c0: e59d0434 ldr r0, [sp, #1076] + 1d8c4: e2800f01 add r0, r0, #4 ; 0x4 + 1d8c8: ebf59812 bl 0xffd83918 + 1d8cc: 0800416e stmeqda r0, {r1, r2, r3, r5, r6, r8, lr} + 1d8d0: e1a04000 mov r4, r0 + 1d8d4: ebf599a9 bl 0xffd83f80 + 1d8d8: 0800416c stmeqda r0, {r2, r3, r5, r6, r8, lr} + 1d8dc: e3540000 cmp r4, #0 ; 0x0 + 1d8e0: ebf599a6 bl 0xffd83f80 + 1d8e4: 0800416e stmeqda r0, {r1, r2, r3, r5, r6, r8, lr} + 1d8e8: e28cc00b add ip, ip, #11 ; 0xb + 1d8ec: ba000004 blt 0x1d904 + 1d8f0: e1a00fac mov r0, ip, lsr #31 + 1d8f4: e08ff100 add pc, pc, r0, lsl #2 + 1d8f8: 080041de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, lr} + 1d8fc: ebf59594 bl 0xffd82f54 + 1d900: ea000110 b 0x1dd48 + 1d904: ebf5999d bl 0xffd83f80 + 1d908: 08004170 stmeqda r0, {r4, r5, r6, r8, lr} + 1d90c: e59d0434 ldr r0, [sp, #1076] + 1d910: e2800f02 add r0, r0, #8 ; 0x8 + 1d914: ebf597ff bl 0xffd83918 + 1d918: 08004174 stmeqda r0, {r2, r4, r5, r6, r8, lr} + 1d91c: e1a04000 mov r4, r0 + 1d920: ebf59996 bl 0xffd83f80 + 1d924: 08004172 stmeqda r0, {r1, r4, r5, r6, r8, lr} + 1d928: e59d0434 ldr r0, [sp, #1076] + 1d92c: e2800f03 add r0, r0, #12 ; 0xc + 1d930: ebf597f8 bl 0xffd83918 + 1d934: 08004176 stmeqda r0, {r1, r2, r4, r5, r6, r8, lr} + 1d938: e1a05000 mov r5, r0 + 1d93c: ebf5998f bl 0xffd83f80 + 1d940: 08004174 stmeqda r0, {r2, r4, r5, r6, r8, lr} + 1d944: e1540005 cmp r4, r5 + 1d948: ebf5998c bl 0xffd83f80 + 1d94c: 08004176 stmeqda r0, {r1, r2, r4, r5, r6, r8, lr} + 1d950: e28cc010 add ip, ip, #16 ; 0x10 + 1d954: da000004 ble 0x1d96c + 1d958: e1a00fac mov r0, ip, lsr #31 + 1d95c: e08ff100 add pc, pc, r0, lsl #2 + 1d960: 080041da stmeqda r0, {r1, r3, r4, r6, r7, r8, lr} + 1d964: ebf5957a bl 0xffd82f54 + 1d968: ea0000eb b 0x1dd1c + 1d96c: ebf59983 bl 0xffd83f80 + 1d970: 08004178 stmeqda r0, {r3, r4, r5, r6, r8, lr} + 1d974: e3b06004 movs r6, #4 ; 0x4 + 1d978: ebf59980 bl 0xffd83f80 + 1d97c: 0800417a stmeqda r0, {r1, r3, r4, r5, r6, r8, lr} + 1d980: e3a01000 mov r1, #0 ; 0x0 + 1d984: e0516006 subs r6, r1, r6 + 1d988: ebf5997c bl 0xffd83f80 + 1d98c: 0800417c stmeqda r0, {r2, r3, r4, r5, r6, r8, lr} + 1d990: e1a00006 mov r0, r6 + 1d994: e58d0420 str r0, [sp, #1056] + 1d998: e28cc009 add ip, ip, #9 ; 0x9 + 1d99c: ebf59977 bl 0xffd83f80 + 1d9a0: 0800417e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, lr} + 1d9a4: e1a01004 mov r1, r4 + 1d9a8: e2940000 adds r0, r4, #0 ; 0x0 + 1d9ac: e58d0418 str r0, [sp, #1048] + 1d9b0: ebf59972 bl 0xffd83f80 + 1d9b4: 08004180 stmeqda r0, {r7, r8, lr} + 1d9b8: e3b07020 movs r7, #32 ; 0x20 + 1d9bc: ebf5996f bl 0xffd83f80 + 1d9c0: 08004182 stmeqda r0, {r1, r7, r8, lr} + 1d9c4: e59d1418 ldr r1, [sp, #1048] + 1d9c8: e59d1418 ldr r1, [sp, #1048] + 1d9cc: e0110007 ands r0, r1, r7 + 1d9d0: e58d0418 str r0, [sp, #1048] + 1d9d4: ebf59969 bl 0xffd83f80 + 1d9d8: 08004184 stmeqda r0, {r2, r7, r8, lr} + 1d9dc: e59d0434 ldr r0, [sp, #1076] + 1d9e0: e2800f08 add r0, r0, #32 ; 0x20 + 1d9e4: ebf597cb bl 0xffd83918 + 1d9e8: 08004188 stmeqda r0, {r3, r7, r8, lr} + 1d9ec: e1a08000 mov r8, r0 + 1d9f0: ebf59962 bl 0xffd83f80 + 1d9f4: 08004186 stmeqda r0, {r1, r2, r7, r8, lr} + 1d9f8: e59d0418 ldr r0, [sp, #1048] + 1d9fc: e1b00850 movs r0, r0, asr r8 + 1da00: e58d0418 str r0, [sp, #1048] + 1da04: ebf5995d bl 0xffd83f80 + 1da08: 08004188 stmeqda r0, {r3, r7, r8, lr} + 1da0c: e1a01004 mov r1, r4 + 1da10: e2947000 adds r7, r4, #0 ; 0x0 + 1da14: ebf59959 bl 0xffd83f80 + 1da18: 0800418a stmeqda r0, {r1, r3, r7, r8, lr} + 1da1c: e3b0001c movs r0, #28 ; 0x1c + 1da20: e58d041c str r0, [sp, #1052] + 1da24: ebf59955 bl 0xffd83f80 + 1da28: 0800418c stmeqda r0, {r2, r3, r7, r8, lr} + 1da2c: e1a01007 mov r1, r7 + 1da30: e59d041c ldr r0, [sp, #1052] + 1da34: e0177000 ands r7, r7, r0 + 1da38: ebf59950 bl 0xffd83f80 + 1da3c: 0800418e stmeqda r0, {r1, r2, r3, r7, r8, lr} + 1da40: e59d0434 ldr r0, [sp, #1076] + 1da44: e2800f01 add r0, r0, #4 ; 0x4 + 1da48: ebf597b2 bl 0xffd83918 + 1da4c: 08004192 stmeqda r0, {r1, r4, r7, r8, lr} + 1da50: e1a05000 mov r5, r0 + 1da54: ebf59949 bl 0xffd83f80 + 1da58: 08004190 stmeqda r0, {r4, r7, r8, lr} + 1da5c: e1a01004 mov r1, r4 + 1da60: e2944004 adds r4, r4, #4 ; 0x4 + 1da64: ebf59945 bl 0xffd83f80 + 1da68: 08004192 stmeqda r0, {r1, r4, r7, r8, lr} + 1da6c: e1a00004 mov r0, r4 + 1da70: e58d0430 str r0, [sp, #1072] + 1da74: ebf59941 bl 0xffd83f80 + 1da78: 08004194 stmeqda r0, {r2, r4, r7, r8, lr} + 1da7c: e59d1420 ldr r1, [sp, #1056] + 1da80: e1550001 cmp r5, r1 + 1da84: ebf5993d bl 0xffd83f80 + 1da88: 08004196 stmeqda r0, {r1, r2, r4, r7, r8, lr} + 1da8c: e28cc02b add ip, ip, #43 ; 0x2b + 1da90: da000004 ble 0x1daa8 + 1da94: e1a00fac mov r0, ip, lsr #31 + 1da98: e08ff100 add pc, pc, r0, lsl #2 + 1da9c: 080041d2 stmeqda r0, {r1, r4, r6, r7, r8, lr} + 1daa0: ebf5952b bl 0xffd82f54 + 1daa4: ea000084 b 0x1dcbc + 1daa8: ebf59934 bl 0xffd83f80 + 1daac: 08004198 stmeqda r0, {r3, r4, r7, r8, lr} + 1dab0: e3b06000 movs r6, #0 ; 0x0 + 1dab4: ebf59931 bl 0xffd83f80 + 1dab8: 0800419a stmeqda r0, {r1, r3, r4, r7, r8, lr} + 1dabc: e1b00307 movs r0, r7, lsl #6 + 1dac0: e58d041c str r0, [sp, #1052] + 1dac4: e28cc006 add ip, ip, #6 ; 0x6 + 1dac8: ebf5992c bl 0xffd83f80 + 1dacc: 0800419c stmeqda r0, {r2, r3, r4, r7, r8, lr} + 1dad0: e1a01005 mov r1, r5 + 1dad4: e2954000 adds r4, r5, #0 ; 0x0 + 1dad8: ebf59928 bl 0xffd83f80 + 1dadc: 0800419e stmeqda r0, {r1, r2, r3, r4, r7, r8, lr} + 1dae0: e3b03020 movs r3, #32 ; 0x20 + 1dae4: ebf59925 bl 0xffd83f80 + 1dae8: 080041a0 stmeqda r0, {r5, r7, r8, lr} + 1daec: e1a01004 mov r1, r4 + 1daf0: e0144003 ands r4, r4, r3 + 1daf4: ebf59921 bl 0xffd83f80 + 1daf8: 080041a2 stmeqda r0, {r1, r5, r7, r8, lr} + 1dafc: e59d0434 ldr r0, [sp, #1076] + 1db00: e2800f07 add r0, r0, #28 ; 0x1c + 1db04: ebf59783 bl 0xffd83918 + 1db08: 080041a6 stmeqda r0, {r1, r2, r5, r7, r8, lr} + 1db0c: e1a07000 mov r7, r0 + 1db10: ebf5991a bl 0xffd83f80 + 1db14: 080041a4 stmeqda r0, {r2, r5, r7, r8, lr} + 1db18: e1b04754 movs r4, r4, asr r7 + 1db1c: ebf59917 bl 0xffd83f80 + 1db20: 080041a6 stmeqda r0, {r1, r2, r5, r7, r8, lr} + 1db24: e59d1418 ldr r1, [sp, #1048] + 1db28: e59d1418 ldr r1, [sp, #1048] + 1db2c: e0914004 adds r4, r1, r4 + 1db30: ebf59912 bl 0xffd83f80 + 1db34: 080041a8 stmeqda r0, {r3, r5, r7, r8, lr} + 1db38: e1b04584 movs r4, r4, lsl #11 + 1db3c: ebf5990f bl 0xffd83f80 + 1db40: 080041aa stmeqda r0, {r1, r3, r5, r7, r8, lr} + 1db44: e59d1428 ldr r1, [sp, #1064] + 1db48: e0844001 add r4, r4, r1 + 1db4c: ebf5990b bl 0xffd83f80 + 1db50: 080041ac stmeqda r0, {r2, r3, r5, r7, r8, lr} + 1db54: e1a01004 mov r1, r4 + 1db58: e59d041c ldr r0, [sp, #1052] + 1db5c: e0944000 adds r4, r4, r0 + 1db60: ebf59906 bl 0xffd83f80 + 1db64: 080041ae stmeqda r0, {r1, r2, r3, r5, r7, r8, lr} + 1db68: e1a01005 mov r1, r5 + 1db6c: e2953000 adds r3, r5, #0 ; 0x0 + 1db70: ebf59902 bl 0xffd83f80 + 1db74: 080041b0 stmeqda r0, {r4, r5, r7, r8, lr} + 1db78: e3b0801c movs r8, #28 ; 0x1c + 1db7c: ebf598ff bl 0xffd83f80 + 1db80: 080041b2 stmeqda r0, {r1, r4, r5, r7, r8, lr} + 1db84: e1a01003 mov r1, r3 + 1db88: e0133008 ands r3, r3, r8 + 1db8c: ebf598fb bl 0xffd83f80 + 1db90: 080041b4 stmeqda r0, {r2, r4, r5, r7, r8, lr} + 1db94: e1b03083 movs r3, r3, lsl #1 + 1db98: ebf598f8 bl 0xffd83f80 + 1db9c: 080041b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, lr} + 1dba0: e1a01004 mov r1, r4 + 1dba4: e0944003 adds r4, r4, r3 + 1dba8: ebf598f4 bl 0xffd83f80 + 1dbac: 080041b8 stmeqda r0, {r3, r4, r5, r7, r8, lr} + 1dbb0: e1a01005 mov r1, r5 + 1dbb4: e2958004 adds r8, r5, #4 ; 0x4 + 1dbb8: ebf598f0 bl 0xffd83f80 + 1dbbc: 080041ba stmeqda r0, {r1, r3, r4, r5, r7, r8, lr} + 1dbc0: e3b05003 movs r5, #3 ; 0x3 + 1dbc4: e28cc032 add ip, ip, #50 ; 0x32 + 1dbc8: ebf598ec bl 0xffd83f80 + 1dbcc: 080041bc stmeqda r0, {r2, r3, r4, r5, r7, r8, lr} + 1dbd0: e2840006 add r0, r4, #6 ; 0x6 + 1dbd4: e1a01006 mov r1, r6 + 1dbd8: ebf5965b bl 0xffd8354c + 1dbdc: 080041be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, lr} + 1dbe0: ebf598e6 bl 0xffd83f80 + 1dbe4: 080041be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, lr} + 1dbe8: e2840004 add r0, r4, #4 ; 0x4 + 1dbec: e1a01006 mov r1, r6 + 1dbf0: ebf59655 bl 0xffd8354c + 1dbf4: 080041c0 stmeqda r0, {r6, r7, r8, lr} + 1dbf8: ebf598e0 bl 0xffd83f80 + 1dbfc: 080041c0 stmeqda r0, {r6, r7, r8, lr} + 1dc00: e2840002 add r0, r4, #2 ; 0x2 + 1dc04: e1a01006 mov r1, r6 + 1dc08: ebf5964f bl 0xffd8354c + 1dc0c: 080041c2 stmeqda r0, {r1, r6, r7, r8, lr} + 1dc10: ebf598da bl 0xffd83f80 + 1dc14: 080041c2 stmeqda r0, {r1, r6, r7, r8, lr} + 1dc18: e2840000 add r0, r4, #0 ; 0x0 + 1dc1c: e1a01006 mov r1, r6 + 1dc20: ebf59649 bl 0xffd8354c + 1dc24: 080041c4 stmeqda r0, {r2, r6, r7, r8, lr} + 1dc28: ebf598d4 bl 0xffd83f80 + 1dc2c: 080041c4 stmeqda r0, {r2, r6, r7, r8, lr} + 1dc30: e1a01004 mov r1, r4 + 1dc34: e2944040 adds r4, r4, #64 ; 0x40 + 1dc38: ebf598d0 bl 0xffd83f80 + 1dc3c: 080041c6 stmeqda r0, {r1, r2, r6, r7, r8, lr} + 1dc40: e1a01005 mov r1, r5 + 1dc44: e2555001 subs r5, r5, #1 ; 0x1 + 1dc48: ebf598cc bl 0xffd83f80 + 1dc4c: 080041c8 stmeqda r0, {r3, r6, r7, r8, lr} + 1dc50: e3550000 cmp r5, #0 ; 0x0 + 1dc54: ebf598c9 bl 0xffd83f80 + 1dc58: 080041ca stmeqda r0, {r1, r3, r6, r7, r8, lr} + 1dc5c: e28cc01c add ip, ip, #28 ; 0x1c + 1dc60: ba000004 blt 0x1dc78 + 1dc64: e1a00fac mov r0, ip, lsr #31 + 1dc68: e08ff100 add pc, pc, r0, lsl #2 + 1dc6c: 080041bc stmeqda r0, {r2, r3, r4, r5, r7, r8, lr} + 1dc70: ebf594b7 bl 0xffd82f54 + 1dc74: eaffffd3 b 0x1dbc8 + 1dc78: ebf598c0 bl 0xffd83f80 + 1dc7c: 080041cc stmeqda r0, {r2, r3, r6, r7, r8, lr} + 1dc80: e1a01008 mov r1, r8 + 1dc84: e2985000 adds r5, r8, #0 ; 0x0 + 1dc88: ebf598bc bl 0xffd83f80 + 1dc8c: 080041ce stmeqda r0, {r1, r2, r3, r6, r7, r8, lr} + 1dc90: e59d1420 ldr r1, [sp, #1056] + 1dc94: e1550001 cmp r5, r1 + 1dc98: ebf598b8 bl 0xffd83f80 + 1dc9c: 080041d0 stmeqda r0, {r4, r6, r7, r8, lr} + 1dca0: e28cc009 add ip, ip, #9 ; 0x9 + 1dca4: ca000004 bgt 0x1dcbc + 1dca8: e1a00fac mov r0, ip, lsr #31 + 1dcac: e08ff100 add pc, pc, r0, lsl #2 + 1dcb0: 0800419c stmeqda r0, {r2, r3, r4, r7, r8, lr} + 1dcb4: ebf594a6 bl 0xffd82f54 + 1dcb8: eaffff82 b 0x1dac8 + 1dcbc: ebf598af bl 0xffd83f80 + 1dcc0: 080041d2 stmeqda r0, {r1, r4, r6, r7, r8, lr} + 1dcc4: e59d1430 ldr r1, [sp, #1072] + 1dcc8: e1a04001 mov r4, r1 + 1dccc: ebf598ab bl 0xffd83f80 + 1dcd0: 080041d4 stmeqda r0, {r2, r4, r6, r7, r8, lr} + 1dcd4: e59d0434 ldr r0, [sp, #1076] + 1dcd8: e2800f03 add r0, r0, #12 ; 0xc + 1dcdc: ebf5970d bl 0xffd83918 + 1dce0: 080041d8 stmeqda r0, {r3, r4, r6, r7, r8, lr} + 1dce4: e58d041c str r0, [sp, #1052] + 1dce8: ebf598a4 bl 0xffd83f80 + 1dcec: 080041d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, lr} + 1dcf0: e59d041c ldr r0, [sp, #1052] + 1dcf4: e1540000 cmp r4, r0 + 1dcf8: ebf598a0 bl 0xffd83f80 + 1dcfc: 080041d8 stmeqda r0, {r3, r4, r6, r7, r8, lr} + 1dd00: e28cc00e add ip, ip, #14 ; 0xe + 1dd04: ca000004 bgt 0x1dd1c + 1dd08: e1a00fac mov r0, ip, lsr #31 + 1dd0c: e08ff100 add pc, pc, r0, lsl #2 + 1dd10: 0800417e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, lr} + 1dd14: ebf5948e bl 0xffd82f54 + 1dd18: eaffff1f b 0x1d99c + 1dd1c: ebf59897 bl 0xffd83f80 + 1dd20: 080041da stmeqda r0, {r1, r3, r4, r6, r7, r8, lr} + 1dd24: e3b03000 movs r3, #0 ; 0x0 + 1dd28: ebf59894 bl 0xffd83f80 + 1dd2c: 080041dc stmeqda r0, {r2, r3, r4, r6, r7, r8, lr} + 1dd30: e59d0434 ldr r0, [sp, #1076] + 1dd34: e2800f01 add r0, r0, #4 ; 0x4 + 1dd38: e1a01003 mov r1, r3 + 1dd3c: ebf59622 bl 0xffd835cc + 1dd40: 080041de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, lr} + 1dd44: e28cc007 add ip, ip, #7 ; 0x7 + 1dd48: ebf5988c bl 0xffd83f80 + 1dd4c: 080041de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, lr} + 1dd50: e59d0434 ldr r0, [sp, #1076] + 1dd54: e2800f00 add r0, r0, #0 ; 0x0 + 1dd58: ebf596ee bl 0xffd83918 + 1dd5c: 080041e2 stmeqda r0, {r1, r5, r6, r7, r8, lr} + 1dd60: e1a04000 mov r4, r0 + 1dd64: ebf59885 bl 0xffd83f80 + 1dd68: 080041e0 stmeqda r0, {r5, r6, r7, r8, lr} + 1dd6c: e3b05010 movs r5, #16 ; 0x10 + 1dd70: ebf59882 bl 0xffd83f80 + 1dd74: 080041e2 stmeqda r0, {r1, r5, r6, r7, r8, lr} + 1dd78: e0840005 add r0, r4, r5 + 1dd7c: ebf596ce bl 0xffd838bc + 1dd80: 080041e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, lr} + 1dd84: e1a03000 mov r3, r0 + 1dd88: ebf5987c bl 0xffd83f80 + 1dd8c: 080041e4 stmeqda r0, {r2, r5, r6, r7, r8, lr} + 1dd90: e1a01003 mov r1, r3 + 1dd94: e2533001 subs r3, r3, #1 ; 0x1 + 1dd98: ebf59878 bl 0xffd83f80 + 1dd9c: 080041e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, lr} + 1dda0: e1b03103 movs r3, r3, lsl #2 + 1dda4: ebf59875 bl 0xffd83f80 + 1dda8: 080041e8 stmeqda r0, {r3, r5, r6, r7, r8, lr} + 1ddac: e1a00003 mov r0, r3 + 1ddb0: e58d0420 str r0, [sp, #1056] + 1ddb4: ebf59871 bl 0xffd83f80 + 1ddb8: 080041ea stmeqda r0, {r1, r3, r5, r6, r7, r8, lr} + 1ddbc: e59d0434 ldr r0, [sp, #1076] + 1ddc0: e2800f01 add r0, r0, #4 ; 0x4 + 1ddc4: ebf596d3 bl 0xffd83918 + 1ddc8: 080041ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, lr} + 1ddcc: e1a06000 mov r6, r0 + 1ddd0: ebf5986a bl 0xffd83f80 + 1ddd4: 080041ec stmeqda r0, {r2, r3, r5, r6, r7, r8, lr} + 1ddd8: e1b06146 movs r6, r6, asr #2 + 1dddc: ebf59867 bl 0xffd83f80 + 1dde0: 080041ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, lr} + 1dde4: e59d0434 ldr r0, [sp, #1076] + 1dde8: e2800f0a add r0, r0, #40 ; 0x28 + 1ddec: e1a01006 mov r1, r6 + 1ddf0: ebf595f5 bl 0xffd835cc + 1ddf4: 080041f0 stmeqda r0, {r4, r5, r6, r7, r8, lr} + 1ddf8: ebf59860 bl 0xffd83f80 + 1ddfc: 080041f0 stmeqda r0, {r4, r5, r6, r7, r8, lr} + 1de00: e59d0420 ldr r0, [sp, #1056] + 1de04: e59d1424 ldr r1, [sp, #1060] + 1de08: e1500001 cmp r0, r1 + 1de0c: ebf5985b bl 0xffd83f80 + 1de10: 080041f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, lr} + 1de14: e28cc028 add ip, ip, #40 ; 0x28 + 1de18: ba000004 blt 0x1de30 + 1de1c: e1a00fac mov r0, ip, lsr #31 + 1de20: e08ff100 add pc, pc, r0, lsl #2 + 1de24: 0800425a stmeqda r0, {r1, r3, r4, r6, r9, lr} + 1de28: ebf59449 bl 0xffd82f54 + 1de2c: ea0000fa b 0x1e21c + 1de30: ebf59852 bl 0xffd83f80 + 1de34: 080041f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, lr} + 1de38: e59d0434 ldr r0, [sp, #1076] + 1de3c: e2800f02 add r0, r0, #8 ; 0x8 + 1de40: ebf596b4 bl 0xffd83918 + 1de44: 080041f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, lr} + 1de48: e1a04000 mov r4, r0 + 1de4c: ebf5984b bl 0xffd83f80 + 1de50: 080041f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, lr} + 1de54: e59d0434 ldr r0, [sp, #1076] + 1de58: e2800f03 add r0, r0, #12 ; 0xc + 1de5c: ebf596ad bl 0xffd83918 + 1de60: 080041fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, lr} + 1de64: e1a07000 mov r7, r0 + 1de68: ebf59844 bl 0xffd83f80 + 1de6c: 080041f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, lr} + 1de70: e1540007 cmp r4, r7 + 1de74: ebf59841 bl 0xffd83f80 + 1de78: 080041fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, lr} + 1de7c: e28cc010 add ip, ip, #16 ; 0x10 + 1de80: da000004 ble 0x1de98 + 1de84: e1a00fac mov r0, ip, lsr #31 + 1de88: e08ff100 add pc, pc, r0, lsl #2 + 1de8c: 08004258 stmeqda r0, {r3, r4, r6, r9, lr} + 1de90: ebf5942f bl 0xffd82f54 + 1de94: ea0000da b 0x1e204 + 1de98: ebf59838 bl 0xffd83f80 + 1de9c: 080041fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, lr} + 1dea0: e1a01004 mov r1, r4 + 1dea4: e2940000 adds r0, r4, #0 ; 0x0 + 1dea8: e58d0418 str r0, [sp, #1048] + 1deac: ebf59833 bl 0xffd83f80 + 1deb0: 080041fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, lr} + 1deb4: e3b08020 movs r8, #32 ; 0x20 + 1deb8: ebf59830 bl 0xffd83f80 + 1debc: 08004200 stmeqda r0, {r9, lr} + 1dec0: e59d1418 ldr r1, [sp, #1048] + 1dec4: e59d1418 ldr r1, [sp, #1048] + 1dec8: e0110008 ands r0, r1, r8 + 1decc: e58d0418 str r0, [sp, #1048] + 1ded0: ebf5982a bl 0xffd83f80 + 1ded4: 08004202 stmeqda r0, {r1, r9, lr} + 1ded8: e59d0434 ldr r0, [sp, #1076] + 1dedc: e2800f08 add r0, r0, #32 ; 0x20 + 1dee0: ebf5968c bl 0xffd83918 + 1dee4: 08004206 stmeqda r0, {r1, r2, r9, lr} + 1dee8: e58d041c str r0, [sp, #1052] + 1deec: ebf59823 bl 0xffd83f80 + 1def0: 08004204 stmeqda r0, {r2, r9, lr} + 1def4: e59d0418 ldr r0, [sp, #1048] + 1def8: e59de41c ldr lr, [sp, #1052] + 1defc: e1b00e50 movs r0, r0, asr lr + 1df00: e58d0418 str r0, [sp, #1048] + 1df04: ebf5981d bl 0xffd83f80 + 1df08: 08004206 stmeqda r0, {r1, r2, r9, lr} + 1df0c: e1a01004 mov r1, r4 + 1df10: e2947000 adds r7, r4, #0 ; 0x0 + 1df14: ebf59819 bl 0xffd83f80 + 1df18: 08004208 stmeqda r0, {r3, r9, lr} + 1df1c: e3b0301c movs r3, #28 ; 0x1c + 1df20: ebf59816 bl 0xffd83f80 + 1df24: 0800420a stmeqda r0, {r1, r3, r9, lr} + 1df28: e1a01007 mov r1, r7 + 1df2c: e0177003 ands r7, r7, r3 + 1df30: ebf59812 bl 0xffd83f80 + 1df34: 0800420c stmeqda r0, {r2, r3, r9, lr} + 1df38: e59d1420 ldr r1, [sp, #1056] + 1df3c: e1a05001 mov r5, r1 + 1df40: ebf5980e bl 0xffd83f80 + 1df44: 0800420e stmeqda r0, {r1, r2, r3, r9, lr} + 1df48: e1a01004 mov r1, r4 + 1df4c: e2944004 adds r4, r4, #4 ; 0x4 + 1df50: ebf5980a bl 0xffd83f80 + 1df54: 08004210 stmeqda r0, {r4, r9, lr} + 1df58: e1a00004 mov r0, r4 + 1df5c: e58d0430 str r0, [sp, #1072] + 1df60: ebf59806 bl 0xffd83f80 + 1df64: 08004212 stmeqda r0, {r1, r4, r9, lr} + 1df68: e59d1424 ldr r1, [sp, #1060] + 1df6c: e1550001 cmp r5, r1 + 1df70: ebf59802 bl 0xffd83f80 + 1df74: 08004214 stmeqda r0, {r2, r4, r9, lr} + 1df78: e28cc029 add ip, ip, #41 ; 0x29 + 1df7c: da000004 ble 0x1df94 + 1df80: e1a00fac mov r0, ip, lsr #31 + 1df84: e08ff100 add pc, pc, r0, lsl #2 + 1df88: 08004250 stmeqda r0, {r4, r6, r9, lr} + 1df8c: ebf593f0 bl 0xffd82f54 + 1df90: ea000084 b 0x1e1a8 + 1df94: ebf597f9 bl 0xffd83f80 + 1df98: 08004216 stmeqda r0, {r1, r2, r4, r9, lr} + 1df9c: e3b06000 movs r6, #0 ; 0x0 + 1dfa0: ebf597f6 bl 0xffd83f80 + 1dfa4: 08004218 stmeqda r0, {r3, r4, r9, lr} + 1dfa8: e1b00307 movs r0, r7, lsl #6 + 1dfac: e58d041c str r0, [sp, #1052] + 1dfb0: e28cc006 add ip, ip, #6 ; 0x6 + 1dfb4: ebf597f1 bl 0xffd83f80 + 1dfb8: 0800421a stmeqda r0, {r1, r3, r4, r9, lr} + 1dfbc: e1a01005 mov r1, r5 + 1dfc0: e2954000 adds r4, r5, #0 ; 0x0 + 1dfc4: ebf597ed bl 0xffd83f80 + 1dfc8: 0800421c stmeqda r0, {r2, r3, r4, r9, lr} + 1dfcc: e3b07020 movs r7, #32 ; 0x20 + 1dfd0: ebf597ea bl 0xffd83f80 + 1dfd4: 0800421e stmeqda r0, {r1, r2, r3, r4, r9, lr} + 1dfd8: e1a01004 mov r1, r4 + 1dfdc: e0144007 ands r4, r4, r7 + 1dfe0: ebf597e6 bl 0xffd83f80 + 1dfe4: 08004220 stmeqda r0, {r5, r9, lr} + 1dfe8: e59d0434 ldr r0, [sp, #1076] + 1dfec: e2800f07 add r0, r0, #28 ; 0x1c + 1dff0: ebf59648 bl 0xffd83918 + 1dff4: 08004224 stmeqda r0, {r2, r5, r9, lr} + 1dff8: e1a08000 mov r8, r0 + 1dffc: ebf597df bl 0xffd83f80 + 1e000: 08004222 stmeqda r0, {r1, r5, r9, lr} + 1e004: e1b04854 movs r4, r4, asr r8 + 1e008: ebf597dc bl 0xffd83f80 + 1e00c: 08004224 stmeqda r0, {r2, r5, r9, lr} + 1e010: e59d1418 ldr r1, [sp, #1048] + 1e014: e59d1418 ldr r1, [sp, #1048] + 1e018: e0914004 adds r4, r1, r4 + 1e01c: ebf597d7 bl 0xffd83f80 + 1e020: 08004226 stmeqda r0, {r1, r2, r5, r9, lr} + 1e024: e1b04584 movs r4, r4, lsl #11 + 1e028: ebf597d4 bl 0xffd83f80 + 1e02c: 08004228 stmeqda r0, {r3, r5, r9, lr} + 1e030: e59d1428 ldr r1, [sp, #1064] + 1e034: e0844001 add r4, r4, r1 + 1e038: ebf597d0 bl 0xffd83f80 + 1e03c: 0800422a stmeqda r0, {r1, r3, r5, r9, lr} + 1e040: e1a01004 mov r1, r4 + 1e044: e59d041c ldr r0, [sp, #1052] + 1e048: e0944000 adds r4, r4, r0 + 1e04c: ebf597cb bl 0xffd83f80 + 1e050: 0800422c stmeqda r0, {r2, r3, r5, r9, lr} + 1e054: e1a01005 mov r1, r5 + 1e058: e2953000 adds r3, r5, #0 ; 0x0 + 1e05c: ebf597c7 bl 0xffd83f80 + 1e060: 0800422e stmeqda r0, {r1, r2, r3, r5, r9, lr} + 1e064: e3b0701c movs r7, #28 ; 0x1c + 1e068: ebf597c4 bl 0xffd83f80 + 1e06c: 08004230 stmeqda r0, {r4, r5, r9, lr} + 1e070: e1a01003 mov r1, r3 + 1e074: e0133007 ands r3, r3, r7 + 1e078: ebf597c0 bl 0xffd83f80 + 1e07c: 08004232 stmeqda r0, {r1, r4, r5, r9, lr} + 1e080: e1b03083 movs r3, r3, lsl #1 + 1e084: ebf597bd bl 0xffd83f80 + 1e088: 08004234 stmeqda r0, {r2, r4, r5, r9, lr} + 1e08c: e1a01004 mov r1, r4 + 1e090: e0944003 adds r4, r4, r3 + 1e094: ebf597b9 bl 0xffd83f80 + 1e098: 08004236 stmeqda r0, {r1, r2, r4, r5, r9, lr} + 1e09c: e1a01005 mov r1, r5 + 1e0a0: e2958004 adds r8, r5, #4 ; 0x4 + 1e0a4: ebf597b5 bl 0xffd83f80 + 1e0a8: 08004238 stmeqda r0, {r3, r4, r5, r9, lr} + 1e0ac: e3b05003 movs r5, #3 ; 0x3 + 1e0b0: e28cc032 add ip, ip, #50 ; 0x32 + 1e0b4: ebf597b1 bl 0xffd83f80 + 1e0b8: 0800423a stmeqda r0, {r1, r3, r4, r5, r9, lr} + 1e0bc: e2840006 add r0, r4, #6 ; 0x6 + 1e0c0: e1a01006 mov r1, r6 + 1e0c4: ebf59520 bl 0xffd8354c + 1e0c8: 0800423c stmeqda r0, {r2, r3, r4, r5, r9, lr} + 1e0cc: ebf597ab bl 0xffd83f80 + 1e0d0: 0800423c stmeqda r0, {r2, r3, r4, r5, r9, lr} + 1e0d4: e2840004 add r0, r4, #4 ; 0x4 + 1e0d8: e1a01006 mov r1, r6 + 1e0dc: ebf5951a bl 0xffd8354c + 1e0e0: 0800423e stmeqda r0, {r1, r2, r3, r4, r5, r9, lr} + 1e0e4: ebf597a5 bl 0xffd83f80 + 1e0e8: 0800423e stmeqda r0, {r1, r2, r3, r4, r5, r9, lr} + 1e0ec: e2840002 add r0, r4, #2 ; 0x2 + 1e0f0: e1a01006 mov r1, r6 + 1e0f4: ebf59514 bl 0xffd8354c + 1e0f8: 08004240 stmeqda r0, {r6, r9, lr} + 1e0fc: ebf5979f bl 0xffd83f80 + 1e100: 08004240 stmeqda r0, {r6, r9, lr} + 1e104: e2840000 add r0, r4, #0 ; 0x0 + 1e108: e1a01006 mov r1, r6 + 1e10c: ebf5950e bl 0xffd8354c + 1e110: 08004242 stmeqda r0, {r1, r6, r9, lr} + 1e114: ebf59799 bl 0xffd83f80 + 1e118: 08004242 stmeqda r0, {r1, r6, r9, lr} + 1e11c: e1a01004 mov r1, r4 + 1e120: e2944040 adds r4, r4, #64 ; 0x40 + 1e124: ebf59795 bl 0xffd83f80 + 1e128: 08004244 stmeqda r0, {r2, r6, r9, lr} + 1e12c: e1a01005 mov r1, r5 + 1e130: e2555001 subs r5, r5, #1 ; 0x1 + 1e134: ebf59791 bl 0xffd83f80 + 1e138: 08004246 stmeqda r0, {r1, r2, r6, r9, lr} + 1e13c: e3550000 cmp r5, #0 ; 0x0 + 1e140: ebf5978e bl 0xffd83f80 + 1e144: 08004248 stmeqda r0, {r3, r6, r9, lr} + 1e148: e28cc01c add ip, ip, #28 ; 0x1c + 1e14c: ba000004 blt 0x1e164 + 1e150: e1a00fac mov r0, ip, lsr #31 + 1e154: e08ff100 add pc, pc, r0, lsl #2 + 1e158: 0800423a stmeqda r0, {r1, r3, r4, r5, r9, lr} + 1e15c: ebf5937c bl 0xffd82f54 + 1e160: eaffffd3 b 0x1e0b4 + 1e164: ebf59785 bl 0xffd83f80 + 1e168: 0800424a stmeqda r0, {r1, r3, r6, r9, lr} + 1e16c: e1a01008 mov r1, r8 + 1e170: e2985000 adds r5, r8, #0 ; 0x0 + 1e174: ebf59781 bl 0xffd83f80 + 1e178: 0800424c stmeqda r0, {r2, r3, r6, r9, lr} + 1e17c: e59d1424 ldr r1, [sp, #1060] + 1e180: e1550001 cmp r5, r1 + 1e184: ebf5977d bl 0xffd83f80 + 1e188: 0800424e stmeqda r0, {r1, r2, r3, r6, r9, lr} + 1e18c: e28cc009 add ip, ip, #9 ; 0x9 + 1e190: ca000004 bgt 0x1e1a8 + 1e194: e1a00fac mov r0, ip, lsr #31 + 1e198: e08ff100 add pc, pc, r0, lsl #2 + 1e19c: 0800421a stmeqda r0, {r1, r3, r4, r9, lr} + 1e1a0: ebf5936b bl 0xffd82f54 + 1e1a4: eaffff82 b 0x1dfb4 + 1e1a8: ebf59774 bl 0xffd83f80 + 1e1ac: 08004250 stmeqda r0, {r4, r6, r9, lr} + 1e1b0: e59d1430 ldr r1, [sp, #1072] + 1e1b4: e1a04001 mov r4, r1 + 1e1b8: ebf59770 bl 0xffd83f80 + 1e1bc: 08004252 stmeqda r0, {r1, r4, r6, r9, lr} + 1e1c0: e59d0434 ldr r0, [sp, #1076] + 1e1c4: e2800f03 add r0, r0, #12 ; 0xc + 1e1c8: ebf595d2 bl 0xffd83918 + 1e1cc: 08004256 stmeqda r0, {r1, r2, r4, r6, r9, lr} + 1e1d0: e1a08000 mov r8, r0 + 1e1d4: ebf59769 bl 0xffd83f80 + 1e1d8: 08004254 stmeqda r0, {r2, r4, r6, r9, lr} + 1e1dc: e1540008 cmp r4, r8 + 1e1e0: ebf59766 bl 0xffd83f80 + 1e1e4: 08004256 stmeqda r0, {r1, r2, r4, r6, r9, lr} + 1e1e8: e28cc00e add ip, ip, #14 ; 0xe + 1e1ec: ca000004 bgt 0x1e204 + 1e1f0: e1a00fac mov r0, ip, lsr #31 + 1e1f4: e08ff100 add pc, pc, r0, lsl #2 + 1e1f8: 080041fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, lr} + 1e1fc: ebf59354 bl 0xffd82f54 + 1e200: eaffff24 b 0x1de98 + 1e204: ebf5975d bl 0xffd83f80 + 1e208: 08004258 stmeqda r0, {r3, r4, r6, r9, lr} + 1e20c: e59d1420 ldr r1, [sp, #1056] + 1e210: e1a00001 mov r0, r1 + 1e214: e58d0424 str r0, [sp, #1060] + 1e218: e28cc003 add ip, ip, #3 ; 0x3 + 1e21c: ebf59757 bl 0xffd83f80 + 1e220: 0800425a stmeqda r0, {r1, r3, r4, r6, r9, lr} + 1e224: e59d0434 ldr r0, [sp, #1076] + 1e228: e2800f00 add r0, r0, #0 ; 0x0 + 1e22c: ebf595b9 bl 0xffd83918 + 1e230: 0800425e stmeqda r0, {r1, r2, r3, r4, r6, r9, lr} + 1e234: e58d041c str r0, [sp, #1052] + 1e238: ebf59750 bl 0xffd83f80 + 1e23c: 0800425c stmeqda r0, {r2, r3, r4, r6, r9, lr} + 1e240: e3b04010 movs r4, #16 ; 0x10 + 1e244: ebf5974d bl 0xffd83f80 + 1e248: 0800425e stmeqda r0, {r1, r2, r3, r4, r6, r9, lr} + 1e24c: e59d041c ldr r0, [sp, #1052] + 1e250: e0800004 add r0, r0, r4 + 1e254: ebf59598 bl 0xffd838bc + 1e258: 08004262 stmeqda r0, {r1, r5, r6, r9, lr} + 1e25c: e1a03000 mov r3, r0 + 1e260: ebf59746 bl 0xffd83f80 + 1e264: 08004260 stmeqda r0, {r5, r6, r9, lr} + 1e268: e59d0434 ldr r0, [sp, #1076] + 1e26c: e2800f0b add r0, r0, #44 ; 0x2c + 1e270: ebf595a8 bl 0xffd83918 + 1e274: 08004264 stmeqda r0, {r2, r5, r6, r9, lr} + 1e278: e1a05000 mov r5, r0 + 1e27c: ebf5973f bl 0xffd83f80 + 1e280: 08004262 stmeqda r0, {r1, r5, r6, r9, lr} + 1e284: e1a01003 mov r1, r3 + 1e288: e0130593 muls r3, r3, r5 + 1e28c: ebf5973b bl 0xffd83f80 + 1e290: 08004264 stmeqda r0, {r2, r5, r6, r9, lr} + 1e294: e1b03083 movs r3, r3, lsl #1 + 1e298: ebf59738 bl 0xffd83f80 + 1e29c: 08004266 stmeqda r0, {r1, r2, r5, r6, r9, lr} + 1e2a0: e59d0434 ldr r0, [sp, #1076] + 1e2a4: e2800f09 add r0, r0, #36 ; 0x24 + 1e2a8: ebf5959a bl 0xffd83918 + 1e2ac: 0800426a stmeqda r0, {r1, r3, r5, r6, r9, lr} + 1e2b0: e1a06000 mov r6, r0 + 1e2b4: ebf59731 bl 0xffd83f80 + 1e2b8: 08004268 stmeqda r0, {r3, r5, r6, r9, lr} + 1e2bc: e1a01006 mov r1, r6 + 1e2c0: e0963003 adds r3, r6, r3 + 1e2c4: ebf5972d bl 0xffd83f80 + 1e2c8: 0800426a stmeqda r0, {r1, r3, r5, r6, r9, lr} + 1e2cc: e59d0434 ldr r0, [sp, #1076] + 1e2d0: e2800f0a add r0, r0, #40 ; 0x28 + 1e2d4: ebf5958f bl 0xffd83918 + 1e2d8: 0800426e stmeqda r0, {r1, r2, r3, r5, r6, r9, lr} + 1e2dc: e1a07000 mov r7, r0 + 1e2e0: ebf59726 bl 0xffd83f80 + 1e2e4: 0800426c stmeqda r0, {r2, r3, r5, r6, r9, lr} + 1e2e8: e1b04087 movs r4, r7, lsl #1 + 1e2ec: ebf59723 bl 0xffd83f80 + 1e2f0: 0800426e stmeqda r0, {r1, r2, r3, r5, r6, r9, lr} + 1e2f4: e1a01003 mov r1, r3 + 1e2f8: e0933004 adds r3, r3, r4 + 1e2fc: ebf5971f bl 0xffd83f80 + 1e300: 08004270 stmeqda r0, {r4, r5, r6, r9, lr} + 1e304: e1a00003 mov r0, r3 + 1e308: e58d0420 str r0, [sp, #1056] + 1e30c: ebf5971b bl 0xffd83f80 + 1e310: 08004272 stmeqda r0, {r1, r4, r5, r6, r9, lr} + 1e314: e59d0434 ldr r0, [sp, #1076] + 1e318: e2800f02 add r0, r0, #8 ; 0x8 + 1e31c: ebf5957d bl 0xffd83918 + 1e320: 08004276 stmeqda r0, {r1, r2, r4, r5, r6, r9, lr} + 1e324: e1a04000 mov r4, r0 + 1e328: ebf59714 bl 0xffd83f80 + 1e32c: 08004274 stmeqda r0, {r2, r4, r5, r6, r9, lr} + 1e330: e28cc036 add ip, ip, #54 ; 0x36 + 1e334: e1a00fac mov r0, ip, lsr #31 + 1e338: e08ff100 add pc, pc, r0, lsl #2 + 1e33c: 080042f0 stmeqda r0, {r4, r5, r6, r7, r9, lr} + 1e340: ebf59303 bl 0xffd82f54 + 1e344: ea00006e b 0x1e504 + 1e348: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1e34c: 00000000 andeq r0, r0, r0 + 1e350: ebf5970a bl 0xffd83f80 + 1e354: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1e358: e59d0434 ldr r0, [sp, #1076] + 1e35c: e2800f00 add r0, r0, #0 ; 0x0 + 1e360: ebf5956c bl 0xffd83918 + 1e364: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1e368: e58d041c str r0, [sp, #1052] + 1e36c: ebf59703 bl 0xffd83f80 + 1e370: 080042f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, lr} + 1e374: e59d041c ldr r0, [sp, #1052] + 1e378: e2800000 add r0, r0, #0 ; 0x0 + 1e37c: ebf59539 bl 0xffd83868 + 1e380: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1e384: e1a04000 mov r4, r0 + 1e388: ebf596fc bl 0xffd83f80 + 1e38c: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1e390: e3b05080 movs r5, #128 ; 0x80 + 1e394: ebf596f9 bl 0xffd83f80 + 1e398: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1e39c: e1b05385 movs r5, r5, lsl #7 + 1e3a0: ebf596f6 bl 0xffd83f80 + 1e3a4: 080042fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, lr} + 1e3a8: e1a01005 mov r1, r5 + 1e3ac: e2953000 adds r3, r5, #0 ; 0x0 + 1e3b0: ebf596f2 bl 0xffd83f80 + 1e3b4: 08004300 stmeqda r0, {r8, r9, lr} + 1e3b8: e1a01003 mov r1, r3 + 1e3bc: e1933004 orrs r3, r3, r4 + 1e3c0: ebf596ee bl 0xffd83f80 + 1e3c4: 08004302 stmeqda r0, {r1, r8, r9, lr} + 1e3c8: e59d041c ldr r0, [sp, #1052] + 1e3cc: e2800000 add r0, r0, #0 ; 0x0 + 1e3d0: e1a01003 mov r1, r3 + 1e3d4: ebf5945c bl 0xffd8354c + 1e3d8: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1e3dc: ebf596e7 bl 0xffd83f80 + 1e3e0: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1e3e4: e59d0434 ldr r0, [sp, #1076] + 1e3e8: e2800f0c add r0, r0, #48 ; 0x30 + 1e3ec: e58d0434 str r0, [sp, #1076] + 1e3f0: ebf596e2 bl 0xffd83f80 + 1e3f4: 08004306 stmeqda r0, {r1, r2, r8, r9, lr} + 1e3f8: e59d9434 ldr r9, [sp, #1076] + 1e3fc: e3c99003 bic r9, r9, #3 ; 0x3 + 1e400: e289000c add r0, r9, #12 ; 0xc + 1e404: e58d0434 str r0, [sp, #1076] + 1e408: e2890000 add r0, r9, #0 ; 0x0 + 1e40c: ebf59541 bl 0xffd83918 + 1e410: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e414: e1a06000 mov r6, r0 + 1e418: e2890004 add r0, r9, #4 ; 0x4 + 1e41c: ebf5953d bl 0xffd83918 + 1e420: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e424: e1a07000 mov r7, r0 + 1e428: e2890008 add r0, r9, #8 ; 0x8 + 1e42c: ebf59539 bl 0xffd83918 + 1e430: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e434: e1a08000 mov r8, r0 + 1e438: ebf596d0 bl 0xffd83f80 + 1e43c: 08004308 stmeqda r0, {r3, r8, r9, lr} + 1e440: e1a00006 mov r0, r6 + 1e444: e58d0420 str r0, [sp, #1056] + 1e448: ebf596cc bl 0xffd83f80 + 1e44c: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e450: e1a00007 mov r0, r7 + 1e454: e58d0424 str r0, [sp, #1060] + 1e458: ebf596c8 bl 0xffd83f80 + 1e45c: 0800430c stmeqda r0, {r2, r3, r8, r9, lr} + 1e460: e1a00008 mov r0, r8 + 1e464: e58d0428 str r0, [sp, #1064] + 1e468: ebf596c4 bl 0xffd83f80 + 1e46c: 0800430e stmeqda r0, {r1, r2, r3, r8, r9, lr} + 1e470: e59d9434 ldr r9, [sp, #1076] + 1e474: e3c99003 bic r9, r9, #3 ; 0x3 + 1e478: e2890010 add r0, r9, #16 ; 0x10 + 1e47c: e58d0434 str r0, [sp, #1076] + 1e480: e2890000 add r0, r9, #0 ; 0x0 + 1e484: ebf59523 bl 0xffd83918 + 1e488: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e48c: e1a07000 mov r7, r0 + 1e490: e2890004 add r0, r9, #4 ; 0x4 + 1e494: ebf5951f bl 0xffd83918 + 1e498: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e49c: e1a08000 mov r8, r0 + 1e4a0: e2890008 add r0, r9, #8 ; 0x8 + 1e4a4: ebf5951b bl 0xffd83918 + 1e4a8: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e4ac: e58d0418 str r0, [sp, #1048] + 1e4b0: e289000c add r0, r9, #12 ; 0xc + 1e4b4: ebf59517 bl 0xffd83918 + 1e4b8: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e4bc: e58d041c str r0, [sp, #1052] + 1e4c0: ebf596ae bl 0xffd83f80 + 1e4c4: 08004310 stmeqda r0, {r4, r8, r9, lr} + 1e4c8: e59d9434 ldr r9, [sp, #1076] + 1e4cc: e3c99003 bic r9, r9, #3 ; 0x3 + 1e4d0: e2890004 add r0, r9, #4 ; 0x4 + 1e4d4: e58d0434 str r0, [sp, #1076] + 1e4d8: e2890000 add r0, r9, #0 ; 0x0 + 1e4dc: ebf5950d bl 0xffd83918 + 1e4e0: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 1e4e4: e1a03000 mov r3, r0 + 1e4e8: ebf596a4 bl 0xffd83f80 + 1e4ec: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e4f0: e1a00003 mov r0, r3 + 1e4f4: e28cc03a add ip, ip, #58 ; 0x3a + 1e4f8: eaf592f4 b 0xffd830d0 + 1e4fc: 080042f0 stmeqda r0, {r4, r5, r6, r7, r9, lr} + 1e500: 00000000 andeq r0, r0, r0 + 1e504: ebf5969d bl 0xffd83f80 + 1e508: 080042f0 stmeqda r0, {r4, r5, r6, r7, r9, lr} + 1e50c: e59d0434 ldr r0, [sp, #1076] + 1e510: e2800f03 add r0, r0, #12 ; 0xc + 1e514: ebf594ff bl 0xffd83918 + 1e518: 080042f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, lr} + 1e51c: e1a08000 mov r8, r0 + 1e520: ebf59696 bl 0xffd83f80 + 1e524: 080042f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, lr} + 1e528: e1540008 cmp r4, r8 + 1e52c: ebf59693 bl 0xffd83f80 + 1e530: 080042f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, lr} + 1e534: e28cc00b add ip, ip, #11 ; 0xb + 1e538: ca000004 bgt 0x1e550 + 1e53c: e1a00fac mov r0, ip, lsr #31 + 1e540: e08ff100 add pc, pc, r0, lsl #2 + 1e544: 08004276 stmeqda r0, {r1, r2, r4, r5, r6, r9, lr} + 1e548: ebf59281 bl 0xffd82f54 + 1e54c: ea00006c b 0x1e704 + 1e550: ebf5968a bl 0xffd83f80 + 1e554: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1e558: e59d0434 ldr r0, [sp, #1076] + 1e55c: e2800f00 add r0, r0, #0 ; 0x0 + 1e560: ebf594ec bl 0xffd83918 + 1e564: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1e568: e58d041c str r0, [sp, #1052] + 1e56c: ebf59683 bl 0xffd83f80 + 1e570: 080042f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, lr} + 1e574: e59d041c ldr r0, [sp, #1052] + 1e578: e2800000 add r0, r0, #0 ; 0x0 + 1e57c: ebf594b9 bl 0xffd83868 + 1e580: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1e584: e1a04000 mov r4, r0 + 1e588: ebf5967c bl 0xffd83f80 + 1e58c: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1e590: e3b05080 movs r5, #128 ; 0x80 + 1e594: ebf59679 bl 0xffd83f80 + 1e598: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1e59c: e1b05385 movs r5, r5, lsl #7 + 1e5a0: ebf59676 bl 0xffd83f80 + 1e5a4: 080042fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, lr} + 1e5a8: e1a01005 mov r1, r5 + 1e5ac: e2953000 adds r3, r5, #0 ; 0x0 + 1e5b0: ebf59672 bl 0xffd83f80 + 1e5b4: 08004300 stmeqda r0, {r8, r9, lr} + 1e5b8: e1a01003 mov r1, r3 + 1e5bc: e1933004 orrs r3, r3, r4 + 1e5c0: ebf5966e bl 0xffd83f80 + 1e5c4: 08004302 stmeqda r0, {r1, r8, r9, lr} + 1e5c8: e59d041c ldr r0, [sp, #1052] + 1e5cc: e2800000 add r0, r0, #0 ; 0x0 + 1e5d0: e1a01003 mov r1, r3 + 1e5d4: ebf593dc bl 0xffd8354c + 1e5d8: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1e5dc: ebf59667 bl 0xffd83f80 + 1e5e0: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1e5e4: e59d0434 ldr r0, [sp, #1076] + 1e5e8: e2800f0c add r0, r0, #48 ; 0x30 + 1e5ec: e58d0434 str r0, [sp, #1076] + 1e5f0: ebf59662 bl 0xffd83f80 + 1e5f4: 08004306 stmeqda r0, {r1, r2, r8, r9, lr} + 1e5f8: e59d9434 ldr r9, [sp, #1076] + 1e5fc: e3c99003 bic r9, r9, #3 ; 0x3 + 1e600: e289000c add r0, r9, #12 ; 0xc + 1e604: e58d0434 str r0, [sp, #1076] + 1e608: e2890000 add r0, r9, #0 ; 0x0 + 1e60c: ebf594c1 bl 0xffd83918 + 1e610: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e614: e1a06000 mov r6, r0 + 1e618: e2890004 add r0, r9, #4 ; 0x4 + 1e61c: ebf594bd bl 0xffd83918 + 1e620: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e624: e1a07000 mov r7, r0 + 1e628: e2890008 add r0, r9, #8 ; 0x8 + 1e62c: ebf594b9 bl 0xffd83918 + 1e630: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e634: e1a08000 mov r8, r0 + 1e638: ebf59650 bl 0xffd83f80 + 1e63c: 08004308 stmeqda r0, {r3, r8, r9, lr} + 1e640: e1a00006 mov r0, r6 + 1e644: e58d0420 str r0, [sp, #1056] + 1e648: ebf5964c bl 0xffd83f80 + 1e64c: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1e650: e1a00007 mov r0, r7 + 1e654: e58d0424 str r0, [sp, #1060] + 1e658: ebf59648 bl 0xffd83f80 + 1e65c: 0800430c stmeqda r0, {r2, r3, r8, r9, lr} + 1e660: e1a00008 mov r0, r8 + 1e664: e58d0428 str r0, [sp, #1064] + 1e668: ebf59644 bl 0xffd83f80 + 1e66c: 0800430e stmeqda r0, {r1, r2, r3, r8, r9, lr} + 1e670: e59d9434 ldr r9, [sp, #1076] + 1e674: e3c99003 bic r9, r9, #3 ; 0x3 + 1e678: e2890010 add r0, r9, #16 ; 0x10 + 1e67c: e58d0434 str r0, [sp, #1076] + 1e680: e2890000 add r0, r9, #0 ; 0x0 + 1e684: ebf594a3 bl 0xffd83918 + 1e688: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e68c: e1a07000 mov r7, r0 + 1e690: e2890004 add r0, r9, #4 ; 0x4 + 1e694: ebf5949f bl 0xffd83918 + 1e698: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e69c: e1a08000 mov r8, r0 + 1e6a0: e2890008 add r0, r9, #8 ; 0x8 + 1e6a4: ebf5949b bl 0xffd83918 + 1e6a8: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e6ac: e58d0418 str r0, [sp, #1048] + 1e6b0: e289000c add r0, r9, #12 ; 0xc + 1e6b4: ebf59497 bl 0xffd83918 + 1e6b8: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e6bc: e58d041c str r0, [sp, #1052] + 1e6c0: ebf5962e bl 0xffd83f80 + 1e6c4: 08004310 stmeqda r0, {r4, r8, r9, lr} + 1e6c8: e59d9434 ldr r9, [sp, #1076] + 1e6cc: e3c99003 bic r9, r9, #3 ; 0x3 + 1e6d0: e2890004 add r0, r9, #4 ; 0x4 + 1e6d4: e58d0434 str r0, [sp, #1076] + 1e6d8: e2890000 add r0, r9, #0 ; 0x0 + 1e6dc: ebf5948d bl 0xffd83918 + 1e6e0: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 1e6e4: e1a03000 mov r3, r0 + 1e6e8: ebf59624 bl 0xffd83f80 + 1e6ec: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1e6f0: e1a00003 mov r0, r3 + 1e6f4: e28cc03a add ip, ip, #58 ; 0x3a + 1e6f8: eaf59274 b 0xffd830d0 + 1e6fc: 08004276 stmeqda r0, {r1, r2, r4, r5, r6, r9, lr} + 1e700: 00000000 andeq r0, r0, r0 + 1e704: ebf5961d bl 0xffd83f80 + 1e708: 08004276 stmeqda r0, {r1, r2, r4, r5, r6, r9, lr} + 1e70c: e1a01004 mov r1, r4 + 1e710: e2940000 adds r0, r4, #0 ; 0x0 + 1e714: e58d0418 str r0, [sp, #1048] + 1e718: ebf59618 bl 0xffd83f80 + 1e71c: 08004278 stmeqda r0, {r3, r4, r5, r6, r9, lr} + 1e720: e3b00020 movs r0, #32 ; 0x20 + 1e724: e58d041c str r0, [sp, #1052] + 1e728: ebf59614 bl 0xffd83f80 + 1e72c: 0800427a stmeqda r0, {r1, r3, r4, r5, r6, r9, lr} + 1e730: e59d1418 ldr r1, [sp, #1048] + 1e734: e59d1418 ldr r1, [sp, #1048] + 1e738: e59d041c ldr r0, [sp, #1052] + 1e73c: e0110000 ands r0, r1, r0 + 1e740: e58d0418 str r0, [sp, #1048] + 1e744: ebf5960d bl 0xffd83f80 + 1e748: 0800427c stmeqda r0, {r2, r3, r4, r5, r6, r9, lr} + 1e74c: e59d0434 ldr r0, [sp, #1076] + 1e750: e2800f08 add r0, r0, #32 ; 0x20 + 1e754: ebf5946f bl 0xffd83918 + 1e758: 08004280 stmeqda r0, {r7, r9, lr} + 1e75c: e1a03000 mov r3, r0 + 1e760: ebf59606 bl 0xffd83f80 + 1e764: 0800427e stmeqda r0, {r1, r2, r3, r4, r5, r6, r9, lr} + 1e768: e59d0418 ldr r0, [sp, #1048] + 1e76c: e1b00350 movs r0, r0, asr r3 + 1e770: e58d0418 str r0, [sp, #1048] + 1e774: ebf59601 bl 0xffd83f80 + 1e778: 08004280 stmeqda r0, {r7, r9, lr} + 1e77c: e1a01004 mov r1, r4 + 1e780: e2947000 adds r7, r4, #0 ; 0x0 + 1e784: ebf595fd bl 0xffd83f80 + 1e788: 08004282 stmeqda r0, {r1, r7, r9, lr} + 1e78c: e3b0501c movs r5, #28 ; 0x1c + 1e790: ebf595fa bl 0xffd83f80 + 1e794: 08004284 stmeqda r0, {r2, r7, r9, lr} + 1e798: e1a01007 mov r1, r7 + 1e79c: e0177005 ands r7, r7, r5 + 1e7a0: ebf595f6 bl 0xffd83f80 + 1e7a4: 08004286 stmeqda r0, {r1, r2, r7, r9, lr} + 1e7a8: e59d0434 ldr r0, [sp, #1076] + 1e7ac: e2800f01 add r0, r0, #4 ; 0x4 + 1e7b0: ebf59458 bl 0xffd83918 + 1e7b4: 0800428a stmeqda r0, {r1, r3, r7, r9, lr} + 1e7b8: e1a05000 mov r5, r0 + 1e7bc: ebf595ef bl 0xffd83f80 + 1e7c0: 08004288 stmeqda r0, {r3, r7, r9, lr} + 1e7c4: e3b06000 movs r6, #0 ; 0x0 + 1e7c8: ebf595ec bl 0xffd83f80 + 1e7cc: 0800428a stmeqda r0, {r1, r3, r7, r9, lr} + 1e7d0: e1a01004 mov r1, r4 + 1e7d4: e2944004 adds r4, r4, #4 ; 0x4 + 1e7d8: ebf595e8 bl 0xffd83f80 + 1e7dc: 0800428c stmeqda r0, {r2, r3, r7, r9, lr} + 1e7e0: e1a00004 mov r0, r4 + 1e7e4: e58d0430 str r0, [sp, #1072] + 1e7e8: ebf595e4 bl 0xffd83f80 + 1e7ec: 0800428e stmeqda r0, {r1, r2, r3, r7, r9, lr} + 1e7f0: e59d1424 ldr r1, [sp, #1060] + 1e7f4: e1550001 cmp r5, r1 + 1e7f8: ebf595e0 bl 0xffd83f80 + 1e7fc: 08004290 stmeqda r0, {r4, r7, r9, lr} + 1e800: e28cc02e add ip, ip, #46 ; 0x2e + 1e804: da000004 ble 0x1e81c + 1e808: e1a00fac mov r0, ip, lsr #31 + 1e80c: e08ff100 add pc, pc, r0, lsl #2 + 1e810: 080042e4 stmeqda r0, {r2, r5, r6, r7, r9, lr} + 1e814: ebf591ce bl 0xffd82f54 + 1e818: ea0000c0 b 0x1eb20 + 1e81c: ebf595d7 bl 0xffd83f80 + 1e820: 08004292 stmeqda r0, {r1, r4, r7, r9, lr} + 1e824: e1a01005 mov r1, r5 + 1e828: e2954000 adds r4, r5, #0 ; 0x0 + 1e82c: ebf595d3 bl 0xffd83f80 + 1e830: 08004294 stmeqda r0, {r2, r4, r7, r9, lr} + 1e834: e3b08020 movs r8, #32 ; 0x20 + 1e838: ebf595d0 bl 0xffd83f80 + 1e83c: 08004296 stmeqda r0, {r1, r2, r4, r7, r9, lr} + 1e840: e1a01004 mov r1, r4 + 1e844: e0144008 ands r4, r4, r8 + 1e848: ebf595cc bl 0xffd83f80 + 1e84c: 08004298 stmeqda r0, {r3, r4, r7, r9, lr} + 1e850: e59d0434 ldr r0, [sp, #1076] + 1e854: e2800f07 add r0, r0, #28 ; 0x1c + 1e858: ebf5942e bl 0xffd83918 + 1e85c: 0800429c stmeqda r0, {r2, r3, r4, r7, r9, lr} + 1e860: e58d041c str r0, [sp, #1052] + 1e864: ebf595c5 bl 0xffd83f80 + 1e868: 0800429a stmeqda r0, {r1, r3, r4, r7, r9, lr} + 1e86c: e59de41c ldr lr, [sp, #1052] + 1e870: e1b04e54 movs r4, r4, asr lr + 1e874: ebf595c1 bl 0xffd83f80 + 1e878: 0800429c stmeqda r0, {r2, r3, r4, r7, r9, lr} + 1e87c: e59d1418 ldr r1, [sp, #1048] + 1e880: e59d1418 ldr r1, [sp, #1048] + 1e884: e0914004 adds r4, r1, r4 + 1e888: ebf595bc bl 0xffd83f80 + 1e88c: 0800429e stmeqda r0, {r1, r2, r3, r4, r7, r9, lr} + 1e890: e1b04584 movs r4, r4, lsl #11 + 1e894: ebf595b9 bl 0xffd83f80 + 1e898: 080042a0 stmeqda r0, {r5, r7, r9, lr} + 1e89c: e59d1428 ldr r1, [sp, #1064] + 1e8a0: e0844001 add r4, r4, r1 + 1e8a4: ebf595b5 bl 0xffd83f80 + 1e8a8: 080042a2 stmeqda r0, {r1, r5, r7, r9, lr} + 1e8ac: e1b03307 movs r3, r7, lsl #6 + 1e8b0: ebf595b2 bl 0xffd83f80 + 1e8b4: 080042a4 stmeqda r0, {r2, r5, r7, r9, lr} + 1e8b8: e1a01004 mov r1, r4 + 1e8bc: e0944003 adds r4, r4, r3 + 1e8c0: ebf595ae bl 0xffd83f80 + 1e8c4: 080042a6 stmeqda r0, {r1, r2, r5, r7, r9, lr} + 1e8c8: e1a01005 mov r1, r5 + 1e8cc: e2953000 adds r3, r5, #0 ; 0x0 + 1e8d0: ebf595aa bl 0xffd83f80 + 1e8d4: 080042a8 stmeqda r0, {r3, r5, r7, r9, lr} + 1e8d8: e3b0801c movs r8, #28 ; 0x1c + 1e8dc: ebf595a7 bl 0xffd83f80 + 1e8e0: 080042aa stmeqda r0, {r1, r3, r5, r7, r9, lr} + 1e8e4: e1a01003 mov r1, r3 + 1e8e8: e0133008 ands r3, r3, r8 + 1e8ec: ebf595a3 bl 0xffd83f80 + 1e8f0: 080042ac stmeqda r0, {r2, r3, r5, r7, r9, lr} + 1e8f4: e1b03083 movs r3, r3, lsl #1 + 1e8f8: ebf595a0 bl 0xffd83f80 + 1e8fc: 080042ae stmeqda r0, {r1, r2, r3, r5, r7, r9, lr} + 1e900: e1a01004 mov r1, r4 + 1e904: e0944003 adds r4, r4, r3 + 1e908: ebf5959c bl 0xffd83f80 + 1e90c: 080042b0 stmeqda r0, {r4, r5, r7, r9, lr} + 1e910: e1b03086 movs r3, r6, lsl #1 + 1e914: ebf59599 bl 0xffd83f80 + 1e918: 080042b2 stmeqda r0, {r1, r4, r5, r7, r9, lr} + 1e91c: e59d1420 ldr r1, [sp, #1056] + 1e920: e0833001 add r3, r3, r1 + 1e924: ebf59595 bl 0xffd83f80 + 1e928: 080042b4 stmeqda r0, {r2, r4, r5, r7, r9, lr} + 1e92c: e2830000 add r0, r3, #0 ; 0x0 + 1e930: ebf593cc bl 0xffd83868 + 1e934: 080042b8 stmeqda r0, {r3, r4, r5, r7, r9, lr} + 1e938: e1a03000 mov r3, r0 + 1e93c: ebf5958f bl 0xffd83f80 + 1e940: 080042b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, lr} + 1e944: e1a01005 mov r1, r5 + 1e948: e2958004 adds r8, r5, #4 ; 0x4 + 1e94c: ebf5958b bl 0xffd83f80 + 1e950: 080042b8 stmeqda r0, {r3, r4, r5, r7, r9, lr} + 1e954: e1a01006 mov r1, r6 + 1e958: e2960001 adds r0, r6, #1 ; 0x1 + 1e95c: e58d041c str r0, [sp, #1052] + 1e960: ebf59586 bl 0xffd83f80 + 1e964: 080042ba stmeqda r0, {r1, r3, r4, r5, r7, r9, lr} + 1e968: e1b03283 movs r3, r3, lsl #5 + 1e96c: ebf59583 bl 0xffd83f80 + 1e970: 080042bc stmeqda r0, {r2, r3, r4, r5, r7, r9, lr} + 1e974: e59d0434 ldr r0, [sp, #1076] + 1e978: e2800f06 add r0, r0, #24 ; 0x18 + 1e97c: ebf593e5 bl 0xffd83918 + 1e980: 080042c0 stmeqda r0, {r6, r7, r9, lr} + 1e984: e1a05000 mov r5, r0 + 1e988: ebf5957c bl 0xffd83f80 + 1e98c: 080042be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, lr} + 1e990: e1a01005 mov r1, r5 + 1e994: e0956003 adds r6, r5, r3 + 1e998: ebf59578 bl 0xffd83f80 + 1e99c: 080042c0 stmeqda r0, {r6, r7, r9, lr} + 1e9a0: e3b05003 movs r5, #3 ; 0x3 + 1e9a4: e28cc04e add ip, ip, #78 ; 0x4e + 1e9a8: ebf59574 bl 0xffd83f80 + 1e9ac: 080042c2 stmeqda r0, {r1, r6, r7, r9, lr} + 1e9b0: e2860000 add r0, r6, #0 ; 0x0 + 1e9b4: ebf593ab bl 0xffd83868 + 1e9b8: 080042c6 stmeqda r0, {r1, r2, r6, r7, r9, lr} + 1e9bc: e1a03000 mov r3, r0 + 1e9c0: ebf5956e bl 0xffd83f80 + 1e9c4: 080042c4 stmeqda r0, {r2, r6, r7, r9, lr} + 1e9c8: e2840000 add r0, r4, #0 ; 0x0 + 1e9cc: e1a01003 mov r1, r3 + 1e9d0: ebf592dd bl 0xffd8354c + 1e9d4: 080042c6 stmeqda r0, {r1, r2, r6, r7, r9, lr} + 1e9d8: ebf59568 bl 0xffd83f80 + 1e9dc: 080042c6 stmeqda r0, {r1, r2, r6, r7, r9, lr} + 1e9e0: e2860002 add r0, r6, #2 ; 0x2 + 1e9e4: ebf5939f bl 0xffd83868 + 1e9e8: 080042ca stmeqda r0, {r1, r3, r6, r7, r9, lr} + 1e9ec: e1a03000 mov r3, r0 + 1e9f0: ebf59562 bl 0xffd83f80 + 1e9f4: 080042c8 stmeqda r0, {r3, r6, r7, r9, lr} + 1e9f8: e2840002 add r0, r4, #2 ; 0x2 + 1e9fc: e1a01003 mov r1, r3 + 1ea00: ebf592d1 bl 0xffd8354c + 1ea04: 080042ca stmeqda r0, {r1, r3, r6, r7, r9, lr} + 1ea08: ebf5955c bl 0xffd83f80 + 1ea0c: 080042ca stmeqda r0, {r1, r3, r6, r7, r9, lr} + 1ea10: e2860004 add r0, r6, #4 ; 0x4 + 1ea14: ebf59393 bl 0xffd83868 + 1ea18: 080042ce stmeqda r0, {r1, r2, r3, r6, r7, r9, lr} + 1ea1c: e1a03000 mov r3, r0 + 1ea20: ebf59556 bl 0xffd83f80 + 1ea24: 080042cc stmeqda r0, {r2, r3, r6, r7, r9, lr} + 1ea28: e2840004 add r0, r4, #4 ; 0x4 + 1ea2c: e1a01003 mov r1, r3 + 1ea30: ebf592c5 bl 0xffd8354c + 1ea34: 080042ce stmeqda r0, {r1, r2, r3, r6, r7, r9, lr} + 1ea38: ebf59550 bl 0xffd83f80 + 1ea3c: 080042ce stmeqda r0, {r1, r2, r3, r6, r7, r9, lr} + 1ea40: e2860006 add r0, r6, #6 ; 0x6 + 1ea44: ebf59387 bl 0xffd83868 + 1ea48: 080042d2 stmeqda r0, {r1, r4, r6, r7, r9, lr} + 1ea4c: e1a03000 mov r3, r0 + 1ea50: ebf5954a bl 0xffd83f80 + 1ea54: 080042d0 stmeqda r0, {r4, r6, r7, r9, lr} + 1ea58: e2840006 add r0, r4, #6 ; 0x6 + 1ea5c: e1a01003 mov r1, r3 + 1ea60: ebf592b9 bl 0xffd8354c + 1ea64: 080042d2 stmeqda r0, {r1, r4, r6, r7, r9, lr} + 1ea68: ebf59544 bl 0xffd83f80 + 1ea6c: 080042d2 stmeqda r0, {r1, r4, r6, r7, r9, lr} + 1ea70: e1a01004 mov r1, r4 + 1ea74: e2944040 adds r4, r4, #64 ; 0x40 + 1ea78: ebf59540 bl 0xffd83f80 + 1ea7c: 080042d4 stmeqda r0, {r2, r4, r6, r7, r9, lr} + 1ea80: e1a01006 mov r1, r6 + 1ea84: e2966008 adds r6, r6, #8 ; 0x8 + 1ea88: ebf5953c bl 0xffd83f80 + 1ea8c: 080042d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, lr} + 1ea90: e1a01005 mov r1, r5 + 1ea94: e2555001 subs r5, r5, #1 ; 0x1 + 1ea98: ebf59538 bl 0xffd83f80 + 1ea9c: 080042d8 stmeqda r0, {r3, r4, r6, r7, r9, lr} + 1eaa0: e3550000 cmp r5, #0 ; 0x0 + 1eaa4: ebf59535 bl 0xffd83f80 + 1eaa8: 080042da stmeqda r0, {r1, r3, r4, r6, r7, r9, lr} + 1eaac: e28cc033 add ip, ip, #51 ; 0x33 + 1eab0: ba000004 blt 0x1eac8 + 1eab4: e1a00fac mov r0, ip, lsr #31 + 1eab8: e08ff100 add pc, pc, r0, lsl #2 + 1eabc: 080042c2 stmeqda r0, {r1, r6, r7, r9, lr} + 1eac0: ebf59123 bl 0xffd82f54 + 1eac4: eaffffb7 b 0x1e9a8 + 1eac8: ebf5952c bl 0xffd83f80 + 1eacc: 080042dc stmeqda r0, {r2, r3, r4, r6, r7, r9, lr} + 1ead0: e1a01008 mov r1, r8 + 1ead4: e2985000 adds r5, r8, #0 ; 0x0 + 1ead8: ebf59528 bl 0xffd83f80 + 1eadc: 080042de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, lr} + 1eae0: e59d141c ldr r1, [sp, #1052] + 1eae4: e59d141c ldr r1, [sp, #1052] + 1eae8: e2916000 adds r6, r1, #0 ; 0x0 + 1eaec: ebf59523 bl 0xffd83f80 + 1eaf0: 080042e0 stmeqda r0, {r5, r6, r7, r9, lr} + 1eaf4: e59d1424 ldr r1, [sp, #1060] + 1eaf8: e1550001 cmp r5, r1 + 1eafc: ebf5951f bl 0xffd83f80 + 1eb00: 080042e2 stmeqda r0, {r1, r5, r6, r7, r9, lr} + 1eb04: e28cc00c add ip, ip, #12 ; 0xc + 1eb08: ca000004 bgt 0x1eb20 + 1eb0c: e1a00fac mov r0, ip, lsr #31 + 1eb10: e08ff100 add pc, pc, r0, lsl #2 + 1eb14: 08004292 stmeqda r0, {r1, r4, r7, r9, lr} + 1eb18: ebf5910d bl 0xffd82f54 + 1eb1c: eaffff3e b 0x1e81c + 1eb20: ebf59516 bl 0xffd83f80 + 1eb24: 080042e4 stmeqda r0, {r2, r5, r6, r7, r9, lr} + 1eb28: e59d1430 ldr r1, [sp, #1072] + 1eb2c: e1a04001 mov r4, r1 + 1eb30: ebf59512 bl 0xffd83f80 + 1eb34: 080042e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, lr} + 1eb38: e59d0434 ldr r0, [sp, #1076] + 1eb3c: e2800f00 add r0, r0, #0 ; 0x0 + 1eb40: ebf59374 bl 0xffd83918 + 1eb44: 080042ea stmeqda r0, {r1, r3, r5, r6, r7, r9, lr} + 1eb48: e1a06000 mov r6, r0 + 1eb4c: ebf5950b bl 0xffd83f80 + 1eb50: 080042e8 stmeqda r0, {r3, r5, r6, r7, r9, lr} + 1eb54: e3b07010 movs r7, #16 ; 0x10 + 1eb58: ebf59508 bl 0xffd83f80 + 1eb5c: 080042ea stmeqda r0, {r1, r3, r5, r6, r7, r9, lr} + 1eb60: e0860007 add r0, r6, r7 + 1eb64: ebf59354 bl 0xffd838bc + 1eb68: 080042ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, lr} + 1eb6c: e1a03000 mov r3, r0 + 1eb70: ebf59502 bl 0xffd83f80 + 1eb74: 080042ec stmeqda r0, {r2, r3, r5, r6, r7, r9, lr} + 1eb78: e1b03083 movs r3, r3, lsl #1 + 1eb7c: ebf594ff bl 0xffd83f80 + 1eb80: 080042ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, lr} + 1eb84: e59d0420 ldr r0, [sp, #1056] + 1eb88: e0800003 add r0, r0, r3 + 1eb8c: e58d0420 str r0, [sp, #1056] + 1eb90: ebf594fa bl 0xffd83f80 + 1eb94: 080042f0 stmeqda r0, {r4, r5, r6, r7, r9, lr} + 1eb98: e59d0434 ldr r0, [sp, #1076] + 1eb9c: e2800f03 add r0, r0, #12 ; 0xc + 1eba0: ebf5935c bl 0xffd83918 + 1eba4: 080042f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, lr} + 1eba8: e1a08000 mov r8, r0 + 1ebac: ebf594f3 bl 0xffd83f80 + 1ebb0: 080042f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, lr} + 1ebb4: e1540008 cmp r4, r8 + 1ebb8: ebf594f0 bl 0xffd83f80 + 1ebbc: 080042f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, lr} + 1ebc0: e28cc021 add ip, ip, #33 ; 0x21 + 1ebc4: ca000004 bgt 0x1ebdc + 1ebc8: e1a00fac mov r0, ip, lsr #31 + 1ebcc: e08ff100 add pc, pc, r0, lsl #2 + 1ebd0: 08004276 stmeqda r0, {r1, r2, r4, r5, r6, r9, lr} + 1ebd4: ebf590de bl 0xffd82f54 + 1ebd8: eafffec9 b 0x1e704 + 1ebdc: ebf594e7 bl 0xffd83f80 + 1ebe0: 080042f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, lr} + 1ebe4: e59d0434 ldr r0, [sp, #1076] + 1ebe8: e2800f00 add r0, r0, #0 ; 0x0 + 1ebec: ebf59349 bl 0xffd83918 + 1ebf0: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1ebf4: e58d041c str r0, [sp, #1052] + 1ebf8: ebf594e0 bl 0xffd83f80 + 1ebfc: 080042f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, lr} + 1ec00: e59d041c ldr r0, [sp, #1052] + 1ec04: e2800000 add r0, r0, #0 ; 0x0 + 1ec08: ebf59316 bl 0xffd83868 + 1ec0c: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1ec10: e1a04000 mov r4, r0 + 1ec14: ebf594d9 bl 0xffd83f80 + 1ec18: 080042fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, lr} + 1ec1c: e3b05080 movs r5, #128 ; 0x80 + 1ec20: ebf594d6 bl 0xffd83f80 + 1ec24: 080042fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, lr} + 1ec28: e1b05385 movs r5, r5, lsl #7 + 1ec2c: ebf594d3 bl 0xffd83f80 + 1ec30: 080042fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, lr} + 1ec34: e1a01005 mov r1, r5 + 1ec38: e2953000 adds r3, r5, #0 ; 0x0 + 1ec3c: ebf594cf bl 0xffd83f80 + 1ec40: 08004300 stmeqda r0, {r8, r9, lr} + 1ec44: e1a01003 mov r1, r3 + 1ec48: e1933004 orrs r3, r3, r4 + 1ec4c: ebf594cb bl 0xffd83f80 + 1ec50: 08004302 stmeqda r0, {r1, r8, r9, lr} + 1ec54: e59d041c ldr r0, [sp, #1052] + 1ec58: e2800000 add r0, r0, #0 ; 0x0 + 1ec5c: e1a01003 mov r1, r3 + 1ec60: ebf59239 bl 0xffd8354c + 1ec64: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1ec68: ebf594c4 bl 0xffd83f80 + 1ec6c: 08004304 stmeqda r0, {r2, r8, r9, lr} + 1ec70: e59d0434 ldr r0, [sp, #1076] + 1ec74: e2800f0c add r0, r0, #48 ; 0x30 + 1ec78: e58d0434 str r0, [sp, #1076] + 1ec7c: ebf594bf bl 0xffd83f80 + 1ec80: 08004306 stmeqda r0, {r1, r2, r8, r9, lr} + 1ec84: e59d9434 ldr r9, [sp, #1076] + 1ec88: e3c99003 bic r9, r9, #3 ; 0x3 + 1ec8c: e289000c add r0, r9, #12 ; 0xc + 1ec90: e58d0434 str r0, [sp, #1076] + 1ec94: e2890000 add r0, r9, #0 ; 0x0 + 1ec98: ebf5931e bl 0xffd83918 + 1ec9c: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1eca0: e1a06000 mov r6, r0 + 1eca4: e2890004 add r0, r9, #4 ; 0x4 + 1eca8: ebf5931a bl 0xffd83918 + 1ecac: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1ecb0: e1a07000 mov r7, r0 + 1ecb4: e2890008 add r0, r9, #8 ; 0x8 + 1ecb8: ebf59316 bl 0xffd83918 + 1ecbc: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1ecc0: e1a08000 mov r8, r0 + 1ecc4: ebf594ad bl 0xffd83f80 + 1ecc8: 08004308 stmeqda r0, {r3, r8, r9, lr} + 1eccc: e1a00006 mov r0, r6 + 1ecd0: e58d0420 str r0, [sp, #1056] + 1ecd4: ebf594a9 bl 0xffd83f80 + 1ecd8: 0800430a stmeqda r0, {r1, r3, r8, r9, lr} + 1ecdc: e1a00007 mov r0, r7 + 1ece0: e58d0424 str r0, [sp, #1060] + 1ece4: ebf594a5 bl 0xffd83f80 + 1ece8: 0800430c stmeqda r0, {r2, r3, r8, r9, lr} + 1ecec: e1a00008 mov r0, r8 + 1ecf0: e58d0428 str r0, [sp, #1064] + 1ecf4: ebf594a1 bl 0xffd83f80 + 1ecf8: 0800430e stmeqda r0, {r1, r2, r3, r8, r9, lr} + 1ecfc: e59d9434 ldr r9, [sp, #1076] + 1ed00: e3c99003 bic r9, r9, #3 ; 0x3 + 1ed04: e2890010 add r0, r9, #16 ; 0x10 + 1ed08: e58d0434 str r0, [sp, #1076] + 1ed0c: e2890000 add r0, r9, #0 ; 0x0 + 1ed10: ebf59300 bl 0xffd83918 + 1ed14: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1ed18: e1a07000 mov r7, r0 + 1ed1c: e2890004 add r0, r9, #4 ; 0x4 + 1ed20: ebf592fc bl 0xffd83918 + 1ed24: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1ed28: e1a08000 mov r8, r0 + 1ed2c: e2890008 add r0, r9, #8 ; 0x8 + 1ed30: ebf592f8 bl 0xffd83918 + 1ed34: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1ed38: e58d0418 str r0, [sp, #1048] + 1ed3c: e289000c add r0, r9, #12 ; 0xc + 1ed40: ebf592f4 bl 0xffd83918 + 1ed44: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1ed48: e58d041c str r0, [sp, #1052] + 1ed4c: ebf5948b bl 0xffd83f80 + 1ed50: 08004310 stmeqda r0, {r4, r8, r9, lr} + 1ed54: e59d9434 ldr r9, [sp, #1076] + 1ed58: e3c99003 bic r9, r9, #3 ; 0x3 + 1ed5c: e2890004 add r0, r9, #4 ; 0x4 + 1ed60: e58d0434 str r0, [sp, #1076] + 1ed64: e2890000 add r0, r9, #0 ; 0x0 + 1ed68: ebf592ea bl 0xffd83918 + 1ed6c: 08004314 stmeqda r0, {r2, r4, r8, r9, lr} + 1ed70: e1a03000 mov r3, r0 + 1ed74: ebf59481 bl 0xffd83f80 + 1ed78: 08004312 stmeqda r0, {r1, r4, r8, r9, lr} + 1ed7c: e1a00003 mov r0, r3 + 1ed80: e28cc03a add ip, ip, #58 ; 0x3a + 1ed84: eaf590d1 b 0xffd830d0 + 1ed88: 08002c86 stmeqda r0, {r1, r2, r7, sl, fp, sp} + 1ed8c: 00000000 andeq r0, r0, r0 + 1ed90: ebf5947a bl 0xffd83f80 + 1ed94: 08002c86 stmeqda r0, {r1, r2, r7, sl, fp, sp} + 1ed98: ebf59478 bl 0xffd83f80 + 1ed9c: 08002c88 stmeqda r0, {r3, r7, sl, fp, sp} + 1eda0: e3a0008b mov r0, #139 ; 0x8b + 1eda4: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 1eda8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1edac: e58d0438 str r0, [sp, #1080] + 1edb0: e28cc006 add ip, ip, #6 ; 0x6 + 1edb4: e1a00fac mov r0, ip, lsr #31 + 1edb8: e08ff100 add pc, pc, r0, lsl #2 + 1edbc: 080062ac stmeqda r0, {r2, r3, r5, r7, r9, sp, lr} + 1edc0: ebf59063 bl 0xffd82f54 + 1edc4: ea000001 b 0x1edd0 + 1edc8: 080062ac stmeqda r0, {r2, r3, r5, r7, r9, sp, lr} + 1edcc: 00000000 andeq r0, r0, r0 + 1edd0: ebf5946a bl 0xffd83f80 + 1edd4: 080062ac stmeqda r0, {r2, r3, r5, r7, r9, sp, lr} + 1edd8: e59d9434 ldr r9, [sp, #1076] + 1eddc: e3c99003 bic r9, r9, #3 ; 0x3 + 1ede0: e2499008 sub r9, r9, #8 ; 0x8 + 1ede4: e58d9434 str r9, [sp, #1076] + 1ede8: e2890000 add r0, r9, #0 ; 0x0 + 1edec: e1a01007 mov r1, r7 + 1edf0: ebf59215 bl 0xffd8364c + 1edf4: e2890004 add r0, r9, #4 ; 0x4 + 1edf8: e59d1438 ldr r1, [sp, #1080] + 1edfc: ebf59212 bl 0xffd8364c + 1ee00: ebf5945e bl 0xffd83f80 + 1ee04: 080062ae stmeqda r0, {r1, r2, r3, r5, r7, r9, sp, lr} + 1ee08: e3a00fc1 mov r0, #772 ; 0x304 + 1ee0c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1ee10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ee14: ebf592bf bl 0xffd83918 + 1ee18: 080062b2 stmeqda r0, {r1, r4, r5, r7, r9, sp, lr} + 1ee1c: e1a06000 mov r6, r0 + 1ee20: ebf59456 bl 0xffd83f80 + 1ee24: 080062b0 stmeqda r0, {r4, r5, r7, r9, sp, lr} + 1ee28: e3a00fc2 mov r0, #776 ; 0x308 + 1ee2c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1ee30: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ee34: ebf592b7 bl 0xffd83918 + 1ee38: 080062b4 stmeqda r0, {r2, r4, r5, r7, r9, sp, lr} + 1ee3c: e1a05000 mov r5, r0 + 1ee40: ebf5944e bl 0xffd83f80 + 1ee44: 080062b2 stmeqda r0, {r1, r4, r5, r7, r9, sp, lr} + 1ee48: e3a00fc3 mov r0, #780 ; 0x30c + 1ee4c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1ee50: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ee54: ebf592af bl 0xffd83918 + 1ee58: 080062b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sp, lr} + 1ee5c: e1a04000 mov r4, r0 + 1ee60: ebf59446 bl 0xffd83f80 + 1ee64: 080062b4 stmeqda r0, {r2, r4, r5, r7, r9, sp, lr} + 1ee68: e1a01005 mov r1, r5 + 1ee6c: e0953004 adds r3, r5, r4 + 1ee70: ebf59442 bl 0xffd83f80 + 1ee74: 080062b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, sp, lr} + 1ee78: e2830000 add r0, r3, #0 ; 0x0 + 1ee7c: ebf5924e bl 0xffd837bc + 1ee80: 080062ba stmeqda r0, {r1, r3, r4, r5, r7, r9, sp, lr} + 1ee84: e1a04000 mov r4, r0 + 1ee88: ebf5943c bl 0xffd83f80 + 1ee8c: 080062b8 stmeqda r0, {r3, r4, r5, r7, r9, sp, lr} + 1ee90: e3a00e31 mov r0, #784 ; 0x310 + 1ee94: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1ee98: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ee9c: ebf5929d bl 0xffd83918 + 1eea0: 080062bc stmeqda r0, {r2, r3, r4, r5, r7, r9, sp, lr} + 1eea4: e1a07000 mov r7, r0 + 1eea8: ebf59434 bl 0xffd83f80 + 1eeac: 080062ba stmeqda r0, {r1, r3, r4, r5, r7, r9, sp, lr} + 1eeb0: e1a01005 mov r1, r5 + 1eeb4: e0953007 adds r3, r5, r7 + 1eeb8: ebf59430 bl 0xffd83f80 + 1eebc: 080062bc stmeqda r0, {r2, r3, r4, r5, r7, r9, sp, lr} + 1eec0: e2830000 add r0, r3, #0 ; 0x0 + 1eec4: ebf5923c bl 0xffd837bc + 1eec8: 080062c0 stmeqda r0, {r6, r7, r9, sp, lr} + 1eecc: e1a03000 mov r3, r0 + 1eed0: ebf5942a bl 0xffd83f80 + 1eed4: 080062be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, sp, lr} + 1eed8: e1b03403 movs r3, r3, lsl #8 + 1eedc: ebf59427 bl 0xffd83f80 + 1eee0: 080062c0 stmeqda r0, {r6, r7, r9, sp, lr} + 1eee4: e1a01004 mov r1, r4 + 1eee8: e1944003 orrs r4, r4, r3 + 1eeec: ebf59423 bl 0xffd83f80 + 1eef0: 080062c2 stmeqda r0, {r1, r6, r7, r9, sp, lr} + 1eef4: e2860012 add r0, r6, #18 ; 0x12 + 1eef8: e1a01004 mov r1, r4 + 1eefc: ebf59192 bl 0xffd8354c + 1ef00: 080062c4 stmeqda r0, {r2, r6, r7, r9, sp, lr} + 1ef04: ebf5941d bl 0xffd83f80 + 1ef08: 080062c4 stmeqda r0, {r2, r6, r7, r9, sp, lr} + 1ef0c: e2860014 add r0, r6, #20 ; 0x14 + 1ef10: ebf59254 bl 0xffd83868 + 1ef14: 080062c8 stmeqda r0, {r3, r6, r7, r9, sp, lr} + 1ef18: e1a04000 mov r4, r0 + 1ef1c: ebf59417 bl 0xffd83f80 + 1ef20: 080062c6 stmeqda r0, {r1, r2, r6, r7, r9, sp, lr} + 1ef24: e3b030ff movs r3, #255 ; 0xff + 1ef28: ebf59414 bl 0xffd83f80 + 1ef2c: 080062c8 stmeqda r0, {r3, r6, r7, r9, sp, lr} + 1ef30: e1b03403 movs r3, r3, lsl #8 + 1ef34: ebf59411 bl 0xffd83f80 + 1ef38: 080062ca stmeqda r0, {r1, r3, r6, r7, r9, sp, lr} + 1ef3c: e1a01003 mov r1, r3 + 1ef40: e0133004 ands r3, r3, r4 + 1ef44: ebf5940d bl 0xffd83f80 + 1ef48: 080062cc stmeqda r0, {r2, r3, r6, r7, r9, sp, lr} + 1ef4c: e1a01007 mov r1, r7 + 1ef50: e2977001 adds r7, r7, #1 ; 0x1 + 1ef54: ebf59409 bl 0xffd83f80 + 1ef58: 080062ce stmeqda r0, {r1, r2, r3, r6, r7, r9, sp, lr} + 1ef5c: e1a01005 mov r1, r5 + 1ef60: e0954007 adds r4, r5, r7 + 1ef64: ebf59405 bl 0xffd83f80 + 1ef68: 080062d0 stmeqda r0, {r4, r6, r7, r9, sp, lr} + 1ef6c: e2840000 add r0, r4, #0 ; 0x0 + 1ef70: ebf59211 bl 0xffd837bc + 1ef74: 080062d4 stmeqda r0, {r2, r4, r6, r7, r9, sp, lr} + 1ef78: e1a04000 mov r4, r0 + 1ef7c: ebf593ff bl 0xffd83f80 + 1ef80: 080062d2 stmeqda r0, {r1, r4, r6, r7, r9, sp, lr} + 1ef84: e1a01003 mov r1, r3 + 1ef88: e1933004 orrs r3, r3, r4 + 1ef8c: ebf593fb bl 0xffd83f80 + 1ef90: 080062d4 stmeqda r0, {r2, r4, r6, r7, r9, sp, lr} + 1ef94: e2860014 add r0, r6, #20 ; 0x14 + 1ef98: e1a01003 mov r1, r3 + 1ef9c: ebf5916a bl 0xffd8354c + 1efa0: 080062d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sp, lr} + 1efa4: ebf593f5 bl 0xffd83f80 + 1efa8: 080062d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sp, lr} + 1efac: e3b040a3 movs r4, #163 ; 0xa3 + 1efb0: ebf593f2 bl 0xffd83f80 + 1efb4: 080062d8 stmeqda r0, {r3, r4, r6, r7, r9, sp, lr} + 1efb8: e1b04284 movs r4, r4, lsl #5 + 1efbc: ebf593ef bl 0xffd83f80 + 1efc0: 080062da stmeqda r0, {r1, r3, r4, r6, r7, r9, sp, lr} + 1efc4: e1a01005 mov r1, r5 + 1efc8: e0953004 adds r3, r5, r4 + 1efcc: ebf593eb bl 0xffd83f80 + 1efd0: 080062dc stmeqda r0, {r2, r3, r4, r6, r7, r9, sp, lr} + 1efd4: e1a01007 mov r1, r7 + 1efd8: e2577008 subs r7, r7, #8 ; 0x8 + 1efdc: ebf593e7 bl 0xffd83f80 + 1efe0: 080062de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sp, lr} + 1efe4: e1a01005 mov r1, r5 + 1efe8: e0954007 adds r4, r5, r7 + 1efec: ebf593e3 bl 0xffd83f80 + 1eff0: 080062e0 stmeqda r0, {r5, r6, r7, r9, sp, lr} + 1eff4: e2830000 add r0, r3, #0 ; 0x0 + 1eff8: ebf591ef bl 0xffd837bc + 1effc: 080062e4 stmeqda r0, {r2, r5, r6, r7, r9, sp, lr} + 1f000: e1a03000 mov r3, r0 + 1f004: ebf593dd bl 0xffd83f80 + 1f008: 080062e2 stmeqda r0, {r1, r5, r6, r7, r9, sp, lr} + 1f00c: e2840000 add r0, r4, #0 ; 0x0 + 1f010: ebf591e9 bl 0xffd837bc + 1f014: 080062e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, sp, lr} + 1f018: e1a04000 mov r4, r0 + 1f01c: ebf593d7 bl 0xffd83f80 + 1f020: 080062e4 stmeqda r0, {r2, r5, r6, r7, r9, sp, lr} + 1f024: e1530004 cmp r3, r4 + 1f028: ebf593d4 bl 0xffd83f80 + 1f02c: 080062e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, sp, lr} + 1f030: e28cc071 add ip, ip, #113 ; 0x71 + 1f034: 2a000004 bcs 0x1f04c + 1f038: e1a00fac mov r0, ip, lsr #31 + 1f03c: e08ff100 add pc, pc, r0, lsl #2 + 1f040: 0800631c stmeqda r0, {r2, r3, r4, r8, r9, sp, lr} + 1f044: ebf58fc2 bl 0xffd82f54 + 1f048: ea00004d b 0x1f184 + 1f04c: ebf593cb bl 0xffd83f80 + 1f050: 080062e8 stmeqda r0, {r3, r5, r6, r7, r9, sp, lr} + 1f054: e3a00fc5 mov r0, #788 ; 0x314 + 1f058: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f05c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f060: ebf5922c bl 0xffd83918 + 1f064: 080062ec stmeqda r0, {r2, r3, r5, r6, r7, r9, sp, lr} + 1f068: e1a04000 mov r4, r0 + 1f06c: ebf593c3 bl 0xffd83f80 + 1f070: 080062ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sp, lr} + 1f074: e1a01005 mov r1, r5 + 1f078: e0953004 adds r3, r5, r4 + 1f07c: ebf593bf bl 0xffd83f80 + 1f080: 080062ec stmeqda r0, {r2, r3, r5, r6, r7, r9, sp, lr} + 1f084: e1a01007 mov r1, r7 + 1f088: e2977004 adds r7, r7, #4 ; 0x4 + 1f08c: ebf593bb bl 0xffd83f80 + 1f090: 080062ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sp, lr} + 1f094: e1a01005 mov r1, r5 + 1f098: e0954007 adds r4, r5, r7 + 1f09c: ebf593b7 bl 0xffd83f80 + 1f0a0: 080062f0 stmeqda r0, {r4, r5, r6, r7, r9, sp, lr} + 1f0a4: e2830000 add r0, r3, #0 ; 0x0 + 1f0a8: ebf591c3 bl 0xffd837bc + 1f0ac: 080062f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sp, lr} + 1f0b0: e1a03000 mov r3, r0 + 1f0b4: ebf593b1 bl 0xffd83f80 + 1f0b8: 080062f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sp, lr} + 1f0bc: e2840000 add r0, r4, #0 ; 0x0 + 1f0c0: ebf591bd bl 0xffd837bc + 1f0c4: 080062f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sp, lr} + 1f0c8: e1a04000 mov r4, r0 + 1f0cc: ebf593ab bl 0xffd83f80 + 1f0d0: 080062f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sp, lr} + 1f0d4: e1530004 cmp r3, r4 + 1f0d8: ebf593a8 bl 0xffd83f80 + 1f0dc: 080062f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sp, lr} + 1f0e0: e28cc01e add ip, ip, #30 ; 0x1e + 1f0e4: 2a000004 bcs 0x1f0fc + 1f0e8: e1a00fac mov r0, ip, lsr #31 + 1f0ec: e08ff100 add pc, pc, r0, lsl #2 + 1f0f0: 0800631c stmeqda r0, {r2, r3, r4, r8, r9, sp, lr} + 1f0f4: ebf58f96 bl 0xffd82f54 + 1f0f8: ea000021 b 0x1f184 + 1f0fc: ebf5939f bl 0xffd83f80 + 1f100: 080062f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sp, lr} + 1f104: e2860000 add r0, r6, #0 ; 0x0 + 1f108: ebf591d6 bl 0xffd83868 + 1f10c: 080062fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sp, lr} + 1f110: e1a04000 mov r4, r0 + 1f114: ebf59399 bl 0xffd83f80 + 1f118: 080062fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sp, lr} + 1f11c: e3a00fc6 mov r0, #792 ; 0x318 + 1f120: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f124: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f128: ebf591fa bl 0xffd83918 + 1f12c: 080062fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sp, lr} + 1f130: e1a03000 mov r3, r0 + 1f134: ebf59391 bl 0xffd83f80 + 1f138: 080062fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sp, lr} + 1f13c: e1a01003 mov r1, r3 + 1f140: e0133004 ands r3, r3, r4 + 1f144: ebf5938d bl 0xffd83f80 + 1f148: 080062fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sp, lr} + 1f14c: e2860000 add r0, r6, #0 ; 0x0 + 1f150: e1a01003 mov r1, r3 + 1f154: ebf590fc bl 0xffd8354c + 1f158: 08006300 stmeqda r0, {r8, r9, sp, lr} + 1f15c: ebf59387 bl 0xffd83f80 + 1f160: 08006300 stmeqda r0, {r8, r9, sp, lr} + 1f164: e28cc014 add ip, ip, #20 ; 0x14 + 1f168: e1a00fac mov r0, ip, lsr #31 + 1f16c: e08ff100 add pc, pc, r0, lsl #2 + 1f170: 0800634e stmeqda r0, {r1, r2, r3, r6, r8, r9, sp, lr} + 1f174: ebf58f76 bl 0xffd82f54 + 1f178: ea0001a3 b 0x1f80c + 1f17c: 0800631c stmeqda r0, {r2, r3, r4, r8, r9, sp, lr} + 1f180: 00000000 andeq r0, r0, r0 + 1f184: ebf5937d bl 0xffd83f80 + 1f188: 0800631c stmeqda r0, {r2, r3, r4, r8, r9, sp, lr} + 1f18c: e2860000 add r0, r6, #0 ; 0x0 + 1f190: ebf591b4 bl 0xffd83868 + 1f194: 08006320 stmeqda r0, {r5, r8, r9, sp, lr} + 1f198: e1a04000 mov r4, r0 + 1f19c: ebf59377 bl 0xffd83f80 + 1f1a0: 0800631e stmeqda r0, {r1, r2, r3, r4, r8, r9, sp, lr} + 1f1a4: e3b07080 movs r7, #128 ; 0x80 + 1f1a8: ebf59374 bl 0xffd83f80 + 1f1ac: 08006320 stmeqda r0, {r5, r8, r9, sp, lr} + 1f1b0: e1b07307 movs r7, r7, lsl #6 + 1f1b4: ebf59371 bl 0xffd83f80 + 1f1b8: 08006322 stmeqda r0, {r1, r5, r8, r9, sp, lr} + 1f1bc: e1a01007 mov r1, r7 + 1f1c0: e2973000 adds r3, r7, #0 ; 0x0 + 1f1c4: ebf5936d bl 0xffd83f80 + 1f1c8: 08006324 stmeqda r0, {r2, r5, r8, r9, sp, lr} + 1f1cc: e1a01003 mov r1, r3 + 1f1d0: e1933004 orrs r3, r3, r4 + 1f1d4: ebf59369 bl 0xffd83f80 + 1f1d8: 08006326 stmeqda r0, {r1, r2, r5, r8, r9, sp, lr} + 1f1dc: e2860000 add r0, r6, #0 ; 0x0 + 1f1e0: e1a01003 mov r1, r3 + 1f1e4: ebf590d8 bl 0xffd8354c + 1f1e8: 08006328 stmeqda r0, {r3, r5, r8, r9, sp, lr} + 1f1ec: ebf59363 bl 0xffd83f80 + 1f1f0: 08006328 stmeqda r0, {r3, r5, r8, r9, sp, lr} + 1f1f4: e3b040a3 movs r4, #163 ; 0xa3 + 1f1f8: ebf59360 bl 0xffd83f80 + 1f1fc: 0800632a stmeqda r0, {r1, r3, r5, r8, r9, sp, lr} + 1f200: e1b04284 movs r4, r4, lsl #5 + 1f204: ebf5935d bl 0xffd83f80 + 1f208: 0800632c stmeqda r0, {r2, r3, r5, r8, r9, sp, lr} + 1f20c: e1a01005 mov r1, r5 + 1f210: e0953004 adds r3, r5, r4 + 1f214: ebf59359 bl 0xffd83f80 + 1f218: 0800632e stmeqda r0, {r1, r2, r3, r5, r8, r9, sp, lr} + 1f21c: e2830000 add r0, r3, #0 ; 0x0 + 1f220: ebf59165 bl 0xffd837bc + 1f224: 08006332 stmeqda r0, {r1, r4, r5, r8, r9, sp, lr} + 1f228: e1a04000 mov r4, r0 + 1f22c: ebf59353 bl 0xffd83f80 + 1f230: 08006330 stmeqda r0, {r4, r5, r8, r9, sp, lr} + 1f234: e1b04404 movs r4, r4, lsl #8 + 1f238: ebf59350 bl 0xffd83f80 + 1f23c: 08006332 stmeqda r0, {r1, r4, r5, r8, r9, sp, lr} + 1f240: e3a00fde mov r0, #888 ; 0x378 + 1f244: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f248: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f24c: ebf591b1 bl 0xffd83918 + 1f250: 08006336 stmeqda r0, {r1, r2, r4, r5, r8, r9, sp, lr} + 1f254: e1a07000 mov r7, r0 + 1f258: ebf59348 bl 0xffd83f80 + 1f25c: 08006334 stmeqda r0, {r2, r4, r5, r8, r9, sp, lr} + 1f260: e1a01005 mov r1, r5 + 1f264: e0953007 adds r3, r5, r7 + 1f268: ebf59344 bl 0xffd83f80 + 1f26c: 08006336 stmeqda r0, {r1, r2, r4, r5, r8, r9, sp, lr} + 1f270: e2830000 add r0, r3, #0 ; 0x0 + 1f274: ebf59150 bl 0xffd837bc + 1f278: 0800633a stmeqda r0, {r1, r3, r4, r5, r8, r9, sp, lr} + 1f27c: e1a03000 mov r3, r0 + 1f280: ebf5933e bl 0xffd83f80 + 1f284: 08006338 stmeqda r0, {r3, r4, r5, r8, r9, sp, lr} + 1f288: e1a01003 mov r1, r3 + 1f28c: e1933004 orrs r3, r3, r4 + 1f290: ebf5933a bl 0xffd83f80 + 1f294: 0800633a stmeqda r0, {r1, r3, r4, r5, r8, r9, sp, lr} + 1f298: e286000a add r0, r6, #10 ; 0xa + 1f29c: e1a01003 mov r1, r3 + 1f2a0: ebf590a9 bl 0xffd8354c + 1f2a4: 0800633c stmeqda r0, {r2, r3, r4, r5, r8, r9, sp, lr} + 1f2a8: ebf59334 bl 0xffd83f80 + 1f2ac: 0800633c stmeqda r0, {r2, r3, r4, r5, r8, r9, sp, lr} + 1f2b0: e3a00fdf mov r0, #892 ; 0x37c + 1f2b4: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f2b8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f2bc: ebf59195 bl 0xffd83918 + 1f2c0: 08006340 stmeqda r0, {r6, r8, r9, sp, lr} + 1f2c4: e1a04000 mov r4, r0 + 1f2c8: ebf5932c bl 0xffd83f80 + 1f2cc: 0800633e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sp, lr} + 1f2d0: e1a01005 mov r1, r5 + 1f2d4: e0953004 adds r3, r5, r4 + 1f2d8: ebf59328 bl 0xffd83f80 + 1f2dc: 08006340 stmeqda r0, {r6, r8, r9, sp, lr} + 1f2e0: e2830000 add r0, r3, #0 ; 0x0 + 1f2e4: ebf59134 bl 0xffd837bc + 1f2e8: 08006344 stmeqda r0, {r2, r6, r8, r9, sp, lr} + 1f2ec: e1a04000 mov r4, r0 + 1f2f0: ebf59322 bl 0xffd83f80 + 1f2f4: 08006342 stmeqda r0, {r1, r6, r8, r9, sp, lr} + 1f2f8: e1b04404 movs r4, r4, lsl #8 + 1f2fc: ebf5931f bl 0xffd83f80 + 1f300: 08006344 stmeqda r0, {r2, r6, r8, r9, sp, lr} + 1f304: e1a01007 mov r1, r7 + 1f308: e2977004 adds r7, r7, #4 ; 0x4 + 1f30c: ebf5931b bl 0xffd83f80 + 1f310: 08006346 stmeqda r0, {r1, r2, r6, r8, r9, sp, lr} + 1f314: e1a01005 mov r1, r5 + 1f318: e0953007 adds r3, r5, r7 + 1f31c: ebf59317 bl 0xffd83f80 + 1f320: 08006348 stmeqda r0, {r3, r6, r8, r9, sp, lr} + 1f324: e2830000 add r0, r3, #0 ; 0x0 + 1f328: ebf59123 bl 0xffd837bc + 1f32c: 0800634c stmeqda r0, {r2, r3, r6, r8, r9, sp, lr} + 1f330: e1a03000 mov r3, r0 + 1f334: ebf59311 bl 0xffd83f80 + 1f338: 0800634a stmeqda r0, {r1, r3, r6, r8, r9, sp, lr} + 1f33c: e1a01003 mov r1, r3 + 1f340: e1933004 orrs r3, r3, r4 + 1f344: ebf5930d bl 0xffd83f80 + 1f348: 0800634c stmeqda r0, {r2, r3, r6, r8, r9, sp, lr} + 1f34c: e286000e add r0, r6, #14 ; 0xe + 1f350: e1a01003 mov r1, r3 + 1f354: ebf5907c bl 0xffd8354c + 1f358: 0800634e stmeqda r0, {r1, r2, r3, r6, r8, r9, sp, lr} + 1f35c: ebf59307 bl 0xffd83f80 + 1f360: 0800634e stmeqda r0, {r1, r2, r3, r6, r8, r9, sp, lr} + 1f364: e3a00d8e mov r0, #9088 ; 0x2380 + 1f368: e3800901 orr r0, r0, #16384 ; 0x4000 + 1f36c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f370: ebf59168 bl 0xffd83918 + 1f374: 08006352 stmeqda r0, {r1, r4, r6, r8, r9, sp, lr} + 1f378: e1a04000 mov r4, r0 + 1f37c: ebf592ff bl 0xffd83f80 + 1f380: 08006350 stmeqda r0, {r4, r6, r8, r9, sp, lr} + 1f384: e1a01005 mov r1, r5 + 1f388: e0953004 adds r3, r5, r4 + 1f38c: ebf592fb bl 0xffd83f80 + 1f390: 08006352 stmeqda r0, {r1, r4, r6, r8, r9, sp, lr} + 1f394: e3a00fe1 mov r0, #900 ; 0x384 + 1f398: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f39c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f3a0: ebf5915c bl 0xffd83918 + 1f3a4: 08006356 stmeqda r0, {r1, r2, r4, r6, r8, r9, sp, lr} + 1f3a8: e1a07000 mov r7, r0 + 1f3ac: ebf592f3 bl 0xffd83f80 + 1f3b0: 08006354 stmeqda r0, {r2, r4, r6, r8, r9, sp, lr} + 1f3b4: e1a01005 mov r1, r5 + 1f3b8: e0954007 adds r4, r5, r7 + 1f3bc: ebf592ef bl 0xffd83f80 + 1f3c0: 08006356 stmeqda r0, {r1, r2, r4, r6, r8, r9, sp, lr} + 1f3c4: e2830000 add r0, r3, #0 ; 0x0 + 1f3c8: ebf590fb bl 0xffd837bc + 1f3cc: 0800635a stmeqda r0, {r1, r3, r4, r6, r8, r9, sp, lr} + 1f3d0: e1a03000 mov r3, r0 + 1f3d4: ebf592e9 bl 0xffd83f80 + 1f3d8: 08006358 stmeqda r0, {r3, r4, r6, r8, r9, sp, lr} + 1f3dc: e2840000 add r0, r4, #0 ; 0x0 + 1f3e0: ebf590f5 bl 0xffd837bc + 1f3e4: 0800635c stmeqda r0, {r2, r3, r4, r6, r8, r9, sp, lr} + 1f3e8: e1a04000 mov r4, r0 + 1f3ec: ebf592e3 bl 0xffd83f80 + 1f3f0: 0800635a stmeqda r0, {r1, r3, r4, r6, r8, r9, sp, lr} + 1f3f4: e1530004 cmp r3, r4 + 1f3f8: ebf592e0 bl 0xffd83f80 + 1f3fc: 0800635c stmeqda r0, {r2, r3, r4, r6, r8, r9, sp, lr} + 1f400: e28cc07c add ip, ip, #124 ; 0x7c + 1f404: 2a000004 bcs 0x1f41c + 1f408: e1a00fac mov r0, ip, lsr #31 + 1f40c: e08ff100 add pc, pc, r0, lsl #2 + 1f410: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f414: ebf58ece bl 0xffd82f54 + 1f418: ea00004d b 0x1f554 + 1f41c: ebf592d7 bl 0xffd83f80 + 1f420: 0800635e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, sp, lr} + 1f424: e3a00fe2 mov r0, #904 ; 0x388 + 1f428: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f42c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f430: ebf59138 bl 0xffd83918 + 1f434: 08006362 stmeqda r0, {r1, r5, r6, r8, r9, sp, lr} + 1f438: e1a04000 mov r4, r0 + 1f43c: ebf592cf bl 0xffd83f80 + 1f440: 08006360 stmeqda r0, {r5, r6, r8, r9, sp, lr} + 1f444: e1a01005 mov r1, r5 + 1f448: e0953004 adds r3, r5, r4 + 1f44c: ebf592cb bl 0xffd83f80 + 1f450: 08006362 stmeqda r0, {r1, r5, r6, r8, r9, sp, lr} + 1f454: e1a01007 mov r1, r7 + 1f458: e2977004 adds r7, r7, #4 ; 0x4 + 1f45c: ebf592c7 bl 0xffd83f80 + 1f460: 08006364 stmeqda r0, {r2, r5, r6, r8, r9, sp, lr} + 1f464: e1a01005 mov r1, r5 + 1f468: e0954007 adds r4, r5, r7 + 1f46c: ebf592c3 bl 0xffd83f80 + 1f470: 08006366 stmeqda r0, {r1, r2, r5, r6, r8, r9, sp, lr} + 1f474: e2830000 add r0, r3, #0 ; 0x0 + 1f478: ebf590cf bl 0xffd837bc + 1f47c: 0800636a stmeqda r0, {r1, r3, r5, r6, r8, r9, sp, lr} + 1f480: e1a03000 mov r3, r0 + 1f484: ebf592bd bl 0xffd83f80 + 1f488: 08006368 stmeqda r0, {r3, r5, r6, r8, r9, sp, lr} + 1f48c: e2840000 add r0, r4, #0 ; 0x0 + 1f490: ebf590c9 bl 0xffd837bc + 1f494: 0800636c stmeqda r0, {r2, r3, r5, r6, r8, r9, sp, lr} + 1f498: e1a04000 mov r4, r0 + 1f49c: ebf592b7 bl 0xffd83f80 + 1f4a0: 0800636a stmeqda r0, {r1, r3, r5, r6, r8, r9, sp, lr} + 1f4a4: e1530004 cmp r3, r4 + 1f4a8: ebf592b4 bl 0xffd83f80 + 1f4ac: 0800636c stmeqda r0, {r2, r3, r5, r6, r8, r9, sp, lr} + 1f4b0: e28cc01e add ip, ip, #30 ; 0x1e + 1f4b4: 2a000004 bcs 0x1f4cc + 1f4b8: e1a00fac mov r0, ip, lsr #31 + 1f4bc: e08ff100 add pc, pc, r0, lsl #2 + 1f4c0: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f4c4: ebf58ea2 bl 0xffd82f54 + 1f4c8: ea000021 b 0x1f554 + 1f4cc: ebf592ab bl 0xffd83f80 + 1f4d0: 0800636e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sp, lr} + 1f4d4: e2860000 add r0, r6, #0 ; 0x0 + 1f4d8: ebf590e2 bl 0xffd83868 + 1f4dc: 08006372 stmeqda r0, {r1, r4, r5, r6, r8, r9, sp, lr} + 1f4e0: e1a04000 mov r4, r0 + 1f4e4: ebf592a5 bl 0xffd83f80 + 1f4e8: 08006370 stmeqda r0, {r4, r5, r6, r8, r9, sp, lr} + 1f4ec: e3a00fe3 mov r0, #908 ; 0x38c + 1f4f0: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f4f4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f4f8: ebf59106 bl 0xffd83918 + 1f4fc: 08006374 stmeqda r0, {r2, r4, r5, r6, r8, r9, sp, lr} + 1f500: e1a03000 mov r3, r0 + 1f504: ebf5929d bl 0xffd83f80 + 1f508: 08006372 stmeqda r0, {r1, r4, r5, r6, r8, r9, sp, lr} + 1f50c: e1a01003 mov r1, r3 + 1f510: e0133004 ands r3, r3, r4 + 1f514: ebf59299 bl 0xffd83f80 + 1f518: 08006374 stmeqda r0, {r2, r4, r5, r6, r8, r9, sp, lr} + 1f51c: e2860000 add r0, r6, #0 ; 0x0 + 1f520: e1a01003 mov r1, r3 + 1f524: ebf59008 bl 0xffd8354c + 1f528: 08006376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sp, lr} + 1f52c: ebf59293 bl 0xffd83f80 + 1f530: 08006376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sp, lr} + 1f534: e28cc014 add ip, ip, #20 ; 0x14 + 1f538: e1a00fac mov r0, ip, lsr #31 + 1f53c: e08ff100 add pc, pc, r0, lsl #2 + 1f540: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f544: ebf58e82 bl 0xffd82f54 + 1f548: ea000094 b 0x1f7a0 + 1f54c: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f550: 00000000 andeq r0, r0, r0 + 1f554: ebf59289 bl 0xffd83f80 + 1f558: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f55c: e2860000 add r0, r6, #0 ; 0x0 + 1f560: ebf590c0 bl 0xffd83868 + 1f564: 08006394 stmeqda r0, {r2, r4, r7, r8, r9, sp, lr} + 1f568: e1a04000 mov r4, r0 + 1f56c: ebf59283 bl 0xffd83f80 + 1f570: 08006392 stmeqda r0, {r1, r4, r7, r8, r9, sp, lr} + 1f574: e3b07080 movs r7, #128 ; 0x80 + 1f578: ebf59280 bl 0xffd83f80 + 1f57c: 08006394 stmeqda r0, {r2, r4, r7, r8, r9, sp, lr} + 1f580: e1b07387 movs r7, r7, lsl #7 + 1f584: ebf5927d bl 0xffd83f80 + 1f588: 08006396 stmeqda r0, {r1, r2, r4, r7, r8, r9, sp, lr} + 1f58c: e1a01007 mov r1, r7 + 1f590: e2973000 adds r3, r7, #0 ; 0x0 + 1f594: ebf59279 bl 0xffd83f80 + 1f598: 08006398 stmeqda r0, {r3, r4, r7, r8, r9, sp, lr} + 1f59c: e1a01003 mov r1, r3 + 1f5a0: e1933004 orrs r3, r3, r4 + 1f5a4: ebf59275 bl 0xffd83f80 + 1f5a8: 0800639a stmeqda r0, {r1, r3, r4, r7, r8, r9, sp, lr} + 1f5ac: e2860000 add r0, r6, #0 ; 0x0 + 1f5b0: e1a01003 mov r1, r3 + 1f5b4: ebf58fe4 bl 0xffd8354c + 1f5b8: 0800639c stmeqda r0, {r2, r3, r4, r7, r8, r9, sp, lr} + 1f5bc: ebf5926f bl 0xffd83f80 + 1f5c0: 0800639c stmeqda r0, {r2, r3, r4, r7, r8, r9, sp, lr} + 1f5c4: e3a00ff2 mov r0, #968 ; 0x3c8 + 1f5c8: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f5cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f5d0: ebf590d0 bl 0xffd83918 + 1f5d4: 080063a0 stmeqda r0, {r5, r7, r8, r9, sp, lr} + 1f5d8: e1a04000 mov r4, r0 + 1f5dc: ebf59267 bl 0xffd83f80 + 1f5e0: 0800639e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, sp, lr} + 1f5e4: e1a01005 mov r1, r5 + 1f5e8: e0953004 adds r3, r5, r4 + 1f5ec: ebf59263 bl 0xffd83f80 + 1f5f0: 080063a0 stmeqda r0, {r5, r7, r8, r9, sp, lr} + 1f5f4: e2830000 add r0, r3, #0 ; 0x0 + 1f5f8: ebf5906f bl 0xffd837bc + 1f5fc: 080063a4 stmeqda r0, {r2, r5, r7, r8, r9, sp, lr} + 1f600: e1a04000 mov r4, r0 + 1f604: ebf5925d bl 0xffd83f80 + 1f608: 080063a2 stmeqda r0, {r1, r5, r7, r8, r9, sp, lr} + 1f60c: e1b04404 movs r4, r4, lsl #8 + 1f610: ebf5925a bl 0xffd83f80 + 1f614: 080063a4 stmeqda r0, {r2, r5, r7, r8, r9, sp, lr} + 1f618: e3a00ff3 mov r0, #972 ; 0x3cc + 1f61c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f620: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f624: ebf590bb bl 0xffd83918 + 1f628: 080063a8 stmeqda r0, {r3, r5, r7, r8, r9, sp, lr} + 1f62c: e1a07000 mov r7, r0 + 1f630: ebf59252 bl 0xffd83f80 + 1f634: 080063a6 stmeqda r0, {r1, r2, r5, r7, r8, r9, sp, lr} + 1f638: e1a01005 mov r1, r5 + 1f63c: e0953007 adds r3, r5, r7 + 1f640: ebf5924e bl 0xffd83f80 + 1f644: 080063a8 stmeqda r0, {r3, r5, r7, r8, r9, sp, lr} + 1f648: e2830000 add r0, r3, #0 ; 0x0 + 1f64c: ebf5905a bl 0xffd837bc + 1f650: 080063ac stmeqda r0, {r2, r3, r5, r7, r8, r9, sp, lr} + 1f654: e1a03000 mov r3, r0 + 1f658: ebf59248 bl 0xffd83f80 + 1f65c: 080063aa stmeqda r0, {r1, r3, r5, r7, r8, r9, sp, lr} + 1f660: e1a01003 mov r1, r3 + 1f664: e1933004 orrs r3, r3, r4 + 1f668: ebf59244 bl 0xffd83f80 + 1f66c: 080063ac stmeqda r0, {r2, r3, r5, r7, r8, r9, sp, lr} + 1f670: e286000c add r0, r6, #12 ; 0xc + 1f674: e1a01003 mov r1, r3 + 1f678: ebf58fb3 bl 0xffd8354c + 1f67c: 080063ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, sp, lr} + 1f680: ebf5923e bl 0xffd83f80 + 1f684: 080063ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, sp, lr} + 1f688: e3a00e3d mov r0, #976 ; 0x3d0 + 1f68c: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f690: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f694: ebf5909f bl 0xffd83918 + 1f698: 080063b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, sp, lr} + 1f69c: e1a04000 mov r4, r0 + 1f6a0: ebf59236 bl 0xffd83f80 + 1f6a4: 080063b0 stmeqda r0, {r4, r5, r7, r8, r9, sp, lr} + 1f6a8: e1a01005 mov r1, r5 + 1f6ac: e0953004 adds r3, r5, r4 + 1f6b0: ebf59232 bl 0xffd83f80 + 1f6b4: 080063b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, sp, lr} + 1f6b8: e2830000 add r0, r3, #0 ; 0x0 + 1f6bc: ebf5903e bl 0xffd837bc + 1f6c0: 080063b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, sp, lr} + 1f6c4: e1a04000 mov r4, r0 + 1f6c8: ebf5922c bl 0xffd83f80 + 1f6cc: 080063b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, sp, lr} + 1f6d0: e1b04404 movs r4, r4, lsl #8 + 1f6d4: ebf59229 bl 0xffd83f80 + 1f6d8: 080063b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, sp, lr} + 1f6dc: e1a01007 mov r1, r7 + 1f6e0: e2977004 adds r7, r7, #4 ; 0x4 + 1f6e4: ebf59225 bl 0xffd83f80 + 1f6e8: 080063b8 stmeqda r0, {r3, r4, r5, r7, r8, r9, sp, lr} + 1f6ec: e1a01005 mov r1, r5 + 1f6f0: e0953007 adds r3, r5, r7 + 1f6f4: ebf59221 bl 0xffd83f80 + 1f6f8: 080063ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, sp, lr} + 1f6fc: e2830000 add r0, r3, #0 ; 0x0 + 1f700: ebf5902d bl 0xffd837bc + 1f704: 080063be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sp, lr} + 1f708: e1a03000 mov r3, r0 + 1f70c: ebf5921b bl 0xffd83f80 + 1f710: 080063bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, sp, lr} + 1f714: e1a01003 mov r1, r3 + 1f718: e1933004 orrs r3, r3, r4 + 1f71c: ebf59217 bl 0xffd83f80 + 1f720: 080063be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sp, lr} + 1f724: e2860010 add r0, r6, #16 ; 0x10 + 1f728: e1a01003 mov r1, r3 + 1f72c: ebf58f86 bl 0xffd8354c + 1f730: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f734: ebf59211 bl 0xffd83f80 + 1f738: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f73c: e59d9434 ldr r9, [sp, #1076] + 1f740: e3c99003 bic r9, r9, #3 ; 0x3 + 1f744: e2890004 add r0, r9, #4 ; 0x4 + 1f748: e58d0434 str r0, [sp, #1076] + 1f74c: e2890000 add r0, r9, #0 ; 0x0 + 1f750: ebf59070 bl 0xffd83918 + 1f754: 080063c4 stmeqda r0, {r2, r6, r7, r8, r9, sp, lr} + 1f758: e1a07000 mov r7, r0 + 1f75c: ebf59207 bl 0xffd83f80 + 1f760: 080063c2 stmeqda r0, {r1, r6, r7, r8, r9, sp, lr} + 1f764: e59d9434 ldr r9, [sp, #1076] + 1f768: e3c99003 bic r9, r9, #3 ; 0x3 + 1f76c: e2890004 add r0, r9, #4 ; 0x4 + 1f770: e58d0434 str r0, [sp, #1076] + 1f774: e2890000 add r0, r9, #0 ; 0x0 + 1f778: ebf59066 bl 0xffd83918 + 1f77c: 080063c6 stmeqda r0, {r1, r2, r6, r7, r8, r9, sp, lr} + 1f780: e1a03000 mov r3, r0 + 1f784: ebf591fd bl 0xffd83f80 + 1f788: 080063c4 stmeqda r0, {r2, r6, r7, r8, r9, sp, lr} + 1f78c: e1a00003 mov r0, r3 + 1f790: e28cc066 add ip, ip, #102 ; 0x66 + 1f794: eaf58e4d b 0xffd830d0 + 1f798: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f79c: 00000000 andeq r0, r0, r0 + 1f7a0: ebf591f6 bl 0xffd83f80 + 1f7a4: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f7a8: e59d9434 ldr r9, [sp, #1076] + 1f7ac: e3c99003 bic r9, r9, #3 ; 0x3 + 1f7b0: e2890004 add r0, r9, #4 ; 0x4 + 1f7b4: e58d0434 str r0, [sp, #1076] + 1f7b8: e2890000 add r0, r9, #0 ; 0x0 + 1f7bc: ebf59055 bl 0xffd83918 + 1f7c0: 080063c4 stmeqda r0, {r2, r6, r7, r8, r9, sp, lr} + 1f7c4: e1a07000 mov r7, r0 + 1f7c8: ebf591ec bl 0xffd83f80 + 1f7cc: 080063c2 stmeqda r0, {r1, r6, r7, r8, r9, sp, lr} + 1f7d0: e59d9434 ldr r9, [sp, #1076] + 1f7d4: e3c99003 bic r9, r9, #3 ; 0x3 + 1f7d8: e2890004 add r0, r9, #4 ; 0x4 + 1f7dc: e58d0434 str r0, [sp, #1076] + 1f7e0: e2890000 add r0, r9, #0 ; 0x0 + 1f7e4: ebf5904b bl 0xffd83918 + 1f7e8: 080063c6 stmeqda r0, {r1, r2, r6, r7, r8, r9, sp, lr} + 1f7ec: e1a03000 mov r3, r0 + 1f7f0: ebf591e2 bl 0xffd83f80 + 1f7f4: 080063c4 stmeqda r0, {r2, r6, r7, r8, r9, sp, lr} + 1f7f8: e1a00003 mov r0, r3 + 1f7fc: e28cc00b add ip, ip, #11 ; 0xb + 1f800: eaf58e32 b 0xffd830d0 + 1f804: 0800634e stmeqda r0, {r1, r2, r3, r6, r8, r9, sp, lr} + 1f808: 00000000 andeq r0, r0, r0 + 1f80c: ebf591db bl 0xffd83f80 + 1f810: 0800634e stmeqda r0, {r1, r2, r3, r6, r8, r9, sp, lr} + 1f814: e3a00d8e mov r0, #9088 ; 0x2380 + 1f818: e3800901 orr r0, r0, #16384 ; 0x4000 + 1f81c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f820: ebf5903c bl 0xffd83918 + 1f824: 08006352 stmeqda r0, {r1, r4, r6, r8, r9, sp, lr} + 1f828: e1a04000 mov r4, r0 + 1f82c: ebf591d3 bl 0xffd83f80 + 1f830: 08006350 stmeqda r0, {r4, r6, r8, r9, sp, lr} + 1f834: e1a01005 mov r1, r5 + 1f838: e0953004 adds r3, r5, r4 + 1f83c: ebf591cf bl 0xffd83f80 + 1f840: 08006352 stmeqda r0, {r1, r4, r6, r8, r9, sp, lr} + 1f844: e3a00fe1 mov r0, #900 ; 0x384 + 1f848: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f84c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f850: ebf59030 bl 0xffd83918 + 1f854: 08006356 stmeqda r0, {r1, r2, r4, r6, r8, r9, sp, lr} + 1f858: e1a07000 mov r7, r0 + 1f85c: ebf591c7 bl 0xffd83f80 + 1f860: 08006354 stmeqda r0, {r2, r4, r6, r8, r9, sp, lr} + 1f864: e1a01005 mov r1, r5 + 1f868: e0954007 adds r4, r5, r7 + 1f86c: ebf591c3 bl 0xffd83f80 + 1f870: 08006356 stmeqda r0, {r1, r2, r4, r6, r8, r9, sp, lr} + 1f874: e2830000 add r0, r3, #0 ; 0x0 + 1f878: ebf58fcf bl 0xffd837bc + 1f87c: 0800635a stmeqda r0, {r1, r3, r4, r6, r8, r9, sp, lr} + 1f880: e1a03000 mov r3, r0 + 1f884: ebf591bd bl 0xffd83f80 + 1f888: 08006358 stmeqda r0, {r3, r4, r6, r8, r9, sp, lr} + 1f88c: e2840000 add r0, r4, #0 ; 0x0 + 1f890: ebf58fc9 bl 0xffd837bc + 1f894: 0800635c stmeqda r0, {r2, r3, r4, r6, r8, r9, sp, lr} + 1f898: e1a04000 mov r4, r0 + 1f89c: ebf591b7 bl 0xffd83f80 + 1f8a0: 0800635a stmeqda r0, {r1, r3, r4, r6, r8, r9, sp, lr} + 1f8a4: e1530004 cmp r3, r4 + 1f8a8: ebf591b4 bl 0xffd83f80 + 1f8ac: 0800635c stmeqda r0, {r2, r3, r4, r6, r8, r9, sp, lr} + 1f8b0: e28cc020 add ip, ip, #32 ; 0x20 + 1f8b4: 2a000004 bcs 0x1f8cc + 1f8b8: e1a00fac mov r0, ip, lsr #31 + 1f8bc: e08ff100 add pc, pc, r0, lsl #2 + 1f8c0: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f8c4: ebf58da2 bl 0xffd82f54 + 1f8c8: eaffff21 b 0x1f554 + 1f8cc: ebf591ab bl 0xffd83f80 + 1f8d0: 0800635e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, sp, lr} + 1f8d4: e3a00fe2 mov r0, #904 ; 0x388 + 1f8d8: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f8dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f8e0: ebf5900c bl 0xffd83918 + 1f8e4: 08006362 stmeqda r0, {r1, r5, r6, r8, r9, sp, lr} + 1f8e8: e1a04000 mov r4, r0 + 1f8ec: ebf591a3 bl 0xffd83f80 + 1f8f0: 08006360 stmeqda r0, {r5, r6, r8, r9, sp, lr} + 1f8f4: e1a01005 mov r1, r5 + 1f8f8: e0953004 adds r3, r5, r4 + 1f8fc: ebf5919f bl 0xffd83f80 + 1f900: 08006362 stmeqda r0, {r1, r5, r6, r8, r9, sp, lr} + 1f904: e1a01007 mov r1, r7 + 1f908: e2977004 adds r7, r7, #4 ; 0x4 + 1f90c: ebf5919b bl 0xffd83f80 + 1f910: 08006364 stmeqda r0, {r2, r5, r6, r8, r9, sp, lr} + 1f914: e1a01005 mov r1, r5 + 1f918: e0954007 adds r4, r5, r7 + 1f91c: ebf59197 bl 0xffd83f80 + 1f920: 08006366 stmeqda r0, {r1, r2, r5, r6, r8, r9, sp, lr} + 1f924: e2830000 add r0, r3, #0 ; 0x0 + 1f928: ebf58fa3 bl 0xffd837bc + 1f92c: 0800636a stmeqda r0, {r1, r3, r5, r6, r8, r9, sp, lr} + 1f930: e1a03000 mov r3, r0 + 1f934: ebf59191 bl 0xffd83f80 + 1f938: 08006368 stmeqda r0, {r3, r5, r6, r8, r9, sp, lr} + 1f93c: e2840000 add r0, r4, #0 ; 0x0 + 1f940: ebf58f9d bl 0xffd837bc + 1f944: 0800636c stmeqda r0, {r2, r3, r5, r6, r8, r9, sp, lr} + 1f948: e1a04000 mov r4, r0 + 1f94c: ebf5918b bl 0xffd83f80 + 1f950: 0800636a stmeqda r0, {r1, r3, r5, r6, r8, r9, sp, lr} + 1f954: e1530004 cmp r3, r4 + 1f958: ebf59188 bl 0xffd83f80 + 1f95c: 0800636c stmeqda r0, {r2, r3, r5, r6, r8, r9, sp, lr} + 1f960: e28cc01e add ip, ip, #30 ; 0x1e + 1f964: 2a000004 bcs 0x1f97c + 1f968: e1a00fac mov r0, ip, lsr #31 + 1f96c: e08ff100 add pc, pc, r0, lsl #2 + 1f970: 08006390 stmeqda r0, {r4, r7, r8, r9, sp, lr} + 1f974: ebf58d76 bl 0xffd82f54 + 1f978: eafffef5 b 0x1f554 + 1f97c: ebf5917f bl 0xffd83f80 + 1f980: 0800636e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sp, lr} + 1f984: e2860000 add r0, r6, #0 ; 0x0 + 1f988: ebf58fb6 bl 0xffd83868 + 1f98c: 08006372 stmeqda r0, {r1, r4, r5, r6, r8, r9, sp, lr} + 1f990: e1a04000 mov r4, r0 + 1f994: ebf59179 bl 0xffd83f80 + 1f998: 08006370 stmeqda r0, {r4, r5, r6, r8, r9, sp, lr} + 1f99c: e3a00fe3 mov r0, #908 ; 0x38c + 1f9a0: e3800a06 orr r0, r0, #24576 ; 0x6000 + 1f9a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1f9a8: ebf58fda bl 0xffd83918 + 1f9ac: 08006374 stmeqda r0, {r2, r4, r5, r6, r8, r9, sp, lr} + 1f9b0: e1a03000 mov r3, r0 + 1f9b4: ebf59171 bl 0xffd83f80 + 1f9b8: 08006372 stmeqda r0, {r1, r4, r5, r6, r8, r9, sp, lr} + 1f9bc: e1a01003 mov r1, r3 + 1f9c0: e0133004 ands r3, r3, r4 + 1f9c4: ebf5916d bl 0xffd83f80 + 1f9c8: 08006374 stmeqda r0, {r2, r4, r5, r6, r8, r9, sp, lr} + 1f9cc: e2860000 add r0, r6, #0 ; 0x0 + 1f9d0: e1a01003 mov r1, r3 + 1f9d4: ebf58edc bl 0xffd8354c + 1f9d8: 08006376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sp, lr} + 1f9dc: ebf59167 bl 0xffd83f80 + 1f9e0: 08006376 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sp, lr} + 1f9e4: e28cc014 add ip, ip, #20 ; 0x14 + 1f9e8: e1a00fac mov r0, ip, lsr #31 + 1f9ec: e08ff100 add pc, pc, r0, lsl #2 + 1f9f0: 080063c0 stmeqda r0, {r6, r7, r8, r9, sp, lr} + 1f9f4: ebf58d56 bl 0xffd82f54 + 1f9f8: eaffff68 b 0x1f7a0 + 1f9fc: 08002c8a stmeqda r0, {r1, r3, r7, sl, fp, sp} + 1fa00: 00000000 andeq r0, r0, r0 + 1fa04: ebf5915d bl 0xffd83f80 + 1fa08: 08002c8a stmeqda r0, {r1, r3, r7, sl, fp, sp} + 1fa0c: ebf5915b bl 0xffd83f80 + 1fa10: 08002c8c stmeqda r0, {r2, r3, r7, sl, fp, sp} + 1fa14: e3a0008f mov r0, #143 ; 0x8f + 1fa18: e3800b0b orr r0, r0, #11264 ; 0x2c00 + 1fa1c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fa20: e58d0438 str r0, [sp, #1080] + 1fa24: e28cc006 add ip, ip, #6 ; 0x6 + 1fa28: e1a00fac mov r0, ip, lsr #31 + 1fa2c: e08ff100 add pc, pc, r0, lsl #2 + 1fa30: 08002fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, sp} + 1fa34: ebf58d46 bl 0xffd82f54 + 1fa38: ea000001 b 0x1fa44 + 1fa3c: 08002fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, sp} + 1fa40: 00000000 andeq r0, r0, r0 + 1fa44: ebf5914d bl 0xffd83f80 + 1fa48: 08002fd4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, fp, sp} + 1fa4c: e59d9434 ldr r9, [sp, #1076] + 1fa50: e3c99003 bic r9, r9, #3 ; 0x3 + 1fa54: e2499014 sub r9, r9, #20 ; 0x14 + 1fa58: e58d9434 str r9, [sp, #1076] + 1fa5c: e2890000 add r0, r9, #0 ; 0x0 + 1fa60: e1a01007 mov r1, r7 + 1fa64: ebf58ef8 bl 0xffd8364c + 1fa68: e2890004 add r0, r9, #4 ; 0x4 + 1fa6c: e1a01008 mov r1, r8 + 1fa70: ebf58ef5 bl 0xffd8364c + 1fa74: e2890008 add r0, r9, #8 ; 0x8 + 1fa78: e59d1418 ldr r1, [sp, #1048] + 1fa7c: ebf58ef2 bl 0xffd8364c + 1fa80: e289000c add r0, r9, #12 ; 0xc + 1fa84: e59d141c ldr r1, [sp, #1052] + 1fa88: ebf58eef bl 0xffd8364c + 1fa8c: e2890010 add r0, r9, #16 ; 0x10 + 1fa90: e59d1438 ldr r1, [sp, #1080] + 1fa94: ebf58eec bl 0xffd8364c + 1fa98: ebf59138 bl 0xffd83f80 + 1fa9c: 08002fd6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, sl, fp, sp} + 1faa0: e59d1428 ldr r1, [sp, #1064] + 1faa4: e1a00001 mov r0, r1 + 1faa8: e58d041c str r0, [sp, #1052] + 1faac: ebf59133 bl 0xffd83f80 + 1fab0: 08002fd8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl, fp, sp} + 1fab4: e59d1424 ldr r1, [sp, #1060] + 1fab8: e1a00001 mov r0, r1 + 1fabc: e58d0418 str r0, [sp, #1048] + 1fac0: ebf5912e bl 0xffd83f80 + 1fac4: 08002fda stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 1fac8: e59d1420 ldr r1, [sp, #1056] + 1facc: e1a08001 mov r8, r1 + 1fad0: ebf5912a bl 0xffd83f80 + 1fad4: 08002fdc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 1fad8: e59d9434 ldr r9, [sp, #1076] + 1fadc: e3c99003 bic r9, r9, #3 ; 0x3 + 1fae0: e249900c sub r9, r9, #12 ; 0xc + 1fae4: e58d9434 str r9, [sp, #1076] + 1fae8: e2890000 add r0, r9, #0 ; 0x0 + 1faec: e1a01008 mov r1, r8 + 1faf0: ebf58ed5 bl 0xffd8364c + 1faf4: e2890004 add r0, r9, #4 ; 0x4 + 1faf8: e59d1418 ldr r1, [sp, #1048] + 1fafc: ebf58ed2 bl 0xffd8364c + 1fb00: e2890008 add r0, r9, #8 ; 0x8 + 1fb04: e59d141c ldr r1, [sp, #1052] + 1fb08: ebf58eaf bl 0xffd835cc + 1fb0c: 08002fde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 1fb10: ebf5911a bl 0xffd83f80 + 1fb14: 08002fde stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl, fp, sp} + 1fb18: e59d0434 ldr r0, [sp, #1076] + 1fb1c: e2400f08 sub r0, r0, #32 ; 0x20 + 1fb20: e58d0434 str r0, [sp, #1076] + 1fb24: ebf59115 bl 0xffd83f80 + 1fb28: 08002fe0 stmeqda r0, {r5, r6, r7, r8, r9, sl, fp, sp} + 1fb2c: e3a00e27 mov r0, #624 ; 0x270 + 1fb30: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1fb34: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fb38: ebf58f76 bl 0xffd83918 + 1fb3c: 08002fe4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb40: e1a03000 mov r3, r0 + 1fb44: ebf5910d bl 0xffd83f80 + 1fb48: 08002fe2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb4c: e2830000 add r0, r3, #0 ; 0x0 + 1fb50: ebf58f19 bl 0xffd837bc + 1fb54: 08002fe6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb58: e1a04000 mov r4, r0 + 1fb5c: ebf59107 bl 0xffd83f80 + 1fb60: 08002fe4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb64: e3b03001 movs r3, #1 ; 0x1 + 1fb68: ebf59104 bl 0xffd83f80 + 1fb6c: 08002fe6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb70: e1a01003 mov r1, r3 + 1fb74: e0133004 ands r3, r3, r4 + 1fb78: ebf59100 bl 0xffd83f80 + 1fb7c: 08002fe8 stmeqda r0, {r3, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb80: e3530000 cmp r3, #0 ; 0x0 + 1fb84: ebf590fd bl 0xffd83f80 + 1fb88: 08002fea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 1fb8c: e28cc02f add ip, ip, #47 ; 0x2f + 1fb90: 1a000004 bne 0x1fba8 + 1fb94: e1a00fac mov r0, ip, lsr #31 + 1fb98: e08ff100 add pc, pc, r0, lsl #2 + 1fb9c: 08002fee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 1fba0: ebf58ceb bl 0xffd82f54 + 1fba4: ea000007 b 0x1fbc8 + 1fba8: ebf590f4 bl 0xffd83f80 + 1fbac: 08002fec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 1fbb0: e28cc003 add ip, ip, #3 ; 0x3 + 1fbb4: e1a00fac mov r0, ip, lsr #31 + 1fbb8: e08ff100 add pc, pc, r0, lsl #2 + 1fbbc: 08003458 stmeqda r0, {r3, r4, r6, sl, ip, sp} + 1fbc0: ebf58ce3 bl 0xffd82f54 + 1fbc4: ea00001d b 0x1fc40 + 1fbc8: ebf590ec bl 0xffd83f80 + 1fbcc: 08002fee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, sl, fp, sp} + 1fbd0: e3a00f9d mov r0, #628 ; 0x274 + 1fbd4: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1fbd8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fbdc: ebf58f4d bl 0xffd83918 + 1fbe0: 08002ff2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fbe4: e1a03000 mov r3, r0 + 1fbe8: ebf590e4 bl 0xffd83f80 + 1fbec: 08002ff0 stmeqda r0, {r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fbf0: e2830000 add r0, r3, #0 ; 0x0 + 1fbf4: ebf58f47 bl 0xffd83918 + 1fbf8: 08002ff4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fbfc: e1a03000 mov r3, r0 + 1fc00: ebf590de bl 0xffd83f80 + 1fc04: 08002ff2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fc08: ebf590dc bl 0xffd83f80 + 1fc0c: 08002ff4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fc10: e3a000f7 mov r0, #247 ; 0xf7 + 1fc14: e3800c2f orr r0, r0, #12032 ; 0x2f00 + 1fc18: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fc1c: e58d0438 str r0, [sp, #1080] + 1fc20: e28cc010 add ip, ip, #16 ; 0x10 + 1fc24: e1a00fac mov r0, ip, lsr #31 + 1fc28: e08ff100 add pc, pc, r0, lsl #2 + 1fc2c: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + 1fc30: ebf58cc7 bl 0xffd82f54 + 1fc34: eaffaadf b 0xa7b8 + 1fc38: 08003458 stmeqda r0, {r3, r4, r6, sl, ip, sp} + 1fc3c: 00000000 andeq r0, r0, r0 + 1fc40: ebf590ce bl 0xffd83f80 + 1fc44: 08003458 stmeqda r0, {r3, r4, r6, sl, ip, sp} + 1fc48: e59d0434 ldr r0, [sp, #1076] + 1fc4c: e2800f08 add r0, r0, #32 ; 0x20 + 1fc50: e58d0434 str r0, [sp, #1076] + 1fc54: ebf590c9 bl 0xffd83f80 + 1fc58: 0800345a stmeqda r0, {r1, r3, r4, r6, sl, ip, sp} + 1fc5c: e59d9434 ldr r9, [sp, #1076] + 1fc60: e3c99003 bic r9, r9, #3 ; 0x3 + 1fc64: e289000c add r0, r9, #12 ; 0xc + 1fc68: e58d0434 str r0, [sp, #1076] + 1fc6c: e2890000 add r0, r9, #0 ; 0x0 + 1fc70: ebf58f28 bl 0xffd83918 + 1fc74: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 1fc78: e1a06000 mov r6, r0 + 1fc7c: e2890004 add r0, r9, #4 ; 0x4 + 1fc80: ebf58f24 bl 0xffd83918 + 1fc84: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 1fc88: e1a07000 mov r7, r0 + 1fc8c: e2890008 add r0, r9, #8 ; 0x8 + 1fc90: ebf58f20 bl 0xffd83918 + 1fc94: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 1fc98: e1a08000 mov r8, r0 + 1fc9c: ebf590b7 bl 0xffd83f80 + 1fca0: 0800345c stmeqda r0, {r2, r3, r4, r6, sl, ip, sp} + 1fca4: e1a00006 mov r0, r6 + 1fca8: e58d0420 str r0, [sp, #1056] + 1fcac: ebf590b3 bl 0xffd83f80 + 1fcb0: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 1fcb4: e1a00007 mov r0, r7 + 1fcb8: e58d0424 str r0, [sp, #1060] + 1fcbc: ebf590af bl 0xffd83f80 + 1fcc0: 08003460 stmeqda r0, {r5, r6, sl, ip, sp} + 1fcc4: e1a00008 mov r0, r8 + 1fcc8: e58d0428 str r0, [sp, #1064] + 1fccc: ebf590ab bl 0xffd83f80 + 1fcd0: 08003462 stmeqda r0, {r1, r5, r6, sl, ip, sp} + 1fcd4: e59d9434 ldr r9, [sp, #1076] + 1fcd8: e3c99003 bic r9, r9, #3 ; 0x3 + 1fcdc: e2890010 add r0, r9, #16 ; 0x10 + 1fce0: e58d0434 str r0, [sp, #1076] + 1fce4: e2890000 add r0, r9, #0 ; 0x0 + 1fce8: ebf58f0a bl 0xffd83918 + 1fcec: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 1fcf0: e1a07000 mov r7, r0 + 1fcf4: e2890004 add r0, r9, #4 ; 0x4 + 1fcf8: ebf58f06 bl 0xffd83918 + 1fcfc: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 1fd00: e1a08000 mov r8, r0 + 1fd04: e2890008 add r0, r9, #8 ; 0x8 + 1fd08: ebf58f02 bl 0xffd83918 + 1fd0c: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 1fd10: e58d0418 str r0, [sp, #1048] + 1fd14: e289000c add r0, r9, #12 ; 0xc + 1fd18: ebf58efe bl 0xffd83918 + 1fd1c: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 1fd20: e58d041c str r0, [sp, #1052] + 1fd24: ebf59095 bl 0xffd83f80 + 1fd28: 08003464 stmeqda r0, {r2, r5, r6, sl, ip, sp} + 1fd2c: e59d9434 ldr r9, [sp, #1076] + 1fd30: e3c99003 bic r9, r9, #3 ; 0x3 + 1fd34: e2890004 add r0, r9, #4 ; 0x4 + 1fd38: e58d0434 str r0, [sp, #1076] + 1fd3c: e2890000 add r0, r9, #0 ; 0x0 + 1fd40: ebf58ef4 bl 0xffd83918 + 1fd44: 08003468 stmeqda r0, {r3, r5, r6, sl, ip, sp} + 1fd48: e1a03000 mov r3, r0 + 1fd4c: ebf5908b bl 0xffd83f80 + 1fd50: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 1fd54: e1a00003 mov r0, r3 + 1fd58: e28cc020 add ip, ip, #32 ; 0x20 + 1fd5c: eaf58cdb b 0xffd830d0 + 1fd60: 08002ff6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fd64: 00000000 andeq r0, r0, r0 + 1fd68: ebf59084 bl 0xffd83f80 + 1fd6c: 08002ff6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fd70: e3a00f9e mov r0, #632 ; 0x278 + 1fd74: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1fd78: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fd7c: ebf58ee5 bl 0xffd83918 + 1fd80: 08002ffa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fd84: e1a03000 mov r3, r0 + 1fd88: ebf5907c bl 0xffd83f80 + 1fd8c: 08002ff8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fd90: e2830000 add r0, r3, #0 ; 0x0 + 1fd94: ebf58edf bl 0xffd83918 + 1fd98: 08002ffc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fd9c: e1a08000 mov r8, r0 + 1fda0: ebf59076 bl 0xffd83f80 + 1fda4: 08002ffa stmeqda r0, {r1, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fda8: e3a00f9f mov r0, #636 ; 0x27c + 1fdac: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1fdb0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fdb4: ebf58ed7 bl 0xffd83918 + 1fdb8: 08002ffe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fdbc: e58d0418 str r0, [sp, #1048] + 1fdc0: ebf5906e bl 0xffd83f80 + 1fdc4: 08002ffc stmeqda r0, {r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fdc8: e3a00dca mov r0, #12928 ; 0x3280 + 1fdcc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fdd0: ebf58ed0 bl 0xffd83918 + 1fdd4: 08003000 stmeqda r0, {ip, sp} + 1fdd8: e1a03000 mov r3, r0 + 1fddc: ebf59067 bl 0xffd83f80 + 1fde0: 08002ffe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, sp} + 1fde4: e1a00003 mov r0, r3 + 1fde8: e58d0424 str r0, [sp, #1060] + 1fdec: ebf59063 bl 0xffd83f80 + 1fdf0: 08003000 stmeqda r0, {ip, sp} + 1fdf4: e2830000 add r0, r3, #0 ; 0x0 + 1fdf8: ebf58e9a bl 0xffd83868 + 1fdfc: 08003004 stmeqda r0, {r2, ip, sp} + 1fe00: e1a03000 mov r3, r0 + 1fe04: ebf5905d bl 0xffd83f80 + 1fe08: 08003002 stmeqda r0, {r1, ip, sp} + 1fe0c: e3b04080 movs r4, #128 ; 0x80 + 1fe10: ebf5905a bl 0xffd83f80 + 1fe14: 08003004 stmeqda r0, {r2, ip, sp} + 1fe18: e1b04384 movs r4, r4, lsl #7 + 1fe1c: ebf59057 bl 0xffd83f80 + 1fe20: 08003006 stmeqda r0, {r1, r2, ip, sp} + 1fe24: e1a00004 mov r0, r4 + 1fe28: e58d0420 str r0, [sp, #1056] + 1fe2c: ebf59053 bl 0xffd83f80 + 1fe30: 08003008 stmeqda r0, {r3, ip, sp} + 1fe34: e59d1420 ldr r1, [sp, #1056] + 1fe38: e0833001 add r3, r3, r1 + 1fe3c: ebf5904f bl 0xffd83f80 + 1fe40: 0800300a stmeqda r0, {r1, r3, ip, sp} + 1fe44: e59d0418 ldr r0, [sp, #1048] + 1fe48: e2800000 add r0, r0, #0 ; 0x0 + 1fe4c: ebf58eb1 bl 0xffd83918 + 1fe50: 0800300e stmeqda r0, {r1, r2, r3, ip, sp} + 1fe54: e1a04000 mov r4, r0 + 1fe58: ebf59048 bl 0xffd83f80 + 1fe5c: 0800300c stmeqda r0, {r2, r3, ip, sp} + 1fe60: ebf59046 bl 0xffd83f80 + 1fe64: 0800300e stmeqda r0, {r1, r2, r3, ip, sp} + 1fe68: e3a00011 mov r0, #17 ; 0x11 + 1fe6c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1fe70: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1fe74: e58d0438 str r0, [sp, #1080] + 1fe78: e28cc033 add ip, ip, #51 ; 0x33 + 1fe7c: e1a00fac mov r0, ip, lsr #31 + 1fe80: e08ff100 add pc, pc, r0, lsl #2 + 1fe84: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 1fe88: ebf58c31 bl 0xffd82f54 + 1fe8c: eaff93fe b 0x4e8c + 1fe90: 08003010 stmeqda r0, {r4, ip, sp} + 1fe94: 00000000 andeq r0, r0, r0 + 1fe98: ebf59038 bl 0xffd83f80 + 1fe9c: 08003010 stmeqda r0, {r4, ip, sp} + 1fea0: e3530000 cmp r3, #0 ; 0x0 + 1fea4: ebf59035 bl 0xffd83f80 + 1fea8: 08003012 stmeqda r0, {r1, r4, ip, sp} + 1feac: e28cc006 add ip, ip, #6 ; 0x6 + 1feb0: ba000004 blt 0x1fec8 + 1feb4: e1a00fac mov r0, ip, lsr #31 + 1feb8: e08ff100 add pc, pc, r0, lsl #2 + 1febc: 08003016 stmeqda r0, {r1, r2, r4, ip, sp} + 1fec0: ebf58c23 bl 0xffd82f54 + 1fec4: ea000004 b 0x1fedc + 1fec8: ebf5902c bl 0xffd83f80 + 1fecc: 08003014 stmeqda r0, {r2, r4, ip, sp} + 1fed0: e1a01003 mov r1, r3 + 1fed4: e2933003 adds r3, r3, #3 ; 0x3 + 1fed8: e28cc003 add ip, ip, #3 ; 0x3 + 1fedc: ebf59027 bl 0xffd83f80 + 1fee0: 08003016 stmeqda r0, {r1, r2, r4, ip, sp} + 1fee4: e1b03143 movs r3, r3, asr #2 + 1fee8: ebf59024 bl 0xffd83f80 + 1feec: 08003018 stmeqda r0, {r3, r4, ip, sp} + 1fef0: e59d0434 ldr r0, [sp, #1076] + 1fef4: e2800f00 add r0, r0, #0 ; 0x0 + 1fef8: e1a01003 mov r1, r3 + 1fefc: ebf58db2 bl 0xffd835cc + 1ff00: 0800301a stmeqda r0, {r1, r3, r4, ip, sp} + 1ff04: ebf5901d bl 0xffd83f80 + 1ff08: 0800301a stmeqda r0, {r1, r3, r4, ip, sp} + 1ff0c: e59d1424 ldr r1, [sp, #1060] + 1ff10: e1a05001 mov r5, r1 + 1ff14: ebf59019 bl 0xffd83f80 + 1ff18: 0800301c stmeqda r0, {r2, r3, r4, ip, sp} + 1ff1c: e2850000 add r0, r5, #0 ; 0x0 + 1ff20: ebf58e50 bl 0xffd83868 + 1ff24: 08003020 stmeqda r0, {r5, ip, sp} + 1ff28: e1a03000 mov r3, r0 + 1ff2c: ebf59013 bl 0xffd83f80 + 1ff30: 0800301e stmeqda r0, {r1, r2, r3, r4, ip, sp} + 1ff34: e59d0418 ldr r0, [sp, #1048] + 1ff38: e2800000 add r0, r0, #0 ; 0x0 + 1ff3c: ebf58e75 bl 0xffd83918 + 1ff40: 08003022 stmeqda r0, {r1, r5, ip, sp} + 1ff44: e1a04000 mov r4, r0 + 1ff48: ebf5900c bl 0xffd83f80 + 1ff4c: 08003020 stmeqda r0, {r5, ip, sp} + 1ff50: ebf5900a bl 0xffd83f80 + 1ff54: 08003022 stmeqda r0, {r1, r5, ip, sp} + 1ff58: e3a00025 mov r0, #37 ; 0x25 + 1ff5c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 1ff60: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 1ff64: e58d0438 str r0, [sp, #1080] + 1ff68: e28cc01a add ip, ip, #26 ; 0x1a + 1ff6c: e1a00fac mov r0, ip, lsr #31 + 1ff70: e08ff100 add pc, pc, r0, lsl #2 + 1ff74: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 1ff78: ebf58bf5 bl 0xffd82f54 + 1ff7c: eaff93c2 b 0x4e8c + 1ff80: 08003024 stmeqda r0, {r2, r5, ip, sp} + 1ff84: 00000000 andeq r0, r0, r0 + 1ff88: ebf58ffc bl 0xffd83f80 + 1ff8c: 08003024 stmeqda r0, {r2, r5, ip, sp} + 1ff90: e3a01000 mov r1, #0 ; 0x0 + 1ff94: e0513003 subs r3, r1, r3 + 1ff98: ebf58ff8 bl 0xffd83f80 + 1ff9c: 08003026 stmeqda r0, {r1, r2, r5, ip, sp} + 1ffa0: e3530000 cmp r3, #0 ; 0x0 + 1ffa4: ebf58ff5 bl 0xffd83f80 + 1ffa8: 08003028 stmeqda r0, {r3, r5, ip, sp} + 1ffac: e28cc009 add ip, ip, #9 ; 0x9 + 1ffb0: ba000004 blt 0x1ffc8 + 1ffb4: e1a00fac mov r0, ip, lsr #31 + 1ffb8: e08ff100 add pc, pc, r0, lsl #2 + 1ffbc: 0800302c stmeqda r0, {r2, r3, r5, ip, sp} + 1ffc0: ebf58be3 bl 0xffd82f54 + 1ffc4: ea000004 b 0x1ffdc + 1ffc8: ebf58fec bl 0xffd83f80 + 1ffcc: 0800302a stmeqda r0, {r1, r3, r5, ip, sp} + 1ffd0: e1a01003 mov r1, r3 + 1ffd4: e2933003 adds r3, r3, #3 ; 0x3 + 1ffd8: e28cc003 add ip, ip, #3 ; 0x3 + 1ffdc: ebf58fe7 bl 0xffd83f80 + 1ffe0: 0800302c stmeqda r0, {r2, r3, r5, ip, sp} + 1ffe4: e1b03143 movs r3, r3, asr #2 + 1ffe8: ebf58fe4 bl 0xffd83f80 + 1ffec: 0800302e stmeqda r0, {r1, r2, r3, r5, ip, sp} + 1fff0: e59d0434 ldr r0, [sp, #1076] + 1fff4: e2800f01 add r0, r0, #4 ; 0x4 + 1fff8: e1a01003 mov r1, r3 + 1fffc: ebf58d72 bl 0xffd835cc + 20000: 08003030 stmeqda r0, {r4, r5, ip, sp} + 20004: ebf58fdd bl 0xffd83f80 + 20008: 08003030 stmeqda r0, {r4, r5, ip, sp} + 2000c: e3a00fa1 mov r0, #644 ; 0x284 + 20010: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20014: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20018: ebf58e3e bl 0xffd83918 + 2001c: 08003034 stmeqda r0, {r2, r4, r5, ip, sp} + 20020: e58d041c str r0, [sp, #1052] + 20024: ebf58fd5 bl 0xffd83f80 + 20028: 08003032 stmeqda r0, {r1, r4, r5, ip, sp} + 2002c: e59d041c ldr r0, [sp, #1052] + 20030: e2800000 add r0, r0, #0 ; 0x0 + 20034: ebf58e0b bl 0xffd83868 + 20038: 08003036 stmeqda r0, {r1, r2, r4, r5, ip, sp} + 2003c: e1a03000 mov r3, r0 + 20040: ebf58fce bl 0xffd83f80 + 20044: 08003034 stmeqda r0, {r2, r4, r5, ip, sp} + 20048: e59d0418 ldr r0, [sp, #1048] + 2004c: e2800000 add r0, r0, #0 ; 0x0 + 20050: ebf58e30 bl 0xffd83918 + 20054: 08003038 stmeqda r0, {r3, r4, r5, ip, sp} + 20058: e1a04000 mov r4, r0 + 2005c: ebf58fc7 bl 0xffd83f80 + 20060: 08003036 stmeqda r0, {r1, r2, r4, r5, ip, sp} + 20064: ebf58fc5 bl 0xffd83f80 + 20068: 08003038 stmeqda r0, {r3, r4, r5, ip, sp} + 2006c: e3a0003b mov r0, #59 ; 0x3b + 20070: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20074: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20078: e58d0438 str r0, [sp, #1080] + 2007c: e28cc01c add ip, ip, #28 ; 0x1c + 20080: e1a00fac mov r0, ip, lsr #31 + 20084: e08ff100 add pc, pc, r0, lsl #2 + 20088: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 2008c: ebf58bb0 bl 0xffd82f54 + 20090: eaff937d b 0x4e8c + 20094: 0800303a stmeqda r0, {r1, r3, r4, r5, ip, sp} + 20098: 00000000 andeq r0, r0, r0 + 2009c: ebf58fb7 bl 0xffd83f80 + 200a0: 0800303a stmeqda r0, {r1, r3, r4, r5, ip, sp} + 200a4: e1a01003 mov r1, r3 + 200a8: e2937000 adds r7, r3, #0 ; 0x0 + 200ac: ebf58fb3 bl 0xffd83f80 + 200b0: 0800303c stmeqda r0, {r2, r3, r4, r5, ip, sp} + 200b4: e59d1424 ldr r1, [sp, #1060] + 200b8: e1a06001 mov r6, r1 + 200bc: ebf58faf bl 0xffd83f80 + 200c0: 0800303e stmeqda r0, {r1, r2, r3, r4, r5, ip, sp} + 200c4: e2860000 add r0, r6, #0 ; 0x0 + 200c8: ebf58de6 bl 0xffd83868 + 200cc: 08003042 stmeqda r0, {r1, r6, ip, sp} + 200d0: e1a03000 mov r3, r0 + 200d4: ebf58fa9 bl 0xffd83f80 + 200d8: 08003040 stmeqda r0, {r6, ip, sp} + 200dc: e59d0418 ldr r0, [sp, #1048] + 200e0: e2800000 add r0, r0, #0 ; 0x0 + 200e4: ebf58e0b bl 0xffd83918 + 200e8: 08003044 stmeqda r0, {r2, r6, ip, sp} + 200ec: e1a04000 mov r4, r0 + 200f0: ebf58fa2 bl 0xffd83f80 + 200f4: 08003042 stmeqda r0, {r1, r6, ip, sp} + 200f8: ebf58fa0 bl 0xffd83f80 + 200fc: 08003044 stmeqda r0, {r2, r6, ip, sp} + 20100: e3a00047 mov r0, #71 ; 0x47 + 20104: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20108: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2010c: e58d0438 str r0, [sp, #1080] + 20110: e28cc016 add ip, ip, #22 ; 0x16 + 20114: e1a00fac mov r0, ip, lsr #31 + 20118: e08ff100 add pc, pc, r0, lsl #2 + 2011c: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 20120: ebf58b8b bl 0xffd82f54 + 20124: eaff9358 b 0x4e8c + 20128: 08003046 stmeqda r0, {r1, r2, r6, ip, sp} + 2012c: 00000000 andeq r0, r0, r0 + 20130: ebf58f92 bl 0xffd83f80 + 20134: 08003046 stmeqda r0, {r1, r2, r6, ip, sp} + 20138: e1b04fa7 movs r4, r7, lsr #31 + 2013c: ebf58f8f bl 0xffd83f80 + 20140: 08003048 stmeqda r0, {r3, r6, ip, sp} + 20144: e1a01007 mov r1, r7 + 20148: e0977004 adds r7, r7, r4 + 2014c: ebf58f8b bl 0xffd83f80 + 20150: 0800304a stmeqda r0, {r1, r3, r6, ip, sp} + 20154: e1b070c7 movs r7, r7, asr #1 + 20158: ebf58f88 bl 0xffd83f80 + 2015c: 0800304c stmeqda r0, {r2, r3, r6, ip, sp} + 20160: e1a01007 mov r1, r7 + 20164: e0170397 muls r7, r7, r3 + 20168: ebf58f84 bl 0xffd83f80 + 2016c: 0800304e stmeqda r0, {r1, r2, r3, r6, ip, sp} + 20170: e3570000 cmp r7, #0 ; 0x0 + 20174: ebf58f81 bl 0xffd83f80 + 20178: 08003050 stmeqda r0, {r4, r6, ip, sp} + 2017c: e28cc012 add ip, ip, #18 ; 0x12 + 20180: ba000004 blt 0x20198 + 20184: e1a00fac mov r0, ip, lsr #31 + 20188: e08ff100 add pc, pc, r0, lsl #2 + 2018c: 08003056 stmeqda r0, {r1, r2, r4, r6, ip, sp} + 20190: ebf58b6f bl 0xffd82f54 + 20194: ea00000c b 0x201cc + 20198: ebf58f78 bl 0xffd83f80 + 2019c: 08003052 stmeqda r0, {r1, r4, r6, ip, sp} + 201a0: e3a00fa2 mov r0, #648 ; 0x288 + 201a4: e3800a03 orr r0, r0, #12288 ; 0x3000 + 201a8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 201ac: ebf58dd9 bl 0xffd83918 + 201b0: 08003056 stmeqda r0, {r1, r2, r4, r6, ip, sp} + 201b4: e1a03000 mov r3, r0 + 201b8: ebf58f70 bl 0xffd83f80 + 201bc: 08003054 stmeqda r0, {r2, r4, r6, ip, sp} + 201c0: e1a01007 mov r1, r7 + 201c4: e0977003 adds r7, r7, r3 + 201c8: e28cc008 add ip, ip, #8 ; 0x8 + 201cc: ebf58f6b bl 0xffd83f80 + 201d0: 08003056 stmeqda r0, {r1, r2, r4, r6, ip, sp} + 201d4: e1b078c7 movs r7, r7, asr #17 + 201d8: ebf58f68 bl 0xffd83f80 + 201dc: 08003058 stmeqda r0, {r3, r4, r6, ip, sp} + 201e0: e59d0434 ldr r0, [sp, #1076] + 201e4: e2800f02 add r0, r0, #8 ; 0x8 + 201e8: e1a01007 mov r1, r7 + 201ec: ebf58cf6 bl 0xffd835cc + 201f0: 0800305a stmeqda r0, {r1, r3, r4, r6, ip, sp} + 201f4: ebf58f61 bl 0xffd83f80 + 201f8: 0800305a stmeqda r0, {r1, r3, r4, r6, ip, sp} + 201fc: e59d041c ldr r0, [sp, #1052] + 20200: e2800000 add r0, r0, #0 ; 0x0 + 20204: ebf58d97 bl 0xffd83868 + 20208: 0800305e stmeqda r0, {r1, r2, r3, r4, r6, ip, sp} + 2020c: e1a03000 mov r3, r0 + 20210: ebf58f5a bl 0xffd83f80 + 20214: 0800305c stmeqda r0, {r2, r3, r4, r6, ip, sp} + 20218: e59d1420 ldr r1, [sp, #1056] + 2021c: e0833001 add r3, r3, r1 + 20220: ebf58f56 bl 0xffd83f80 + 20224: 0800305e stmeqda r0, {r1, r2, r3, r4, r6, ip, sp} + 20228: e59d0418 ldr r0, [sp, #1048] + 2022c: e2800000 add r0, r0, #0 ; 0x0 + 20230: ebf58db8 bl 0xffd83918 + 20234: 08003062 stmeqda r0, {r1, r5, r6, ip, sp} + 20238: e1a04000 mov r4, r0 + 2023c: ebf58f4f bl 0xffd83f80 + 20240: 08003060 stmeqda r0, {r5, r6, ip, sp} + 20244: ebf58f4d bl 0xffd83f80 + 20248: 08003062 stmeqda r0, {r1, r5, r6, ip, sp} + 2024c: e3a00065 mov r0, #101 ; 0x65 + 20250: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20254: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20258: e58d0438 str r0, [sp, #1080] + 2025c: e28cc01a add ip, ip, #26 ; 0x1a + 20260: e1a00fac mov r0, ip, lsr #31 + 20264: e08ff100 add pc, pc, r0, lsl #2 + 20268: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 2026c: ebf58b38 bl 0xffd82f54 + 20270: eaff9305 b 0x4e8c + 20274: 08003064 stmeqda r0, {r2, r5, r6, ip, sp} + 20278: 00000000 andeq r0, r0, r0 + 2027c: ebf58f3f bl 0xffd83f80 + 20280: 08003064 stmeqda r0, {r2, r5, r6, ip, sp} + 20284: e3530000 cmp r3, #0 ; 0x0 + 20288: ebf58f3c bl 0xffd83f80 + 2028c: 08003066 stmeqda r0, {r1, r2, r5, r6, ip, sp} + 20290: e28cc006 add ip, ip, #6 ; 0x6 + 20294: ba000004 blt 0x202ac + 20298: e1a00fac mov r0, ip, lsr #31 + 2029c: e08ff100 add pc, pc, r0, lsl #2 + 202a0: 0800306a stmeqda r0, {r1, r3, r5, r6, ip, sp} + 202a4: ebf58b2a bl 0xffd82f54 + 202a8: ea000004 b 0x202c0 + 202ac: ebf58f33 bl 0xffd83f80 + 202b0: 08003068 stmeqda r0, {r3, r5, r6, ip, sp} + 202b4: e1a01003 mov r1, r3 + 202b8: e2933003 adds r3, r3, #3 ; 0x3 + 202bc: e28cc003 add ip, ip, #3 ; 0x3 + 202c0: ebf58f2e bl 0xffd83f80 + 202c4: 0800306a stmeqda r0, {r1, r3, r5, r6, ip, sp} + 202c8: e1b03143 movs r3, r3, asr #2 + 202cc: ebf58f2b bl 0xffd83f80 + 202d0: 0800306c stmeqda r0, {r2, r3, r5, r6, ip, sp} + 202d4: e59d0434 ldr r0, [sp, #1076] + 202d8: e2800f03 add r0, r0, #12 ; 0xc + 202dc: e1a01003 mov r1, r3 + 202e0: ebf58cb9 bl 0xffd835cc + 202e4: 0800306e stmeqda r0, {r1, r2, r3, r5, r6, ip, sp} + 202e8: ebf58f24 bl 0xffd83f80 + 202ec: 0800306e stmeqda r0, {r1, r2, r3, r5, r6, ip, sp} + 202f0: e59d041c ldr r0, [sp, #1052] + 202f4: e2800000 add r0, r0, #0 ; 0x0 + 202f8: ebf58d5a bl 0xffd83868 + 202fc: 08003072 stmeqda r0, {r1, r4, r5, r6, ip, sp} + 20300: e1a03000 mov r3, r0 + 20304: ebf58f1d bl 0xffd83f80 + 20308: 08003070 stmeqda r0, {r4, r5, r6, ip, sp} + 2030c: e59d0418 ldr r0, [sp, #1048] + 20310: e2800000 add r0, r0, #0 ; 0x0 + 20314: ebf58d7f bl 0xffd83918 + 20318: 08003074 stmeqda r0, {r2, r4, r5, r6, ip, sp} + 2031c: e1a04000 mov r4, r0 + 20320: ebf58f16 bl 0xffd83f80 + 20324: 08003072 stmeqda r0, {r1, r4, r5, r6, ip, sp} + 20328: e28cc014 add ip, ip, #20 ; 0x14 + 2032c: ebf58f13 bl 0xffd83f80 + 20330: 08003074 stmeqda r0, {r2, r4, r5, r6, ip, sp} + 20334: e3a00077 mov r0, #119 ; 0x77 + 20338: e3800a03 orr r0, r0, #12288 ; 0x3000 + 2033c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20340: e58d0438 str r0, [sp, #1080] + 20344: e28cc003 add ip, ip, #3 ; 0x3 + 20348: e1a00fac mov r0, ip, lsr #31 + 2034c: e08ff100 add pc, pc, r0, lsl #2 + 20350: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 20354: ebf58afe bl 0xffd82f54 + 20358: eaff92cb b 0x4e8c + 2035c: 08003076 stmeqda r0, {r1, r2, r4, r5, r6, ip, sp} + 20360: 00000000 andeq r0, r0, r0 + 20364: ebf58f05 bl 0xffd83f80 + 20368: 08003076 stmeqda r0, {r1, r2, r4, r5, r6, ip, sp} + 2036c: e1a01003 mov r1, r3 + 20370: e2937000 adds r7, r3, #0 ; 0x0 + 20374: ebf58f01 bl 0xffd83f80 + 20378: 08003078 stmeqda r0, {r3, r4, r5, r6, ip, sp} + 2037c: e59d1424 ldr r1, [sp, #1060] + 20380: e1a04001 mov r4, r1 + 20384: ebf58efd bl 0xffd83f80 + 20388: 0800307a stmeqda r0, {r1, r3, r4, r5, r6, ip, sp} + 2038c: e2840000 add r0, r4, #0 ; 0x0 + 20390: ebf58d34 bl 0xffd83868 + 20394: 0800307e stmeqda r0, {r1, r2, r3, r4, r5, r6, ip, sp} + 20398: e1a03000 mov r3, r0 + 2039c: ebf58ef7 bl 0xffd83f80 + 203a0: 0800307c stmeqda r0, {r2, r3, r4, r5, r6, ip, sp} + 203a4: e59d1420 ldr r1, [sp, #1056] + 203a8: e0833001 add r3, r3, r1 + 203ac: ebf58ef3 bl 0xffd83f80 + 203b0: 0800307e stmeqda r0, {r1, r2, r3, r4, r5, r6, ip, sp} + 203b4: e59d0418 ldr r0, [sp, #1048] + 203b8: e2800000 add r0, r0, #0 ; 0x0 + 203bc: ebf58d55 bl 0xffd83918 + 203c0: 08003082 stmeqda r0, {r1, r7, ip, sp} + 203c4: e1a04000 mov r4, r0 + 203c8: ebf58eec bl 0xffd83f80 + 203cc: 08003080 stmeqda r0, {r7, ip, sp} + 203d0: ebf58eea bl 0xffd83f80 + 203d4: 08003082 stmeqda r0, {r1, r7, ip, sp} + 203d8: e3a00085 mov r0, #133 ; 0x85 + 203dc: e3800a03 orr r0, r0, #12288 ; 0x3000 + 203e0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 203e4: e58d0438 str r0, [sp, #1080] + 203e8: e28cc019 add ip, ip, #25 ; 0x19 + 203ec: e1a00fac mov r0, ip, lsr #31 + 203f0: e08ff100 add pc, pc, r0, lsl #2 + 203f4: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 203f8: ebf58ad5 bl 0xffd82f54 + 203fc: eaff92a2 b 0x4e8c + 20400: 08003084 stmeqda r0, {r2, r7, ip, sp} + 20404: 00000000 andeq r0, r0, r0 + 20408: ebf58edc bl 0xffd83f80 + 2040c: 08003084 stmeqda r0, {r2, r7, ip, sp} + 20410: e1b04fa7 movs r4, r7, lsr #31 + 20414: ebf58ed9 bl 0xffd83f80 + 20418: 08003086 stmeqda r0, {r1, r2, r7, ip, sp} + 2041c: e1a01007 mov r1, r7 + 20420: e0977004 adds r7, r7, r4 + 20424: ebf58ed5 bl 0xffd83f80 + 20428: 08003088 stmeqda r0, {r3, r7, ip, sp} + 2042c: e1b070c7 movs r7, r7, asr #1 + 20430: ebf58ed2 bl 0xffd83f80 + 20434: 0800308a stmeqda r0, {r1, r3, r7, ip, sp} + 20438: e1a01007 mov r1, r7 + 2043c: e0170397 muls r7, r7, r3 + 20440: ebf58ece bl 0xffd83f80 + 20444: 0800308c stmeqda r0, {r2, r3, r7, ip, sp} + 20448: e3570000 cmp r7, #0 ; 0x0 + 2044c: ebf58ecb bl 0xffd83f80 + 20450: 0800308e stmeqda r0, {r1, r2, r3, r7, ip, sp} + 20454: e28cc012 add ip, ip, #18 ; 0x12 + 20458: ba000004 blt 0x20470 + 2045c: e1a00fac mov r0, ip, lsr #31 + 20460: e08ff100 add pc, pc, r0, lsl #2 + 20464: 08003094 stmeqda r0, {r2, r4, r7, ip, sp} + 20468: ebf58ab9 bl 0xffd82f54 + 2046c: ea00000c b 0x204a4 + 20470: ebf58ec2 bl 0xffd83f80 + 20474: 08003090 stmeqda r0, {r4, r7, ip, sp} + 20478: e3a00fa2 mov r0, #648 ; 0x288 + 2047c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20480: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20484: ebf58d23 bl 0xffd83918 + 20488: 08003094 stmeqda r0, {r2, r4, r7, ip, sp} + 2048c: e1a05000 mov r5, r0 + 20490: ebf58eba bl 0xffd83f80 + 20494: 08003092 stmeqda r0, {r1, r4, r7, ip, sp} + 20498: e1a01007 mov r1, r7 + 2049c: e0977005 adds r7, r7, r5 + 204a0: e28cc008 add ip, ip, #8 ; 0x8 + 204a4: ebf58eb5 bl 0xffd83f80 + 204a8: 08003094 stmeqda r0, {r2, r4, r7, ip, sp} + 204ac: e1b078c7 movs r7, r7, asr #17 + 204b0: ebf58eb2 bl 0xffd83f80 + 204b4: 08003096 stmeqda r0, {r1, r2, r4, r7, ip, sp} + 204b8: e59d0434 ldr r0, [sp, #1076] + 204bc: e2800f04 add r0, r0, #16 ; 0x10 + 204c0: e1a01007 mov r1, r7 + 204c4: ebf58c40 bl 0xffd835cc + 204c8: 08003098 stmeqda r0, {r3, r4, r7, ip, sp} + 204cc: ebf58eab bl 0xffd83f80 + 204d0: 08003098 stmeqda r0, {r3, r4, r7, ip, sp} + 204d4: e59d041c ldr r0, [sp, #1052] + 204d8: e2800000 add r0, r0, #0 ; 0x0 + 204dc: ebf58ce1 bl 0xffd83868 + 204e0: 0800309c stmeqda r0, {r2, r3, r4, r7, ip, sp} + 204e4: e1a03000 mov r3, r0 + 204e8: ebf58ea4 bl 0xffd83f80 + 204ec: 0800309a stmeqda r0, {r1, r3, r4, r7, ip, sp} + 204f0: e59d1420 ldr r1, [sp, #1056] + 204f4: e0833001 add r3, r3, r1 + 204f8: ebf58ea0 bl 0xffd83f80 + 204fc: 0800309c stmeqda r0, {r2, r3, r4, r7, ip, sp} + 20500: e59d0418 ldr r0, [sp, #1048] + 20504: e2800000 add r0, r0, #0 ; 0x0 + 20508: ebf58d02 bl 0xffd83918 + 2050c: 080030a0 stmeqda r0, {r5, r7, ip, sp} + 20510: e1a04000 mov r4, r0 + 20514: ebf58e99 bl 0xffd83f80 + 20518: 0800309e stmeqda r0, {r1, r2, r3, r4, r7, ip, sp} + 2051c: ebf58e97 bl 0xffd83f80 + 20520: 080030a0 stmeqda r0, {r5, r7, ip, sp} + 20524: e3a000a3 mov r0, #163 ; 0xa3 + 20528: e3800a03 orr r0, r0, #12288 ; 0x3000 + 2052c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20530: e58d0438 str r0, [sp, #1080] + 20534: e28cc01a add ip, ip, #26 ; 0x1a + 20538: e1a00fac mov r0, ip, lsr #31 + 2053c: e08ff100 add pc, pc, r0, lsl #2 + 20540: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 20544: ebf58a82 bl 0xffd82f54 + 20548: eaff924f b 0x4e8c + 2054c: 080030a2 stmeqda r0, {r1, r5, r7, ip, sp} + 20550: 00000000 andeq r0, r0, r0 + 20554: ebf58e89 bl 0xffd83f80 + 20558: 080030a2 stmeqda r0, {r1, r5, r7, ip, sp} + 2055c: e1a01003 mov r1, r3 + 20560: e2937000 adds r7, r3, #0 ; 0x0 + 20564: ebf58e85 bl 0xffd83f80 + 20568: 080030a4 stmeqda r0, {r2, r5, r7, ip, sp} + 2056c: e59d1424 ldr r1, [sp, #1060] + 20570: e1a06001 mov r6, r1 + 20574: ebf58e81 bl 0xffd83f80 + 20578: 080030a6 stmeqda r0, {r1, r2, r5, r7, ip, sp} + 2057c: e2860000 add r0, r6, #0 ; 0x0 + 20580: ebf58cb8 bl 0xffd83868 + 20584: 080030aa stmeqda r0, {r1, r3, r5, r7, ip, sp} + 20588: e1a03000 mov r3, r0 + 2058c: ebf58e7b bl 0xffd83f80 + 20590: 080030a8 stmeqda r0, {r3, r5, r7, ip, sp} + 20594: e59d0418 ldr r0, [sp, #1048] + 20598: e2800000 add r0, r0, #0 ; 0x0 + 2059c: ebf58cdd bl 0xffd83918 + 205a0: 080030ac stmeqda r0, {r2, r3, r5, r7, ip, sp} + 205a4: e1a04000 mov r4, r0 + 205a8: ebf58e74 bl 0xffd83f80 + 205ac: 080030aa stmeqda r0, {r1, r3, r5, r7, ip, sp} + 205b0: ebf58e72 bl 0xffd83f80 + 205b4: 080030ac stmeqda r0, {r2, r3, r5, r7, ip, sp} + 205b8: e3a000af mov r0, #175 ; 0xaf + 205bc: e3800a03 orr r0, r0, #12288 ; 0x3000 + 205c0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 205c4: e58d0438 str r0, [sp, #1080] + 205c8: e28cc016 add ip, ip, #22 ; 0x16 + 205cc: e1a00fac mov r0, ip, lsr #31 + 205d0: e08ff100 add pc, pc, r0, lsl #2 + 205d4: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 205d8: ebf58a5d bl 0xffd82f54 + 205dc: eaff922a b 0x4e8c + 205e0: 080030ae stmeqda r0, {r1, r2, r3, r5, r7, ip, sp} + 205e4: 00000000 andeq r0, r0, r0 + 205e8: ebf58e64 bl 0xffd83f80 + 205ec: 080030ae stmeqda r0, {r1, r2, r3, r5, r7, ip, sp} + 205f0: e1b04fa7 movs r4, r7, lsr #31 + 205f4: ebf58e61 bl 0xffd83f80 + 205f8: 080030b0 stmeqda r0, {r4, r5, r7, ip, sp} + 205fc: e1a01007 mov r1, r7 + 20600: e0977004 adds r7, r7, r4 + 20604: ebf58e5d bl 0xffd83f80 + 20608: 080030b2 stmeqda r0, {r1, r4, r5, r7, ip, sp} + 2060c: e1b070c7 movs r7, r7, asr #1 + 20610: ebf58e5a bl 0xffd83f80 + 20614: 080030b4 stmeqda r0, {r2, r4, r5, r7, ip, sp} + 20618: e1a01007 mov r1, r7 + 2061c: e0170397 muls r7, r7, r3 + 20620: ebf58e56 bl 0xffd83f80 + 20624: 080030b6 stmeqda r0, {r1, r2, r4, r5, r7, ip, sp} + 20628: e3570000 cmp r7, #0 ; 0x0 + 2062c: ebf58e53 bl 0xffd83f80 + 20630: 080030b8 stmeqda r0, {r3, r4, r5, r7, ip, sp} + 20634: e28cc012 add ip, ip, #18 ; 0x12 + 20638: ba000004 blt 0x20650 + 2063c: e1a00fac mov r0, ip, lsr #31 + 20640: e08ff100 add pc, pc, r0, lsl #2 + 20644: 080030be stmeqda r0, {r1, r2, r3, r4, r5, r7, ip, sp} + 20648: ebf58a41 bl 0xffd82f54 + 2064c: ea00000c b 0x20684 + 20650: ebf58e4a bl 0xffd83f80 + 20654: 080030ba stmeqda r0, {r1, r3, r4, r5, r7, ip, sp} + 20658: e3a00fa2 mov r0, #648 ; 0x288 + 2065c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20660: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20664: ebf58cab bl 0xffd83918 + 20668: 080030be stmeqda r0, {r1, r2, r3, r4, r5, r7, ip, sp} + 2066c: e1a03000 mov r3, r0 + 20670: ebf58e42 bl 0xffd83f80 + 20674: 080030bc stmeqda r0, {r2, r3, r4, r5, r7, ip, sp} + 20678: e1a01007 mov r1, r7 + 2067c: e0977003 adds r7, r7, r3 + 20680: e28cc008 add ip, ip, #8 ; 0x8 + 20684: ebf58e3d bl 0xffd83f80 + 20688: 080030be stmeqda r0, {r1, r2, r3, r4, r5, r7, ip, sp} + 2068c: e1b078c7 movs r7, r7, asr #17 + 20690: ebf58e3a bl 0xffd83f80 + 20694: 080030c0 stmeqda r0, {r6, r7, ip, sp} + 20698: e59d0434 ldr r0, [sp, #1076] + 2069c: e2800f05 add r0, r0, #20 ; 0x14 + 206a0: e1a01007 mov r1, r7 + 206a4: ebf58bc8 bl 0xffd835cc + 206a8: 080030c2 stmeqda r0, {r1, r6, r7, ip, sp} + 206ac: ebf58e33 bl 0xffd83f80 + 206b0: 080030c2 stmeqda r0, {r1, r6, r7, ip, sp} + 206b4: e59d041c ldr r0, [sp, #1052] + 206b8: e2800000 add r0, r0, #0 ; 0x0 + 206bc: ebf58c69 bl 0xffd83868 + 206c0: 080030c6 stmeqda r0, {r1, r2, r6, r7, ip, sp} + 206c4: e1a03000 mov r3, r0 + 206c8: ebf58e2c bl 0xffd83f80 + 206cc: 080030c4 stmeqda r0, {r2, r6, r7, ip, sp} + 206d0: e59d0418 ldr r0, [sp, #1048] + 206d4: e2800000 add r0, r0, #0 ; 0x0 + 206d8: ebf58c8e bl 0xffd83918 + 206dc: 080030c8 stmeqda r0, {r3, r6, r7, ip, sp} + 206e0: e1a04000 mov r4, r0 + 206e4: ebf58e25 bl 0xffd83f80 + 206e8: 080030c6 stmeqda r0, {r1, r2, r6, r7, ip, sp} + 206ec: ebf58e23 bl 0xffd83f80 + 206f0: 080030c8 stmeqda r0, {r3, r6, r7, ip, sp} + 206f4: e3a000cb mov r0, #203 ; 0xcb + 206f8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 206fc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20700: e58d0438 str r0, [sp, #1080] + 20704: e28cc017 add ip, ip, #23 ; 0x17 + 20708: e1a00fac mov r0, ip, lsr #31 + 2070c: e08ff100 add pc, pc, r0, lsl #2 + 20710: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 20714: ebf58a0e bl 0xffd82f54 + 20718: eaff91db b 0x4e8c + 2071c: 080030ca stmeqda r0, {r1, r3, r6, r7, ip, sp} + 20720: 00000000 andeq r0, r0, r0 + 20724: ebf58e15 bl 0xffd83f80 + 20728: 080030ca stmeqda r0, {r1, r3, r6, r7, ip, sp} + 2072c: e3a01000 mov r1, #0 ; 0x0 + 20730: e0513003 subs r3, r1, r3 + 20734: ebf58e11 bl 0xffd83f80 + 20738: 080030cc stmeqda r0, {r2, r3, r6, r7, ip, sp} + 2073c: e3530000 cmp r3, #0 ; 0x0 + 20740: ebf58e0e bl 0xffd83f80 + 20744: 080030ce stmeqda r0, {r1, r2, r3, r6, r7, ip, sp} + 20748: e28cc009 add ip, ip, #9 ; 0x9 + 2074c: ba000004 blt 0x20764 + 20750: e1a00fac mov r0, ip, lsr #31 + 20754: e08ff100 add pc, pc, r0, lsl #2 + 20758: 080030d2 stmeqda r0, {r1, r4, r6, r7, ip, sp} + 2075c: ebf589fc bl 0xffd82f54 + 20760: ea000004 b 0x20778 + 20764: ebf58e05 bl 0xffd83f80 + 20768: 080030d0 stmeqda r0, {r4, r6, r7, ip, sp} + 2076c: e1a01003 mov r1, r3 + 20770: e2933003 adds r3, r3, #3 ; 0x3 + 20774: e28cc003 add ip, ip, #3 ; 0x3 + 20778: ebf58e00 bl 0xffd83f80 + 2077c: 080030d2 stmeqda r0, {r1, r4, r6, r7, ip, sp} + 20780: e1b03143 movs r3, r3, asr #2 + 20784: ebf58dfd bl 0xffd83f80 + 20788: 080030d4 stmeqda r0, {r2, r4, r6, r7, ip, sp} + 2078c: e59d0434 ldr r0, [sp, #1076] + 20790: e2800f06 add r0, r0, #24 ; 0x18 + 20794: e1a01003 mov r1, r3 + 20798: ebf58b8b bl 0xffd835cc + 2079c: 080030d6 stmeqda r0, {r1, r2, r4, r6, r7, ip, sp} + 207a0: ebf58df6 bl 0xffd83f80 + 207a4: 080030d6 stmeqda r0, {r1, r2, r4, r6, r7, ip, sp} + 207a8: e59d041c ldr r0, [sp, #1052] + 207ac: e2800000 add r0, r0, #0 ; 0x0 + 207b0: ebf58c2c bl 0xffd83868 + 207b4: 080030da stmeqda r0, {r1, r3, r4, r6, r7, ip, sp} + 207b8: e1a03000 mov r3, r0 + 207bc: ebf58def bl 0xffd83f80 + 207c0: 080030d8 stmeqda r0, {r3, r4, r6, r7, ip, sp} + 207c4: e59d1420 ldr r1, [sp, #1056] + 207c8: e0833001 add r3, r3, r1 + 207cc: ebf58deb bl 0xffd83f80 + 207d0: 080030da stmeqda r0, {r1, r3, r4, r6, r7, ip, sp} + 207d4: e59d0418 ldr r0, [sp, #1048] + 207d8: e2800000 add r0, r0, #0 ; 0x0 + 207dc: ebf58c4d bl 0xffd83918 + 207e0: 080030de stmeqda r0, {r1, r2, r3, r4, r6, r7, ip, sp} + 207e4: e1a04000 mov r4, r0 + 207e8: ebf58de4 bl 0xffd83f80 + 207ec: 080030dc stmeqda r0, {r2, r3, r4, r6, r7, ip, sp} + 207f0: ebf58de2 bl 0xffd83f80 + 207f4: 080030de stmeqda r0, {r1, r2, r3, r4, r6, r7, ip, sp} + 207f8: e3a000e1 mov r0, #225 ; 0xe1 + 207fc: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20800: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20804: e58d0438 str r0, [sp, #1080] + 20808: e28cc01a add ip, ip, #26 ; 0x1a + 2080c: e1a00fac mov r0, ip, lsr #31 + 20810: e08ff100 add pc, pc, r0, lsl #2 + 20814: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 20818: ebf589cd bl 0xffd82f54 + 2081c: eaff919a b 0x4e8c + 20820: 080030e0 stmeqda r0, {r5, r6, r7, ip, sp} + 20824: 00000000 andeq r0, r0, r0 + 20828: ebf58dd4 bl 0xffd83f80 + 2082c: 080030e0 stmeqda r0, {r5, r6, r7, ip, sp} + 20830: e1a01003 mov r1, r3 + 20834: e2937000 adds r7, r3, #0 ; 0x0 + 20838: ebf58dd0 bl 0xffd83f80 + 2083c: 080030e2 stmeqda r0, {r1, r5, r6, r7, ip, sp} + 20840: e59d1424 ldr r1, [sp, #1060] + 20844: e1a04001 mov r4, r1 + 20848: ebf58dcc bl 0xffd83f80 + 2084c: 080030e4 stmeqda r0, {r2, r5, r6, r7, ip, sp} + 20850: e2840000 add r0, r4, #0 ; 0x0 + 20854: ebf58c03 bl 0xffd83868 + 20858: 080030e8 stmeqda r0, {r3, r5, r6, r7, ip, sp} + 2085c: e1a03000 mov r3, r0 + 20860: ebf58dc6 bl 0xffd83f80 + 20864: 080030e6 stmeqda r0, {r1, r2, r5, r6, r7, ip, sp} + 20868: e59d1420 ldr r1, [sp, #1056] + 2086c: e0833001 add r3, r3, r1 + 20870: ebf58dc2 bl 0xffd83f80 + 20874: 080030e8 stmeqda r0, {r3, r5, r6, r7, ip, sp} + 20878: e59d0418 ldr r0, [sp, #1048] + 2087c: e2800000 add r0, r0, #0 ; 0x0 + 20880: ebf58c24 bl 0xffd83918 + 20884: 080030ec stmeqda r0, {r2, r3, r5, r6, r7, ip, sp} + 20888: e1a04000 mov r4, r0 + 2088c: ebf58dbb bl 0xffd83f80 + 20890: 080030ea stmeqda r0, {r1, r3, r5, r6, r7, ip, sp} + 20894: ebf58db9 bl 0xffd83f80 + 20898: 080030ec stmeqda r0, {r2, r3, r5, r6, r7, ip, sp} + 2089c: e3a000ef mov r0, #239 ; 0xef + 208a0: e3800a03 orr r0, r0, #12288 ; 0x3000 + 208a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 208a8: e58d0438 str r0, [sp, #1080] + 208ac: e28cc019 add ip, ip, #25 ; 0x19 + 208b0: e1a00fac mov r0, ip, lsr #31 + 208b4: e08ff100 add pc, pc, r0, lsl #2 + 208b8: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 208bc: ebf589a4 bl 0xffd82f54 + 208c0: eaff9171 b 0x4e8c + 208c4: 080030ee stmeqda r0, {r1, r2, r3, r5, r6, r7, ip, sp} + 208c8: 00000000 andeq r0, r0, r0 + 208cc: ebf58dab bl 0xffd83f80 + 208d0: 080030ee stmeqda r0, {r1, r2, r3, r5, r6, r7, ip, sp} + 208d4: e1b04fa7 movs r4, r7, lsr #31 + 208d8: ebf58da8 bl 0xffd83f80 + 208dc: 080030f0 stmeqda r0, {r4, r5, r6, r7, ip, sp} + 208e0: e1a01007 mov r1, r7 + 208e4: e0977004 adds r7, r7, r4 + 208e8: ebf58da4 bl 0xffd83f80 + 208ec: 080030f2 stmeqda r0, {r1, r4, r5, r6, r7, ip, sp} + 208f0: e1b070c7 movs r7, r7, asr #1 + 208f4: ebf58da1 bl 0xffd83f80 + 208f8: 080030f4 stmeqda r0, {r2, r4, r5, r6, r7, ip, sp} + 208fc: e1a01007 mov r1, r7 + 20900: e0170397 muls r7, r7, r3 + 20904: ebf58d9d bl 0xffd83f80 + 20908: 080030f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, ip, sp} + 2090c: e3570000 cmp r7, #0 ; 0x0 + 20910: ebf58d9a bl 0xffd83f80 + 20914: 080030f8 stmeqda r0, {r3, r4, r5, r6, r7, ip, sp} + 20918: e28cc012 add ip, ip, #18 ; 0x12 + 2091c: ba000004 blt 0x20934 + 20920: e1a00fac mov r0, ip, lsr #31 + 20924: e08ff100 add pc, pc, r0, lsl #2 + 20928: 080030fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, ip, sp} + 2092c: ebf58988 bl 0xffd82f54 + 20930: ea00000c b 0x20968 + 20934: ebf58d91 bl 0xffd83f80 + 20938: 080030fa stmeqda r0, {r1, r3, r4, r5, r6, r7, ip, sp} + 2093c: e3a00fa2 mov r0, #648 ; 0x288 + 20940: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20944: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20948: ebf58bf2 bl 0xffd83918 + 2094c: 080030fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, ip, sp} + 20950: e1a05000 mov r5, r0 + 20954: ebf58d89 bl 0xffd83f80 + 20958: 080030fc stmeqda r0, {r2, r3, r4, r5, r6, r7, ip, sp} + 2095c: e1a01007 mov r1, r7 + 20960: e0977005 adds r7, r7, r5 + 20964: e28cc008 add ip, ip, #8 ; 0x8 + 20968: ebf58d84 bl 0xffd83f80 + 2096c: 080030fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, ip, sp} + 20970: e1b078c7 movs r7, r7, asr #17 + 20974: ebf58d81 bl 0xffd83f80 + 20978: 08003100 stmeqda r0, {r8, ip, sp} + 2097c: e59d0434 ldr r0, [sp, #1076] + 20980: e2800f07 add r0, r0, #28 ; 0x1c + 20984: e1a01007 mov r1, r7 + 20988: ebf58b0f bl 0xffd835cc + 2098c: 08003102 stmeqda r0, {r1, r8, ip, sp} + 20990: ebf58d7a bl 0xffd83f80 + 20994: 08003102 stmeqda r0, {r1, r8, ip, sp} + 20998: e3b06000 movs r6, #0 ; 0x0 + 2099c: ebf58d77 bl 0xffd83f80 + 209a0: 08003104 stmeqda r0, {r2, r8, ip, sp} + 209a4: e1a00006 mov r0, r6 + 209a8: e58d0420 str r0, [sp, #1056] + 209ac: ebf58d73 bl 0xffd83f80 + 209b0: 08003106 stmeqda r0, {r1, r2, r8, ip, sp} + 209b4: e3a00fa3 mov r0, #652 ; 0x28c + 209b8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 209bc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 209c0: ebf58bd4 bl 0xffd83918 + 209c4: 0800310a stmeqda r0, {r1, r3, r8, ip, sp} + 209c8: e1a03000 mov r3, r0 + 209cc: ebf58d6b bl 0xffd83f80 + 209d0: 08003108 stmeqda r0, {r3, r8, ip, sp} + 209d4: e2830000 add r0, r3, #0 ; 0x0 + 209d8: ebf58bce bl 0xffd83918 + 209dc: 0800310c stmeqda r0, {r2, r3, r8, ip, sp} + 209e0: e1a03000 mov r3, r0 + 209e4: ebf58d65 bl 0xffd83f80 + 209e8: 0800310a stmeqda r0, {r1, r3, r8, ip, sp} + 209ec: e59d0420 ldr r0, [sp, #1056] + 209f0: e1500003 cmp r0, r3 + 209f4: ebf58d61 bl 0xffd83f80 + 209f8: 0800310c stmeqda r0, {r2, r3, r8, ip, sp} + 209fc: e28cc01d add ip, ip, #29 ; 0x1d + 20a00: 2a000004 bcs 0x20a18 + 20a04: e1a00fac mov r0, ip, lsr #31 + 20a08: e08ff100 add pc, pc, r0, lsl #2 + 20a0c: 08003110 stmeqda r0, {r4, r8, ip, sp} + 20a10: ebf5894f bl 0xffd82f54 + 20a14: ea000007 b 0x20a38 + 20a18: ebf58d58 bl 0xffd83f80 + 20a1c: 0800310e stmeqda r0, {r1, r2, r3, r8, ip, sp} + 20a20: e28cc003 add ip, ip, #3 ; 0x3 + 20a24: e1a00fac mov r0, ip, lsr #31 + 20a28: e08ff100 add pc, pc, r0, lsl #2 + 20a2c: 08003396 stmeqda r0, {r1, r2, r4, r7, r8, r9, ip, sp} + 20a30: ebf58947 bl 0xffd82f54 + 20a34: ea000224 b 0x212cc + 20a38: ebf58d50 bl 0xffd83f80 + 20a3c: 08003110 stmeqda r0, {r4, r8, ip, sp} + 20a40: e3a00e29 mov r0, #656 ; 0x290 + 20a44: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20a48: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20a4c: ebf58bb1 bl 0xffd83918 + 20a50: 08003114 stmeqda r0, {r2, r4, r8, ip, sp} + 20a54: e1a07000 mov r7, r0 + 20a58: ebf58d48 bl 0xffd83f80 + 20a5c: 08003112 stmeqda r0, {r1, r4, r8, ip, sp} + 20a60: e1a00007 mov r0, r7 + 20a64: e58d0428 str r0, [sp, #1064] + 20a68: ebf58d44 bl 0xffd83f80 + 20a6c: 08003114 stmeqda r0, {r2, r4, r8, ip, sp} + 20a70: e1a00006 mov r0, r6 + 20a74: e58d0424 str r0, [sp, #1060] + 20a78: ebf58d40 bl 0xffd83f80 + 20a7c: 08003116 stmeqda r0, {r1, r2, r4, r8, ip, sp} + 20a80: e1a01008 mov r1, r8 + 20a84: e2983000 adds r3, r8, #0 ; 0x0 + 20a88: ebf58d3c bl 0xffd83f80 + 20a8c: 08003118 stmeqda r0, {r3, r4, r8, ip, sp} + 20a90: e1a01003 mov r1, r3 + 20a94: e293302a adds r3, r3, #42 ; 0x2a + 20a98: ebf58d38 bl 0xffd83f80 + 20a9c: 0800311a stmeqda r0, {r1, r3, r4, r8, ip, sp} + 20aa0: e2830000 add r0, r3, #0 ; 0x0 + 20aa4: ebf58b44 bl 0xffd837bc + 20aa8: 0800311e stmeqda r0, {r1, r2, r3, r4, r8, ip, sp} + 20aac: e1a04000 mov r4, r0 + 20ab0: ebf58d32 bl 0xffd83f80 + 20ab4: 0800311c stmeqda r0, {r2, r3, r4, r8, ip, sp} + 20ab8: e3b030c0 movs r3, #192 ; 0xc0 + 20abc: ebf58d2f bl 0xffd83f80 + 20ac0: 0800311e stmeqda r0, {r1, r2, r3, r4, r8, ip, sp} + 20ac4: e1a01003 mov r1, r3 + 20ac8: e0133004 ands r3, r3, r4 + 20acc: ebf58d2b bl 0xffd83f80 + 20ad0: 08003120 stmeqda r0, {r5, r8, ip, sp} + 20ad4: e35300c0 cmp r3, #192 ; 0xc0 + 20ad8: ebf58d28 bl 0xffd83f80 + 20adc: 08003122 stmeqda r0, {r1, r5, r8, ip, sp} + 20ae0: e28cc022 add ip, ip, #34 ; 0x22 + 20ae4: 1a000004 bne 0x20afc + 20ae8: e1a00fac mov r0, ip, lsr #31 + 20aec: e08ff100 add pc, pc, r0, lsl #2 + 20af0: 08003126 stmeqda r0, {r1, r2, r5, r8, ip, sp} + 20af4: ebf58916 bl 0xffd82f54 + 20af8: ea000007 b 0x20b1c + 20afc: ebf58d1f bl 0xffd83f80 + 20b00: 08003124 stmeqda r0, {r2, r5, r8, ip, sp} + 20b04: e28cc003 add ip, ip, #3 ; 0x3 + 20b08: e1a00fac mov r0, ip, lsr #31 + 20b0c: e08ff100 add pc, pc, r0, lsl #2 + 20b10: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 20b14: ebf5890e bl 0xffd82f54 + 20b18: ea000209 b 0x21344 + 20b1c: ebf58d17 bl 0xffd83f80 + 20b20: 08003126 stmeqda r0, {r1, r2, r5, r8, ip, sp} + 20b24: e3b03020 movs r3, #32 ; 0x20 + 20b28: ebf58d14 bl 0xffd83f80 + 20b2c: 08003128 stmeqda r0, {r3, r5, r8, ip, sp} + 20b30: e1a01003 mov r1, r3 + 20b34: e0133004 ands r3, r3, r4 + 20b38: ebf58d10 bl 0xffd83f80 + 20b3c: 0800312a stmeqda r0, {r1, r3, r5, r8, ip, sp} + 20b40: e3530000 cmp r3, #0 ; 0x0 + 20b44: ebf58d0d bl 0xffd83f80 + 20b48: 0800312c stmeqda r0, {r2, r3, r5, r8, ip, sp} + 20b4c: e28cc00c add ip, ip, #12 ; 0xc + 20b50: 0a000004 beq 0x20b68 + 20b54: e1a00fac mov r0, ip, lsr #31 + 20b58: e08ff100 add pc, pc, r0, lsl #2 + 20b5c: 08003130 stmeqda r0, {r4, r5, r8, ip, sp} + 20b60: ebf588fb bl 0xffd82f54 + 20b64: ea000007 b 0x20b88 + 20b68: ebf58d04 bl 0xffd83f80 + 20b6c: 0800312e stmeqda r0, {r1, r2, r3, r5, r8, ip, sp} + 20b70: e28cc003 add ip, ip, #3 ; 0x3 + 20b74: e1a00fac mov r0, ip, lsr #31 + 20b78: e08ff100 add pc, pc, r0, lsl #2 + 20b7c: 080032b4 stmeqda r0, {r2, r4, r5, r7, r9, ip, sp} + 20b80: ebf588f3 bl 0xffd82f54 + 20b84: ea00045c b 0x21cfc + 20b88: ebf58cfc bl 0xffd83f80 + 20b8c: 08003130 stmeqda r0, {r4, r5, r8, ip, sp} + 20b90: e3a00fa5 mov r0, #660 ; 0x294 + 20b94: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20b98: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20b9c: ebf58b5d bl 0xffd83918 + 20ba0: 08003134 stmeqda r0, {r2, r4, r5, r8, ip, sp} + 20ba4: e1a03000 mov r3, r0 + 20ba8: ebf58cf4 bl 0xffd83f80 + 20bac: 08003132 stmeqda r0, {r1, r4, r5, r8, ip, sp} + 20bb0: e2880014 add r0, r8, #20 ; 0x14 + 20bb4: ebf58b57 bl 0xffd83918 + 20bb8: 08003136 stmeqda r0, {r1, r2, r4, r5, r8, ip, sp} + 20bbc: e1a04000 mov r4, r0 + 20bc0: ebf58cee bl 0xffd83f80 + 20bc4: 08003134 stmeqda r0, {r2, r4, r5, r8, ip, sp} + 20bc8: e2830000 add r0, r3, #0 ; 0x0 + 20bcc: ebf58b51 bl 0xffd83918 + 20bd0: 08003138 stmeqda r0, {r3, r4, r5, r8, ip, sp} + 20bd4: e1a03000 mov r3, r0 + 20bd8: ebf58ce8 bl 0xffd83f80 + 20bdc: 08003136 stmeqda r0, {r1, r2, r4, r5, r8, ip, sp} + 20be0: e1a01004 mov r1, r4 + 20be4: e0543003 subs r3, r4, r3 + 20be8: ebf58ce4 bl 0xffd83f80 + 20bec: 08003138 stmeqda r0, {r3, r4, r5, r8, ip, sp} + 20bf0: e3530000 cmp r3, #0 ; 0x0 + 20bf4: ebf58ce1 bl 0xffd83f80 + 20bf8: 0800313a stmeqda r0, {r1, r3, r4, r5, r8, ip, sp} + 20bfc: e28cc018 add ip, ip, #24 ; 0x18 + 20c00: ba000004 blt 0x20c18 + 20c04: e1a00fac mov r0, ip, lsr #31 + 20c08: e08ff100 add pc, pc, r0, lsl #2 + 20c0c: 08003140 stmeqda r0, {r6, r8, ip, sp} + 20c10: ebf588cf bl 0xffd82f54 + 20c14: ea00000d b 0x20c50 + 20c18: ebf58cd8 bl 0xffd83f80 + 20c1c: 0800313c stmeqda r0, {r2, r3, r4, r5, r8, ip, sp} + 20c20: e3a00fa6 mov r0, #664 ; 0x298 + 20c24: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20c28: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20c2c: ebf58b39 bl 0xffd83918 + 20c30: 08003140 stmeqda r0, {r6, r8, ip, sp} + 20c34: e58d0418 str r0, [sp, #1048] + 20c38: ebf58cd0 bl 0xffd83f80 + 20c3c: 0800313e stmeqda r0, {r1, r2, r3, r4, r5, r8, ip, sp} + 20c40: e1a01003 mov r1, r3 + 20c44: e59d0418 ldr r0, [sp, #1048] + 20c48: e0933000 adds r3, r3, r0 + 20c4c: e28cc008 add ip, ip, #8 ; 0x8 + 20c50: ebf58cca bl 0xffd83f80 + 20c54: 08003140 stmeqda r0, {r6, r8, ip, sp} + 20c58: e1b07843 movs r7, r3, asr #16 + 20c5c: ebf58cc7 bl 0xffd83f80 + 20c60: 08003142 stmeqda r0, {r1, r6, r8, ip, sp} + 20c64: e3a00fa7 mov r0, #668 ; 0x29c + 20c68: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20c6c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20c70: ebf58b28 bl 0xffd83918 + 20c74: 08003146 stmeqda r0, {r1, r2, r6, r8, ip, sp} + 20c78: e1a03000 mov r3, r0 + 20c7c: ebf58cbf bl 0xffd83f80 + 20c80: 08003144 stmeqda r0, {r2, r6, r8, ip, sp} + 20c84: e2880018 add r0, r8, #24 ; 0x18 + 20c88: ebf58b22 bl 0xffd83918 + 20c8c: 08003148 stmeqda r0, {r3, r6, r8, ip, sp} + 20c90: e1a04000 mov r4, r0 + 20c94: ebf58cb9 bl 0xffd83f80 + 20c98: 08003146 stmeqda r0, {r1, r2, r6, r8, ip, sp} + 20c9c: e2830000 add r0, r3, #0 ; 0x0 + 20ca0: ebf58b1c bl 0xffd83918 + 20ca4: 0800314a stmeqda r0, {r1, r3, r6, r8, ip, sp} + 20ca8: e1a03000 mov r3, r0 + 20cac: ebf58cb3 bl 0xffd83f80 + 20cb0: 08003148 stmeqda r0, {r3, r6, r8, ip, sp} + 20cb4: e1a01004 mov r1, r4 + 20cb8: e0544003 subs r4, r4, r3 + 20cbc: ebf58caf bl 0xffd83f80 + 20cc0: 0800314a stmeqda r0, {r1, r3, r6, r8, ip, sp} + 20cc4: e3540000 cmp r4, #0 ; 0x0 + 20cc8: ebf58cac bl 0xffd83f80 + 20ccc: 0800314c stmeqda r0, {r2, r3, r6, r8, ip, sp} + 20cd0: e28cc01b add ip, ip, #27 ; 0x1b + 20cd4: ba000004 blt 0x20cec + 20cd8: e1a00fac mov r0, ip, lsr #31 + 20cdc: e08ff100 add pc, pc, r0, lsl #2 + 20ce0: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 20ce4: ebf5889a bl 0xffd82f54 + 20ce8: ea00000c b 0x20d20 + 20cec: ebf58ca3 bl 0xffd83f80 + 20cf0: 0800314e stmeqda r0, {r1, r2, r3, r6, r8, ip, sp} + 20cf4: e3a00fa6 mov r0, #664 ; 0x298 + 20cf8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20cfc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20d00: ebf58b04 bl 0xffd83918 + 20d04: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 20d08: e1a03000 mov r3, r0 + 20d0c: ebf58c9b bl 0xffd83f80 + 20d10: 08003150 stmeqda r0, {r4, r6, r8, ip, sp} + 20d14: e1a01004 mov r1, r4 + 20d18: e0944003 adds r4, r4, r3 + 20d1c: e28cc008 add ip, ip, #8 ; 0x8 + 20d20: ebf58c96 bl 0xffd83f80 + 20d24: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 20d28: e1b06844 movs r6, r4, asr #16 + 20d2c: ebf58c93 bl 0xffd83f80 + 20d30: 08003154 stmeqda r0, {r2, r4, r6, r8, ip, sp} + 20d34: e3a00e2a mov r0, #672 ; 0x2a0 + 20d38: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20d3c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20d40: ebf58af4 bl 0xffd83918 + 20d44: 08003158 stmeqda r0, {r3, r4, r6, r8, ip, sp} + 20d48: e1a03000 mov r3, r0 + 20d4c: ebf58c8b bl 0xffd83f80 + 20d50: 08003156 stmeqda r0, {r1, r2, r4, r6, r8, ip, sp} + 20d54: e288001c add r0, r8, #28 ; 0x1c + 20d58: ebf58aee bl 0xffd83918 + 20d5c: 0800315a stmeqda r0, {r1, r3, r4, r6, r8, ip, sp} + 20d60: e1a04000 mov r4, r0 + 20d64: ebf58c85 bl 0xffd83f80 + 20d68: 08003158 stmeqda r0, {r3, r4, r6, r8, ip, sp} + 20d6c: e2830000 add r0, r3, #0 ; 0x0 + 20d70: ebf58ae8 bl 0xffd83918 + 20d74: 0800315c stmeqda r0, {r2, r3, r4, r6, r8, ip, sp} + 20d78: e1a03000 mov r3, r0 + 20d7c: ebf58c7f bl 0xffd83f80 + 20d80: 0800315a stmeqda r0, {r1, r3, r4, r6, r8, ip, sp} + 20d84: e1a01004 mov r1, r4 + 20d88: e0544003 subs r4, r4, r3 + 20d8c: ebf58c7b bl 0xffd83f80 + 20d90: 0800315c stmeqda r0, {r2, r3, r4, r6, r8, ip, sp} + 20d94: e3540000 cmp r4, #0 ; 0x0 + 20d98: ebf58c78 bl 0xffd83f80 + 20d9c: 0800315e stmeqda r0, {r1, r2, r3, r4, r6, r8, ip, sp} + 20da0: e28cc01b add ip, ip, #27 ; 0x1b + 20da4: ba000004 blt 0x20dbc + 20da8: e1a00fac mov r0, ip, lsr #31 + 20dac: e08ff100 add pc, pc, r0, lsl #2 + 20db0: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 20db4: ebf58866 bl 0xffd82f54 + 20db8: ea00000c b 0x20df0 + 20dbc: ebf58c6f bl 0xffd83f80 + 20dc0: 08003160 stmeqda r0, {r5, r6, r8, ip, sp} + 20dc4: e3a00fa6 mov r0, #664 ; 0x298 + 20dc8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20dcc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20dd0: ebf58ad0 bl 0xffd83918 + 20dd4: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 20dd8: e1a05000 mov r5, r0 + 20ddc: ebf58c67 bl 0xffd83f80 + 20de0: 08003162 stmeqda r0, {r1, r5, r6, r8, ip, sp} + 20de4: e1a01004 mov r1, r4 + 20de8: e0944005 adds r4, r4, r5 + 20dec: e28cc008 add ip, ip, #8 ; 0x8 + 20df0: ebf58c62 bl 0xffd83f80 + 20df4: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 20df8: e1b05844 movs r5, r4, asr #16 + 20dfc: ebf58c5f bl 0xffd83f80 + 20e00: 08003166 stmeqda r0, {r1, r2, r5, r6, r8, ip, sp} + 20e04: e59d0434 ldr r0, [sp, #1076] + 20e08: e2800f05 add r0, r0, #20 ; 0x14 + 20e0c: ebf58ac1 bl 0xffd83918 + 20e10: 0800316a stmeqda r0, {r1, r3, r5, r6, r8, ip, sp} + 20e14: e58d0418 str r0, [sp, #1048] + 20e18: ebf58c58 bl 0xffd83f80 + 20e1c: 08003168 stmeqda r0, {r3, r5, r6, r8, ip, sp} + 20e20: e1a01007 mov r1, r7 + 20e24: e2973000 adds r3, r7, #0 ; 0x0 + 20e28: ebf58c54 bl 0xffd83f80 + 20e2c: 0800316a stmeqda r0, {r1, r3, r5, r6, r8, ip, sp} + 20e30: e1a01003 mov r1, r3 + 20e34: e59d0418 ldr r0, [sp, #1048] + 20e38: e0130093 muls r3, r3, r0 + 20e3c: ebf58c4f bl 0xffd83f80 + 20e40: 0800316c stmeqda r0, {r2, r3, r5, r6, r8, ip, sp} + 20e44: e59d0434 ldr r0, [sp, #1076] + 20e48: e2800f06 add r0, r0, #24 ; 0x18 + 20e4c: ebf58ab1 bl 0xffd83918 + 20e50: 08003170 stmeqda r0, {r4, r5, r6, r8, ip, sp} + 20e54: e58d0418 str r0, [sp, #1048] + 20e58: ebf58c48 bl 0xffd83f80 + 20e5c: 0800316e stmeqda r0, {r1, r2, r3, r5, r6, r8, ip, sp} + 20e60: e1a01006 mov r1, r6 + 20e64: e2964000 adds r4, r6, #0 ; 0x0 + 20e68: ebf58c44 bl 0xffd83f80 + 20e6c: 08003170 stmeqda r0, {r4, r5, r6, r8, ip, sp} + 20e70: e1a01004 mov r1, r4 + 20e74: e59d0418 ldr r0, [sp, #1048] + 20e78: e0140094 muls r4, r4, r0 + 20e7c: ebf58c3f bl 0xffd83f80 + 20e80: 08003172 stmeqda r0, {r1, r4, r5, r6, r8, ip, sp} + 20e84: e1a01003 mov r1, r3 + 20e88: e0933004 adds r3, r3, r4 + 20e8c: ebf58c3b bl 0xffd83f80 + 20e90: 08003174 stmeqda r0, {r2, r4, r5, r6, r8, ip, sp} + 20e94: e59d0434 ldr r0, [sp, #1076] + 20e98: e2800f07 add r0, r0, #28 ; 0x1c + 20e9c: ebf58a9d bl 0xffd83918 + 20ea0: 08003178 stmeqda r0, {r3, r4, r5, r6, r8, ip, sp} + 20ea4: e58d0418 str r0, [sp, #1048] + 20ea8: ebf58c34 bl 0xffd83f80 + 20eac: 08003176 stmeqda r0, {r1, r2, r4, r5, r6, r8, ip, sp} + 20eb0: e1a01005 mov r1, r5 + 20eb4: e2954000 adds r4, r5, #0 ; 0x0 + 20eb8: ebf58c30 bl 0xffd83f80 + 20ebc: 08003178 stmeqda r0, {r3, r4, r5, r6, r8, ip, sp} + 20ec0: e1a01004 mov r1, r4 + 20ec4: e59d0418 ldr r0, [sp, #1048] + 20ec8: e0140094 muls r4, r4, r0 + 20ecc: ebf58c2b bl 0xffd83f80 + 20ed0: 0800317a stmeqda r0, {r1, r3, r4, r5, r6, r8, ip, sp} + 20ed4: e1a01003 mov r1, r3 + 20ed8: e0933004 adds r3, r3, r4 + 20edc: ebf58c27 bl 0xffd83f80 + 20ee0: 0800317c stmeqda r0, {r2, r3, r4, r5, r6, r8, ip, sp} + 20ee4: e3530000 cmp r3, #0 ; 0x0 + 20ee8: ebf58c24 bl 0xffd83f80 + 20eec: 0800317e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, ip, sp} + 20ef0: e28cc030 add ip, ip, #48 ; 0x30 + 20ef4: ba000004 blt 0x20f0c + 20ef8: e1a00fac mov r0, ip, lsr #31 + 20efc: e08ff100 add pc, pc, r0, lsl #2 + 20f00: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 20f04: ebf58812 bl 0xffd82f54 + 20f08: ea00000c b 0x20f40 + 20f0c: ebf58c1b bl 0xffd83f80 + 20f10: 08003180 stmeqda r0, {r7, r8, ip, sp} + 20f14: e3a00fa9 mov r0, #676 ; 0x2a4 + 20f18: e3800a03 orr r0, r0, #12288 ; 0x3000 + 20f1c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 20f20: ebf58a7c bl 0xffd83918 + 20f24: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 20f28: e1a04000 mov r4, r0 + 20f2c: ebf58c13 bl 0xffd83f80 + 20f30: 08003182 stmeqda r0, {r1, r7, r8, ip, sp} + 20f34: e1a01003 mov r1, r3 + 20f38: e0933004 adds r3, r3, r4 + 20f3c: e28cc008 add ip, ip, #8 ; 0x8 + 20f40: ebf58c0e bl 0xffd83f80 + 20f44: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 20f48: e1b00743 movs r0, r3, asr #14 + 20f4c: e58d041c str r0, [sp, #1052] + 20f50: ebf58c0a bl 0xffd83f80 + 20f54: 08003186 stmeqda r0, {r1, r2, r7, r8, ip, sp} + 20f58: e59d141c ldr r1, [sp, #1052] + 20f5c: e59d141c ldr r1, [sp, #1052] + 20f60: e2914000 adds r4, r1, #0 ; 0x0 + 20f64: ebf58c05 bl 0xffd83f80 + 20f68: 08003188 stmeqda r0, {r3, r7, r8, ip, sp} + 20f6c: e1a01004 mov r1, r4 + 20f70: e2544080 subs r4, r4, #128 ; 0x80 + 20f74: ebf58c01 bl 0xffd83f80 + 20f78: 0800318a stmeqda r0, {r1, r3, r7, r8, ip, sp} + 20f7c: e3b030fc movs r3, #252 ; 0xfc + 20f80: ebf58bfe bl 0xffd83f80 + 20f84: 0800318c stmeqda r0, {r2, r3, r7, r8, ip, sp} + 20f88: e1b03283 movs r3, r3, lsl #5 + 20f8c: ebf58bfb bl 0xffd83f80 + 20f90: 0800318e stmeqda r0, {r1, r2, r3, r7, r8, ip, sp} + 20f94: e1540003 cmp r4, r3 + 20f98: ebf58bf8 bl 0xffd83f80 + 20f9c: 08003190 stmeqda r0, {r4, r7, r8, ip, sp} + 20fa0: e28cc015 add ip, ip, #21 ; 0x15 + 20fa4: 8a000004 bhi 0x20fbc + 20fa8: e1a00fac mov r0, ip, lsr #31 + 20fac: e08ff100 add pc, pc, r0, lsl #2 + 20fb0: 08003194 stmeqda r0, {r2, r4, r7, r8, ip, sp} + 20fb4: ebf587e6 bl 0xffd82f54 + 20fb8: ea000007 b 0x20fdc + 20fbc: ebf58bef bl 0xffd83f80 + 20fc0: 08003192 stmeqda r0, {r1, r4, r7, r8, ip, sp} + 20fc4: e28cc003 add ip, ip, #3 ; 0x3 + 20fc8: e1a00fac mov r0, ip, lsr #31 + 20fcc: e08ff100 add pc, pc, r0, lsl #2 + 20fd0: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 20fd4: ebf587de bl 0xffd82f54 + 20fd8: ea0000d9 b 0x21344 + 20fdc: ebf58be7 bl 0xffd83f80 + 20fe0: 08003194 stmeqda r0, {r2, r4, r7, r8, ip, sp} + 20fe4: e59d0434 ldr r0, [sp, #1076] + 20fe8: e2800f00 add r0, r0, #0 ; 0x0 + 20fec: ebf58a49 bl 0xffd83918 + 20ff0: 08003198 stmeqda r0, {r3, r4, r7, r8, ip, sp} + 20ff4: e58d0418 str r0, [sp, #1048] + 20ff8: ebf58be0 bl 0xffd83f80 + 20ffc: 08003196 stmeqda r0, {r1, r2, r4, r7, r8, ip, sp} + 21000: e1a01007 mov r1, r7 + 21004: e2973000 adds r3, r7, #0 ; 0x0 + 21008: ebf58bdc bl 0xffd83f80 + 2100c: 08003198 stmeqda r0, {r3, r4, r7, r8, ip, sp} + 21010: e1a01003 mov r1, r3 + 21014: e59d0418 ldr r0, [sp, #1048] + 21018: e0130093 muls r3, r3, r0 + 2101c: ebf58bd7 bl 0xffd83f80 + 21020: 0800319a stmeqda r0, {r1, r3, r4, r7, r8, ip, sp} + 21024: e3b00000 movs r0, #0 ; 0x0 + 21028: e58d0418 str r0, [sp, #1048] + 2102c: ebf58bd3 bl 0xffd83f80 + 21030: 0800319c stmeqda r0, {r2, r3, r4, r7, r8, ip, sp} + 21034: e1a01006 mov r1, r6 + 21038: e2964000 adds r4, r6, #0 ; 0x0 + 2103c: ebf58bcf bl 0xffd83f80 + 21040: 0800319e stmeqda r0, {r1, r2, r3, r4, r7, r8, ip, sp} + 21044: e1a01004 mov r1, r4 + 21048: e59d0418 ldr r0, [sp, #1048] + 2104c: e0140094 muls r4, r4, r0 + 21050: ebf58bca bl 0xffd83f80 + 21054: 080031a0 stmeqda r0, {r5, r7, r8, ip, sp} + 21058: e1a01003 mov r1, r3 + 2105c: e0933004 adds r3, r3, r4 + 21060: ebf58bc6 bl 0xffd83f80 + 21064: 080031a2 stmeqda r0, {r1, r5, r7, r8, ip, sp} + 21068: e59d0434 ldr r0, [sp, #1076] + 2106c: e2800f01 add r0, r0, #4 ; 0x4 + 21070: ebf58a28 bl 0xffd83918 + 21074: 080031a6 stmeqda r0, {r1, r2, r5, r7, r8, ip, sp} + 21078: e58d0418 str r0, [sp, #1048] + 2107c: ebf58bbf bl 0xffd83f80 + 21080: 080031a4 stmeqda r0, {r2, r5, r7, r8, ip, sp} + 21084: e1a01005 mov r1, r5 + 21088: e2954000 adds r4, r5, #0 ; 0x0 + 2108c: ebf58bbb bl 0xffd83f80 + 21090: 080031a6 stmeqda r0, {r1, r2, r5, r7, r8, ip, sp} + 21094: e1a01004 mov r1, r4 + 21098: e59d0418 ldr r0, [sp, #1048] + 2109c: e0140094 muls r4, r4, r0 + 210a0: ebf58bb6 bl 0xffd83f80 + 210a4: 080031a8 stmeqda r0, {r3, r5, r7, r8, ip, sp} + 210a8: e1a01003 mov r1, r3 + 210ac: e0933004 adds r3, r3, r4 + 210b0: ebf58bb2 bl 0xffd83f80 + 210b4: 080031aa stmeqda r0, {r1, r3, r5, r7, r8, ip, sp} + 210b8: e3530000 cmp r3, #0 ; 0x0 + 210bc: ebf58baf bl 0xffd83f80 + 210c0: 080031ac stmeqda r0, {r2, r3, r5, r7, r8, ip, sp} + 210c4: e28cc02b add ip, ip, #43 ; 0x2b + 210c8: ba000004 blt 0x210e0 + 210cc: e1a00fac mov r0, ip, lsr #31 + 210d0: e08ff100 add pc, pc, r0, lsl #2 + 210d4: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 210d8: ebf5879d bl 0xffd82f54 + 210dc: ea00000c b 0x21114 + 210e0: ebf58ba6 bl 0xffd83f80 + 210e4: 080031ae stmeqda r0, {r1, r2, r3, r5, r7, r8, ip, sp} + 210e8: e3a00fa9 mov r0, #676 ; 0x2a4 + 210ec: e3800a03 orr r0, r0, #12288 ; 0x3000 + 210f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 210f4: ebf58a07 bl 0xffd83918 + 210f8: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 210fc: e1a04000 mov r4, r0 + 21100: ebf58b9e bl 0xffd83f80 + 21104: 080031b0 stmeqda r0, {r4, r5, r7, r8, ip, sp} + 21108: e1a01003 mov r1, r3 + 2110c: e0933004 adds r3, r3, r4 + 21110: e28cc008 add ip, ip, #8 ; 0x8 + 21114: ebf58b99 bl 0xffd83f80 + 21118: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 2111c: e1b00743 movs r0, r3, asr #14 + 21120: e58d0418 str r0, [sp, #1048] + 21124: ebf58b95 bl 0xffd83f80 + 21128: 080031b4 stmeqda r0, {r2, r4, r5, r7, r8, ip, sp} + 2112c: e59d0434 ldr r0, [sp, #1076] + 21130: e2800f02 add r0, r0, #8 ; 0x8 + 21134: ebf589f7 bl 0xffd83918 + 21138: 080031b8 stmeqda r0, {r3, r4, r5, r7, r8, ip, sp} + 2113c: e1a04000 mov r4, r0 + 21140: ebf58b8e bl 0xffd83f80 + 21144: 080031b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, ip, sp} + 21148: e1a01007 mov r1, r7 + 2114c: e2973000 adds r3, r7, #0 ; 0x0 + 21150: ebf58b8a bl 0xffd83f80 + 21154: 080031b8 stmeqda r0, {r3, r4, r5, r7, r8, ip, sp} + 21158: e1a01003 mov r1, r3 + 2115c: e0130493 muls r3, r3, r4 + 21160: ebf58b86 bl 0xffd83f80 + 21164: 080031ba stmeqda r0, {r1, r3, r4, r5, r7, r8, ip, sp} + 21168: e59d0434 ldr r0, [sp, #1076] + 2116c: e2800f03 add r0, r0, #12 ; 0xc + 21170: ebf589e8 bl 0xffd83918 + 21174: 080031be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, ip, sp} + 21178: e1a07000 mov r7, r0 + 2117c: ebf58b7f bl 0xffd83f80 + 21180: 080031bc stmeqda r0, {r2, r3, r4, r5, r7, r8, ip, sp} + 21184: e1a01006 mov r1, r6 + 21188: e2964000 adds r4, r6, #0 ; 0x0 + 2118c: ebf58b7b bl 0xffd83f80 + 21190: 080031be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, ip, sp} + 21194: e1a01004 mov r1, r4 + 21198: e0140794 muls r4, r4, r7 + 2119c: ebf58b77 bl 0xffd83f80 + 211a0: 080031c0 stmeqda r0, {r6, r7, r8, ip, sp} + 211a4: e1a01003 mov r1, r3 + 211a8: e0933004 adds r3, r3, r4 + 211ac: ebf58b73 bl 0xffd83f80 + 211b0: 080031c2 stmeqda r0, {r1, r6, r7, r8, ip, sp} + 211b4: e59d0434 ldr r0, [sp, #1076] + 211b8: e2800f04 add r0, r0, #16 ; 0x10 + 211bc: ebf589d5 bl 0xffd83918 + 211c0: 080031c6 stmeqda r0, {r1, r2, r6, r7, r8, ip, sp} + 211c4: e1a06000 mov r6, r0 + 211c8: ebf58b6c bl 0xffd83f80 + 211cc: 080031c4 stmeqda r0, {r2, r6, r7, r8, ip, sp} + 211d0: e1a01005 mov r1, r5 + 211d4: e2954000 adds r4, r5, #0 ; 0x0 + 211d8: ebf58b68 bl 0xffd83f80 + 211dc: 080031c6 stmeqda r0, {r1, r2, r6, r7, r8, ip, sp} + 211e0: e1a01004 mov r1, r4 + 211e4: e0140694 muls r4, r4, r6 + 211e8: ebf58b64 bl 0xffd83f80 + 211ec: 080031c8 stmeqda r0, {r3, r6, r7, r8, ip, sp} + 211f0: e1a01003 mov r1, r3 + 211f4: e0933004 adds r3, r3, r4 + 211f8: ebf58b60 bl 0xffd83f80 + 211fc: 080031ca stmeqda r0, {r1, r3, r6, r7, r8, ip, sp} + 21200: e3530000 cmp r3, #0 ; 0x0 + 21204: ebf58b5d bl 0xffd83f80 + 21208: 080031cc stmeqda r0, {r2, r3, r6, r7, r8, ip, sp} + 2120c: e28cc030 add ip, ip, #48 ; 0x30 + 21210: ba000004 blt 0x21228 + 21214: e1a00fac mov r0, ip, lsr #31 + 21218: e08ff100 add pc, pc, r0, lsl #2 + 2121c: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21220: ebf5874b bl 0xffd82f54 + 21224: ea00000c b 0x2125c + 21228: ebf58b54 bl 0xffd83f80 + 2122c: 080031ce stmeqda r0, {r1, r2, r3, r6, r7, r8, ip, sp} + 21230: e3a00fa9 mov r0, #676 ; 0x2a4 + 21234: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21238: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2123c: ebf589b5 bl 0xffd83918 + 21240: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21244: e1a07000 mov r7, r0 + 21248: ebf58b4c bl 0xffd83f80 + 2124c: 080031d0 stmeqda r0, {r4, r6, r7, r8, ip, sp} + 21250: e1a01003 mov r1, r3 + 21254: e0933007 adds r3, r3, r7 + 21258: e28cc008 add ip, ip, #8 ; 0x8 + 2125c: ebf58b47 bl 0xffd83f80 + 21260: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21264: e1b07743 movs r7, r3, asr #14 + 21268: ebf58b44 bl 0xffd83f80 + 2126c: 080031d4 stmeqda r0, {r2, r4, r6, r7, r8, ip, sp} + 21270: e59de418 ldr lr, [sp, #1048] + 21274: e1b0340e movs r3, lr, lsl #8 + 21278: ebf58b40 bl 0xffd83f80 + 2127c: 080031d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, ip, sp} + 21280: e59d141c ldr r1, [sp, #1052] + 21284: e59d141c ldr r1, [sp, #1052] + 21288: e2914000 adds r4, r1, #0 ; 0x0 + 2128c: ebf58b3b bl 0xffd83f80 + 21290: 080031d8 stmeqda r0, {r3, r4, r6, r7, r8, ip, sp} + 21294: ebf58b39 bl 0xffd83f80 + 21298: 080031da stmeqda r0, {r1, r3, r4, r6, r7, r8, ip, sp} + 2129c: e3a000dd mov r0, #221 ; 0xdd + 212a0: e3800c31 orr r0, r0, #12544 ; 0x3100 + 212a4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 212a8: e58d0438 str r0, [sp, #1080] + 212ac: e28cc00f add ip, ip, #15 ; 0xf + 212b0: e1a00fac mov r0, ip, lsr #31 + 212b4: e08ff100 add pc, pc, r0, lsl #2 + 212b8: 080c2f20 stmeqda ip, {r5, r8, r9, sl, fp, sp} + 212bc: ebf58724 bl 0xffd82f54 + 212c0: ea000509 b 0x226ec + 212c4: 08003396 stmeqda r0, {r1, r2, r4, r7, r8, r9, ip, sp} + 212c8: 00000000 andeq r0, r0, r0 + 212cc: ebf58b2b bl 0xffd83f80 + 212d0: 08003396 stmeqda r0, {r1, r2, r4, r7, r8, r9, ip, sp} + 212d4: e3a00e47 mov r0, #1136 ; 0x470 + 212d8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 212dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 212e0: ebf5898c bl 0xffd83918 + 212e4: 0800339a stmeqda r0, {r1, r3, r4, r7, r8, r9, ip, sp} + 212e8: e1a03000 mov r3, r0 + 212ec: ebf58b23 bl 0xffd83f80 + 212f0: 08003398 stmeqda r0, {r3, r4, r7, r8, r9, ip, sp} + 212f4: e2830000 add r0, r3, #0 ; 0x0 + 212f8: ebf58986 bl 0xffd83918 + 212fc: 0800339c stmeqda r0, {r2, r3, r4, r7, r8, r9, ip, sp} + 21300: e1a03000 mov r3, r0 + 21304: ebf58b1d bl 0xffd83f80 + 21308: 0800339a stmeqda r0, {r1, r3, r4, r7, r8, r9, ip, sp} + 2130c: ebf58b1b bl 0xffd83f80 + 21310: 0800339c stmeqda r0, {r2, r3, r4, r7, r8, r9, ip, sp} + 21314: e3a0009f mov r0, #159 ; 0x9f + 21318: e3800c33 orr r0, r0, #13056 ; 0x3300 + 2131c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21320: e58d0438 str r0, [sp, #1080] + 21324: e28cc010 add ip, ip, #16 ; 0x10 + 21328: e1a00fac mov r0, ip, lsr #31 + 2132c: e08ff100 add pc, pc, r0, lsl #2 + 21330: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + 21334: ebf58706 bl 0xffd82f54 + 21338: eaffa51e b 0xa7b8 + 2133c: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 21340: 00000000 andeq r0, r0, r0 + 21344: ebf58b0d bl 0xffd83f80 + 21348: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 2134c: e1a01008 mov r1, r8 + 21350: e298802c adds r8, r8, #44 ; 0x2c + 21354: ebf58b09 bl 0xffd83f80 + 21358: 08003382 stmeqda r0, {r1, r7, r8, r9, ip, sp} + 2135c: e3b06080 movs r6, #128 ; 0x80 + 21360: ebf58b06 bl 0xffd83f80 + 21364: 08003384 stmeqda r0, {r2, r7, r8, r9, ip, sp} + 21368: e1b06886 movs r6, r6, lsl #17 + 2136c: ebf58b03 bl 0xffd83f80 + 21370: 08003386 stmeqda r0, {r1, r2, r7, r8, r9, ip, sp} + 21374: e59d0424 ldr r0, [sp, #1060] + 21378: e0800006 add r0, r0, r6 + 2137c: e58d0424 str r0, [sp, #1060] + 21380: ebf58afe bl 0xffd83f80 + 21384: 08003388 stmeqda r0, {r3, r7, r8, r9, ip, sp} + 21388: e3b07001 movs r7, #1 ; 0x1 + 2138c: ebf58afb bl 0xffd83f80 + 21390: 0800338a stmeqda r0, {r1, r3, r7, r8, r9, ip, sp} + 21394: e59d0420 ldr r0, [sp, #1056] + 21398: e0800007 add r0, r0, r7 + 2139c: e58d0420 str r0, [sp, #1056] + 213a0: ebf58af6 bl 0xffd83f80 + 213a4: 0800338c stmeqda r0, {r2, r3, r7, r8, r9, ip, sp} + 213a8: e3a00f1b mov r0, #108 ; 0x6c + 213ac: e3800b0d orr r0, r0, #13312 ; 0x3400 + 213b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 213b4: ebf58957 bl 0xffd83918 + 213b8: 08003390 stmeqda r0, {r4, r7, r8, r9, ip, sp} + 213bc: e1a03000 mov r3, r0 + 213c0: ebf58aee bl 0xffd83f80 + 213c4: 0800338e stmeqda r0, {r1, r2, r3, r7, r8, r9, ip, sp} + 213c8: e2830000 add r0, r3, #0 ; 0x0 + 213cc: ebf58951 bl 0xffd83918 + 213d0: 08003392 stmeqda r0, {r1, r4, r7, r8, r9, ip, sp} + 213d4: e1a03000 mov r3, r0 + 213d8: ebf58ae8 bl 0xffd83f80 + 213dc: 08003390 stmeqda r0, {r4, r7, r8, r9, ip, sp} + 213e0: e59d0420 ldr r0, [sp, #1056] + 213e4: e1500003 cmp r0, r3 + 213e8: ebf58ae4 bl 0xffd83f80 + 213ec: 08003392 stmeqda r0, {r1, r4, r7, r8, r9, ip, sp} + 213f0: e28cc022 add ip, ip, #34 ; 0x22 + 213f4: 3a000004 bcc 0x2140c + 213f8: e1a00fac mov r0, ip, lsr #31 + 213fc: e08ff100 add pc, pc, r0, lsl #2 + 21400: 08003396 stmeqda r0, {r1, r2, r4, r7, r8, r9, ip, sp} + 21404: ebf586d2 bl 0xffd82f54 + 21408: ea000007 b 0x2142c + 2140c: ebf58adb bl 0xffd83f80 + 21410: 08003394 stmeqda r0, {r2, r4, r7, r8, r9, ip, sp} + 21414: e28cc003 add ip, ip, #3 ; 0x3 + 21418: e1a00fac mov r0, ip, lsr #31 + 2141c: e08ff100 add pc, pc, r0, lsl #2 + 21420: 08003116 stmeqda r0, {r1, r2, r4, r8, ip, sp} + 21424: ebf586ca bl 0xffd82f54 + 21428: ea00001d b 0x214a4 + 2142c: ebf58ad3 bl 0xffd83f80 + 21430: 08003396 stmeqda r0, {r1, r2, r4, r7, r8, r9, ip, sp} + 21434: e3a00e47 mov r0, #1136 ; 0x470 + 21438: e3800a03 orr r0, r0, #12288 ; 0x3000 + 2143c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21440: ebf58934 bl 0xffd83918 + 21444: 0800339a stmeqda r0, {r1, r3, r4, r7, r8, r9, ip, sp} + 21448: e1a03000 mov r3, r0 + 2144c: ebf58acb bl 0xffd83f80 + 21450: 08003398 stmeqda r0, {r3, r4, r7, r8, r9, ip, sp} + 21454: e2830000 add r0, r3, #0 ; 0x0 + 21458: ebf5892e bl 0xffd83918 + 2145c: 0800339c stmeqda r0, {r2, r3, r4, r7, r8, r9, ip, sp} + 21460: e1a03000 mov r3, r0 + 21464: ebf58ac5 bl 0xffd83f80 + 21468: 0800339a stmeqda r0, {r1, r3, r4, r7, r8, r9, ip, sp} + 2146c: ebf58ac3 bl 0xffd83f80 + 21470: 0800339c stmeqda r0, {r2, r3, r4, r7, r8, r9, ip, sp} + 21474: e3a0009f mov r0, #159 ; 0x9f + 21478: e3800c33 orr r0, r0, #13056 ; 0x3300 + 2147c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21480: e58d0438 str r0, [sp, #1080] + 21484: e28cc010 add ip, ip, #16 ; 0x10 + 21488: e1a00fac mov r0, ip, lsr #31 + 2148c: e08ff100 add pc, pc, r0, lsl #2 + 21490: 080c31dc stmeqda ip, {r2, r3, r4, r6, r7, r8, ip, sp} + 21494: ebf586ae bl 0xffd82f54 + 21498: eaffa4c6 b 0xa7b8 + 2149c: 08003116 stmeqda r0, {r1, r2, r4, r8, ip, sp} + 214a0: 00000000 andeq r0, r0, r0 + 214a4: ebf58ab5 bl 0xffd83f80 + 214a8: 08003116 stmeqda r0, {r1, r2, r4, r8, ip, sp} + 214ac: e1a01008 mov r1, r8 + 214b0: e2983000 adds r3, r8, #0 ; 0x0 + 214b4: ebf58ab1 bl 0xffd83f80 + 214b8: 08003118 stmeqda r0, {r3, r4, r8, ip, sp} + 214bc: e1a01003 mov r1, r3 + 214c0: e293302a adds r3, r3, #42 ; 0x2a + 214c4: ebf58aad bl 0xffd83f80 + 214c8: 0800311a stmeqda r0, {r1, r3, r4, r8, ip, sp} + 214cc: e2830000 add r0, r3, #0 ; 0x0 + 214d0: ebf588b9 bl 0xffd837bc + 214d4: 0800311e stmeqda r0, {r1, r2, r3, r4, r8, ip, sp} + 214d8: e1a04000 mov r4, r0 + 214dc: ebf58aa7 bl 0xffd83f80 + 214e0: 0800311c stmeqda r0, {r2, r3, r4, r8, ip, sp} + 214e4: e3b030c0 movs r3, #192 ; 0xc0 + 214e8: ebf58aa4 bl 0xffd83f80 + 214ec: 0800311e stmeqda r0, {r1, r2, r3, r4, r8, ip, sp} + 214f0: e1a01003 mov r1, r3 + 214f4: e0133004 ands r3, r3, r4 + 214f8: ebf58aa0 bl 0xffd83f80 + 214fc: 08003120 stmeqda r0, {r5, r8, ip, sp} + 21500: e35300c0 cmp r3, #192 ; 0xc0 + 21504: ebf58a9d bl 0xffd83f80 + 21508: 08003122 stmeqda r0, {r1, r5, r8, ip, sp} + 2150c: e28cc017 add ip, ip, #23 ; 0x17 + 21510: 1a000004 bne 0x21528 + 21514: e1a00fac mov r0, ip, lsr #31 + 21518: e08ff100 add pc, pc, r0, lsl #2 + 2151c: 08003126 stmeqda r0, {r1, r2, r5, r8, ip, sp} + 21520: ebf5868b bl 0xffd82f54 + 21524: ea000007 b 0x21548 + 21528: ebf58a94 bl 0xffd83f80 + 2152c: 08003124 stmeqda r0, {r2, r5, r8, ip, sp} + 21530: e28cc003 add ip, ip, #3 ; 0x3 + 21534: e1a00fac mov r0, ip, lsr #31 + 21538: e08ff100 add pc, pc, r0, lsl #2 + 2153c: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 21540: ebf58683 bl 0xffd82f54 + 21544: eaffff7e b 0x21344 + 21548: ebf58a8c bl 0xffd83f80 + 2154c: 08003126 stmeqda r0, {r1, r2, r5, r8, ip, sp} + 21550: e3b03020 movs r3, #32 ; 0x20 + 21554: ebf58a89 bl 0xffd83f80 + 21558: 08003128 stmeqda r0, {r3, r5, r8, ip, sp} + 2155c: e1a01003 mov r1, r3 + 21560: e0133004 ands r3, r3, r4 + 21564: ebf58a85 bl 0xffd83f80 + 21568: 0800312a stmeqda r0, {r1, r3, r5, r8, ip, sp} + 2156c: e3530000 cmp r3, #0 ; 0x0 + 21570: ebf58a82 bl 0xffd83f80 + 21574: 0800312c stmeqda r0, {r2, r3, r5, r8, ip, sp} + 21578: e28cc00c add ip, ip, #12 ; 0xc + 2157c: 0a000004 beq 0x21594 + 21580: e1a00fac mov r0, ip, lsr #31 + 21584: e08ff100 add pc, pc, r0, lsl #2 + 21588: 08003130 stmeqda r0, {r4, r5, r8, ip, sp} + 2158c: ebf58670 bl 0xffd82f54 + 21590: ea000007 b 0x215b4 + 21594: ebf58a79 bl 0xffd83f80 + 21598: 0800312e stmeqda r0, {r1, r2, r3, r5, r8, ip, sp} + 2159c: e28cc003 add ip, ip, #3 ; 0x3 + 215a0: e1a00fac mov r0, ip, lsr #31 + 215a4: e08ff100 add pc, pc, r0, lsl #2 + 215a8: 080032b4 stmeqda r0, {r2, r4, r5, r7, r9, ip, sp} + 215ac: ebf58668 bl 0xffd82f54 + 215b0: ea0001d1 b 0x21cfc + 215b4: ebf58a71 bl 0xffd83f80 + 215b8: 08003130 stmeqda r0, {r4, r5, r8, ip, sp} + 215bc: e3a00fa5 mov r0, #660 ; 0x294 + 215c0: e3800a03 orr r0, r0, #12288 ; 0x3000 + 215c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 215c8: ebf588d2 bl 0xffd83918 + 215cc: 08003134 stmeqda r0, {r2, r4, r5, r8, ip, sp} + 215d0: e1a03000 mov r3, r0 + 215d4: ebf58a69 bl 0xffd83f80 + 215d8: 08003132 stmeqda r0, {r1, r4, r5, r8, ip, sp} + 215dc: e2880014 add r0, r8, #20 ; 0x14 + 215e0: ebf588cc bl 0xffd83918 + 215e4: 08003136 stmeqda r0, {r1, r2, r4, r5, r8, ip, sp} + 215e8: e1a04000 mov r4, r0 + 215ec: ebf58a63 bl 0xffd83f80 + 215f0: 08003134 stmeqda r0, {r2, r4, r5, r8, ip, sp} + 215f4: e2830000 add r0, r3, #0 ; 0x0 + 215f8: ebf588c6 bl 0xffd83918 + 215fc: 08003138 stmeqda r0, {r3, r4, r5, r8, ip, sp} + 21600: e1a03000 mov r3, r0 + 21604: ebf58a5d bl 0xffd83f80 + 21608: 08003136 stmeqda r0, {r1, r2, r4, r5, r8, ip, sp} + 2160c: e1a01004 mov r1, r4 + 21610: e0543003 subs r3, r4, r3 + 21614: ebf58a59 bl 0xffd83f80 + 21618: 08003138 stmeqda r0, {r3, r4, r5, r8, ip, sp} + 2161c: e3530000 cmp r3, #0 ; 0x0 + 21620: ebf58a56 bl 0xffd83f80 + 21624: 0800313a stmeqda r0, {r1, r3, r4, r5, r8, ip, sp} + 21628: e28cc018 add ip, ip, #24 ; 0x18 + 2162c: ba000004 blt 0x21644 + 21630: e1a00fac mov r0, ip, lsr #31 + 21634: e08ff100 add pc, pc, r0, lsl #2 + 21638: 08003140 stmeqda r0, {r6, r8, ip, sp} + 2163c: ebf58644 bl 0xffd82f54 + 21640: ea00000d b 0x2167c + 21644: ebf58a4d bl 0xffd83f80 + 21648: 0800313c stmeqda r0, {r2, r3, r4, r5, r8, ip, sp} + 2164c: e3a00fa6 mov r0, #664 ; 0x298 + 21650: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21654: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21658: ebf588ae bl 0xffd83918 + 2165c: 08003140 stmeqda r0, {r6, r8, ip, sp} + 21660: e58d0418 str r0, [sp, #1048] + 21664: ebf58a45 bl 0xffd83f80 + 21668: 0800313e stmeqda r0, {r1, r2, r3, r4, r5, r8, ip, sp} + 2166c: e1a01003 mov r1, r3 + 21670: e59d0418 ldr r0, [sp, #1048] + 21674: e0933000 adds r3, r3, r0 + 21678: e28cc008 add ip, ip, #8 ; 0x8 + 2167c: ebf58a3f bl 0xffd83f80 + 21680: 08003140 stmeqda r0, {r6, r8, ip, sp} + 21684: e1b07843 movs r7, r3, asr #16 + 21688: ebf58a3c bl 0xffd83f80 + 2168c: 08003142 stmeqda r0, {r1, r6, r8, ip, sp} + 21690: e3a00fa7 mov r0, #668 ; 0x29c + 21694: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21698: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2169c: ebf5889d bl 0xffd83918 + 216a0: 08003146 stmeqda r0, {r1, r2, r6, r8, ip, sp} + 216a4: e1a03000 mov r3, r0 + 216a8: ebf58a34 bl 0xffd83f80 + 216ac: 08003144 stmeqda r0, {r2, r6, r8, ip, sp} + 216b0: e2880018 add r0, r8, #24 ; 0x18 + 216b4: ebf58897 bl 0xffd83918 + 216b8: 08003148 stmeqda r0, {r3, r6, r8, ip, sp} + 216bc: e1a04000 mov r4, r0 + 216c0: ebf58a2e bl 0xffd83f80 + 216c4: 08003146 stmeqda r0, {r1, r2, r6, r8, ip, sp} + 216c8: e2830000 add r0, r3, #0 ; 0x0 + 216cc: ebf58891 bl 0xffd83918 + 216d0: 0800314a stmeqda r0, {r1, r3, r6, r8, ip, sp} + 216d4: e1a03000 mov r3, r0 + 216d8: ebf58a28 bl 0xffd83f80 + 216dc: 08003148 stmeqda r0, {r3, r6, r8, ip, sp} + 216e0: e1a01004 mov r1, r4 + 216e4: e0544003 subs r4, r4, r3 + 216e8: ebf58a24 bl 0xffd83f80 + 216ec: 0800314a stmeqda r0, {r1, r3, r6, r8, ip, sp} + 216f0: e3540000 cmp r4, #0 ; 0x0 + 216f4: ebf58a21 bl 0xffd83f80 + 216f8: 0800314c stmeqda r0, {r2, r3, r6, r8, ip, sp} + 216fc: e28cc01b add ip, ip, #27 ; 0x1b + 21700: ba000004 blt 0x21718 + 21704: e1a00fac mov r0, ip, lsr #31 + 21708: e08ff100 add pc, pc, r0, lsl #2 + 2170c: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 21710: ebf5860f bl 0xffd82f54 + 21714: ea00000c b 0x2174c + 21718: ebf58a18 bl 0xffd83f80 + 2171c: 0800314e stmeqda r0, {r1, r2, r3, r6, r8, ip, sp} + 21720: e3a00fa6 mov r0, #664 ; 0x298 + 21724: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21728: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2172c: ebf58879 bl 0xffd83918 + 21730: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 21734: e1a03000 mov r3, r0 + 21738: ebf58a10 bl 0xffd83f80 + 2173c: 08003150 stmeqda r0, {r4, r6, r8, ip, sp} + 21740: e1a01004 mov r1, r4 + 21744: e0944003 adds r4, r4, r3 + 21748: e28cc008 add ip, ip, #8 ; 0x8 + 2174c: ebf58a0b bl 0xffd83f80 + 21750: 08003152 stmeqda r0, {r1, r4, r6, r8, ip, sp} + 21754: e1b06844 movs r6, r4, asr #16 + 21758: ebf58a08 bl 0xffd83f80 + 2175c: 08003154 stmeqda r0, {r2, r4, r6, r8, ip, sp} + 21760: e3a00e2a mov r0, #672 ; 0x2a0 + 21764: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21768: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2176c: ebf58869 bl 0xffd83918 + 21770: 08003158 stmeqda r0, {r3, r4, r6, r8, ip, sp} + 21774: e1a03000 mov r3, r0 + 21778: ebf58a00 bl 0xffd83f80 + 2177c: 08003156 stmeqda r0, {r1, r2, r4, r6, r8, ip, sp} + 21780: e288001c add r0, r8, #28 ; 0x1c + 21784: ebf58863 bl 0xffd83918 + 21788: 0800315a stmeqda r0, {r1, r3, r4, r6, r8, ip, sp} + 2178c: e1a04000 mov r4, r0 + 21790: ebf589fa bl 0xffd83f80 + 21794: 08003158 stmeqda r0, {r3, r4, r6, r8, ip, sp} + 21798: e2830000 add r0, r3, #0 ; 0x0 + 2179c: ebf5885d bl 0xffd83918 + 217a0: 0800315c stmeqda r0, {r2, r3, r4, r6, r8, ip, sp} + 217a4: e1a03000 mov r3, r0 + 217a8: ebf589f4 bl 0xffd83f80 + 217ac: 0800315a stmeqda r0, {r1, r3, r4, r6, r8, ip, sp} + 217b0: e1a01004 mov r1, r4 + 217b4: e0544003 subs r4, r4, r3 + 217b8: ebf589f0 bl 0xffd83f80 + 217bc: 0800315c stmeqda r0, {r2, r3, r4, r6, r8, ip, sp} + 217c0: e3540000 cmp r4, #0 ; 0x0 + 217c4: ebf589ed bl 0xffd83f80 + 217c8: 0800315e stmeqda r0, {r1, r2, r3, r4, r6, r8, ip, sp} + 217cc: e28cc01b add ip, ip, #27 ; 0x1b + 217d0: ba000004 blt 0x217e8 + 217d4: e1a00fac mov r0, ip, lsr #31 + 217d8: e08ff100 add pc, pc, r0, lsl #2 + 217dc: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 217e0: ebf585db bl 0xffd82f54 + 217e4: ea00000c b 0x2181c + 217e8: ebf589e4 bl 0xffd83f80 + 217ec: 08003160 stmeqda r0, {r5, r6, r8, ip, sp} + 217f0: e3a00fa6 mov r0, #664 ; 0x298 + 217f4: e3800a03 orr r0, r0, #12288 ; 0x3000 + 217f8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 217fc: ebf58845 bl 0xffd83918 + 21800: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 21804: e1a05000 mov r5, r0 + 21808: ebf589dc bl 0xffd83f80 + 2180c: 08003162 stmeqda r0, {r1, r5, r6, r8, ip, sp} + 21810: e1a01004 mov r1, r4 + 21814: e0944005 adds r4, r4, r5 + 21818: e28cc008 add ip, ip, #8 ; 0x8 + 2181c: ebf589d7 bl 0xffd83f80 + 21820: 08003164 stmeqda r0, {r2, r5, r6, r8, ip, sp} + 21824: e1b05844 movs r5, r4, asr #16 + 21828: ebf589d4 bl 0xffd83f80 + 2182c: 08003166 stmeqda r0, {r1, r2, r5, r6, r8, ip, sp} + 21830: e59d0434 ldr r0, [sp, #1076] + 21834: e2800f05 add r0, r0, #20 ; 0x14 + 21838: ebf58836 bl 0xffd83918 + 2183c: 0800316a stmeqda r0, {r1, r3, r5, r6, r8, ip, sp} + 21840: e58d0418 str r0, [sp, #1048] + 21844: ebf589cd bl 0xffd83f80 + 21848: 08003168 stmeqda r0, {r3, r5, r6, r8, ip, sp} + 2184c: e1a01007 mov r1, r7 + 21850: e2973000 adds r3, r7, #0 ; 0x0 + 21854: ebf589c9 bl 0xffd83f80 + 21858: 0800316a stmeqda r0, {r1, r3, r5, r6, r8, ip, sp} + 2185c: e1a01003 mov r1, r3 + 21860: e59d0418 ldr r0, [sp, #1048] + 21864: e0130093 muls r3, r3, r0 + 21868: ebf589c4 bl 0xffd83f80 + 2186c: 0800316c stmeqda r0, {r2, r3, r5, r6, r8, ip, sp} + 21870: e59d0434 ldr r0, [sp, #1076] + 21874: e2800f06 add r0, r0, #24 ; 0x18 + 21878: ebf58826 bl 0xffd83918 + 2187c: 08003170 stmeqda r0, {r4, r5, r6, r8, ip, sp} + 21880: e58d0418 str r0, [sp, #1048] + 21884: ebf589bd bl 0xffd83f80 + 21888: 0800316e stmeqda r0, {r1, r2, r3, r5, r6, r8, ip, sp} + 2188c: e1a01006 mov r1, r6 + 21890: e2964000 adds r4, r6, #0 ; 0x0 + 21894: ebf589b9 bl 0xffd83f80 + 21898: 08003170 stmeqda r0, {r4, r5, r6, r8, ip, sp} + 2189c: e1a01004 mov r1, r4 + 218a0: e59d0418 ldr r0, [sp, #1048] + 218a4: e0140094 muls r4, r4, r0 + 218a8: ebf589b4 bl 0xffd83f80 + 218ac: 08003172 stmeqda r0, {r1, r4, r5, r6, r8, ip, sp} + 218b0: e1a01003 mov r1, r3 + 218b4: e0933004 adds r3, r3, r4 + 218b8: ebf589b0 bl 0xffd83f80 + 218bc: 08003174 stmeqda r0, {r2, r4, r5, r6, r8, ip, sp} + 218c0: e59d0434 ldr r0, [sp, #1076] + 218c4: e2800f07 add r0, r0, #28 ; 0x1c + 218c8: ebf58812 bl 0xffd83918 + 218cc: 08003178 stmeqda r0, {r3, r4, r5, r6, r8, ip, sp} + 218d0: e58d0418 str r0, [sp, #1048] + 218d4: ebf589a9 bl 0xffd83f80 + 218d8: 08003176 stmeqda r0, {r1, r2, r4, r5, r6, r8, ip, sp} + 218dc: e1a01005 mov r1, r5 + 218e0: e2954000 adds r4, r5, #0 ; 0x0 + 218e4: ebf589a5 bl 0xffd83f80 + 218e8: 08003178 stmeqda r0, {r3, r4, r5, r6, r8, ip, sp} + 218ec: e1a01004 mov r1, r4 + 218f0: e59d0418 ldr r0, [sp, #1048] + 218f4: e0140094 muls r4, r4, r0 + 218f8: ebf589a0 bl 0xffd83f80 + 218fc: 0800317a stmeqda r0, {r1, r3, r4, r5, r6, r8, ip, sp} + 21900: e1a01003 mov r1, r3 + 21904: e0933004 adds r3, r3, r4 + 21908: ebf5899c bl 0xffd83f80 + 2190c: 0800317c stmeqda r0, {r2, r3, r4, r5, r6, r8, ip, sp} + 21910: e3530000 cmp r3, #0 ; 0x0 + 21914: ebf58999 bl 0xffd83f80 + 21918: 0800317e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, ip, sp} + 2191c: e28cc030 add ip, ip, #48 ; 0x30 + 21920: ba000004 blt 0x21938 + 21924: e1a00fac mov r0, ip, lsr #31 + 21928: e08ff100 add pc, pc, r0, lsl #2 + 2192c: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 21930: ebf58587 bl 0xffd82f54 + 21934: ea00000c b 0x2196c + 21938: ebf58990 bl 0xffd83f80 + 2193c: 08003180 stmeqda r0, {r7, r8, ip, sp} + 21940: e3a00fa9 mov r0, #676 ; 0x2a4 + 21944: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21948: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2194c: ebf587f1 bl 0xffd83918 + 21950: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 21954: e1a04000 mov r4, r0 + 21958: ebf58988 bl 0xffd83f80 + 2195c: 08003182 stmeqda r0, {r1, r7, r8, ip, sp} + 21960: e1a01003 mov r1, r3 + 21964: e0933004 adds r3, r3, r4 + 21968: e28cc008 add ip, ip, #8 ; 0x8 + 2196c: ebf58983 bl 0xffd83f80 + 21970: 08003184 stmeqda r0, {r2, r7, r8, ip, sp} + 21974: e1b00743 movs r0, r3, asr #14 + 21978: e58d041c str r0, [sp, #1052] + 2197c: ebf5897f bl 0xffd83f80 + 21980: 08003186 stmeqda r0, {r1, r2, r7, r8, ip, sp} + 21984: e59d141c ldr r1, [sp, #1052] + 21988: e59d141c ldr r1, [sp, #1052] + 2198c: e2914000 adds r4, r1, #0 ; 0x0 + 21990: ebf5897a bl 0xffd83f80 + 21994: 08003188 stmeqda r0, {r3, r7, r8, ip, sp} + 21998: e1a01004 mov r1, r4 + 2199c: e2544080 subs r4, r4, #128 ; 0x80 + 219a0: ebf58976 bl 0xffd83f80 + 219a4: 0800318a stmeqda r0, {r1, r3, r7, r8, ip, sp} + 219a8: e3b030fc movs r3, #252 ; 0xfc + 219ac: ebf58973 bl 0xffd83f80 + 219b0: 0800318c stmeqda r0, {r2, r3, r7, r8, ip, sp} + 219b4: e1b03283 movs r3, r3, lsl #5 + 219b8: ebf58970 bl 0xffd83f80 + 219bc: 0800318e stmeqda r0, {r1, r2, r3, r7, r8, ip, sp} + 219c0: e1540003 cmp r4, r3 + 219c4: ebf5896d bl 0xffd83f80 + 219c8: 08003190 stmeqda r0, {r4, r7, r8, ip, sp} + 219cc: e28cc015 add ip, ip, #21 ; 0x15 + 219d0: 8a000004 bhi 0x219e8 + 219d4: e1a00fac mov r0, ip, lsr #31 + 219d8: e08ff100 add pc, pc, r0, lsl #2 + 219dc: 08003194 stmeqda r0, {r2, r4, r7, r8, ip, sp} + 219e0: ebf5855b bl 0xffd82f54 + 219e4: ea000007 b 0x21a08 + 219e8: ebf58964 bl 0xffd83f80 + 219ec: 08003192 stmeqda r0, {r1, r4, r7, r8, ip, sp} + 219f0: e28cc003 add ip, ip, #3 ; 0x3 + 219f4: e1a00fac mov r0, ip, lsr #31 + 219f8: e08ff100 add pc, pc, r0, lsl #2 + 219fc: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 21a00: ebf58553 bl 0xffd82f54 + 21a04: eafffe4e b 0x21344 + 21a08: ebf5895c bl 0xffd83f80 + 21a0c: 08003194 stmeqda r0, {r2, r4, r7, r8, ip, sp} + 21a10: e59d0434 ldr r0, [sp, #1076] + 21a14: e2800f00 add r0, r0, #0 ; 0x0 + 21a18: ebf587be bl 0xffd83918 + 21a1c: 08003198 stmeqda r0, {r3, r4, r7, r8, ip, sp} + 21a20: e58d0418 str r0, [sp, #1048] + 21a24: ebf58955 bl 0xffd83f80 + 21a28: 08003196 stmeqda r0, {r1, r2, r4, r7, r8, ip, sp} + 21a2c: e1a01007 mov r1, r7 + 21a30: e2973000 adds r3, r7, #0 ; 0x0 + 21a34: ebf58951 bl 0xffd83f80 + 21a38: 08003198 stmeqda r0, {r3, r4, r7, r8, ip, sp} + 21a3c: e1a01003 mov r1, r3 + 21a40: e59d0418 ldr r0, [sp, #1048] + 21a44: e0130093 muls r3, r3, r0 + 21a48: ebf5894c bl 0xffd83f80 + 21a4c: 0800319a stmeqda r0, {r1, r3, r4, r7, r8, ip, sp} + 21a50: e3b00000 movs r0, #0 ; 0x0 + 21a54: e58d0418 str r0, [sp, #1048] + 21a58: ebf58948 bl 0xffd83f80 + 21a5c: 0800319c stmeqda r0, {r2, r3, r4, r7, r8, ip, sp} + 21a60: e1a01006 mov r1, r6 + 21a64: e2964000 adds r4, r6, #0 ; 0x0 + 21a68: ebf58944 bl 0xffd83f80 + 21a6c: 0800319e stmeqda r0, {r1, r2, r3, r4, r7, r8, ip, sp} + 21a70: e1a01004 mov r1, r4 + 21a74: e59d0418 ldr r0, [sp, #1048] + 21a78: e0140094 muls r4, r4, r0 + 21a7c: ebf5893f bl 0xffd83f80 + 21a80: 080031a0 stmeqda r0, {r5, r7, r8, ip, sp} + 21a84: e1a01003 mov r1, r3 + 21a88: e0933004 adds r3, r3, r4 + 21a8c: ebf5893b bl 0xffd83f80 + 21a90: 080031a2 stmeqda r0, {r1, r5, r7, r8, ip, sp} + 21a94: e59d0434 ldr r0, [sp, #1076] + 21a98: e2800f01 add r0, r0, #4 ; 0x4 + 21a9c: ebf5879d bl 0xffd83918 + 21aa0: 080031a6 stmeqda r0, {r1, r2, r5, r7, r8, ip, sp} + 21aa4: e58d0418 str r0, [sp, #1048] + 21aa8: ebf58934 bl 0xffd83f80 + 21aac: 080031a4 stmeqda r0, {r2, r5, r7, r8, ip, sp} + 21ab0: e1a01005 mov r1, r5 + 21ab4: e2954000 adds r4, r5, #0 ; 0x0 + 21ab8: ebf58930 bl 0xffd83f80 + 21abc: 080031a6 stmeqda r0, {r1, r2, r5, r7, r8, ip, sp} + 21ac0: e1a01004 mov r1, r4 + 21ac4: e59d0418 ldr r0, [sp, #1048] + 21ac8: e0140094 muls r4, r4, r0 + 21acc: ebf5892b bl 0xffd83f80 + 21ad0: 080031a8 stmeqda r0, {r3, r5, r7, r8, ip, sp} + 21ad4: e1a01003 mov r1, r3 + 21ad8: e0933004 adds r3, r3, r4 + 21adc: ebf58927 bl 0xffd83f80 + 21ae0: 080031aa stmeqda r0, {r1, r3, r5, r7, r8, ip, sp} + 21ae4: e3530000 cmp r3, #0 ; 0x0 + 21ae8: ebf58924 bl 0xffd83f80 + 21aec: 080031ac stmeqda r0, {r2, r3, r5, r7, r8, ip, sp} + 21af0: e28cc02b add ip, ip, #43 ; 0x2b + 21af4: ba000004 blt 0x21b0c + 21af8: e1a00fac mov r0, ip, lsr #31 + 21afc: e08ff100 add pc, pc, r0, lsl #2 + 21b00: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 21b04: ebf58512 bl 0xffd82f54 + 21b08: ea00000c b 0x21b40 + 21b0c: ebf5891b bl 0xffd83f80 + 21b10: 080031ae stmeqda r0, {r1, r2, r3, r5, r7, r8, ip, sp} + 21b14: e3a00fa9 mov r0, #676 ; 0x2a4 + 21b18: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21b1c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21b20: ebf5877c bl 0xffd83918 + 21b24: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 21b28: e1a04000 mov r4, r0 + 21b2c: ebf58913 bl 0xffd83f80 + 21b30: 080031b0 stmeqda r0, {r4, r5, r7, r8, ip, sp} + 21b34: e1a01003 mov r1, r3 + 21b38: e0933004 adds r3, r3, r4 + 21b3c: e28cc008 add ip, ip, #8 ; 0x8 + 21b40: ebf5890e bl 0xffd83f80 + 21b44: 080031b2 stmeqda r0, {r1, r4, r5, r7, r8, ip, sp} + 21b48: e1b00743 movs r0, r3, asr #14 + 21b4c: e58d0418 str r0, [sp, #1048] + 21b50: ebf5890a bl 0xffd83f80 + 21b54: 080031b4 stmeqda r0, {r2, r4, r5, r7, r8, ip, sp} + 21b58: e59d0434 ldr r0, [sp, #1076] + 21b5c: e2800f02 add r0, r0, #8 ; 0x8 + 21b60: ebf5876c bl 0xffd83918 + 21b64: 080031b8 stmeqda r0, {r3, r4, r5, r7, r8, ip, sp} + 21b68: e1a04000 mov r4, r0 + 21b6c: ebf58903 bl 0xffd83f80 + 21b70: 080031b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, ip, sp} + 21b74: e1a01007 mov r1, r7 + 21b78: e2973000 adds r3, r7, #0 ; 0x0 + 21b7c: ebf588ff bl 0xffd83f80 + 21b80: 080031b8 stmeqda r0, {r3, r4, r5, r7, r8, ip, sp} + 21b84: e1a01003 mov r1, r3 + 21b88: e0130493 muls r3, r3, r4 + 21b8c: ebf588fb bl 0xffd83f80 + 21b90: 080031ba stmeqda r0, {r1, r3, r4, r5, r7, r8, ip, sp} + 21b94: e59d0434 ldr r0, [sp, #1076] + 21b98: e2800f03 add r0, r0, #12 ; 0xc + 21b9c: ebf5875d bl 0xffd83918 + 21ba0: 080031be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, ip, sp} + 21ba4: e1a07000 mov r7, r0 + 21ba8: ebf588f4 bl 0xffd83f80 + 21bac: 080031bc stmeqda r0, {r2, r3, r4, r5, r7, r8, ip, sp} + 21bb0: e1a01006 mov r1, r6 + 21bb4: e2964000 adds r4, r6, #0 ; 0x0 + 21bb8: ebf588f0 bl 0xffd83f80 + 21bbc: 080031be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, ip, sp} + 21bc0: e1a01004 mov r1, r4 + 21bc4: e0140794 muls r4, r4, r7 + 21bc8: ebf588ec bl 0xffd83f80 + 21bcc: 080031c0 stmeqda r0, {r6, r7, r8, ip, sp} + 21bd0: e1a01003 mov r1, r3 + 21bd4: e0933004 adds r3, r3, r4 + 21bd8: ebf588e8 bl 0xffd83f80 + 21bdc: 080031c2 stmeqda r0, {r1, r6, r7, r8, ip, sp} + 21be0: e59d0434 ldr r0, [sp, #1076] + 21be4: e2800f04 add r0, r0, #16 ; 0x10 + 21be8: ebf5874a bl 0xffd83918 + 21bec: 080031c6 stmeqda r0, {r1, r2, r6, r7, r8, ip, sp} + 21bf0: e1a06000 mov r6, r0 + 21bf4: ebf588e1 bl 0xffd83f80 + 21bf8: 080031c4 stmeqda r0, {r2, r6, r7, r8, ip, sp} + 21bfc: e1a01005 mov r1, r5 + 21c00: e2954000 adds r4, r5, #0 ; 0x0 + 21c04: ebf588dd bl 0xffd83f80 + 21c08: 080031c6 stmeqda r0, {r1, r2, r6, r7, r8, ip, sp} + 21c0c: e1a01004 mov r1, r4 + 21c10: e0140694 muls r4, r4, r6 + 21c14: ebf588d9 bl 0xffd83f80 + 21c18: 080031c8 stmeqda r0, {r3, r6, r7, r8, ip, sp} + 21c1c: e1a01003 mov r1, r3 + 21c20: e0933004 adds r3, r3, r4 + 21c24: ebf588d5 bl 0xffd83f80 + 21c28: 080031ca stmeqda r0, {r1, r3, r6, r7, r8, ip, sp} + 21c2c: e3530000 cmp r3, #0 ; 0x0 + 21c30: ebf588d2 bl 0xffd83f80 + 21c34: 080031cc stmeqda r0, {r2, r3, r6, r7, r8, ip, sp} + 21c38: e28cc030 add ip, ip, #48 ; 0x30 + 21c3c: ba000004 blt 0x21c54 + 21c40: e1a00fac mov r0, ip, lsr #31 + 21c44: e08ff100 add pc, pc, r0, lsl #2 + 21c48: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21c4c: ebf584c0 bl 0xffd82f54 + 21c50: ea00000c b 0x21c88 + 21c54: ebf588c9 bl 0xffd83f80 + 21c58: 080031ce stmeqda r0, {r1, r2, r3, r6, r7, r8, ip, sp} + 21c5c: e3a00fa9 mov r0, #676 ; 0x2a4 + 21c60: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21c64: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21c68: ebf5872a bl 0xffd83918 + 21c6c: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21c70: e1a07000 mov r7, r0 + 21c74: ebf588c1 bl 0xffd83f80 + 21c78: 080031d0 stmeqda r0, {r4, r6, r7, r8, ip, sp} + 21c7c: e1a01003 mov r1, r3 + 21c80: e0933007 adds r3, r3, r7 + 21c84: e28cc008 add ip, ip, #8 ; 0x8 + 21c88: ebf588bc bl 0xffd83f80 + 21c8c: 080031d2 stmeqda r0, {r1, r4, r6, r7, r8, ip, sp} + 21c90: e1b07743 movs r7, r3, asr #14 + 21c94: ebf588b9 bl 0xffd83f80 + 21c98: 080031d4 stmeqda r0, {r2, r4, r6, r7, r8, ip, sp} + 21c9c: e59de418 ldr lr, [sp, #1048] + 21ca0: e1b0340e movs r3, lr, lsl #8 + 21ca4: ebf588b5 bl 0xffd83f80 + 21ca8: 080031d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, ip, sp} + 21cac: e59d141c ldr r1, [sp, #1052] + 21cb0: e59d141c ldr r1, [sp, #1052] + 21cb4: e2914000 adds r4, r1, #0 ; 0x0 + 21cb8: ebf588b0 bl 0xffd83f80 + 21cbc: 080031d8 stmeqda r0, {r3, r4, r6, r7, r8, ip, sp} + 21cc0: e28cc00c add ip, ip, #12 ; 0xc + 21cc4: ebf588ad bl 0xffd83f80 + 21cc8: 080031da stmeqda r0, {r1, r3, r4, r6, r7, r8, ip, sp} + 21ccc: e3a000dd mov r0, #221 ; 0xdd + 21cd0: e3800c31 orr r0, r0, #12544 ; 0x3100 + 21cd4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21cd8: e58d0438 str r0, [sp, #1080] + 21cdc: e28cc003 add ip, ip, #3 ; 0x3 + 21ce0: e1a00fac mov r0, ip, lsr #31 + 21ce4: e08ff100 add pc, pc, r0, lsl #2 + 21ce8: 080c2f20 stmeqda ip, {r5, r8, r9, sl, fp, sp} + 21cec: ebf58498 bl 0xffd82f54 + 21cf0: ea00027d b 0x226ec + 21cf4: 080032b4 stmeqda r0, {r2, r4, r5, r7, r9, ip, sp} + 21cf8: 00000000 andeq r0, r0, r0 + 21cfc: ebf5889f bl 0xffd83f80 + 21d00: 080032b4 stmeqda r0, {r2, r4, r5, r7, r9, ip, sp} + 21d04: e3b03008 movs r3, #8 ; 0x8 + 21d08: ebf5889c bl 0xffd83f80 + 21d0c: 080032b6 stmeqda r0, {r1, r2, r4, r5, r7, r9, ip, sp} + 21d10: e1a01003 mov r1, r3 + 21d14: e0133004 ands r3, r3, r4 + 21d18: ebf58898 bl 0xffd83f80 + 21d1c: 080032b8 stmeqda r0, {r3, r4, r5, r7, r9, ip, sp} + 21d20: e3530000 cmp r3, #0 ; 0x0 + 21d24: ebf58895 bl 0xffd83f80 + 21d28: 080032ba stmeqda r0, {r1, r3, r4, r5, r7, r9, ip, sp} + 21d2c: e28cc00c add ip, ip, #12 ; 0xc + 21d30: 1a000004 bne 0x21d48 + 21d34: e1a00fac mov r0, ip, lsr #31 + 21d38: e08ff100 add pc, pc, r0, lsl #2 + 21d3c: 080032d8 stmeqda r0, {r3, r4, r6, r7, r9, ip, sp} + 21d40: ebf58483 bl 0xffd82f54 + 21d44: ea00004a b 0x21e74 + 21d48: ebf5888c bl 0xffd83f80 + 21d4c: 080032bc stmeqda r0, {r2, r3, r4, r5, r7, r9, ip, sp} + 21d50: e2880014 add r0, r8, #20 ; 0x14 + 21d54: ebf586ef bl 0xffd83918 + 21d58: 080032c0 stmeqda r0, {r6, r7, r9, ip, sp} + 21d5c: e1a03000 mov r3, r0 + 21d60: ebf58886 bl 0xffd83f80 + 21d64: 080032be stmeqda r0, {r1, r2, r3, r4, r5, r7, r9, ip, sp} + 21d68: e3530000 cmp r3, #0 ; 0x0 + 21d6c: ebf58883 bl 0xffd83f80 + 21d70: 080032c0 stmeqda r0, {r6, r7, r9, ip, sp} + 21d74: e28cc00b add ip, ip, #11 ; 0xb + 21d78: ba000004 blt 0x21d90 + 21d7c: e1a00fac mov r0, ip, lsr #31 + 21d80: e08ff100 add pc, pc, r0, lsl #2 + 21d84: 080032c6 stmeqda r0, {r1, r2, r6, r7, r9, ip, sp} + 21d88: ebf58471 bl 0xffd82f54 + 21d8c: ea00000c b 0x21dc4 + 21d90: ebf5887a bl 0xffd83f80 + 21d94: 080032c2 stmeqda r0, {r1, r6, r7, r9, ip, sp} + 21d98: e3a00fb5 mov r0, #724 ; 0x2d4 + 21d9c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21da0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21da4: ebf586db bl 0xffd83918 + 21da8: 080032c6 stmeqda r0, {r1, r2, r6, r7, r9, ip, sp} + 21dac: e1a04000 mov r4, r0 + 21db0: ebf58872 bl 0xffd83f80 + 21db4: 080032c4 stmeqda r0, {r2, r6, r7, r9, ip, sp} + 21db8: e1a01003 mov r1, r3 + 21dbc: e0933004 adds r3, r3, r4 + 21dc0: e28cc008 add ip, ip, #8 ; 0x8 + 21dc4: ebf5886d bl 0xffd83f80 + 21dc8: 080032c6 stmeqda r0, {r1, r2, r6, r7, r9, ip, sp} + 21dcc: e1b00843 movs r0, r3, asr #16 + 21dd0: e58d0418 str r0, [sp, #1048] + 21dd4: ebf58869 bl 0xffd83f80 + 21dd8: 080032c8 stmeqda r0, {r3, r6, r7, r9, ip, sp} + 21ddc: e2880018 add r0, r8, #24 ; 0x18 + 21de0: ebf586cc bl 0xffd83918 + 21de4: 080032cc stmeqda r0, {r2, r3, r6, r7, r9, ip, sp} + 21de8: e1a03000 mov r3, r0 + 21dec: ebf58863 bl 0xffd83f80 + 21df0: 080032ca stmeqda r0, {r1, r3, r6, r7, r9, ip, sp} + 21df4: e3530000 cmp r3, #0 ; 0x0 + 21df8: ebf58860 bl 0xffd83f80 + 21dfc: 080032cc stmeqda r0, {r2, r3, r6, r7, r9, ip, sp} + 21e00: e28cc00e add ip, ip, #14 ; 0xe + 21e04: ba000004 blt 0x21e1c + 21e08: e1a00fac mov r0, ip, lsr #31 + 21e0c: e08ff100 add pc, pc, r0, lsl #2 + 21e10: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 21e14: ebf5844e bl 0xffd82f54 + 21e18: ea000174 b 0x223f0 + 21e1c: ebf58857 bl 0xffd83f80 + 21e20: 080032ce stmeqda r0, {r1, r2, r3, r6, r7, r9, ip, sp} + 21e24: e3a00fb5 mov r0, #724 ; 0x2d4 + 21e28: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21e2c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21e30: ebf586b8 bl 0xffd83918 + 21e34: 080032d2 stmeqda r0, {r1, r4, r6, r7, r9, ip, sp} + 21e38: e1a05000 mov r5, r0 + 21e3c: ebf5884f bl 0xffd83f80 + 21e40: 080032d0 stmeqda r0, {r4, r6, r7, r9, ip, sp} + 21e44: e1a01003 mov r1, r3 + 21e48: e0933005 adds r3, r3, r5 + 21e4c: ebf5884b bl 0xffd83f80 + 21e50: 080032d2 stmeqda r0, {r1, r4, r6, r7, r9, ip, sp} + 21e54: e28cc00b add ip, ip, #11 ; 0xb + 21e58: e1a00fac mov r0, ip, lsr #31 + 21e5c: e08ff100 add pc, pc, r0, lsl #2 + 21e60: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 21e64: ebf5843a bl 0xffd82f54 + 21e68: ea000160 b 0x223f0 + 21e6c: 080032d8 stmeqda r0, {r3, r4, r6, r7, r9, ip, sp} + 21e70: 00000000 andeq r0, r0, r0 + 21e74: ebf58841 bl 0xffd83f80 + 21e78: 080032d8 stmeqda r0, {r3, r4, r6, r7, r9, ip, sp} + 21e7c: e3a00fd3 mov r0, #844 ; 0x34c + 21e80: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21e84: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21e88: ebf586a2 bl 0xffd83918 + 21e8c: 080032dc stmeqda r0, {r2, r3, r4, r6, r7, r9, ip, sp} + 21e90: e1a03000 mov r3, r0 + 21e94: ebf58839 bl 0xffd83f80 + 21e98: 080032da stmeqda r0, {r1, r3, r4, r6, r7, r9, ip, sp} + 21e9c: e2830000 add r0, r3, #0 ; 0x0 + 21ea0: ebf5869c bl 0xffd83918 + 21ea4: 080032de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, ip, sp} + 21ea8: e1a03000 mov r3, r0 + 21eac: ebf58833 bl 0xffd83f80 + 21eb0: 080032dc stmeqda r0, {r2, r3, r4, r6, r7, r9, ip, sp} + 21eb4: e2880014 add r0, r8, #20 ; 0x14 + 21eb8: ebf58696 bl 0xffd83918 + 21ebc: 080032e0 stmeqda r0, {r5, r6, r7, r9, ip, sp} + 21ec0: e1a04000 mov r4, r0 + 21ec4: ebf5882d bl 0xffd83f80 + 21ec8: 080032de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, ip, sp} + 21ecc: e2830000 add r0, r3, #0 ; 0x0 + 21ed0: ebf58690 bl 0xffd83918 + 21ed4: 080032e2 stmeqda r0, {r1, r5, r6, r7, r9, ip, sp} + 21ed8: e1a03000 mov r3, r0 + 21edc: ebf58827 bl 0xffd83f80 + 21ee0: 080032e0 stmeqda r0, {r5, r6, r7, r9, ip, sp} + 21ee4: e1a01004 mov r1, r4 + 21ee8: e0543003 subs r3, r4, r3 + 21eec: ebf58823 bl 0xffd83f80 + 21ef0: 080032e2 stmeqda r0, {r1, r5, r6, r7, r9, ip, sp} + 21ef4: e3530000 cmp r3, #0 ; 0x0 + 21ef8: ebf58820 bl 0xffd83f80 + 21efc: 080032e4 stmeqda r0, {r2, r5, r6, r7, r9, ip, sp} + 21f00: e28cc01d add ip, ip, #29 ; 0x1d + 21f04: ba000004 blt 0x21f1c + 21f08: e1a00fac mov r0, ip, lsr #31 + 21f0c: e08ff100 add pc, pc, r0, lsl #2 + 21f10: 080032ea stmeqda r0, {r1, r3, r5, r6, r7, r9, ip, sp} + 21f14: ebf5840e bl 0xffd82f54 + 21f18: ea00000c b 0x21f50 + 21f1c: ebf58817 bl 0xffd83f80 + 21f20: 080032e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, ip, sp} + 21f24: e3a00e35 mov r0, #848 ; 0x350 + 21f28: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21f2c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21f30: ebf58678 bl 0xffd83918 + 21f34: 080032ea stmeqda r0, {r1, r3, r5, r6, r7, r9, ip, sp} + 21f38: e1a06000 mov r6, r0 + 21f3c: ebf5880f bl 0xffd83f80 + 21f40: 080032e8 stmeqda r0, {r3, r5, r6, r7, r9, ip, sp} + 21f44: e1a01003 mov r1, r3 + 21f48: e0933006 adds r3, r3, r6 + 21f4c: e28cc008 add ip, ip, #8 ; 0x8 + 21f50: ebf5880a bl 0xffd83f80 + 21f54: 080032ea stmeqda r0, {r1, r3, r5, r6, r7, r9, ip, sp} + 21f58: e1b00843 movs r0, r3, asr #16 + 21f5c: e58d0418 str r0, [sp, #1048] + 21f60: ebf58806 bl 0xffd83f80 + 21f64: 080032ec stmeqda r0, {r2, r3, r5, r6, r7, r9, ip, sp} + 21f68: e3a00fd5 mov r0, #852 ; 0x354 + 21f6c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 21f70: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 21f74: ebf58667 bl 0xffd83918 + 21f78: 080032f0 stmeqda r0, {r4, r5, r6, r7, r9, ip, sp} + 21f7c: e1a03000 mov r3, r0 + 21f80: ebf587fe bl 0xffd83f80 + 21f84: 080032ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, ip, sp} + 21f88: e2830000 add r0, r3, #0 ; 0x0 + 21f8c: ebf58661 bl 0xffd83918 + 21f90: 080032f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, ip, sp} + 21f94: e1a03000 mov r3, r0 + 21f98: ebf587f8 bl 0xffd83f80 + 21f9c: 080032f0 stmeqda r0, {r4, r5, r6, r7, r9, ip, sp} + 21fa0: e2880018 add r0, r8, #24 ; 0x18 + 21fa4: ebf5865b bl 0xffd83918 + 21fa8: 080032f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, ip, sp} + 21fac: e1a04000 mov r4, r0 + 21fb0: ebf587f2 bl 0xffd83f80 + 21fb4: 080032f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, ip, sp} + 21fb8: e2830000 add r0, r3, #0 ; 0x0 + 21fbc: ebf58655 bl 0xffd83918 + 21fc0: 080032f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, ip, sp} + 21fc4: e1a03000 mov r3, r0 + 21fc8: ebf587ec bl 0xffd83f80 + 21fcc: 080032f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, ip, sp} + 21fd0: e1a01004 mov r1, r4 + 21fd4: e0543003 subs r3, r4, r3 + 21fd8: ebf587e8 bl 0xffd83f80 + 21fdc: 080032f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, ip, sp} + 21fe0: e3530000 cmp r3, #0 ; 0x0 + 21fe4: ebf587e5 bl 0xffd83f80 + 21fe8: 080032f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, ip, sp} + 21fec: e28cc020 add ip, ip, #32 ; 0x20 + 21ff0: ba000004 blt 0x22008 + 21ff4: e1a00fac mov r0, ip, lsr #31 + 21ff8: e08ff100 add pc, pc, r0, lsl #2 + 21ffc: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 22000: ebf583d3 bl 0xffd82f54 + 22004: ea00000c b 0x2203c + 22008: ebf587dc bl 0xffd83f80 + 2200c: 080032fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, ip, sp} + 22010: e3a00e35 mov r0, #848 ; 0x350 + 22014: e3800a03 orr r0, r0, #12288 ; 0x3000 + 22018: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2201c: ebf5863d bl 0xffd83918 + 22020: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 22024: e1a07000 mov r7, r0 + 22028: ebf587d4 bl 0xffd83f80 + 2202c: 080032fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, ip, sp} + 22030: e1a01003 mov r1, r3 + 22034: e0933007 adds r3, r3, r7 + 22038: e28cc008 add ip, ip, #8 ; 0x8 + 2203c: ebf587cf bl 0xffd83f80 + 22040: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 22044: e1b07843 movs r7, r3, asr #16 + 22048: ebf587cc bl 0xffd83f80 + 2204c: 08003300 stmeqda r0, {r8, r9, ip, sp} + 22050: e59d1418 ldr r1, [sp, #1048] + 22054: e59d1418 ldr r1, [sp, #1048] + 22058: e2914000 adds r4, r1, #0 ; 0x0 + 2205c: ebf587c7 bl 0xffd83f80 + 22060: 08003302 stmeqda r0, {r1, r8, r9, ip, sp} + 22064: e1a01004 mov r1, r4 + 22068: e29440ff adds r4, r4, #255 ; 0xff + 2206c: ebf587c3 bl 0xffd83f80 + 22070: 08003304 stmeqda r0, {r2, r8, r9, ip, sp} + 22074: e3a00fd6 mov r0, #856 ; 0x358 + 22078: e3800a03 orr r0, r0, #12288 ; 0x3000 + 2207c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22080: ebf58624 bl 0xffd83918 + 22084: 08003308 stmeqda r0, {r3, r8, r9, ip, sp} + 22088: e1a03000 mov r3, r0 + 2208c: ebf587bb bl 0xffd83f80 + 22090: 08003306 stmeqda r0, {r1, r2, r8, r9, ip, sp} + 22094: e1540003 cmp r4, r3 + 22098: ebf587b8 bl 0xffd83f80 + 2209c: 08003308 stmeqda r0, {r3, r8, r9, ip, sp} + 220a0: e28cc014 add ip, ip, #20 ; 0x14 + 220a4: 9a000004 bls 0x220bc + 220a8: e1a00fac mov r0, ip, lsr #31 + 220ac: e08ff100 add pc, pc, r0, lsl #2 + 220b0: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 220b4: ebf583a6 bl 0xffd82f54 + 220b8: eafffca1 b 0x21344 + 220bc: ebf587af bl 0xffd83f80 + 220c0: 0800330a stmeqda r0, {r1, r3, r8, r9, ip, sp} + 220c4: e3a00fd7 mov r0, #860 ; 0x35c + 220c8: e3800a03 orr r0, r0, #12288 ; 0x3000 + 220cc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 220d0: ebf58610 bl 0xffd83918 + 220d4: 0800330e stmeqda r0, {r1, r2, r3, r8, r9, ip, sp} + 220d8: e1a03000 mov r3, r0 + 220dc: ebf587a7 bl 0xffd83f80 + 220e0: 0800330c stmeqda r0, {r2, r3, r8, r9, ip, sp} + 220e4: e1570003 cmp r7, r3 + 220e8: ebf587a4 bl 0xffd83f80 + 220ec: 0800330e stmeqda r0, {r1, r2, r3, r8, r9, ip, sp} + 220f0: e28cc00b add ip, ip, #11 ; 0xb + 220f4: ca000004 bgt 0x2210c + 220f8: e1a00fac mov r0, ip, lsr #31 + 220fc: e08ff100 add pc, pc, r0, lsl #2 + 22100: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 22104: ebf58392 bl 0xffd82f54 + 22108: eafffc8d b 0x21344 + 2210c: ebf5879b bl 0xffd83f80 + 22110: 08003310 stmeqda r0, {r4, r8, r9, ip, sp} + 22114: e3a00e36 mov r0, #864 ; 0x360 + 22118: e3800a03 orr r0, r0, #12288 ; 0x3000 + 2211c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22120: ebf585fc bl 0xffd83918 + 22124: 08003314 stmeqda r0, {r2, r4, r8, r9, ip, sp} + 22128: e1a03000 mov r3, r0 + 2212c: ebf58793 bl 0xffd83f80 + 22130: 08003312 stmeqda r0, {r1, r4, r8, r9, ip, sp} + 22134: e1570003 cmp r7, r3 + 22138: ebf58790 bl 0xffd83f80 + 2213c: 08003314 stmeqda r0, {r2, r4, r8, r9, ip, sp} + 22140: e28cc00b add ip, ip, #11 ; 0xb + 22144: da000004 ble 0x2215c + 22148: e1a00fac mov r0, ip, lsr #31 + 2214c: e08ff100 add pc, pc, r0, lsl #2 + 22150: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 22154: ebf5837e bl 0xffd82f54 + 22158: eafffc79 b 0x21344 + 2215c: ebf58787 bl 0xffd83f80 + 22160: 08003316 stmeqda r0, {r1, r2, r4, r8, r9, ip, sp} + 22164: e288001c add r0, r8, #28 ; 0x1c + 22168: ebf585ea bl 0xffd83918 + 2216c: 0800331a stmeqda r0, {r1, r3, r4, r8, r9, ip, sp} + 22170: e1a06000 mov r6, r0 + 22174: ebf58781 bl 0xffd83f80 + 22178: 08003318 stmeqda r0, {r3, r4, r8, r9, ip, sp} + 2217c: e3560000 cmp r6, #0 ; 0x0 + 22180: ebf5877e bl 0xffd83f80 + 22184: 0800331a stmeqda r0, {r1, r3, r4, r8, r9, ip, sp} + 22188: e28cc00b add ip, ip, #11 ; 0xb + 2218c: ca000004 bgt 0x221a4 + 22190: e1a00fac mov r0, ip, lsr #31 + 22194: e08ff100 add pc, pc, r0, lsl #2 + 22198: 08003364 stmeqda r0, {r2, r5, r6, r8, r9, ip, sp} + 2219c: ebf5836c bl 0xffd82f54 + 221a0: ea000065 b 0x2233c + 221a4: ebf58775 bl 0xffd83f80 + 221a8: 0800331c stmeqda r0, {r2, r3, r4, r8, r9, ip, sp} + 221ac: e2880000 add r0, r8, #0 ; 0x0 + 221b0: ebf585ac bl 0xffd83868 + 221b4: 08003320 stmeqda r0, {r5, r8, r9, ip, sp} + 221b8: e1a04000 mov r4, r0 + 221bc: ebf5876f bl 0xffd83f80 + 221c0: 0800331e stmeqda r0, {r1, r2, r3, r4, r8, r9, ip, sp} + 221c4: e3b050c0 movs r5, #192 ; 0xc0 + 221c8: ebf5876c bl 0xffd83f80 + 221cc: 08003320 stmeqda r0, {r5, r8, r9, ip, sp} + 221d0: e1b05205 movs r5, r5, lsl #4 + 221d4: ebf58769 bl 0xffd83f80 + 221d8: 08003322 stmeqda r0, {r1, r5, r8, r9, ip, sp} + 221dc: e1a01005 mov r1, r5 + 221e0: e2953000 adds r3, r5, #0 ; 0x0 + 221e4: ebf58765 bl 0xffd83f80 + 221e8: 08003324 stmeqda r0, {r2, r5, r8, r9, ip, sp} + 221ec: e1a01003 mov r1, r3 + 221f0: e0133004 ands r3, r3, r4 + 221f4: ebf58761 bl 0xffd83f80 + 221f8: 08003326 stmeqda r0, {r1, r2, r5, r8, r9, ip, sp} + 221fc: e1b03403 movs r3, r3, lsl #8 + 22200: ebf5875e bl 0xffd83f80 + 22204: 08003328 stmeqda r0, {r3, r5, r8, r9, ip, sp} + 22208: e59d1424 ldr r1, [sp, #1060] + 2220c: e1a04001 mov r4, r1 + 22210: ebf5875a bl 0xffd83f80 + 22214: 0800332a stmeqda r0, {r1, r3, r5, r8, r9, ip, sp} + 22218: e1a01003 mov r1, r3 + 2221c: e1933004 orrs r3, r3, r4 + 22220: ebf58756 bl 0xffd83f80 + 22224: 0800332c stmeqda r0, {r2, r3, r5, r8, r9, ip, sp} + 22228: e3a00e35 mov r0, #848 ; 0x350 + 2222c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 22230: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22234: ebf585b7 bl 0xffd83918 + 22238: 08003330 stmeqda r0, {r4, r5, r8, r9, ip, sp} + 2223c: e1a04000 mov r4, r0 + 22240: ebf5874e bl 0xffd83f80 + 22244: 0800332e stmeqda r0, {r1, r2, r3, r5, r8, r9, ip, sp} + 22248: e1a01006 mov r1, r6 + 2224c: e0166004 ands r6, r6, r4 + 22250: ebf5874a bl 0xffd83f80 + 22254: 08003330 stmeqda r0, {r4, r5, r8, r9, ip, sp} + 22258: e1b04106 movs r4, r6, lsl #2 + 2225c: ebf58747 bl 0xffd83f80 + 22260: 08003332 stmeqda r0, {r1, r4, r5, r8, r9, ip, sp} + 22264: e1a01003 mov r1, r3 + 22268: e1933004 orrs r3, r3, r4 + 2226c: ebf58743 bl 0xffd83f80 + 22270: 08003334 stmeqda r0, {r2, r4, r5, r8, r9, ip, sp} + 22274: e1a01008 mov r1, r8 + 22278: e2984000 adds r4, r8, #0 ; 0x0 + 2227c: ebf5873f bl 0xffd83f80 + 22280: 08003336 stmeqda r0, {r1, r2, r4, r5, r8, r9, ip, sp} + 22284: e1a01004 mov r1, r4 + 22288: e294402b adds r4, r4, #43 ; 0x2b + 2228c: ebf5873b bl 0xffd83f80 + 22290: 08003338 stmeqda r0, {r3, r4, r5, r8, r9, ip, sp} + 22294: e2840000 add r0, r4, #0 ; 0x0 + 22298: ebf58547 bl 0xffd837bc + 2229c: 0800333c stmeqda r0, {r2, r3, r4, r5, r8, r9, ip, sp} + 222a0: e1a05000 mov r5, r0 + 222a4: ebf58735 bl 0xffd83f80 + 222a8: 0800333a stmeqda r0, {r1, r3, r4, r5, r8, r9, ip, sp} + 222ac: e3b04003 movs r4, #3 ; 0x3 + 222b0: ebf58732 bl 0xffd83f80 + 222b4: 0800333c stmeqda r0, {r2, r3, r4, r5, r8, r9, ip, sp} + 222b8: e1a01004 mov r1, r4 + 222bc: e0144005 ands r4, r4, r5 + 222c0: ebf5872e bl 0xffd83f80 + 222c4: 0800333e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, ip, sp} + 222c8: e1a01003 mov r1, r3 + 222cc: e1933004 orrs r3, r3, r4 + 222d0: ebf5872a bl 0xffd83f80 + 222d4: 08003340 stmeqda r0, {r6, r8, r9, ip, sp} + 222d8: e59d1428 ldr r1, [sp, #1064] + 222dc: e1a05001 mov r5, r1 + 222e0: ebf58726 bl 0xffd83f80 + 222e4: 08003342 stmeqda r0, {r1, r6, r8, r9, ip, sp} + 222e8: e2850000 add r0, r5, #0 ; 0x0 + 222ec: ebf58589 bl 0xffd83918 + 222f0: 08003346 stmeqda r0, {r1, r2, r6, r8, r9, ip, sp} + 222f4: e1a04000 mov r4, r0 + 222f8: ebf58720 bl 0xffd83f80 + 222fc: 08003344 stmeqda r0, {r2, r6, r8, r9, ip, sp} + 22300: e28cc047 add ip, ip, #71 ; 0x47 + 22304: ebf5871d bl 0xffd83f80 + 22308: 08003346 stmeqda r0, {r1, r2, r6, r8, r9, ip, sp} + 2230c: e3a00049 mov r0, #73 ; 0x49 + 22310: e3800c33 orr r0, r0, #13056 ; 0x3300 + 22314: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22318: e58d0438 str r0, [sp, #1080] + 2231c: e28cc003 add ip, ip, #3 ; 0x3 + 22320: e1a00fac mov r0, ip, lsr #31 + 22324: e08ff100 add pc, pc, r0, lsl #2 + 22328: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 2232c: ebf58308 bl 0xffd82f54 + 22330: eaff8ad5 b 0x4e8c + 22334: 08003364 stmeqda r0, {r2, r5, r6, r8, r9, ip, sp} + 22338: 00000000 andeq r0, r0, r0 + 2233c: ebf5870f bl 0xffd83f80 + 22340: 08003364 stmeqda r0, {r2, r5, r6, r8, r9, ip, sp} + 22344: e3a00f1a mov r0, #104 ; 0x68 + 22348: e3800b0d orr r0, r0, #13312 ; 0x3400 + 2234c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22350: ebf58570 bl 0xffd83918 + 22354: 08003368 stmeqda r0, {r3, r5, r6, r8, r9, ip, sp} + 22358: e1a03000 mov r3, r0 + 2235c: ebf58707 bl 0xffd83f80 + 22360: 08003366 stmeqda r0, {r1, r2, r5, r6, r8, r9, ip, sp} + 22364: e3b0400f movs r4, #15 ; 0xf + 22368: ebf58704 bl 0xffd83f80 + 2236c: 08003368 stmeqda r0, {r3, r5, r6, r8, r9, ip, sp} + 22370: e1a01006 mov r1, r6 + 22374: e0166004 ands r6, r6, r4 + 22378: ebf58700 bl 0xffd83f80 + 2237c: 0800336a stmeqda r0, {r1, r3, r5, r6, r8, r9, ip, sp} + 22380: e2830000 add r0, r3, #0 ; 0x0 + 22384: ebf58563 bl 0xffd83918 + 22388: 0800336e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, ip, sp} + 2238c: e1a05000 mov r5, r0 + 22390: ebf586fa bl 0xffd83f80 + 22394: 0800336c stmeqda r0, {r2, r3, r5, r6, r8, r9, ip, sp} + 22398: e1a01008 mov r1, r8 + 2239c: e2983000 adds r3, r8, #0 ; 0x0 + 223a0: ebf586f6 bl 0xffd83f80 + 223a4: 0800336e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, ip, sp} + 223a8: e1a01006 mov r1, r6 + 223ac: e2964000 adds r4, r6, #0 ; 0x0 + 223b0: ebf586f2 bl 0xffd83f80 + 223b4: 08003370 stmeqda r0, {r4, r5, r6, r8, r9, ip, sp} + 223b8: ebf586f0 bl 0xffd83f80 + 223bc: 08003372 stmeqda r0, {r1, r4, r5, r6, r8, r9, ip, sp} + 223c0: e3a00075 mov r0, #117 ; 0x75 + 223c4: e3800c33 orr r0, r0, #13056 ; 0x3300 + 223c8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 223cc: e58d0438 str r0, [sp, #1080] + 223d0: e28cc01c add ip, ip, #28 ; 0x1c + 223d4: e1a00fac mov r0, ip, lsr #31 + 223d8: e08ff100 add pc, pc, r0, lsl #2 + 223dc: 080c31e4 stmeqda ip, {r2, r5, r6, r7, r8, ip, sp} + 223e0: ebf582db bl 0xffd82f54 + 223e4: eaffbff9 b 0x123d0 + 223e8: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 223ec: 00000000 andeq r0, r0, r0 + 223f0: ebf586e2 bl 0xffd83f80 + 223f4: 080032fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, ip, sp} + 223f8: e1b07843 movs r7, r3, asr #16 + 223fc: ebf586df bl 0xffd83f80 + 22400: 08003300 stmeqda r0, {r8, r9, ip, sp} + 22404: e59d1418 ldr r1, [sp, #1048] + 22408: e59d1418 ldr r1, [sp, #1048] + 2240c: e2914000 adds r4, r1, #0 ; 0x0 + 22410: ebf586da bl 0xffd83f80 + 22414: 08003302 stmeqda r0, {r1, r8, r9, ip, sp} + 22418: e1a01004 mov r1, r4 + 2241c: e29440ff adds r4, r4, #255 ; 0xff + 22420: ebf586d6 bl 0xffd83f80 + 22424: 08003304 stmeqda r0, {r2, r8, r9, ip, sp} + 22428: e3a00fd6 mov r0, #856 ; 0x358 + 2242c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 22430: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22434: ebf58537 bl 0xffd83918 + 22438: 08003308 stmeqda r0, {r3, r8, r9, ip, sp} + 2243c: e1a03000 mov r3, r0 + 22440: ebf586ce bl 0xffd83f80 + 22444: 08003306 stmeqda r0, {r1, r2, r8, r9, ip, sp} + 22448: e1540003 cmp r4, r3 + 2244c: ebf586cb bl 0xffd83f80 + 22450: 08003308 stmeqda r0, {r3, r8, r9, ip, sp} + 22454: e28cc014 add ip, ip, #20 ; 0x14 + 22458: 9a000004 bls 0x22470 + 2245c: e1a00fac mov r0, ip, lsr #31 + 22460: e08ff100 add pc, pc, r0, lsl #2 + 22464: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 22468: ebf582b9 bl 0xffd82f54 + 2246c: eafffbb4 b 0x21344 + 22470: ebf586c2 bl 0xffd83f80 + 22474: 0800330a stmeqda r0, {r1, r3, r8, r9, ip, sp} + 22478: e3a00fd7 mov r0, #860 ; 0x35c + 2247c: e3800a03 orr r0, r0, #12288 ; 0x3000 + 22480: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22484: ebf58523 bl 0xffd83918 + 22488: 0800330e stmeqda r0, {r1, r2, r3, r8, r9, ip, sp} + 2248c: e1a03000 mov r3, r0 + 22490: ebf586ba bl 0xffd83f80 + 22494: 0800330c stmeqda r0, {r2, r3, r8, r9, ip, sp} + 22498: e1570003 cmp r7, r3 + 2249c: ebf586b7 bl 0xffd83f80 + 224a0: 0800330e stmeqda r0, {r1, r2, r3, r8, r9, ip, sp} + 224a4: e28cc00b add ip, ip, #11 ; 0xb + 224a8: ca000004 bgt 0x224c0 + 224ac: e1a00fac mov r0, ip, lsr #31 + 224b0: e08ff100 add pc, pc, r0, lsl #2 + 224b4: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 224b8: ebf582a5 bl 0xffd82f54 + 224bc: eafffba0 b 0x21344 + 224c0: ebf586ae bl 0xffd83f80 + 224c4: 08003310 stmeqda r0, {r4, r8, r9, ip, sp} + 224c8: e3a00e36 mov r0, #864 ; 0x360 + 224cc: e3800a03 orr r0, r0, #12288 ; 0x3000 + 224d0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 224d4: ebf5850f bl 0xffd83918 + 224d8: 08003314 stmeqda r0, {r2, r4, r8, r9, ip, sp} + 224dc: e1a03000 mov r3, r0 + 224e0: ebf586a6 bl 0xffd83f80 + 224e4: 08003312 stmeqda r0, {r1, r4, r8, r9, ip, sp} + 224e8: e1570003 cmp r7, r3 + 224ec: ebf586a3 bl 0xffd83f80 + 224f0: 08003314 stmeqda r0, {r2, r4, r8, r9, ip, sp} + 224f4: e28cc00b add ip, ip, #11 ; 0xb + 224f8: da000004 ble 0x22510 + 224fc: e1a00fac mov r0, ip, lsr #31 + 22500: e08ff100 add pc, pc, r0, lsl #2 + 22504: 08003380 stmeqda r0, {r7, r8, r9, ip, sp} + 22508: ebf58291 bl 0xffd82f54 + 2250c: eafffb8c b 0x21344 + 22510: ebf5869a bl 0xffd83f80 + 22514: 08003316 stmeqda r0, {r1, r2, r4, r8, r9, ip, sp} + 22518: e288001c add r0, r8, #28 ; 0x1c + 2251c: ebf584fd bl 0xffd83918 + 22520: 0800331a stmeqda r0, {r1, r3, r4, r8, r9, ip, sp} + 22524: e1a06000 mov r6, r0 + 22528: ebf58694 bl 0xffd83f80 + 2252c: 08003318 stmeqda r0, {r3, r4, r8, r9, ip, sp} + 22530: e3560000 cmp r6, #0 ; 0x0 + 22534: ebf58691 bl 0xffd83f80 + 22538: 0800331a stmeqda r0, {r1, r3, r4, r8, r9, ip, sp} + 2253c: e28cc00b add ip, ip, #11 ; 0xb + 22540: ca000004 bgt 0x22558 + 22544: e1a00fac mov r0, ip, lsr #31 + 22548: e08ff100 add pc, pc, r0, lsl #2 + 2254c: 08003364 stmeqda r0, {r2, r5, r6, r8, r9, ip, sp} + 22550: ebf5827f bl 0xffd82f54 + 22554: eaffff78 b 0x2233c + 22558: ebf58688 bl 0xffd83f80 + 2255c: 0800331c stmeqda r0, {r2, r3, r4, r8, r9, ip, sp} + 22560: e2880000 add r0, r8, #0 ; 0x0 + 22564: ebf584bf bl 0xffd83868 + 22568: 08003320 stmeqda r0, {r5, r8, r9, ip, sp} + 2256c: e1a04000 mov r4, r0 + 22570: ebf58682 bl 0xffd83f80 + 22574: 0800331e stmeqda r0, {r1, r2, r3, r4, r8, r9, ip, sp} + 22578: e3b050c0 movs r5, #192 ; 0xc0 + 2257c: ebf5867f bl 0xffd83f80 + 22580: 08003320 stmeqda r0, {r5, r8, r9, ip, sp} + 22584: e1b05205 movs r5, r5, lsl #4 + 22588: ebf5867c bl 0xffd83f80 + 2258c: 08003322 stmeqda r0, {r1, r5, r8, r9, ip, sp} + 22590: e1a01005 mov r1, r5 + 22594: e2953000 adds r3, r5, #0 ; 0x0 + 22598: ebf58678 bl 0xffd83f80 + 2259c: 08003324 stmeqda r0, {r2, r5, r8, r9, ip, sp} + 225a0: e1a01003 mov r1, r3 + 225a4: e0133004 ands r3, r3, r4 + 225a8: ebf58674 bl 0xffd83f80 + 225ac: 08003326 stmeqda r0, {r1, r2, r5, r8, r9, ip, sp} + 225b0: e1b03403 movs r3, r3, lsl #8 + 225b4: ebf58671 bl 0xffd83f80 + 225b8: 08003328 stmeqda r0, {r3, r5, r8, r9, ip, sp} + 225bc: e59d1424 ldr r1, [sp, #1060] + 225c0: e1a04001 mov r4, r1 + 225c4: ebf5866d bl 0xffd83f80 + 225c8: 0800332a stmeqda r0, {r1, r3, r5, r8, r9, ip, sp} + 225cc: e1a01003 mov r1, r3 + 225d0: e1933004 orrs r3, r3, r4 + 225d4: ebf58669 bl 0xffd83f80 + 225d8: 0800332c stmeqda r0, {r2, r3, r5, r8, r9, ip, sp} + 225dc: e3a00e35 mov r0, #848 ; 0x350 + 225e0: e3800a03 orr r0, r0, #12288 ; 0x3000 + 225e4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 225e8: ebf584ca bl 0xffd83918 + 225ec: 08003330 stmeqda r0, {r4, r5, r8, r9, ip, sp} + 225f0: e1a04000 mov r4, r0 + 225f4: ebf58661 bl 0xffd83f80 + 225f8: 0800332e stmeqda r0, {r1, r2, r3, r5, r8, r9, ip, sp} + 225fc: e1a01006 mov r1, r6 + 22600: e0166004 ands r6, r6, r4 + 22604: ebf5865d bl 0xffd83f80 + 22608: 08003330 stmeqda r0, {r4, r5, r8, r9, ip, sp} + 2260c: e1b04106 movs r4, r6, lsl #2 + 22610: ebf5865a bl 0xffd83f80 + 22614: 08003332 stmeqda r0, {r1, r4, r5, r8, r9, ip, sp} + 22618: e1a01003 mov r1, r3 + 2261c: e1933004 orrs r3, r3, r4 + 22620: ebf58656 bl 0xffd83f80 + 22624: 08003334 stmeqda r0, {r2, r4, r5, r8, r9, ip, sp} + 22628: e1a01008 mov r1, r8 + 2262c: e2984000 adds r4, r8, #0 ; 0x0 + 22630: ebf58652 bl 0xffd83f80 + 22634: 08003336 stmeqda r0, {r1, r2, r4, r5, r8, r9, ip, sp} + 22638: e1a01004 mov r1, r4 + 2263c: e294402b adds r4, r4, #43 ; 0x2b + 22640: ebf5864e bl 0xffd83f80 + 22644: 08003338 stmeqda r0, {r3, r4, r5, r8, r9, ip, sp} + 22648: e2840000 add r0, r4, #0 ; 0x0 + 2264c: ebf5845a bl 0xffd837bc + 22650: 0800333c stmeqda r0, {r2, r3, r4, r5, r8, r9, ip, sp} + 22654: e1a05000 mov r5, r0 + 22658: ebf58648 bl 0xffd83f80 + 2265c: 0800333a stmeqda r0, {r1, r3, r4, r5, r8, r9, ip, sp} + 22660: e3b04003 movs r4, #3 ; 0x3 + 22664: ebf58645 bl 0xffd83f80 + 22668: 0800333c stmeqda r0, {r2, r3, r4, r5, r8, r9, ip, sp} + 2266c: e1a01004 mov r1, r4 + 22670: e0144005 ands r4, r4, r5 + 22674: ebf58641 bl 0xffd83f80 + 22678: 0800333e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, ip, sp} + 2267c: e1a01003 mov r1, r3 + 22680: e1933004 orrs r3, r3, r4 + 22684: ebf5863d bl 0xffd83f80 + 22688: 08003340 stmeqda r0, {r6, r8, r9, ip, sp} + 2268c: e59d1428 ldr r1, [sp, #1064] + 22690: e1a05001 mov r5, r1 + 22694: ebf58639 bl 0xffd83f80 + 22698: 08003342 stmeqda r0, {r1, r6, r8, r9, ip, sp} + 2269c: e2850000 add r0, r5, #0 ; 0x0 + 226a0: ebf5849c bl 0xffd83918 + 226a4: 08003346 stmeqda r0, {r1, r2, r6, r8, r9, ip, sp} + 226a8: e1a04000 mov r4, r0 + 226ac: ebf58633 bl 0xffd83f80 + 226b0: 08003344 stmeqda r0, {r2, r6, r8, r9, ip, sp} + 226b4: ebf58631 bl 0xffd83f80 + 226b8: 08003346 stmeqda r0, {r1, r2, r6, r8, r9, ip, sp} + 226bc: e3a00049 mov r0, #73 ; 0x49 + 226c0: e3800c33 orr r0, r0, #13056 ; 0x3300 + 226c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 226c8: e58d0438 str r0, [sp, #1080] + 226cc: e28cc04a add ip, ip, #74 ; 0x4a + 226d0: e1a00fac mov r0, ip, lsr #31 + 226d4: e08ff100 add pc, pc, r0, lsl #2 + 226d8: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 226dc: ebf5821c bl 0xffd82f54 + 226e0: eaff89e9 b 0x4e8c + 226e4: 080c2f20 stmeqda ip, {r5, r8, r9, sl, fp, sp} + 226e8: 00000000 andeq r0, r0, r0 + 226ec: ebf58623 bl 0xffd83f80 + 226f0: 080c2f20 stmeqda ip, {r5, r8, r9, sl, fp, sp} + 226f4: ebf5833f bl 0xffd833f8 + 226f8: ebf58620 bl 0xffd83f80 + 226fc: 080c2f22 stmeqda ip, {r1, r5, r8, r9, sl, fp, sp} + 22700: e59d0438 ldr r0, [sp, #1080] + 22704: e28cc006 add ip, ip, #6 ; 0x6 + 22708: eaf58270 b 0xffd830d0 + 2270c: 0800339e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, ip, sp} + 22710: 00000000 andeq r0, r0, r0 + 22714: ebf58619 bl 0xffd83f80 + 22718: 0800339e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, ip, sp} + 2271c: e3a00f1d mov r0, #116 ; 0x74 + 22720: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22724: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22728: ebf5847a bl 0xffd83918 + 2272c: 080033a2 stmeqda r0, {r1, r5, r7, r8, r9, ip, sp} + 22730: e1a03000 mov r3, r0 + 22734: ebf58611 bl 0xffd83f80 + 22738: 080033a0 stmeqda r0, {r5, r7, r8, r9, ip, sp} + 2273c: e3b04000 movs r4, #0 ; 0x0 + 22740: ebf5860e bl 0xffd83f80 + 22744: 080033a2 stmeqda r0, {r1, r5, r7, r8, r9, ip, sp} + 22748: e2830000 add r0, r3, #0 ; 0x0 + 2274c: e1a01004 mov r1, r4 + 22750: ebf5839d bl 0xffd835cc + 22754: 080033a4 stmeqda r0, {r2, r5, r7, r8, r9, ip, sp} + 22758: ebf58608 bl 0xffd83f80 + 2275c: 080033a4 stmeqda r0, {r2, r5, r7, r8, r9, ip, sp} + 22760: e3a00f1e mov r0, #120 ; 0x78 + 22764: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22768: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2276c: ebf58469 bl 0xffd83918 + 22770: 080033a8 stmeqda r0, {r3, r5, r7, r8, r9, ip, sp} + 22774: e1a03000 mov r3, r0 + 22778: ebf58600 bl 0xffd83f80 + 2277c: 080033a6 stmeqda r0, {r1, r2, r5, r7, r8, r9, ip, sp} + 22780: e2830000 add r0, r3, #0 ; 0x0 + 22784: e1a01004 mov r1, r4 + 22788: ebf5838f bl 0xffd835cc + 2278c: 080033a8 stmeqda r0, {r3, r5, r7, r8, r9, ip, sp} + 22790: ebf585fa bl 0xffd83f80 + 22794: 080033a8 stmeqda r0, {r3, r5, r7, r8, r9, ip, sp} + 22798: e1a00004 mov r0, r4 + 2279c: e58d0420 str r0, [sp, #1056] + 227a0: ebf585f6 bl 0xffd83f80 + 227a4: 080033aa stmeqda r0, {r1, r3, r5, r7, r8, r9, ip, sp} + 227a8: e3a00f1f mov r0, #124 ; 0x7c + 227ac: e3800b0d orr r0, r0, #13312 ; 0x3400 + 227b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 227b4: ebf58457 bl 0xffd83918 + 227b8: 080033ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, ip, sp} + 227bc: e1a04000 mov r4, r0 + 227c0: ebf585ee bl 0xffd83f80 + 227c4: 080033ac stmeqda r0, {r2, r3, r5, r7, r8, r9, ip, sp} + 227c8: e59d1420 ldr r1, [sp, #1056] + 227cc: e1a00001 mov r0, r1 + 227d0: e58d0418 str r0, [sp, #1048] + 227d4: ebf585e9 bl 0xffd83f80 + 227d8: 080033ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, ip, sp} + 227dc: e59de418 ldr lr, [sp, #1048] + 227e0: e1b0310e movs r3, lr, lsl #2 + 227e4: ebf585e5 bl 0xffd83f80 + 227e8: 080033b0 stmeqda r0, {r4, r5, r7, r8, r9, ip, sp} + 227ec: e1a01003 mov r1, r3 + 227f0: e0933004 adds r3, r3, r4 + 227f4: ebf585e1 bl 0xffd83f80 + 227f8: 080033b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, ip, sp} + 227fc: e2830000 add r0, r3, #0 ; 0x0 + 22800: ebf58444 bl 0xffd83918 + 22804: 080033b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, ip, sp} + 22808: e1a07000 mov r7, r0 + 2280c: ebf585db bl 0xffd83f80 + 22810: 080033b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, ip, sp} + 22814: e3570001 cmp r7, #1 ; 0x1 + 22818: ebf585d8 bl 0xffd83f80 + 2281c: 080033b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, ip, sp} + 22820: e28cc031 add ip, ip, #49 ; 0x31 + 22824: 8a000004 bhi 0x2283c + 22828: e1a00fac mov r0, ip, lsr #31 + 2282c: e08ff100 add pc, pc, r0, lsl #2 + 22830: 080033d0 stmeqda r0, {r4, r6, r7, r8, r9, ip, sp} + 22834: ebf581c6 bl 0xffd82f54 + 22838: ea00002b b 0x228ec + 2283c: ebf585cf bl 0xffd83f80 + 22840: 080033b8 stmeqda r0, {r3, r4, r5, r7, r8, r9, ip, sp} + 22844: e3a00dd2 mov r0, #13440 ; 0x3480 + 22848: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2284c: ebf58431 bl 0xffd83918 + 22850: 080033bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22854: e58d0418 str r0, [sp, #1048] + 22858: ebf585c8 bl 0xffd83f80 + 2285c: 080033ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, ip, sp} + 22860: e3a00f1d mov r0, #116 ; 0x74 + 22864: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22868: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2286c: ebf58429 bl 0xffd83918 + 22870: 080033be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22874: e1a08000 mov r8, r0 + 22878: ebf585c0 bl 0xffd83f80 + 2287c: 080033bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22880: e2870000 add r0, r7, #0 ; 0x0 + 22884: ebf58423 bl 0xffd83918 + 22888: 080033c0 stmeqda r0, {r6, r7, r8, r9, ip, sp} + 2288c: e1a03000 mov r3, r0 + 22890: ebf585ba bl 0xffd83f80 + 22894: 080033be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22898: e59d0418 ldr r0, [sp, #1048] + 2289c: e2800000 add r0, r0, #0 ; 0x0 + 228a0: ebf5841c bl 0xffd83918 + 228a4: 080033c2 stmeqda r0, {r1, r6, r7, r8, r9, ip, sp} + 228a8: e1a04000 mov r4, r0 + 228ac: ebf585b3 bl 0xffd83f80 + 228b0: 080033c0 stmeqda r0, {r6, r7, r8, r9, ip, sp} + 228b4: ebf585b1 bl 0xffd83f80 + 228b8: 080033c2 stmeqda r0, {r1, r6, r7, r8, r9, ip, sp} + 228bc: e3a000c5 mov r0, #197 ; 0xc5 + 228c0: e3800c33 orr r0, r0, #13056 ; 0x3300 + 228c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 228c8: e58d0438 str r0, [sp, #1080] + 228cc: e28cc01a add ip, ip, #26 ; 0x1a + 228d0: e1a00fac mov r0, ip, lsr #31 + 228d4: e08ff100 add pc, pc, r0, lsl #2 + 228d8: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 228dc: ebf5819c bl 0xffd82f54 + 228e0: eaff8969 b 0x4e8c + 228e4: 080033d0 stmeqda r0, {r4, r6, r7, r8, r9, ip, sp} + 228e8: 00000000 andeq r0, r0, r0 + 228ec: ebf585a3 bl 0xffd83f80 + 228f0: 080033d0 stmeqda r0, {r4, r6, r7, r8, r9, ip, sp} + 228f4: e3570001 cmp r7, #1 ; 0x1 + 228f8: ebf585a0 bl 0xffd83f80 + 228fc: 080033d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, ip, sp} + 22900: e28cc006 add ip, ip, #6 ; 0x6 + 22904: 0a000004 beq 0x2291c + 22908: e1a00fac mov r0, ip, lsr #31 + 2290c: e08ff100 add pc, pc, r0, lsl #2 + 22910: 0800340e stmeqda r0, {r1, r2, r3, sl, ip, sp} + 22914: ebf5818e bl 0xffd82f54 + 22918: ea00006f b 0x22adc + 2291c: ebf58597 bl 0xffd83f80 + 22920: 080033d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, ip, sp} + 22924: e3a00f21 mov r0, #132 ; 0x84 + 22928: e3800b0d orr r0, r0, #13312 ; 0x3400 + 2292c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22930: ebf583f8 bl 0xffd83918 + 22934: 080033d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, ip, sp} + 22938: e1a06000 mov r6, r0 + 2293c: ebf5858f bl 0xffd83f80 + 22940: 080033d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, ip, sp} + 22944: e3a00f22 mov r0, #136 ; 0x88 + 22948: e3800b0d orr r0, r0, #13312 ; 0x3400 + 2294c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22950: ebf583f0 bl 0xffd83918 + 22954: 080033da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, ip, sp} + 22958: e1a03000 mov r3, r0 + 2295c: ebf58587 bl 0xffd83f80 + 22960: 080033d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, ip, sp} + 22964: e2830000 add r0, r3, #0 ; 0x0 + 22968: ebf583ea bl 0xffd83918 + 2296c: 080033dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, ip, sp} + 22970: e1a05000 mov r5, r0 + 22974: ebf58581 bl 0xffd83f80 + 22978: 080033da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, ip, sp} + 2297c: e1b04105 movs r4, r5, lsl #2 + 22980: ebf5857e bl 0xffd83f80 + 22984: 080033dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, ip, sp} + 22988: e2860000 add r0, r6, #0 ; 0x0 + 2298c: ebf583e1 bl 0xffd83918 + 22990: 080033e0 stmeqda r0, {r5, r6, r7, r8, r9, ip, sp} + 22994: e1a03000 mov r3, r0 + 22998: ebf58578 bl 0xffd83f80 + 2299c: 080033de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, ip, sp} + 229a0: e1a01003 mov r1, r3 + 229a4: e0937004 adds r7, r3, r4 + 229a8: ebf58574 bl 0xffd83f80 + 229ac: 080033e0 stmeqda r0, {r5, r6, r7, r8, r9, ip, sp} + 229b0: e3b08000 movs r8, #0 ; 0x0 + 229b4: ebf58571 bl 0xffd83f80 + 229b8: 080033e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, ip, sp} + 229bc: e1580005 cmp r8, r5 + 229c0: ebf5856e bl 0xffd83f80 + 229c4: 080033e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, ip, sp} + 229c8: e28cc023 add ip, ip, #35 ; 0x23 + 229cc: 3a000004 bcc 0x229e4 + 229d0: e1a00fac mov r0, ip, lsr #31 + 229d4: e08ff100 add pc, pc, r0, lsl #2 + 229d8: 0800340e stmeqda r0, {r1, r2, r3, sl, ip, sp} + 229dc: ebf5815c bl 0xffd82f54 + 229e0: ea00003d b 0x22adc + 229e4: ebf58565 bl 0xffd83f80 + 229e8: 080033e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, ip, sp} + 229ec: e3a00dd2 mov r0, #13440 ; 0x3480 + 229f0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 229f4: ebf583c7 bl 0xffd83918 + 229f8: 080033ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, ip, sp} + 229fc: e58d041c str r0, [sp, #1052] + 22a00: ebf5855e bl 0xffd83f80 + 22a04: 080033e8 stmeqda r0, {r3, r5, r6, r7, r8, r9, ip, sp} + 22a08: e3a00f23 mov r0, #140 ; 0x8c + 22a0c: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22a10: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22a14: ebf583bf bl 0xffd83918 + 22a18: 080033ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, ip, sp} + 22a1c: e58d0418 str r0, [sp, #1048] + 22a20: ebf58556 bl 0xffd83f80 + 22a24: 080033ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, ip, sp} + 22a28: e2870003 add r0, r7, #3 ; 0x3 + 22a2c: ebf58362 bl 0xffd837bc + 22a30: 080033ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, ip, sp} + 22a34: e1a04000 mov r4, r0 + 22a38: ebf58550 bl 0xffd83f80 + 22a3c: 080033ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, ip, sp} + 22a40: e3b0302c movs r3, #44 ; 0x2c + 22a44: ebf5854d bl 0xffd83f80 + 22a48: 080033ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r8, r9, ip, sp} + 22a4c: e1a01004 mov r1, r4 + 22a50: e0140394 muls r4, r4, r3 + 22a54: ebf58549 bl 0xffd83f80 + 22a58: 080033f0 stmeqda r0, {r4, r5, r6, r7, r8, r9, ip, sp} + 22a5c: e59d0418 ldr r0, [sp, #1048] + 22a60: e2800000 add r0, r0, #0 ; 0x0 + 22a64: ebf583ab bl 0xffd83918 + 22a68: 080033f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, ip, sp} + 22a6c: e1a03000 mov r3, r0 + 22a70: ebf58542 bl 0xffd83f80 + 22a74: 080033f2 stmeqda r0, {r1, r4, r5, r6, r7, r8, r9, ip, sp} + 22a78: e1a01003 mov r1, r3 + 22a7c: e0933004 adds r3, r3, r4 + 22a80: ebf5853e bl 0xffd83f80 + 22a84: 080033f4 stmeqda r0, {r2, r4, r5, r6, r7, r8, r9, ip, sp} + 22a88: e59d041c ldr r0, [sp, #1052] + 22a8c: e2800000 add r0, r0, #0 ; 0x0 + 22a90: ebf583a0 bl 0xffd83918 + 22a94: 080033f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, ip, sp} + 22a98: e1a04000 mov r4, r0 + 22a9c: ebf58537 bl 0xffd83f80 + 22aa0: 080033f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r8, r9, ip, sp} + 22aa4: ebf58535 bl 0xffd83f80 + 22aa8: 080033f8 stmeqda r0, {r3, r4, r5, r6, r7, r8, r9, ip, sp} + 22aac: e3a000fb mov r0, #251 ; 0xfb + 22ab0: e3800c33 orr r0, r0, #13056 ; 0x3300 + 22ab4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22ab8: e58d0438 str r0, [sp, #1080] + 22abc: e28cc028 add ip, ip, #40 ; 0x28 + 22ac0: e1a00fac mov r0, ip, lsr #31 + 22ac4: e08ff100 add pc, pc, r0, lsl #2 + 22ac8: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 22acc: ebf58120 bl 0xffd82f54 + 22ad0: eaff88ed b 0x4e8c + 22ad4: 0800340e stmeqda r0, {r1, r2, r3, sl, ip, sp} + 22ad8: 00000000 andeq r0, r0, r0 + 22adc: ebf58527 bl 0xffd83f80 + 22ae0: 0800340e stmeqda r0, {r1, r2, r3, sl, ip, sp} + 22ae4: e3b03001 movs r3, #1 ; 0x1 + 22ae8: ebf58524 bl 0xffd83f80 + 22aec: 08003410 stmeqda r0, {r4, sl, ip, sp} + 22af0: e59d0420 ldr r0, [sp, #1056] + 22af4: e0800003 add r0, r0, r3 + 22af8: e58d0420 str r0, [sp, #1056] + 22afc: ebf5851f bl 0xffd83f80 + 22b00: 08003412 stmeqda r0, {r1, r4, sl, ip, sp} + 22b04: e59d1420 ldr r1, [sp, #1056] + 22b08: e1a04001 mov r4, r1 + 22b0c: ebf5851b bl 0xffd83f80 + 22b10: 08003414 stmeqda r0, {r2, r4, sl, ip, sp} + 22b14: e354000f cmp r4, #15 ; 0xf + 22b18: ebf58518 bl 0xffd83f80 + 22b1c: 08003416 stmeqda r0, {r1, r2, r4, sl, ip, sp} + 22b20: e28cc00f add ip, ip, #15 ; 0xf + 22b24: 8a000004 bhi 0x22b3c + 22b28: e1a00fac mov r0, ip, lsr #31 + 22b2c: e08ff100 add pc, pc, r0, lsl #2 + 22b30: 080033aa stmeqda r0, {r1, r3, r5, r7, r8, r9, ip, sp} + 22b34: ebf58106 bl 0xffd82f54 + 22b38: ea0000f6 b 0x22f18 + 22b3c: ebf5850f bl 0xffd83f80 + 22b40: 08003418 stmeqda r0, {r3, r4, sl, ip, sp} + 22b44: e3a00f1d mov r0, #116 ; 0x74 + 22b48: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22b4c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22b50: ebf58370 bl 0xffd83918 + 22b54: 0800341c stmeqda r0, {r2, r3, r4, sl, ip, sp} + 22b58: e1a03000 mov r3, r0 + 22b5c: ebf58507 bl 0xffd83f80 + 22b60: 0800341a stmeqda r0, {r1, r3, r4, sl, ip, sp} + 22b64: e2830000 add r0, r3, #0 ; 0x0 + 22b68: ebf5836a bl 0xffd83918 + 22b6c: 0800341e stmeqda r0, {r1, r2, r3, r4, sl, ip, sp} + 22b70: e1a03000 mov r3, r0 + 22b74: ebf58501 bl 0xffd83f80 + 22b78: 0800341c stmeqda r0, {r2, r3, r4, sl, ip, sp} + 22b7c: e1a00003 mov r0, r3 + 22b80: e58d0420 str r0, [sp, #1056] + 22b84: ebf584fd bl 0xffd83f80 + 22b88: 0800341e stmeqda r0, {r1, r2, r3, r4, sl, ip, sp} + 22b8c: e3a00f1e mov r0, #120 ; 0x78 + 22b90: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22b94: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22b98: ebf5835e bl 0xffd83918 + 22b9c: 08003422 stmeqda r0, {r1, r5, sl, ip, sp} + 22ba0: e1a05000 mov r5, r0 + 22ba4: ebf584f5 bl 0xffd83f80 + 22ba8: 08003420 stmeqda r0, {r5, sl, ip, sp} + 22bac: e353007f cmp r3, #127 ; 0x7f + 22bb0: ebf584f2 bl 0xffd83f80 + 22bb4: 08003422 stmeqda r0, {r1, r5, sl, ip, sp} + 22bb8: e28cc018 add ip, ip, #24 ; 0x18 + 22bbc: 9a000004 bls 0x22bd4 + 22bc0: e1a00fac mov r0, ip, lsr #31 + 22bc4: e08ff100 add pc, pc, r0, lsl #2 + 22bc8: 08003448 stmeqda r0, {r3, r6, sl, ip, sp} + 22bcc: ebf580e0 bl 0xffd82f54 + 22bd0: ea000053 b 0x22d24 + 22bd4: ebf584e9 bl 0xffd83f80 + 22bd8: 08003424 stmeqda r0, {r2, r5, sl, ip, sp} + 22bdc: e3a00e49 mov r0, #1168 ; 0x490 + 22be0: e3800a03 orr r0, r0, #12288 ; 0x3000 + 22be4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22be8: ebf5834a bl 0xffd83918 + 22bec: 08003428 stmeqda r0, {r3, r5, sl, ip, sp} + 22bf0: e1a04000 mov r4, r0 + 22bf4: ebf584e1 bl 0xffd83f80 + 22bf8: 08003426 stmeqda r0, {r1, r2, r5, sl, ip, sp} + 22bfc: e3b08004 movs r8, #4 ; 0x4 + 22c00: ebf584de bl 0xffd83f80 + 22c04: 08003428 stmeqda r0, {r3, r5, sl, ip, sp} + 22c08: e3a01000 mov r1, #0 ; 0x0 + 22c0c: e0518008 subs r8, r1, r8 + 22c10: ebf584da bl 0xffd83f80 + 22c14: 0800342a stmeqda r0, {r1, r3, r5, sl, ip, sp} + 22c18: e3b07002 movs r7, #2 ; 0x2 + 22c1c: ebf584d7 bl 0xffd83f80 + 22c20: 0800342c stmeqda r0, {r2, r3, r5, sl, ip, sp} + 22c24: e1b03183 movs r3, r3, lsl #3 + 22c28: ebf584d4 bl 0xffd83f80 + 22c2c: 0800342e stmeqda r0, {r1, r2, r3, r5, sl, ip, sp} + 22c30: e1a01003 mov r1, r3 + 22c34: e2933001 adds r3, r3, #1 ; 0x1 + 22c38: ebf584d0 bl 0xffd83f80 + 22c3c: 08003430 stmeqda r0, {r4, r5, sl, ip, sp} + 22c40: e1a01003 mov r1, r3 + 22c44: e0936004 adds r6, r3, r4 + 22c48: e28cc017 add ip, ip, #23 ; 0x17 + 22c4c: ebf584cb bl 0xffd83f80 + 22c50: 08003432 stmeqda r0, {r1, r4, r5, sl, ip, sp} + 22c54: e2860000 add r0, r6, #0 ; 0x0 + 22c58: ebf582d7 bl 0xffd837bc + 22c5c: 08003436 stmeqda r0, {r1, r2, r4, r5, sl, ip, sp} + 22c60: e1a04000 mov r4, r0 + 22c64: ebf584c5 bl 0xffd83f80 + 22c68: 08003434 stmeqda r0, {r2, r4, r5, sl, ip, sp} + 22c6c: e1a01008 mov r1, r8 + 22c70: e2983000 adds r3, r8, #0 ; 0x0 + 22c74: ebf584c1 bl 0xffd83f80 + 22c78: 08003436 stmeqda r0, {r1, r2, r4, r5, sl, ip, sp} + 22c7c: e1a01003 mov r1, r3 + 22c80: e0133004 ands r3, r3, r4 + 22c84: ebf584bd bl 0xffd83f80 + 22c88: 08003438 stmeqda r0, {r3, r4, r5, sl, ip, sp} + 22c8c: e1a01003 mov r1, r3 + 22c90: e1933007 orrs r3, r3, r7 + 22c94: ebf584b9 bl 0xffd83f80 + 22c98: 0800343a stmeqda r0, {r1, r3, r4, r5, sl, ip, sp} + 22c9c: e2860000 add r0, r6, #0 ; 0x0 + 22ca0: e1a01003 mov r1, r3 + 22ca4: ebf58209 bl 0xffd834d0 + 22ca8: 0800343c stmeqda r0, {r2, r3, r4, r5, sl, ip, sp} + 22cac: ebf584b3 bl 0xffd83f80 + 22cb0: 0800343c stmeqda r0, {r2, r3, r4, r5, sl, ip, sp} + 22cb4: e1a01006 mov r1, r6 + 22cb8: e2966008 adds r6, r6, #8 ; 0x8 + 22cbc: ebf584af bl 0xffd83f80 + 22cc0: 0800343e stmeqda r0, {r1, r2, r3, r4, r5, sl, ip, sp} + 22cc4: e3b00001 movs r0, #1 ; 0x1 + 22cc8: e58d0418 str r0, [sp, #1048] + 22ccc: ebf584ab bl 0xffd83f80 + 22cd0: 08003440 stmeqda r0, {r6, sl, ip, sp} + 22cd4: e59d0420 ldr r0, [sp, #1056] + 22cd8: e59d1418 ldr r1, [sp, #1048] + 22cdc: e0800001 add r0, r0, r1 + 22ce0: e58d0420 str r0, [sp, #1056] + 22ce4: ebf584a5 bl 0xffd83f80 + 22ce8: 08003442 stmeqda r0, {r1, r6, sl, ip, sp} + 22cec: e59d1420 ldr r1, [sp, #1056] + 22cf0: e1a03001 mov r3, r1 + 22cf4: ebf584a1 bl 0xffd83f80 + 22cf8: 08003444 stmeqda r0, {r2, r6, sl, ip, sp} + 22cfc: e353007f cmp r3, #127 ; 0x7f + 22d00: ebf5849e bl 0xffd83f80 + 22d04: 08003446 stmeqda r0, {r1, r2, r6, sl, ip, sp} + 22d08: e28cc024 add ip, ip, #36 ; 0x24 + 22d0c: 8a000004 bhi 0x22d24 + 22d10: e1a00fac mov r0, ip, lsr #31 + 22d14: e08ff100 add pc, pc, r0, lsl #2 + 22d18: 08003432 stmeqda r0, {r1, r4, r5, sl, ip, sp} + 22d1c: ebf5808c bl 0xffd82f54 + 22d20: eaffffc9 b 0x22c4c + 22d24: ebf58495 bl 0xffd83f80 + 22d28: 08003448 stmeqda r0, {r3, r6, sl, ip, sp} + 22d2c: e2850000 add r0, r5, #0 ; 0x0 + 22d30: ebf582f8 bl 0xffd83918 + 22d34: 0800344c stmeqda r0, {r2, r3, r6, sl, ip, sp} + 22d38: e1a05000 mov r5, r0 + 22d3c: ebf5848f bl 0xffd83f80 + 22d40: 0800344a stmeqda r0, {r1, r3, r6, sl, ip, sp} + 22d44: e3550000 cmp r5, #0 ; 0x0 + 22d48: ebf5848c bl 0xffd83f80 + 22d4c: 0800344c stmeqda r0, {r2, r3, r6, sl, ip, sp} + 22d50: e28cc00b add ip, ip, #11 ; 0xb + 22d54: 1a000004 bne 0x22d6c + 22d58: e1a00fac mov r0, ip, lsr #31 + 22d5c: e08ff100 add pc, pc, r0, lsl #2 + 22d60: 08003458 stmeqda r0, {r3, r4, r6, sl, ip, sp} + 22d64: ebf5807a bl 0xffd82f54 + 22d68: ea000020 b 0x22df0 + 22d6c: ebf58483 bl 0xffd83f80 + 22d70: 0800344e stmeqda r0, {r1, r2, r3, r6, sl, ip, sp} + 22d74: e3a00f25 mov r0, #148 ; 0x94 + 22d78: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22d7c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22d80: ebf582e4 bl 0xffd83918 + 22d84: 08003452 stmeqda r0, {r1, r4, r6, sl, ip, sp} + 22d88: e1a03000 mov r3, r0 + 22d8c: ebf5847b bl 0xffd83f80 + 22d90: 08003450 stmeqda r0, {r4, r6, sl, ip, sp} + 22d94: e3a00f26 mov r0, #152 ; 0x98 + 22d98: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22d9c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22da0: ebf582dc bl 0xffd83918 + 22da4: 08003454 stmeqda r0, {r2, r4, r6, sl, ip, sp} + 22da8: e1a04000 mov r4, r0 + 22dac: ebf58473 bl 0xffd83f80 + 22db0: 08003452 stmeqda r0, {r1, r4, r6, sl, ip, sp} + 22db4: e3b06008 movs r6, #8 ; 0x8 + 22db8: ebf58470 bl 0xffd83f80 + 22dbc: 08003454 stmeqda r0, {r2, r4, r6, sl, ip, sp} + 22dc0: ebf5846e bl 0xffd83f80 + 22dc4: 08003456 stmeqda r0, {r1, r2, r4, r6, sl, ip, sp} + 22dc8: e3a00059 mov r0, #89 ; 0x59 + 22dcc: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22dd0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22dd4: e58d0438 str r0, [sp, #1080] + 22dd8: e28cc013 add ip, ip, #19 ; 0x13 + 22ddc: e1a00fac mov r0, ip, lsr #31 + 22de0: e08ff100 add pc, pc, r0, lsl #2 + 22de4: 080c2f30 stmeqda ip, {r4, r5, r8, r9, sl, fp, sp} + 22de8: ebf58059 bl 0xffd82f54 + 22dec: ea00009c b 0x23064 + 22df0: ebf58462 bl 0xffd83f80 + 22df4: 08003458 stmeqda r0, {r3, r4, r6, sl, ip, sp} + 22df8: e59d0434 ldr r0, [sp, #1076] + 22dfc: e2800f08 add r0, r0, #32 ; 0x20 + 22e00: e58d0434 str r0, [sp, #1076] + 22e04: ebf5845d bl 0xffd83f80 + 22e08: 0800345a stmeqda r0, {r1, r3, r4, r6, sl, ip, sp} + 22e0c: e59d9434 ldr r9, [sp, #1076] + 22e10: e3c99003 bic r9, r9, #3 ; 0x3 + 22e14: e289000c add r0, r9, #12 ; 0xc + 22e18: e58d0434 str r0, [sp, #1076] + 22e1c: e2890000 add r0, r9, #0 ; 0x0 + 22e20: ebf582bc bl 0xffd83918 + 22e24: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 22e28: e1a06000 mov r6, r0 + 22e2c: e2890004 add r0, r9, #4 ; 0x4 + 22e30: ebf582b8 bl 0xffd83918 + 22e34: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 22e38: e1a07000 mov r7, r0 + 22e3c: e2890008 add r0, r9, #8 ; 0x8 + 22e40: ebf582b4 bl 0xffd83918 + 22e44: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 22e48: e1a08000 mov r8, r0 + 22e4c: ebf5844b bl 0xffd83f80 + 22e50: 0800345c stmeqda r0, {r2, r3, r4, r6, sl, ip, sp} + 22e54: e1a00006 mov r0, r6 + 22e58: e58d0420 str r0, [sp, #1056] + 22e5c: ebf58447 bl 0xffd83f80 + 22e60: 0800345e stmeqda r0, {r1, r2, r3, r4, r6, sl, ip, sp} + 22e64: e1a00007 mov r0, r7 + 22e68: e58d0424 str r0, [sp, #1060] + 22e6c: ebf58443 bl 0xffd83f80 + 22e70: 08003460 stmeqda r0, {r5, r6, sl, ip, sp} + 22e74: e1a00008 mov r0, r8 + 22e78: e58d0428 str r0, [sp, #1064] + 22e7c: ebf5843f bl 0xffd83f80 + 22e80: 08003462 stmeqda r0, {r1, r5, r6, sl, ip, sp} + 22e84: e59d9434 ldr r9, [sp, #1076] + 22e88: e3c99003 bic r9, r9, #3 ; 0x3 + 22e8c: e2890010 add r0, r9, #16 ; 0x10 + 22e90: e58d0434 str r0, [sp, #1076] + 22e94: e2890000 add r0, r9, #0 ; 0x0 + 22e98: ebf5829e bl 0xffd83918 + 22e9c: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 22ea0: e1a07000 mov r7, r0 + 22ea4: e2890004 add r0, r9, #4 ; 0x4 + 22ea8: ebf5829a bl 0xffd83918 + 22eac: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 22eb0: e1a08000 mov r8, r0 + 22eb4: e2890008 add r0, r9, #8 ; 0x8 + 22eb8: ebf58296 bl 0xffd83918 + 22ebc: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 22ec0: e58d0418 str r0, [sp, #1048] + 22ec4: e289000c add r0, r9, #12 ; 0xc + 22ec8: ebf58292 bl 0xffd83918 + 22ecc: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 22ed0: e58d041c str r0, [sp, #1052] + 22ed4: ebf58429 bl 0xffd83f80 + 22ed8: 08003464 stmeqda r0, {r2, r5, r6, sl, ip, sp} + 22edc: e59d9434 ldr r9, [sp, #1076] + 22ee0: e3c99003 bic r9, r9, #3 ; 0x3 + 22ee4: e2890004 add r0, r9, #4 ; 0x4 + 22ee8: e58d0434 str r0, [sp, #1076] + 22eec: e2890000 add r0, r9, #0 ; 0x0 + 22ef0: ebf58288 bl 0xffd83918 + 22ef4: 08003468 stmeqda r0, {r3, r5, r6, sl, ip, sp} + 22ef8: e1a03000 mov r3, r0 + 22efc: ebf5841f bl 0xffd83f80 + 22f00: 08003466 stmeqda r0, {r1, r2, r5, r6, sl, ip, sp} + 22f04: e1a00003 mov r0, r3 + 22f08: e28cc020 add ip, ip, #32 ; 0x20 + 22f0c: eaf5806f b 0xffd830d0 + 22f10: 080033aa stmeqda r0, {r1, r3, r5, r7, r8, r9, ip, sp} + 22f14: 00000000 andeq r0, r0, r0 + 22f18: ebf58418 bl 0xffd83f80 + 22f1c: 080033aa stmeqda r0, {r1, r3, r5, r7, r8, r9, ip, sp} + 22f20: e3a00f1f mov r0, #124 ; 0x7c + 22f24: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22f28: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22f2c: ebf58279 bl 0xffd83918 + 22f30: 080033ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, ip, sp} + 22f34: e1a04000 mov r4, r0 + 22f38: ebf58410 bl 0xffd83f80 + 22f3c: 080033ac stmeqda r0, {r2, r3, r5, r7, r8, r9, ip, sp} + 22f40: e59d1420 ldr r1, [sp, #1056] + 22f44: e1a00001 mov r0, r1 + 22f48: e58d0418 str r0, [sp, #1048] + 22f4c: ebf5840b bl 0xffd83f80 + 22f50: 080033ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, ip, sp} + 22f54: e59de418 ldr lr, [sp, #1048] + 22f58: e1b0310e movs r3, lr, lsl #2 + 22f5c: ebf58407 bl 0xffd83f80 + 22f60: 080033b0 stmeqda r0, {r4, r5, r7, r8, r9, ip, sp} + 22f64: e1a01003 mov r1, r3 + 22f68: e0933004 adds r3, r3, r4 + 22f6c: ebf58403 bl 0xffd83f80 + 22f70: 080033b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, ip, sp} + 22f74: e2830000 add r0, r3, #0 ; 0x0 + 22f78: ebf58266 bl 0xffd83918 + 22f7c: 080033b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, ip, sp} + 22f80: e1a07000 mov r7, r0 + 22f84: ebf583fd bl 0xffd83f80 + 22f88: 080033b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, ip, sp} + 22f8c: e3570001 cmp r7, #1 ; 0x1 + 22f90: ebf583fa bl 0xffd83f80 + 22f94: 080033b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, ip, sp} + 22f98: e28cc019 add ip, ip, #25 ; 0x19 + 22f9c: 8a000004 bhi 0x22fb4 + 22fa0: e1a00fac mov r0, ip, lsr #31 + 22fa4: e08ff100 add pc, pc, r0, lsl #2 + 22fa8: 080033d0 stmeqda r0, {r4, r6, r7, r8, r9, ip, sp} + 22fac: ebf57fe8 bl 0xffd82f54 + 22fb0: eafffe4d b 0x228ec + 22fb4: ebf583f1 bl 0xffd83f80 + 22fb8: 080033b8 stmeqda r0, {r3, r4, r5, r7, r8, r9, ip, sp} + 22fbc: e3a00dd2 mov r0, #13440 ; 0x3480 + 22fc0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22fc4: ebf58253 bl 0xffd83918 + 22fc8: 080033bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22fcc: e58d0418 str r0, [sp, #1048] + 22fd0: ebf583ea bl 0xffd83f80 + 22fd4: 080033ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, ip, sp} + 22fd8: e3a00f1d mov r0, #116 ; 0x74 + 22fdc: e3800b0d orr r0, r0, #13312 ; 0x3400 + 22fe0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 22fe4: ebf5824b bl 0xffd83918 + 22fe8: 080033be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22fec: e1a08000 mov r8, r0 + 22ff0: ebf583e2 bl 0xffd83f80 + 22ff4: 080033bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, ip, sp} + 22ff8: e2870000 add r0, r7, #0 ; 0x0 + 22ffc: ebf58245 bl 0xffd83918 + 23000: 080033c0 stmeqda r0, {r6, r7, r8, r9, ip, sp} + 23004: e1a03000 mov r3, r0 + 23008: ebf583dc bl 0xffd83f80 + 2300c: 080033be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, ip, sp} + 23010: e59d0418 ldr r0, [sp, #1048] + 23014: e2800000 add r0, r0, #0 ; 0x0 + 23018: ebf5823e bl 0xffd83918 + 2301c: 080033c2 stmeqda r0, {r1, r6, r7, r8, r9, ip, sp} + 23020: e1a04000 mov r4, r0 + 23024: ebf583d5 bl 0xffd83f80 + 23028: 080033c0 stmeqda r0, {r6, r7, r8, r9, ip, sp} + 2302c: ebf583d3 bl 0xffd83f80 + 23030: 080033c2 stmeqda r0, {r1, r6, r7, r8, r9, ip, sp} + 23034: e3a000c5 mov r0, #197 ; 0xc5 + 23038: e3800c33 orr r0, r0, #13056 ; 0x3300 + 2303c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23040: e58d0438 str r0, [sp, #1080] + 23044: e28cc01a add ip, ip, #26 ; 0x1a + 23048: e1a00fac mov r0, ip, lsr #31 + 2304c: e08ff100 add pc, pc, r0, lsl #2 + 23050: 080c31e0 stmeqda ip, {r5, r6, r7, r8, ip, sp} + 23054: ebf57fbe bl 0xffd82f54 + 23058: eaff878b b 0x4e8c + 2305c: 080c2f30 stmeqda ip, {r4, r5, r8, r9, sl, fp, sp} + 23060: 00000000 andeq r0, r0, r0 + 23064: ebf583c5 bl 0xffd83f80 + 23068: 080c2f30 stmeqda ip, {r4, r5, r8, r9, sl, fp, sp} + 2306c: ebf580aa bl 0xffd8331c + 23070: 080c2f32 stmeqda ip, {r1, r4, r5, r8, r9, sl, fp, sp} + 23074: e28cc003 add ip, ip, #3 ; 0x3 + 23078: e1a00fac mov r0, ip, lsr #31 + 2307c: e08ff100 add pc, pc, r0, lsl #2 + 23080: 00000008 andeq r0, r0, r8 + 23084: ebf57f7c bl 0xffd82e7c + 23088: ea2a73dc b 0xac0000 + 2308c: 08002c8e stmeqda r0, {r1, r2, r3, r7, sl, fp, sp} + 23090: 00000000 andeq r0, r0, r0 + 23094: ebf583b9 bl 0xffd83f80 + 23098: 08002c8e stmeqda r0, {r1, r2, r3, r7, sl, fp, sp} + 2309c: e59d9434 ldr r9, [sp, #1076] + 230a0: e3c99003 bic r9, r9, #3 ; 0x3 + 230a4: e2890004 add r0, r9, #4 ; 0x4 + 230a8: e58d0434 str r0, [sp, #1076] + 230ac: e2890000 add r0, r9, #0 ; 0x0 + 230b0: ebf58218 bl 0xffd83918 + 230b4: 08002c92 stmeqda r0, {r1, r4, r7, sl, fp, sp} + 230b8: e1a07000 mov r7, r0 + 230bc: ebf583af bl 0xffd83f80 + 230c0: 08002c90 stmeqda r0, {r4, r7, sl, fp, sp} + 230c4: e59d9434 ldr r9, [sp, #1076] + 230c8: e3c99003 bic r9, r9, #3 ; 0x3 + 230cc: e2890004 add r0, r9, #4 ; 0x4 + 230d0: e58d0434 str r0, [sp, #1076] + 230d4: e2890000 add r0, r9, #0 ; 0x0 + 230d8: ebf5820e bl 0xffd83918 + 230dc: 08002c94 stmeqda r0, {r2, r4, r7, sl, fp, sp} + 230e0: e1a03000 mov r3, r0 + 230e4: ebf583a5 bl 0xffd83f80 + 230e8: 08002c92 stmeqda r0, {r1, r4, r7, sl, fp, sp} + 230ec: e1a00003 mov r0, r3 + 230f0: e28cc00b add ip, ip, #11 ; 0xb + 230f4: eaf57ff5 b 0xffd830d0 + 230f8: 08002c6c stmeqda r0, {r2, r3, r5, r6, sl, fp, sp} + 230fc: 00000000 andeq r0, r0, r0 + 23100: ebf5839e bl 0xffd83f80 + 23104: 08002c6c stmeqda r0, {r2, r3, r5, r6, sl, fp, sp} + 23108: e59d9434 ldr r9, [sp, #1076] + 2310c: e3c99003 bic r9, r9, #3 ; 0x3 + 23110: e2890004 add r0, r9, #4 ; 0x4 + 23114: e58d0434 str r0, [sp, #1076] + 23118: e2890000 add r0, r9, #0 ; 0x0 + 2311c: ebf581fd bl 0xffd83918 + 23120: 08002c70 stmeqda r0, {r4, r5, r6, sl, fp, sp} + 23124: e1a03000 mov r3, r0 + 23128: ebf58394 bl 0xffd83f80 + 2312c: 08002c6e stmeqda r0, {r1, r2, r3, r5, r6, sl, fp, sp} + 23130: e1a00003 mov r0, r3 + 23134: e28cc007 add ip, ip, #7 ; 0x7 + 23138: eaf57fe4 b 0xffd830d0 + 2313c: 08000390 stmeqda r0, {r4, r7, r8, r9} + 23140: 00000000 andeq r0, r0, r0 + 23144: ebf5838d bl 0xffd83f80 + 23148: 08000390 stmeqda r0, {r4, r7, r8, r9} + 2314c: e3a00f15 mov r0, #84 ; 0x54 + 23150: e3800b01 orr r0, r0, #1024 ; 0x400 + 23154: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23158: ebf581ee bl 0xffd83918 + 2315c: 08000394 stmeqda r0, {r2, r4, r7, r8, r9} + 23160: e1a03000 mov r3, r0 + 23164: ebf58385 bl 0xffd83f80 + 23168: 08000392 stmeqda r0, {r1, r4, r7, r8, r9} + 2316c: e2830000 add r0, r3, #0 ; 0x0 + 23170: ebf581bc bl 0xffd83868 + 23174: 08000396 stmeqda r0, {r1, r2, r4, r7, r8, r9} + 23178: e1a05000 mov r5, r0 + 2317c: ebf5837f bl 0xffd83f80 + 23180: 08000394 stmeqda r0, {r2, r4, r7, r8, r9} + 23184: e3a00f16 mov r0, #88 ; 0x58 + 23188: e3800b01 orr r0, r0, #1024 ; 0x400 + 2318c: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23190: ebf581e0 bl 0xffd83918 + 23194: 08000398 stmeqda r0, {r3, r4, r7, r8, r9} + 23198: e1a04000 mov r4, r0 + 2319c: ebf58377 bl 0xffd83f80 + 231a0: 08000396 stmeqda r0, {r1, r2, r4, r7, r8, r9} + 231a4: e1a01007 mov r1, r7 + 231a8: e0973004 adds r3, r7, r4 + 231ac: ebf58373 bl 0xffd83f80 + 231b0: 08000398 stmeqda r0, {r3, r4, r7, r8, r9} + 231b4: e2830000 add r0, r3, #0 ; 0x0 + 231b8: ebf581aa bl 0xffd83868 + 231bc: 0800039c stmeqda r0, {r2, r3, r4, r7, r8, r9} + 231c0: e1a04000 mov r4, r0 + 231c4: ebf5836d bl 0xffd83f80 + 231c8: 0800039a stmeqda r0, {r1, r3, r4, r7, r8, r9} + 231cc: e2830000 add r0, r3, #0 ; 0x0 + 231d0: e1a01005 mov r1, r5 + 231d4: ebf580dc bl 0xffd8354c + 231d8: 0800039c stmeqda r0, {r2, r3, r4, r7, r8, r9} + 231dc: ebf58367 bl 0xffd83f80 + 231e0: 0800039c stmeqda r0, {r2, r3, r4, r7, r8, r9} + 231e4: e2870012 add r0, r7, #18 ; 0x12 + 231e8: ebf5819e bl 0xffd83868 + 231ec: 080003a0 stmeqda r0, {r5, r7, r8, r9} + 231f0: e1a04000 mov r4, r0 + 231f4: ebf58361 bl 0xffd83f80 + 231f8: 0800039e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9} + 231fc: e2870010 add r0, r7, #16 ; 0x10 + 23200: ebf58198 bl 0xffd83868 + 23204: 080003a2 stmeqda r0, {r1, r5, r7, r8, r9} + 23208: e1a03000 mov r3, r0 + 2320c: ebf5835b bl 0xffd83f80 + 23210: 080003a0 stmeqda r0, {r5, r7, r8, r9} + 23214: e1b04804 movs r4, r4, lsl #16 + 23218: ebf58358 bl 0xffd83f80 + 2321c: 080003a2 stmeqda r0, {r1, r5, r7, r8, r9} + 23220: e1b03803 movs r3, r3, lsl #16 + 23224: ebf58355 bl 0xffd83f80 + 23228: 080003a4 stmeqda r0, {r2, r5, r7, r8, r9} + 2322c: e1540003 cmp r4, r3 + 23230: ebf58352 bl 0xffd83f80 + 23234: 080003a6 stmeqda r0, {r1, r2, r5, r7, r8, r9} + 23238: e28cc031 add ip, ip, #49 ; 0x31 + 2323c: ba000004 blt 0x23254 + 23240: e1a00fac mov r0, ip, lsr #31 + 23244: e08ff100 add pc, pc, r0, lsl #2 + 23248: 080003b8 stmeqda r0, {r3, r4, r5, r7, r8, r9} + 2324c: ebf57f40 bl 0xffd82f54 + 23250: ea00002a b 0x23300 + 23254: ebf58349 bl 0xffd83f80 + 23258: 080003a8 stmeqda r0, {r3, r5, r7, r8, r9} + 2325c: e3a00f17 mov r0, #92 ; 0x5c + 23260: e3800b01 orr r0, r0, #1024 ; 0x400 + 23264: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23268: ebf581aa bl 0xffd83918 + 2326c: 080003ac stmeqda r0, {r2, r3, r5, r7, r8, r9} + 23270: e1a06000 mov r6, r0 + 23274: ebf58341 bl 0xffd83f80 + 23278: 080003aa stmeqda r0, {r1, r3, r5, r7, r8, r9} + 2327c: e1a01008 mov r1, r8 + 23280: e0985006 adds r5, r8, r6 + 23284: e28cc008 add ip, ip, #8 ; 0x8 + 23288: ebf5833c bl 0xffd83f80 + 2328c: 080003ac stmeqda r0, {r2, r3, r5, r7, r8, r9} + 23290: e2850012 add r0, r5, #18 ; 0x12 + 23294: ebf58173 bl 0xffd83868 + 23298: 080003b0 stmeqda r0, {r4, r5, r7, r8, r9} + 2329c: e1a04000 mov r4, r0 + 232a0: ebf58336 bl 0xffd83f80 + 232a4: 080003ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9} + 232a8: e2850010 add r0, r5, #16 ; 0x10 + 232ac: ebf5816d bl 0xffd83868 + 232b0: 080003b2 stmeqda r0, {r1, r4, r5, r7, r8, r9} + 232b4: e1a03000 mov r3, r0 + 232b8: ebf58330 bl 0xffd83f80 + 232bc: 080003b0 stmeqda r0, {r4, r5, r7, r8, r9} + 232c0: e1b04804 movs r4, r4, lsl #16 + 232c4: ebf5832d bl 0xffd83f80 + 232c8: 080003b2 stmeqda r0, {r1, r4, r5, r7, r8, r9} + 232cc: e1b03803 movs r3, r3, lsl #16 + 232d0: ebf5832a bl 0xffd83f80 + 232d4: 080003b4 stmeqda r0, {r2, r4, r5, r7, r8, r9} + 232d8: e1540003 cmp r4, r3 + 232dc: ebf58327 bl 0xffd83f80 + 232e0: 080003b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9} + 232e4: e28cc016 add ip, ip, #22 ; 0x16 + 232e8: aa000004 bge 0x23300 + 232ec: e1a00fac mov r0, ip, lsr #31 + 232f0: e08ff100 add pc, pc, r0, lsl #2 + 232f4: 080003ac stmeqda r0, {r2, r3, r5, r7, r8, r9} + 232f8: ebf57f15 bl 0xffd82f54 + 232fc: eaffffe1 b 0x23288 + 23300: ebf5831e bl 0xffd83f80 + 23304: 080003b8 stmeqda r0, {r3, r4, r5, r7, r8, r9} + 23308: e2870012 add r0, r7, #18 ; 0x12 + 2330c: ebf58155 bl 0xffd83868 + 23310: 080003bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9} + 23314: e1a03000 mov r3, r0 + 23318: ebf58318 bl 0xffd83f80 + 2331c: 080003ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9} + 23320: e3a00e46 mov r0, #1120 ; 0x460 + 23324: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23328: ebf5817a bl 0xffd83918 + 2332c: 080003be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9} + 23330: e1a03000 mov r3, r0 + 23334: ebf58311 bl 0xffd83f80 + 23338: 080003bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9} + 2333c: e2870012 add r0, r7, #18 ; 0x12 + 23340: e1a01003 mov r1, r3 + 23344: ebf58080 bl 0xffd8354c + 23348: 080003be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9} + 2334c: ebf5830b bl 0xffd83f80 + 23350: 080003be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9} + 23354: e2870012 add r0, r7, #18 ; 0x12 + 23358: ebf58142 bl 0xffd83868 + 2335c: 080003c2 stmeqda r0, {r1, r6, r7, r8, r9} + 23360: e1a03000 mov r3, r0 + 23364: ebf58305 bl 0xffd83f80 + 23368: 080003c0 stmeqda r0, {r6, r7, r8, r9} + 2336c: e1b03803 movs r3, r3, lsl #16 + 23370: ebf58302 bl 0xffd83f80 + 23374: 080003c2 stmeqda r0, {r1, r6, r7, r8, r9} + 23378: e3530000 cmp r3, #0 ; 0x0 + 2337c: ebf582ff bl 0xffd83f80 + 23380: 080003c4 stmeqda r0, {r2, r6, r7, r8, r9} + 23384: e28cc01c add ip, ip, #28 ; 0x1c + 23388: ba000004 blt 0x233a0 + 2338c: e1a00fac mov r0, ip, lsr #31 + 23390: e08ff100 add pc, pc, r0, lsl #2 + 23394: 080003d4 stmeqda r0, {r2, r4, r6, r7, r8, r9} + 23398: ebf57eed bl 0xffd82f54 + 2339c: ea000018 b 0x23404 + 233a0: ebf582f6 bl 0xffd83f80 + 233a4: 080003c6 stmeqda r0, {r1, r2, r6, r7, r8, r9} + 233a8: e3a00f06 mov r0, #24 ; 0x18 + 233ac: e3800b01 orr r0, r0, #1024 ; 0x400 + 233b0: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 233b4: ebf58157 bl 0xffd83918 + 233b8: 080003ca stmeqda r0, {r1, r3, r6, r7, r8, r9} + 233bc: e1a08000 mov r8, r0 + 233c0: ebf582ee bl 0xffd83f80 + 233c4: 080003c8 stmeqda r0, {r3, r6, r7, r8, r9} + 233c8: e28cc008 add ip, ip, #8 ; 0x8 + 233cc: ebf582eb bl 0xffd83f80 + 233d0: 080003ca stmeqda r0, {r1, r3, r6, r7, r8, r9} + 233d4: e3a000cd mov r0, #205 ; 0xcd + 233d8: e3800c03 orr r0, r0, #768 ; 0x300 + 233dc: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 233e0: e58d0438 str r0, [sp, #1080] + 233e4: e28cc003 add ip, ip, #3 ; 0x3 + 233e8: e1a00fac mov r0, ip, lsr #31 + 233ec: e08ff100 add pc, pc, r0, lsl #2 + 233f0: 080057d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, ip, lr} + 233f4: ebf57ed6 bl 0xffd82f54 + 233f8: ea0002ea b 0x23fa8 + 233fc: 080003d4 stmeqda r0, {r2, r4, r6, r7, r8, r9} + 23400: 00000000 andeq r0, r0, r0 + 23404: ebf582dd bl 0xffd83f80 + 23408: 080003d4 stmeqda r0, {r2, r4, r6, r7, r8, r9} + 2340c: e2870012 add r0, r7, #18 ; 0x12 + 23410: ebf58114 bl 0xffd83868 + 23414: 080003d8 stmeqda r0, {r3, r4, r6, r7, r8, r9} + 23418: e1a03000 mov r3, r0 + 2341c: ebf582d7 bl 0xffd83f80 + 23420: 080003d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9} + 23424: e3b03000 movs r3, #0 ; 0x0 + 23428: ebf582d4 bl 0xffd83f80 + 2342c: 080003d8 stmeqda r0, {r3, r4, r6, r7, r8, r9} + 23430: e2870012 add r0, r7, #18 ; 0x12 + 23434: e1a01003 mov r1, r3 + 23438: ebf58043 bl 0xffd8354c + 2343c: 080003da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9} + 23440: ebf582ce bl 0xffd83f80 + 23444: 080003da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9} + 23448: e2870008 add r0, r7, #8 ; 0x8 + 2344c: ebf58131 bl 0xffd83918 + 23450: 080003de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9} + 23454: e1a03000 mov r3, r0 + 23458: ebf582c8 bl 0xffd83f80 + 2345c: 080003dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9} + 23460: e1a01003 mov r1, r3 + 23464: e2933001 adds r3, r3, #1 ; 0x1 + 23468: ebf582c4 bl 0xffd83f80 + 2346c: 080003de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9} + 23470: e2870008 add r0, r7, #8 ; 0x8 + 23474: e1a01003 mov r1, r3 + 23478: ebf58053 bl 0xffd835cc + 2347c: 080003e0 stmeqda r0, {r5, r6, r7, r8, r9} + 23480: ebf582be bl 0xffd83f80 + 23484: 080003e0 stmeqda r0, {r5, r6, r7, r8, r9} + 23488: ebf582bc bl 0xffd83f80 + 2348c: 080003e2 stmeqda r0, {r1, r5, r6, r7, r8, r9} + 23490: e3a000e5 mov r0, #229 ; 0xe5 + 23494: e3800c03 orr r0, r0, #768 ; 0x300 + 23498: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 2349c: e58d0438 str r0, [sp, #1080] + 234a0: e28cc01e add ip, ip, #30 ; 0x1e + 234a4: e1a00fac mov r0, ip, lsr #31 + 234a8: e08ff100 add pc, pc, r0, lsl #2 + 234ac: 080006c8 stmeqda r0, {r3, r6, r7, r9, sl} + 234b0: ebf57ea7 bl 0xffd82f54 + 234b4: ea000001 b 0x234c0 + 234b8: 080006c8 stmeqda r0, {r3, r6, r7, r9, sl} + 234bc: 00000000 andeq r0, r0, r0 + 234c0: ebf582ae bl 0xffd83f80 + 234c4: 080006c8 stmeqda r0, {r3, r6, r7, r9, sl} + 234c8: e3b04080 movs r4, #128 ; 0x80 + 234cc: ebf582ab bl 0xffd83f80 + 234d0: 080006ca stmeqda r0, {r1, r3, r6, r7, r9, sl} + 234d4: e1b04984 movs r4, r4, lsl #19 + 234d8: ebf582a8 bl 0xffd83f80 + 234dc: 080006cc stmeqda r0, {r2, r3, r6, r7, r9, sl} + 234e0: e3a00ff5 mov r0, #980 ; 0x3d4 + 234e4: e3800b01 orr r0, r0, #1024 ; 0x400 + 234e8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 234ec: ebf58109 bl 0xffd83918 + 234f0: 080006d0 stmeqda r0, {r4, r6, r7, r9, sl} + 234f4: e1a05000 mov r5, r0 + 234f8: ebf582a0 bl 0xffd83f80 + 234fc: 080006ce stmeqda r0, {r1, r2, r3, r6, r7, r9, sl} + 23500: e2850000 add r0, r5, #0 ; 0x0 + 23504: ebf580d7 bl 0xffd83868 + 23508: 080006d2 stmeqda r0, {r1, r4, r6, r7, r9, sl} + 2350c: e1a03000 mov r3, r0 + 23510: ebf5829a bl 0xffd83f80 + 23514: 080006d0 stmeqda r0, {r4, r6, r7, r9, sl} + 23518: e2840000 add r0, r4, #0 ; 0x0 + 2351c: e1a01003 mov r1, r3 + 23520: ebf58009 bl 0xffd8354c + 23524: 080006d2 stmeqda r0, {r1, r4, r6, r7, r9, sl} + 23528: ebf58294 bl 0xffd83f80 + 2352c: 080006d2 stmeqda r0, {r1, r4, r6, r7, r9, sl} + 23530: e1a01004 mov r1, r4 + 23534: e294404c adds r4, r4, #76 ; 0x4c + 23538: ebf58290 bl 0xffd83f80 + 2353c: 080006d4 stmeqda r0, {r2, r4, r6, r7, r9, sl} + 23540: e2850002 add r0, r5, #2 ; 0x2 + 23544: ebf580c7 bl 0xffd83868 + 23548: 080006d8 stmeqda r0, {r3, r4, r6, r7, r9, sl} + 2354c: e1a03000 mov r3, r0 + 23550: ebf5828a bl 0xffd83f80 + 23554: 080006d6 stmeqda r0, {r1, r2, r4, r6, r7, r9, sl} + 23558: e2840000 add r0, r4, #0 ; 0x0 + 2355c: e1a01003 mov r1, r3 + 23560: ebf57ff9 bl 0xffd8354c + 23564: 080006d8 stmeqda r0, {r3, r4, r6, r7, r9, sl} + 23568: ebf58284 bl 0xffd83f80 + 2356c: 080006d8 stmeqda r0, {r3, r4, r6, r7, r9, sl} + 23570: e1a01004 mov r1, r4 + 23574: e2944004 adds r4, r4, #4 ; 0x4 + 23578: ebf58280 bl 0xffd83f80 + 2357c: 080006da stmeqda r0, {r1, r3, r4, r6, r7, r9, sl} + 23580: e2850004 add r0, r5, #4 ; 0x4 + 23584: ebf580b7 bl 0xffd83868 + 23588: 080006de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl} + 2358c: e1a03000 mov r3, r0 + 23590: ebf5827a bl 0xffd83f80 + 23594: 080006dc stmeqda r0, {r2, r3, r4, r6, r7, r9, sl} + 23598: e2840000 add r0, r4, #0 ; 0x0 + 2359c: e1a01003 mov r1, r3 + 235a0: ebf57fe9 bl 0xffd8354c + 235a4: 080006de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl} + 235a8: ebf58274 bl 0xffd83f80 + 235ac: 080006de stmeqda r0, {r1, r2, r3, r4, r6, r7, r9, sl} + 235b0: e1a01004 mov r1, r4 + 235b4: e2944002 adds r4, r4, #2 ; 0x2 + 235b8: ebf58270 bl 0xffd83f80 + 235bc: 080006e0 stmeqda r0, {r5, r6, r7, r9, sl} + 235c0: e2850006 add r0, r5, #6 ; 0x6 + 235c4: ebf580a7 bl 0xffd83868 + 235c8: 080006e4 stmeqda r0, {r2, r5, r6, r7, r9, sl} + 235cc: e1a03000 mov r3, r0 + 235d0: ebf5826a bl 0xffd83f80 + 235d4: 080006e2 stmeqda r0, {r1, r5, r6, r7, r9, sl} + 235d8: e2840000 add r0, r4, #0 ; 0x0 + 235dc: e1a01003 mov r1, r3 + 235e0: ebf57fd9 bl 0xffd8354c + 235e4: 080006e4 stmeqda r0, {r2, r5, r6, r7, r9, sl} + 235e8: ebf58264 bl 0xffd83f80 + 235ec: 080006e4 stmeqda r0, {r2, r5, r6, r7, r9, sl} + 235f0: e1a01004 mov r1, r4 + 235f4: e2944002 adds r4, r4, #2 ; 0x2 + 235f8: ebf58260 bl 0xffd83f80 + 235fc: 080006e6 stmeqda r0, {r1, r2, r5, r6, r7, r9, sl} + 23600: e2850008 add r0, r5, #8 ; 0x8 + 23604: ebf58097 bl 0xffd83868 + 23608: 080006ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl} + 2360c: e1a03000 mov r3, r0 + 23610: ebf5825a bl 0xffd83f80 + 23614: 080006e8 stmeqda r0, {r3, r5, r6, r7, r9, sl} + 23618: e2840000 add r0, r4, #0 ; 0x0 + 2361c: e1a01003 mov r1, r3 + 23620: ebf57fc9 bl 0xffd8354c + 23624: 080006ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl} + 23628: ebf58254 bl 0xffd83f80 + 2362c: 080006ea stmeqda r0, {r1, r3, r5, r6, r7, r9, sl} + 23630: e1a01004 mov r1, r4 + 23634: e2544014 subs r4, r4, #20 ; 0x14 + 23638: ebf58250 bl 0xffd83f80 + 2363c: 080006ec stmeqda r0, {r2, r3, r5, r6, r7, r9, sl} + 23640: e285000a add r0, r5, #10 ; 0xa + 23644: ebf58087 bl 0xffd83868 + 23648: 080006f0 stmeqda r0, {r4, r5, r6, r7, r9, sl} + 2364c: e1a03000 mov r3, r0 + 23650: ebf5824a bl 0xffd83f80 + 23654: 080006ee stmeqda r0, {r1, r2, r3, r5, r6, r7, r9, sl} + 23658: e2840000 add r0, r4, #0 ; 0x0 + 2365c: e1a01003 mov r1, r3 + 23660: ebf57fb9 bl 0xffd8354c + 23664: 080006f0 stmeqda r0, {r4, r5, r6, r7, r9, sl} + 23668: ebf58244 bl 0xffd83f80 + 2366c: 080006f0 stmeqda r0, {r4, r5, r6, r7, r9, sl} + 23670: e1a01004 mov r1, r4 + 23674: e2944002 adds r4, r4, #2 ; 0x2 + 23678: ebf58240 bl 0xffd83f80 + 2367c: 080006f2 stmeqda r0, {r1, r4, r5, r6, r7, r9, sl} + 23680: e285000c add r0, r5, #12 ; 0xc + 23684: ebf58077 bl 0xffd83868 + 23688: 080006f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl} + 2368c: e1a03000 mov r3, r0 + 23690: ebf5823a bl 0xffd83f80 + 23694: 080006f4 stmeqda r0, {r2, r4, r5, r6, r7, r9, sl} + 23698: e2840000 add r0, r4, #0 ; 0x0 + 2369c: e1a01003 mov r1, r3 + 236a0: ebf57fa9 bl 0xffd8354c + 236a4: 080006f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl} + 236a8: ebf58234 bl 0xffd83f80 + 236ac: 080006f6 stmeqda r0, {r1, r2, r4, r5, r6, r7, r9, sl} + 236b0: e1a01004 mov r1, r4 + 236b4: e2944002 adds r4, r4, #2 ; 0x2 + 236b8: ebf58230 bl 0xffd83f80 + 236bc: 080006f8 stmeqda r0, {r3, r4, r5, r6, r7, r9, sl} + 236c0: e285000e add r0, r5, #14 ; 0xe + 236c4: ebf58067 bl 0xffd83868 + 236c8: 080006fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl} + 236cc: e1a03000 mov r3, r0 + 236d0: ebf5822a bl 0xffd83f80 + 236d4: 080006fa stmeqda r0, {r1, r3, r4, r5, r6, r7, r9, sl} + 236d8: e2840000 add r0, r4, #0 ; 0x0 + 236dc: e1a01003 mov r1, r3 + 236e0: ebf57f99 bl 0xffd8354c + 236e4: 080006fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl} + 236e8: ebf58224 bl 0xffd83f80 + 236ec: 080006fc stmeqda r0, {r2, r3, r4, r5, r6, r7, r9, sl} + 236f0: e1a01004 mov r1, r4 + 236f4: e2944002 adds r4, r4, #2 ; 0x2 + 236f8: ebf58220 bl 0xffd83f80 + 236fc: 080006fe stmeqda r0, {r1, r2, r3, r4, r5, r6, r7, r9, sl} + 23700: e2850010 add r0, r5, #16 ; 0x10 + 23704: ebf58057 bl 0xffd83868 + 23708: 08000702 stmeqda r0, {r1, r8, r9, sl} + 2370c: e1a03000 mov r3, r0 + 23710: ebf5821a bl 0xffd83f80 + 23714: 08000700 stmeqda r0, {r8, r9, sl} + 23718: e2840000 add r0, r4, #0 ; 0x0 + 2371c: e1a01003 mov r1, r3 + 23720: ebf57f89 bl 0xffd8354c + 23724: 08000702 stmeqda r0, {r1, r8, r9, sl} + 23728: ebf58214 bl 0xffd83f80 + 2372c: 08000702 stmeqda r0, {r1, r8, r9, sl} + 23730: e1a01004 mov r1, r4 + 23734: e2944002 adds r4, r4, #2 ; 0x2 + 23738: ebf58210 bl 0xffd83f80 + 2373c: 08000704 stmeqda r0, {r2, r8, r9, sl} + 23740: e2850012 add r0, r5, #18 ; 0x12 + 23744: ebf58047 bl 0xffd83868 + 23748: 08000708 stmeqda r0, {r3, r8, r9, sl} + 2374c: e1a03000 mov r3, r0 + 23750: ebf5820a bl 0xffd83f80 + 23754: 08000706 stmeqda r0, {r1, r2, r8, r9, sl} + 23758: e2840000 add r0, r4, #0 ; 0x0 + 2375c: e1a01003 mov r1, r3 + 23760: ebf57f79 bl 0xffd8354c + 23764: 08000708 stmeqda r0, {r3, r8, r9, sl} + 23768: ebf58204 bl 0xffd83f80 + 2376c: 08000708 stmeqda r0, {r3, r8, r9, sl} + 23770: e1a01004 mov r1, r4 + 23774: e2944002 adds r4, r4, #2 ; 0x2 + 23778: ebf58200 bl 0xffd83f80 + 2377c: 0800070a stmeqda r0, {r1, r3, r8, r9, sl} + 23780: e2850014 add r0, r5, #20 ; 0x14 + 23784: ebf58037 bl 0xffd83868 + 23788: 0800070e stmeqda r0, {r1, r2, r3, r8, r9, sl} + 2378c: e1a03000 mov r3, r0 + 23790: ebf581fa bl 0xffd83f80 + 23794: 0800070c stmeqda r0, {r2, r3, r8, r9, sl} + 23798: e2840000 add r0, r4, #0 ; 0x0 + 2379c: e1a01003 mov r1, r3 + 237a0: ebf57f69 bl 0xffd8354c + 237a4: 0800070e stmeqda r0, {r1, r2, r3, r8, r9, sl} + 237a8: ebf581f4 bl 0xffd83f80 + 237ac: 0800070e stmeqda r0, {r1, r2, r3, r8, r9, sl} + 237b0: e1a01004 mov r1, r4 + 237b4: e2544042 subs r4, r4, #66 ; 0x42 + 237b8: ebf581f0 bl 0xffd83f80 + 237bc: 08000710 stmeqda r0, {r4, r8, r9, sl} + 237c0: e2850016 add r0, r5, #22 ; 0x16 + 237c4: ebf58027 bl 0xffd83868 + 237c8: 08000714 stmeqda r0, {r2, r4, r8, r9, sl} + 237cc: e1a03000 mov r3, r0 + 237d0: ebf581ea bl 0xffd83f80 + 237d4: 08000712 stmeqda r0, {r1, r4, r8, r9, sl} + 237d8: e2840000 add r0, r4, #0 ; 0x0 + 237dc: e1a01003 mov r1, r3 + 237e0: ebf57f59 bl 0xffd8354c + 237e4: 08000714 stmeqda r0, {r2, r4, r8, r9, sl} + 237e8: ebf581e4 bl 0xffd83f80 + 237ec: 08000714 stmeqda r0, {r2, r4, r8, r9, sl} + 237f0: e1a01004 mov r1, r4 + 237f4: e2944002 adds r4, r4, #2 ; 0x2 + 237f8: ebf581e0 bl 0xffd83f80 + 237fc: 08000716 stmeqda r0, {r1, r2, r4, r8, r9, sl} + 23800: e2850018 add r0, r5, #24 ; 0x18 + 23804: ebf58017 bl 0xffd83868 + 23808: 0800071a stmeqda r0, {r1, r3, r4, r8, r9, sl} + 2380c: e1a03000 mov r3, r0 + 23810: ebf581da bl 0xffd83f80 + 23814: 08000718 stmeqda r0, {r3, r4, r8, r9, sl} + 23818: e2840000 add r0, r4, #0 ; 0x0 + 2381c: e1a01003 mov r1, r3 + 23820: ebf57f49 bl 0xffd8354c + 23824: 0800071a stmeqda r0, {r1, r3, r4, r8, r9, sl} + 23828: ebf581d4 bl 0xffd83f80 + 2382c: 0800071a stmeqda r0, {r1, r3, r4, r8, r9, sl} + 23830: e1a01004 mov r1, r4 + 23834: e2944002 adds r4, r4, #2 ; 0x2 + 23838: ebf581d0 bl 0xffd83f80 + 2383c: 0800071c stmeqda r0, {r2, r3, r4, r8, r9, sl} + 23840: e285001a add r0, r5, #26 ; 0x1a + 23844: ebf58007 bl 0xffd83868 + 23848: 08000720 stmeqda r0, {r5, r8, r9, sl} + 2384c: e1a03000 mov r3, r0 + 23850: ebf581ca bl 0xffd83f80 + 23854: 0800071e stmeqda r0, {r1, r2, r3, r4, r8, r9, sl} + 23858: e2840000 add r0, r4, #0 ; 0x0 + 2385c: e1a01003 mov r1, r3 + 23860: ebf57f39 bl 0xffd8354c + 23864: 08000720 stmeqda r0, {r5, r8, r9, sl} + 23868: ebf581c4 bl 0xffd83f80 + 2386c: 08000720 stmeqda r0, {r5, r8, r9, sl} + 23870: e1a01004 mov r1, r4 + 23874: e2944002 adds r4, r4, #2 ; 0x2 + 23878: ebf581c0 bl 0xffd83f80 + 2387c: 08000722 stmeqda r0, {r1, r5, r8, r9, sl} + 23880: e285001c add r0, r5, #28 ; 0x1c + 23884: ebf57ff7 bl 0xffd83868 + 23888: 08000726 stmeqda r0, {r1, r2, r5, r8, r9, sl} + 2388c: e1a03000 mov r3, r0 + 23890: ebf581ba bl 0xffd83f80 + 23894: 08000724 stmeqda r0, {r2, r5, r8, r9, sl} + 23898: e2840000 add r0, r4, #0 ; 0x0 + 2389c: e1a01003 mov r1, r3 + 238a0: ebf57f29 bl 0xffd8354c + 238a4: 08000726 stmeqda r0, {r1, r2, r5, r8, r9, sl} + 238a8: ebf581b4 bl 0xffd83f80 + 238ac: 08000726 stmeqda r0, {r1, r2, r5, r8, r9, sl} + 238b0: e1a01004 mov r1, r4 + 238b4: e2944002 adds r4, r4, #2 ; 0x2 + 238b8: ebf581b0 bl 0xffd83f80 + 238bc: 08000728 stmeqda r0, {r3, r5, r8, r9, sl} + 238c0: e285001e add r0, r5, #30 ; 0x1e + 238c4: ebf57fe7 bl 0xffd83868 + 238c8: 0800072c stmeqda r0, {r2, r3, r5, r8, r9, sl} + 238cc: e1a03000 mov r3, r0 + 238d0: ebf581aa bl 0xffd83f80 + 238d4: 0800072a stmeqda r0, {r1, r3, r5, r8, r9, sl} + 238d8: e2840000 add r0, r4, #0 ; 0x0 + 238dc: e1a01003 mov r1, r3 + 238e0: ebf57f19 bl 0xffd8354c + 238e4: 0800072c stmeqda r0, {r2, r3, r5, r8, r9, sl} + 238e8: ebf581a4 bl 0xffd83f80 + 238ec: 0800072c stmeqda r0, {r2, r3, r5, r8, r9, sl} + 238f0: e1a01004 mov r1, r4 + 238f4: e2944002 adds r4, r4, #2 ; 0x2 + 238f8: ebf581a0 bl 0xffd83f80 + 238fc: 0800072e stmeqda r0, {r1, r2, r3, r5, r8, r9, sl} + 23900: e2850020 add r0, r5, #32 ; 0x20 + 23904: ebf57fd7 bl 0xffd83868 + 23908: 08000732 stmeqda r0, {r1, r4, r5, r8, r9, sl} + 2390c: e1a03000 mov r3, r0 + 23910: ebf5819a bl 0xffd83f80 + 23914: 08000730 stmeqda r0, {r4, r5, r8, r9, sl} + 23918: e2840000 add r0, r4, #0 ; 0x0 + 2391c: e1a01003 mov r1, r3 + 23920: ebf57f09 bl 0xffd8354c + 23924: 08000732 stmeqda r0, {r1, r4, r5, r8, r9, sl} + 23928: ebf58194 bl 0xffd83f80 + 2392c: 08000732 stmeqda r0, {r1, r4, r5, r8, r9, sl} + 23930: e1a01004 mov r1, r4 + 23934: e2944002 adds r4, r4, #2 ; 0x2 + 23938: ebf58190 bl 0xffd83f80 + 2393c: 08000734 stmeqda r0, {r2, r4, r5, r8, r9, sl} + 23940: e2850022 add r0, r5, #34 ; 0x22 + 23944: ebf57fc7 bl 0xffd83868 + 23948: 08000738 stmeqda r0, {r3, r4, r5, r8, r9, sl} + 2394c: e1a03000 mov r3, r0 + 23950: ebf5818a bl 0xffd83f80 + 23954: 08000736 stmeqda r0, {r1, r2, r4, r5, r8, r9, sl} + 23958: e2840000 add r0, r4, #0 ; 0x0 + 2395c: e1a01003 mov r1, r3 + 23960: ebf57ef9 bl 0xffd8354c + 23964: 08000738 stmeqda r0, {r3, r4, r5, r8, r9, sl} + 23968: ebf58184 bl 0xffd83f80 + 2396c: 08000738 stmeqda r0, {r3, r4, r5, r8, r9, sl} + 23970: e1a01004 mov r1, r4 + 23974: e2944002 adds r4, r4, #2 ; 0x2 + 23978: ebf58180 bl 0xffd83f80 + 2397c: 0800073a stmeqda r0, {r1, r3, r4, r5, r8, r9, sl} + 23980: e2850024 add r0, r5, #36 ; 0x24 + 23984: ebf57fb7 bl 0xffd83868 + 23988: 0800073e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl} + 2398c: e1a03000 mov r3, r0 + 23990: ebf5817a bl 0xffd83f80 + 23994: 0800073c stmeqda r0, {r2, r3, r4, r5, r8, r9, sl} + 23998: e2840000 add r0, r4, #0 ; 0x0 + 2399c: e1a01003 mov r1, r3 + 239a0: ebf57ee9 bl 0xffd8354c + 239a4: 0800073e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl} + 239a8: ebf58174 bl 0xffd83f80 + 239ac: 0800073e stmeqda r0, {r1, r2, r3, r4, r5, r8, r9, sl} + 239b0: e1a01004 mov r1, r4 + 239b4: e2944002 adds r4, r4, #2 ; 0x2 + 239b8: ebf58170 bl 0xffd83f80 + 239bc: 08000740 stmeqda r0, {r6, r8, r9, sl} + 239c0: e2850026 add r0, r5, #38 ; 0x26 + 239c4: ebf57fa7 bl 0xffd83868 + 239c8: 08000744 stmeqda r0, {r2, r6, r8, r9, sl} + 239cc: e1a03000 mov r3, r0 + 239d0: ebf5816a bl 0xffd83f80 + 239d4: 08000742 stmeqda r0, {r1, r6, r8, r9, sl} + 239d8: e2840000 add r0, r4, #0 ; 0x0 + 239dc: e1a01003 mov r1, r3 + 239e0: ebf57ed9 bl 0xffd8354c + 239e4: 08000744 stmeqda r0, {r2, r6, r8, r9, sl} + 239e8: ebf58164 bl 0xffd83f80 + 239ec: 08000744 stmeqda r0, {r2, r6, r8, r9, sl} + 239f0: e1a01004 mov r1, r4 + 239f4: e2944002 adds r4, r4, #2 ; 0x2 + 239f8: ebf58160 bl 0xffd83f80 + 239fc: 08000746 stmeqda r0, {r1, r2, r6, r8, r9, sl} + 23a00: e2850028 add r0, r5, #40 ; 0x28 + 23a04: ebf57f97 bl 0xffd83868 + 23a08: 0800074a stmeqda r0, {r1, r3, r6, r8, r9, sl} + 23a0c: e1a03000 mov r3, r0 + 23a10: ebf5815a bl 0xffd83f80 + 23a14: 08000748 stmeqda r0, {r3, r6, r8, r9, sl} + 23a18: e2840000 add r0, r4, #0 ; 0x0 + 23a1c: e1a01003 mov r1, r3 + 23a20: ebf57ec9 bl 0xffd8354c + 23a24: 0800074a stmeqda r0, {r1, r3, r6, r8, r9, sl} + 23a28: ebf58154 bl 0xffd83f80 + 23a2c: 0800074a stmeqda r0, {r1, r3, r6, r8, r9, sl} + 23a30: e1a01004 mov r1, r4 + 23a34: e2944002 adds r4, r4, #2 ; 0x2 + 23a38: ebf58150 bl 0xffd83f80 + 23a3c: 0800074c stmeqda r0, {r2, r3, r6, r8, r9, sl} + 23a40: e285002a add r0, r5, #42 ; 0x2a + 23a44: ebf57f87 bl 0xffd83868 + 23a48: 08000750 stmeqda r0, {r4, r6, r8, r9, sl} + 23a4c: e1a03000 mov r3, r0 + 23a50: ebf5814a bl 0xffd83f80 + 23a54: 0800074e stmeqda r0, {r1, r2, r3, r6, r8, r9, sl} + 23a58: e2840000 add r0, r4, #0 ; 0x0 + 23a5c: e1a01003 mov r1, r3 + 23a60: ebf57eb9 bl 0xffd8354c + 23a64: 08000750 stmeqda r0, {r4, r6, r8, r9, sl} + 23a68: ebf58144 bl 0xffd83f80 + 23a6c: 08000750 stmeqda r0, {r4, r6, r8, r9, sl} + 23a70: e1a01004 mov r1, r4 + 23a74: e2944002 adds r4, r4, #2 ; 0x2 + 23a78: ebf58140 bl 0xffd83f80 + 23a7c: 08000752 stmeqda r0, {r1, r4, r6, r8, r9, sl} + 23a80: e285002c add r0, r5, #44 ; 0x2c + 23a84: ebf57f77 bl 0xffd83868 + 23a88: 08000756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl} + 23a8c: e1a03000 mov r3, r0 + 23a90: ebf5813a bl 0xffd83f80 + 23a94: 08000754 stmeqda r0, {r2, r4, r6, r8, r9, sl} + 23a98: e2840000 add r0, r4, #0 ; 0x0 + 23a9c: e1a01003 mov r1, r3 + 23aa0: ebf57ea9 bl 0xffd8354c + 23aa4: 08000756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl} + 23aa8: ebf58134 bl 0xffd83f80 + 23aac: 08000756 stmeqda r0, {r1, r2, r4, r6, r8, r9, sl} + 23ab0: e1a01004 mov r1, r4 + 23ab4: e2944002 adds r4, r4, #2 ; 0x2 + 23ab8: ebf58130 bl 0xffd83f80 + 23abc: 08000758 stmeqda r0, {r3, r4, r6, r8, r9, sl} + 23ac0: e285002e add r0, r5, #46 ; 0x2e + 23ac4: ebf57f67 bl 0xffd83868 + 23ac8: 0800075c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl} + 23acc: e1a03000 mov r3, r0 + 23ad0: ebf5812a bl 0xffd83f80 + 23ad4: 0800075a stmeqda r0, {r1, r3, r4, r6, r8, r9, sl} + 23ad8: e2840000 add r0, r4, #0 ; 0x0 + 23adc: e1a01003 mov r1, r3 + 23ae0: ebf57e99 bl 0xffd8354c + 23ae4: 0800075c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl} + 23ae8: ebf58124 bl 0xffd83f80 + 23aec: 0800075c stmeqda r0, {r2, r3, r4, r6, r8, r9, sl} + 23af0: e1a01004 mov r1, r4 + 23af4: e2944002 adds r4, r4, #2 ; 0x2 + 23af8: ebf58120 bl 0xffd83f80 + 23afc: 0800075e stmeqda r0, {r1, r2, r3, r4, r6, r8, r9, sl} + 23b00: e2850030 add r0, r5, #48 ; 0x30 + 23b04: ebf57f57 bl 0xffd83868 + 23b08: 08000762 stmeqda r0, {r1, r5, r6, r8, r9, sl} + 23b0c: e1a03000 mov r3, r0 + 23b10: ebf5811a bl 0xffd83f80 + 23b14: 08000760 stmeqda r0, {r5, r6, r8, r9, sl} + 23b18: e2840000 add r0, r4, #0 ; 0x0 + 23b1c: e1a01003 mov r1, r3 + 23b20: ebf57e89 bl 0xffd8354c + 23b24: 08000762 stmeqda r0, {r1, r5, r6, r8, r9, sl} + 23b28: ebf58114 bl 0xffd83f80 + 23b2c: 08000762 stmeqda r0, {r1, r5, r6, r8, r9, sl} + 23b30: e1a01004 mov r1, r4 + 23b34: e2944002 adds r4, r4, #2 ; 0x2 + 23b38: ebf58110 bl 0xffd83f80 + 23b3c: 08000764 stmeqda r0, {r2, r5, r6, r8, r9, sl} + 23b40: e2850032 add r0, r5, #50 ; 0x32 + 23b44: ebf57f47 bl 0xffd83868 + 23b48: 08000768 stmeqda r0, {r3, r5, r6, r8, r9, sl} + 23b4c: e1a03000 mov r3, r0 + 23b50: ebf5810a bl 0xffd83f80 + 23b54: 08000766 stmeqda r0, {r1, r2, r5, r6, r8, r9, sl} + 23b58: e2840000 add r0, r4, #0 ; 0x0 + 23b5c: e1a01003 mov r1, r3 + 23b60: ebf57e79 bl 0xffd8354c + 23b64: 08000768 stmeqda r0, {r3, r5, r6, r8, r9, sl} + 23b68: ebf58104 bl 0xffd83f80 + 23b6c: 08000768 stmeqda r0, {r3, r5, r6, r8, r9, sl} + 23b70: e1a01004 mov r1, r4 + 23b74: e2944002 adds r4, r4, #2 ; 0x2 + 23b78: ebf58100 bl 0xffd83f80 + 23b7c: 0800076a stmeqda r0, {r1, r3, r5, r6, r8, r9, sl} + 23b80: e2850034 add r0, r5, #52 ; 0x34 + 23b84: ebf57f37 bl 0xffd83868 + 23b88: 0800076e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl} + 23b8c: e1a03000 mov r3, r0 + 23b90: ebf580fa bl 0xffd83f80 + 23b94: 0800076c stmeqda r0, {r2, r3, r5, r6, r8, r9, sl} + 23b98: e2840000 add r0, r4, #0 ; 0x0 + 23b9c: e1a01003 mov r1, r3 + 23ba0: ebf57e69 bl 0xffd8354c + 23ba4: 0800076e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl} + 23ba8: ebf580f4 bl 0xffd83f80 + 23bac: 0800076e stmeqda r0, {r1, r2, r3, r5, r6, r8, r9, sl} + 23bb0: e1a01004 mov r1, r4 + 23bb4: e2944002 adds r4, r4, #2 ; 0x2 + 23bb8: ebf580f0 bl 0xffd83f80 + 23bbc: 08000770 stmeqda r0, {r4, r5, r6, r8, r9, sl} + 23bc0: e2850036 add r0, r5, #54 ; 0x36 + 23bc4: ebf57f27 bl 0xffd83868 + 23bc8: 08000774 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl} + 23bcc: e1a03000 mov r3, r0 + 23bd0: ebf580ea bl 0xffd83f80 + 23bd4: 08000772 stmeqda r0, {r1, r4, r5, r6, r8, r9, sl} + 23bd8: e2840000 add r0, r4, #0 ; 0x0 + 23bdc: e1a01003 mov r1, r3 + 23be0: ebf57e59 bl 0xffd8354c + 23be4: 08000774 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl} + 23be8: ebf580e4 bl 0xffd83f80 + 23bec: 08000774 stmeqda r0, {r2, r4, r5, r6, r8, r9, sl} + 23bf0: e1a01004 mov r1, r4 + 23bf4: e2944002 adds r4, r4, #2 ; 0x2 + 23bf8: ebf580e0 bl 0xffd83f80 + 23bfc: 08000776 stmeqda r0, {r1, r2, r4, r5, r6, r8, r9, sl} + 23c00: e2850038 add r0, r5, #56 ; 0x38 + 23c04: ebf57f17 bl 0xffd83868 + 23c08: 0800077a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, sl} + 23c0c: e1a03000 mov r3, r0 + 23c10: ebf580da bl 0xffd83f80 + 23c14: 08000778 stmeqda r0, {r3, r4, r5, r6, r8, r9, sl} + 23c18: e2840000 add r0, r4, #0 ; 0x0 + 23c1c: e1a01003 mov r1, r3 + 23c20: ebf57e49 bl 0xffd8354c + 23c24: 0800077a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, sl} + 23c28: ebf580d4 bl 0xffd83f80 + 23c2c: 0800077a stmeqda r0, {r1, r3, r4, r5, r6, r8, r9, sl} + 23c30: e1a01004 mov r1, r4 + 23c34: e2944002 adds r4, r4, #2 ; 0x2 + 23c38: ebf580d0 bl 0xffd83f80 + 23c3c: 0800077c stmeqda r0, {r2, r3, r4, r5, r6, r8, r9, sl} + 23c40: e285003a add r0, r5, #58 ; 0x3a + 23c44: ebf57f07 bl 0xffd83868 + 23c48: 08000780 stmeqda r0, {r7, r8, r9, sl} + 23c4c: e1a03000 mov r3, r0 + 23c50: ebf580ca bl 0xffd83f80 + 23c54: 0800077e stmeqda r0, {r1, r2, r3, r4, r5, r6, r8, r9, sl} + 23c58: e2840000 add r0, r4, #0 ; 0x0 + 23c5c: e1a01003 mov r1, r3 + 23c60: ebf57e39 bl 0xffd8354c + 23c64: 08000780 stmeqda r0, {r7, r8, r9, sl} + 23c68: ebf580c4 bl 0xffd83f80 + 23c6c: 08000780 stmeqda r0, {r7, r8, r9, sl} + 23c70: e1a01004 mov r1, r4 + 23c74: e2944002 adds r4, r4, #2 ; 0x2 + 23c78: ebf580c0 bl 0xffd83f80 + 23c7c: 08000782 stmeqda r0, {r1, r7, r8, r9, sl} + 23c80: e285003c add r0, r5, #60 ; 0x3c + 23c84: ebf57ef7 bl 0xffd83868 + 23c88: 08000786 stmeqda r0, {r1, r2, r7, r8, r9, sl} + 23c8c: e1a03000 mov r3, r0 + 23c90: ebf580ba bl 0xffd83f80 + 23c94: 08000784 stmeqda r0, {r2, r7, r8, r9, sl} + 23c98: e2840000 add r0, r4, #0 ; 0x0 + 23c9c: e1a01003 mov r1, r3 + 23ca0: ebf57e29 bl 0xffd8354c + 23ca4: 08000786 stmeqda r0, {r1, r2, r7, r8, r9, sl} + 23ca8: ebf580b4 bl 0xffd83f80 + 23cac: 08000786 stmeqda r0, {r1, r2, r7, r8, r9, sl} + 23cb0: e1a01004 mov r1, r4 + 23cb4: e2944002 adds r4, r4, #2 ; 0x2 + 23cb8: ebf580b0 bl 0xffd83f80 + 23cbc: 08000788 stmeqda r0, {r3, r7, r8, r9, sl} + 23cc0: e285003e add r0, r5, #62 ; 0x3e + 23cc4: ebf57ee7 bl 0xffd83868 + 23cc8: 0800078c stmeqda r0, {r2, r3, r7, r8, r9, sl} + 23ccc: e1a03000 mov r3, r0 + 23cd0: ebf580aa bl 0xffd83f80 + 23cd4: 0800078a stmeqda r0, {r1, r3, r7, r8, r9, sl} + 23cd8: e2840000 add r0, r4, #0 ; 0x0 + 23cdc: e1a01003 mov r1, r3 + 23ce0: ebf57e19 bl 0xffd8354c + 23ce4: 0800078c stmeqda r0, {r2, r3, r7, r8, r9, sl} + 23ce8: ebf580a4 bl 0xffd83f80 + 23cec: 0800078c stmeqda r0, {r2, r3, r7, r8, r9, sl} + 23cf0: e1a01004 mov r1, r4 + 23cf4: e2944002 adds r4, r4, #2 ; 0x2 + 23cf8: ebf580a0 bl 0xffd83f80 + 23cfc: 0800078e stmeqda r0, {r1, r2, r3, r7, r8, r9, sl} + 23d00: e1a01005 mov r1, r5 + 23d04: e2953000 adds r3, r5, #0 ; 0x0 + 23d08: ebf5809c bl 0xffd83f80 + 23d0c: 08000790 stmeqda r0, {r4, r7, r8, r9, sl} + 23d10: e1a01003 mov r1, r3 + 23d14: e2933040 adds r3, r3, #64 ; 0x40 + 23d18: ebf58098 bl 0xffd83f80 + 23d1c: 08000792 stmeqda r0, {r1, r4, r7, r8, r9, sl} + 23d20: e2830000 add r0, r3, #0 ; 0x0 + 23d24: ebf57ecf bl 0xffd83868 + 23d28: 08000796 stmeqda r0, {r1, r2, r4, r7, r8, r9, sl} + 23d2c: e1a03000 mov r3, r0 + 23d30: ebf58092 bl 0xffd83f80 + 23d34: 08000794 stmeqda r0, {r2, r4, r7, r8, r9, sl} + 23d38: e2840000 add r0, r4, #0 ; 0x0 + 23d3c: e1a01003 mov r1, r3 + 23d40: ebf57e01 bl 0xffd8354c + 23d44: 08000796 stmeqda r0, {r1, r2, r4, r7, r8, r9, sl} + 23d48: ebf5808c bl 0xffd83f80 + 23d4c: 08000796 stmeqda r0, {r1, r2, r4, r7, r8, r9, sl} + 23d50: e1a01004 mov r1, r4 + 23d54: e2944002 adds r4, r4, #2 ; 0x2 + 23d58: ebf58088 bl 0xffd83f80 + 23d5c: 08000798 stmeqda r0, {r3, r4, r7, r8, r9, sl} + 23d60: e1a01005 mov r1, r5 + 23d64: e2953000 adds r3, r5, #0 ; 0x0 + 23d68: ebf58084 bl 0xffd83f80 + 23d6c: 0800079a stmeqda r0, {r1, r3, r4, r7, r8, r9, sl} + 23d70: e1a01003 mov r1, r3 + 23d74: e2933042 adds r3, r3, #66 ; 0x42 + 23d78: ebf58080 bl 0xffd83f80 + 23d7c: 0800079c stmeqda r0, {r2, r3, r4, r7, r8, r9, sl} + 23d80: e2830000 add r0, r3, #0 ; 0x0 + 23d84: ebf57eb7 bl 0xffd83868 + 23d88: 080007a0 stmeqda r0, {r5, r7, r8, r9, sl} + 23d8c: e1a03000 mov r3, r0 + 23d90: ebf5807a bl 0xffd83f80 + 23d94: 0800079e stmeqda r0, {r1, r2, r3, r4, r7, r8, r9, sl} + 23d98: e2840000 add r0, r4, #0 ; 0x0 + 23d9c: e1a01003 mov r1, r3 + 23da0: ebf57de9 bl 0xffd8354c + 23da4: 080007a0 stmeqda r0, {r5, r7, r8, r9, sl} + 23da8: ebf58074 bl 0xffd83f80 + 23dac: 080007a0 stmeqda r0, {r5, r7, r8, r9, sl} + 23db0: e1a01004 mov r1, r4 + 23db4: e2944002 adds r4, r4, #2 ; 0x2 + 23db8: ebf58070 bl 0xffd83f80 + 23dbc: 080007a2 stmeqda r0, {r1, r5, r7, r8, r9, sl} + 23dc0: e1a01005 mov r1, r5 + 23dc4: e2953000 adds r3, r5, #0 ; 0x0 + 23dc8: ebf5806c bl 0xffd83f80 + 23dcc: 080007a4 stmeqda r0, {r2, r5, r7, r8, r9, sl} + 23dd0: e1a01003 mov r1, r3 + 23dd4: e2933044 adds r3, r3, #68 ; 0x44 + 23dd8: ebf58068 bl 0xffd83f80 + 23ddc: 080007a6 stmeqda r0, {r1, r2, r5, r7, r8, r9, sl} + 23de0: e2830000 add r0, r3, #0 ; 0x0 + 23de4: ebf57e9f bl 0xffd83868 + 23de8: 080007aa stmeqda r0, {r1, r3, r5, r7, r8, r9, sl} + 23dec: e1a03000 mov r3, r0 + 23df0: ebf58062 bl 0xffd83f80 + 23df4: 080007a8 stmeqda r0, {r3, r5, r7, r8, r9, sl} + 23df8: e2840000 add r0, r4, #0 ; 0x0 + 23dfc: e1a01003 mov r1, r3 + 23e00: ebf57dd1 bl 0xffd8354c + 23e04: 080007aa stmeqda r0, {r1, r3, r5, r7, r8, r9, sl} + 23e08: ebf5805c bl 0xffd83f80 + 23e0c: 080007aa stmeqda r0, {r1, r3, r5, r7, r8, r9, sl} + 23e10: e1a01004 mov r1, r4 + 23e14: e2944002 adds r4, r4, #2 ; 0x2 + 23e18: ebf58058 bl 0xffd83f80 + 23e1c: 080007ac stmeqda r0, {r2, r3, r5, r7, r8, r9, sl} + 23e20: e1a01005 mov r1, r5 + 23e24: e2953000 adds r3, r5, #0 ; 0x0 + 23e28: ebf58054 bl 0xffd83f80 + 23e2c: 080007ae stmeqda r0, {r1, r2, r3, r5, r7, r8, r9, sl} + 23e30: e1a01003 mov r1, r3 + 23e34: e2933046 adds r3, r3, #70 ; 0x46 + 23e38: ebf58050 bl 0xffd83f80 + 23e3c: 080007b0 stmeqda r0, {r4, r5, r7, r8, r9, sl} + 23e40: e2830000 add r0, r3, #0 ; 0x0 + 23e44: ebf57e87 bl 0xffd83868 + 23e48: 080007b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, sl} + 23e4c: e1a03000 mov r3, r0 + 23e50: ebf5804a bl 0xffd83f80 + 23e54: 080007b2 stmeqda r0, {r1, r4, r5, r7, r8, r9, sl} + 23e58: e2840000 add r0, r4, #0 ; 0x0 + 23e5c: e1a01003 mov r1, r3 + 23e60: ebf57db9 bl 0xffd8354c + 23e64: 080007b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, sl} + 23e68: ebf58044 bl 0xffd83f80 + 23e6c: 080007b4 stmeqda r0, {r2, r4, r5, r7, r8, r9, sl} + 23e70: e1a01004 mov r1, r4 + 23e74: e2944002 adds r4, r4, #2 ; 0x2 + 23e78: ebf58040 bl 0xffd83f80 + 23e7c: 080007b6 stmeqda r0, {r1, r2, r4, r5, r7, r8, r9, sl} + 23e80: e1a01005 mov r1, r5 + 23e84: e2953000 adds r3, r5, #0 ; 0x0 + 23e88: ebf5803c bl 0xffd83f80 + 23e8c: 080007b8 stmeqda r0, {r3, r4, r5, r7, r8, r9, sl} + 23e90: e1a01003 mov r1, r3 + 23e94: e2933048 adds r3, r3, #72 ; 0x48 + 23e98: ebf58038 bl 0xffd83f80 + 23e9c: 080007ba stmeqda r0, {r1, r3, r4, r5, r7, r8, r9, sl} + 23ea0: e2830000 add r0, r3, #0 ; 0x0 + 23ea4: ebf57e6f bl 0xffd83868 + 23ea8: 080007be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 23eac: e1a03000 mov r3, r0 + 23eb0: ebf58032 bl 0xffd83f80 + 23eb4: 080007bc stmeqda r0, {r2, r3, r4, r5, r7, r8, r9, sl} + 23eb8: e2840000 add r0, r4, #0 ; 0x0 + 23ebc: e1a01003 mov r1, r3 + 23ec0: ebf57da1 bl 0xffd8354c + 23ec4: 080007be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 23ec8: ebf5802c bl 0xffd83f80 + 23ecc: 080007be stmeqda r0, {r1, r2, r3, r4, r5, r7, r8, r9, sl} + 23ed0: e1a01004 mov r1, r4 + 23ed4: e2944002 adds r4, r4, #2 ; 0x2 + 23ed8: ebf58028 bl 0xffd83f80 + 23edc: 080007c0 stmeqda r0, {r6, r7, r8, r9, sl} + 23ee0: e1a01005 mov r1, r5 + 23ee4: e2953000 adds r3, r5, #0 ; 0x0 + 23ee8: ebf58024 bl 0xffd83f80 + 23eec: 080007c2 stmeqda r0, {r1, r6, r7, r8, r9, sl} + 23ef0: e1a01003 mov r1, r3 + 23ef4: e293304a adds r3, r3, #74 ; 0x4a + 23ef8: ebf58020 bl 0xffd83f80 + 23efc: 080007c4 stmeqda r0, {r2, r6, r7, r8, r9, sl} + 23f00: e2830000 add r0, r3, #0 ; 0x0 + 23f04: ebf57e57 bl 0xffd83868 + 23f08: 080007c8 stmeqda r0, {r3, r6, r7, r8, r9, sl} + 23f0c: e1a03000 mov r3, r0 + 23f10: ebf5801a bl 0xffd83f80 + 23f14: 080007c6 stmeqda r0, {r1, r2, r6, r7, r8, r9, sl} + 23f18: e2840000 add r0, r4, #0 ; 0x0 + 23f1c: e1a01003 mov r1, r3 + 23f20: ebf57d89 bl 0xffd8354c + 23f24: 080007c8 stmeqda r0, {r3, r6, r7, r8, r9, sl} + 23f28: ebf58014 bl 0xffd83f80 + 23f2c: 080007c8 stmeqda r0, {r3, r6, r7, r8, r9, sl} + 23f30: e1a01004 mov r1, r4 + 23f34: e2944002 adds r4, r4, #2 ; 0x2 + 23f38: ebf58010 bl 0xffd83f80 + 23f3c: 080007ca stmeqda r0, {r1, r3, r6, r7, r8, r9, sl} + 23f40: e1a01005 mov r1, r5 + 23f44: e2953000 adds r3, r5, #0 ; 0x0 + 23f48: ebf5800c bl 0xffd83f80 + 23f4c: 080007cc stmeqda r0, {r2, r3, r6, r7, r8, r9, sl} + 23f50: e1a01003 mov r1, r3 + 23f54: e293304c adds r3, r3, #76 ; 0x4c + 23f58: ebf58008 bl 0xffd83f80 + 23f5c: 080007ce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9, sl} + 23f60: e2830000 add r0, r3, #0 ; 0x0 + 23f64: ebf57e3f bl 0xffd83868 + 23f68: 080007d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, sl} + 23f6c: e1a03000 mov r3, r0 + 23f70: ebf58002 bl 0xffd83f80 + 23f74: 080007d0 stmeqda r0, {r4, r6, r7, r8, r9, sl} + 23f78: e2840000 add r0, r4, #0 ; 0x0 + 23f7c: e1a01003 mov r1, r3 + 23f80: ebf57d71 bl 0xffd8354c + 23f84: 080007d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, sl} + 23f88: ebf57ffc bl 0xffd83f80 + 23f8c: 080007d2 stmeqda r0, {r1, r4, r6, r7, r8, r9, sl} + 23f90: e59d0438 ldr r0, [sp, #1080] + 23f94: e28ccc02 add ip, ip, #512 ; 0x200 + 23f98: e28cc009 add ip, ip, #9 ; 0x9 + 23f9c: eaf57c4b b 0xffd830d0 + 23fa0: 080057d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, ip, lr} + 23fa4: 00000000 andeq r0, r0, r0 + 23fa8: ebf57ff4 bl 0xffd83f80 + 23fac: 080057d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, ip, lr} + 23fb0: e3a00e7f mov r0, #2032 ; 0x7f0 + 23fb4: e3800a05 orr r0, r0, #20480 ; 0x5000 + 23fb8: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 23fbc: ebf57e55 bl 0xffd83918 + 23fc0: 080057d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl, ip, lr} + 23fc4: e1a03000 mov r3, r0 + 23fc8: ebf57fec bl 0xffd83f80 + 23fcc: 080057d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9, sl, ip, lr} + 23fd0: e283000a add r0, r3, #10 ; 0xa + 23fd4: ebf57df8 bl 0xffd837bc + 23fd8: 080057da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, sl, ip, lr} + 23fdc: e1a03000 mov r3, r0 + 23fe0: ebf57fe6 bl 0xffd83f80 + 23fe4: 080057d8 stmeqda r0, {r3, r4, r6, r7, r8, r9, sl, ip, lr} + 23fe8: e3530000 cmp r3, #0 ; 0x0 + 23fec: ebf57fe3 bl 0xffd83f80 + 23ff0: 080057da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9, sl, ip, lr} + 23ff4: e28cc010 add ip, ip, #16 ; 0x10 + 23ff8: 0a000004 beq 0x24010 + 23ffc: e1a00fac mov r0, ip, lsr #31 + 24000: e08ff100 add pc, pc, r0, lsl #2 + 24004: 080057ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, ip, lr} + 24008: ebf57bd1 bl 0xffd82f54 + 2400c: ea00002d b 0x240c8 + 24010: ebf57fda bl 0xffd83f80 + 24014: 080057dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9, sl, ip, lr} + 24018: e3a00ffd mov r0, #1012 ; 0x3f4 + 2401c: e3800b15 orr r0, r0, #21504 ; 0x5400 + 24020: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 24024: ebf57e3b bl 0xffd83918 + 24028: 080057e0 stmeqda r0, {r5, r6, r7, r8, r9, sl, ip, lr} + 2402c: e1a04000 mov r4, r0 + 24030: ebf57fd2 bl 0xffd83f80 + 24034: 080057de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9, sl, ip, lr} + 24038: e2840000 add r0, r4, #0 ; 0x0 + 2403c: ebf57e35 bl 0xffd83918 + 24040: 080057e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl, ip, lr} + 24044: e1a03000 mov r3, r0 + 24048: ebf57fcc bl 0xffd83f80 + 2404c: 080057e0 stmeqda r0, {r5, r6, r7, r8, r9, sl, ip, lr} + 24050: e1a01003 mov r1, r3 + 24054: e2933001 adds r3, r3, #1 ; 0x1 + 24058: ebf57fc8 bl 0xffd83f80 + 2405c: 080057e2 stmeqda r0, {r1, r5, r6, r7, r8, r9, sl, ip, lr} + 24060: e2840000 add r0, r4, #0 ; 0x0 + 24064: e1a01003 mov r1, r3 + 24068: ebf57d57 bl 0xffd835cc + 2406c: 080057e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl, ip, lr} + 24070: ebf57fc2 bl 0xffd83f80 + 24074: 080057e4 stmeqda r0, {r2, r5, r6, r7, r8, r9, sl, ip, lr} + 24078: e3530000 cmp r3, #0 ; 0x0 + 2407c: ebf57fbf bl 0xffd83f80 + 24080: 080057e6 stmeqda r0, {r1, r2, r5, r6, r7, r8, r9, sl, ip, lr} + 24084: e28cc017 add ip, ip, #23 ; 0x17 + 24088: 0a000004 beq 0x240a0 + 2408c: e1a00fac mov r0, ip, lsr #31 + 24090: e08ff100 add pc, pc, r0, lsl #2 + 24094: 080057ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, ip, lr} + 24098: ebf57bad bl 0xffd82f54 + 2409c: ea000009 b 0x240c8 + 240a0: ebf57fb6 bl 0xffd83f80 + 240a4: 080057e8 stmeqda r0, {r3, r5, r6, r7, r8, r9, sl, ip, lr} + 240a8: e3b03001 movs r3, #1 ; 0x1 + 240ac: ebf57fb3 bl 0xffd83f80 + 240b0: 080057ea stmeqda r0, {r1, r3, r5, r6, r7, r8, r9, sl, ip, lr} + 240b4: e2840000 add r0, r4, #0 ; 0x0 + 240b8: e1a01003 mov r1, r3 + 240bc: ebf57d42 bl 0xffd835cc + 240c0: 080057ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, ip, lr} + 240c4: e28cc007 add ip, ip, #7 ; 0x7 + 240c8: ebf57fac bl 0xffd83f80 + 240cc: 080057ec stmeqda r0, {r2, r3, r5, r6, r7, r8, r9, sl, ip, lr} + 240d0: e59d0438 ldr r0, [sp, #1080] + 240d4: e28cc003 add ip, ip, #3 ; 0x3 + 240d8: eaf57bfc b 0xffd830d0 + 240dc: 080003cc stmeqda r0, {r2, r3, r6, r7, r8, r9} + 240e0: 00000000 andeq r0, r0, r0 + 240e4: ebf57fa5 bl 0xffd83f80 + 240e8: 080003cc stmeqda r0, {r2, r3, r6, r7, r8, r9} + 240ec: e2880012 add r0, r8, #18 ; 0x12 + 240f0: ebf57ddc bl 0xffd83868 + 240f4: 080003d0 stmeqda r0, {r4, r6, r7, r8, r9} + 240f8: e1a03000 mov r3, r0 + 240fc: ebf57f9f bl 0xffd83f80 + 24100: 080003ce stmeqda r0, {r1, r2, r3, r6, r7, r8, r9} + 24104: e1b03803 movs r3, r3, lsl #16 + 24108: ebf57f9c bl 0xffd83f80 + 2410c: 080003d0 stmeqda r0, {r4, r6, r7, r8, r9} + 24110: e3530000 cmp r3, #0 ; 0x0 + 24114: ebf57f99 bl 0xffd83f80 + 24118: 080003d2 stmeqda r0, {r1, r4, r6, r7, r8, r9} + 2411c: e28cc00e add ip, ip, #14 ; 0xe + 24120: aa000002 bge 0x24130 + 24124: ebf57b8a bl 0xffd82f54 + 24128: 080003c8 stmeqda r0, {r3, r6, r7, r8, r9} + 2412c: ea00002e b 0x241ec + 24130: ebf57f92 bl 0xffd83f80 + 24134: 080003d4 stmeqda r0, {r2, r4, r6, r7, r8, r9} + 24138: e2870012 add r0, r7, #18 ; 0x12 + 2413c: ebf57dc9 bl 0xffd83868 + 24140: 080003d8 stmeqda r0, {r3, r4, r6, r7, r8, r9} + 24144: e1a03000 mov r3, r0 + 24148: ebf57f8c bl 0xffd83f80 + 2414c: 080003d6 stmeqda r0, {r1, r2, r4, r6, r7, r8, r9} + 24150: e3b03000 movs r3, #0 ; 0x0 + 24154: ebf57f89 bl 0xffd83f80 + 24158: 080003d8 stmeqda r0, {r3, r4, r6, r7, r8, r9} + 2415c: e2870012 add r0, r7, #18 ; 0x12 + 24160: e1a01003 mov r1, r3 + 24164: ebf57cf8 bl 0xffd8354c + 24168: 080003da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9} + 2416c: ebf57f83 bl 0xffd83f80 + 24170: 080003da stmeqda r0, {r1, r3, r4, r6, r7, r8, r9} + 24174: e2870008 add r0, r7, #8 ; 0x8 + 24178: ebf57de6 bl 0xffd83918 + 2417c: 080003de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9} + 24180: e1a03000 mov r3, r0 + 24184: ebf57f7d bl 0xffd83f80 + 24188: 080003dc stmeqda r0, {r2, r3, r4, r6, r7, r8, r9} + 2418c: e1a01003 mov r1, r3 + 24190: e2933001 adds r3, r3, #1 ; 0x1 + 24194: ebf57f79 bl 0xffd83f80 + 24198: 080003de stmeqda r0, {r1, r2, r3, r4, r6, r7, r8, r9} + 2419c: e2870008 add r0, r7, #8 ; 0x8 + 241a0: e1a01003 mov r1, r3 + 241a4: ebf57d08 bl 0xffd835cc + 241a8: 080003e0 stmeqda r0, {r5, r6, r7, r8, r9} + 241ac: ebf57f73 bl 0xffd83f80 + 241b0: 080003e0 stmeqda r0, {r5, r6, r7, r8, r9} + 241b4: ebf57f71 bl 0xffd83f80 + 241b8: 080003e2 stmeqda r0, {r1, r5, r6, r7, r8, r9} + 241bc: e3a000e5 mov r0, #229 ; 0xe5 + 241c0: e3800c03 orr r0, r0, #768 ; 0x300 + 241c4: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 241c8: e58d0438 str r0, [sp, #1080] + 241cc: e28cc01e add ip, ip, #30 ; 0x1e + 241d0: e1a00fac mov r0, ip, lsr #31 + 241d4: e08ff100 add pc, pc, r0, lsl #2 + 241d8: 080006c8 stmeqda r0, {r3, r6, r7, r9, sl} + 241dc: ebf57b5c bl 0xffd82f54 + 241e0: eafffcb6 b 0x234c0 + 241e4: 080003c8 stmeqda r0, {r3, r6, r7, r8, r9} + 241e8: 00000000 andeq r0, r0, r0 + 241ec: ebf57f63 bl 0xffd83f80 + 241f0: 080003c8 stmeqda r0, {r3, r6, r7, r8, r9} + 241f4: ebf57f61 bl 0xffd83f80 + 241f8: 080003ca stmeqda r0, {r1, r3, r6, r7, r8, r9} + 241fc: e3a000cd mov r0, #205 ; 0xcd + 24200: e3800c03 orr r0, r0, #768 ; 0x300 + 24204: e3800302 orr r0, r0, #134217728 ; 0x8000000 + 24208: e58d0438 str r0, [sp, #1080] + 2420c: e28cc006 add ip, ip, #6 ; 0x6 + 24210: e1a00fac mov r0, ip, lsr #31 + 24214: e08ff100 add pc, pc, r0, lsl #2 + 24218: 080057d4 stmeqda r0, {r2, r4, r6, r7, r8, r9, sl, ip, lr} + 2421c: ebf57b4c bl 0xffd82f54 + 24220: eaffff60 b 0x23fa8 diff --git a/gp2x/speedtest.c b/gp2x/speedtest.c new file mode 100644 index 0000000..b6ce78a --- /dev/null +++ b/gp2x/speedtest.c @@ -0,0 +1,205 @@ +/* speedtest.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0) + Copyright (C) 2006 god_at_hell + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include +#include +#include +#include +#include +#include + +#include "display.h" +#include "cpuctrl.h" +#include "gp2xminilib.h" + +void prim() +{ + //FILE *primout; + unsigned char cad[256]; + char p = 0; + int primnumber; + int l = 1; + float g = 0; + int i = 3; + + while(i != 500000) + { + int m = 2; + float temp = sqrt(i); + float ifloat = (float)i; + + if(temp == (int)temp) + { + m = i; + p = 1; + } + + while(m < temp) + { + g = ifloat/m; + if (g == (int)g) + { + m = i; + p = 1; + } + m++; + } + + if (p == 0) + { + l += 1; + primnumber = i; + sprintf(cad,"%u is primnumber",i); + v_putcad(1,13,0xffffff,0xB00000,cad); + //primout = fopen("/mnt/sd/primnumber.txt", "a"); + //fprintf(primout,"%u: %u\n", l, i); + //fclose(primout); + //execl("sync",NULL); + gp2x_video_flip(); + } + p = 0; + i++; + } +} + +void ant() +{ + int i,n; + unsigned char cad[256]; + short direction = 0; //clockwise ... 0 = Up, 1 = Right + unsigned short col1, col2; + col1=gp2x_video_color15(0,0,0,0); + col2=gp2x_video_color15(0xFF,0xFF,0xFF,0); + short antx = 200; + short anty = 140; + for(i = 0; i < 9000; i++) + { + for(n = 0; n < 500000; n++); + if(gp2x_screen15[(320*anty) + antx]==col1) + { + for(n = 0; n < 3; n++) + { + int m = 0; + for(m = 0; m < 3; m++) + { + gp2x_screen15[320*(anty+n)+antx+m] = col2; + } + } + sprintf(cad,"%u steps left ",8999-i); + v_putcad(1,3,0x000000,0xffffff,cad); + gp2x_video_flip(); + for(n = 0; n < 3; n++) + { + int m = 0; + for(m = 0; m < 3; m++) + { + gp2x_screen15[320*(anty+n)+antx+m] = col2; + } + } + sprintf(cad,"%u steps left ",8999-i); + v_putcad(1,3,0x000000,0xffffff,cad); + gp2x_video_flip(); + if(direction == 0) antx-=3; + if(direction == 1) anty-=3; + if(direction == 2) antx+=3; + if(direction == 3) anty+=3; + direction--; + if(direction < 0) direction=3; + } + if(gp2x_screen15[(320*anty) + antx]==col2) + { + for(n = 0; n < 3; n++) + { + int m = 0; + for(m = 0; m < 3; m++) + { + gp2x_screen15[320*(anty+n)+antx+m] = col1; + } + } + sprintf(cad,"%u steps left ",8999-i); + v_putcad(1,3,0x000000,0xffffff,cad); + gp2x_video_flip(); + for(n = 0; n < 3; n++) + { + int m = 0; + for(m = 0; m < 3; m++) + { + gp2x_screen15[320*(anty+n)+antx+m] = col1; + } + } + sprintf(cad,"%u steps left ",8999-i); + v_putcad(1,3,0x000000,0xffffff,cad); + gp2x_video_flip(); + if(direction == 0) antx+=3; + if(direction == 1) anty+=3; + if(direction == 2) antx-=3; + if(direction == 3) anty-=3; + direction++; + if(direction > 3) direction=0; + } + } +} + +void speedtest(short test) +{ + unsigned BACKGROUND; + if(test == 0) BACKGROUND=0xB00000; + if(test == 1) BACKGROUND=0xFFFFFF; + short start = 240; + short cpuspeed = start; + unsigned char cad[256]; + FILE *speed; + + do + { + speed = fopen("/mnt/sd/speed.txt", "w"); + ClearScreen(BACKGROUND); + if(test == 0) v_putcad(1,1,0x00ff00,BACKGROUND,"Prim-Speedtest"); + if(test == 1) v_putcad(1,1,0x006600,BACKGROUND,"Ant-Speedtest"); + v_putcad(1,6,0xffffff,BACKGROUND,"Testing Speed"); + if(cpuspeed > start) + { + sprintf(cad,"%uMhz checked",cpuspeed-5); + v_putcad(1,9,0xffffff,BACKGROUND,cad); + } + gp2x_video_flip(); + ClearScreen(BACKGROUND); + if(test == 0) v_putcad(1,1,0x00ff00,BACKGROUND,"Prim-Speedtest"); + if(test == 1) v_putcad(1,1,0x006600,BACKGROUND,"Ant-Speedtest"); + v_putcad(1,6,0xffffff,BACKGROUND,"Testing Speed"); + if(cpuspeed > start) + { + sprintf(cad,"%uMhz checked",cpuspeed-5); + if(test == 0) v_putcad(1,9,0xffffff,BACKGROUND,cad); + if(test == 1) v_putcad(1,9,0x000000,BACKGROUND,cad); + } + gp2x_video_flip(); + fprintf (speed,"set CPU-Frequency = %uMHz\r\n",cpuspeed); + set_FCLK(cpuspeed); + + if(test == 0) prim(); + if(test == 1) ant(); + + fprintf(speed,"%uMhz checked\n\n", cpuspeed); + cpuspeed = cpuspeed + 5; + fclose(speed); + execl("sync",NULL); + } + while(1); +} diff --git a/gp2x/speedtest.h b/gp2x/speedtest.h new file mode 100644 index 0000000..d3f5b3e --- /dev/null +++ b/gp2x/speedtest.h @@ -0,0 +1,3 @@ +void prim(); +void ant(); +void speedtest(short test); diff --git a/gp2x/video.S b/gp2x/video.S new file mode 100644 index 0000000..4838fe5 --- /dev/null +++ b/gp2x/video.S @@ -0,0 +1,78790 @@ + .file "video.c" + .text + .align 2 + .global render_scanline_text_base_normal + .type render_scanline_text_base_normal, %function +render_scanline_text_base_normal: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L516 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + add r5, ip, r0, asl #2 + ldrh lr, [r5, #18] + ldrh r4, [ip, #6] + add ip, ip, r0, asl #1 + add r4, r4, lr + mov r7, r4, asl #23 + ldrh r6, [ip, #8] + mov r7, r7, lsr #23 + ldrh r0, [r5, #16] + cmp r7, #255 + movls lr, #0 + movhi lr, #1 + mov r5, r6, lsr #14 + rsb fp, r1, r2 + ldr r2, .L516+4 + ands lr, lr, r5, lsr #1 + add r8, r3, r1, asl #1 + mov ip, r6, asl #3 + subne r3, r7, #256 + ldr r9, .L516+8 + ldr r2, [r2, r5, asl #2] + movne r3, r3, lsr #3 + moveq r3, r4, asl #3 + add r0, r0, r1 + and ip, ip, #63488 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + add ip, ip, r9 + mov r0, r0, asl #23 + addne r4, ip, r3, asl #6 + addeq r4, ip, r3 + mov r0, r0, lsr #23 + tst r5, #1 + andeq r0, r0, #255 + sub sp, sp, #8 + moveq r3, r0, lsr #3 + addeq sl, r4, r3, asl #1 + streq r4, [sp, #0] + beq .L9 + cmp r0, #255 + subhi r0, r0, #256 + movhi r3, r0, lsr #3 + movls r3, r0, lsr #3 + addhi r3, r4, r3, asl #1 + addls sl, r4, r3, asl #1 + addls r4, r4, #2048 + addhi sl, r3, #2048 + strhi r4, [sp, #0] + strls r4, [sp, #0] +.L9: + ands r5, r6, #128 + beq .L10 + and r3, r7, #7 + mov r2, r6, asl #12 + and r1, r0, #255 + mov r3, r3, asl #3 + and r2, r2, #49152 + add r2, r2, r3 + rsb r4, r1, #256 + mov r3, r3, asl #1 + rsb r3, r3, #56 + cmp fp, r4 + add r9, r2, r9 + str r3, [sp, #4] + and r0, r0, #7 + bls .L487 + cmp r0, #0 + moveq ip, r0 + bne .L488 +.L100: + rsb r3, ip, r4 + movs r7, r3, lsr #3 + beq .L124 + ldr lr, .L516+12 + mov r5, r8 + mov r6, #0 + b .L126 +.L490: + ldr r0, [ip, #4] + ldr ip, [ip, #0] + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r5, #6] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r5, #4] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r0, r0, lsr #24 + strh r2, [r5, #2] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + and r1, ip, #255 + strh r0, [r5, #0] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r5, #14] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r5, #12] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov ip, ip, lsr #24 + strh r3, [r5, #10] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, lr] + add r6, r6, #1 + cmp r7, r6 + strh ip, [r5, #8] @ movhi + add sl, sl, #2 + add r5, r5, #16 + beq .L489 +.L126: + ldrh r2, [sl, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + tst r2, #1024 + bne .L490 + ldmia ip, {r0, ip} @ phole ldm + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r5, #0] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r5, #2] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r0, r0, lsr #24 + strh r2, [r5, #4] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + and r1, ip, #255 + strh r0, [r5, #6] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r5, #8] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r5, #10] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov ip, ip, lsr #24 + strh r3, [r5, #12] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, lr] + add r6, r6, #1 + cmp r7, r6 + strh ip, [r5, #14] @ movhi + add sl, sl, #2 + add r5, r5, #16 + bne .L126 +.L489: + add r8, r8, r7, asl #4 +.L124: + rsb sl, r4, fp + movs r4, sl, lsr #3 + ldreq r3, [sp, #0] + beq .L136 + ldr lr, .L516+12 + ldr r6, [sp, #0] + mov r5, r8 + mov r7, #0 + b .L137 +.L492: + ldr r0, [ip, #4] + ldr ip, [ip, #0] + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r5, #6] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r5, #4] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r0, r0, lsr #24 + strh r2, [r5, #2] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + and r1, ip, #255 + strh r0, [r5, #0] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r5, #14] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r5, #12] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov ip, ip, lsr #24 + strh r3, [r5, #10] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, lr] + add r7, r7, #1 + cmp r4, r7 + strh ip, [r5, #8] @ movhi + add r6, r6, #2 + add r5, r5, #16 + beq .L491 +.L137: + ldrh r2, [r6, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + tst r2, #1024 + bne .L492 + ldmia ip, {r0, ip} @ phole ldm + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r5, #0] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r5, #2] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r0, r0, lsr #24 + strh r2, [r5, #4] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + and r1, ip, #255 + strh r0, [r5, #6] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r5, #8] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r5, #10] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov ip, ip, lsr #24 + strh r3, [r5, #12] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, lr] + add r7, r7, #1 + cmp r4, r7 + strh ip, [r5, #14] @ movhi + add r6, r6, #2 + add r5, r5, #16 + bne .L137 +.L491: + ldr r2, [sp, #0] + add r8, r8, r4, asl #4 + add r3, r2, r4, asl #1 +.L136: + ands r5, sl, #7 + beq .L431 + ldrh r4, [r3, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + tst r4, #1024 + beq .L147 + cmp r5, #3 + bhi .L493 + ldr r1, [ip, #4] + ldr lr, .L516+12 +.L152: + mov r0, #0 +.L153: + mov r3, r1, lsr #24 + mov r3, r3, asl #1 + add r0, r0, #1 + ldrh r3, [r3, lr] + cmp r5, r0 + strh r3, [r8], #2 @ movhi + mov r1, r1, asl #8 + bhi .L153 +.L431: + add sp, sp, #8 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L10: + and r1, r0, #255 + and r3, r7, #7 + mov r2, r6, asl #12 + mov r3, r3, asl #2 + and r2, r2, #49152 + rsb r4, r1, #256 + add r2, r2, r3 + cmp fp, r4 + mov r3, r3, asl #1 + add ip, r2, r9 + rsb lr, r3, #28 + and r0, r0, #7 + bls .L494 + cmp r0, #0 + moveq r6, r0 + bne .L495 +.L276: + rsb r3, r6, r4 + movs r9, r3, lsr #3 + beq .L296 + ldr r6, .L516+12 + mov r0, r8 + mov r7, #0 + b .L298 +.L496: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L329 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #14] @ movhi + streqh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r2, [r6, #0] + strneh r3, [r0, #0] @ movhi + streqh r2, [r0, #0] @ movhi +.L328: + add r7, r7, #1 + cmp r9, r7 + add r0, r0, #16 + beq .L354 +.L497: + add sl, sl, #2 +.L298: + ldrh r1, [sl, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, lr + tst r1, #1024 + bne .L496 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L329 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #0] @ movhi + streqh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r2, [r6, #0] + add r7, r7, #1 + strneh r3, [r0, #14] @ movhi + streqh r2, [r0, #14] @ movhi + cmp r9, r7 + add r0, r0, #16 + bne .L497 +.L354: + add r8, r8, r9, asl #4 +.L296: + rsb r9, r4, fp + movs r4, r9, lsr #3 + ldreq r2, [sp, #0] + beq .L358 + ldr r6, .L516+12 + ldr r7, [sp, #0] + mov r0, r8 + mov sl, #0 + b .L359 +.L499: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L390 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #14] @ movhi + streqh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r2, [r6, #0] + strneh r3, [r0, #0] @ movhi + streqh r2, [r0, #0] @ movhi +.L389: + add sl, sl, #1 + cmp r4, sl + add r0, r0, #16 + add r7, r7, #2 + beq .L498 +.L359: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, lr + tst r1, #1024 + bne .L499 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L390 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #0] @ movhi + streqh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r2, [r6, #0] + add sl, sl, #1 + strneh r3, [r0, #14] @ movhi + streqh r2, [r0, #14] @ movhi + cmp r4, sl + add r0, r0, #16 + add r7, r7, #2 + bne .L359 +.L498: + ldr r3, [sp, #0] + add r8, r8, r4, asl #4 + add r2, r3, r4, asl #1 +.L358: + ands r5, r9, #7 + beq .L431 + ldrh r4, [r2, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r3, ip, r3, asl #5 + mov r2, r4, lsr #12 + addne r3, r3, lr + tst r4, #1024 + mov r0, r2, asl #4 + beq .L419 + ldr r2, [r3, #0] + ldr ip, .L516+12 + mov r1, #0 +.L421: + movs r3, r2, lsr #28 + orr r3, r0, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldreqh r3, [ip, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp r5, r1 + mov r2, r2, asl #4 + add r8, r8, #2 + bne .L421 + b .L431 +.L494: + cmp r0, #0 + bne .L500 +.L161: + movs r9, fp, lsr #3 + beq .L200 + ldr r5, .L516+12 + mov r0, r8 + mov r6, sl + mov r7, #0 + b .L202 +.L502: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L233 + ands r3, r2, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #14] @ movhi + streqh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r2, [r5, #0] + strneh r3, [r0, #0] @ movhi + streqh r2, [r0, #0] @ movhi +.L232: + add r7, r7, #1 + cmp r9, r7 + add r0, r0, #16 + add r6, r6, #2 + beq .L501 +.L202: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r4, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, lr + tst r1, #1024 + bne .L502 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L233 + ands r3, r2, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #0] @ movhi + streqh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #2] @ movhi + streqh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #4] @ movhi + streqh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #6] @ movhi + streqh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #8] @ movhi + streqh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #10] @ movhi + streqh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + strneh r3, [r0, #12] @ movhi + streqh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r2, [r5, #0] + add r7, r7, #1 + strneh r3, [r0, #14] @ movhi + streqh r2, [r0, #14] @ movhi + cmp r9, r7 + add r0, r0, #16 + add r6, r6, #2 + bne .L202 +.L501: + add r8, r8, r9, asl #4 + add sl, sl, r9, asl #1 +.L200: + ands r4, fp, #7 + beq .L431 + ldrh r1, [sl, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r3, ip, r3, asl #5 + mov r2, r1, lsr #12 + addne r3, r3, lr + tst r1, #1024 + mov r0, r2, asl #4 + beq .L262 + ldr r2, [r3, #0] + ldr ip, .L516+12 + mov r1, #0 +.L264: + movs r3, r2, lsr #28 + orr r3, r0, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldreqh r3, [ip, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp r4, r1 + mov r2, r2, asl #4 + add r8, r8, #2 + bne .L264 + b .L431 +.L487: + cmp r0, #0 + bne .L503 +.L14: + movs lr, fp, lsr #3 + beq .L74 + ldr r5, .L516+12 + mov r4, r8 + mov r6, sl + mov r7, #0 + b .L76 +.L505: + ldr r0, [ip, #4] + ldr ip, [ip, #0] + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r4, #6] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r4, #4] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r0, r0, lsr #24 + strh r2, [r4, #2] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, r5] + and r1, ip, #255 + strh r0, [r4, #0] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r4, #14] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r4, #12] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + mov ip, ip, lsr #24 + strh r3, [r4, #10] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, r5] + add r7, r7, #1 + cmp lr, r7 + strh ip, [r4, #8] @ movhi + add r6, r6, #2 + add r4, r4, #16 + beq .L504 +.L76: + ldrh r2, [r6, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + tst r2, #1024 + bne .L505 + ldmia ip, {r0, ip} @ phole ldm + and r1, r0, #255 + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r3, r0, lsr #8 + and r3, r3, #255 + strh r1, [r4, #0] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + mov r2, r0, lsr #16 + and r2, r2, #255 + strh r3, [r4, #2] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r0, r0, lsr #24 + strh r2, [r4, #4] @ movhi + mov r0, r0, asl #1 + ldrh r0, [r0, r5] + and r1, ip, #255 + strh r0, [r4, #6] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r2, ip, lsr #8 + and r2, r2, #255 + strh r1, [r4, #8] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r3, ip, lsr #16 + and r3, r3, #255 + strh r2, [r4, #10] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + mov ip, ip, lsr #24 + strh r3, [r4, #12] @ movhi + mov ip, ip, asl #1 + ldrh ip, [ip, r5] + add r7, r7, #1 + cmp lr, r7 + strh ip, [r4, #14] @ movhi + add r6, r6, #2 + add r4, r4, #16 + bne .L76 +.L504: + add r8, r8, lr, asl #4 + add sl, sl, lr, asl #1 +.L74: + ands r4, fp, #7 + beq .L431 + ldrh r2, [sl, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + tst r2, #1024 + beq .L86 + cmp r4, #3 + bhi .L506 + ldr r1, [ip, #4] + ldr lr, .L516+12 +.L91: + mov r0, #0 +.L92: + mov r3, r1, lsr #24 + mov r3, r3, asl #1 + add r0, r0, #1 + ldrh r3, [r3, lr] + cmp r4, r0 + strh r3, [r8], #2 @ movhi + mov r1, r1, asl #8 + bhi .L92 + b .L431 +.L329: + ldrh r3, [r6, #0] + strh r3, [r0, #14] @ movhi + strh r3, [r0, #0] @ movhi + strh r3, [r0, #2] @ movhi + strh r3, [r0, #4] @ movhi + strh r3, [r0, #6] @ movhi + strh r3, [r0, #8] @ movhi + strh r3, [r0, #10] @ movhi + strh r3, [r0, #12] @ movhi + b .L328 +.L390: + ldrh r3, [r6, #0] + strh r3, [r0, #14] @ movhi + strh r3, [r0, #0] @ movhi + strh r3, [r0, #2] @ movhi + strh r3, [r0, #4] @ movhi + strh r3, [r0, #6] @ movhi + strh r3, [r0, #8] @ movhi + strh r3, [r0, #10] @ movhi + strh r3, [r0, #12] @ movhi + b .L389 +.L517: + .align 2 +.L516: + .word io_registers + .word map_widths + .word vram + .word palette_ram_converted +.L500: + rsb r4, r0, #8 + cmp fp, r4 + bcs .L163 + ldrh r1, [sl, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add ip, ip, r3, asl #5 + mov r2, r1, lsr #12 + addne ip, ip, lr + tst r1, #1024 + mov r4, r2, asl #4 + bne .L507 + cmp fp, #0 + ldr r2, [ip, #0] + beq .L431 + mov r3, r0, asl #2 + mov r0, r2, lsr r3 + ldr r2, .L516+12 + mov r1, #0 +.L176: + ands r3, r0, #15 + orr r3, r4, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldreqh r3, [r2, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp fp, r1 + mov r0, r0, lsr #4 + add r8, r8, #2 + bne .L176 + b .L431 +.L495: + ldrh r5, [sl, #0] + rsb r6, r0, #8 + mov r2, r5, asl #22 + mov r3, r5, lsr #12 + mov r2, r2, lsr #22 + tst r5, #2048 + mov r7, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, lr + tst r5, #1024 + beq .L279 + cmp r6, #0 + ldr r2, [r3, #0] + beq .L281 + mov r3, r0, asl #2 + ldr r5, .L516+12 + mov r0, r2, asl r3 + mov r1, #0 + mov r2, r8 +.L283: + movs r3, r0, lsr #28 + orr r3, r7, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + add r1, r1, #1 + strneh r3, [r2, #0] @ movhi + streqh r3, [r2, #0] @ movhi + cmp r6, r1 + mov r0, r0, asl #4 + add r2, r2, #2 + bne .L283 + add r8, r8, r6, asl #1 +.L281: + add sl, sl, #2 + b .L276 +.L488: + ldrh r2, [sl, #0] + rsb ip, r0, #8 + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + ands r1, r2, #1024 + beq .L103 + cmp r0, #3 + bhi .L508 + subs lr, ip, #4 + ldr r2, [r5, #4] + ldreq r6, .L516+12 + beq .L111 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r6, .L516+12 + mov r0, r2, asl r3 + mov r1, r8 + mov r2, #0 +.L113: + mov r3, r0, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r6] + cmp lr, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, asl #8 + bne .L113 + add r3, r8, ip, asl #1 + sub r8, r3, #8 +.L111: + ldr r3, [r5, #0] + mov ip, lr + and r0, r3, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, r6] + mov r2, r3, lsr #8 + and r2, r2, #255 + strh r0, [r8, #6] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r6] + mov r1, r3, lsr #16 + and r1, r1, #255 + strh r2, [r8, #4] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r6] + mov r3, r3, lsr #24 + strh r1, [r8, #2] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r6] + strh r3, [r8], #8 @ movhi +.L107: + add sl, sl, #2 + b .L100 +.L503: + rsb ip, r0, #8 + cmp fp, ip + bcs .L16 + ldrh r2, [sl, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + ands r4, r2, #1024 + bne .L509 + cmp r0, #3 + bls .L37 + cmp fp, #0 + ldr r2, [ip, #4] + beq .L431 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r1, .L516+12 + mov r0, r2, lsr r3 + mov r2, r4 +.L40: + and r3, r0, #255 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r1] + cmp fp, r2 + strh r3, [r8], #2 @ movhi + mov r0, r0, lsr #8 + bne .L40 + b .L431 +.L233: + ldrh r3, [r5, #0] + strh r3, [r0, #14] @ movhi + strh r3, [r0, #0] @ movhi + strh r3, [r0, #2] @ movhi + strh r3, [r0, #4] @ movhi + strh r3, [r0, #6] @ movhi + strh r3, [r0, #8] @ movhi + strh r3, [r0, #10] @ movhi + strh r3, [r0, #12] @ movhi + b .L232 +.L147: + cmp r5, #3 + bhi .L510 + ldr r1, [ip, #0] + ldr lr, .L516+12 +.L157: + mov r0, #0 +.L158: + and r3, r1, #255 + mov r3, r3, asl #1 + add r0, r0, #1 + ldrh r3, [r3, lr] + cmp r5, r0 + strh r3, [r8], #2 @ movhi + mov r1, r1, lsr #8 + bhi .L158 + b .L431 +.L419: + ldr r2, [r3, #0] + ldr ip, .L516+12 + mov r1, #0 +.L426: + ands r3, r2, #15 + orr r3, r0, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldreqh r3, [ip, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp r5, r1 + mov r2, r2, lsr #4 + add r8, r8, #2 + bne .L426 + b .L431 +.L86: + cmp r4, #3 + bhi .L511 + ldr r1, [ip, #0] + ldr lr, .L516+12 +.L96: + mov r0, #0 +.L97: + and r3, r1, #255 + mov r3, r3, asl #1 + add r0, r0, #1 + ldrh r3, [r3, lr] + cmp r4, r0 + strh r3, [r8], #2 @ movhi + mov r1, r1, lsr #8 + bhi .L97 + b .L431 +.L262: + ldr r2, [r3, #0] + ldr ip, .L516+12 + mov r1, #0 +.L269: + ands r3, r2, #15 + orr r3, r0, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldreqh r3, [ip, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp r4, r1 + mov r2, r2, lsr #4 + add r8, r8, #2 + bne .L269 + b .L431 +.L279: + cmp r6, #0 + ldr r2, [r3, #0] + beq .L281 + mov r3, r0, asl #2 + ldr r5, .L516+12 + mov r0, r2, lsr r3 + mov r1, #0 + mov r2, r8 +.L290: + ands r3, r0, #15 + orr r3, r7, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldreqh r3, [r5, #0] + add r1, r1, #1 + strneh r3, [r2, #0] @ movhi + streqh r3, [r2, #0] @ movhi + cmp r6, r1 + mov r0, r0, lsr #4 + add r2, r2, #2 + bne .L290 + add r8, r8, r6, asl #1 + b .L281 +.L163: + ldrh r1, [sl, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, lr + tst r1, #1024 + bne .L512 + cmp r4, #0 + ldr r2, [r3, #0] + beq .L185 + mov r3, r0, asl #2 + ldr r6, .L516+12 + mov r0, r2, lsr r3 + mov r1, #0 + mov r2, r8 +.L194: + ands r3, r0, #15 + orr r3, r5, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + add r1, r1, #1 + strneh r3, [r2, #0] @ movhi + streqh r3, [r2, #0] @ movhi + cmp r4, r1 + mov r0, r0, lsr #4 + add r2, r2, #2 + bne .L194 +.L484: + add r8, r8, r4, asl #1 +.L185: + rsb fp, r4, fp + add sl, sl, #2 + b .L161 +.L103: + cmp r0, #3 + bhi .L513 + subs lr, ip, #4 + ldr r2, [r5, #0] + ldreq r6, .L516+12 + beq .L120 + mov r3, r0, asl #3 + ldr r6, .L516+12 + mov r0, r2, lsr r3 + mov r2, r1 + mov r1, r8 +.L122: + and r3, r0, #255 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r6] + cmp lr, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, lsr #8 + bne .L122 + add r3, r8, ip, asl #1 + sub r8, r3, #8 +.L120: + ldr r3, [r5, #4] + mov ip, lr + and r0, r3, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, r6] + mov r2, r3, lsr #8 + and r2, r2, #255 + strh r0, [r8, #0] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r6] + mov r1, r3, lsr #16 + and r1, r1, #255 + strh r2, [r8, #2] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r6] + mov r3, r3, lsr #24 + strh r1, [r8, #4] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r6] + add sl, sl, #2 + strh r3, [r8, #6] @ movhi + add r8, r8, #8 + b .L100 +.L16: + ldrh r2, [sl, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add lr, r9, r3, asl #6 + ldrne r3, [sp, #4] + addne lr, lr, r3 + ands r1, r2, #1024 + bne .L514 + cmp r0, #3 + bls .L65 + cmp ip, #0 + ldr r2, [lr, #4] + beq .L57 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr lr, .L516+12 + mov r0, r2, lsr r3 + mov r2, r1 + mov r1, r8 +.L68: + and r3, r0, #255 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, lr] + cmp ip, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, lsr #8 + bne .L68 +.L482: + add r8, r8, ip, asl #1 +.L57: + rsb fp, ip, fp + add sl, sl, #2 + b .L14 +.L510: + ldr r1, [ip, #0] + ldr lr, .L516+12 + and r0, r1, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + mov r3, r1, lsr #8 + and r3, r3, #255 + strh r0, [r8, #0] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r1, lsr #16 + and r2, r2, #255 + strh r3, [r8, #2] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r1, r1, lsr #24 + strh r2, [r8, #4] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + subs r5, r5, #4 + strh r1, [r8, #6] @ movhi + ldr r1, [ip, #4] + addne r8, r8, #8 + bne .L157 + b .L431 +.L493: + ldr r1, [ip, #4] + ldr lr, .L516+12 + and r0, r1, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + mov r3, r1, lsr #8 + and r3, r3, #255 + strh r0, [r8, #6] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r1, lsr #16 + and r2, r2, #255 + strh r3, [r8, #4] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r1, r1, lsr #24 + strh r2, [r8, #2] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + subs r5, r5, #4 + strh r1, [r8, #0] @ movhi + ldr r1, [ip, #0] + addne r8, r8, #8 + bne .L152 + b .L431 +.L506: + ldr r1, [ip, #4] + ldr lr, .L516+12 + and r0, r1, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + mov r3, r1, lsr #8 + and r3, r3, #255 + strh r0, [r8, #6] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r1, lsr #16 + and r2, r2, #255 + strh r3, [r8, #4] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r1, r1, lsr #24 + strh r2, [r8, #2] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + subs r4, r4, #4 + strh r1, [r8, #0] @ movhi + ldr r1, [ip, #0] + addne r8, r8, #8 + bne .L91 + b .L431 +.L511: + ldr r1, [ip, #0] + ldr lr, .L516+12 + and r0, r1, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, lr] + mov r3, r1, lsr #8 + and r3, r3, #255 + strh r0, [r8, #0] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + mov r2, r1, lsr #16 + and r2, r2, #255 + strh r3, [r8, #2] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + mov r1, r1, lsr #24 + strh r2, [r8, #4] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, lr] + subs r4, r4, #4 + strh r1, [r8, #6] @ movhi + ldr r1, [ip, #4] + addne r8, r8, #8 + bne .L96 + b .L431 +.L509: + cmp r0, #3 + bls .L22 + cmp fp, #0 + ldr r2, [ip, #0] + beq .L431 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r1, .L516+12 + mov r0, r2, asl r3 + mov r2, #0 +.L26: + mov r3, r0, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r1] + cmp fp, r2 + strh r3, [r8], #2 @ movhi + mov r0, r0, asl #8 + bne .L26 + b .L431 +.L508: + cmp ip, #0 + ldr r2, [r5, #0] + beq .L107 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr lr, .L516+12 + mov r0, r2, asl r3 + mov r1, r8 + mov r2, #0 +.L109: + mov r3, r0, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, lr] + cmp ip, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, asl #8 + bne .L109 + add r8, r8, ip, asl #1 +.L515: + add sl, sl, #2 + b .L100 +.L507: + cmp fp, #0 + ldr r2, [ip, #0] + beq .L431 + mov r3, r0, asl #2 + mov r0, r2, asl r3 + ldr r2, .L516+12 + mov r1, r5 +.L170: + movs r3, r0, lsr #28 + orr r3, r4, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldreqh r3, [r2, #0] + add r1, r1, #1 + strneh r3, [r8, #0] @ movhi + streqh r3, [r8, #0] @ movhi + cmp fp, r1 + mov r0, r0, asl #4 + add r8, r8, #2 + bne .L170 + b .L431 +.L514: + cmp r0, #3 + bls .L55 + cmp ip, #0 + ldr r2, [lr, #0] + beq .L57 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr lr, .L516+12 + mov r0, r2, asl r3 + mov r1, r8 + mov r2, #0 +.L59: + mov r3, r0, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, lr] + cmp ip, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, asl #8 + bne .L59 + b .L482 +.L513: + cmp ip, #0 + ldr r2, [r5, #4] + beq .L107 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr lr, .L516+12 + mov r0, r2, lsr r3 + mov r2, r1 + mov r1, r8 +.L118: + and r3, r0, #255 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, lr] + cmp ip, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, lsr #8 + bne .L118 + add r8, r8, ip, asl #1 + b .L515 +.L512: + cmp r4, #0 + ldr r2, [r3, #0] + beq .L185 + mov r3, r0, asl #2 + ldr r6, .L516+12 + mov r0, r2, asl r3 + mov r1, #0 + mov r2, r8 +.L187: + movs r3, r0, lsr #28 + orr r3, r5, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldreqh r3, [r6, #0] + add r1, r1, #1 + strneh r3, [r2, #0] @ movhi + streqh r3, [r2, #0] @ movhi + cmp r4, r1 + mov r0, r0, asl #4 + add r2, r2, #2 + bne .L187 + b .L484 +.L65: + subs r4, ip, #4 + ldr r2, [lr, #0] + ldreq r5, .L516+12 + beq .L70 + mov r3, r0, asl #3 + ldr r5, .L516+12 + mov r0, r2, lsr r3 + mov r2, r1 + mov r1, r8 +.L72: + and r3, r0, #255 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r5] + cmp r4, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, lsr #8 + bne .L72 + add r3, r8, ip, asl #1 + sub r8, r3, #8 +.L70: + ldr r3, [lr, #4] + and r0, r3, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, r5] + mov r2, r3, lsr #8 + and r2, r2, #255 + strh r0, [r8, #0] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r1, r3, lsr #16 + and r1, r1, #255 + strh r2, [r8, #2] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r3, r3, lsr #24 + strh r1, [r8, #4] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + strh r3, [r8, #6] @ movhi + add r8, r8, #8 + b .L57 +.L55: + subs r4, ip, #4 + ldr r2, [lr, #4] + ldreq r5, .L516+12 + beq .L61 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r5, .L516+12 + mov r0, r2, asl r3 + mov r1, r8 + mov r2, #0 +.L63: + mov r3, r0, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r5] + cmp r4, r2 + strh r3, [r1], #2 @ movhi + mov r0, r0, asl #8 + bne .L63 + add r3, r8, ip, asl #1 + sub r8, r3, #8 +.L61: + ldr r3, [lr, #0] + and r0, r3, #255 + mov r0, r0, asl #1 + ldrh r0, [r0, r5] + mov r2, r3, lsr #8 + and r2, r2, #255 + strh r0, [r8, #6] @ movhi + mov r2, r2, asl #1 + ldrh r2, [r2, r5] + mov r1, r3, lsr #16 + and r1, r1, #255 + strh r2, [r8, #4] @ movhi + mov r1, r1, asl #1 + ldrh r1, [r1, r5] + mov r3, r3, lsr #24 + strh r1, [r8, #2] @ movhi + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + strh r3, [r8], #8 @ movhi + b .L57 +.L22: + mov r3, r0, asl #3 + ldr r1, [ip, #4] + add r2, fp, r0 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L27 + cmp fp, #0 + ldrne r0, .L516+12 + movne r2, #0 + beq .L431 +.L36: + mov r3, r1, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r0] + cmp fp, r2 + strh r3, [r8], #2 @ movhi + mov r1, r1, asl #8 + bne .L36 + b .L431 +.L37: + add r2, fp, r0 + ldr r3, [ip, #0] + cmp r2, #4 + mov r1, r0, asl #3 + mov r2, r3, lsr r1 + bhi .L41 + cmp fp, #0 + ldrne r0, .L516+12 + movne r1, r4 + beq .L431 +.L50: + and r3, r2, #255 + mov r3, r3, asl #1 + add r1, r1, #1 + ldrh r3, [r3, r0] + cmp fp, r1 + strh r3, [r8], #2 @ movhi + mov r2, r2, lsr #8 + bne .L50 + b .L431 +.L27: + rsbs lr, r0, #4 + beq .L30 + ldr r4, .L516+12 + mov r0, r8 + mov r2, #0 +.L32: + mov r3, r1, lsr #24 + mov r3, r3, asl #1 + add r2, r2, #1 + ldrh r3, [r3, r4] + cmp lr, r2 + strh r3, [r0], #2 @ movhi + mov r1, r1, asl #8 + bne .L32 + add r8, r8, lr, asl #1 +.L30: + subs r0, fp, lr + ldr r2, [ip, #0] + beq .L431 + ldr ip, .L516+12 + mov r1, #0 +.L35: + mov r3, r2, lsr #24 + mov r3, r3, asl #1 + add r1, r1, #1 + ldrh r3, [r3, ip] + cmp r0, r1 + strh r3, [r8], #2 @ movhi + mov r2, r2, asl #8 + bne .L35 + b .L431 +.L41: + rsbs lr, r0, #4 + beq .L44 + ldr r5, .L516+12 + mov r1, r4 + mov r0, r8 +.L46: + and r3, r2, #255 + mov r3, r3, asl #1 + add r1, r1, #1 + ldrh r3, [r3, r5] + cmp lr, r1 + strh r3, [r0], #2 @ movhi + mov r2, r2, lsr #8 + bne .L46 + add r8, r8, lr, asl #1 +.L44: + subs r0, fp, lr + ldr r2, [ip, #4] + beq .L431 + ldr ip, .L516+12 + mov r1, #0 +.L49: + and r3, r2, #255 + mov r3, r3, asl #1 + add r1, r1, #1 + ldrh r3, [r3, ip] + cmp r0, r1 + strh r3, [r8], #2 @ movhi + mov r2, r2, lsr #8 + bne .L49 + b .L431 + .size render_scanline_text_base_normal, .-render_scanline_text_base_normal + .align 2 + .global render_scanline_text_transparent_normal + .type render_scanline_text_transparent_normal, %function +render_scanline_text_transparent_normal: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L1161 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + add r5, ip, r0, asl #2 + ldrh lr, [r5, #18] + ldrh r4, [ip, #6] + add ip, ip, r0, asl #1 + add r4, r4, lr + mov r6, r4, asl #23 + ldrh r7, [ip, #8] + mov r6, r6, lsr #23 + ldrh r0, [r5, #16] + cmp r6, #255 + movls lr, #0 + movhi lr, #1 + mov r5, r7, lsr #14 + rsb r9, r1, r2 + ldr r2, .L1161+4 + ands lr, lr, r5, lsr #1 + mov ip, r7, asl #3 + add lr, r3, r1, asl #1 + ldr r8, .L1161+8 + subne r3, r6, #256 + ldr r2, [r2, r5, asl #2] + movne r3, r3, lsr #3 + moveq r3, r4, asl #3 + add r0, r0, r1 + and ip, ip, #63488 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + add ip, ip, r8 + mov r0, r0, asl #23 + addne r4, ip, r3, asl #6 + addeq r4, ip, r3 + mov r0, r0, lsr #23 + tst r5, #1 + andeq r0, r0, #255 + sub sp, sp, #4 + moveq r3, r0, lsr #3 + addeq ip, r4, r3, asl #1 + streq r4, [sp, #0] + beq .L526 + cmp r0, #255 + subhi r0, r0, #256 + movhi r3, r0, lsr #3 + movls r3, r0, lsr #3 + addhi r3, r4, r3, asl #1 + addls ip, r4, r3, asl #1 + addls r4, r4, #2048 + addhi ip, r3, #2048 + strhi r4, [sp, #0] + strls r4, [sp, #0] +.L526: + tst r7, #128 + beq .L527 + and r1, r0, #255 + and r3, r6, #7 + mov r2, r7, asl #12 + mov r3, r3, asl #3 + and r2, r2, #49152 + rsb sl, r1, #256 + add r2, r2, r3 + cmp r9, sl + mov r3, r3, asl #1 + add r8, r2, r8 + rsb fp, r3, #56 + and r0, r0, #7 + bls .L1136 + cmp r0, #0 + moveq r5, r0 + bne .L1137 +.L729: + rsb r3, r5, sl + movs r7, r3, lsr #3 + beq .L783 + ldr r5, .L1161+12 + mov r0, lr + mov r6, #0 + b .L785 +.L1138: + ldr r2, [r1, #4] + cmp r2, #0 + beq .L790 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #2] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #0] @ movhi +.L790: + ldr r2, [r1, #0] + cmp r2, #0 + beq .L799 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #10] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #8] @ movhi +.L799: + add r6, r6, #1 + cmp r7, r6 + add r0, r0, #16 + beq .L825 +.L1139: + add ip, ip, #2 +.L785: + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r1, r8, r3, asl #6 + addne r1, r1, fp + tst r2, #1024 + bne .L1138 + ldr r2, [r1, #0] + cmp r2, #0 + beq .L808 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #6] @ movhi +.L808: + ldr r2, [r1, #4] + cmp r2, #0 + beq .L799 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + add r6, r6, #1 + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #14] @ movhi + cmp r7, r6 + add r0, r0, #16 + bne .L1139 +.L825: + add lr, lr, r7, asl #4 +.L783: + rsb sl, sl, r9 + movs r4, sl, lsr #3 + ldreq r3, [sp, #0] + beq .L829 + ldr r7, .L1161+12 + ldr r6, [sp, #0] + mov r5, lr + mov r2, #0 + b .L830 +.L1141: + ldr r1, [r0, #4] + cmp r1, #0 + beq .L835 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #2] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #0] @ movhi +.L835: + ldr r1, [r0, #0] + cmp r1, #0 + beq .L844 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #10] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #8] @ movhi +.L844: + add r2, r2, #1 + cmp r4, r2 + add r5, r5, #16 + add r6, r6, #2 + beq .L1140 +.L830: + ldrh r1, [r6, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r8, r3, asl #6 + addne r0, r0, fp + tst r1, #1024 + bne .L1141 + ldr r1, [r0, #0] + cmp r1, #0 + beq .L853 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #4] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #6] @ movhi +.L853: + ldr r1, [r0, #4] + cmp r1, #0 + beq .L844 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + add r2, r2, #1 + strneh r3, [r5, #8] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + add r6, r6, #2 + strneh r3, [r5, #10] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #12] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r5, #14] @ movhi + cmp r4, r2 + add r5, r5, #16 + bne .L830 +.L1140: + ldr r2, [sp, #0] + add lr, lr, r4, asl #4 + add r3, r2, r4, asl #1 +.L829: + ands r5, sl, #7 + beq .L1118 + ldrh r4, [r3, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add ip, r8, r3, asl #6 + addne ip, ip, fp + tst r4, #1024 + beq .L874 + cmp r5, #3 + ldrls r2, [ip, #4] + bls .L888 + ldr r1, [ip, #4] + cmp r1, #0 + beq .L878 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #6] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #4] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #2] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #0] @ movhi +.L878: + subs r5, r5, #4 + ldr r2, [ip, #0] + addne lr, lr, #8 + beq .L1118 +.L888: + mov r1, #0 +.L889: + movs r3, r2, lsr #24 + mov ip, r3, asl #1 + ldrne r3, .L1161+12 + mov r0, r1, asl #1 + ldrneh ip, [ip, r3] + add r1, r1, #1 + strneh ip, [r0, lr] @ movhi + cmp r1, r5 + mov r2, r2, asl #8 + bcc .L889 +.L1118: + add sp, sp, #4 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L527: + and r1, r0, #255 + and r3, r6, #7 + mov r2, r7, asl #12 + mov r3, r3, asl #2 + and r2, r2, #49152 + rsb r4, r1, #256 + add r2, r2, r3 + cmp r9, r4 + mov r3, r3, asl #1 + add r8, r2, r8 + rsb fp, r3, #28 + and r0, r0, #7 + bls .L1142 + cmp r0, #0 + moveq r6, r0 + bne .L1143 +.L1003: + rsb r3, r6, r4 + movs sl, r3, lsr #3 + beq .L1021 + ldr r6, .L1161+12 + mov r0, lr + mov r7, #0 + b .L1023 +.L1144: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1028 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #0] @ movhi +.L1028: + add r7, r7, #1 + cmp sl, r7 + add r0, r0, #16 + beq .L1061 +.L1145: + add ip, ip, #2 +.L1023: + ldrh r1, [ip, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, r8, r2, asl #5 + addne r3, r3, fp + tst r1, #1024 + bne .L1144 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1028 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + add r7, r7, #1 + strneh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #14] @ movhi + cmp sl, r7 + add r0, r0, #16 + bne .L1145 +.L1061: + add lr, lr, sl, asl #4 +.L1021: + rsb sl, r4, r9 + movs r4, sl, lsr #3 + ldreq r2, [sp, #0] + beq .L1065 + ldr r7, .L1161+12 + ldr r6, [sp, #0] + mov r0, lr + mov ip, #0 + b .L1066 +.L1147: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1071 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #0] @ movhi +.L1071: + add ip, ip, #1 + cmp r4, ip + add r0, r0, #16 + add r6, r6, #2 + beq .L1146 +.L1066: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, r8, r2, asl #5 + addne r3, r3, fp + tst r1, #1024 + bne .L1147 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1071 + ands r3, r2, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + add ip, ip, #1 + strneh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + add r6, r6, #2 + strneh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #14] @ movhi + cmp r4, ip + add r0, r0, #16 + bne .L1066 +.L1146: + ldr r3, [sp, #0] + add lr, lr, r4, asl #4 + add r2, r3, r4, asl #1 +.L1065: + ands r5, sl, #7 + beq .L1118 + ldrh r4, [r2, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r3, r8, r3, asl #5 + mov r2, r4, lsr #12 + addne r3, r3, fp + tst r4, #1024 + mov ip, r2, asl #4 + beq .L1108 + ldr r2, [r3, #0] + ldr r4, .L1161+12 + mov r0, #0 +.L1110: + movs r3, r2, lsr #28 + orr r3, ip, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r5, r0 + mov r2, r2, asl #4 + bne .L1110 + b .L1118 +.L1142: + cmp r0, #0 + bne .L1148 +.L912: + movs sl, r9, lsr #3 + beq .L947 + ldr r6, .L1161+12 + mov r0, lr + mov r5, ip + mov r7, #0 + b .L949 +.L1150: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L954 + ands r3, r2, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #0] @ movhi +.L954: + add r7, r7, #1 + cmp sl, r7 + add r0, r0, #16 + add r5, r5, #2 + beq .L1149 +.L949: + ldrh r1, [r5, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r4, r3, asl #4 + add r3, r8, r2, asl #5 + addne r3, r3, fp + tst r1, #1024 + bne .L1150 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L954 + ands r3, r2, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + add r7, r7, #1 + strneh r3, [r0, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + add r5, r5, #2 + strneh r3, [r0, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r4, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #14] @ movhi + cmp sl, r7 + add r0, r0, #16 + bne .L949 +.L1149: + add lr, lr, sl, asl #4 + add ip, ip, sl, asl #1 +.L947: + ands r4, r9, #7 + beq .L1118 + ldrh r1, [ip, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r3, r8, r3, asl #5 + mov r2, r1, lsr #12 + addne r3, r3, fp + tst r1, #1024 + mov ip, r2, asl #4 + beq .L991 + ldr r2, [r3, #0] + ldr r5, .L1161+12 + mov r0, #0 +.L993: + movs r3, r2, lsr #28 + orr r3, ip, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r4, r0 + mov r2, r2, asl #4 + bne .L993 + b .L1118 +.L1136: + cmp r0, #0 + bne .L1151 +.L531: + movs r7, r9, lsr #3 + beq .L645 + ldr r5, .L1161+12 + mov r0, lr + mov r4, ip + mov r6, #0 + b .L647 +.L1153: + ldr r2, [r1, #4] + cmp r2, #0 + beq .L652 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #2] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #0] @ movhi +.L652: + ldr r2, [r1, #0] + cmp r2, #0 + beq .L661 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #10] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #8] @ movhi +.L661: + add r6, r6, #1 + cmp r7, r6 + add r0, r0, #16 + add r4, r4, #2 + beq .L1152 +.L647: + ldrh r2, [r4, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r1, r8, r3, asl #6 + addne r1, r1, fp + tst r2, #1024 + bne .L1153 + ldr r2, [r1, #0] + cmp r2, #0 + beq .L670 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #6] @ movhi +.L670: + ldr r2, [r1, #4] + cmp r2, #0 + beq .L661 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + add r6, r6, #1 + strneh r3, [r0, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + add r4, r4, #2 + strneh r3, [r0, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #14] @ movhi + cmp r7, r6 + add r0, r0, #16 + bne .L647 +.L1152: + add lr, lr, r7, asl #4 + add ip, ip, r7, asl #1 +.L645: + ands r4, r9, #7 + beq .L1118 + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r8, r3, asl #6 + addne ip, ip, fp + tst r2, #1024 + beq .L691 + cmp r4, #3 + ldrls r2, [ip, #4] + bls .L705 + ldr r1, [ip, #4] + cmp r1, #0 + beq .L695 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #6] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #4] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #2] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #0] @ movhi +.L695: + subs r4, r4, #4 + ldr r2, [ip, #0] + addne lr, lr, #8 + beq .L1118 +.L705: + mov r1, #0 +.L706: + movs r3, r2, lsr #24 + mov ip, r3, asl #1 + ldrne r3, .L1161+12 + mov r0, r1, asl #1 + ldrneh ip, [ip, r3] + add r1, r1, #1 + strneh ip, [r0, lr] @ movhi + cmp r4, r1 + mov r2, r2, asl #8 + bhi .L706 + b .L1118 +.L1148: + rsb r4, r0, #8 + cmp r9, r4 + bcs .L914 + ldrh r1, [ip, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add ip, r8, r3, asl #5 + mov r2, r1, lsr #12 + addne ip, ip, fp + tst r1, #1024 + mov r2, r2, asl #4 + bne .L1154 + cmp r9, #0 + ldr ip, [ip, #0] + beq .L1118 + mov r3, r0, asl #2 + ldr r4, .L1161+12 + mov r0, ip, lsr r3 + mov ip, #0 +.L926: + ands r3, r0, #15 + orr r3, r2, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, lr] @ movhi + cmp r9, ip + mov r0, r0, lsr #4 + bne .L926 + b .L1118 +.L1162: + .align 2 +.L1161: + .word io_registers + .word map_widths + .word vram + .word palette_ram_converted +.L1137: + ldrh r2, [ip, #0] + rsb r5, r0, #8 + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r6, r8, r3, asl #6 + addne r6, r6, fp + ands r2, r2, #1024 + beq .L732 + cmp r0, #3 + bhi .L1155 + subs r4, r5, #4 + ldr r2, [r6, #4] + beq .L743 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, asl r3 + ldr r7, .L1161+12 + mov r1, #0 +.L745: + movs r3, r0, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, asl #8 + bne .L745 + add r3, lr, r5, asl #1 + sub lr, r3, #8 +.L743: + ldr r1, [r6, #0] + cmp r1, #0 + beq .L774 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #6] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #4] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #2] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #0] @ movhi +.L774: + add lr, lr, #8 + mov r5, r4 +.L736: + add ip, ip, #2 + b .L729 +.L1143: + ldrh r5, [ip, #0] + rsb r6, r0, #8 + mov r2, r5, asl #22 + mov r3, r5, lsr #12 + mov r2, r2, lsr #22 + tst r5, #2048 + mov r7, r3, asl #4 + add r3, r8, r2, asl #5 + addne r3, r3, fp + tst r5, #1024 + beq .L1006 + cmp r6, #0 + ldr r2, [r3, #0] + beq .L1008 + mov r3, r0, asl #2 + mov r0, r2, asl r3 + ldr r5, .L1161+12 + mov r1, #0 +.L1010: + movs r3, r0, lsr #28 + orr r3, r7, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r6, r1 + mov r0, r0, asl #4 + bne .L1010 + add lr, lr, r6, asl #1 +.L1008: + add ip, ip, #2 + b .L1003 +.L1151: + rsb r4, r0, #8 + cmp r9, r4 + bcs .L533 + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add ip, r8, r3, asl #6 + addne ip, ip, fp + tst r2, #1024 + bne .L1156 + cmp r0, #3 + bls .L566 + cmp r9, #0 + ldr r2, [ip, #4] + beq .L1118 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, lsr r3 + ldr ip, .L1161+12 + mov r1, #0 +.L569: + ands r3, r0, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r9, r1 + mov r0, r0, lsr #8 + bne .L569 + b .L1118 +.L1108: + ldr r2, [r3, #0] + ldr r4, .L1161+12 + mov r0, #0 +.L1114: + ands r3, r2, #15 + orr r3, ip, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r5, r0 + mov r2, r2, lsr #4 + bne .L1114 + b .L1118 +.L874: + cmp r5, #3 + ldrls r2, [ip, #0] + bls .L905 + ldr r1, [ip, #0] + cmp r1, #0 + beq .L895 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #0] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #2] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #4] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #6] @ movhi +.L895: + subs r5, r5, #4 + ldr r2, [ip, #4] + addne lr, lr, #8 + beq .L1118 +.L905: + mov r1, #0 +.L906: + ands r3, r2, #255 + mov ip, r3, asl #1 + ldrne r3, .L1161+12 + mov r0, r1, asl #1 + ldrneh ip, [ip, r3] + add r1, r1, #1 + strneh ip, [r0, lr] @ movhi + cmp r1, r5 + mov r2, r2, lsr #8 + bcc .L906 + b .L1118 +.L991: + ldr r2, [r3, #0] + ldr r5, .L1161+12 + mov r0, #0 +.L997: + ands r3, r2, #15 + orr r3, ip, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r4, r0 + mov r2, r2, lsr #4 + bne .L997 + b .L1118 +.L691: + cmp r4, #3 + ldrls r2, [ip, #0] + bls .L722 + ldr r1, [ip, #0] + cmp r1, #0 + beq .L712 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #0] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #2] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #4] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #6] @ movhi +.L712: + subs r4, r4, #4 + ldr r2, [ip, #4] + addne lr, lr, #8 + beq .L1118 +.L722: + mov r1, #0 +.L723: + ands r3, r2, #255 + mov ip, r3, asl #1 + ldrne r3, .L1161+12 + mov r0, r1, asl #1 + ldrneh ip, [ip, r3] + add r1, r1, #1 + strneh ip, [r0, lr] @ movhi + cmp r4, r1 + mov r2, r2, lsr #8 + bhi .L723 + b .L1118 +.L732: + cmp r0, #3 + bhi .L1157 + subs r4, r5, #4 + ldr r2, [r6, #0] + beq .L767 + mov r3, r0, asl #3 + mov r0, r2, lsr r3 + ldr r7, .L1161+12 + mov r1, #0 +.L769: + ands r3, r0, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, lsr #8 + bne .L769 + add r3, lr, r5, asl #1 + sub lr, r3, #8 +.L767: + ldr r1, [r6, #4] + cmp r1, #0 + beq .L774 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #0] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #2] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #4] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #6] @ movhi + b .L774 +.L1006: + cmp r6, #0 + ldr r2, [r3, #0] + beq .L1008 + mov r3, r0, asl #2 + mov r0, r2, lsr r3 + ldr r5, .L1161+12 + mov r1, #0 +.L1016: + ands r3, r0, #15 + orr r3, r7, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r6, r1 + mov r0, r0, lsr #4 + bne .L1016 + add lr, lr, r6, asl #1 + b .L1008 +.L914: + ldrh r1, [ip, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, r8, r2, asl #5 + addne r3, r3, fp + tst r1, #1024 + bne .L1158 + cmp r4, #0 + ldr r2, [r3, #0] + beq .L934 + mov r3, r0, asl #2 + mov r0, r2, lsr r3 + ldr r6, .L1161+12 + mov r1, #0 +.L942: + ands r3, r0, #15 + orr r3, r5, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, lsr #4 + bne .L942 +.L1133: + add lr, lr, r4, asl #1 +.L934: + rsb r9, r4, r9 + add ip, ip, #2 + b .L912 +.L533: + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r8, r3, asl #6 + addne r5, r5, fp + ands r2, r2, #1024 + bne .L1159 + cmp r0, #3 + bls .L621 + cmp r4, #0 + ldr r1, [r5, #4] + beq .L598 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r5, .L1161+12 + mov r0, r1, lsr r3 + mov r1, r2 +.L624: + ands r3, r0, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, lsr #8 + bne .L624 +.L1120: + add lr, lr, r4, asl #1 +.L598: + rsb r9, r4, r9 + add ip, ip, #2 + b .L531 +.L1155: + cmp r5, #0 + ldr r2, [r6, #0] + beq .L736 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, asl r3 + ldr r4, .L1161+12 + mov r1, #0 +.L738: + movs r3, r0, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r5, r1 + mov r0, r0, asl #8 + bne .L738 + add lr, lr, r5, asl #1 +.L1160: + add ip, ip, #2 + b .L729 +.L1154: + cmp r9, #0 + ldr ip, [ip, #0] + beq .L1118 + mov r3, r0, asl #2 + ldr r4, .L1161+12 + mov r0, ip, asl r3 + mov ip, #0 +.L921: + movs r3, r0, lsr #28 + orr r3, r2, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, lr] @ movhi + cmp r9, ip + mov r0, r0, asl #4 + bne .L921 + b .L1118 +.L1159: + cmp r0, #3 + bls .L596 + cmp r4, #0 + ldr r2, [r5, #0] + beq .L598 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, asl r3 + ldr r5, .L1161+12 + mov r1, #0 +.L600: + movs r3, r0, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, asl #8 + bne .L600 + b .L1120 +.L1157: + cmp r5, #0 + ldr r1, [r6, #4] + beq .L736 + mov r3, r0, asl #3 + sub r3, r3, #32 + ldr r4, .L1161+12 + mov r0, r1, lsr r3 + mov r1, r2 +.L762: + ands r3, r0, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r5, r1 + mov r0, r0, lsr #8 + bne .L762 + add lr, lr, r5, asl #1 + b .L1160 +.L1156: + cmp r0, #3 + bls .L539 + cmp r9, #0 + ldr r2, [ip, #0] + beq .L1118 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, asl r3 + ldr ip, .L1161+12 + mov r1, #0 +.L543: + movs r3, r0, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r9, r1 + mov r0, r0, asl #8 + bne .L543 + b .L1118 +.L1158: + cmp r4, #0 + ldr r2, [r3, #0] + beq .L934 + mov r3, r0, asl #2 + mov r0, r2, asl r3 + ldr r6, .L1161+12 + mov r1, #0 +.L936: + movs r3, r0, lsr #28 + orr r3, r5, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r1 + mov r0, r0, asl #4 + bne .L936 + b .L1133 +.L539: + mov r3, r0, asl #3 + ldr r1, [ip, #4] + add r2, r9, r0 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L547 + cmp r9, #0 + ldrne ip, .L1161+12 + movne r0, #0 + beq .L1118 +.L562: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, lr] @ movhi + cmp r9, r0 + mov r1, r1, asl #8 + bne .L562 + b .L1118 +.L596: + subs r6, r4, #4 + ldr r2, [r5, #4] + beq .L605 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r0, r2, asl r3 + ldr r7, .L1161+12 + mov r1, #0 +.L607: + movs r3, r0, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r6, r1 + mov r0, r0, asl #8 + bne .L607 + add r3, lr, r4, asl #1 + sub lr, r3, #8 +.L605: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L636 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #6] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #4] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #2] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #0] @ movhi +.L636: + add lr, lr, #8 + b .L598 +.L566: + add r2, r9, r0 + ldr r3, [ip, #0] + cmp r2, #4 + mov r1, r0, asl #3 + mov r2, r3, lsr r1 + bhi .L573 + cmp r9, #0 + ldrne ip, .L1161+12 + movne r0, #0 + beq .L1118 +.L588: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r9, r0 + mov r2, r2, lsr #8 + bne .L588 + b .L1118 +.L621: + subs r6, r4, #4 + ldr r2, [r5, #0] + beq .L629 + mov r3, r0, asl #3 + mov r0, r2, lsr r3 + ldr r7, .L1161+12 + mov r1, #0 +.L631: + ands r3, r0, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r2, r1, asl #1 + add r1, r1, #1 + strneh r3, [r2, lr] @ movhi + cmp r6, r1 + mov r0, r0, lsr #8 + bne .L631 + add r3, lr, r4, asl #1 + sub lr, r3, #8 +.L629: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L636 + ands r2, r1, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #8 + strneh r2, [lr, #0] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r3, r1, lsr #16 + strneh r2, [lr, #2] @ movhi + ands r2, r3, #255 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #4] @ movhi + movs r2, r1, lsr #24 + ldrne r3, .L1161+12 + movne r2, r2, asl #1 + ldrneh r2, [r2, r3] + strneh r2, [lr, #6] @ movhi + add lr, lr, #8 + b .L598 +.L547: + rsbs r4, r0, #4 + beq .L550 + ldr r5, .L1161+12 + mov r0, #0 +.L552: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, lr] @ movhi + cmp r4, r0 + mov r1, r1, asl #8 + bne .L552 + add lr, lr, r4, asl #1 +.L550: + subs r4, r9, r4 + ldr r2, [ip, #0] + beq .L1118 + ldr ip, .L1161+12 + mov r0, #0 +.L558: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r4, r0 + mov r2, r2, asl #8 + bne .L558 + b .L1118 +.L573: + rsbs r4, r0, #4 + beq .L576 + ldr r5, .L1161+12 + mov r0, #0 +.L578: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r4, r0 + mov r2, r2, lsr #8 + bne .L578 + add lr, lr, r4, asl #1 +.L576: + subs r4, r9, r4 + ldr r2, [ip, #4] + beq .L1118 + ldr ip, .L1161+12 + mov r0, #0 +.L584: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r4, r0 + mov r2, r2, lsr #8 + bne .L584 + b .L1118 + .size render_scanline_text_transparent_normal, .-render_scanline_text_transparent_normal + .align 2 + .global render_scanline_text_base_color16 + .type render_scanline_text_base_color16, %function +render_scanline_text_base_color16: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L1954 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh r5, [ip, #80] + add r7, r0, #7 + mov r8, r5, asr r0 + mov r7, r5, asr r7 + add r6, ip, r0, asl #2 + ldrh r4, [ip, #6] + ldrh lr, [r6, #18] + add ip, ip, r0, asl #1 + add fp, r4, lr + ldrh r9, [ip, #8] + mov sl, fp, asl #23 + rsb r2, r1, r2 + sub sp, sp, #16 + mov sl, sl, lsr #23 + cmp sl, #255 + movls r4, #0 + movhi r4, #1 + ldrh lr, [r6, #16] + str r2, [sp, #12] + mov r6, r9, lsr #14 + ldr r2, .L1954+4 + ands r4, r4, r6, lsr #1 + and r7, r7, #2 + and r8, r8, #1 + add lr, lr, r1 + orr r8, r8, r7 + mov ip, r9, asl #3 + add r7, r3, r1, asl #1 + ldr r2, [r2, r6, asl #2] + subne r3, sl, #256 + ldr r1, .L1954+8 + movne r3, r3, lsr #3 + moveq r3, fp, asl #3 + and ip, ip, #63488 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + add ip, ip, r1 + mov lr, lr, asl #23 + addne r4, ip, r3, asl #6 + addeq r4, ip, r3 + mov r0, r5, lsr #12 + tst r6, #1 + mov lr, lr, lsr #23 + and r0, r0, #2 + mov r5, r5, asl #26 + andeq lr, lr, #255 + orr r0, r0, r5, lsr #31 + moveq r3, lr, lsr #3 + mov r0, r0, asl #9 + mov r8, r8, asl #9 + addeq fp, r4, r3, asl #1 + streq r4, [sp, #0] + beq .L1171 + cmp lr, #255 + subhi lr, lr, #256 + movhi r3, lr, lsr #3 + movls r3, lr, lsr #3 + addhi r3, r4, r3, asl #1 + addls fp, r4, r3, asl #1 + addls r4, r4, #2048 + addhi fp, r3, #2048 + strhi r4, [sp, #0] + strls r4, [sp, #0] +.L1171: + tst r9, #128 + beq .L1172 + mov r2, r9, asl #12 + and r3, sl, #7 + and r1, lr, #255 + mov r3, r3, asl #3 + and r2, r2, #49152 + ldr r4, [sp, #12] + rsb r9, r1, #256 + add r2, r2, r3 + ldr r1, .L1954+8 + mov r3, r3, asl #1 + rsb r3, r3, #56 + cmp r4, r9 + add r2, r2, r1 + str r3, [sp, #4] + and lr, lr, #7 + bls .L1925 + cmp lr, #0 + moveq r6, lr + bne .L1926 +.L1412: + rsb r3, r6, r9 + movs sl, r3, lsr #3 + beq .L1476 + mov lr, r7 + mov r6, #0 + b .L1478 +.L1927: + ldr r1, [r5, #4] + add r6, r6, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #0] + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + streqh r0, [lr, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + streqh r0, [lr, #8] @ movhi + cmp sl, r6 + add lr, lr, #16 + beq .L1530 +.L1928: + add fp, fp, #2 +.L1478: + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r5, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r1, #1024 + bne .L1927 + ldr r1, [r5, #0] + add r6, r6, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + streqh r0, [lr, #4] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #4] + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + streqh r0, [lr, #6] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp sl, r6 + add lr, lr, #16 + bne .L1928 +.L1530: + add r7, r7, sl, asl #4 +.L1476: + ldr r4, [sp, #12] + rsb r9, r9, r4 + movs r4, r9, lsr #3 + ldreq r3, [sp, #0] + beq .L1534 + ldr r6, [sp, #0] + mov lr, r7 + mov sl, #0 + b .L1535 +.L1930: + ldr r1, [r5, #4] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #0] + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + streqh r0, [lr, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + streqh r0, [lr, #8] @ movhi + cmp r4, sl + add lr, lr, #16 + add r6, r6, #2 + beq .L1929 +.L1535: + ldrh r1, [r6, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r5, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r1, #1024 + bne .L1930 + ldr r1, [r5, #0] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + streqh r0, [lr, #4] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #4] + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + streqh r0, [lr, #6] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp r4, sl + add lr, lr, #16 + add r6, r6, #2 + bne .L1535 +.L1929: + ldr r1, [sp, #0] + add r7, r7, r4, asl #4 + add r3, r1, r4, asl #1 +.L1534: + ands lr, r9, #7 + beq .L1907 + ldrh r4, [r3, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r2, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r2, r2, r3 + tst r4, #1024 + beq .L1591 + cmp lr, #3 + ldrls r2, [r2, #4] + bhi .L1931 +.L1608: + mov r1, #0 +.L1609: + movs r3, r2, lsr #24 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, asl #8 + add r7, r7, #2 + bhi .L1609 +.L1907: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L1172: + and r1, lr, #255 + rsb r4, r1, #256 + and r3, sl, #7 + ldr r1, [sp, #12] + mov r2, r9, asl #12 + mov r3, r3, asl #2 + and r2, r2, #49152 + add r2, r2, r3 + cmp r1, r4 + mov r3, r3, asl #1 + ldr r1, .L1954+8 + rsb r3, r3, #28 + add ip, r2, r1 + str r3, [sp, #8] + and r1, lr, #7 + bls .L1932 + cmp r1, #0 + moveq r6, r1 + bne .L1933 +.L1752: + rsb r3, r6, r4 + movs r9, r3, lsr #3 + beq .L1772 + mov r3, r0, asl #16 + mov r5, r3, lsr #16 + mov lr, r7 + mov sl, #0 + b .L1774 +.L1934: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1805 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi +.L1804: + add sl, sl, #1 + cmp r9, sl + add lr, lr, #16 + beq .L1830 +.L1935: + add fp, fp, #2 +.L1774: + ldrh r1, [fp, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r6, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L1934 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1805 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + add sl, sl, #1 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp r9, sl + add lr, lr, #16 + bne .L1935 +.L1830: + add r7, r7, r9, asl #4 +.L1772: + ldr r3, [sp, #12] + rsb fp, r4, r3 + movs r4, fp, lsr #3 + ldreq r2, [sp, #0] + beq .L1834 + mov r3, r0, asl #16 + ldr sl, [sp, #0] + mov r5, r3, lsr #16 + mov lr, r7 + mov r9, #0 + b .L1835 +.L1937: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1866 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi +.L1865: + add r9, r9, #1 + cmp r4, r9 + add lr, lr, #16 + add sl, sl, #2 + beq .L1936 +.L1835: + ldrh r1, [sl, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r6, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L1937 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1866 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + add r9, r9, #1 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp r4, r9 + add lr, lr, #16 + add sl, sl, #2 + bne .L1835 +.L1936: + ldr r3, [sp, #0] + add r7, r7, r4, asl #4 + add r2, r3, r4, asl #1 +.L1834: + ands lr, fp, #7 + beq .L1907 + ldrh r4, [r2, #0] + tst r4, #2048 + mov r3, r4, asl #22 + ldrne r1, [sp, #8] + mov r3, r3, lsr #22 + add r3, ip, r3, asl #5 + addne r3, r3, r1 + mov r2, r4, lsr #12 + tst r4, #1024 + mov ip, r2, asl #4 + moveq r1, #0 + ldreq r2, [r3, #0] + beq .L1902 + ldr r2, [r3, #0] + mov r1, #0 +.L1897: + movs r3, r2, lsr #28 + orr r3, ip, r3 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, asl #4 + add r7, r7, #2 + bne .L1897 + b .L1907 +.L1932: + cmp r1, #0 + bne .L1938 +.L1637: + ldr r1, [sp, #12] + movs r4, r1, lsr #3 + beq .L1676 + mov r3, r0, asl #16 + mov r5, r3, lsr #16 + mov lr, r7 + mov sl, fp + mov r9, #0 + b .L1678 +.L1940: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1709 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi +.L1708: + add r9, r9, #1 + cmp r4, r9 + add lr, lr, #16 + add sl, sl, #2 + beq .L1939 +.L1678: + ldrh r1, [sl, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r6, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L1940 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L1709 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r2, lsr #4 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r2, lsr #8 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r2, lsr #12 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r2, lsr #16 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r2, lsr #20 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r2, lsr #24 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, r8 + add r9, r9, #1 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp r4, r9 + add lr, lr, #16 + add sl, sl, #2 + bne .L1678 +.L1939: + add r7, r7, r4, asl #4 + add fp, fp, r4, asl #1 +.L1676: + ldr r3, [sp, #12] + ands lr, r3, #7 + beq .L1907 + ldrh r1, [fp, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #8] + mov r3, r3, lsr #22 + add r3, ip, r3, asl #5 + mov r2, r1, lsr #12 + addne r3, r3, r4 + tst r1, #1024 + mov ip, r2, asl #4 + moveq r1, #0 + ldreq r2, [r3, #0] + beq .L1745 + ldr r2, [r3, #0] + mov r1, #0 +.L1740: + movs r3, r2, lsr #28 + orr r3, ip, r3 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, asl #4 + add r7, r7, #2 + bne .L1740 + b .L1907 +.L1925: + cmp lr, #0 + bne .L1941 +.L1176: + ldr r3, [sp, #12] + movs r9, r3, lsr #3 + beq .L1308 + mov lr, r7 + mov r6, fp + mov sl, #0 + b .L1310 +.L1943: + ldr r1, [r5, #4] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + streqh r0, [lr, #2] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #0] + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #14] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #12] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + streqh r0, [lr, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + streqh r0, [lr, #8] @ movhi + cmp r9, sl + add lr, lr, #16 + add r6, r6, #2 + beq .L1942 +.L1310: + ldrh r1, [r6, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add r5, r2, r3, asl #6 + addne r5, r5, r4 + tst r1, #1024 + bne .L1943 + ldr r1, [r5, #0] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #4] @ movhi + streqh r0, [lr, #4] @ movhi + movs r3, r1, lsr #24 + ldr r1, [r5, #4] + orrne r3, r3, r8 + strneh r3, [lr, #6] @ movhi + streqh r0, [lr, #6] @ movhi + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [lr, #8] @ movhi + mov r3, r1, lsr #8 + streqh r0, [lr, #8] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #10] @ movhi + mov r3, r1, lsr #16 + streqh r0, [lr, #10] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [lr, #12] @ movhi + streqh r0, [lr, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [lr, #14] @ movhi + streqh r0, [lr, #14] @ movhi + cmp r9, sl + add lr, lr, #16 + add r6, r6, #2 + bne .L1310 +.L1942: + add r7, r7, r9, asl #4 + add fp, fp, r9, asl #1 +.L1308: + ldr r1, [sp, #12] + ands lr, r1, #7 + beq .L1907 + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r2, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r2, r2, r3 + tst r1, #1024 + beq .L1366 + cmp lr, #3 + ldrls r2, [r2, #4] + bhi .L1944 +.L1383: + mov r1, #0 +.L1384: + movs r3, r2, lsr #24 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, asl #8 + add r7, r7, #2 + bhi .L1384 + b .L1907 +.L1805: + strh r5, [lr, #0] @ movhi + strh r5, [lr, #2] @ movhi + strh r5, [lr, #4] @ movhi + strh r5, [lr, #6] @ movhi + strh r5, [lr, #8] @ movhi + strh r5, [lr, #10] @ movhi + strh r5, [lr, #12] @ movhi + strh r5, [lr, #14] @ movhi + b .L1804 +.L1866: + strh r5, [lr, #0] @ movhi + strh r5, [lr, #2] @ movhi + strh r5, [lr, #4] @ movhi + strh r5, [lr, #6] @ movhi + strh r5, [lr, #8] @ movhi + strh r5, [lr, #10] @ movhi + strh r5, [lr, #12] @ movhi + strh r5, [lr, #14] @ movhi + b .L1865 +.L1902: + ands r3, r2, #15 + orr r3, ip, r3 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, lsr #4 + add r7, r7, #2 + bne .L1902 + b .L1907 +.L1938: + ldr r2, [sp, #12] + rsb r5, r1, #8 + cmp r2, r5 + bcs .L1639 + ldrh lr, [fp, #0] + mov r3, lr, asl #22 + mov r3, r3, lsr #22 + tst lr, #2048 + add ip, ip, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, lr, lsr #12 + addne ip, ip, r3 + tst lr, #1024 + mov r2, r2, asl #4 + bne .L1945 + ldr r4, [sp, #12] + ldr ip, [ip, #0] + cmp r4, #0 + beq .L1907 + mov r3, r1, asl #2 + mov r1, ip, lsr r3 + mov ip, #0 +.L1652: + ands r3, r1, #15 + orr r3, r2, r3 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add ip, ip, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, ip + mov r1, r1, lsr #4 + add r7, r7, #2 + bne .L1652 + b .L1907 +.L1955: + .align 2 +.L1954: + .word io_registers + .word map_widths + .word vram +.L1933: + ldrh r5, [fp, #0] + rsb r6, r1, #8 + mov r2, r5, asl #22 + mov r2, r2, lsr #22 + tst r5, #2048 + mov r3, r5, lsr #12 + mov sl, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r5, #1024 + beq .L1755 + cmp r6, #0 + ldr r2, [r3, #0] + beq .L1757 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov lr, #0 + mov r2, r7 +.L1759: + movs r3, r1, lsr #28 + orr r3, sl, r3 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r2, #0] @ movhi + streqh r0, [r2, #0] @ movhi + cmp r6, lr + mov r1, r1, asl #4 + add r2, r2, #2 + bne .L1759 + add r7, r7, r6, asl #1 +.L1757: + add fp, fp, #2 + b .L1752 +.L1926: + ldrh r1, [fp, #0] + rsb r6, lr, #8 + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add sl, r2, r3, asl #6 + addne sl, sl, r4 + ands r5, r1, #1024 + beq .L1415 + cmp lr, #3 + bhi .L1946 + subs ip, r6, #4 + ldr r1, [sl, #4] + beq .L1427 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L1429: + movs r3, r1, lsr #24 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp ip, r5 + mov r1, r1, asl #8 + add lr, lr, #2 + bne .L1429 + add r3, r7, r6, asl #1 + sub r7, r3, #8 +.L1427: + ldr r1, [sl, #0] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + streqh r0, [r7, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi +.L1475: + add r7, r7, #8 + mov r6, ip +.L1419: + add fp, fp, #2 + b .L1412 +.L1941: + ldr r3, [sp, #12] + rsb r4, lr, #8 + cmp r3, r4 + bcs .L1178 + ldrh r1, [fp, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add ip, r2, r3, asl #6 + addne ip, ip, r4 + tst r1, #1024 + bne .L1947 + cmp lr, #3 + bls .L1215 + ldr r4, [sp, #12] + ldr r2, [ip, #4] + cmp r4, #0 + beq .L1907 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L1218: + ands r3, r1, #255 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add r2, r2, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, r2 + mov r1, r1, lsr #8 + add r7, r7, #2 + bne .L1218 + b .L1907 +.L1709: + strh r5, [lr, #0] @ movhi + strh r5, [lr, #2] @ movhi + strh r5, [lr, #4] @ movhi + strh r5, [lr, #6] @ movhi + strh r5, [lr, #8] @ movhi + strh r5, [lr, #10] @ movhi + strh r5, [lr, #12] @ movhi + strh r5, [lr, #14] @ movhi + b .L1708 +.L1745: + ands r3, r2, #15 + orr r3, ip, r3 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, lsr #4 + add r7, r7, #2 + bne .L1745 + b .L1907 +.L1591: + cmp lr, #3 + ldrls r2, [r2, #0] + bhi .L1948 +.L1629: + mov r1, #0 +.L1630: + ands r3, r2, #255 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #2 + bhi .L1630 + b .L1907 +.L1366: + cmp lr, #3 + ldrls r2, [r2, #0] + bhi .L1949 +.L1404: + mov r1, #0 +.L1405: + ands r3, r2, #255 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #2 + bhi .L1405 + b .L1907 +.L1755: + cmp r6, #0 + ldr r2, [r3, #0] + beq .L1757 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov lr, #0 + mov r2, r7 +.L1766: + ands r3, r1, #15 + orr r3, sl, r3 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r2, #0] @ movhi + streqh r0, [r2, #0] @ movhi + cmp r6, lr + mov r1, r1, lsr #4 + add r2, r2, #2 + bne .L1766 + add r7, r7, r6, asl #1 + b .L1757 +.L1639: + ldrh lr, [fp, #0] + mov r2, lr, asl #22 + mov r2, r2, lsr #22 + tst lr, #2048 + mov r3, lr, lsr #12 + mov r4, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst lr, #1024 + bne .L1950 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L1661 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov lr, #0 + mov r2, r7 +.L1670: + ands r3, r1, #15 + orr r3, r4, r3 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r2, #0] @ movhi + streqh r0, [r2, #0] @ movhi + cmp r5, lr + mov r1, r1, lsr #4 + add r2, r2, #2 + bne .L1670 +.L1922: + add r7, r7, r5, asl #1 +.L1661: + ldr r3, [sp, #12] + add fp, fp, #2 + rsb r3, r5, r3 + str r3, [sp, #12] + b .L1637 +.L1415: + cmp lr, #3 + bhi .L1951 + subs ip, r6, #4 + ldr r1, [sl, #0] + beq .L1456 + mov r3, lr, asl #3 + mov r1, r1, lsr r3 + mov lr, r7 + mov r5, #0 +.L1458: + ands r3, r1, #255 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp ip, r5 + mov r1, r1, lsr #8 + add lr, lr, #2 + bne .L1458 + add r3, r7, r6, asl #1 + sub r7, r3, #8 +.L1456: + ldr r1, [sl, #4] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + streqh r0, [r7, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + streqh r0, [r7, #6] @ movhi + b .L1475 +.L1178: + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add ip, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + ands r5, r1, #1024 + bne .L1952 + cmp lr, #3 + bls .L1279 + cmp r4, #0 + ldr r1, [ip, #4] + beq .L1251 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov ip, r5 + mov lr, r7 +.L1282: + ands r3, r1, #255 + orr r3, r3, r8 + add ip, ip, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r4, ip + mov r1, r1, lsr #8 + add lr, lr, #2 + bne .L1282 +.L1909: + add r7, r7, r4, asl #1 +.L1251: + ldr r1, [sp, #12] + add fp, fp, #2 + rsb r1, r4, r1 + str r1, [sp, #12] + b .L1176 +.L1948: + ldmia r2, {r1, r2} @ phole ldm + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + streqh r0, [r7, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + streqh r0, [r7, #6] @ movhi + subs lr, lr, #4 + addne r7, r7, #8 + bne .L1629 + b .L1907 +.L1931: + ldr r1, [r2, #4] + ldr r2, [r2, #0] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + streqh r0, [r7, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + subs lr, lr, #4 + addne r7, r7, #8 + bne .L1608 + b .L1907 +.L1944: + ldr r1, [r2, #4] + ldr r2, [r2, #0] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + streqh r0, [r7, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + subs lr, lr, #4 + addne r7, r7, #8 + bne .L1383 + b .L1907 +.L1949: + ldmia r2, {r1, r2} @ phole ldm + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + streqh r0, [r7, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + streqh r0, [r7, #6] @ movhi + subs lr, lr, #4 + addne r7, r7, #8 + bne .L1404 + b .L1907 +.L1946: + cmp r6, #0 + ldr r1, [sl, #0] + beq .L1419 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L1421: + movs r3, r1, lsr #24 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r6, r5 + mov r1, r1, asl #8 + add lr, lr, #2 + bne .L1421 + add r7, r7, r6, asl #1 +.L1953: + add fp, fp, #2 + b .L1412 +.L1945: + ldr r4, [sp, #12] + ldr ip, [ip, #0] + cmp r4, #0 + beq .L1907 + mov r3, r1, asl #2 + mov r1, ip, asl r3 + mov ip, #0 +.L1646: + movs r3, r1, lsr #28 + orr r3, r2, r3 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add ip, ip, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, ip + mov r1, r1, asl #4 + add r7, r7, #2 + bne .L1646 + b .L1907 +.L1952: + cmp lr, #3 + bls .L1249 + cmp r4, #0 + ldr r1, [ip, #0] + beq .L1251 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L1253: + movs r3, r1, lsr #24 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r4, r5 + mov r1, r1, asl #8 + add lr, lr, #2 + bne .L1253 + b .L1909 +.L1950: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L1661 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov lr, #0 + mov r2, r7 +.L1663: + movs r3, r1, lsr #28 + orr r3, r4, r3 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r2, #0] @ movhi + streqh r0, [r2, #0] @ movhi + cmp r5, lr + mov r1, r1, asl #4 + add r2, r2, #2 + bne .L1663 + b .L1922 +.L1947: + cmp lr, #3 + bls .L1184 + ldr r1, [sp, #12] + ldr r2, [ip, #0] + cmp r1, #0 + beq .L1907 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r2, #0 +.L1188: + movs r3, r1, lsr #24 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add r2, r2, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, r2 + mov r1, r1, asl #8 + add r7, r7, #2 + bne .L1188 + b .L1907 +.L1951: + cmp r6, #0 + ldr r1, [sl, #4] + beq .L1419 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov lr, r7 +.L1450: + ands r3, r1, #255 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r6, r5 + mov r1, r1, lsr #8 + add lr, lr, #2 + bne .L1450 + add r7, r7, r6, asl #1 + b .L1953 +.L1184: + ldr r4, [sp, #12] + mov r3, lr, asl #3 + ldr r1, [ip, #4] + add r2, r4, lr + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L1193 + cmp r4, #0 + movne r2, #0 + beq .L1907 +.L1210: + movs r3, r1, lsr #24 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add r2, r2, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, r2 + mov r1, r1, asl #8 + add r7, r7, #2 + bne .L1210 + b .L1907 +.L1249: + subs r6, r4, #4 + ldr r1, [ip, #4] + beq .L1259 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L1261: + movs r3, r1, lsr #24 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r6, r5 + mov r1, r1, asl #8 + add lr, lr, #2 + bne .L1261 + add r3, r7, r4, asl #1 + sub r7, r3, #8 +.L1259: + ldr r1, [ip, #0] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #6] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #4] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + streqh r0, [r7, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi +.L1307: + add r7, r7, #8 + b .L1251 +.L1215: + ldr r4, [sp, #12] + ldr r3, [ip, #0] + add r2, r4, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov r2, r3, lsr r1 + bhi .L1223 + cmp r4, #0 + movne r1, #0 + beq .L1907 +.L1240: + ands r3, r2, #255 + orr r3, r3, r8 + strneh r3, [r7, #0] @ movhi + ldr r3, [sp, #12] + add r1, r1, #1 + streqh r0, [r7, #0] @ movhi + cmp r3, r1 + mov r2, r2, lsr #8 + add r7, r7, #2 + bne .L1240 + b .L1907 +.L1279: + subs r6, r4, #4 + ldr r1, [ip, #0] + beq .L1288 + mov r3, lr, asl #3 + mov r1, r1, lsr r3 + mov lr, r7 + mov r5, #0 +.L1290: + ands r3, r1, #255 + orr r3, r3, r8 + add r5, r5, #1 + strneh r3, [lr, #0] @ movhi + streqh r0, [lr, #0] @ movhi + cmp r6, r5 + mov r1, r1, lsr #8 + add lr, lr, #2 + bne .L1290 + add r3, r7, r4, asl #1 + sub r7, r3, #8 +.L1288: + ldr r1, [ip, #4] + ands r3, r1, #255 + orrne r3, r3, r8 + strneh r3, [r7, #0] @ movhi + mov r3, r1, lsr #8 + streqh r0, [r7, #0] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #2] @ movhi + mov r3, r1, lsr #16 + streqh r0, [r7, #2] @ movhi + ands r3, r3, #255 + orrne r3, r3, r8 + strneh r3, [r7, #4] @ movhi + streqh r0, [r7, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, r8 + strneh r3, [r7, #6] @ movhi + bne .L1307 + strh r0, [r7, #6] @ movhi + add r7, r7, #8 + b .L1251 +.L1193: + rsbs r4, lr, #4 + beq .L1196 + mov r2, r7 + mov lr, #0 +.L1198: + movs r3, r1, lsr #24 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r2, #0] @ movhi + streqh r0, [r2, #0] @ movhi + cmp r4, lr + mov r1, r1, asl #8 + add r2, r2, #2 + bne .L1198 + add r7, r7, r4, asl #1 +.L1196: + ldr r1, [sp, #12] + ldr r2, [ip, #0] + subs lr, r1, r4 + beq .L1907 + mov r1, #0 +.L1205: + movs r3, r2, lsr #24 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, asl #8 + add r7, r7, #2 + bne .L1205 + b .L1907 +.L1223: + rsbs r4, lr, #4 + beq .L1226 + mov r1, r7 + mov lr, #0 +.L1228: + ands r3, r2, #255 + orr r3, r3, r8 + add lr, lr, #1 + strneh r3, [r1, #0] @ movhi + streqh r0, [r1, #0] @ movhi + cmp r4, lr + mov r2, r2, lsr #8 + add r1, r1, #2 + bne .L1228 + add r7, r7, r4, asl #1 +.L1226: + ldr r1, [sp, #12] + ldr r2, [ip, #4] + subs lr, r1, r4 + beq .L1907 + mov r1, #0 +.L1235: + ands r3, r2, #255 + orr r3, r3, r8 + add r1, r1, #1 + strneh r3, [r7, #0] @ movhi + streqh r0, [r7, #0] @ movhi + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #2 + bne .L1235 + b .L1907 + .size render_scanline_text_base_color16, .-render_scanline_text_base_color16 + .align 2 + .global render_scanline_text_transparent_color16 + .type render_scanline_text_transparent_color16, %function +render_scanline_text_transparent_color16: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L2599 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh lr, [ip, #80] + add r6, r0, #7 + mov r6, lr, asr r6 + mov lr, lr, asr r0 + add r7, ip, r0, asl #2 + ldrh r5, [ip, #6] + ldrh r4, [r7, #18] + add ip, ip, r0, asl #1 + add sl, r5, r4 + ldrh r8, [ip, #8] + mov r5, sl, asl #23 + sub sp, sp, #8 + mov r5, r5, lsr #23 + rsb r2, r1, r2 + ldrh r4, [r7, #16] + cmp r5, #255 + movls ip, #0 + movhi ip, #1 + mov r7, r8, lsr #14 + str r2, [sp, #4] + ldr r2, .L2599+4 + ands ip, ip, r7, lsr #1 + add fp, r3, r1, asl #1 + ldr r2, [r2, r7, asl #2] + subne r3, r5, #256 + mov r0, r8, asl #3 + ldr r9, .L2599+8 + movne r3, r3, lsr #3 + moveq r3, sl, asl #3 + add r4, r4, r1 + and r0, r0, #63488 + add r0, r0, r9 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + mov r4, r4, asl #23 + addne r0, r0, r3, asl #6 + addeq r0, r0, r3 + mov r4, r4, lsr #23 + tst r7, #1 + and lr, lr, #1 + and r6, r6, #2 + andeq r4, r4, #255 + orr lr, lr, r6 + moveq r3, r4, lsr #3 + mov lr, lr, asl #9 + addeq r7, r0, r3, asl #1 + streq r0, [sp, #0] + beq .L1964 + cmp r4, #255 + subhi r4, r4, #256 + movhi r3, r4, lsr #3 + movls r3, r4, lsr #3 + addhi r3, r0, r3, asl #1 + addls r7, r0, r3, asl #1 + addls r0, r0, #2048 + addhi r7, r3, #2048 + strhi r0, [sp, #0] + strls r0, [sp, #0] +.L1964: + tst r8, #128 + beq .L1965 + and r1, r4, #255 + rsb r0, r1, #256 + and r3, r5, #7 + mov r2, r8, asl #12 + ldr r1, [sp, #4] + mov r3, r3, asl #3 + and r2, r2, #49152 + add r2, r2, r3 + cmp r1, r0 + mov r3, r3, asl #1 + add r2, r2, r9 + rsb ip, r3, #56 + and r4, r4, #7 + bls .L2574 + cmp r4, #0 + moveq r8, r4 + bne .L2575 +.L2167: + rsb r3, r8, r0 + movs sl, r3, lsr #3 + beq .L2221 + mov r6, fp + mov r8, #0 + b .L2223 +.L2576: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2228 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #0] @ movhi +.L2228: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2237 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #8] @ movhi +.L2237: + add r8, r8, #1 + cmp sl, r8 + add r6, r6, #16 + beq .L2263 +.L2577: + add r7, r7, #2 +.L2223: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, ip + tst r1, #1024 + bne .L2576 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2246 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #6] @ movhi +.L2246: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2237 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #8] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #10] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r6, #14] @ movhi + cmp sl, r8 + add r6, r6, #16 + bne .L2577 +.L2263: + add fp, fp, sl, asl #4 +.L2221: + ldr r3, [sp, #4] + rsb sl, r0, r3 + movs r0, sl, lsr #3 + ldreq r0, [sp, #0] + beq .L2267 + ldr r7, [sp, #0] + mov r6, fp + mov r8, #0 + b .L2268 +.L2579: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2273 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #0] @ movhi +.L2273: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2282 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #8] @ movhi +.L2282: + add r8, r8, #1 + cmp r0, r8 + add r6, r6, #16 + add r7, r7, #2 + beq .L2578 +.L2268: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, ip + tst r1, #1024 + bne .L2579 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2291 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r6, #6] @ movhi +.L2291: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2282 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r6, #8] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #10] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r6, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r6, #14] @ movhi + cmp r0, r8 + add r6, r6, #16 + add r7, r7, #2 + bne .L2268 +.L2578: + ldr r1, [sp, #0] + add fp, fp, r0, asl #4 + add r0, r1, r0, asl #1 +.L2267: + ands r4, sl, #7 + beq .L2556 + ldrh r0, [r0, #0] + mov r3, r0, asl #22 + mov r3, r3, lsr #22 + tst r0, #2048 + add r2, r2, r3, asl #6 + addne r2, r2, ip + tst r0, #1024 + beq .L2312 + cmp r4, #3 + ldrls r0, [r2, #4] + bls .L2326 + ldr r1, [r2, #4] + cmp r1, #0 + beq .L2316 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi +.L2316: + subs r4, r4, #4 + ldr r0, [r2, #0] + addne fp, fp, #8 + beq .L2556 +.L2326: + mov r1, #0 +.L2327: + movs r3, r0, lsr #24 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp r1, r4 + mov r0, r0, asl #8 + bcc .L2327 +.L2556: + add sp, sp, #8 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L1965: + and r1, r4, #255 + ldr ip, [sp, #4] + and r3, r5, #7 + mov r2, r8, asl #12 + mov r3, r3, asl #2 + rsb r0, r1, #256 + and r2, r2, #49152 + add r2, r2, r3 + cmp ip, r0 + mov r3, r3, asl #1 + add sl, r2, r9 + rsb ip, r3, #28 + and r1, r4, #7 + bls .L2580 + cmp r1, #0 + moveq r8, r1 + bne .L2581 +.L2441: + rsb r3, r8, r0 + movs r9, r3, lsr #3 + beq .L2459 + mov r4, fp + mov r8, #0 + b .L2461 +.L2582: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2466 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi +.L2466: + add r8, r8, #1 + cmp r9, r8 + add r4, r4, #16 + beq .L2499 +.L2583: + add r7, r7, #2 +.L2461: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r6, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, ip + tst r1, #1024 + bne .L2582 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2466 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r4, #14] @ movhi + cmp r9, r8 + add r4, r4, #16 + bne .L2583 +.L2499: + add fp, fp, r9, asl #4 +.L2459: + ldr r1, [sp, #4] + rsb r9, r0, r1 + movs r0, r9, lsr #3 + ldreq r0, [sp, #0] + beq .L2503 + ldr r7, [sp, #0] + mov r4, fp + mov r8, #0 + b .L2504 +.L2585: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2509 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi +.L2509: + add r8, r8, #1 + cmp r0, r8 + add r4, r4, #16 + add r7, r7, #2 + beq .L2584 +.L2504: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r6, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, ip + tst r1, #1024 + bne .L2585 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2509 + ands r3, r2, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r6, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r6, r3 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r4, #14] @ movhi + cmp r0, r8 + add r4, r4, #16 + add r7, r7, #2 + bne .L2504 +.L2584: + ldr r3, [sp, #0] + add fp, fp, r0, asl #4 + add r0, r3, r0, asl #1 +.L2503: + ands r4, r9, #7 + beq .L2556 + ldrh r0, [r0, #0] + mov r3, r0, asl #22 + mov r3, r3, lsr #22 + tst r0, #2048 + add r3, sl, r3, asl #5 + addne r3, r3, ip + mov r2, r0, lsr #12 + tst r0, #1024 + mov r2, r2, asl #4 + ldreq r0, [r3, #0] + moveq ip, #0 + beq .L2552 + ldr r0, [r3, #0] + mov ip, #0 +.L2548: + movs r3, r0, lsr #28 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r1, fp] @ movhi + cmp r4, ip + mov r0, r0, asl #4 + bne .L2548 + b .L2556 +.L2580: + cmp r1, #0 + bne .L2586 +.L2350: + ldr r1, [sp, #4] + movs r0, r1, lsr #3 + beq .L2385 + mov r4, fp + mov r6, r7 + mov r8, #0 + b .L2387 +.L2588: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2392 + ands r3, r2, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #14] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi +.L2392: + add r8, r8, #1 + cmp r0, r8 + add r4, r4, #16 + add r6, r6, #2 + beq .L2587 +.L2387: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, ip + tst r1, #1024 + bne .L2588 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L2392 + ands r3, r2, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r5, r3 + orrne r3, r3, lr + strneh r3, [r4, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r5, r3 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r4, #14] @ movhi + cmp r0, r8 + add r4, r4, #16 + add r6, r6, #2 + bne .L2387 +.L2587: + add fp, fp, r0, asl #4 + add r7, r7, r0, asl #1 +.L2385: + ldr r3, [sp, #4] + ands r4, r3, #7 + beq .L2556 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, sl, r3, asl #5 + addne r0, r0, ip + mov r2, r1, lsr #12 + tst r1, #1024 + mov r2, r2, asl #4 + ldreq r0, [r0, #0] + moveq ip, #0 + beq .L2435 + ldr r0, [r0, #0] + mov ip, #0 +.L2431: + movs r3, r0, lsr #28 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r1, fp] @ movhi + cmp r4, ip + mov r0, r0, asl #4 + bne .L2431 + b .L2556 +.L2574: + cmp r4, #0 + bne .L2589 +.L1969: + ldr r3, [sp, #4] + movs sl, r3, lsr #3 + beq .L2083 + mov r5, fp + mov r6, r7 + mov r8, #0 + b .L2085 +.L2591: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2090 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r5, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r5, #0] @ movhi +.L2090: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2099 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r5, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #10] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r5, #8] @ movhi +.L2099: + add r8, r8, #1 + cmp sl, r8 + add r5, r5, #16 + add r6, r6, #2 + beq .L2590 +.L2085: + ldrh r1, [r6, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, ip + tst r1, #1024 + bne .L2591 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L2108 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r5, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [r5, #6] @ movhi +.L2108: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L2099 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [r5, #8] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #10] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [r5, #12] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + add r8, r8, #1 + strneh r3, [r5, #14] @ movhi + cmp sl, r8 + add r5, r5, #16 + add r6, r6, #2 + bne .L2085 +.L2590: + add fp, fp, sl, asl #4 + add r7, r7, sl, asl #1 +.L2083: + ldr r1, [sp, #4] + ands r4, r1, #7 + beq .L2556 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r2, r3, asl #6 + addne r0, r0, ip + tst r1, #1024 + beq .L2129 + cmp r4, #3 + ldrls r0, [r0, #4] + bls .L2143 + ldr r1, [r0, #4] + cmp r1, #0 + beq .L2133 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi +.L2133: + subs r4, r4, #4 + ldr r0, [r0, #0] + addne fp, fp, #8 + beq .L2556 +.L2143: + mov r1, #0 +.L2144: + movs r3, r0, lsr #24 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp r4, r1 + mov r0, r0, asl #8 + bhi .L2144 + b .L2556 +.L2552: + ands r3, r0, #15 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r1, fp] @ movhi + cmp r4, ip + mov r0, r0, lsr #4 + bne .L2552 + b .L2556 +.L2586: + ldr r3, [sp, #4] + rsb r5, r1, #8 + cmp r3, r5 + bcs .L2352 + ldrh r4, [r7, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r0, sl, r3, asl #5 + mov r2, r4, lsr #12 + addne r0, r0, ip + tst r4, #1024 + mov r2, r2, asl #4 + bne .L2592 + ldr r3, [sp, #4] + ldr r0, [r0, #0] + cmp r3, #0 + beq .L2556 + mov r3, r1, asl #2 + mov r0, r0, lsr r3 + mov ip, #0 +.L2364: + ands r3, r0, #15 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + strneh r3, [r1, fp] @ movhi + ldr r1, [sp, #4] + add ip, ip, #1 + cmp r1, ip + mov r0, r0, lsr #4 + bne .L2364 + b .L2556 +.L2581: + ldrh r6, [r7, #0] + rsb r8, r1, #8 + mov r2, r6, asl #22 + mov r3, r6, lsr #12 + mov r2, r2, lsr #22 + tst r6, #2048 + mov r9, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, ip + tst r6, #1024 + beq .L2444 + cmp r8, #0 + ldr r2, [r3, #0] + beq .L2446 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov r4, #0 +.L2448: + movs r3, r1, lsr #28 + orr r3, r9, r3 + mov r2, r4, asl #1 + orr r3, r3, lr + add r4, r4, #1 + strneh r3, [r2, fp] @ movhi + cmp r8, r4 + mov r1, r1, asl #4 + bne .L2448 + add fp, fp, r8, asl #1 +.L2446: + add r7, r7, #2 + b .L2441 +.L2575: + ldrh r1, [r7, #0] + rsb r8, r4, #8 + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add sl, r2, r3, asl #6 + addne sl, sl, ip + ands r6, r1, #1024 + beq .L2170 + cmp r4, #3 + bhi .L2593 + subs r5, r8, #4 + ldr r1, [sl, #4] + beq .L2181 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r6, #0 +.L2183: + movs r3, r1, lsr #24 + mov r4, r6, asl #1 + orr r3, r3, lr + add r6, r6, #1 + strneh r3, [r4, fp] @ movhi + cmp r5, r6 + mov r1, r1, asl #8 + bne .L2183 + add r3, fp, r8, asl #1 + sub fp, r3, #8 +.L2181: + ldr r1, [sl, #0] + cmp r1, #0 + beq .L2212 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi +.L2212: + add fp, fp, #8 + mov r8, r5 +.L2174: + add r7, r7, #2 + b .L2167 +.L2589: + rsb r0, r4, #8 + cmp r1, r0 + bcs .L1971 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r2, r3, asl #6 + addne r0, r0, ip + tst r1, #1024 + bne .L2594 + cmp r4, #3 + bls .L2004 + ldr ip, [sp, #4] + ldr r0, [r0, #4] + cmp ip, #0 + beq .L2556 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, lsr r3 + mov r1, #0 +.L2007: + ands r3, r0, #255 + orr r3, r3, lr + mov r2, r1, asl #1 + strneh r3, [r2, fp] @ movhi + ldr r3, [sp, #4] + add r1, r1, #1 + cmp r3, r1 + mov r0, r0, lsr #8 + bne .L2007 + b .L2556 +.L2600: + .align 2 +.L2599: + .word io_registers + .word map_widths + .word vram +.L2435: + ands r3, r0, #15 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r1, fp] @ movhi + cmp r4, ip + mov r0, r0, lsr #4 + bne .L2435 + b .L2556 +.L2312: + cmp r4, #3 + ldrls r0, [r2, #0] + bls .L2343 + ldr r1, [r2, #0] + cmp r1, #0 + beq .L2333 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi +.L2333: + subs r4, r4, #4 + ldr r0, [r2, #4] + addne fp, fp, #8 + beq .L2556 +.L2343: + mov r1, #0 +.L2344: + ands r3, r0, #255 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp r1, r4 + mov r0, r0, lsr #8 + bcc .L2344 + b .L2556 +.L2129: + cmp r4, #3 + ldrls r0, [r0, #0] + bls .L2160 + ldr r1, [r0, #0] + cmp r1, #0 + beq .L2150 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi +.L2150: + subs r4, r4, #4 + ldr r0, [r0, #4] + addne fp, fp, #8 + beq .L2556 +.L2160: + mov r1, #0 +.L2161: + ands r3, r0, #255 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp r4, r1 + mov r0, r0, lsr #8 + bhi .L2161 + b .L2556 +.L2352: + ldrh r4, [r7, #0] + mov r2, r4, asl #22 + mov r3, r4, lsr #12 + mov r2, r2, lsr #22 + tst r4, #2048 + mov r0, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, ip + tst r4, #1024 + bne .L2595 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L2372 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov r4, #0 +.L2380: + ands r3, r1, #15 + orr r3, r0, r3 + mov r2, r4, asl #1 + orr r3, r3, lr + add r4, r4, #1 + strneh r3, [r2, fp] @ movhi + cmp r5, r4 + mov r1, r1, lsr #4 + bne .L2380 +.L2571: + add fp, fp, r5, asl #1 +.L2372: + ldr r3, [sp, #4] + add r7, r7, #2 + rsb r3, r5, r3 + str r3, [sp, #4] + b .L2350 +.L2444: + cmp r8, #0 + ldr r2, [r3, #0] + beq .L2446 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov r4, #0 +.L2454: + ands r3, r1, #15 + orr r3, r9, r3 + mov r2, r4, asl #1 + orr r3, r3, lr + add r4, r4, #1 + strneh r3, [r2, fp] @ movhi + cmp r8, r4 + mov r1, r1, lsr #4 + bne .L2454 + add fp, fp, r8, asl #1 + b .L2446 +.L2170: + cmp r4, #3 + bhi .L2596 + subs r5, r8, #4 + ldr r1, [sl, #0] + beq .L2205 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov r6, #0 +.L2207: + ands r3, r1, #255 + mov r4, r6, asl #1 + orr r3, r3, lr + add r6, r6, #1 + strneh r3, [r4, fp] @ movhi + cmp r5, r6 + mov r1, r1, lsr #8 + bne .L2207 + add r3, fp, r8, asl #1 + sub fp, r3, #8 +.L2205: + ldr r1, [sl, #4] + cmp r1, #0 + beq .L2212 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + b .L2212 +.L1971: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r6, r2, r3, asl #6 + addne r6, r6, ip + ands r5, r1, #1024 + bne .L2597 + cmp r4, #3 + bls .L2059 + cmp r0, #0 + ldr r1, [r6, #4] + beq .L2036 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 +.L2062: + ands r3, r1, #255 + mov r4, r5, asl #1 + orr r3, r3, lr + add r5, r5, #1 + strneh r3, [r4, fp] @ movhi + cmp r0, r5 + mov r1, r1, lsr #8 + bne .L2062 +.L2558: + add fp, fp, r0, asl #1 +.L2036: + ldr r1, [sp, #4] + add r7, r7, #2 + rsb r1, r0, r1 + str r1, [sp, #4] + b .L1969 +.L2593: + cmp r8, #0 + ldr r1, [sl, #0] + beq .L2174 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r6, #0 +.L2176: + movs r3, r1, lsr #24 + mov r4, r6, asl #1 + orr r3, r3, lr + add r6, r6, #1 + strneh r3, [r4, fp] @ movhi + cmp r8, r6 + mov r1, r1, asl #8 + bne .L2176 + add fp, fp, r8, asl #1 +.L2598: + add r7, r7, #2 + b .L2167 +.L2592: + ldr ip, [sp, #4] + ldr r0, [r0, #0] + cmp ip, #0 + beq .L2556 + mov r3, r1, asl #2 + mov r0, r0, asl r3 + mov ip, #0 +.L2359: + movs r3, r0, lsr #28 + orr r3, r2, r3 + mov r1, ip, asl #1 + orr r3, r3, lr + strneh r3, [r1, fp] @ movhi + ldr r1, [sp, #4] + add ip, ip, #1 + cmp r1, ip + mov r0, r0, asl #4 + bne .L2359 + b .L2556 +.L2597: + cmp r4, #3 + bls .L2034 + cmp r0, #0 + ldr r1, [r6, #0] + beq .L2036 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r5, #0 +.L2038: + movs r3, r1, lsr #24 + mov r4, r5, asl #1 + orr r3, r3, lr + add r5, r5, #1 + strneh r3, [r4, fp] @ movhi + cmp r0, r5 + mov r1, r1, asl #8 + bne .L2038 + b .L2558 +.L2595: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L2372 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov r4, #0 +.L2374: + movs r3, r1, lsr #28 + orr r3, r0, r3 + mov r2, r4, asl #1 + orr r3, r3, lr + add r4, r4, #1 + strneh r3, [r2, fp] @ movhi + cmp r5, r4 + mov r1, r1, asl #4 + bne .L2374 + b .L2571 +.L2594: + cmp r4, #3 + bls .L1977 + ldr r3, [sp, #4] + ldr r0, [r0, #0] + cmp r3, #0 + beq .L2556 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, asl r3 + mov r1, #0 +.L1981: + movs r3, r0, lsr #24 + ldr ip, [sp, #4] + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp ip, r1 + mov r0, r0, asl #8 + bne .L1981 + b .L2556 +.L2596: + cmp r8, #0 + ldr r1, [sl, #4] + beq .L2174 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 +.L2200: + ands r3, r1, #255 + mov r4, r6, asl #1 + orr r3, r3, lr + add r6, r6, #1 + strneh r3, [r4, fp] @ movhi + cmp r8, r6 + mov r1, r1, lsr #8 + bne .L2200 + add fp, fp, r8, asl #1 + b .L2598 +.L1977: + ldr ip, [sp, #4] + mov r3, r4, asl #3 + ldr r1, [r0, #4] + add r2, ip, r4 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L1985 + cmp ip, #0 + movne r0, #0 + beq .L2556 +.L2000: + movs r3, r1, lsr #24 + orr r3, r3, lr + mov r2, r0, asl #1 + strneh r3, [r2, fp] @ movhi + ldr r3, [sp, #4] + add r0, r0, #1 + cmp r3, r0 + mov r1, r1, asl #8 + bne .L2000 + b .L2556 +.L2034: + subs r8, r0, #4 + ldr r1, [r6, #4] + beq .L2043 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r5, #0 +.L2045: + movs r3, r1, lsr #24 + mov r4, r5, asl #1 + orr r3, r3, lr + add r5, r5, #1 + strneh r3, [r4, fp] @ movhi + cmp r8, r5 + mov r1, r1, asl #8 + bne .L2045 + add r3, fp, r0, asl #1 + sub fp, r3, #8 +.L2043: + ldr r1, [r6, #0] + cmp r1, #0 + beq .L2074 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi +.L2074: + add fp, fp, #8 + b .L2036 +.L2004: + ldr ip, [sp, #4] + ldr r3, [r0, #0] + add r2, ip, r4 + cmp r2, #4 + mov r1, r4, asl #3 + mov r2, r3, lsr r1 + bhi .L2011 + cmp ip, #0 + movne r0, #0 + beq .L2556 +.L2026: + ands r3, r2, #255 + orr r3, r3, lr + mov r1, r0, asl #1 + strneh r3, [r1, fp] @ movhi + ldr r3, [sp, #4] + add r0, r0, #1 + cmp r3, r0 + mov r2, r2, lsr #8 + bne .L2026 + b .L2556 +.L2059: + subs r8, r0, #4 + ldr r1, [r6, #0] + beq .L2067 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov r5, #0 +.L2069: + ands r3, r1, #255 + mov r4, r5, asl #1 + orr r3, r3, lr + add r5, r5, #1 + strneh r3, [r4, fp] @ movhi + cmp r8, r5 + mov r1, r1, lsr #8 + bne .L2069 + add r3, fp, r0, asl #1 + sub fp, r3, #8 +.L2067: + ldr r1, [r6, #4] + cmp r1, #0 + beq .L2074 + ands r3, r1, #255 + orrne r3, r3, lr + strneh r3, [fp, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, r3, lr + strneh r3, [fp, #4] @ movhi + movs r3, r1, lsr #24 + orrne r3, r3, lr + strneh r3, [fp, #6] @ movhi + add fp, fp, #8 + b .L2036 +.L1985: + rsbs r4, r4, #4 + beq .L1988 + mov ip, #0 +.L1990: + movs r3, r1, lsr #24 + mov r2, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r2, fp] @ movhi + cmp r4, ip + mov r1, r1, asl #8 + bne .L1990 + add fp, fp, r4, asl #1 +.L1988: + ldr r1, [sp, #4] + ldr r0, [r0, #0] + subs ip, r1, r4 + beq .L2556 + mov r1, #0 +.L1996: + movs r3, r0, lsr #24 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp ip, r1 + mov r0, r0, asl #8 + bne .L1996 + b .L2556 +.L2011: + rsbs r4, r4, #4 + beq .L2014 + mov ip, #0 +.L2016: + ands r3, r2, #255 + mov r1, ip, asl #1 + orr r3, r3, lr + add ip, ip, #1 + strneh r3, [r1, fp] @ movhi + cmp r4, ip + mov r2, r2, lsr #8 + bne .L2016 + add fp, fp, r4, asl #1 +.L2014: + ldr r1, [sp, #4] + ldr r0, [r0, #4] + subs ip, r1, r4 + beq .L2556 + mov r1, #0 +.L2022: + ands r3, r0, #255 + mov r2, r1, asl #1 + orr r3, r3, lr + add r1, r1, #1 + strneh r3, [r2, fp] @ movhi + cmp ip, r1 + mov r0, r0, lsr #8 + bne .L2022 + b .L2556 + .size render_scanline_text_transparent_color16, .-render_scanline_text_transparent_color16 + .align 2 + .global render_scanline_text_base_color32 + .type render_scanline_text_base_color32, %function +render_scanline_text_base_color32: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L3398 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh r5, [ip, #80] + add r7, r0, #7 + mov r8, r5, asr r0 + mov r7, r5, asr r7 + add r6, ip, r0, asl #2 + ldrh r4, [ip, #6] + ldrh lr, [r6, #18] + add ip, ip, r0, asl #1 + add fp, r4, lr + ldrh r9, [ip, #8] + mov sl, fp, asl #23 + rsb r2, r1, r2 + sub sp, sp, #16 + mov sl, sl, lsr #23 + cmp sl, #255 + movls r4, #0 + movhi r4, #1 + ldrh lr, [r6, #16] + str r2, [sp, #12] + mov r6, r9, lsr #14 + ldr r2, .L3398+4 + ands r4, r4, r6, lsr #1 + and r7, r7, #2 + and r8, r8, #1 + add lr, lr, r1 + orr r8, r8, r7 + mov ip, r9, asl #3 + add r7, r3, r1, asl #2 + ldr r2, [r2, r6, asl #2] + subne r3, sl, #256 + ldr r1, .L3398+8 + movne r3, r3, lsr #3 + moveq r3, fp, asl #3 + and ip, ip, #63488 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + add ip, ip, r1 + mov lr, lr, asl #23 + addne r4, ip, r3, asl #6 + addeq r4, ip, r3 + mov r0, r5, lsr #12 + tst r6, #1 + mov lr, lr, lsr #23 + and r0, r0, #2 + mov r5, r5, asl #26 + andeq lr, lr, #255 + orr r0, r0, r5, lsr #31 + moveq r3, lr, lsr #3 + mov r0, r0, asl #9 + mov r8, r8, asl #9 + addeq fp, r4, r3, asl #1 + streq r4, [sp, #0] + beq .L2609 + cmp lr, #255 + subhi lr, lr, #256 + movhi r3, lr, lsr #3 + movls r3, lr, lsr #3 + addhi r3, r4, r3, asl #1 + addls fp, r4, r3, asl #1 + addls r4, r4, #2048 + addhi fp, r3, #2048 + strhi r4, [sp, #0] + strls r4, [sp, #0] +.L2609: + tst r9, #128 + beq .L2610 + mov r2, r9, asl #12 + and r3, sl, #7 + and r1, lr, #255 + mov r3, r3, asl #3 + and r2, r2, #49152 + ldr r4, [sp, #12] + rsb r9, r1, #256 + add r2, r2, r3 + ldr r1, .L3398+8 + mov r3, r3, asl #1 + rsb r3, r3, #56 + cmp r4, r9 + add r2, r2, r1 + str r3, [sp, #4] + and lr, lr, #7 + bls .L3366 + cmp lr, #0 + moveq r6, lr + bne .L3367 +.L2850: + rsb r3, r6, r9 + movs sl, r3, lsr #3 + beq .L2914 + mov lr, r7 + mov r6, #0 + b .L2916 +.L3368: + ldr r1, [r5, #4] + add r6, r6, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #12] + mov r3, r1, lsr #8 + streq r0, [lr, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + mov r3, r1, lsr #16 + streq r0, [lr, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] + ldr r1, [r5, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #28] + mov r3, r1, lsr #8 + streq r0, [lr, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + mov r3, r1, lsr #16 + streq r0, [lr, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + streq r0, [lr, #20] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #16] + streq r0, [lr, #16] + cmp sl, r6 + add lr, lr, #32 + beq .L2968 +.L3369: + add fp, fp, #2 +.L2916: + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r5, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r1, #1024 + bne .L3368 + ldr r1, [r5, #0] + add r6, r6, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #0] + mov r3, r1, lsr #8 + streq r0, [lr, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + mov r3, r1, lsr #16 + streq r0, [lr, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + streq r0, [lr, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #12] + streq r0, [lr, #12] + ldr r1, [r5, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #16] + mov r3, r1, lsr #8 + streq r0, [lr, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + mov r3, r1, lsr #16 + streq r0, [lr, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #28] + streq r0, [lr, #28] + cmp sl, r6 + add lr, lr, #32 + bne .L3369 +.L2968: + add r7, r7, sl, asl #5 +.L2914: + ldr r4, [sp, #12] + rsb r9, r9, r4 + movs r4, r9, lsr #3 + ldreq r3, [sp, #0] + beq .L2972 + ldr r6, [sp, #0] + mov lr, r7 + mov sl, #0 + b .L2973 +.L3371: + ldr r1, [r5, #4] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #12] + mov r3, r1, lsr #8 + streq r0, [lr, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + mov r3, r1, lsr #16 + streq r0, [lr, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] + ldr r1, [r5, #0] + add r6, r6, #2 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #28] + mov r3, r1, lsr #8 + streq r0, [lr, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + mov r3, r1, lsr #16 + streq r0, [lr, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + streq r0, [lr, #20] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #16] + streq r0, [lr, #16] + cmp r4, sl + add lr, lr, #32 + beq .L3370 +.L2973: + ldrh r1, [r6, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r5, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r1, #1024 + bne .L3371 + ldr r1, [r5, #0] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #0] + mov r3, r1, lsr #8 + streq r0, [lr, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + mov r3, r1, lsr #16 + streq r0, [lr, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + streq r0, [lr, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #12] + streq r0, [lr, #12] + ldr r1, [r5, #4] + add r6, r6, #2 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #16] + mov r3, r1, lsr #8 + streq r0, [lr, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + mov r3, r1, lsr #16 + streq r0, [lr, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #28] + streq r0, [lr, #28] + cmp r4, sl + add lr, lr, #32 + bne .L2973 +.L3370: + ldr r1, [sp, #0] + add r7, r7, r4, asl #5 + add r3, r1, r4, asl #1 +.L2972: + ands lr, r9, #7 + beq .L3345 + ldrh r4, [r3, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r2, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r2, r2, r3 + tst r4, #1024 + beq .L3029 + cmp lr, #3 + ldrls r2, [r2, #4] + bhi .L3372 +.L3046: + mov r1, #0 +.L3047: + movs r3, r2, lsr #24 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp r1, lr + mov r2, r2, asl #8 + add r7, r7, #4 + bcc .L3047 +.L3345: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L2610: + mov r2, r9, asl #12 + and r3, sl, #7 + and r1, lr, #255 + mov r3, r3, asl #2 + and r2, r2, #49152 + ldr r4, [sp, #12] + rsb r9, r1, #256 + add r2, r2, r3 + ldr r1, .L3398+8 + mov r3, r3, asl #1 + rsb r3, r3, #28 + cmp r4, r9 + add ip, r2, r1 + str r3, [sp, #8] + and r1, lr, #7 + bls .L3373 + cmp r1, #0 + moveq r6, r1 + bne .L3374 +.L3190: + rsb r3, r6, r9 + movs sl, r3, lsr #3 + beq .L3210 + mov lr, r7 + mov r6, #0 + b .L3212 +.L3375: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3243 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + mov r3, r2, lsr #4 + streq r0, [lr, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + mov r3, r2, lsr #8 + streq r0, [lr, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #12 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #16 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #20 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #24 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L3242: + add r6, r6, #1 + cmp sl, r6 + add lr, lr, #32 + beq .L3268 +.L3376: + add fp, fp, #2 +.L3212: + ldrh r1, [fp, #0] + tst r1, #2048 + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + ldrne r4, [sp, #8] + mov r2, r2, lsr #22 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + addne r3, r3, r4 + tst r1, #1024 + bne .L3375 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3243 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + mov r3, r2, lsr #4 + streq r0, [lr, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + mov r3, r2, lsr #8 + streq r0, [lr, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #12 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #16 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #20 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #24 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + bne .L3242 + str r0, [lr, #28] +.L3386: + add r6, r6, #1 + cmp sl, r6 + add lr, lr, #32 + bne .L3376 +.L3268: + add r7, r7, sl, asl #5 +.L3210: + ldr r1, [sp, #12] + rsb r9, r9, r1 + movs r4, r9, lsr #3 + ldreq r2, [sp, #0] + beq .L3272 + ldr r6, [sp, #0] + mov lr, r7 + mov sl, #0 + b .L3273 +.L3378: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3304 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + mov r3, r2, lsr #4 + streq r0, [lr, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + mov r3, r2, lsr #8 + streq r0, [lr, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #12 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #16 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #20 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #24 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L3303: + add sl, sl, #1 + cmp r4, sl + add lr, lr, #32 + add r6, r6, #2 + beq .L3377 +.L3273: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L3378 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3304 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + mov r3, r2, lsr #4 + streq r0, [lr, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + mov r3, r2, lsr #8 + streq r0, [lr, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #12 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #16 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #20 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #24 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + bne .L3303 + str r0, [lr, #28] +.L3387: + add sl, sl, #1 + cmp r4, sl + add lr, lr, #32 + add r6, r6, #2 + bne .L3273 +.L3377: + ldr r3, [sp, #0] + add r7, r7, r4, asl #5 + add r2, r3, r4, asl #1 +.L3272: + ands lr, r9, #7 + beq .L3345 + ldrh r4, [r2, #0] + tst r4, #2048 + mov r3, r4, asl #22 + ldrne r1, [sp, #8] + mov r3, r3, lsr #22 + add r3, ip, r3, asl #5 + addne r3, r3, r1 + mov r2, r4, lsr #12 + tst r4, #1024 + mov ip, r2, asl #4 + moveq r1, #0 + ldreq r2, [r3, #0] + beq .L3340 + ldr r2, [r3, #0] + mov r1, #0 +.L3335: + movs r3, r2, lsr #28 + orr r3, r8, r3 + orr r3, ip, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, asl #4 + add r7, r7, #4 + bne .L3335 + b .L3345 +.L3373: + cmp r1, #0 + bne .L3379 +.L3075: + ldr r4, [sp, #12] + movs r9, r4, lsr #3 + beq .L3114 + mov lr, r7 + mov r6, fp + mov sl, #0 + b .L3116 +.L3381: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3147 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + mov r3, r2, lsr #4 + streq r0, [lr, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + mov r3, r2, lsr #8 + streq r0, [lr, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #12 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #16 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #20 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #24 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L3146: + add sl, sl, #1 + cmp r9, sl + add lr, lr, #32 + add r6, r6, #2 + beq .L3380 +.L3116: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r5, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L3381 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3147 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #0] + mov r3, r2, lsr #4 + streq r0, [lr, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #4] + mov r3, r2, lsr #8 + streq r0, [lr, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #8] + mov r3, r2, lsr #12 + streq r0, [lr, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #12] + mov r3, r2, lsr #16 + streq r0, [lr, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #16] + mov r3, r2, lsr #20 + streq r0, [lr, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #20] + mov r3, r2, lsr #24 + streq r0, [lr, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r5, r3 + strne r3, [lr, #28] + bne .L3146 + str r0, [lr, #28] +.L3391: + add sl, sl, #1 + cmp r9, sl + add lr, lr, #32 + add r6, r6, #2 + bne .L3116 +.L3380: + add r7, r7, r9, asl #5 + add fp, fp, r9, asl #1 +.L3114: + ldr r3, [sp, #12] + ands lr, r3, #7 + beq .L3345 + ldrh r1, [fp, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #8] + mov r3, r3, lsr #22 + add r3, ip, r3, asl #5 + mov r2, r1, lsr #12 + addne r3, r3, r4 + tst r1, #1024 + mov ip, r2, asl #4 + moveq r1, #0 + ldreq r2, [r3, #0] + beq .L3183 + ldr r2, [r3, #0] + mov r1, #0 +.L3178: + movs r3, r2, lsr #28 + orr r3, r8, r3 + orr r3, ip, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, asl #4 + add r7, r7, #4 + bne .L3178 + b .L3345 +.L3366: + cmp lr, #0 + bne .L3382 +.L2614: + ldr r3, [sp, #12] + movs r9, r3, lsr #3 + beq .L2746 + mov lr, r7 + mov r6, fp + mov sl, #0 + b .L2748 +.L3384: + ldr r1, [r5, #4] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #12] + mov r3, r1, lsr #8 + streq r0, [lr, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + mov r3, r1, lsr #16 + streq r0, [lr, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + streq r0, [lr, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #0] + streq r0, [lr, #0] + ldr r1, [r5, #0] + add r6, r6, #2 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #28] + mov r3, r1, lsr #8 + streq r0, [lr, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + mov r3, r1, lsr #16 + streq r0, [lr, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + streq r0, [lr, #20] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #16] + streq r0, [lr, #16] + cmp r9, sl + add lr, lr, #32 + beq .L3383 +.L2748: + ldrh r1, [r6, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add r5, r2, r3, asl #6 + addne r5, r5, r4 + tst r1, #1024 + bne .L3384 + ldr r1, [r5, #0] + add sl, sl, #1 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #0] + mov r3, r1, lsr #8 + streq r0, [lr, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #4] + mov r3, r1, lsr #16 + streq r0, [lr, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #8] + streq r0, [lr, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #12] + streq r0, [lr, #12] + ldr r1, [r5, #4] + add r6, r6, #2 + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [lr, #16] + mov r3, r1, lsr #8 + streq r0, [lr, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #20] + mov r3, r1, lsr #16 + streq r0, [lr, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [lr, #24] + streq r0, [lr, #24] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [lr, #28] + streq r0, [lr, #28] + cmp r9, sl + add lr, lr, #32 + bne .L2748 +.L3383: + add r7, r7, r9, asl #5 + add fp, fp, r9, asl #1 +.L2746: + ldr r1, [sp, #12] + ands lr, r1, #7 + beq .L3345 + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r2, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne r2, r2, r3 + tst r1, #1024 + beq .L2804 + cmp lr, #3 + ldrls r2, [r2, #4] + bhi .L3385 +.L2821: + mov r1, #0 +.L2822: + movs r3, r2, lsr #24 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, asl #8 + add r7, r7, #4 + bhi .L2822 + b .L3345 +.L3243: + str r0, [lr, #0] + str r0, [lr, #4] + str r0, [lr, #8] + str r0, [lr, #12] + str r0, [lr, #16] + str r0, [lr, #20] + str r0, [lr, #24] + str r0, [lr, #28] + b .L3386 +.L3304: + str r0, [lr, #0] + str r0, [lr, #4] + str r0, [lr, #8] + str r0, [lr, #12] + str r0, [lr, #16] + str r0, [lr, #20] + str r0, [lr, #24] + str r0, [lr, #28] + b .L3387 +.L3340: + ands r3, r2, #15 + orr r3, r8, r3 + orr r3, ip, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, lsr #4 + add r7, r7, #4 + bne .L3340 + b .L3345 +.L3379: + rsb r5, r1, #8 + cmp r4, r5 + bcs .L3077 + ldrh lr, [fp, #0] + mov r3, lr, asl #22 + mov r3, r3, lsr #22 + tst lr, #2048 + add ip, ip, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, lr, lsr #12 + addne ip, ip, r3 + tst lr, #1024 + mov r2, r2, asl #4 + bne .L3388 + ldr r4, [sp, #12] + ldr ip, [ip, #0] + cmp r4, #0 + beq .L3345 + mov r3, r1, asl #2 + mov r1, ip, lsr r3 + mov ip, #0 +.L3090: + ands r3, r1, #15 + orr r3, r8, r3 + orr r3, r2, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add ip, ip, #1 + streq r0, [r7, #0] + cmp r3, ip + mov r1, r1, lsr #4 + add r7, r7, #4 + bne .L3090 + b .L3345 +.L3374: + ldrh r5, [fp, #0] + rsb r6, r1, #8 + mov r2, r5, asl #22 + mov r2, r2, lsr #22 + tst r5, #2048 + mov r3, r5, lsr #12 + mov sl, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r5, #1024 + beq .L3193 + cmp r6, #0 + ldr r2, [r3, #0] + beq .L3195 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov lr, #0 + mov r2, r7 +.L3197: + movs r3, r1, lsr #28 + orr r3, r8, r3 + orr r3, sl, r3 + add lr, lr, #1 + strne r3, [r2, #0] + streq r0, [r2, #0] + cmp r6, lr + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L3197 + add r7, r7, r6, asl #2 +.L3195: + add fp, fp, #2 + b .L3190 +.L3399: + .align 2 +.L3398: + .word io_registers + .word map_widths + .word vram +.L3367: + ldrh r1, [fp, #0] + rsb r6, lr, #8 + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add sl, r2, r3, asl #6 + addne sl, sl, r4 + ands r5, r1, #1024 + beq .L2853 + cmp lr, #3 + bhi .L3389 + subs ip, r6, #4 + ldr r1, [sl, #4] + beq .L2865 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L2867: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp ip, r5 + mov r1, r1, asl #8 + add lr, lr, #4 + bne .L2867 + add r3, r7, r6, asl #2 + sub r7, r3, #16 +.L2865: + ldr r1, [sl, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #12] + mov r3, r1, lsr #8 + streq r0, [r7, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + mov r3, r1, lsr #16 + streq r0, [r7, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + streq r0, [r7, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L2913: + add r7, r7, #16 + mov r6, ip +.L2857: + add fp, fp, #2 + b .L2850 +.L3382: + ldr r3, [sp, #12] + rsb r4, lr, #8 + cmp r3, r4 + bcs .L2616 + ldrh r1, [fp, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r4, [sp, #4] + mov r3, r3, lsr #22 + add ip, r2, r3, asl #6 + addne ip, ip, r4 + tst r1, #1024 + bne .L3390 + cmp lr, #3 + bls .L2653 + ldr r4, [sp, #12] + ldr r2, [ip, #4] + cmp r4, #0 + beq .L3345 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L2656: + ands r3, r1, #255 + orr r3, r8, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add r2, r2, #1 + streq r0, [r7, #0] + cmp r3, r2 + mov r1, r1, lsr #8 + add r7, r7, #4 + bne .L2656 + b .L3345 +.L3147: + str r0, [lr, #0] + str r0, [lr, #4] + str r0, [lr, #8] + str r0, [lr, #12] + str r0, [lr, #16] + str r0, [lr, #20] + str r0, [lr, #24] + str r0, [lr, #28] + b .L3391 +.L3183: + ands r3, r2, #15 + orr r3, r8, r3 + orr r3, ip, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, lsr #4 + add r7, r7, #4 + bne .L3183 + b .L3345 +.L3029: + cmp lr, #3 + ldrls r2, [r2, #0] + bhi .L3392 +.L3067: + mov r1, #0 +.L3068: + ands r3, r2, #255 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #4 + bhi .L3068 + b .L3345 +.L2804: + cmp lr, #3 + ldrls r2, [r2, #0] + bhi .L3393 +.L2842: + mov r1, #0 +.L2843: + ands r3, r2, #255 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #4 + bhi .L2843 + b .L3345 +.L3193: + cmp r6, #0 + ldr r2, [r3, #0] + beq .L3195 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov lr, #0 + mov r2, r7 +.L3204: + ands r3, r1, #15 + orr r3, r8, r3 + orr r3, sl, r3 + add lr, lr, #1 + strne r3, [r2, #0] + streq r0, [r2, #0] + cmp r6, lr + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L3204 + add r7, r7, r6, asl #2 + b .L3195 +.L3077: + ldrh lr, [fp, #0] + mov r2, lr, asl #22 + mov r2, r2, lsr #22 + tst lr, #2048 + mov r3, lr, lsr #12 + mov r4, r3, asl #4 + add r3, ip, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst lr, #1024 + bne .L3394 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L3099 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov lr, #0 + mov r2, r7 +.L3108: + ands r3, r1, #15 + orr r3, r8, r3 + orr r3, r4, r3 + add lr, lr, #1 + strne r3, [r2, #0] + streq r0, [r2, #0] + cmp r5, lr + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L3108 +.L3360: + add r7, r7, r5, asl #2 +.L3099: + ldr r3, [sp, #12] + add fp, fp, #2 + rsb r3, r5, r3 + str r3, [sp, #12] + b .L3075 +.L2853: + cmp lr, #3 + bhi .L3395 + subs ip, r6, #4 + ldr r1, [sl, #0] + beq .L2894 + mov r3, lr, asl #3 + mov r1, r1, lsr r3 + mov lr, r7 + mov r5, #0 +.L2896: + ands r3, r1, #255 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp ip, r5 + mov r1, r1, lsr #8 + add lr, lr, #4 + bne .L2896 + add r3, r7, r6, asl #2 + sub r7, r3, #16 +.L2894: + ldr r1, [sl, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #0] + mov r3, r1, lsr #8 + streq r0, [r7, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + mov r3, r1, lsr #16 + streq r0, [r7, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + streq r0, [r7, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #12] + streq r0, [r7, #12] + b .L2913 +.L2616: + ldrh r1, [fp, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add ip, r2, r3, asl #6 + ldrne r3, [sp, #4] + addne ip, ip, r3 + ands r5, r1, #1024 + bne .L3396 + cmp lr, #3 + bls .L2717 + cmp r4, #0 + ldr r1, [ip, #4] + beq .L2689 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov ip, r5 + mov lr, r7 +.L2720: + ands r3, r1, #255 + orr r3, r8, r3 + add ip, ip, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r4, ip + mov r1, r1, lsr #8 + add lr, lr, #4 + bne .L2720 +.L3347: + add r7, r7, r4, asl #2 +.L2689: + ldr r1, [sp, #12] + add fp, fp, #2 + rsb r1, r4, r1 + str r1, [sp, #12] + b .L2614 +.L3392: + ldr r1, [r2, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #0] + mov r3, r1, lsr #8 + streq r0, [r7, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + mov r3, r1, lsr #16 + streq r0, [r7, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + streq r0, [r7, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #12] + streq r0, [r7, #12] + subs lr, lr, #4 + ldr r2, [r2, #4] + addne r7, r7, #16 + bne .L3067 + b .L3345 +.L3372: + ldr r1, [r2, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #12] + mov r3, r1, lsr #8 + streq r0, [r7, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + mov r3, r1, lsr #16 + streq r0, [r7, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + streq r0, [r7, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #0] + streq r0, [r7, #0] + subs lr, lr, #4 + ldr r2, [r2, #0] + addne r7, r7, #16 + bne .L3046 + b .L3345 +.L3385: + ldr r1, [r2, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #12] + mov r3, r1, lsr #8 + streq r0, [r7, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + mov r3, r1, lsr #16 + streq r0, [r7, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + streq r0, [r7, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #0] + streq r0, [r7, #0] + subs lr, lr, #4 + ldr r2, [r2, #0] + addne r7, r7, #16 + bne .L2821 + b .L3345 +.L3393: + ldr r1, [r2, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #0] + mov r3, r1, lsr #8 + streq r0, [r7, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + mov r3, r1, lsr #16 + streq r0, [r7, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + streq r0, [r7, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #12] + streq r0, [r7, #12] + subs lr, lr, #4 + ldr r2, [r2, #4] + addne r7, r7, #16 + bne .L2842 + b .L3345 +.L3389: + cmp r6, #0 + ldr r1, [sl, #0] + beq .L2857 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L2859: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r6, r5 + mov r1, r1, asl #8 + add lr, lr, #4 + bne .L2859 + add r7, r7, r6, asl #2 +.L3397: + add fp, fp, #2 + b .L2850 +.L3388: + ldr r4, [sp, #12] + ldr ip, [ip, #0] + cmp r4, #0 + beq .L3345 + mov r3, r1, asl #2 + mov r1, ip, asl r3 + mov ip, #0 +.L3084: + movs r3, r1, lsr #28 + orr r3, r8, r3 + orr r3, r2, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add ip, ip, #1 + streq r0, [r7, #0] + cmp r3, ip + mov r1, r1, asl #4 + add r7, r7, #4 + bne .L3084 + b .L3345 +.L3396: + cmp lr, #3 + bls .L2687 + cmp r4, #0 + ldr r1, [ip, #0] + beq .L2689 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L2691: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r4, r5 + mov r1, r1, asl #8 + add lr, lr, #4 + bne .L2691 + b .L3347 +.L3394: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L3099 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov lr, #0 + mov r2, r7 +.L3101: + movs r3, r1, lsr #28 + orr r3, r8, r3 + orr r3, r4, r3 + add lr, lr, #1 + strne r3, [r2, #0] + streq r0, [r2, #0] + cmp r5, lr + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L3101 + b .L3360 +.L3390: + cmp lr, #3 + bls .L2622 + ldr r1, [sp, #12] + ldr r2, [ip, #0] + cmp r1, #0 + beq .L3345 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r2, #0 +.L2626: + movs r3, r1, lsr #24 + orr r3, r8, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add r2, r2, #1 + streq r0, [r7, #0] + cmp r3, r2 + mov r1, r1, asl #8 + add r7, r7, #4 + bne .L2626 + b .L3345 +.L3395: + cmp r6, #0 + ldr r1, [sl, #4] + beq .L2857 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov lr, r7 +.L2888: + ands r3, r1, #255 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r6, r5 + mov r1, r1, lsr #8 + add lr, lr, #4 + bne .L2888 + add r7, r7, r6, asl #2 + b .L3397 +.L2622: + ldr r4, [sp, #12] + mov r3, lr, asl #3 + ldr r1, [ip, #4] + add r2, r4, lr + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L2631 + cmp r4, #0 + movne r2, #0 + beq .L3345 +.L2648: + movs r3, r1, lsr #24 + orr r3, r8, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add r2, r2, #1 + streq r0, [r7, #0] + cmp r3, r2 + mov r1, r1, asl #8 + add r7, r7, #4 + bne .L2648 + b .L3345 +.L2687: + subs r6, r4, #4 + ldr r1, [ip, #4] + beq .L2697 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov lr, r7 + mov r5, #0 +.L2699: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r6, r5 + mov r1, r1, asl #8 + add lr, lr, #4 + bne .L2699 + add r3, r7, r4, asl #2 + sub r7, r3, #16 +.L2697: + ldr r1, [ip, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #12] + mov r3, r1, lsr #8 + streq r0, [r7, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + mov r3, r1, lsr #16 + streq r0, [r7, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + streq r0, [r7, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L2745: + add r7, r7, #16 + b .L2689 +.L2653: + ldr r4, [sp, #12] + ldr r3, [ip, #0] + add r2, r4, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov r2, r3, lsr r1 + bhi .L2661 + cmp r4, #0 + movne r1, #0 + beq .L3345 +.L2678: + ands r3, r2, #255 + orr r3, r8, r3 + strne r3, [r7, #0] + ldr r3, [sp, #12] + add r1, r1, #1 + streq r0, [r7, #0] + cmp r3, r1 + mov r2, r2, lsr #8 + add r7, r7, #4 + bne .L2678 + b .L3345 +.L2717: + subs r6, r4, #4 + ldr r1, [ip, #0] + beq .L2726 + mov r3, lr, asl #3 + mov r1, r1, lsr r3 + mov lr, r7 + mov r5, #0 +.L2728: + ands r3, r1, #255 + orr r3, r8, r3 + add r5, r5, #1 + strne r3, [lr, #0] + streq r0, [lr, #0] + cmp r6, r5 + mov r1, r1, lsr #8 + add lr, lr, #4 + bne .L2728 + add r3, r7, r4, asl #2 + sub r7, r3, #16 +.L2726: + ldr r1, [ip, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r7, #0] + mov r3, r1, lsr #8 + streq r0, [r7, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #4] + mov r3, r1, lsr #16 + streq r0, [r7, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r7, #8] + streq r0, [r7, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r7, #12] + bne .L2745 + str r0, [r7, #12] + add r7, r7, #16 + b .L2689 +.L2631: + rsbs r4, lr, #4 + beq .L2634 + mov r2, r7 + mov lr, #0 +.L2636: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add lr, lr, #1 + strne r3, [r2, #0] + streq r0, [r2, #0] + cmp r4, lr + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L2636 + add r7, r7, r4, asl #2 +.L2634: + ldr r1, [sp, #12] + ldr r2, [ip, #0] + subs lr, r1, r4 + beq .L3345 + mov r1, #0 +.L2643: + movs r3, r2, lsr #24 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, asl #8 + add r7, r7, #4 + bne .L2643 + b .L3345 +.L2661: + rsbs r4, lr, #4 + beq .L2664 + mov r1, r7 + mov lr, #0 +.L2666: + ands r3, r2, #255 + orr r3, r8, r3 + add lr, lr, #1 + strne r3, [r1, #0] + streq r0, [r1, #0] + cmp r4, lr + mov r2, r2, lsr #8 + add r1, r1, #4 + bne .L2666 + add r7, r7, r4, asl #2 +.L2664: + ldr r1, [sp, #12] + ldr r2, [ip, #4] + subs lr, r1, r4 + beq .L3345 + mov r1, #0 +.L2673: + ands r3, r2, #255 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r7, #0] + streq r0, [r7, #0] + cmp lr, r1 + mov r2, r2, lsr #8 + add r7, r7, #4 + bne .L2673 + b .L3345 + .size render_scanline_text_base_color32, .-render_scanline_text_base_color32 + .align 2 + .global render_scanline_text_transparent_color32 + .type render_scanline_text_transparent_color32, %function +render_scanline_text_transparent_color32: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L4043 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh lr, [ip, #80] + add r6, r0, #7 + mov r6, lr, asr r6 + mov lr, lr, asr r0 + add r7, ip, r0, asl #2 + ldrh r5, [ip, #6] + ldrh r4, [r7, #18] + add ip, ip, r0, asl #1 + add sl, r5, r4 + ldrh r8, [ip, #8] + mov r5, sl, asl #23 + mov r5, r5, lsr #23 + ldrh r4, [r7, #16] + cmp r5, #255 + movls ip, #0 + movhi ip, #1 + mov r7, r8, lsr #14 + rsb fp, r1, r2 + ldr r2, .L4043+4 + ands ip, ip, r7, lsr #1 + ldr r2, [r2, r7, asl #2] + add ip, r3, r1, asl #2 + mov r0, r8, asl #3 + subne r3, r5, #256 + ldr r9, .L4043+8 + movne r3, r3, lsr #3 + moveq r3, sl, asl #3 + add r4, r4, r1 + and r0, r0, #63488 + add r0, r0, r9 + addne r3, r3, r2, lsr #3 + andeq r3, r3, #1984 + mov r4, r4, asl #23 + addne r0, r0, r3, asl #6 + addeq r0, r0, r3 + mov r4, r4, lsr #23 + tst r7, #1 + and lr, lr, #1 + and r6, r6, #2 + andeq r4, r4, #255 + sub sp, sp, #4 + orr lr, lr, r6 + moveq r3, r4, lsr #3 + mov lr, lr, asl #9 + addeq r7, r0, r3, asl #1 + streq r0, [sp, #0] + beq .L3408 + cmp r4, #255 + subhi r4, r4, #256 + movhi r3, r4, lsr #3 + movls r3, r4, lsr #3 + addhi r3, r0, r3, asl #1 + addls r7, r0, r3, asl #1 + addls r0, r0, #2048 + addhi r7, r3, #2048 + strhi r0, [sp, #0] + strls r0, [sp, #0] +.L3408: + tst r8, #128 + beq .L3409 + and r1, r4, #255 + and r3, r5, #7 + mov r2, r8, asl #12 + mov r3, r3, asl #3 + and r2, r2, #49152 + rsb r0, r1, #256 + add r2, r2, r3 + cmp fp, r0 + mov r3, r3, asl #1 + add r2, r2, r9 + and r4, r4, #7 + rsb r9, r3, #56 + bls .L4018 + cmp r4, #0 + moveq r6, r4 + bne .L4019 +.L3611: + rsb r3, r6, r0 + movs sl, r3, lsr #3 + beq .L3665 + mov r6, ip + mov r8, #0 + b .L3667 +.L4020: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3672 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #0] +.L3672: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3681 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #20] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #16] +.L3681: + add r8, r8, #1 + cmp sl, r8 + add r6, r6, #32 + beq .L3707 +.L4021: + add r7, r7, #2 +.L3667: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, r9 + tst r1, #1024 + bne .L4020 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3690 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #12] +.L3690: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3681 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #16] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #20] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #24] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + add r8, r8, #1 + strne r3, [r6, #28] + cmp sl, r8 + add r6, r6, #32 + bne .L4021 +.L3707: + add ip, ip, sl, asl #5 +.L3665: + rsb sl, r0, fp + movs r0, sl, lsr #3 + ldreq r0, [sp, #0] + beq .L3711 + ldr r7, [sp, #0] + mov r6, ip + mov r8, #0 + b .L3712 +.L4023: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3717 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #0] +.L3717: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3726 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #20] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #16] +.L3726: + add r8, r8, #1 + cmp r0, r8 + add r6, r6, #32 + add r7, r7, #2 + beq .L4022 +.L3712: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, r9 + tst r1, #1024 + bne .L4023 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3735 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r6, #12] +.L3735: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3726 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r6, #16] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #20] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r6, #24] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + add r8, r8, #1 + strne r3, [r6, #28] + cmp r0, r8 + add r6, r6, #32 + add r7, r7, #2 + bne .L3712 +.L4022: + ldr r3, [sp, #0] + add ip, ip, r0, asl #5 + add r0, r3, r0, asl #1 +.L3711: + ands r4, sl, #7 + beq .L4000 + ldrh r0, [r0, #0] + mov r3, r0, asl #22 + mov r3, r3, lsr #22 + tst r0, #2048 + add r2, r2, r3, asl #6 + addne r2, r2, r9 + tst r0, #1024 + beq .L3756 + cmp r4, #3 + ldrls r0, [r2, #4] + bls .L3770 + ldr r1, [r2, #4] + cmp r1, #0 + beq .L3760 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #0] +.L3760: + subs r4, r4, #4 + ldr r0, [r2, #0] + addne ip, ip, #16 + beq .L4000 +.L3770: + mov r1, #0 +.L3771: + movs r3, r0, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r4 + mov r0, r0, asl #8 + bcc .L3771 +.L4000: + add sp, sp, #4 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L3409: + and r3, r5, #7 + and r1, r4, #255 + mov r2, r8, asl #12 + mov r3, r3, asl #2 + rsb r5, r1, #256 + and r2, r2, #49152 + add r2, r2, r3 + cmp fp, r5 + mov r3, r3, asl #1 + add sl, r2, r9 + and r1, r4, #7 + rsb r9, r3, #28 + bls .L4024 + cmp r1, #0 + moveq r4, r1 + bne .L4025 +.L3885: + rsb r3, r4, r5 + movs r0, r3, lsr #3 + beq .L3903 + mov r4, ip + mov r8, #0 + b .L3905 +.L4026: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3910 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] +.L3910: + add r8, r8, #1 + cmp r0, r8 + add r4, r4, #32 + beq .L3943 +.L4027: + add r7, r7, #2 +.L3905: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r6, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, r9 + tst r1, #1024 + bne .L4026 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3910 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r6, r3 + add r8, r8, #1 + strne r3, [r4, #28] + cmp r0, r8 + add r4, r4, #32 + bne .L4027 +.L3943: + add ip, ip, r0, asl #5 +.L3903: + rsb fp, r5, fp + movs r0, fp, lsr #3 + ldreq r0, [sp, #0] + beq .L3947 + ldr r7, [sp, #0] + mov r4, ip + mov r8, #0 + b .L3948 +.L4029: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3953 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] +.L3953: + add r8, r8, #1 + cmp r0, r8 + add r4, r4, #32 + add r7, r7, #2 + beq .L4028 +.L3948: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r6, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, r9 + tst r1, #1024 + bne .L4029 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3953 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r6, r3 + add r8, r8, #1 + strne r3, [r4, #28] + cmp r0, r8 + add r4, r4, #32 + add r7, r7, #2 + bne .L3948 +.L4028: + ldr r3, [sp, #0] + add ip, ip, r0, asl #5 + add r0, r3, r0, asl #1 +.L3947: + ands r4, fp, #7 + beq .L4000 + ldrh r0, [r0, #0] + mov r3, r0, asl #22 + mov r3, r3, lsr #22 + tst r0, #2048 + add r3, sl, r3, asl #5 + mov r2, r0, lsr #12 + addne r3, r3, r9 + tst r0, #1024 + mov r2, r2, asl #4 + ldreq r0, [r3, #0] + moveq r1, #0 + beq .L3996 + ldr r0, [r3, #0] + mov r1, #0 +.L3992: + movs r3, r0, lsr #28 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, asl #4 + bne .L3992 + b .L4000 +.L4024: + cmp r1, #0 + bne .L4030 +.L3794: + movs r0, fp, lsr #3 + beq .L3829 + mov r4, ip + mov r6, r7 + mov r8, #0 + b .L3831 +.L4032: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3836 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #0] +.L3836: + add r8, r8, #1 + cmp r0, r8 + add r4, r4, #32 + add r6, r6, #2 + beq .L4031 +.L3831: + ldrh r1, [r6, #0] + mov r2, r1, asl #22 + mov r3, r1, lsr #12 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r5, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, r9 + tst r1, #1024 + bne .L4032 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L3836 + ands r3, r2, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, lr, r3 + orrne r3, r5, r3 + strne r3, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, lr, r3 + orrne r3, r5, r3 + add r8, r8, #1 + strne r3, [r4, #28] + cmp r0, r8 + add r4, r4, #32 + add r6, r6, #2 + bne .L3831 +.L4031: + add ip, ip, r0, asl #5 + add r7, r7, r0, asl #1 +.L3829: + ands r4, fp, #7 + beq .L4000 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, sl, r3, asl #5 + mov r2, r1, lsr #12 + addne r0, r0, r9 + tst r1, #1024 + mov r2, r2, asl #4 + ldreq r0, [r0, #0] + moveq r1, #0 + beq .L3879 + ldr r0, [r0, #0] + mov r1, #0 +.L3875: + movs r3, r0, lsr #28 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, asl #4 + bne .L3875 + b .L4000 +.L4018: + cmp r4, #0 + bne .L4033 +.L3413: + movs sl, fp, lsr #3 + beq .L3527 + mov r5, ip + mov r6, r7 + mov r8, #0 + b .L3529 +.L4035: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3534 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r5, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r5, #0] +.L3534: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3543 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r5, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #20] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r5, #16] +.L3543: + add r8, r8, #1 + cmp sl, r8 + add r5, r5, #32 + add r6, r6, #2 + beq .L4034 +.L3529: + ldrh r1, [r6, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r4, r2, r3, asl #6 + addne r4, r4, r9 + tst r1, #1024 + bne .L4035 + ldr r1, [r4, #0] + cmp r1, #0 + beq .L3552 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r5, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [r5, #12] +.L3552: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L3543 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [r5, #16] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #20] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [r5, #24] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + add r8, r8, #1 + strne r3, [r5, #28] + cmp sl, r8 + add r5, r5, #32 + add r6, r6, #2 + bne .L3529 +.L4034: + add ip, ip, sl, asl #5 + add r7, r7, sl, asl #1 +.L3527: + ands r4, fp, #7 + beq .L4000 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r2, r3, asl #6 + addne r0, r0, r9 + tst r1, #1024 + beq .L3573 + cmp r4, #3 + ldrls r0, [r0, #4] + bls .L3587 + ldr r1, [r0, #4] + cmp r1, #0 + beq .L3577 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #0] +.L3577: + subs r4, r4, #4 + ldr r0, [r0, #0] + addne ip, ip, #16 + beq .L4000 +.L3587: + mov r1, #0 +.L3588: + movs r3, r0, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, asl #8 + bhi .L3588 + b .L4000 +.L3996: + ands r3, r0, #15 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, lsr #4 + beq .L4000 + ands r3, r0, #15 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, lsr #4 + bne .L3996 + b .L4000 +.L4030: + rsb r5, r1, #8 + cmp fp, r5 + bcs .L3796 + ldrh r4, [r7, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r0, sl, r3, asl #5 + mov r2, r4, lsr #12 + addne r0, r0, r9 + tst r4, #1024 + mov r2, r2, asl #4 + bne .L4036 + cmp fp, #0 + ldr r0, [r0, #0] + beq .L4000 + mov r3, r1, asl #2 + mov r0, r0, lsr r3 + mov r1, #0 +.L3808: + ands r3, r0, #15 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp fp, r1 + mov r0, r0, lsr #4 + bne .L3808 + b .L4000 +.L4025: + ldrh r6, [r7, #0] + rsb r4, r1, #8 + mov r2, r6, asl #22 + mov r3, r6, lsr #12 + mov r2, r2, lsr #22 + tst r6, #2048 + mov r8, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, r9 + tst r6, #1024 + beq .L3888 + cmp r4, #0 + ldr r2, [r3, #0] + beq .L3890 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov r2, #0 +.L3892: + movs r3, r1, lsr #28 + orr r3, lr, r3 + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r4, r2 + mov r1, r1, asl #4 + bne .L3892 + add ip, ip, r4, asl #2 +.L3890: + add r7, r7, #2 + b .L3885 +.L4019: + ldrh r1, [r7, #0] + rsb r6, r4, #8 + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r8, r2, r3, asl #6 + addne r8, r8, r9 + ands sl, r1, #1024 + beq .L3614 + cmp r4, #3 + bhi .L4037 + subs r5, r6, #4 + ldr r1, [r8, #4] + beq .L3625 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r4, #0 +.L3627: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r5, r4 + mov r1, r1, asl #8 + bne .L3627 + add r3, ip, r6, asl #2 + sub ip, r3, #16 +.L3625: + ldr r1, [r8, #0] + cmp r1, #0 + beq .L3656 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #0] +.L3656: + add ip, ip, #16 + mov r6, r5 +.L3618: + add r7, r7, #2 + b .L3611 +.L4033: + rsb r0, r4, #8 + cmp fp, r0 + bcs .L3415 + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r2, r3, asl #6 + addne r0, r0, r9 + tst r1, #1024 + bne .L4038 + cmp r4, #3 + bls .L3448 + cmp fp, #0 + ldr r0, [r0, #4] + beq .L4000 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, lsr r3 + mov r2, #0 +.L3451: + ands r3, r0, #255 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp fp, r2 + mov r0, r0, lsr #8 + bne .L3451 + b .L4000 +.L3879: + ands r3, r0, #15 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, lsr #4 + beq .L4000 + ands r3, r0, #15 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, lsr #4 + bne .L3879 + b .L4000 +.L4044: + .align 2 +.L4043: + .word io_registers + .word map_widths + .word vram +.L3756: + cmp r4, #3 + ldrls r0, [r2, #0] + bls .L3787 + ldr r1, [r2, #0] + cmp r1, #0 + beq .L3777 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #12] +.L3777: + subs r4, r4, #4 + ldr r0, [r2, #4] + addne ip, ip, #16 + beq .L4000 +.L3787: + mov r1, #0 +.L3788: + ands r3, r0, #255 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r4 + mov r0, r0, lsr #8 + bcc .L3788 + b .L4000 +.L3573: + cmp r4, #3 + ldrls r0, [r0, #0] + bls .L3604 + ldr r1, [r0, #0] + cmp r1, #0 + beq .L3594 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #12] +.L3594: + subs r4, r4, #4 + ldr r0, [r0, #4] + addne ip, ip, #16 + beq .L4000 +.L3604: + mov r1, #0 +.L3605: + ands r3, r0, #255 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r0, r0, lsr #8 + bhi .L3605 + b .L4000 +.L3796: + ldrh r4, [r7, #0] + mov r2, r4, asl #22 + mov r3, r4, lsr #12 + mov r2, r2, lsr #22 + tst r4, #2048 + mov r0, r3, asl #4 + add r3, sl, r2, asl #5 + addne r3, r3, r9 + tst r4, #1024 + bne .L4039 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L3816 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov r2, #0 +.L3824: + ands r3, r1, #15 + orr r3, lr, r3 + orr r3, r0, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r5, r2 + mov r1, r1, lsr #4 + bne .L3824 +.L4015: + add ip, ip, r5, asl #2 +.L3816: + rsb fp, r5, fp + add r7, r7, #2 + b .L3794 +.L3888: + cmp r4, #0 + ldr r2, [r3, #0] + beq .L3890 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov r2, #0 +.L3898: + ands r3, r1, #15 + orr r3, lr, r3 + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r4, r2 + mov r1, r1, lsr #4 + bne .L3898 + add ip, ip, r4, asl #2 + b .L3890 +.L3614: + cmp r4, #3 + bhi .L4040 + subs r5, r6, #4 + ldr r1, [r8, #0] + beq .L3649 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov r4, #0 +.L3651: + ands r3, r1, #255 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r5, r4 + mov r1, r1, lsr #8 + bne .L3651 + add r3, ip, r6, asl #2 + sub ip, r3, #16 +.L3649: + ldr r1, [r8, #4] + cmp r1, #0 + beq .L3656 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #12] + b .L3656 +.L3415: + ldrh r1, [r7, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r5, r2, r3, asl #6 + addne r5, r5, r9 + ands r6, r1, #1024 + bne .L4041 + cmp r4, #3 + bls .L3503 + cmp r0, #0 + ldr r1, [r5, #4] + beq .L3480 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov r4, r6 +.L3506: + ands r3, r1, #255 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r0, r4 + mov r1, r1, lsr #8 + bne .L3506 +.L4002: + add ip, ip, r0, asl #2 +.L3480: + rsb fp, r0, fp + add r7, r7, #2 + b .L3413 +.L4037: + cmp r6, #0 + ldr r1, [r8, #0] + beq .L3618 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r4, #0 +.L3620: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r6, r4 + mov r1, r1, asl #8 + bne .L3620 + add ip, ip, r6, asl #2 +.L4042: + add r7, r7, #2 + b .L3611 +.L4036: + cmp fp, #0 + ldr r0, [r0, #0] + beq .L4000 + mov r3, r1, asl #2 + mov r0, r0, asl r3 + mov r1, #0 +.L3803: + movs r3, r0, lsr #28 + orr r3, lr, r3 + orr r3, r2, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp fp, r1 + mov r0, r0, asl #4 + bne .L3803 + b .L4000 +.L4041: + cmp r4, #3 + bls .L3478 + cmp r0, #0 + ldr r1, [r5, #0] + beq .L3480 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r4, #0 +.L3482: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r0, r4 + mov r1, r1, asl #8 + bne .L3482 + b .L4002 +.L4039: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L3816 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov r2, #0 +.L3818: + movs r3, r1, lsr #28 + orr r3, lr, r3 + orr r3, r0, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r5, r2 + mov r1, r1, asl #4 + bne .L3818 + b .L4015 +.L4038: + cmp r4, #3 + bls .L3421 + cmp fp, #0 + ldr r0, [r0, #0] + beq .L4000 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, asl r3 + mov r2, #0 +.L3425: + movs r3, r0, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp fp, r2 + mov r0, r0, asl #8 + bne .L3425 + b .L4000 +.L4040: + cmp r6, #0 + ldr r1, [r8, #4] + beq .L3618 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov r4, sl +.L3644: + ands r3, r1, #255 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r6, r4 + mov r1, r1, lsr #8 + bne .L3644 + add ip, ip, r6, asl #2 + b .L4042 +.L3421: + mov r3, r4, asl #3 + ldr r1, [r0, #4] + add r2, fp, r4 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L3429 + cmp fp, #0 + movne r2, #0 + beq .L4000 +.L3444: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp fp, r2 + mov r1, r1, asl #8 + bne .L3444 + b .L4000 +.L3478: + subs r6, r0, #4 + ldr r1, [r5, #4] + beq .L3487 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r4, #0 +.L3489: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r6, r4 + mov r1, r1, asl #8 + bne .L3489 + add r3, ip, r0, asl #2 + sub ip, r3, #16 +.L3487: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L3518 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #0] +.L3518: + add ip, ip, #16 + b .L3480 +.L3448: + add r2, fp, r4 + ldr r3, [r0, #0] + cmp r2, #4 + mov r1, r4, asl #3 + mov r2, r3, lsr r1 + bhi .L3455 + cmp fp, #0 + movne r1, #0 + beq .L4000 +.L3470: + ands r3, r2, #255 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp fp, r1 + mov r2, r2, lsr #8 + bne .L3470 + b .L4000 +.L3503: + subs r6, r0, #4 + ldr r1, [r5, #0] + beq .L3511 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov r4, #0 +.L3513: + ands r3, r1, #255 + orr r3, lr, r3 + strne r3, [ip, r4, asl #2] + add r4, r4, #1 + cmp r6, r4 + mov r1, r1, lsr #8 + bne .L3513 + add r3, ip, r0, asl #2 + sub ip, r3, #16 +.L3511: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L3518 + ands r3, r1, #255 + orrne r3, lr, r3 + strne r3, [ip, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + orrne r3, lr, r3 + strne r3, [ip, #8] + movs r3, r1, lsr #24 + orrne r3, lr, r3 + strne r3, [ip, #12] + add ip, ip, #16 + b .L3480 +.L3429: + rsbs r4, r4, #4 + beq .L3432 + mov r2, #0 +.L3434: + movs r3, r1, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r4, r2 + mov r1, r1, asl #8 + bne .L3434 + add ip, ip, r4, asl #2 +.L3432: + subs r1, fp, r4 + ldr r0, [r0, #0] + beq .L4000 + mov r2, #0 +.L3440: + movs r3, r0, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r1, r2 + mov r0, r0, asl #8 + bne .L3440 + b .L4000 +.L3455: + rsbs r4, r4, #4 + beq .L3458 + mov r1, #0 +.L3460: + ands r3, r2, #255 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r2, r2, lsr #8 + bne .L3460 + add ip, ip, r4, asl #2 +.L3458: + subs r1, fp, r4 + ldr r0, [r0, #4] + beq .L4000 + mov r2, #0 +.L3466: + ands r3, r0, #255 + orr r3, lr, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r1, r2 + mov r0, r0, lsr #8 + bne .L3466 + b .L4000 + .size render_scanline_text_transparent_color32, .-render_scanline_text_transparent_color32 + .align 2 + .global render_scanline_text_base_alpha + .type render_scanline_text_base_alpha, %function +render_scanline_text_base_alpha: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r7, .L4840 + add lr, r0, #7 + ldrh ip, [r7, #80] + sub sp, sp, #16 + mov lr, ip, asr lr + mov r4, ip, asr r0 + mov r5, ip, lsr #12 + and r5, r5, #2 + mov ip, ip, asl #26 + orr r5, r5, ip, lsr #31 + and lr, lr, #2 + and r4, r4, #1 + orr r4, r4, lr + mov ip, r5, asl #25 + orr r8, ip, r4, asl #9 + tst r8, #512 + mov r6, r0 + mov lr, r1 + mov r9, r2 + mov fp, r3 + mov r5, r5, asl #9 + beq .L4813 + add r0, r7, r0, asl #2 + ldrh r1, [r7, #6] + ldrh r3, [r0, #18] + add r2, r7, r6, asl #1 + add sl, r1, r3 + ldrh r3, [r0, #16] + ldrh r7, [r2, #8] + mov r6, sl, asl #23 + mov r6, r6, lsr #23 + add r3, r3, lr + mov r4, r7, lsr #14 + cmp r6, #255 + movls r1, #0 + movhi r1, #1 + mov ip, r3, asl #23 + ldr r3, .L4840+4 + ands r1, r1, r4, lsr #1 + mov r2, r7, asl #3 + ldr r1, [r3, r4, asl #2] + ldr r0, .L4840+8 + subne r3, r6, #256 + movne r3, r3, lsr #3 + moveq r3, sl, asl #3 + and r2, r2, #63488 + addne r3, r3, r1, lsr #3 + andeq r3, r3, #1984 + add r2, r2, r0 + addne r1, r2, r3, asl #6 + addeq r1, r2, r3 + mov ip, ip, lsr #23 + tst r4, #1 + andeq ip, ip, #255 + rsb r9, lr, r9 + moveq r3, ip, lsr #3 + str r9, [sp, #12] + addeq sl, r1, r3, asl #1 + add r9, fp, lr, asl #2 + streq r1, [sp, #0] + bne .L4814 + tst r7, #128 + bne .L4815 +.L4056: + and r1, ip, #255 + and r3, r6, #7 + mov r2, r7, asl #12 + mov r3, r3, asl #2 + rsb fp, r1, #256 + and r2, r2, #49152 + ldr r1, [sp, #12] + add r2, r2, r3 + mov r3, r3, asl #1 + cmp r1, fp + rsb r3, r3, #28 + add r0, r2, r0 + str r3, [sp, #8] + and r1, ip, #7 + bls .L4816 + cmp r1, #0 + moveq r4, r1 + beq .L4636 + ldrh ip, [sl, #0] + rsb r4, r1, #8 + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov lr, r3, asl #4 + add r3, r0, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + bne .L4817 + cmp r4, #0 + ldr r2, [r3, #0] + beq .L4641 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov ip, #0 + mov r2, r9 +.L4650: + ands r3, r1, #15 + orr r3, r8, r3 + orr r3, lr, r3 + add ip, ip, #1 + strne r3, [r2, #0] + streq r5, [r2, #0] + cmp r4, ip + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L4650 + add r9, r9, r4, asl #2 +.L4641: + add sl, sl, #2 +.L4636: + rsb r3, r4, fp + movs r1, r3, lsr #3 + beq .L4656 + mov r4, r9 + mov r7, #0 + b .L4658 +.L4818: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4689 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + streq r5, [r4, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + streq r5, [r4, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] +.L4688: + add r7, r7, #1 + cmp r1, r7 + add r4, r4, #32 + beq .L4714 +.L4819: + add sl, sl, #2 +.L4658: + ldrh ip, [sl, #0] + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov r6, r3, asl #4 + add r3, r0, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + bne .L4818 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4689 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + streq r5, [r4, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + streq r5, [r4, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + bne .L4688 + str r5, [r4, #28] +.L4836: + add r7, r7, #1 + cmp r1, r7 + add r4, r4, #32 + bne .L4819 +.L4714: + add r9, r9, r1, asl #5 +.L4656: + ldr r3, [sp, #12] + rsb lr, fp, r3 + movs r1, lr, lsr #3 + ldreq r1, [sp, #0] + beq .L4718 + ldr r7, [sp, #0] + mov r4, r9 + mov sl, #0 + b .L4719 +.L4821: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4750 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + streq r5, [r4, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + streq r5, [r4, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] +.L4749: + add sl, sl, #1 + cmp r1, sl + add r4, r4, #32 + add r7, r7, #2 + beq .L4820 +.L4719: + ldrh ip, [r7, #0] + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov r6, r3, asl #4 + add r3, r0, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + bne .L4821 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4750 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + streq r5, [r4, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + streq r5, [r4, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + bne .L4749 + str r5, [r4, #28] +.L4837: + add sl, sl, #1 + cmp r1, sl + add r4, r4, #32 + add r7, r7, #2 + bne .L4719 +.L4820: + ldr r3, [sp, #0] + add r9, r9, r1, asl #5 + add r1, r3, r1, asl #1 +.L4718: + ands ip, lr, #7 + beq .L4791 + ldrh r1, [r1, #0] + mov r3, r1, asl #22 + tst r1, #2048 + mov r3, r3, lsr #22 + add r0, r0, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, r1, lsr #12 + addne r0, r0, r3 + tst r1, #1024 + mov r2, r2, asl #4 + ldreq r0, [r0, #0] + moveq r1, #0 + beq .L4786 + ldr r0, [r0, #0] + mov r1, #0 +.L4781: + movs r3, r0, lsr #28 + orr r3, r8, r3 + orr r3, r2, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp ip, r1 + mov r0, r0, asl #4 + add r9, r9, #4 + bne .L4781 +.L4791: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L4815: + and r1, ip, #255 + and r3, r6, #7 + mov r2, r7, asl #12 + mov r3, r3, asl #3 + rsb fp, r1, #256 + and r2, r2, #49152 + ldr r1, [sp, #12] + add r2, r2, r3 + mov r3, r3, asl #1 + rsb r3, r3, #56 + cmp r1, fp + add r0, r2, r0 + str r3, [sp, #4] + and r4, ip, #7 + bls .L4822 + cmp r4, #0 + moveq r2, r4 + beq .L4296 + ldrh ip, [sl, #0] + rsb r2, r4, #8 + tst ip, #2048 + mov r3, ip, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add lr, r0, r3, asl #6 + addne lr, lr, r1 + ands ip, ip, #1024 + bne .L4823 + cmp r4, #3 + bls .L4331 + cmp r2, #0 + ldr r1, [lr, #4] + beq .L4303 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov r4, ip + mov ip, r9 +.L4334: + ands r3, r1, #255 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r2, r4 + mov r1, r1, lsr #8 + add ip, ip, #4 + bne .L4334 + add r9, r9, r2, asl #2 +.L4303: + add sl, sl, #2 +.L4296: + rsb r3, r2, fp + movs r2, r3, lsr #3 + beq .L4360 + mov r4, r9 + mov r7, #0 + b .L4362 +.L4824: + ldr ip, [r6, #4] + add r7, r7, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #12] + mov r3, ip, lsr #8 + streq r5, [r4, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + mov r3, ip, lsr #16 + streq r5, [r4, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] + ldr ip, [r6, #0] + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #28] + mov r3, ip, lsr #8 + streq r5, [r4, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + mov r3, ip, lsr #16 + streq r5, [r4, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + streq r5, [r4, #20] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #16] + streq r5, [r4, #16] + cmp r2, r7 + add r4, r4, #32 + beq .L4414 +.L4825: + add sl, sl, #2 +.L4362: + ldrh ip, [sl, #0] + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + tst ip, #2048 + add r6, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r6, r6, r3 + tst ip, #1024 + bne .L4824 + ldr ip, [r6, #0] + add r7, r7, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #0] + mov r3, ip, lsr #8 + streq r5, [r4, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + mov r3, ip, lsr #16 + streq r5, [r4, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + streq r5, [r4, #8] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #12] + streq r5, [r4, #12] + ldr ip, [r6, #4] + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #16] + mov r3, ip, lsr #8 + streq r5, [r4, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + mov r3, ip, lsr #16 + streq r5, [r4, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #28] + streq r5, [r4, #28] + cmp r2, r7 + add r4, r4, #32 + bne .L4825 +.L4414: + add r9, r9, r2, asl #5 +.L4360: + ldr ip, [sp, #12] + rsb r2, fp, ip + movs r1, r2, lsr #3 + ldreq r1, [sp, #0] + beq .L4418 + ldr r7, [sp, #0] + mov r4, r9 + mov sl, #0 + b .L4419 +.L4827: + ldr ip, [r6, #4] + add sl, sl, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #12] + mov r3, ip, lsr #8 + streq r5, [r4, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + mov r3, ip, lsr #16 + streq r5, [r4, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] + ldr ip, [r6, #0] + add r7, r7, #2 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #28] + mov r3, ip, lsr #8 + streq r5, [r4, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + mov r3, ip, lsr #16 + streq r5, [r4, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + streq r5, [r4, #20] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #16] + streq r5, [r4, #16] + cmp r1, sl + add r4, r4, #32 + beq .L4826 +.L4419: + ldrh ip, [r7, #0] + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + tst ip, #2048 + add r6, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r6, r6, r3 + tst ip, #1024 + bne .L4827 + ldr ip, [r6, #0] + add sl, sl, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #0] + mov r3, ip, lsr #8 + streq r5, [r4, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + mov r3, ip, lsr #16 + streq r5, [r4, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + streq r5, [r4, #8] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #12] + streq r5, [r4, #12] + ldr ip, [r6, #4] + add r7, r7, #2 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #16] + mov r3, ip, lsr #8 + streq r5, [r4, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + mov r3, ip, lsr #16 + streq r5, [r4, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #28] + streq r5, [r4, #28] + cmp r1, sl + add r4, r4, #32 + bne .L4419 +.L4826: + ldr ip, [sp, #0] + add r9, r9, r1, asl #5 + add r1, ip, r1, asl #1 +.L4418: + ands ip, r2, #7 + beq .L4791 + ldrh r1, [r1, #0] + tst r1, #2048 + mov r3, r1, asl #22 + ldrne r2, [sp, #4] + mov r3, r3, lsr #22 + add r0, r0, r3, asl #6 + addne r0, r0, r2 + tst r1, #1024 + beq .L4475 + cmp ip, #3 + ldrls r0, [r0, #4] + bhi .L4828 +.L4492: + mov r1, #0 +.L4493: + movs r3, r0, lsr #24 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r1, ip + mov r0, r0, asl #8 + add r9, r9, #4 + bcc .L4493 + b .L4791 +.L4814: + cmp ip, #255 + subhi ip, ip, #256 + movhi r3, ip, lsr #3 + movls r3, ip, lsr #3 + addhi r3, r1, r3, asl #1 + addls sl, r1, r3, asl #1 + addls r1, r1, #2048 + addhi sl, r3, #2048 + strhi r1, [sp, #0] + strls r1, [sp, #0] + tst r7, #128 + beq .L4056 + b .L4815 +.L4813: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_text_base_color32 +.L4816: + cmp r1, #0 + beq .L4521 + ldr r2, [sp, #12] + rsb r4, r1, #8 + cmp r2, r4 + bcc .L4829 + ldrh ip, [sl, #0] + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov lr, r3, asl #4 + add r3, r0, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + beq .L4543 + cmp r4, #0 + ldr r2, [r3, #0] + beq .L4545 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov ip, #0 + mov r2, r9 +.L4547: + movs r3, r1, lsr #28 + orr r3, r8, r3 + orr r3, lr, r3 + add ip, ip, #1 + strne r3, [r2, #0] + streq r5, [r2, #0] + cmp r4, ip + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L4547 +.L4806: + add r9, r9, r4, asl #2 +.L4545: + ldr r3, [sp, #12] + add sl, sl, #2 + rsb r3, r4, r3 + str r3, [sp, #12] +.L4521: + ldr ip, [sp, #12] + movs fp, ip, lsr #3 + beq .L4560 + mov r4, r9 + mov r7, sl + mov lr, #0 + b .L4562 +.L4831: + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4593 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, r2, lsr #4 + streq r5, [r4, #28] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, r2, lsr #8 + streq r5, [r4, #24] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #12 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #16 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #20 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #24 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] +.L4592: + add lr, lr, #1 + cmp fp, lr + add r4, r4, #32 + add r7, r7, #2 + beq .L4830 +.L4562: + ldrh ip, [r7, #0] + tst ip, #2048 + mov r2, ip, asl #22 + mov r3, ip, lsr #12 + ldrne r1, [sp, #8] + mov r2, r2, lsr #22 + mov r6, r3, asl #4 + add r3, r0, r2, asl #5 + addne r3, r3, r1 + tst ip, #1024 + bne .L4831 + ldr r2, [r3, #0] + cmp r2, #0 + beq .L4593 + ands r3, r2, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #4 + streq r5, [r4, #0] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #8 + streq r5, [r4, #4] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #12 + streq r5, [r4, #8] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #16 + streq r5, [r4, #12] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, r2, lsr #20 + streq r5, [r4, #16] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, r2, lsr #24 + streq r5, [r4, #20] + ands r3, r3, #15 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, r2, lsr #28 + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + bne .L4592 + str r5, [r4, #28] +.L4838: + add lr, lr, #1 + cmp fp, lr + add r4, r4, #32 + add r7, r7, #2 + bne .L4562 +.L4830: + add r9, r9, fp, asl #5 + add sl, sl, fp, asl #1 +.L4560: + ldr r2, [sp, #12] + ands r4, r2, #7 + beq .L4791 + ldrh ip, [sl, #0] + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + tst ip, #2048 + add r0, r0, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, ip, lsr #12 + addne r0, r0, r3 + tst ip, #1024 + mov r2, r2, asl #4 + ldreq r0, [r0, #0] + moveq r1, #0 + beq .L4629 + ldr r0, [r0, #0] + mov r1, #0 +.L4624: + movs r3, r0, lsr #28 + orr r3, r8, r3 + orr r3, r2, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r4, r1 + mov r0, r0, asl #4 + add r9, r9, #4 + bne .L4624 + b .L4791 +.L4822: + cmp r4, #0 + beq .L4060 + rsb lr, r4, #8 + cmp r1, lr + bcc .L4832 + ldrh ip, [sl, #0] + tst ip, #2048 + mov r3, ip, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add r2, r0, r3, asl #6 + addne r2, r2, r1 + ands ip, ip, #1024 + beq .L4131 + cmp r4, #3 + bls .L4133 + cmp lr, #0 + ldr r2, [r2, #0] + beq .L4135 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov ip, r9 + mov r4, #0 +.L4137: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp lr, r4 + mov r1, r1, asl #8 + add ip, ip, #4 + bne .L4137 +.L4793: + add r9, r9, lr, asl #2 +.L4135: + ldr r2, [sp, #12] + add sl, sl, #2 + rsb r2, lr, r2 + str r2, [sp, #12] +.L4060: + ldr r3, [sp, #12] + movs r2, r3, lsr #3 + beq .L4192 + mov r4, r9 + mov r7, sl + mov fp, #0 + b .L4194 +.L4841: + .align 2 +.L4840: + .word io_registers + .word map_widths + .word vram +.L4834: + ldr ip, [r6, #4] + add fp, fp, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #12] + mov r3, ip, lsr #8 + streq r5, [r4, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + mov r3, ip, lsr #16 + streq r5, [r4, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + streq r5, [r4, #4] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #0] + streq r5, [r4, #0] + ldr ip, [r6, #0] + add r7, r7, #2 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #28] + mov r3, ip, lsr #8 + streq r5, [r4, #28] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + mov r3, ip, lsr #16 + streq r5, [r4, #24] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + streq r5, [r4, #20] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #16] + streq r5, [r4, #16] + cmp r2, fp + add r4, r4, #32 + beq .L4833 +.L4194: + ldrh ip, [r7, #0] + tst ip, #2048 + mov r3, ip, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add r6, r0, r3, asl #6 + addne r6, r6, r1 + tst ip, #1024 + bne .L4834 + ldr ip, [r6, #0] + add fp, fp, #1 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #0] + mov r3, ip, lsr #8 + streq r5, [r4, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #4] + mov r3, ip, lsr #16 + streq r5, [r4, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #8] + streq r5, [r4, #8] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #12] + streq r5, [r4, #12] + ldr ip, [r6, #4] + add r7, r7, #2 + ands r3, ip, #255 + orrne r3, r8, r3 + strne r3, [r4, #16] + mov r3, ip, lsr #8 + streq r5, [r4, #16] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #20] + mov r3, ip, lsr #16 + streq r5, [r4, #20] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r4, #24] + streq r5, [r4, #24] + movs r3, ip, lsr #24 + orrne r3, r8, r3 + strne r3, [r4, #28] + streq r5, [r4, #28] + cmp r2, fp + add r4, r4, #32 + bne .L4194 +.L4833: + add r9, r9, r2, asl #5 + add sl, sl, r2, asl #1 +.L4192: + ldr r2, [sp, #12] + ands r4, r2, #7 + beq .L4791 + ldrh ip, [sl, #0] + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + tst ip, #2048 + add r0, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r0, r0, r3 + tst ip, #1024 + bne .L4835 + cmp r4, #3 + ldrls r0, [r0, #0] + bls .L4288 + ldr r1, [r0, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r9, #0] + mov r3, r1, lsr #8 + streq r5, [r9, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + mov r3, r1, lsr #16 + streq r5, [r9, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + streq r5, [r9, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #12] + streq r5, [r9, #12] + subs r4, r4, #4 + ldr r0, [r0, #4] + addne r9, r9, #16 + beq .L4791 +.L4288: + mov r1, #0 +.L4289: + ands r3, r0, #255 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r4, r1 + mov r0, r0, lsr #8 + add r9, r9, #4 + bhi .L4289 + b .L4791 +.L4689: + str r5, [r4, #0] + str r5, [r4, #4] + str r5, [r4, #8] + str r5, [r4, #12] + str r5, [r4, #16] + str r5, [r4, #20] + str r5, [r4, #24] + str r5, [r4, #28] + b .L4836 +.L4750: + str r5, [r4, #0] + str r5, [r4, #4] + str r5, [r4, #8] + str r5, [r4, #12] + str r5, [r4, #16] + str r5, [r4, #20] + str r5, [r4, #24] + str r5, [r4, #28] + b .L4837 +.L4786: + ands r3, r0, #15 + orr r3, r8, r3 + orr r3, r2, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp ip, r1 + mov r0, r0, lsr #4 + add r9, r9, #4 + bne .L4786 + b .L4791 +.L4593: + str r5, [r4, #0] + str r5, [r4, #4] + str r5, [r4, #8] + str r5, [r4, #12] + str r5, [r4, #16] + str r5, [r4, #20] + str r5, [r4, #24] + str r5, [r4, #28] + b .L4838 +.L4629: + ands r3, r0, #15 + orr r3, r8, r3 + orr r3, r2, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r4, r1 + mov r0, r0, lsr #4 + add r9, r9, #4 + bne .L4629 + b .L4791 +.L4475: + cmp ip, #3 + ldrls r0, [r0, #0] + bhi .L4839 +.L4513: + mov r1, #0 +.L4514: + ands r3, r0, #255 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp ip, r1 + mov r0, r0, lsr #8 + add r9, r9, #4 + bhi .L4514 + b .L4791 +.L4835: + cmp r4, #3 + ldrls r0, [r0, #4] + bls .L4267 + ldr r1, [r0, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r9, #12] + mov r3, r1, lsr #8 + streq r5, [r9, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + mov r3, r1, lsr #16 + streq r5, [r9, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + streq r5, [r9, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #0] + streq r5, [r9, #0] + subs r4, r4, #4 + ldr r0, [r0, #0] + addne r9, r9, #16 + beq .L4791 +.L4267: + mov r1, #0 +.L4268: + movs r3, r0, lsr #24 + orr r3, r8, r3 + add r1, r1, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r4, r1 + mov r0, r0, asl #8 + add r9, r9, #4 + bhi .L4268 + b .L4791 +.L4823: + cmp r4, #3 + bls .L4301 + cmp r2, #0 + ldr r1, [lr, #0] + beq .L4303 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, r9 + mov r4, #0 +.L4305: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r2, r4 + mov r1, r1, asl #8 + add ip, ip, #4 + bne .L4305 + add r9, r9, r2, asl #2 + b .L4303 +.L4817: + cmp r4, #0 + ldr r2, [r3, #0] + beq .L4641 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + mov ip, #0 + mov r2, r9 +.L4643: + movs r3, r1, lsr #28 + orr r3, r8, r3 + orr r3, lr, r3 + add ip, ip, #1 + strne r3, [r2, #0] + streq r5, [r2, #0] + cmp r4, ip + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L4643 + add r9, r9, r4, asl #2 + b .L4641 +.L4829: + ldrh ip, [sl, #0] + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + tst ip, #2048 + add r0, r0, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, ip, lsr #12 + addne r0, r0, r3 + tst ip, #1024 + mov r2, r2, asl #4 + beq .L4527 + ldr ip, [sp, #12] + ldr r0, [r0, #0] + cmp ip, #0 + beq .L4791 + mov r3, r1, asl #2 + mov r0, r0, asl r3 + mov r1, #0 +.L4530: + movs r3, r0, lsr #28 + orr r3, r8, r3 + orr r3, r2, r3 + strne r3, [r9, #0] + ldr r3, [sp, #12] + add r1, r1, #1 + streq r5, [r9, #0] + cmp r3, r1 + mov r0, r0, asl #4 + add r9, r9, #4 + bne .L4530 + b .L4791 +.L4832: + ldrh ip, [sl, #0] + tst ip, #2048 + mov r3, ip, asl #22 + ldrne r2, [sp, #4] + mov r3, r3, lsr #22 + add r0, r0, r3, asl #6 + addne r0, r0, r2 + tst ip, #1024 + beq .L4066 + cmp r4, #3 + bls .L4068 + ldr r3, [sp, #12] + ldr r0, [r0, #0] + cmp r3, #0 + beq .L4791 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, asl r3 + mov r2, #0 +.L4072: + movs r3, r0, lsr #24 + ldr ip, [sp, #12] + orr r3, r8, r3 + add r2, r2, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp ip, r2 + mov r0, r0, asl #8 + add r9, r9, #4 + bne .L4072 + b .L4791 +.L4839: + ldr r1, [r0, #0] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r9, #0] + mov r3, r1, lsr #8 + streq r5, [r9, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + mov r3, r1, lsr #16 + streq r5, [r9, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + streq r5, [r9, #8] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #12] + streq r5, [r9, #12] + subs ip, ip, #4 + ldr r0, [r0, #4] + addne r9, r9, #16 + bne .L4513 + b .L4791 +.L4828: + ldr r1, [r0, #4] + ands r3, r1, #255 + orrne r3, r8, r3 + strne r3, [r9, #12] + mov r3, r1, lsr #8 + streq r5, [r9, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + mov r3, r1, lsr #16 + streq r5, [r9, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + streq r5, [r9, #4] + movs r3, r1, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #0] + streq r5, [r9, #0] + subs ip, ip, #4 + ldr r0, [r0, #0] + addne r9, r9, #16 + bne .L4492 + b .L4791 +.L4066: + cmp r4, #3 + bls .L4099 + ldr ip, [sp, #12] + ldr r0, [r0, #4] + cmp ip, #0 + beq .L4791 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r0, r0, lsr r3 + mov r2, #0 +.L4102: + ands r3, r0, #255 + ldr r1, [sp, #12] + orr r3, r8, r3 + add r2, r2, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r1, r2 + mov r0, r0, lsr #8 + add r9, r9, #4 + bne .L4102 + b .L4791 +.L4131: + cmp r4, #3 + bls .L4163 + cmp lr, #0 + ldr r2, [r2, #4] + beq .L4135 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, ip + mov ip, r9 +.L4166: + ands r3, r1, #255 + orr r3, r8, r3 + add r2, r2, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp lr, r2 + mov r1, r1, lsr #8 + add ip, ip, #4 + bne .L4166 + b .L4793 +.L4301: + subs r6, r2, #4 + ldr r1, [lr, #4] + beq .L4311 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, r9 + mov r4, #0 +.L4313: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r6, r4 + mov r1, r1, asl #8 + add ip, ip, #4 + bne .L4313 + add r3, r9, r2, asl #2 + sub r9, r3, #16 +.L4311: + ldr r2, [lr, #0] + ands r3, r2, #255 + orrne r3, r8, r3 + strne r3, [r9, #12] + mov r3, r2, lsr #8 + streq r5, [r9, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + mov r3, r2, lsr #16 + streq r5, [r9, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + streq r5, [r9, #4] + movs r3, r2, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #0] + streq r5, [r9, #0] +.L4359: + add r9, r9, #16 + mov r2, r6 + add sl, sl, #2 + b .L4296 +.L4331: + subs r6, r2, #4 + ldr r1, [lr, #0] + beq .L4340 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov ip, r9 + mov r4, #0 +.L4342: + ands r3, r1, #255 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r6, r4 + mov r1, r1, lsr #8 + add ip, ip, #4 + bne .L4342 + add r3, r9, r2, asl #2 + sub r9, r3, #16 +.L4340: + ldr r2, [lr, #4] + ands r3, r2, #255 + orrne r3, r8, r3 + strne r3, [r9, #0] + mov r3, r2, lsr #8 + streq r5, [r9, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + mov r3, r2, lsr #16 + streq r5, [r9, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + streq r5, [r9, #8] + movs r3, r2, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #12] + streq r5, [r9, #12] + b .L4359 +.L4527: + ldr ip, [sp, #12] + ldr r0, [r0, #0] + cmp ip, #0 + beq .L4791 + mov r3, r1, asl #2 + mov r0, r0, lsr r3 + mov r1, #0 +.L4536: + ands r3, r0, #15 + orr r3, r8, r3 + orr r3, r2, r3 + strne r3, [r9, #0] + ldr r3, [sp, #12] + add r1, r1, #1 + streq r5, [r9, #0] + cmp r3, r1 + mov r0, r0, lsr #4 + add r9, r9, #4 + bne .L4536 + b .L4791 +.L4543: + cmp r4, #0 + ldr r2, [r3, #0] + beq .L4545 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + mov ip, #0 + mov r2, r9 +.L4554: + ands r3, r1, #15 + orr r3, r8, r3 + orr r3, lr, r3 + add ip, ip, #1 + strne r3, [r2, #0] + streq r5, [r2, #0] + cmp r4, ip + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L4554 + b .L4806 +.L4068: + ldr ip, [sp, #12] + mov r3, r4, asl #3 + ldr r1, [r0, #4] + add r2, ip, r4 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L4077 + cmp ip, #0 + movne r2, #0 + beq .L4791 +.L4094: + movs r3, r1, lsr #24 + orr r3, r8, r3 + strne r3, [r9, #0] + ldr r3, [sp, #12] + add r2, r2, #1 + streq r5, [r9, #0] + cmp r3, r2 + mov r1, r1, asl #8 + add r9, r9, #4 + bne .L4094 + b .L4791 +.L4163: + subs r6, lr, #4 + ldr r1, [r2, #0] + beq .L4172 + mov r3, r4, asl #3 + mov r1, r1, lsr r3 + mov ip, r9 + mov r4, #0 +.L4174: + ands r3, r1, #255 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r6, r4 + mov r1, r1, lsr #8 + add ip, ip, #4 + bne .L4174 + add r3, r9, lr, asl #2 + sub r9, r3, #16 +.L4172: + ldr r2, [r2, #4] + ands r3, r2, #255 + orrne r3, r8, r3 + strne r3, [r9, #0] + mov r3, r2, lsr #8 + streq r5, [r9, #0] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + mov r3, r2, lsr #16 + streq r5, [r9, #4] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + streq r5, [r9, #8] + movs r3, r2, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #12] + streq r5, [r9, #12] +.L4191: + add r9, r9, #16 + b .L4135 +.L4133: + subs r6, lr, #4 + ldr r1, [r2, #4] + beq .L4143 + mov r3, r4, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, r9 + mov r4, #0 +.L4145: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add r4, r4, #1 + strne r3, [ip, #0] + streq r5, [ip, #0] + cmp r6, r4 + mov r1, r1, asl #8 + add ip, ip, #4 + bne .L4145 + add r3, r9, lr, asl #2 + sub r9, r3, #16 +.L4143: + ldr r2, [r2, #0] + ands r3, r2, #255 + orrne r3, r8, r3 + strne r3, [r9, #12] + mov r3, r2, lsr #8 + streq r5, [r9, #12] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #8] + mov r3, r2, lsr #16 + streq r5, [r9, #8] + ands r3, r3, #255 + orrne r3, r8, r3 + strne r3, [r9, #4] + streq r5, [r9, #4] + movs r3, r2, lsr #24 + orrne r3, r8, r3 + strne r3, [r9, #0] + streq r5, [r9, #0] + add r9, r9, #16 + b .L4135 +.L4099: + ldr ip, [sp, #12] + ldr r3, [r0, #0] + add r2, ip, r4 + cmp r2, #4 + mov r1, r4, asl #3 + mov r2, r3, lsr r1 + bhi .L4107 + cmp ip, #0 + movne r1, #0 + beq .L4791 +.L4124: + ands r3, r2, #255 + orr r3, r8, r3 + strne r3, [r9, #0] + ldr r3, [sp, #12] + add r1, r1, #1 + streq r5, [r9, #0] + cmp r3, r1 + mov r2, r2, lsr #8 + add r9, r9, #4 + bne .L4124 + b .L4791 +.L4077: + rsbs r4, r4, #4 + beq .L4080 + mov r2, r9 + mov ip, #0 +.L4082: + movs r3, r1, lsr #24 + orr r3, r8, r3 + add ip, ip, #1 + strne r3, [r2, #0] + streq r5, [r2, #0] + cmp r4, ip + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L4082 + add r9, r9, r4, asl #2 +.L4080: + ldr r2, [sp, #12] + ldr r0, [r0, #0] + subs r1, r2, r4 + beq .L4791 + mov r2, #0 +.L4089: + movs r3, r0, lsr #24 + orr r3, r8, r3 + add r2, r2, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r1, r2 + mov r0, r0, asl #8 + add r9, r9, #4 + bne .L4089 + b .L4791 +.L4107: + rsbs r4, r4, #4 + beq .L4110 + mov r1, r9 + mov ip, #0 +.L4112: + ands r3, r2, #255 + orr r3, r8, r3 + add ip, ip, #1 + strne r3, [r1, #0] + streq r5, [r1, #0] + cmp r4, ip + mov r2, r2, lsr #8 + add r1, r1, #4 + bne .L4112 + add r9, r9, r4, asl #2 +.L4110: + ldr r2, [sp, #12] + ldr r0, [r0, #4] + subs r1, r2, r4 + beq .L4791 + mov r2, #0 +.L4119: + ands r3, r0, #255 + orr r3, r8, r3 + add r2, r2, #1 + strne r3, [r9, #0] + streq r5, [r9, #0] + cmp r1, r2 + mov r0, r0, lsr #8 + add r9, r9, #4 + bne .L4119 + b .L4791 + .size render_scanline_text_base_alpha, .-render_scanline_text_base_alpha + .align 2 + .global render_scanline_text_transparent_alpha + .type render_scanline_text_transparent_alpha, %function +render_scanline_text_transparent_alpha: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5485 + add lr, r0, #7 + ldrh ip, [r5, #80] + sub sp, sp, #16 + mov lr, ip, asr lr + mov ip, ip, asr r0 + and lr, lr, #2 + and ip, ip, #1 + orr ip, ip, lr + mov r6, ip, asl #9 + tst r6, #512 + mov r4, r0 + mov ip, r1 + mov r8, r2 + mov sl, r3 + beq .L5463 + add r0, r5, r0, asl #2 + ldrh r1, [r5, #6] + ldrh r3, [r0, #18] + add r2, r5, r4, asl #1 + add r7, r1, r3 + ldrh r3, [r0, #16] + ldrh lr, [r2, #8] + mov r5, r7, asl #23 + mov r5, r5, lsr #23 + add r3, r3, ip + mov r0, lr, lsr #14 + cmp r5, #255 + movls r1, #0 + movhi r1, #1 + mov r4, r3, asl #23 + ldr r3, .L5485+4 + ands r1, r1, r0, lsr #1 + mov r2, lr, asl #3 + ldr r1, [r3, r0, asl #2] + ldr r9, .L5485+8 + subne r3, r5, #256 + movne r3, r3, lsr #3 + moveq r3, r7, asl #3 + and r2, r2, #63488 + addne r3, r3, r1, lsr #3 + andeq r3, r3, #1984 + add r2, r2, r9 + addne r1, r2, r3, asl #6 + addeq r1, r2, r3 + mov r4, r4, lsr #23 + tst r0, #1 + andeq r4, r4, #255 + moveq r3, r4, lsr #3 + rsb fp, ip, r8 + addeq r7, r1, r3, asl #1 + add r8, sl, ip, asl #2 + streq r1, [sp, #0] + bne .L5464 + tst lr, #128 + bne .L5465 +.L4853: + mov r2, lr, asl #12 + and r3, r5, #7 + mov r3, r3, asl #2 + and r1, r4, #255 + and r2, r2, #49152 + rsb r1, r1, #256 + add r2, r2, r3 + mov r3, r3, asl #1 + cmp fp, r1 + rsb r3, r3, #28 + str r1, [sp, #12] + add lr, r2, r9 + str r3, [sp, #8] + and r1, r4, #7 + bls .L5466 + cmp r1, #0 + moveq r5, r1 + beq .L5329 + ldrh ip, [r7, #0] + rsb r5, r1, #8 + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov r0, r3, asl #4 + add r3, lr, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + bne .L5467 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L5334 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + orr r0, r6, r0 + mov r2, r8 + mov ip, #0 +.L5342: + ands r4, r1, #15 + ldrne r3, [r2, #0] + add ip, ip, #1 + orrne r3, r4, r3, asl #16 + orrne r3, r3, r0 + strne r3, [r2, #0] + cmp r5, ip + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L5342 + add r8, r8, r5, asl #2 +.L5334: + add r7, r7, #2 +.L5329: + ldr r1, [sp, #12] + rsb r3, r5, r1 + movs sl, r3, lsr #3 + beq .L5347 + mov r4, r8 + mov ip, #0 + b .L5349 +.L5468: + ldr r1, [r3, #0] + cmp r1, #0 + beq .L5354 + ands r0, r1, #15 + ldrne r3, [r4, #28] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #28] + mov r3, r1, lsr #4 + ands r0, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + mov r3, r1, lsr #8 + ands r0, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r1, lsr #12 + ands r0, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r1, lsr #16 + ands r0, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r1, lsr #20 + ands r0, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r1, lsr #24 + ands r0, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + movs r1, r1, lsr #28 + beq .L5354 + ldr r3, [r4, #0] + orr r2, r6, r5 + orr r3, r1, r3, asl #16 + orr r3, r3, r2 + str r3, [r4, #0] +.L5354: + add ip, ip, #1 + cmp sl, ip + add r4, r4, #32 + beq .L5387 +.L5469: + add r7, r7, #2 +.L5349: + ldrh r1, [r7, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r5, r3, asl #4 + add r3, lr, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L5468 + ldr r1, [r3, #0] + cmp r1, #0 + beq .L5354 + ands r0, r1, #15 + ldrne r3, [r4, #0] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #0] + mov r3, r1, lsr #4 + ands r0, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + mov r3, r1, lsr #8 + ands r0, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r1, lsr #12 + ands r0, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r1, lsr #16 + ands r0, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r1, lsr #20 + ands r0, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r1, lsr #24 + ands r0, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + movs r1, r1, lsr #28 + ldrne r3, [r4, #28] + orrne r2, r6, r5 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + add ip, ip, #1 + strne r3, [r4, #28] + cmp sl, ip + add r4, r4, #32 + bne .L5469 +.L5387: + add r8, r8, sl, asl #5 +.L5347: + ldr r3, [sp, #12] + rsb r9, r3, fp + movs sl, r9, lsr #3 + ldreq r1, [sp, #0] + beq .L5391 + ldr ip, [sp, #0] + mov r4, r8 + mov r7, #0 + b .L5392 +.L5471: + ldr r1, [r3, #0] + cmp r1, #0 + beq .L5397 + ands r0, r1, #15 + ldrne r3, [r4, #28] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #28] + mov r3, r1, lsr #4 + ands r0, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + mov r3, r1, lsr #8 + ands r0, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r1, lsr #12 + ands r0, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r1, lsr #16 + ands r0, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r1, lsr #20 + ands r0, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r1, lsr #24 + ands r0, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + movs r1, r1, lsr #28 + beq .L5397 + ldr r3, [r4, #0] + orr r2, r6, r5 + orr r3, r1, r3, asl #16 + orr r3, r3, r2 + str r3, [r4, #0] +.L5397: + add r7, r7, #1 + cmp sl, r7 + add r4, r4, #32 + add ip, ip, #2 + beq .L5470 +.L5392: + ldrh r1, [ip, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r5, r3, asl #4 + add r3, lr, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L5471 + ldr r1, [r3, #0] + cmp r1, #0 + beq .L5397 + ands r0, r1, #15 + ldrne r3, [r4, #0] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #0] + mov r3, r1, lsr #4 + ands r0, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + mov r3, r1, lsr #8 + ands r0, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r1, lsr #12 + ands r0, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r1, lsr #16 + ands r0, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r1, lsr #20 + ands r0, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r1, lsr #24 + ands r0, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r5 + orrne r3, r0, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + movs r1, r1, lsr #28 + ldrne r3, [r4, #28] + orrne r2, r6, r5 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + add r7, r7, #1 + strne r3, [r4, #28] + cmp sl, r7 + add r4, r4, #32 + add ip, ip, #2 + bne .L5392 +.L5470: + ldr r3, [sp, #0] + add r8, r8, sl, asl #5 + add r1, r3, sl, asl #1 +.L5391: + ands r4, r9, #7 + beq .L5444 + ldrh r1, [r1, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, lr, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, r1, lsr #12 + addne r0, r0, r3 + mov r2, r2, asl #4 + tst r1, #1024 + ldreq r0, [r0, #0] + orreq r2, r6, r2 + moveq lr, #0 + beq .L5440 + ldr r0, [r0, #0] + orr r2, r6, r2 + mov lr, #0 +.L5436: + movs r1, r0, lsr #28 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp r4, lr + mov r0, r0, asl #4 + add r8, r8, #4 + bne .L5436 +.L5444: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5465: + and r3, r5, #7 + mov r2, lr, asl #12 + mov r3, r3, asl #3 + and r1, r4, #255 + and r2, r2, #49152 + add r2, r2, r3 + rsb sl, r1, #256 + mov r3, r3, asl #1 + rsb r3, r3, #56 + cmp fp, sl + add r0, r2, r9 + str r3, [sp, #4] + and ip, r4, #7 + bls .L5472 + cmp ip, #0 + moveq lr, ip + beq .L5055 + ldrh r2, [r7, #0] + rsb lr, ip, #8 + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + ands r2, r2, #1024 + bne .L5473 + cmp ip, #3 + bls .L5085 + cmp lr, #0 + ldr r1, [r5, #4] + beq .L5062 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov r4, r2 + mov r2, r8 +.L5088: + ands r3, r1, #255 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp lr, r4 + mov r1, r1, lsr #8 + add r2, r2, #4 + bne .L5088 + add r8, r8, lr, asl #2 +.L5062: + add r7, r7, #2 +.L5055: + rsb r3, lr, sl + movs lr, r3, lsr #3 + beq .L5109 + mov r4, r8 + mov ip, #0 + b .L5111 +.L5474: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L5116 + ands r3, r1, #255 + ldrne r2, [r4, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #4] + movs r3, r1, lsr #24 + ldrne r2, [r4, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #0] +.L5116: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L5125 + ands r3, r1, #255 + ldrne r2, [r4, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #20] + movs r3, r1, lsr #24 + ldrne r2, [r4, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #16] +.L5125: + add ip, ip, #1 + cmp lr, ip + add r4, r4, #32 + beq .L5151 +.L5475: + add r7, r7, #2 +.L5111: + ldrh r2, [r7, #0] + tst r2, #2048 + mov r3, r2, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add r5, r0, r3, asl #6 + addne r5, r5, r1 + tst r2, #1024 + bne .L5474 + ldr r1, [r5, #0] + cmp r1, #0 + beq .L5134 + ands r3, r1, #255 + ldrne r2, [r4, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #8] + movs r3, r1, lsr #24 + ldrne r2, [r4, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #12] +.L5134: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L5125 + ands r3, r1, #255 + ldrne r2, [r4, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #16] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #20] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #24] + movs r3, r1, lsr #24 + ldrne r2, [r4, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + add ip, ip, #1 + strne r3, [r4, #28] + cmp lr, ip + add r4, r4, #32 + bne .L5475 +.L5151: + add r8, r8, lr, asl #5 +.L5109: + rsb lr, sl, fp + movs sl, lr, lsr #3 + ldreq r1, [sp, #0] + beq .L5155 + ldr ip, [sp, #0] + mov r4, r8 + mov r7, #0 + b .L5156 +.L5477: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L5161 + ands r3, r1, #255 + ldrne r2, [r4, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #4] + movs r3, r1, lsr #24 + ldrne r2, [r4, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #0] +.L5161: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L5170 + ands r3, r1, #255 + ldrne r2, [r4, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #20] + movs r3, r1, lsr #24 + ldrne r2, [r4, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #16] +.L5170: + add r7, r7, #1 + cmp sl, r7 + add r4, r4, #32 + add ip, ip, #2 + beq .L5476 +.L5156: + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r2, #1024 + bne .L5477 + ldr r1, [r5, #0] + cmp r1, #0 + beq .L5179 + ands r3, r1, #255 + ldrne r2, [r4, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #8] + movs r3, r1, lsr #24 + ldrne r2, [r4, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #12] +.L5179: + ldr r1, [r5, #4] + cmp r1, #0 + beq .L5170 + ands r3, r1, #255 + ldrne r2, [r4, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #16] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r4, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #20] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r4, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r4, #24] + movs r3, r1, lsr #24 + ldrne r2, [r4, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + add r7, r7, #1 + strne r3, [r4, #28] + cmp sl, r7 + add r4, r4, #32 + add ip, ip, #2 + bne .L5156 +.L5476: + ldr r2, [sp, #0] + add r8, r8, sl, asl #5 + add r1, r2, sl, asl #1 +.L5155: + ands ip, lr, #7 + beq .L5444 + ldrh r1, [r1, #0] + mov r3, r1, asl #22 + mov r3, r3, lsr #22 + tst r1, #2048 + add r0, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r0, r0, r3 + tst r1, #1024 + beq .L5200 + cmp ip, #3 + ldrls r0, [r0, #4] + bls .L5214 + ldr r1, [r0, #4] + cmp r1, #0 + beq .L5204 + ands r3, r1, #255 + ldrne r2, [r8, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r8, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r8, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #4] + movs r3, r1, lsr #24 + ldrne r2, [r8, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #0] +.L5204: + subs ip, ip, #4 + ldr r0, [r0, #0] + addne r8, r8, #16 + beq .L5444 +.L5214: + mov r1, #0 +.L5215: + movs r3, r0, lsr #24 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, asl #8 + add r8, r8, #4 + bhi .L5215 + b .L5444 +.L5464: + cmp r4, #255 + subhi r4, r4, #256 + movhi r3, r4, lsr #3 + movls r3, r4, lsr #3 + addhi r3, r1, r3, asl #1 + addls r7, r1, r3, asl #1 + addls r1, r1, #2048 + addhi r7, r3, #2048 + strhi r1, [sp, #0] + strls r1, [sp, #0] + tst lr, #128 + beq .L4853 + b .L5465 +.L5463: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_text_transparent_color32 +.L5466: + cmp r1, #0 + beq .L5238 + rsb r5, r1, #8 + cmp fp, r5 + bcc .L5478 + ldrh ip, [r7, #0] + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + tst ip, #2048 + mov r3, ip, lsr #12 + mov r0, r3, asl #4 + add r3, lr, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst ip, #1024 + beq .L5258 + cmp r5, #0 + ldr r2, [r3, #0] + beq .L5260 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + orr r0, r6, r0 + mov r2, r8 + mov r4, #0 +.L5262: + movs ip, r1, lsr #28 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + orrne r3, r3, r0 + strne r3, [r2, #0] + cmp r5, r4 + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L5262 +.L5459: + add r8, r8, r5, asl #2 +.L5260: + rsb fp, r5, fp + add r7, r7, #2 +.L5238: + movs r9, fp, lsr #3 + beq .L5273 + mov r4, r8 + mov ip, r7 + mov sl, #0 + b .L5275 +.L5486: + .align 2 +.L5485: + .word io_registers + .word map_widths + .word vram +.L5480: + ldr r5, [r3, #0] + cmp r5, #0 + beq .L5280 + ands r1, r5, #15 + ldrne r3, [r4, #28] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #28] + mov r3, r5, lsr #4 + ands r1, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + mov r3, r5, lsr #8 + ands r1, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r5, lsr #12 + ands r1, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r5, lsr #16 + ands r1, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r5, lsr #20 + ands r1, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r5, lsr #24 + ands r1, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + movs r5, r5, lsr #28 + beq .L5280 + ldr r3, [r4, #0] + orr r2, r6, r0 + orr r3, r5, r3, asl #16 + orr r3, r3, r2 + str r3, [r4, #0] +.L5280: + add sl, sl, #1 + cmp r9, sl + add r4, r4, #32 + add ip, ip, #2 + beq .L5479 +.L5275: + ldrh r1, [ip, #0] + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + tst r1, #2048 + mov r3, r1, lsr #12 + mov r0, r3, asl #4 + add r3, lr, r2, asl #5 + ldrne r2, [sp, #8] + addne r3, r3, r2 + tst r1, #1024 + bne .L5480 + ldr r5, [r3, #0] + cmp r5, #0 + beq .L5280 + ands r1, r5, #15 + ldrne r3, [r4, #0] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #0] + mov r3, r5, lsr #4 + ands r1, r3, #15 + ldrne r3, [r4, #4] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #4] + mov r3, r5, lsr #8 + ands r1, r3, #15 + ldrne r3, [r4, #8] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #8] + mov r3, r5, lsr #12 + ands r1, r3, #15 + ldrne r3, [r4, #12] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #12] + mov r3, r5, lsr #16 + ands r1, r3, #15 + ldrne r3, [r4, #16] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #16] + mov r3, r5, lsr #20 + ands r1, r3, #15 + ldrne r3, [r4, #20] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #20] + mov r3, r5, lsr #24 + ands r1, r3, #15 + ldrne r3, [r4, #24] + orrne r2, r6, r0 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r4, #24] + movs r5, r5, lsr #28 + ldrne r3, [r4, #28] + orrne r2, r6, r0 + orrne r3, r5, r3, asl #16 + orrne r3, r3, r2 + add sl, sl, #1 + strne r3, [r4, #28] + cmp r9, sl + add r4, r4, #32 + add ip, ip, #2 + bne .L5275 +.L5479: + add r8, r8, r9, asl #5 + add r7, r7, r9, asl #1 +.L5273: + ands r5, fp, #7 + beq .L5444 + ldrh r4, [r7, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r0, lr, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, r4, lsr #12 + addne r0, r0, r3 + mov r2, r2, asl #4 + tst r4, #1024 + ldreq r0, [r0, #0] + orreq r2, r6, r2 + moveq lr, #0 + beq .L5323 + ldr r0, [r0, #0] + orr r2, r6, r2 + mov lr, #0 +.L5319: + movs r1, r0, lsr #28 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp r5, lr + mov r0, r0, asl #4 + add r8, r8, #4 + bne .L5319 + b .L5444 +.L5472: + cmp ip, #0 + beq .L4857 + rsb lr, ip, #8 + cmp fp, lr + bcc .L5481 + ldrh r2, [r7, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + ands r2, r2, #1024 + beq .L4920 + cmp ip, #3 + bls .L4922 + cmp lr, #0 + ldr r2, [r5, #0] + beq .L4924 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r4, #0 + mov r2, r8 +.L4926: + movs r3, r1, lsr #24 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp lr, r4 + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L4926 +.L5446: + add r8, r8, lr, asl #2 +.L4924: + rsb fp, lr, fp + add r7, r7, #2 +.L4857: + movs r9, fp, lsr #3 + beq .L4971 + mov r1, r8 + mov ip, r7 + mov sl, #0 + b .L4973 +.L5483: + ldr r4, [r5, #4] + cmp r4, #0 + beq .L4978 + ands r3, r4, #255 + ldrne r2, [r1, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [r1, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [r1, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #4] + movs r3, r4, lsr #24 + ldrne r2, [r1, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #0] +.L4978: + ldr r4, [r5, #0] + cmp r4, #0 + beq .L4987 + ands r3, r4, #255 + ldrne r2, [r1, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [r1, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [r1, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #20] + movs r3, r4, lsr #24 + ldrne r2, [r1, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #16] +.L4987: + add sl, sl, #1 + cmp r9, sl + add r1, r1, #32 + add ip, ip, #2 + beq .L5482 +.L4973: + ldrh r2, [ip, #0] + mov r3, r2, asl #22 + mov r3, r3, lsr #22 + tst r2, #2048 + add r5, r0, r3, asl #6 + ldrne r3, [sp, #4] + addne r5, r5, r3 + tst r2, #1024 + bne .L5483 + ldr r4, [r5, #0] + cmp r4, #0 + beq .L4996 + ands r3, r4, #255 + ldrne r2, [r1, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [r1, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [r1, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #8] + movs r3, r4, lsr #24 + ldrne r2, [r1, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #12] +.L4996: + ldr r4, [r5, #4] + cmp r4, #0 + beq .L4987 + ands r3, r4, #255 + ldrne r2, [r1, #16] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [r1, #20] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [r1, #24] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r1, #24] + movs r3, r4, lsr #24 + ldrne r2, [r1, #28] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + add sl, sl, #1 + strne r3, [r1, #28] + cmp r9, sl + add r1, r1, #32 + add ip, ip, #2 + bne .L4973 +.L5482: + add r8, r8, r9, asl #5 + add r7, r7, r9, asl #1 +.L4971: + ands ip, fp, #7 + beq .L5444 + ldrh r2, [r7, #0] + tst r2, #2048 + mov r3, r2, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add r0, r0, r3, asl #6 + addne r0, r0, r1 + tst r2, #1024 + bne .L5484 + cmp ip, #3 + ldrls r0, [r0, #0] + bls .L5048 + ldr r1, [r0, #0] + cmp r1, #0 + beq .L5038 + ands r3, r1, #255 + ldrne r2, [r8, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r8, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r8, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #8] + movs r3, r1, lsr #24 + ldrne r2, [r8, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #12] +.L5038: + subs ip, ip, #4 + ldr r0, [r0, #4] + addne r8, r8, #16 + beq .L5444 +.L5048: + mov r1, #0 +.L5049: + ands r3, r0, #255 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, lsr #8 + add r8, r8, #4 + bhi .L5049 + b .L5444 +.L5440: + ands r1, r0, #15 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp r4, lr + mov r0, r0, lsr #4 + add r8, r8, #4 + bne .L5440 + b .L5444 +.L5323: + ands r1, r0, #15 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp r5, lr + mov r0, r0, lsr #4 + add r8, r8, #4 + bne .L5323 + b .L5444 +.L5200: + cmp ip, #3 + ldrls r0, [r0, #0] + bls .L5231 + ldr r1, [r0, #0] + cmp r1, #0 + beq .L5221 + ands r3, r1, #255 + ldrne r2, [r8, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r8, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r8, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #8] + movs r3, r1, lsr #24 + ldrne r2, [r8, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #12] +.L5221: + subs ip, ip, #4 + ldr r0, [r0, #4] + addne r8, r8, #16 + beq .L5444 +.L5231: + mov r1, #0 +.L5232: + ands r3, r0, #255 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, lsr #8 + add r8, r8, #4 + bhi .L5232 + b .L5444 +.L5484: + cmp ip, #3 + ldrls r0, [r0, #4] + bls .L5031 + ldr r1, [r0, #4] + cmp r1, #0 + beq .L5021 + ands r3, r1, #255 + ldrne r2, [r8, #12] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r2, [r8, #8] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r2, [r8, #4] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #4] + movs r3, r1, lsr #24 + ldrne r2, [r8, #0] + orrne r3, r6, r3 + orrne r3, r3, r2, asl #16 + strne r3, [r8, #0] +.L5021: + subs ip, ip, #4 + ldr r0, [r0, #0] + addne r8, r8, #16 + beq .L5444 +.L5031: + mov r1, #0 +.L5032: + movs r3, r0, lsr #24 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, asl #8 + add r8, r8, #4 + bhi .L5032 + b .L5444 +.L5473: + cmp ip, #3 + bls .L5060 + cmp lr, #0 + ldr r2, [r5, #0] + beq .L5062 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r4, #0 + mov r2, r8 +.L5064: + movs r3, r1, lsr #24 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp lr, r4 + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L5064 + add r8, r8, lr, asl #2 + b .L5062 +.L5467: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L5334 + mov r3, r1, asl #2 + mov r1, r2, asl r3 + orr r0, r6, r0 + mov r2, r8 + mov ip, #0 +.L5336: + movs r4, r1, lsr #28 + ldrne r3, [r2, #0] + add ip, ip, #1 + orrne r3, r4, r3, asl #16 + orrne r3, r3, r0 + strne r3, [r2, #0] + cmp r5, ip + mov r1, r1, asl #4 + add r2, r2, #4 + bne .L5336 + add r8, r8, r5, asl #2 + b .L5334 +.L5478: + ldrh r4, [r7, #0] + mov r3, r4, asl #22 + mov r3, r3, lsr #22 + tst r4, #2048 + add r0, lr, r3, asl #5 + ldrne r3, [sp, #8] + mov r2, r4, lsr #12 + addne r0, r0, r3 + tst r4, #1024 + mov r2, r2, asl #4 + beq .L5244 + cmp fp, #0 + ldr r0, [r0, #0] + beq .L5444 + mov r3, r1, asl #2 + mov r0, r0, asl r3 + orr r2, r6, r2 + mov lr, #0 +.L5247: + movs r1, r0, lsr #28 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp fp, lr + mov r0, r0, asl #4 + add r8, r8, #4 + bne .L5247 + b .L5444 +.L5481: + ldrh r2, [r7, #0] + tst r2, #2048 + mov r3, r2, asl #22 + ldrne r1, [sp, #4] + mov r3, r3, lsr #22 + add r0, r0, r3, asl #6 + addne r0, r0, r1 + tst r2, #1024 + beq .L4863 + cmp ip, #3 + bls .L4865 + cmp fp, #0 + ldr r0, [r0, #0] + beq .L5444 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r0, r0, asl r3 + mov r1, #0 +.L4869: + movs r3, r0, lsr #24 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp fp, r1 + mov r0, r0, asl #8 + add r8, r8, #4 + bne .L4869 + b .L5444 +.L5060: + subs r9, lr, #4 + ldr r2, [r5, #4] + beq .L5069 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r4, #0 + mov r2, r8 +.L5071: + movs r3, r1, lsr #24 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp r9, r4 + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L5071 + add r3, r8, lr, asl #2 + sub r8, r3, #16 +.L5069: + ldr r2, [r5, #0] + cmp r2, #0 + beq .L5100 + ands r1, r2, #255 + ldrne r3, [r8, #12] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #12] + mov r3, r2, lsr #8 + ands r1, r3, #255 + ldrne r3, [r8, #8] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #8] + mov r3, r2, lsr #16 + ands r1, r3, #255 + ldrne r3, [r8, #4] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #4] + movs r2, r2, lsr #24 + ldrne r3, [r8, #0] + orrne r3, r6, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r8, #0] +.L5100: + add r8, r8, #16 + mov lr, r9 + add r7, r7, #2 + b .L5055 +.L5258: + cmp r5, #0 + ldr r2, [r3, #0] + beq .L5260 + mov r3, r1, asl #2 + mov r1, r2, lsr r3 + orr r0, r6, r0 + mov r2, r8 + mov r4, #0 +.L5268: + ands ip, r1, #15 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + orrne r3, r3, r0 + strne r3, [r2, #0] + cmp r5, r4 + mov r1, r1, lsr #4 + add r2, r2, #4 + bne .L5268 + b .L5459 +.L4920: + cmp ip, #3 + bls .L4947 + cmp lr, #0 + ldr r1, [r5, #4] + beq .L4924 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, lsr r3 + mov r4, r2 + mov r2, r8 +.L4950: + ands r3, r1, #255 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp lr, r4 + mov r1, r1, lsr #8 + add r2, r2, #4 + bne .L4950 + b .L5446 +.L5244: + cmp fp, #0 + ldr r0, [r0, #0] + beq .L5444 + mov r3, r1, asl #2 + mov r0, r0, lsr r3 + orr r2, r6, r2 + mov lr, #0 +.L5252: + ands r1, r0, #15 + ldrne r3, [r8, #0] + add lr, lr, #1 + orrne r3, r1, r3, asl #16 + orrne r3, r3, r2 + strne r3, [r8, #0] + cmp fp, lr + mov r0, r0, lsr #4 + add r8, r8, #4 + bne .L5252 + b .L5444 +.L4863: + cmp ip, #3 + bls .L4892 + cmp fp, #0 + ldr r0, [r0, #4] + beq .L5444 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r0, r0, lsr r3 + mov r1, #0 +.L4895: + ands r3, r0, #255 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp fp, r1 + mov r0, r0, lsr #8 + add r8, r8, #4 + bne .L4895 + b .L5444 +.L5085: + subs r9, lr, #4 + ldr r2, [r5, #0] + beq .L5093 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r4, #0 + mov r2, r8 +.L5095: + ands r3, r1, #255 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp r9, r4 + mov r1, r1, lsr #8 + add r2, r2, #4 + bne .L5095 + add r3, r8, lr, asl #2 + sub r8, r3, #16 +.L5093: + ldr r2, [r5, #4] + cmp r2, #0 + beq .L5100 + ands r1, r2, #255 + ldrne r3, [r8, #0] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #0] + mov r3, r2, lsr #8 + ands r1, r3, #255 + ldrne r3, [r8, #4] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #4] + mov r3, r2, lsr #16 + ands r1, r3, #255 + ldrne r3, [r8, #8] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #8] + movs r2, r2, lsr #24 + ldrne r3, [r8, #12] + orrne r3, r6, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r8, #12] + b .L5100 +.L4922: + subs sl, lr, #4 + ldr r2, [r5, #4] + beq .L4931 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, asl r3 + mov r4, #0 + mov r2, r8 +.L4933: + movs r3, r1, lsr #24 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp sl, r4 + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L4933 + add r3, r8, lr, asl #2 + sub r8, r3, #16 +.L4931: + ldr r2, [r5, #0] + cmp r2, #0 + beq .L4962 + ands r1, r2, #255 + ldrne r3, [r8, #12] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #12] + mov r3, r2, lsr #8 + ands r1, r3, #255 + ldrne r3, [r8, #8] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #8] + mov r3, r2, lsr #16 + ands r1, r3, #255 + ldrne r3, [r8, #4] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #4] + movs r2, r2, lsr #24 + ldrne r3, [r8, #0] + orrne r3, r6, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r8, #0] +.L4962: + add r8, r8, #16 + b .L4924 +.L4865: + mov r3, ip, asl #3 + ldr r1, [r0, #4] + add r2, fp, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L4873 + cmp fp, #0 + movne r0, #0 + beq .L5444 +.L4888: + movs r3, r1, lsr #24 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r0, r0, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp fp, r0 + mov r1, r1, asl #8 + add r8, r8, #4 + bne .L4888 + b .L5444 +.L4947: + subs sl, lr, #4 + ldr r2, [r5, #0] + beq .L4955 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r4, #0 + mov r2, r8 +.L4957: + ands r3, r1, #255 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp sl, r4 + mov r1, r1, lsr #8 + add r2, r2, #4 + bne .L4957 + add r3, r8, lr, asl #2 + sub r8, r3, #16 +.L4955: + ldr r2, [r5, #4] + cmp r2, #0 + beq .L4962 + ands r1, r2, #255 + ldrne r3, [r8, #0] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #0] + mov r3, r2, lsr #8 + ands r1, r3, #255 + ldrne r3, [r8, #4] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #4] + mov r3, r2, lsr #16 + ands r1, r3, #255 + ldrne r3, [r8, #8] + orrne r3, r6, r3, asl #16 + orrne r3, r1, r3 + strne r3, [r8, #8] + movs r2, r2, lsr #24 + ldrne r3, [r8, #12] + orrne r3, r6, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r8, #12] + add r8, r8, #16 + b .L4924 +.L4892: + add r2, fp, ip + ldr r3, [r0, #0] + cmp r2, #4 + mov r1, ip, asl #3 + mov r2, r3, lsr r1 + bhi .L4899 + cmp fp, #0 + movne r0, #0 + beq .L5444 +.L4914: + ands r3, r2, #255 + orr r1, r6, r3 + ldrne r3, [r8, #0] + add r0, r0, #1 + orrne r3, r1, r3, asl #16 + strne r3, [r8, #0] + cmp fp, r0 + mov r2, r2, lsr #8 + add r8, r8, #4 + bne .L4914 + b .L5444 +.L4873: + rsbs r5, ip, #4 + beq .L4876 + mov r2, r8 + mov r4, #0 +.L4878: + movs r3, r1, lsr #24 + orr ip, r6, r3 + ldrne r3, [r2, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r2, #0] + cmp r5, r4 + mov r1, r1, asl #8 + add r2, r2, #4 + bne .L4878 + add r8, r8, r5, asl #2 +.L4876: + subs ip, fp, r5 + ldr r0, [r0, #0] + beq .L5444 + mov r1, #0 +.L4884: + movs r3, r0, lsr #24 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, asl #8 + add r8, r8, #4 + bne .L4884 + b .L5444 +.L4899: + rsbs r5, ip, #4 + beq .L4902 + mov r1, r8 + mov r4, #0 +.L4904: + ands r3, r2, #255 + orr ip, r6, r3 + ldrne r3, [r1, #0] + add r4, r4, #1 + orrne r3, ip, r3, asl #16 + strne r3, [r1, #0] + cmp r5, r4 + mov r2, r2, lsr #8 + add r1, r1, #4 + bne .L4904 + add r8, r8, r5, asl #2 +.L4902: + subs ip, fp, r5 + ldr r0, [r0, #4] + beq .L5444 + mov r1, #0 +.L4910: + ands r3, r0, #255 + orr r2, r6, r3 + ldrne r3, [r8, #0] + add r1, r1, #1 + orrne r3, r2, r3, asl #16 + strne r3, [r8, #0] + cmp ip, r1 + mov r0, r0, lsr #8 + add r8, r8, #4 + bne .L4910 + b .L5444 + .size render_scanline_text_transparent_alpha, .-render_scanline_text_transparent_alpha + .align 2 + .global render_scanline_affine_base_normal + .type render_scanline_affine_base_normal, %function +render_scanline_affine_base_normal: + @ args = 0, pretend = 0, frame = 24 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5544 + mov lr, r0, asl #4 + add ip, r5, r0, asl #1 + ldrh r4, [ip, #8] + ldr ip, .L5544+4 + sub r0, r0, #2 + sub lr, lr, #32 + add lr, lr, r5 + ldr sl, [ip, r0, asl #2] + ldr ip, .L5544+8 + ldrsh fp, [lr, #36] + mov r6, r4, lsr #14 + ldr r7, .L5544+12 + mov r5, r4, lsr #12 + ldrsh r9, [lr, #32] + mov lr, r4, asl #3 + mov r4, r4, asl #12 + ldr r8, [ip, r0, asl #2] + and r5, r5, #2 + and lr, lr, #63488 + and r4, r4, #49152 + sub sp, sp, #24 + add ip, r6, #7 + add r4, r4, r7 + add lr, lr, r7 + mov r0, #1 + add r6, r6, #4 + cmp fp, #0 + orrne r5, r5, #1 + mov r0, r0, asl ip + str r4, [sp, #16] + mla ip, r9, r1, r8 + rsb r4, r1, r2 + str r6, [sp, #8] + str lr, [sp, #12] + add r7, r3, r1, asl #1 + mla r8, fp, r1, sl + cmp r5, #3 + ldrls pc, [pc, r5, asl #2] + b .L5531 + .p2align 2 +.L5493: + .word .L5489 + .word .L5490 + .word .L5491 + .word .L5492 +.L5491: + sub sl, r0, #1 + and r3, sl, r8, asr #8 + cmp r0, r3 + bhi .L5541 +.L5531: + add sp, sp, #24 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5489: + mov r3, r8, asr #8 + ldr sl, .L5544+16 + cmp r0, r3 + ldrh r1, [sl, #0] + bls .L5497 + ldr r5, [sp, #12] + ldr lr, [sp, #8] + mov r2, r3, lsr #3 + add r6, r5, r2, asl lr + ldr r2, [sp, #16] + and r3, r3, #7 + cmp r4, #0 + add fp, r2, r3, asl #3 + beq .L5497 + mov r5, ip, asr #8 + cmp r0, r5 + movhi r8, #0 + bhi .L5536 + mov r3, r1, asl #16 + mov r3, r3, lsr #16 + mov r8, #0 +.L5504: + add r8, r8, #1 + add ip, ip, r9 + cmp r4, r8 + mov r2, ip, asr #8 + strh r3, [r7], #2 @ movhi + beq .L5496 + cmp r0, r2 + bls .L5504 + mov r5, r2 + b .L5536 +.L5490: + ldr r5, .L5544+16 + cmp r4, #0 + ldrh r3, [r5, #0] + beq .L5531 + mov r1, r8, asr #8 + mov r5, ip, asr #8 + cmp r0, r5 + cmphi r0, r1 + movls r2, #0 + movhi r2, #1 + movls r3, r3, asl #16 + movls r1, r3, lsr #16 + movls sl, r2 + bls .L5512 + b .L5543 +.L5513: + cmp r0, r2 + cmphi r0, r3 + bhi .L5514 +.L5512: + add sl, sl, #1 + add ip, ip, r9 + add r8, r8, fp + cmp r4, sl + strh r1, [r7, #0] @ movhi + mov r2, ip, asr #8 + mov r3, r8, asr #8 + add r7, r7, #2 + bne .L5513 + b .L5531 +.L5492: + cmp r4, #0 + sub lr, r0, #1 + beq .L5531 + mvn r6, #0 + mov r0, #0 +.L5527: + and r3, lr, r8, asr #8 + ldr r5, [sp, #8] + mov r2, r3, lsr #3 + mov r2, r2, asl r5 + and r1, lr, ip, asr #8 + and sl, r3, #7 + add r3, r2, r1, lsr #3 + cmp r3, r6 + and r5, r1, #7 + ldrne r1, [sp, #12] + mov r6, r3 + ldrne r2, [sp, #16] + ldrneb r3, [r1, r3] @ zero_extendqisi2 + add r0, r0, #1 + addne r3, r2, r3, asl #6 + strne r3, [sp, #4] + ldr r3, [sp, #4] + cmp r4, r0 + add r2, r3, sl, asl #3 + ldrb r3, [r2, r5] @ zero_extendqisi2 + ldr r5, .L5544+16 + mov r3, r3, asl #1 + ldrh r3, [r3, r5] + add ip, ip, r9 + strh r3, [r7, #0] @ movhi + add r8, r8, fp + add r7, r7, #2 + bne .L5527 + b .L5531 +.L5541: + ldr r0, [sp, #12] + ldr r1, [sp, #8] + mov r2, r3, lsr #3 + add r6, r0, r2, asl r1 + ldr r2, [sp, #16] + and r3, r3, #7 + cmp r4, #0 + add r5, r2, r3, asl #3 + beq .L5531 + ldr lr, .L5544+16 + mov r0, #0 +.L5525: + and r3, sl, ip, asr #8 + ldrb r1, [r6, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r1, asl #6 + ldrb r2, [r3, r5] @ zero_extendqisi2 + add r0, r0, #1 + mov r2, r2, asl #1 + ldrh r2, [r2, lr] + cmp r4, r0 + strh r2, [r7], #2 @ movhi + add ip, ip, r9 + bne .L5525 + b .L5531 +.L5497: + mov r8, #0 +.L5496: + cmp r8, r4 + ldrh r3, [sl, #0] + bcs .L5531 + mov r3, r3, asl #16 + rsb r2, r8, r4 + mov r3, r3, lsr #16 + mov r1, #0 +.L5508: + add r1, r1, #1 + cmp r2, r1 + strh r3, [r7], #2 @ movhi + bne .L5508 + b .L5531 +.L5506: + cmp r0, r5 + bls .L5496 +.L5536: + ldrb r3, [r6, r5, lsr #3] @ zero_extendqisi2 + and r2, r5, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, fp] @ zero_extendqisi2 + add r8, r8, #1 + mov r1, r1, asl #1 + ldrh r1, [r1, sl] + add ip, ip, r9 + cmp r4, r8 + mov r5, ip, asr #8 + strh r1, [r7], #2 @ movhi + bhi .L5506 + b .L5496 +.L5514: + mov r5, r2 + mov r1, r3 +.L5515: + cmp r0, r1 + cmphi r0, r5 + mvnhi r6, #0 + bhi .L5519 + b .L5516 +.L5518: + cmp r0, r1 + cmphi r0, r5 + bls .L5516 +.L5519: + ldr r2, [sp, #8] + mov r3, r1, lsr #3 + mov r3, r3, asl r2 + add r3, r3, r5, lsr #3 + cmp r3, r6 + ldrne r2, [sp, #12] + and r1, r1, #7 + str r1, [sp, #0] + mov r6, r3 + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r2, [sp, #16] + and lr, r5, #7 + addne r3, r2, r3, asl #6 + strne r3, [sp, #20] + ldr r2, [sp, #0] + ldr r3, [sp, #20] + add sl, sl, #1 + add r3, r3, r2, asl #3 + str r3, [sp, #0] + ldrb r3, [r3, lr] @ zero_extendqisi2 + ldr lr, .L5544+16 + mov r3, r3, asl #1 + ldrh r3, [r3, lr] + add ip, ip, r9 + add r8, r8, fp + cmp r4, sl + strh r3, [r7, #0] @ movhi + mov r1, r8, asr #8 + mov r5, ip, asr #8 + add r7, r7, #2 + bhi .L5518 + b .L5531 +.L5516: + ldr lr, .L5544+16 + ldrh r3, [lr, #0] +.L5520: + add sl, sl, #1 + cmp r4, sl + strh r3, [r7], #2 @ movhi + bhi .L5520 + b .L5531 +.L5543: + mov sl, #0 + b .L5515 +.L5545: + .align 2 +.L5544: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .word palette_ram_converted + .size render_scanline_affine_base_normal, .-render_scanline_affine_base_normal + .align 2 + .global render_scanline_affine_transparent_normal + .type render_scanline_affine_transparent_normal, %function +render_scanline_affine_transparent_normal: + @ args = 0, pretend = 0, frame = 28 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5602 + mov lr, r0, asl #4 + add ip, r5, r0, asl #1 + ldrh r4, [ip, #8] + ldr ip, .L5602+4 + sub r0, r0, #2 + sub lr, lr, #32 + add lr, lr, r5 + ldr sl, [ip, r0, asl #2] + ldr ip, .L5602+8 + ldrsh fp, [lr, #36] + mov r6, r4, lsr #14 + ldr r7, .L5602+12 + mov r5, r4, lsr #12 + ldrsh r9, [lr, #32] + mov lr, r4, asl #3 + mov r4, r4, asl #12 + ldr r8, [ip, r0, asl #2] + and r5, r5, #2 + and lr, lr, #63488 + and r4, r4, #49152 + sub sp, sp, #28 + add ip, r6, #7 + add r4, r4, r7 + add lr, lr, r7 + mov r0, #1 + add r6, r6, #4 + cmp fp, #0 + orrne r5, r5, #1 + mov r0, r0, asl ip + str r4, [sp, #16] + str lr, [sp, #12] + rsb r4, r1, r2 + str r6, [sp, #8] + add lr, r3, r1, asl #1 + mla ip, r9, r1, r8 + mla r7, fp, r1, sl + cmp r5, #3 + ldrls pc, [pc, r5, asl #2] + b .L5594 + .p2align 2 +.L5552: + .word .L5548 + .word .L5549 + .word .L5550 + .word .L5551 +.L5548: + mov r3, r7, asr #8 + cmp r0, r3 + bhi .L5597 +.L5594: + add sp, sp, #28 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5549: + cmp r4, #0 + beq .L5594 + mov r5, ip, asr #8 + mov r1, r7, asr #8 + cmp r0, r5 + cmphi r0, r1 + movls r3, #0 + movhi r3, #1 + movls r8, r3 + bls .L5556 + b .L5600 +.L5570: + cmp r0, r2 + cmphi r0, r3 + bhi .L5571 +.L5556: + add r8, r8, #1 + add ip, ip, r9 + add r7, r7, fp + cmp r4, r8 + mov r2, ip, asr #8 + mov r3, r7, asr #8 + add lr, lr, #2 + bne .L5570 + b .L5594 +.L5550: + sub r8, r0, #1 + and r3, r8, r7, asr #8 + cmp r0, r3 + bls .L5594 + ldr r0, [sp, #12] + ldr r1, [sp, #8] + mov r2, r3, lsr #3 + add r6, r0, r2, asl r1 + ldr r2, [sp, #16] + and r3, r3, #7 + cmp r4, #0 + add r5, r2, r3, asl #3 + beq .L5594 + ldr r7, .L5602+16 + mov r0, #0 +.L5583: + and r3, r8, ip, asr #8 + ldrb r2, [r6, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r2, asl #6 + ldrb r1, [r3, r5] @ zero_extendqisi2 + mov r3, r0, asl #1 + cmp r1, #0 + mov r1, r1, asl #1 + ldrneh r1, [r1, r7] + add r0, r0, #1 + strneh r1, [r3, lr] @ movhi + cmp r4, r0 + add ip, ip, r9 + bne .L5583 + b .L5594 +.L5551: + cmp r4, #0 + sub r6, r0, #1 + beq .L5594 + mvn r3, #0 + str r3, [sp, #24] + mov r5, #0 +.L5588: + and r3, r6, r7, asr #8 + ldr sl, [sp, #8] + mov r2, r3, lsr #3 + mov r2, r2, asl sl + and r1, r6, ip, asr #8 + and r0, r3, #7 + and r8, r1, #7 + add r3, r2, r1, lsr #3 + ldr r1, [sp, #24] + str r3, [sp, #24] + cmp r3, r1 + ldrne r2, [sp, #12] + ldrne r1, [sp, #16] + ldrneb r3, [r2, r3] @ zero_extendqisi2 + mov sl, r5, asl #1 + addne r3, r1, r3, asl #6 + strne r3, [sp, #4] + ldr r2, [sp, #4] + add r5, r5, #1 + add r3, r2, r0, asl #3 + ldrb r2, [r3, r8] @ zero_extendqisi2 + add ip, ip, r9 + cmp r2, #0 + ldrne r3, .L5602+16 + mov r1, r2, asl #1 + ldrneh r1, [r1, r3] + add r7, r7, fp + strneh r1, [sl, lr] @ movhi + cmp r4, r5 + bne .L5588 + b .L5594 +.L5597: + ldr r1, [sp, #12] + ldr r5, [sp, #8] + ldr sl, [sp, #16] + mov r2, r3, lsr #3 + cmp r4, #0 + and r3, r3, #7 + add r6, r1, r2, asl r5 + add r8, sl, r3, asl #3 + beq .L5594 + mov r5, ip, asr #8 + cmp r0, r5 + movls r7, #0 + bls .L5563 + b .L5601 +.L5561: + cmp r0, r2 + add lr, lr, #2 + bhi .L5562 +.L5563: + add r7, r7, #1 + add ip, ip, r9 + cmp r4, r7 + mov r2, ip, asr #8 + bne .L5561 + b .L5594 +.L5571: + mov r5, r2 + mov r1, r3 +.L5572: + cmp r1, r0 + movcc r3, #0 + movcs r3, #1 + cmp r0, r5 + orrls r3, r3, #1 + cmp r3, #0 + mvneq r6, #0 + beq .L5574 + b .L5594 +.L5575: + cmp r0, r1 + cmphi r0, r5 + bls .L5594 +.L5574: + ldr r2, [sp, #8] + mov r3, r1, lsr #3 + mov r3, r3, asl r2 + add r3, r3, r5, lsr #3 + cmp r3, r6 + and r2, r5, #7 + str r2, [sp, #0] + ldrne r2, [sp, #12] + mov r6, r3 + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r2, [sp, #16] + and sl, r1, #7 + addne r3, r2, r3, asl #6 + strne r3, [sp, #20] + ldr r2, [sp, #20] + add r8, r8, #1 + add r3, r2, sl, asl #3 + ldr sl, [sp, #0] + add ip, ip, r9 + ldrb r2, [r3, sl] @ zero_extendqisi2 + add r7, r7, fp + cmp r2, #0 + ldrne r3, .L5602+16 + mov r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov r1, r7, asr #8 + strneh r2, [lr, #0] @ movhi + cmp r4, r8 + mov r5, ip, asr #8 + add lr, lr, #2 + bhi .L5575 + b .L5594 +.L5562: + mov r5, r2 +.L5564: + cmp r5, r0 + bcc .L5596 + b .L5594 +.L5566: + cmp r0, r5 + bls .L5594 +.L5596: + ldrb r3, [r6, r5, lsr #3] @ zero_extendqisi2 + and r2, r5, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r8] @ zero_extendqisi2 + add r7, r7, #1 + cmp r1, #0 + ldrne r3, .L5602+16 + mov r1, r1, asl #1 + ldrneh r1, [r1, r3] + add ip, ip, r9 + strneh r1, [lr, #0] @ movhi + cmp r4, r7 + mov r5, ip, asr #8 + add lr, lr, #2 + bhi .L5566 + b .L5594 +.L5600: + mov r8, #0 + b .L5572 +.L5601: + mov r7, #0 + b .L5564 +.L5603: + .align 2 +.L5602: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .word palette_ram_converted + .size render_scanline_affine_transparent_normal, .-render_scanline_affine_transparent_normal + .align 2 + .global render_scanline_affine_base_color16 + .type render_scanline_affine_base_color16, %function +render_scanline_affine_base_color16: + @ args = 0, pretend = 0, frame = 36 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5672 + add r7, r0, #7 + ldrh r6, [r5, #80] + mov lr, r0, asl #4 + mov sl, r6, asr r0 + mov r7, r6, asr r7 + sub lr, lr, #32 + add ip, r5, r0, asl #1 + add lr, lr, r5 + ldrh r4, [ip, #8] + ldrsh ip, [lr, #36] + sub sp, sp, #36 + str ip, [sp, #24] + ldr ip, .L5672+4 + sub r0, r0, #2 + ldr ip, [ip, r0, asl #2] + mov r8, r4, lsr #12 + str ip, [sp, #4] + ldr ip, .L5672+8 + mov r9, r4, lsr #14 + ldr r0, [ip, r0, asl #2] + ldrsh lr, [lr, #32] + str r0, [sp, #8] + ldr r0, [sp, #24] + and r8, r8, #2 + add ip, r9, #7 + cmp r0, #0 + orrne r8, r8, #1 + mov r0, #1 + mov r5, r6, lsr #12 + str lr, [sp, #12] + mov ip, r0, asl ip + mov lr, r4, asl #3 + ldr r0, .L5672+12 + mov r4, r4, asl #12 + and r7, r7, #2 + mov r6, r6, asl #26 + and r5, r5, #2 + and sl, sl, #1 + and lr, lr, #63488 + and r4, r4, #49152 + orr r5, r5, r6, lsr #31 + orr sl, sl, r7 + add r4, r4, r0 + add lr, lr, r0 + rsb fp, r1, r2 + add r7, r3, r1, asl #1 + ldr r6, [sp, #8] + ldr r2, [sp, #12] + ldr r0, [sp, #4] + ldr r3, [sp, #24] + mov r5, r5, asl #9 + mov sl, sl, asl #9 + str r4, [sp, #32] + str r5, [sp, #16] + str sl, [sp, #20] + add r9, r9, #4 + str lr, [sp, #28] + mla r6, r2, r1, r6 + mla r0, r3, r1, r0 + cmp r8, #3 + ldrls pc, [pc, r8, asl #2] + b .L5661 + .p2align 2 +.L5610: + .word .L5606 + .word .L5607 + .word .L5608 + .word .L5609 +.L5608: + sub lr, ip, #1 + and r3, lr, r0, asr #8 + cmp ip, r3 + bhi .L5669 +.L5661: + add sp, sp, #36 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5606: + mov r3, r0, asr #8 + cmp ip, r3 + movls r0, #0 + bls .L5617 + ldr r0, [sp, #28] + ldr r1, [sp, #32] + mov r2, r3, lsr #3 + cmp fp, #0 + and r3, r3, #7 + add r9, r0, r2, asl r9 + add r4, r1, r3, asl #3 + beq .L5661 + mov r2, r6, asr #8 + cmp ip, r2 + movhi r0, #0 + bhi .L5664 + ldr r2, [sp, #16] + mov r0, #0 + mov r3, r2, asl #16 + mov r3, r3, lsr #16 + b .L5625 +.L5623: + cmp ip, r2 + bhi .L5664 +.L5625: + ldr r1, [sp, #12] + add r0, r0, #1 + add r6, r6, r1 + cmp fp, r0 + mov r2, r6, asr #8 + strh r3, [r7], #2 @ movhi + bne .L5623 +.L5617: + cmp r0, fp + bcs .L5661 + ldr r2, [sp, #16] + mov r1, #0 + mov r3, r2, asl #16 + mov r3, r3, lsr #16 + rsb r2, r0, fp +.L5632: + add r1, r1, #1 + cmp r1, r2 + strh r3, [r7], #2 @ movhi + bne .L5632 + b .L5661 +.L5607: + cmp fp, #0 + beq .L5661 + mov r1, r6, asr #8 + mov r2, r0, asr #8 + cmp ip, r1 + cmphi ip, r2 + ldrls r4, [sp, #16] + movls r8, #0 + movhi r8, #1 + movls r3, r4, asl #16 + movls r1, r3, lsr #16 + bls .L5614 + b .L5671 +.L5633: + cmp ip, r2 + cmphi ip, r3 + bhi .L5634 +.L5614: + ldr r3, [sp, #12] + ldr r4, [sp, #24] + add r8, r8, #1 + add r6, r6, r3 + add r0, r0, r4 + cmp fp, r8 + strh r1, [r7, #0] @ movhi + mov r2, r6, asr #8 + mov r3, r0, asr #8 + add r7, r7, #2 + bne .L5633 + b .L5661 +.L5609: + cmp fp, #0 + sub sl, ip, #1 + beq .L5661 + mvn r5, #0 + mov r4, #0 +.L5654: + and r3, sl, r0, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl r9 + and r1, sl, r6, asr #8 + add ip, r2, r1, lsr #3 + cmp ip, r5 + and r8, r1, #7 + ldrne r1, [sp, #28] + and lr, r3, #7 + ldrne r2, [sp, #32] + ldrneb r3, [r1, ip] @ zero_extendqisi2 + add r4, r4, #1 + addne r3, r2, r3, asl #6 + strne r3, [sp, #0] + ldr r1, [sp, #0] + mov r5, ip + add r3, r1, lr, asl #3 + ldrb r2, [r3, r8] @ zero_extendqisi2 + ldr r3, [sp, #20] + cmp r2, #0 + orr r1, r2, r3 + ldreq r1, [sp, #16] + ldr r2, [sp, #12] + ldr r3, [sp, #24] + cmp fp, r4 + strh r1, [r7, #0] @ movhi + add r6, r6, r2 + add r0, r0, r3 + add r7, r7, #2 + bne .L5654 + b .L5661 +.L5669: + ldr r4, [sp, #28] + ldr ip, [sp, #32] + mov r2, r3, lsr #3 + cmp fp, #0 + and r3, r3, #7 + add r9, r4, r2, asl r9 + add r4, ip, r3, asl #3 + beq .L5661 + mov r0, #0 +.L5648: + and r3, lr, r6, asr #8 + ldrb r1, [r9, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r1, asl #6 + ldrb r2, [r3, r4] @ zero_extendqisi2 + ldr r1, [sp, #20] + cmp r2, #0 + add r0, r0, #1 + orr r2, r2, r1 + ldr r3, [sp, #12] + ldreq r2, [sp, #16] + cmp fp, r0 + strh r2, [r7, #0] @ movhi + add r6, r6, r3 + add r7, r7, #2 + bne .L5648 + b .L5661 +.L5627: + cmp ip, r2 + bls .L5617 +.L5664: + ldrb r3, [r9, r2, lsr #3] @ zero_extendqisi2 + and r2, r2, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r4] @ zero_extendqisi2 + ldr r2, [sp, #20] + cmp r1, #0 + orr r1, r1, r2 + strneh r1, [r7, #0] @ movhi + ldreq r3, [sp, #16] + ldr r1, [sp, #12] + add r0, r0, #1 + streqh r3, [r7, #0] @ movhi + add r6, r6, r1 + cmp fp, r0 + add r7, r7, #2 + mov r2, r6, asr #8 + bhi .L5627 + b .L5617 +.L5634: + mov r1, r2 + mov r2, r3 +.L5635: + cmp r2, ip + cmpcc r1, ip + mvncc r4, #0 + bcc .L5639 + b .L5636 +.L5638: + cmp ip, r2 + cmphi ip, r1 + bls .L5636 +.L5639: + mov r3, r2, lsr #3 + mov r3, r3, asl r9 + and lr, r2, #7 + and r2, r1, #7 + add r1, r3, r1, lsr #3 + cmp r1, r4 + ldrne r4, [sp, #28] + add r8, r8, #1 + ldrneb r3, [r4, r1] @ zero_extendqisi2 + ldrne r4, [sp, #32] + addne r5, r4, r3, asl #6 + add r3, r5, lr, asl #3 + ldrb r2, [r3, r2] @ zero_extendqisi2 + ldr r3, [sp, #20] + cmp r2, #0 + orr r2, r2, r3 + strneh r2, [r7, #0] @ movhi + ldreq r4, [sp, #16] + ldr r2, [sp, #12] + ldr r3, [sp, #24] + streqh r4, [r7, #0] @ movhi + add r6, r6, r2 + add r0, r0, r3 + cmp fp, r8 + mov r4, r1 + add r7, r7, #2 + mov r1, r6, asr #8 + mov r2, r0, asr #8 + bhi .L5638 + b .L5661 +.L5636: + ldr r4, [sp, #16] + mov r3, r4, asl #16 + mov r3, r3, lsr #16 +.L5640: + add r8, r8, #1 + cmp fp, r8 + strh r3, [r7], #2 @ movhi + bhi .L5640 + b .L5661 +.L5671: + mov r8, #0 + b .L5635 +.L5673: + .align 2 +.L5672: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_base_color16, .-render_scanline_affine_base_color16 + .align 2 + .global render_scanline_affine_transparent_color16 + .type render_scanline_affine_transparent_color16, %function +render_scanline_affine_transparent_color16: + @ args = 0, pretend = 0, frame = 36 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5730 + add r7, r0, #7 + ldrh r6, [r5, #80] + add ip, r5, r0, asl #1 + mov r7, r6, asr r7 + mov r6, r6, asr r0 + ldrh r4, [ip, #8] + mov lr, r0, asl #4 + ldr ip, .L5730+4 + sub r0, r0, #2 + sub lr, lr, #32 + add lr, lr, r5 + ldr ip, [ip, r0, asl #2] + sub sp, sp, #36 + ldrsh r9, [lr, #36] + mov r8, r4, lsr #14 + mov r5, r4, lsr #12 + str ip, [sp, #8] + ldrsh fp, [lr, #32] + ldr ip, .L5730+8 + ldr sl, .L5730+12 + mov lr, r4, asl #3 + mov r4, r4, asl #12 + str r9, [sp, #16] + and r4, r4, #49152 + ldr r9, [ip, r0, asl #2] + and r7, r7, #2 + ldr ip, [sp, #16] + add r4, r4, sl + and r6, r6, #1 + orr r6, r6, r7 + and r5, r5, #2 + and lr, lr, #63488 + str r4, [sp, #24] + ldr r7, [sp, #8] + rsb r4, r1, r2 + ldr r2, [sp, #16] + add lr, lr, sl + cmp ip, #0 + orrne r5, r5, #1 + mov r0, #1 + add ip, r8, #7 + mov r6, r6, asl #9 + mov r0, r0, asl ip + str lr, [sp, #20] + str r6, [sp, #12] + add r8, r8, #4 + add lr, r3, r1, asl #1 + mla ip, fp, r1, r9 + mla r7, r2, r1, r7 + cmp r5, #3 + ldrls pc, [pc, r5, asl #2] + b .L5722 + .p2align 2 +.L5680: + .word .L5676 + .word .L5677 + .word .L5678 + .word .L5679 +.L5676: + mov r3, r7, asr #8 + cmp r0, r3 + bhi .L5725 +.L5722: + add sp, sp, #36 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5677: + cmp r4, #0 + beq .L5722 + mov r5, ip, asr #8 + mov r1, r7, asr #8 + cmp r0, r5 + cmphi r0, r1 + movls r3, #0 + movhi r3, #1 + movls sl, r3 + bls .L5684 + b .L5728 +.L5698: + cmp r0, r2 + cmphi r0, r3 + bhi .L5699 +.L5684: + ldr r3, [sp, #16] + add sl, sl, #1 + add ip, ip, fp + add r7, r7, r3 + cmp r4, sl + mov r2, ip, asr #8 + mov r3, r7, asr #8 + add lr, lr, #2 + bne .L5698 + b .L5722 +.L5678: + sub r6, r0, #1 + and r3, r6, r7, asr #8 + cmp r0, r3 + bls .L5722 + ldr r9, [sp, #20] + ldr r0, [sp, #24] + mov r2, r3, lsr #3 + cmp r4, #0 + and r3, r3, #7 + add r8, r9, r2, asl r8 + add r5, r0, r3, asl #3 + beq .L5722 + mov r0, #0 +.L5711: + and r3, r6, ip, asr #8 + ldrb r2, [r8, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r2, asl #6 + ldrb r1, [r3, r5] @ zero_extendqisi2 + ldr r2, [sp, #12] + cmp r1, #0 + mov r3, r0, asl #1 + orr r1, r1, r2 + add r0, r0, #1 + strneh r1, [r3, lr] @ movhi + cmp r4, r0 + add ip, ip, fp + bne .L5711 + b .L5722 +.L5679: + cmp r4, #0 + sub r6, r0, #1 + beq .L5722 + mvn r3, #0 + str r3, [sp, #32] + mov sl, #0 +.L5716: + and r3, r6, r7, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl r8 + and r1, r6, ip, asr #8 + and r9, r3, #7 + and r5, r1, #7 + add r3, r2, r1, lsr #3 + ldr r1, [sp, #32] + str r3, [sp, #32] + cmp r3, r1 + ldrne r2, [sp, #20] + ldrne r1, [sp, #24] + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldr r0, [sp, #16] + addne r3, r1, r3, asl #6 + strne r3, [sp, #4] + ldr r2, [sp, #4] + add r7, r7, r0 + add r3, r2, r9, asl #3 + ldrb r2, [r3, r5] @ zero_extendqisi2 + ldr r3, [sp, #12] + mov r0, sl, asl #1 + cmp r2, #0 + add sl, sl, #1 + orr r1, r2, r3 + strneh r1, [r0, lr] @ movhi + cmp r4, sl + add ip, ip, fp + bne .L5716 + b .L5722 +.L5725: + ldr r9, [sp, #20] + ldr r1, [sp, #24] + mov r2, r3, lsr #3 + cmp r4, #0 + and r3, r3, #7 + add r8, r9, r2, asl r8 + add r6, r1, r3, asl #3 + beq .L5722 + mov r5, ip, asr #8 + cmp r0, r5 + movls r7, #0 + bls .L5691 + b .L5729 +.L5689: + cmp r0, r2 + add lr, lr, #2 + bhi .L5690 +.L5691: + add r7, r7, #1 + add ip, ip, fp + cmp r4, r7 + mov r2, ip, asr #8 + bne .L5689 + b .L5722 +.L5699: + mov r5, r2 + mov r1, r3 +.L5700: + cmp r1, r0 + movcc r3, #0 + movcs r3, #1 + cmp r0, r5 + orrls r3, r3, #1 + cmp r3, #0 + mvneq r6, #0 + beq .L5702 + b .L5722 +.L5703: + cmp r0, r1 + cmphi r0, r5 + bls .L5722 +.L5702: + mov r3, r1, lsr #3 + mov r3, r3, asl r8 + add r3, r3, r5, lsr #3 + cmp r3, r6 + and r2, r5, #7 + str r2, [sp, #0] + ldrne r2, [sp, #20] + mov r6, r3 + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r2, [sp, #24] + ldr r9, [sp, #16] + addne r3, r2, r3, asl #6 + strne r3, [sp, #28] + ldr r2, [sp, #28] + add r7, r7, r9 + and r9, r1, #7 + add r3, r2, r9, asl #3 + ldr r9, [sp, #0] + add sl, sl, #1 + ldrb r2, [r3, r9] @ zero_extendqisi2 + ldr r3, [sp, #12] + cmp r2, #0 + orr r2, r2, r3 + strneh r2, [lr, #0] @ movhi + add ip, ip, fp + cmp r4, sl + mov r1, r7, asr #8 + mov r5, ip, asr #8 + add lr, lr, #2 + bhi .L5703 + b .L5722 +.L5690: + mov r5, r2 +.L5692: + cmp r5, r0 + bcc .L5724 + b .L5722 +.L5694: + cmp r0, r5 + bls .L5722 +.L5724: + ldrb r3, [r8, r5, lsr #3] @ zero_extendqisi2 + and r2, r5, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r6] @ zero_extendqisi2 + ldr r2, [sp, #12] + cmp r1, #0 + add r7, r7, #1 + orr r1, r1, r2 + strneh r1, [lr, #0] @ movhi + add ip, ip, fp + cmp r4, r7 + mov r5, ip, asr #8 + add lr, lr, #2 + bhi .L5694 + b .L5722 +.L5728: + mov sl, #0 + b .L5700 +.L5729: + mov r7, #0 + b .L5692 +.L5731: + .align 2 +.L5730: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_transparent_color16, .-render_scanline_affine_transparent_color16 + .align 2 + .global render_scanline_affine_base_color32 + .type render_scanline_affine_base_color32, %function +render_scanline_affine_base_color32: + @ args = 0, pretend = 0, frame = 36 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5799 + add r7, r0, #7 + ldrh r6, [r5, #80] + add ip, r5, r0, asl #1 + mov sl, r6, asr r0 + mov r7, r6, asr r7 + ldrh r4, [ip, #8] + mov lr, r0, asl #4 + ldr ip, .L5799+4 + sub r0, r0, #2 + sub lr, lr, #32 + ldr ip, [ip, r0, asl #2] + add lr, lr, r5 + sub sp, sp, #36 + ldrsh r5, [lr, #36] + str ip, [sp, #4] + ldr ip, .L5799+8 + str r5, [sp, #24] + ldr r0, [ip, r0, asl #2] + mov r8, r4, lsr #12 + ldr ip, [sp, #24] + mov r9, r4, lsr #14 + ldrsh lr, [lr, #32] + and r8, r8, #2 + str r0, [sp, #8] + cmp ip, #0 + orrne r8, r8, #1 + mov r0, #1 + add ip, r9, #7 + mov r5, r6, lsr #12 + str lr, [sp, #12] + mov ip, r0, asl ip + mov lr, r4, asl #3 + ldr r0, .L5799+12 + mov r4, r4, asl #12 + and r7, r7, #2 + mov r6, r6, asl #26 + and r5, r5, #2 + and sl, sl, #1 + and lr, lr, #63488 + and r4, r4, #49152 + orr r5, r5, r6, lsr #31 + orr sl, sl, r7 + add r4, r4, r0 + add lr, lr, r0 + rsb fp, r1, r2 + add r6, r3, r1, asl #2 + ldr r7, [sp, #8] + ldr r2, [sp, #12] + ldr r0, [sp, #4] + ldr r3, [sp, #24] + mov r5, r5, asl #9 + mov sl, sl, asl #9 + str r4, [sp, #32] + str r5, [sp, #16] + str sl, [sp, #20] + add r9, r9, #4 + str lr, [sp, #28] + mla r7, r2, r1, r7 + mla r0, r3, r1, r0 + cmp r8, #3 + ldrls pc, [pc, r8, asl #2] + b .L5788 + .p2align 2 +.L5738: + .word .L5734 + .word .L5735 + .word .L5736 + .word .L5737 +.L5736: + sub lr, ip, #1 + and r3, lr, r0, asr #8 + cmp ip, r3 + bhi .L5796 +.L5788: + add sp, sp, #36 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5734: + mov r3, r0, asr #8 + cmp ip, r3 + movls r0, #0 + bls .L5745 + ldr r4, [sp, #28] + ldr r5, [sp, #32] + mov r2, r3, lsr #3 + cmp fp, #0 + and r3, r3, #7 + add r9, r4, r2, asl r9 + add r4, r5, r3, asl #3 + beq .L5788 + mov r2, r7, asr #8 + cmp ip, r2 + movhi r0, #0 + movls r0, #0 + bls .L5751 + b .L5793 +.L5752: + cmp ip, r2 + bhi .L5793 +.L5751: + ldr lr, [sp, #12] + add r0, r0, #1 + ldr r1, [sp, #16] + add r7, r7, lr + cmp fp, r0 + mov r2, r7, asr #8 + str r1, [r6], #4 + bne .L5752 +.L5745: + cmp r0, fp + bcs .L5788 + rsb r2, r0, fp + ldr r0, [sp, #16] + mov r3, #0 +.L5760: + add r3, r3, #1 + cmp r2, r3 + str r0, [r6], #4 + bne .L5760 + b .L5788 +.L5735: + cmp fp, #0 + beq .L5788 + mov r1, r7, asr #8 + mov r2, r0, asr #8 + cmp ip, r1 + cmphi ip, r2 + movls r3, #0 + movhi r3, #1 + movls r8, r3 + bls .L5742 + b .L5798 +.L5761: + cmp ip, r2 + cmphi ip, r3 + bhi .L5762 +.L5742: + ldr r2, [sp, #24] + ldr r1, [sp, #12] + add r8, r8, #1 + ldr r4, [sp, #16] + add r0, r0, r2 + add r7, r7, r1 + cmp fp, r8 + str r4, [r6, #0] + mov r2, r7, asr #8 + mov r3, r0, asr #8 + add r6, r6, #4 + bne .L5761 + b .L5788 +.L5737: + cmp fp, #0 + sub sl, ip, #1 + beq .L5788 + mvn r5, #0 + mov r4, #0 +.L5781: + and r3, sl, r0, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl r9 + and r1, sl, r7, asr #8 + add ip, r2, r1, lsr #3 + cmp ip, r5 + ldrne r5, [sp, #28] + and lr, r3, #7 + and r8, r1, #7 + ldrneb r3, [r5, ip] @ zero_extendqisi2 + ldrne r1, [sp, #32] + add r4, r4, #1 + addne r3, r1, r3, asl #6 + strne r3, [sp, #0] + ldr r2, [sp, #0] + add r3, r2, lr, asl #3 + ldrb r2, [r3, r8] @ zero_extendqisi2 + ldr r3, [sp, #20] + cmp r2, #0 + ldreq r5, [sp, #16] + orr r1, r3, r2 + strne r1, [r6, #0] + ldr lr, [sp, #12] + ldr r1, [sp, #24] + streq r5, [r6, #0] + cmp fp, r4 + add r7, r7, lr + add r0, r0, r1 + add r6, r6, #4 + mov r5, ip + bne .L5781 + b .L5788 +.L5796: + ldr ip, [sp, #28] + ldr r0, [sp, #32] + mov r2, r3, lsr #3 + cmp fp, #0 + and r3, r3, #7 + add r9, ip, r2, asl r9 + add r4, r0, r3, asl #3 + beq .L5788 + mov r0, #0 +.L5775: + and r3, lr, r7, asr #8 + ldrb r1, [r9, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r1, asl #6 + ldrb r2, [r3, r4] @ zero_extendqisi2 + ldr r1, [sp, #20] + cmp r2, #0 + orr r3, r1, r2 + ldreq r2, [sp, #16] + strne r3, [r6, #0] + add r0, r0, #1 + ldr r3, [sp, #12] + streq r2, [r6, #0] + cmp fp, r0 + add r7, r7, r3 + add r6, r6, #4 + bne .L5775 + b .L5788 +.L5755: + cmp ip, r2 + bls .L5745 +.L5793: + ldrb r3, [r9, r2, lsr #3] @ zero_extendqisi2 + and r2, r2, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r4] @ zero_extendqisi2 + ldr r3, [sp, #20] + cmp r1, #0 + ldreq r5, [sp, #16] + ldr lr, [sp, #12] + orr r2, r3, r1 + add r0, r0, #1 + strne r2, [r6, #0] + streq r5, [r6, #0] + add r7, r7, lr + cmp fp, r0 + add r6, r6, #4 + mov r2, r7, asr #8 + bhi .L5755 + b .L5745 +.L5762: + mov r1, r2 + mov r2, r3 +.L5763: + cmp r2, ip + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + mvneq r5, #0 + beq .L5767 + b .L5789 +.L5766: + cmp ip, r2 + cmphi ip, r1 + bls .L5789 +.L5767: + mov r3, r2, lsr #3 + mov r3, r3, asl r9 + and lr, r2, #7 + and r2, r1, #7 + add r1, r3, r1, lsr #3 + cmp r1, r5 + ldrne r4, [sp, #28] + ldrne r5, [sp, #32] + ldrneb r3, [r4, r1] @ zero_extendqisi2 + add r8, r8, #1 + addne r4, r5, r3, asl #6 + add r3, r4, lr, asl #3 + ldrb r2, [r3, r2] @ zero_extendqisi2 + ldr lr, [sp, #20] + cmp r2, #0 + orr r3, lr, r2 + strne r3, [r6, #0] + ldreq r2, [sp, #16] + ldr r5, [sp, #24] + ldr r3, [sp, #12] + streq r2, [r6, #0] + add r0, r0, r5 + add r7, r7, r3 + cmp fp, r8 + mov r5, r1 + add r6, r6, #4 + mov r1, r7, asr #8 + mov r2, r0, asr #8 + bhi .L5766 + b .L5788 +.L5789: + add r8, r8, #1 + ldr r5, [sp, #16] + cmp fp, r8 + str r5, [r6], #4 + bls .L5788 + add r8, r8, #1 + ldr r5, [sp, #16] + cmp fp, r8 + str r5, [r6], #4 + bhi .L5789 + b .L5788 +.L5798: + mov r8, #0 + b .L5763 +.L5800: + .align 2 +.L5799: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_base_color32, .-render_scanline_affine_base_color32 + .align 2 + .global render_scanline_affine_transparent_color32 + .type render_scanline_affine_transparent_color32, %function +render_scanline_affine_transparent_color32: + @ args = 0, pretend = 0, frame = 32 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5857 + add r7, r0, #7 + ldrh r6, [r5, #80] + add ip, r5, r0, asl #1 + mov r7, r6, asr r7 + mov r6, r6, asr r0 + ldrh r4, [ip, #8] + mov lr, r0, asl #4 + ldr ip, .L5857+4 + sub r0, r0, #2 + sub lr, lr, #32 + add lr, lr, r5 + ldr ip, [ip, r0, asl #2] + sub sp, sp, #32 + ldrsh r9, [lr, #36] + mov r8, r4, lsr #14 + mov r5, r4, lsr #12 + str ip, [sp, #8] + ldrsh fp, [lr, #32] + ldr ip, .L5857+8 + ldr sl, .L5857+12 + mov lr, r4, asl #3 + mov r4, r4, asl #12 + str r9, [sp, #16] + and r4, r4, #49152 + ldr r9, [ip, r0, asl #2] + and r7, r7, #2 + ldr ip, [sp, #16] + add r4, r4, sl + and r6, r6, #1 + orr r6, r6, r7 + and r5, r5, #2 + and lr, lr, #63488 + str r4, [sp, #24] + ldr r7, [sp, #8] + rsb r4, r1, r2 + ldr r2, [sp, #16] + add lr, lr, sl + cmp ip, #0 + orrne r5, r5, #1 + mov r0, #1 + add ip, r8, #7 + mov r6, r6, asl #9 + mov r0, r0, asl ip + str lr, [sp, #20] + str r6, [sp, #12] + add r8, r8, #4 + add lr, r3, r1, asl #2 + mla ip, fp, r1, r9 + mla r7, r2, r1, r7 + cmp r5, #3 + ldrls pc, [pc, r5, asl #2] + b .L5849 + .p2align 2 +.L5807: + .word .L5803 + .word .L5804 + .word .L5805 + .word .L5806 +.L5803: + mov r3, r7, asr #8 + cmp r0, r3 + bhi .L5852 +.L5849: + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5804: + cmp r4, #0 + beq .L5849 + mov r5, ip, asr #8 + mov r1, r7, asr #8 + cmp r0, r5 + cmphi r0, r1 + movls r3, #0 + movhi r3, #1 + movls sl, r3 + bls .L5811 + b .L5855 +.L5825: + cmp r0, r2 + cmphi r0, r3 + bhi .L5826 +.L5811: + ldr r3, [sp, #16] + add sl, sl, #1 + add ip, ip, fp + add r7, r7, r3 + cmp r4, sl + mov r2, ip, asr #8 + mov r3, r7, asr #8 + add lr, lr, #4 + bne .L5825 + b .L5849 +.L5805: + sub r6, r0, #1 + and r3, r6, r7, asr #8 + cmp r0, r3 + bls .L5849 + ldr r0, [sp, #20] + ldr r1, [sp, #24] + mov r2, r3, lsr #3 + cmp r4, #0 + and r3, r3, #7 + add r8, r0, r2, asl r8 + add r5, r1, r3, asl #3 + beq .L5849 + mov r0, #0 +.L5838: + and r3, r6, ip, asr #8 + ldrb r2, [r8, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r2, asl #6 + ldrb r1, [r3, r5] @ zero_extendqisi2 + ldr r2, [sp, #12] + cmp r1, #0 + orr r3, r2, r1 + strne r3, [lr, r0, asl #2] + add r0, r0, #1 + cmp r4, r0 + add ip, ip, fp + bne .L5838 + b .L5849 +.L5806: + cmp r4, #0 + sub r0, r0, #1 + beq .L5849 + mov r9, #0 + mvn r6, #0 +.L5843: + and r3, r0, r7, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl r8 + and r1, r0, ip, asr #8 + and sl, r3, #7 + add r3, r2, r1, lsr #3 + cmp r3, r6 + ldrne r2, [sp, #20] + and r5, r1, #7 + ldr r1, [sp, #16] + mov r6, r3 + add r7, r7, r1 + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r1, [sp, #24] + add ip, ip, fp + addne r3, r1, r3, asl #6 + strne r3, [sp, #4] + ldr r2, [sp, #4] + add r3, r2, sl, asl #3 + ldrb r2, [r3, r5] @ zero_extendqisi2 + ldr r3, [sp, #12] + cmp r2, #0 + orr r1, r3, r2 + strne r1, [lr, r9, asl #2] + add r9, r9, #1 + cmp r4, r9 + bne .L5843 + b .L5849 +.L5852: + ldr r9, [sp, #20] + ldr r1, [sp, #24] + mov r2, r3, lsr #3 + cmp r4, #0 + and r3, r3, #7 + add r8, r9, r2, asl r8 + add r6, r1, r3, asl #3 + beq .L5849 + mov r5, ip, asr #8 + cmp r0, r5 + movls r7, #0 + bls .L5818 + b .L5856 +.L5816: + cmp r0, r2 + add lr, lr, #4 + bhi .L5817 +.L5818: + add r7, r7, #1 + add ip, ip, fp + cmp r4, r7 + mov r2, ip, asr #8 + bne .L5816 + b .L5849 +.L5826: + mov r5, r2 + mov r1, r3 +.L5827: + cmp r1, r0 + movcc r3, #0 + movcs r3, #1 + cmp r0, r5 + orrls r3, r3, #1 + cmp r3, #0 + mvneq r6, #0 + beq .L5829 + b .L5849 +.L5830: + cmp r0, r1 + cmphi r0, r5 + bls .L5849 +.L5829: + mov r3, r1, lsr #3 + mov r3, r3, asl r8 + add r3, r3, r5, lsr #3 + cmp r3, r6 + and r2, r5, #7 + str r2, [sp, #0] + ldrne r2, [sp, #20] + mov r6, r3 + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r2, [sp, #24] + ldr r9, [sp, #16] + addne r3, r2, r3, asl #6 + strne r3, [sp, #28] + ldr r2, [sp, #28] + add r7, r7, r9 + and r9, r1, #7 + add r3, r2, r9, asl #3 + ldr r9, [sp, #0] + add sl, sl, #1 + ldrb r2, [r3, r9] @ zero_extendqisi2 + ldr r9, [sp, #12] + cmp r2, #0 + orr r3, r9, r2 + strne r3, [lr, #0] + add ip, ip, fp + cmp r4, sl + mov r1, r7, asr #8 + mov r5, ip, asr #8 + add lr, lr, #4 + bhi .L5830 + b .L5849 +.L5817: + mov r5, r2 +.L5819: + cmp r5, r0 + bcc .L5851 + b .L5849 +.L5821: + cmp r0, r5 + bls .L5849 +.L5851: + ldrb r3, [r8, r5, lsr #3] @ zero_extendqisi2 + and r2, r5, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r6] @ zero_extendqisi2 + ldr r2, [sp, #12] + cmp r1, #0 + add r7, r7, #1 + orr r3, r2, r1 + strne r3, [lr, #0] + add ip, ip, fp + cmp r4, r7 + mov r5, ip, asr #8 + add lr, lr, #4 + bhi .L5821 + b .L5849 +.L5855: + mov sl, #0 + b .L5827 +.L5856: + mov r7, #0 + b .L5819 +.L5858: + .align 2 +.L5857: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_transparent_color32, .-render_scanline_affine_transparent_color32 + .align 2 + .global render_scanline_affine_base_alpha + .type render_scanline_affine_base_alpha, %function +render_scanline_affine_base_alpha: + @ args = 0, pretend = 0, frame = 32 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r7, .L5933 + add lr, r0, #7 + ldrh ip, [r7, #80] + sub sp, sp, #32 + mov lr, ip, asr lr + mov r4, ip, asr r0 + mov r5, ip, lsr #12 + and r5, r5, #2 + mov ip, ip, asl #26 + orr r5, r5, ip, lsr #31 + and r4, r4, #1 + and lr, lr, #2 + mov ip, r5, asl #25 + orr r4, r4, lr + orr r4, ip, r4, asl #9 + mov r5, r5, asl #9 + tst r4, #512 + mov r6, r0 + str r4, [sp, #12] + mov r8, r1 + mov sl, r2 + stmib sp, {r3, r5} @ phole stm + beq .L5928 + add r3, r7, r0, asl #1 + ldrh r1, [r3, #8] + ldr r3, .L5933+4 + mov r2, r0, asl #4 + sub r0, r0, #2 + ldr r6, [r3, r0, asl #2] + ldr r3, .L5933+8 + mov lr, r1, lsr #14 + ldr r5, [r3, r0, asl #2] + ldr r4, .L5933+12 + mov ip, r1, lsr #12 + mov r0, r1, asl #3 + sub r2, r2, #32 + mov r1, r1, asl #12 + add r2, r2, r7 + and r1, r1, #49152 + ldrsh fp, [r2, #36] + add r1, r1, r4 + ldrsh r9, [r2, #32] + and ip, ip, #2 + and r0, r0, #63488 + str r1, [sp, #24] + ldr r1, [sp, #4] + add r0, r0, r4 + add r2, lr, #7 + mov r3, #1 + add lr, lr, #4 + cmp fp, #0 + orrne ip, ip, #1 + str r0, [sp, #20] + mov r7, r3, asl r2 + mla r0, r9, r8, r5 + rsb sl, r8, sl + str lr, [sp, #16] + add r4, r1, r8, asl #2 + mla r5, fp, r8, r6 + cmp ip, #3 + ldrls pc, [pc, ip, asl #2] + b .L5918 + .p2align 2 +.L5867: + .word .L5863 + .word .L5864 + .word .L5865 + .word .L5866 +.L5919: + add ip, ip, #1 + ldr r1, [sp, #8] + cmp sl, ip + str r1, [r4], #4 + bhi .L5919 +.L5918: + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5928: + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_affine_base_color32 +.L5863: + mov r1, r5, asr #8 + cmp r7, r1 + movls ip, #0 + bls .L5874 + ldr r6, [sp, #20] + ldr r8, [sp, #16] + ldr ip, [sp, #24] + mov r2, r1, lsr #3 + and r3, r1, #7 + cmp sl, #0 + add lr, r6, r2, asl r8 + add r5, ip, r3, asl #3 + beq .L5918 + mov r2, r0, asr #8 + cmp r7, r2 + movls ip, #0 + bls .L5881 + b .L5931 +.L5879: + cmp r7, r2 + bhi .L5882 +.L5881: + add ip, ip, #1 + ldr r1, [sp, #8] + add r0, r0, r9 + cmp sl, ip + mov r2, r0, asr #8 + str r1, [r4], #4 + bne .L5879 +.L5874: + cmp ip, sl + bcs .L5918 + ldr r8, [sp, #8] + rsb r2, ip, sl + mov r3, #0 +.L5890: + add r3, r3, #1 + cmp r2, r3 + str r8, [r4], #4 + bne .L5890 + b .L5918 +.L5866: + sub r7, r7, #1 + cmp sl, #0 + str r7, [sp, #28] + beq .L5918 + mvn r8, #0 + mov r7, #0 +.L5911: + ldr r2, [sp, #28] + ldr r6, [sp, #16] + and r3, r2, r5, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl r6 + ldr ip, [sp, #28] + and lr, r3, #7 + and r1, ip, r0, asr #8 + add ip, r2, r1, lsr #3 + cmp ip, r8 + and r6, r1, #7 + ldrne r1, [sp, #20] + ldrne r2, [sp, #24] + ldrneb r3, [r1, ip] @ zero_extendqisi2 + add r7, r7, #1 + addne r3, r2, r3, asl #6 + strne r3, [sp, #0] + ldr r8, [sp, #0] + add r0, r0, r9 + add r3, r8, lr, asl #3 + ldrb r2, [r3, r6] @ zero_extendqisi2 + ldr lr, [sp, #12] + cmp r2, #0 + orr r1, lr, r2 + ldreq r1, [sp, #8] + cmp sl, r7 + str r1, [r4, #0] + add r5, r5, fp + add r4, r4, #4 + mov r8, ip + bne .L5911 + b .L5918 +.L5865: + sub r6, r7, #1 + and r1, r6, r5, asr #8 + cmp r7, r1 + bls .L5918 + mov r2, r1, lsr #3 + and r3, r1, #7 + ldr ip, [sp, #20] + ldr r1, [sp, #16] + cmp sl, #0 + add lr, ip, r2, asl r1 + ldr r2, [sp, #24] + add r5, r2, r3, asl #3 + beq .L5918 + mov ip, #0 +.L5905: + and r3, r6, r0, asr #8 + ldrb r1, [lr, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r1, asl #6 + ldrb r2, [r3, r5] @ zero_extendqisi2 + ldr r8, [sp, #12] + cmp r2, #0 + ldreq r1, [sp, #8] + orr r3, r8, r2 + add ip, ip, #1 + strne r3, [r4, #0] + streq r1, [r4, #0] + cmp sl, ip + add r0, r0, r9 + add r4, r4, #4 + bne .L5905 + b .L5918 +.L5864: + cmp sl, #0 + beq .L5918 + mov r1, r0, asr #8 + mov r2, r5, asr #8 + cmp r7, r1 + cmphi r7, r2 + movls r3, #0 + movhi r3, #1 + movls ip, r3 + bls .L5871 + b .L5932 +.L5891: + cmp r7, r2 + cmphi r7, r3 + bhi .L5892 +.L5871: + add ip, ip, #1 + ldr lr, [sp, #8] + add r0, r0, r9 + add r5, r5, fp + cmp sl, ip + str lr, [r4, #0] + mov r2, r0, asr #8 + mov r3, r5, asr #8 + add r4, r4, #4 + bne .L5891 + b .L5918 +.L5892: + mov r1, r2 + mov r2, r3 +.L5893: + cmp r7, r2 + cmphi r7, r1 + mvnhi r8, #0 + bhi .L5897 + b .L5919 +.L5896: + cmp r7, r2 + cmphi r7, r1 + bls .L5919 +.L5897: + ldr r6, [sp, #16] + mov r3, r2, lsr #3 + mov r3, r3, asl r6 + and r6, r2, #7 + and r2, r1, #7 + add r1, r3, r1, lsr #3 + cmp r1, r8 + ldrne r8, [sp, #20] + add ip, ip, #1 + ldrneb r3, [r8, r1] @ zero_extendqisi2 + ldrne r8, [sp, #24] + add r0, r0, r9 + addne lr, r8, r3, asl #6 + add r3, lr, r6, asl #3 + ldrb r2, [r3, r2] @ zero_extendqisi2 + ldr r6, [sp, #12] + cmp r2, #0 + ldreq r8, [sp, #8] + orr r3, r6, r2 + streq r8, [r4, #0] + strne r3, [r4, #0] + add r5, r5, fp + cmp sl, ip + mov r8, r1 + add r4, r4, #4 + mov r1, r0, asr #8 + mov r2, r5, asr #8 + bhi .L5896 + b .L5918 +.L5931: + mov ip, #0 +.L5882: + cmp r2, r7 + bcc .L5924 + b .L5874 +.L5885: + cmp r7, r2 + bls .L5874 +.L5924: + ldrb r3, [lr, r2, lsr #3] @ zero_extendqisi2 + and r2, r2, #7 + add r2, r2, r3, asl #6 + ldrb r1, [r2, r5] @ zero_extendqisi2 + ldr r3, [sp, #12] + cmp r1, #0 + ldreq r6, [sp, #8] + orr r2, r3, r1 + add ip, ip, #1 + strne r2, [r4, #0] + streq r6, [r4, #0] + add r0, r0, r9 + cmp sl, ip + add r4, r4, #4 + mov r2, r0, asr #8 + bhi .L5885 + b .L5874 +.L5932: + mov ip, #0 + b .L5893 +.L5934: + .align 2 +.L5933: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_base_alpha, .-render_scanline_affine_base_alpha + .align 2 + .global render_scanline_affine_transparent_alpha + .type render_scanline_affine_transparent_alpha, %function +render_scanline_affine_transparent_alpha: + @ args = 0, pretend = 0, frame = 36 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L5993 + add lr, r0, #7 + ldrh ip, [r5, #80] + sub sp, sp, #36 + mov lr, ip, asr lr + mov ip, ip, asr r0 + and lr, lr, #2 + and ip, ip, #1 + orr ip, ip, lr + mov ip, ip, asl #9 + tst ip, #512 + mov r4, r0 + str ip, [sp, #12] + mov r8, r1 + mov sl, r2 + str r3, [sp, #8] + beq .L5988 + add r3, r5, r0, asl #1 + ldrh r1, [r3, #8] + ldr r3, .L5993+4 + mov r2, r0, asl #4 + sub r0, r0, #2 + ldr r6, [r3, r0, asl #2] + ldr r3, .L5993+8 + sub r2, r2, #32 + add r2, r2, r5 + mov lr, r1, lsr #14 + ldr r5, [r3, r0, asl #2] + ldr r4, .L5993+12 + mov ip, r1, lsr #12 + mov r0, r1, asl #3 + mov r1, r1, asl #12 + and r1, r1, #49152 + ldrsh fp, [r2, #36] + add r1, r1, r4 + ldrsh r9, [r2, #32] + and ip, ip, #2 + and r0, r0, #63488 + str r1, [sp, #20] + ldr r1, [sp, #8] + add r0, r0, r4 + add r2, lr, #7 + mov r3, #1 + cmp fp, #0 + orrne ip, ip, #1 + str r0, [sp, #16] + mov r7, r3, asl r2 + mla r0, r9, r8, r5 + rsb sl, r8, sl + add lr, lr, #4 + add r4, r1, r8, asl #2 + mla r5, fp, r8, r6 + cmp ip, #3 + ldrls pc, [pc, ip, asl #2] + b .L5985 + .p2align 2 +.L5943: + .word .L5939 + .word .L5940 + .word .L5941 + .word .L5942 +.L5941: + sub r6, r7, #1 + and r1, r6, r5, asr #8 + cmp r7, r1 + bls .L5985 + ldr r5, [sp, #16] + ldr ip, [sp, #20] + mov r2, r1, lsr #3 + and r3, r1, #7 + cmp sl, #0 + add lr, r5, r2, asl lr + add r1, ip, r3, asl #3 + beq .L5985 + mov ip, #0 +.L5974: + and r3, r6, r0, asr #8 + ldrb r2, [lr, r3, lsr #3] @ zero_extendqisi2 + and r3, r3, #7 + add r3, r3, r2, asl #6 + ldrb r2, [r3, r1] @ zero_extendqisi2 + add ip, ip, #1 + cmp r2, #0 + ldrne r3, [r4, #0] + ldrne r5, [sp, #12] + add r0, r0, r9 + orrne r3, r5, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r4, #0] + cmp sl, ip + add r4, r4, #4 + bne .L5974 +.L5985: + add sp, sp, #36 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5988: + add sp, sp, #36 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_affine_transparent_color32 +.L5939: + mov r1, r5, asr #8 + cmp r7, r1 + bls .L5985 + ldr r5, [sp, #16] + ldr r6, [sp, #20] + mov r2, r1, lsr #3 + and r3, r1, #7 + cmp sl, #0 + add lr, r5, r2, asl lr + add r1, r6, r3, asl #3 + beq .L5985 + mov ip, r0, asr #8 + cmp r7, ip + movls r5, #0 + bls .L5954 + b .L5991 +.L5952: + cmp r7, r3 + add r4, r4, #4 + bhi .L5953 +.L5954: + add r5, r5, #1 + add r0, r0, r9 + cmp sl, r5 + mov r3, r0, asr #8 + bne .L5952 + b .L5985 +.L5942: + cmp sl, #0 + sub r8, r7, #1 + beq .L5985 + mvn r6, #0 + str r6, [sp, #32] + mov r7, #0 +.L5979: + and r3, r8, r5, asr #8 + mov r2, r3, lsr #3 + mov r2, r2, asl lr + and r1, r8, r0, asr #8 + and r6, r3, #7 + and ip, r1, #7 + add r3, r2, r1, lsr #3 + ldr r1, [sp, #32] + str r3, [sp, #32] + cmp r3, r1 + ldrne r2, [sp, #16] + ldrne r1, [sp, #20] + ldrneb r3, [r2, r3] @ zero_extendqisi2 + add r7, r7, #1 + addne r3, r1, r3, asl #6 + strne r3, [sp, #4] + ldr r2, [sp, #4] + add r0, r0, r9 + add r3, r2, r6, asl #3 + ldrb r2, [r3, ip] @ zero_extendqisi2 + ldr r3, [sp, #12] + cmp r2, #0 + orr r1, r3, r2 + ldrne r3, [r4, #0] + add r5, r5, fp + orrne r3, r1, r3, asl #16 + strne r3, [r4, #0] + cmp sl, r7 + add r4, r4, #4 + bne .L5979 + b .L5985 +.L5940: + cmp sl, #0 + beq .L5985 + mov ip, r0, asr #8 + mov r1, r5, asr #8 + cmp r7, ip + cmphi r7, r1 + movls r3, #0 + movhi r3, #1 + movls r8, r3 + bls .L5947 + b .L5992 +.L5961: + cmp r7, r2 + cmphi r7, r3 + bhi .L5962 +.L5947: + add r8, r8, #1 + add r0, r0, r9 + add r5, r5, fp + cmp sl, r8 + mov r2, r0, asr #8 + mov r3, r5, asr #8 + add r4, r4, #4 + bne .L5961 + b .L5985 +.L5962: + mov ip, r2 + mov r1, r3 +.L5963: + cmp r1, r7 + movcc r3, #0 + movcs r3, #1 + cmp r7, ip + orrls r3, r3, #1 + cmp r3, #0 + mvneq r2, #0 + streq r2, [sp, #28] + beq .L5965 + b .L5985 +.L5966: + cmp r7, r1 + cmphi r7, ip + bls .L5985 +.L5965: + mov r3, r1, lsr #3 + mov r3, r3, asl lr + and r2, ip, #7 + str r2, [sp, #0] + ldr r2, [sp, #28] + add r3, r3, ip, lsr #3 + cmp r3, r2 + ldrne r2, [sp, #16] + str r3, [sp, #28] + ldrneb r3, [r2, r3] @ zero_extendqisi2 + ldrne r2, [sp, #20] + and r6, r1, #7 + addne r3, r2, r3, asl #6 + strne r3, [sp, #24] + ldr r2, [sp, #24] + add r8, r8, #1 + add r3, r2, r6, asl #3 + ldr r6, [sp, #0] + add r0, r0, r9 + ldrb r2, [r3, r6] @ zero_extendqisi2 + ldr r3, [sp, #12] + cmp r2, #0 + orr r6, r3, r2 + ldrne r3, [r4, #0] + add r5, r5, fp + orrne r3, r6, r3, asl #16 + strne r3, [r4, #0] + cmp sl, r8 + mov r1, r5, asr #8 + mov ip, r0, asr #8 + add r4, r4, #4 + bhi .L5966 + b .L5985 +.L5953: + mov ip, r3 +.L5955: + cmp ip, r7 + bcc .L5987 + b .L5985 +.L5957: + cmp r7, ip + bls .L5985 +.L5987: + ldrb r2, [lr, ip, lsr #3] @ zero_extendqisi2 + and r3, ip, #7 + add r3, r3, r2, asl #6 + ldrb r2, [r3, r1] @ zero_extendqisi2 + add r5, r5, #1 + cmp r2, #0 + ldrne r3, [r4, #0] + ldrne r6, [sp, #12] + add r0, r0, r9 + orrne r3, r6, r3, asl #16 + orrne r3, r2, r3 + strne r3, [r4, #0] + cmp sl, r5 + mov ip, r0, asr #8 + add r4, r4, #4 + bhi .L5957 + b .L5985 +.L5992: + mov r8, #0 + b .L5963 +.L5991: + mov r5, #0 + b .L5955 +.L5994: + .align 2 +.L5993: + .word io_registers + .word affine_reference_y + .word affine_reference_x + .word vram + .size render_scanline_affine_transparent_alpha, .-render_scanline_affine_transparent_alpha + .align 2 + .global render_scanline_bitmap_mode3_normal + .type render_scanline_bitmap_mode3_normal, %function +render_scanline_bitmap_mode3_normal: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L6038 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r3, .L6038+4 + ldrh r6, [ip, #36] + ldrh r9, [ip, #32] + ldr ip, .L6038+8 + ldr r4, [r3, #0] + ldr lr, [ip, #0] + mov r3, r9, asl #16 + mov ip, r6, asl #16 + mov sl, r3, asr #16 + mov r7, ip, asr #16 + cmp r6, #0 + mla lr, r7, r0, lr + add r5, r2, r0, asl #1 + rsb r8, r0, r1 + ldr fp, .L6038+12 + mla r0, sl, r0, r4 + beq .L5996 + cmp r8, #0 + ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + mov r6, r0, asr #8 + mov r4, lr, asr #8 + cmp r6, #239 + cmpls r4, #159 + movhi r1, #0 + movls r1, #1 + mov r2, r6 + mov r3, r4 + movhi ip, r1 + bhi .L6002 + b .L6036 +.L6023: + cmp r3, #239 + cmpls r2, #159 + bls .L6024 +.L6002: + add ip, ip, #1 + add r0, r0, sl + add lr, lr, r7 + cmp r8, ip + mov r3, r0, asr #8 + mov r2, lr, asr #8 + add r5, r5, #2 + bne .L6023 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L5996: + mov r3, lr, asr #8 + cmp r3, #159 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + rsb r3, r3, r3, asl #4 + cmp r9, #256 + add r4, fp, r3, asl #5 + mov lr, r0, asr #8 + beq .L6004 + cmp r8, #0 + ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + cmp lr, #239 + movhi ip, r6 + bhi .L6009 + b .L6037 +.L6019: + cmp r2, #239 + bls .L6020 +.L6009: + add ip, ip, #1 + add r0, r0, sl + cmp r8, ip + mov r2, r0, asr #8 + add r5, r5, #2 + bne .L6019 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6024: + mov r4, r2 + mov r6, r3 + mov r2, r3 + mov r3, r4 +.L6025: + cmp r3, #159 + cmpls r2, #239 + bls .L6032 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6027: + cmp r4, #159 + cmpls r6, #239 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6032: + rsb r3, r4, r4, asl #4 + add r3, r6, r3, asl #4 + mov r3, r3, asl #1 + ldrh r2, [r3, fp] + add ip, ip, #1 + mov r3, r2, lsr #10 + and r1, r2, #31 + orr r3, r3, r1, asl #11 + and r2, r2, #992 + add r0, r0, sl + add lr, lr, r7 + orr r3, r3, r2, asl #1 + cmp r8, ip + mov r4, lr, asr #8 + mov r6, r0, asr #8 + strh r3, [r5], #2 @ movhi + bhi .L6027 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6020: + mov lr, r2 + b .L6031 +.L6021: + cmp lr, #239 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6031: + mov r2, lr, asl #1 + ldrh r3, [r2, r4] + add ip, ip, #1 + mov r2, r3, lsr #10 + and r1, r3, #31 + orr r2, r2, r1, asl #11 + and r3, r3, #992 + add r0, r0, sl + orr r2, r2, r3, asl #1 + cmp r8, ip + mov lr, r0, asr #8 + strh r2, [r5], #2 @ movhi + bhi .L6021 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6004: + cmp lr, #0 + sublt r5, r5, lr, asl #1 + addlt r8, r8, lr + movlt lr, r6 + movlt r3, lr + blt .L6012 + addne r4, r4, lr, asl #1 + mov r3, lr +.L6012: + add r3, r8, r3 + cmp r3, #239 + rsbhi r8, lr, #240 + cmp r8, #0 + ldmlefd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + mov r0, #0 +.L6018: + ldrh r3, [r4], #2 + add r0, r0, #1 + mov r2, r3, lsr #10 + and r1, r3, #31 + orr r2, r2, r1, asl #11 + and r3, r3, #992 + orr r2, r2, r3, asl #1 + cmp r8, r0 + strh r2, [r5], #2 @ movhi + bne .L6018 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6036: + mov ip, #0 + b .L6025 +.L6037: + mov ip, r6 + b .L6031 +.L6039: + .align 2 +.L6038: + .word io_registers + .word affine_reference_x + .word affine_reference_y + .word vram + .size render_scanline_bitmap_mode3_normal, .-render_scanline_bitmap_mode3_normal + .align 2 + .global render_scanline_bitmap_mode4_normal + .type render_scanline_bitmap_mode4_normal, %function +render_scanline_bitmap_mode4_normal: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr r3, .L6084 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh ip, [r3, #0] + ldr r4, .L6084+4 + ldrh sl, [r3, #36] + tst ip, #16 + ldrh r9, [r3, #32] + ldr ip, .L6084+8 + ldr r3, .L6084+12 + ldr r5, [ip, #0] + ldr r6, [r3, #0] + mov lr, r9, asl #16 + mov ip, sl, asl #16 + add r3, r4, #40960 + moveq fp, r4 + movne fp, r3 + mov r8, lr, asr #16 + mov r7, ip, asr #16 + cmp sl, #0 + mla r4, r7, r0, r5 + add ip, r2, r0, asl #1 + rsb lr, r0, r1 + mla r5, r8, r0, r6 + beq .L6044 + cmp lr, #0 + ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + mov r1, r5, asr #8 + mov r0, r4, asr #8 + cmp r1, #239 + cmpls r0, #159 + mov r2, r1 + mov r3, r0 + movhi r6, #0 + movls r6, #1 + bhi .L6050 + b .L6082 +.L6071: + cmp r3, #239 + cmpls r2, #159 + bls .L6072 +.L6050: + add r6, r6, #1 + add r5, r5, r8 + add r4, r4, r7 + cmp lr, r6 + mov r3, r5, asr #8 + mov r2, r4, asr #8 + add ip, ip, #2 + bne .L6071 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6044: + mov r3, r4, asr #8 + cmp r3, #159 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + rsb r3, r3, r3, asl #4 + cmp r9, #256 + add r1, fp, r3, asl #4 + mov r0, r5, asr #8 + beq .L6052 + cmp lr, #0 + ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + cmp r0, #239 + movhi r2, sl + bhi .L6057 + b .L6083 +.L6067: + cmp r3, #239 + bls .L6068 +.L6057: + add r2, r2, #1 + add r5, r5, r8 + cmp lr, r2 + mov r3, r5, asr #8 + add ip, ip, #2 + bne .L6067 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6072: + mov r0, r2 + mov r1, r3 + mov r2, r3 + mov r3, r0 +.L6073: + cmp r3, #159 + cmpls r2, #239 + ldrls sl, .L6084+16 + bls .L6074 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6075: + cmp r0, #159 + cmpls r1, #239 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6074: + rsb r3, r0, r0, asl #4 + add r3, fp, r3, asl #4 + ldrb r2, [r3, r1] @ zero_extendqisi2 + add r6, r6, #1 + mov r2, r2, asl #1 + ldrh r2, [r2, sl] + add r5, r5, r8 + add r4, r4, r7 + cmp lr, r6 + mov r0, r4, asr #8 + mov r1, r5, asr #8 + strh r2, [ip], #2 @ movhi + bhi .L6075 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6068: + ldr r4, .L6084+16 + mov r0, r3 + b .L6079 +.L6069: + cmp r0, #239 + ldmhifd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6079: + ldrb r3, [r1, r0] @ zero_extendqisi2 + add r2, r2, #1 + mov r3, r3, asl #1 + ldrh r3, [r3, r4] + add r5, r5, r8 + cmp lr, r2 + mov r0, r5, asr #8 + strh r3, [ip], #2 @ movhi + bhi .L6069 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6052: + cmp r0, #0 + sublt ip, ip, r0, asl #1 + addlt lr, lr, r0 + movlt r0, sl + movlt r3, r0 + blt .L6060 + addne r1, r1, r0 + mov r3, r0 +.L6060: + add r3, lr, r3 + cmp r3, #239 + rsbhi lr, r0, #240 + cmp lr, #0 + ldmlefd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + ldr r0, .L6084+16 + mov r2, #0 +.L6066: + ldrb r3, [r1], #1 @ zero_extendqisi2 + add r2, r2, #1 + mov r3, r3, asl #1 + ldrh r3, [r3, r0] + cmp lr, r2 + strh r3, [ip], #2 @ movhi + bne .L6066 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6082: + mov r6, #0 + b .L6073 +.L6083: + ldr r4, .L6084+16 + mov r2, sl + b .L6079 +.L6085: + .align 2 +.L6084: + .word io_registers + .word vram + .word affine_reference_y + .word affine_reference_x + .word palette_ram_converted + .size render_scanline_bitmap_mode4_normal, .-render_scanline_bitmap_mode4_normal + .align 2 + .global render_scanline_bitmap_mode5_normal + .type render_scanline_bitmap_mode5_normal, %function +render_scanline_bitmap_mode5_normal: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr r3, .L6132 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh ip, [r3, #0] + ldrh r9, [r3, #36] + tst ip, #16 + ldr r4, .L6132+4 + ldrh fp, [r3, #32] + ldr ip, .L6132+8 + ldr r3, .L6132+12 + ldr r5, [ip, #0] + ldr r6, [r3, #0] + mov ip, r9, asl #16 + mov lr, fp, asl #16 + add r3, r4, #40960 + movne r4, r3 + mov r7, ip, asr #16 + sub sp, sp, #4 + mov sl, lr, asr #16 + cmp r9, #0 + str r4, [sp, #0] + add ip, r2, r0, asl #1 + mla r4, r7, r0, r5 + rsb r8, r0, r1 + mla r0, sl, r0, r6 + beq .L6090 + cmp r8, #0 + beq .L6122 + mov lr, r0, asr #8 + mov r5, r4, asr #8 + cmp lr, #159 + cmpls r5, #127 + movhi r1, #0 + movls r1, #1 + mov r2, lr + mov r3, r5 + movhi r6, r1 + bhi .L6096 + b .L6130 +.L6117: + cmp r3, #159 + cmpls r2, #127 + bls .L6118 +.L6096: + add r6, r6, #1 + add r0, r0, sl + add r4, r4, r7 + cmp r8, r6 + mov r3, r0, asr #8 + mov r2, r4, asr #8 + add ip, ip, #2 + bne .L6117 +.L6122: + add sp, sp, #4 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6090: + mov r3, r4, asr #8 + cmp r3, #127 + bhi .L6122 + ldr r1, [sp, #0] + add r3, r3, r3, asl #2 + cmp fp, #256 + add lr, r1, r3, asl #6 + mov r5, r0, asr #8 + beq .L6098 + cmp r8, #0 + beq .L6122 + cmp r5, #159 + movhi r4, r9 + bhi .L6103 + b .L6131 +.L6113: + cmp r2, #159 + bls .L6114 +.L6103: + add r4, r4, #1 + add r0, r0, sl + cmp r8, r4 + mov r2, r0, asr #8 + add ip, ip, #2 + bne .L6113 + b .L6122 +.L6118: + mov r5, r2 + mov lr, r3 + mov r2, r3 + mov r3, r5 +.L6119: + cmp r3, #127 + cmpls r2, #159 + bls .L6126 + b .L6122 +.L6121: + cmp r5, #127 + cmpls lr, #159 + bhi .L6122 +.L6126: + add r3, r5, r5, asl #2 + add r3, lr, r3, asl #5 + ldr r1, [sp, #0] + mov r3, r3, asl #1 + ldrh r2, [r3, r1] + add r6, r6, #1 + mov r3, r2, lsr #10 + and r1, r2, #31 + orr r3, r3, r1, asl #11 + and r2, r2, #992 + add r0, r0, sl + add r4, r4, r7 + orr r3, r3, r2, asl #1 + cmp r8, r6 + mov r5, r4, asr #8 + mov lr, r0, asr #8 + strh r3, [ip], #2 @ movhi + bhi .L6121 + b .L6122 +.L6114: + mov r5, r2 + b .L6125 +.L6115: + cmp r5, #159 + bhi .L6122 +.L6125: + mov r2, r5, asl #1 + ldrh r3, [r2, lr] + add r4, r4, #1 + mov r2, r3, lsr #10 + and r1, r3, #31 + orr r2, r2, r1, asl #11 + and r3, r3, #992 + add r0, r0, sl + orr r2, r2, r3, asl #1 + cmp r8, r4 + mov r5, r0, asr #8 + strh r2, [ip], #2 @ movhi + bhi .L6115 + b .L6122 +.L6098: + cmp r5, #0 + sublt ip, ip, r5, asl #1 + addlt r8, r8, r5 + movlt r5, r9 + movlt r3, r5 + blt .L6106 + addne lr, lr, r5, asl #1 + mov r3, r5 +.L6106: + add r3, r8, r3 + cmp r3, #159 + rsbhi r8, r5, #160 + cmp r8, #0 + ble .L6122 + mov r0, #0 +.L6112: + ldrh r3, [lr], #2 + add r0, r0, #1 + mov r2, r3, lsr #10 + and r1, r3, #31 + orr r2, r2, r1, asl #11 + and r3, r3, #992 + orr r2, r2, r3, asl #1 + cmp r8, r0 + strh r2, [ip], #2 @ movhi + bne .L6112 + b .L6122 +.L6130: + mov r6, #0 + b .L6119 +.L6131: + mov r4, r9 + b .L6125 +.L6133: + .align 2 +.L6132: + .word io_registers + .word vram + .word affine_reference_y + .word affine_reference_x + .size render_scanline_bitmap_mode5_normal, .-render_scanline_bitmap_mode5_normal + .align 2 + .global render_scanline_obj_normal_1D + .type render_scanline_obj_normal_1D, %function +render_scanline_obj_normal_1D: + @ args = 0, pretend = 0, frame = 104 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L6976 + sub sp, sp, #104 + ldrh ip, [ip, #6] + add r0, r0, r0, asl #2 + add r0, ip, r0, asl #5 + str ip, [sp, #28] + ldr ip, .L6976+4 + str r1, [sp, #8] + ldr ip, [ip, r0, asl #2] + str r2, [sp, #4] + str ip, [sp, #32] + cmp ip, #0 + ldr ip, .L6976+8 + str r3, [sp, #0] + add r0, ip, r0, asl #7 + str r0, [sp, #36] + beq .L6922 + add r0, r3, r1, asl #1 + rsb r1, r1, r2 + mov r2, #0 + str r0, [sp, #76] + str r1, [sp, #100] + str r2, [sp, #24] + mov r4, r2 +.L6137: + ldr r5, [sp, #36] + ldr r6, .L6976+12 + ldrb r3, [r4, r5] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh lr, [r3, r6] + add r3, r3, r6 + ldrh r1, [r3, #2] + mov r4, lr, lsr #12 + and r2, r4, #12 + orr r0, r2, r1, lsr #14 + and ip, lr, #255 + mov r2, r1, asl #23 + cmp ip, #160 + ldrh r6, [r3, #4] + mov r5, r2, asr #23 + ldr r3, .L6976+16 + ldr r2, .L6976+20 + subgt ip, ip, #256 + tst lr, #256 + ldr r7, [r2, r0, asl #2] + ldr sl, [r3, r0, asl #2] + beq .L6140 + tst lr, #8192 + beq .L6142 + mov r3, r1, lsr #4 + ldr r4, .L6976+12 + and r3, r3, #992 + add r3, r3, r4 + tst lr, #512 + ldrh lr, [r3, #30] + add r2, r7, r7, lsr #31 + add r1, sl, sl, lsr #31 + str lr, [sp, #12] + mov lr, r2, asr #1 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + movne r0, lr, asl #1 + strne r0, [sp, #48] + moveq r9, r7 + streq lr, [sp, #48] + moveq r0, r4 + movne r9, r7, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L6147 + rsb r2, r5, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L6149 + ldr r3, [sp, #48] + ldr r5, [sp, #8] + rsb r3, r2, r3 + str r3, [sp, #48] +.L6147: + ldr r2, [sp, #4] + add r3, r5, r9 + cmp r3, r2 + blt .L6151 + rsb r9, r5, r2 + cmp r9, #0 + ble .L6149 +.L6151: + add r0, ip, r0 + ldr ip, [sp, #12] + mov r2, r1, asl #16 + mov lr, lr, asl #8 + mov r1, ip, asl #16 + mov r3, r8, asl #16 + mov ip, r1, asr #16 + str lr, [sp, #84] + ldr r1, [sp, #28] + ldr lr, [sp, #0] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + cmp fp, #0 + add r8, lr, r5, asl #1 + str r3, [sp, #40] + str r2, [sp, #44] + mov r4, r4, asl #8 + rsb lr, r0, r1 + bne .L6153 + mla r3, lr, ip, r4 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L6149 + cmp r7, #0 + add r3, r7, #7 + movge r3, r7 + mov r3, r3, asr #3 + mov r2, r6, asl #22 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L6976+24 + add r0, r0, ip, asl #2 + cmp r9, #0 + add r4, r3, r0, asl #3 + ble .L6149 + ldr r3, [sp, #44] + ldr r2, [sp, #48] + ldr r5, [sp, #40] + mul r3, lr, r3 + mul r2, r5, r2 + ldr r6, [sp, #84] + rsb r3, r2, r3 + add r0, r6, r3 + mov lr, r0, asr #8 + cmp lr, r7 + movcs ip, fp + bcs .L6159 + b .L6972 +.L6160: + cmp lr, r7 + bcc .L6936 +.L6159: + ldr lr, [sp, #40] + add ip, ip, #1 + add r0, r0, lr + cmp r9, ip + mov lr, r0, asr #8 + add r8, r8, #2 + bne .L6160 +.L6149: + ldr lr, [sp, #24] + ldr r0, [sp, #32] + add lr, lr, #1 + cmp lr, r0 + str lr, [sp, #24] + beq .L6922 +.L6954: + ldr r4, [sp, #24] + b .L6137 +.L6140: + ldr lr, [sp, #28] + tst r1, #8192 + rsb ip, ip, lr + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r1, asl #19 + and r3, r4, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L6149 + .p2align 2 +.L6221: + .word .L6217 + .word .L6218 + .word .L6219 + .word .L6220 +.L6217: + cmp r7, #0 + add r3, r7, #7 + mov r2, r6, asl #22 + movge r3, r7 + mov r8, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r8, r3, r2 + and r1, ip, #7 + add r1, r1, r0, asl #3 + ldr r0, [sp, #8] + ldr r3, .L6976+24 + cmp r5, r0 + mov r2, r6, lsr #8 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L6949 + ldr r2, [sp, #4] + add r3, r5, r7 + cmp r2, r3 + bhi .L6303 + rsb r8, r5, r2 + cmp r8, #0 + ble .L6149 + ldr r3, [sp, #0] + movs r7, r8, lsr #3 + add r2, r3, r5, asl #1 + beq .L6306 + ldr r6, .L6976+36 + mov r4, r2 + mov r5, r0 + mov ip, #0 +.L6308: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L6309 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi +.L6309: + add ip, ip, #1 + cmp ip, r7 + add r5, r5, #32 + add r4, r4, #16 + bne .L6308 + add r0, r0, r7, asl #5 + add r2, r2, r7, asl #4 +.L6306: + ands r4, r8, #7 + beq .L6149 + ldr r0, [r0, #0] + ldr r5, .L6976+36 + mov lr, #0 +.L6328: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov ip, lr, asl #1 + add lr, lr, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r4 + mov r0, r0, lsr #4 + bne .L6328 + b .L6149 +.L6218: + cmp r7, #0 + add r3, r7, #7 + mov r2, r6, asl #22 + movge r3, r7 + mov r1, ip, lsr #3 + mov r8, r3, asr #3 + mov r2, r2, lsr #22 + mla r0, r8, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + and r2, ip, #7 + ldr ip, [sp, #8] + add r0, r0, r3, asr #3 + ldr r3, .L6976+24 + add r2, r2, r0, asl #3 + mov r1, r6, lsr #8 + cmp r5, ip + add r0, r3, r2, asl #2 + and r1, r1, #240 + blt .L6950 + ldr r2, [sp, #4] + add r3, r5, r7 + cmp r2, r3 + bhi .L6433 + rsb r8, r5, r2 + cmp r8, #0 + ble .L6149 + ldr r3, [sp, #0] + movs r7, r8, lsr #3 + add r2, r3, r5, asl #1 + beq .L6436 + ldr r6, .L6976+36 + mov r4, r2 + mov r5, r0 + mov ip, #0 +.L6438: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L6439 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi +.L6439: + add ip, ip, #1 + cmp ip, r7 + sub r5, r5, #32 + add r4, r4, #16 + bne .L6438 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #4 +.L6436: + ands r4, r8, #7 + beq .L6149 + ldr r0, [r0, #0] + ldr r5, .L6976+36 + mov lr, #0 +.L6458: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov ip, lr, asl #1 + add lr, lr, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r4 + mov r0, r0, asl #4 + bne .L6458 + b .L6149 +.L6219: + cmp r7, #0 + add r3, r7, #7 + mov r1, r6, asl #22 + movge r3, r7 + mov r2, ip, lsr #3 + mov r6, r3, asr #3 + mov r1, r1, lsr #22 + mov r2, r2, asl #1 + mla r0, r2, r6, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr ip, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L6976+24 + cmp r5, ip + add r1, r0, r3 + blt .L6951 + ldr ip, [sp, #4] + add r3, r5, r7 + cmp ip, r3 + bhi .L6638 + rsb r8, r5, ip + cmp r8, #0 + ble .L6149 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r2, lr, r5, asl #1 + beq .L6641 + ldr r3, .L6976+32 + ldr r6, .L6976+36 + add r0, r0, r3 + mov r4, r2 + mov r5, r1 + mov ip, #0 +.L6643: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L6644 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi +.L6644: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L6653 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi +.L6653: + add ip, ip, #1 + cmp r7, ip + add r5, r5, #64 + add r4, r4, #16 + add r0, r0, #64 + bne .L6643 + add r1, r1, r7, asl #6 + add r2, r2, r7, asl #4 +.L6641: + ands lr, r8, #7 + beq .L6149 + cmp lr, #3 + ldrls r0, [r1, #0] + bls .L6676 + ldr r0, [r1, #0] + cmp r0, #0 + beq .L6666 + ands r3, r0, #255 + ldrne r4, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, r0, lsr #8 + ands r3, r3, #255 + ldrne r5, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r2, #2] @ movhi + mov r3, r0, lsr #16 + ands r3, r3, #255 + ldrne r6, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r2, #4] @ movhi + movs r3, r0, lsr #24 + ldrne r7, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r2, #6] @ movhi +.L6666: + subs lr, lr, #4 + ldr r0, [r1, #4] + addne r2, r2, #8 + beq .L6149 +.L6676: + mov r1, #0 +.L6677: + ands r3, r0, #255 + ldrne r4, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov ip, r1, asl #1 + add r1, r1, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r1 + mov r0, r0, lsr #8 + bhi .L6677 + b .L6149 +.L6220: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r1, ip, lsr #3 + mov r8, r2, asr #3 + mov r3, r3, asr #3 + mla r0, r8, r1, r3 + mov r2, r6, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + and r3, ip, #7 + add r3, r3, r2, asl #2 + ldr ip, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L6976+24 + cmp r5, ip + add r1, r0, r3 + blt .L6952 + ldr ip, [sp, #4] + add r3, r5, r7 + cmp r3, ip + bcc .L6858 + rsb r8, r5, ip + cmp r8, #0 + ble .L6149 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add sl, lr, r5, asl #1 + beq .L6861 + ldr r3, .L6976+28 + ldr r6, .L6976+36 + add r0, r0, r3 + mov r4, sl + mov r5, r1 + mov ip, #0 +.L6863: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L6864 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi +.L6864: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L6873 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi +.L6873: + add ip, ip, #1 + cmp ip, r7 + sub r5, r5, #64 + add r4, r4, #16 + sub r0, r0, #64 + bne .L6863 + rsb r3, r7, r7, asl #26 + add r1, r1, r3, asl #6 + add sl, sl, r7, asl #4 +.L6861: + ands ip, r8, #7 + beq .L6149 + cmp ip, #3 + ldrls r2, [r1, #4] + bls .L6896 + ldr r2, [r1, #4] + cmp r2, #0 + beq .L6886 + ands r3, r2, #255 + ldrne r0, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [sl, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [sl, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [sl, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r6, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [sl, #0] @ movhi +.L6886: + subs ip, ip, #4 + ldr r2, [r1, #0] + addne sl, sl, #8 + beq .L6149 +.L6896: + mov r1, #0 +.L6897: + movs r3, r2, lsr #24 + ldrne r7, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r0, r1, asl #1 + add r1, r1, #1 + strneh r3, [r0, sl] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L6897 + b .L6149 +.L6142: + mov r3, r1, lsr #4 + ldr r4, .L6976+12 + and r3, r3, #992 + add r3, r3, r4 + tst lr, #512 + ldrh lr, [r3, #30] + add r2, r7, r7, lsr #31 + add r1, sl, sl, lsr #31 + str lr, [sp, #20] + mov lr, r2, asr #1 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r7 + moveq r9, lr + moveq r0, r4 + movne fp, r7, asl #1 + movne r9, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + str r3, [sp, #16] + bge .L6180 + rsb r2, r5, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L6149 + ldr r5, [sp, #8] + rsb r9, r2, r9 +.L6180: + ldr r2, [sp, #4] + add r3, r5, fp + cmp r3, r2 + blt .L6183 + rsb fp, r5, r2 + cmp fp, #0 + ble .L6149 +.L6183: + add ip, ip, r0 + ldr r0, [sp, #20] + mov r2, r1, asl #16 + mov r1, r0, asl #16 + ldr r0, [sp, #16] + mov r2, r2, asr #16 + mov r1, r1, asr #16 + mov r3, r8, asl #16 + cmp r0, #0 + str r2, [sp, #60] + mov r0, r6, lsr #8 + str r1, [sp, #68] + ldr r2, [sp, #28] + ldr r1, [sp, #0] + mov lr, lr, asl #8 + mov r3, r3, asr #16 + and r0, r0, #240 + str lr, [sp, #80] + str r3, [sp, #56] + mov r4, r4, asl #8 + add r8, r1, r5, asl #1 + rsb lr, ip, r2 + str r0, [sp, #96] + bne .L6185 + ldr r3, [sp, #68] + mla r3, lr, r3, r4 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L6149 + cmp r7, #0 + add r3, r7, #7 + mov r2, r6, asl #22 + movge r3, r7 + mov r1, r0, lsr #3 + mov r3, r3, asr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L6976+24 + add r0, r0, ip, asl #3 + cmp fp, #0 + add r1, r3, r0, asl #2 + ble .L6149 + ldr r3, [sp, #60] + ldr r2, [sp, #56] + mul r3, lr, r3 + mul r2, r9, r2 + ldr r4, [sp, #80] + rsb r3, r2, r3 + add r0, r4, r3 + mov lr, r0, asr #8 + cmp lr, r7 + ldrcs r4, [sp, #16] + bcs .L6191 + b .L6973 +.L6192: + cmp lr, r7 + bcc .L6938 +.L6191: + ldr r5, [sp, #56] + add r4, r4, #1 + add r0, r0, r5 + cmp fp, r4 + mov lr, r0, asr #8 + add r8, r8, #2 + bne .L6192 + ldr lr, [sp, #24] + ldr r0, [sp, #32] + add lr, lr, #1 + cmp lr, r0 + str lr, [sp, #24] + bne .L6954 +.L6922: + add sp, sp, #104 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6153: + cmp r7, #0 + add r1, r7, #7 + mov r2, r6, asl #22 + movge r1, r7 + ldr r3, .L6976+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp r9, #0 + str r2, [sp, #92] + str r1, [sp, #52] + ble .L6149 + mov r3, fp, asl #16 + mov fp, r3, asr #16 + ldr r5, [sp, #40] + ldr r3, [sp, #44] + ldr r1, [sp, #48] + ldr r0, [sp, #48] + mul r2, lr, ip + mul r3, lr, r3 + mul r0, r5, r0 + mul r1, fp, r1 + ldr r6, [sp, #84] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add r4, r4, r2 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + cmp ip, r7 + cmpcc lr, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L6169 + b .L6974 +.L6170: + cmp ip, r7 + cmpcc lr, sl + bcc .L6171 +.L6169: + ldr ip, [sp, #40] + add r6, r6, #1 + add r5, r5, ip + add r4, r4, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + add r8, r8, #2 + bne .L6170 + b .L6149 +.L6185: + cmp r7, #0 + add r1, r7, #7 + mov r2, r6, asl #22 + movge r1, r7 + ldr r3, .L6976+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp fp, #0 + str r2, [sp, #88] + str r1, [sp, #72] + ble .L6149 + ldr r5, [sp, #16] + ldr r2, [sp, #68] + mov r3, r5, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #64] + ldr r1, [sp, #64] + ldr r3, [sp, #60] + ldr r0, [sp, #56] + mul r2, lr, r2 + mul r3, lr, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr r6, [sp, #80] + rsb r2, r1, r2 + rsb r3, r0, r3 + add r5, r6, r3 + add r4, r4, r2 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + cmp lr, r7 + cmpcc r2, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L6204 + b .L6975 +.L6205: + cmp lr, r7 + cmpcc r2, sl + bcc .L6207 +.L6204: + ldr lr, [sp, #64] + ldr ip, [sp, #56] + add r6, r6, #1 + add r4, r4, lr + add r5, r5, ip + cmp fp, r6 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + add r8, r8, #2 + bne .L6205 + b .L6149 +.L6957: + ldr r1, [sp, #88] + and r0, r2, #7 + add r0, r1, r0, asl #2 + mov r3, r2, asr #3 + and r1, r2, #7 + ldr r2, [sp, #72] + mov ip, lr, asr #1 + mul r2, r3, r2 + and r9, ip, #3 + ldr ip, [sp, #88] + mov r3, lr, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, lr, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst lr, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, r9] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + ldr r2, [sp, #96] + cmp r0, #0 + orr r3, r0, r2 + ldrne ip, .L6976+36 + mov r3, r3, asl #1 + ldr lr, [sp, #56] + ldrneh r3, [r3, ip] + ldr r1, [sp, #64] + add r6, r6, #1 + strneh r3, [r8, #0] @ movhi + add r5, r5, lr + add r4, r4, r1 + cmp fp, r6 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + add r8, r8, #2 + ble .L6149 +.L6207: + cmp r2, sl + cmpcc lr, r7 + bcc .L6957 + b .L6149 +.L6194: + cmp lr, r7 + bcs .L6149 +.L6938: + mov r3, lr, asr #1 + and r6, r3, #3 + mov r3, lr, asr #3 + mov r3, r3, asl #5 + mov r2, lr, asr #1 + tst lr, #1 + add ip, r3, r1 + and r5, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r5] @ zero_extendqisi2 + ldrneb r3, [ip, r6] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + ldr ip, [sp, #96] + cmp r2, #0 + orr r3, r2, ip + ldrne r2, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldr r6, [sp, #56] + add r4, r4, #1 + strneh r3, [r8, #0] @ movhi + add r0, r0, r6 + cmp fp, r4 + mov lr, r0, asr #8 + add r8, r8, #2 + bgt .L6194 + b .L6149 +.L6162: + cmp lr, r7 + bcs .L6149 +.L6936: + ldr r1, [sp, #40] + mov r3, lr, asr #3 + add r3, r4, r3, asl #6 + add r0, r0, r1 + and r1, lr, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + add ip, ip, #1 + cmp r2, #0 + ldrne r3, .L6976+36 + mov r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov lr, r0, asr #8 + strneh r2, [r8, #0] @ movhi + cmp r9, ip + add r8, r8, #2 + bgt .L6162 + b .L6149 +.L6977: + .align 2 +.L6976: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 + .word vram+65472 + .word vram+65600 + .word palette_ram_converted+512 +.L6952: + rsb r0, r5, ip + rsb r4, r0, r7 + cmp r4, #0 + ble .L6149 + ldr lr, [sp, #4] + add r3, r5, r7 + cmp lr, r3 + bhi .L6705 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r7, r1, r3, asl #6 + bne .L6707 + ldr r6, [sp, #100] + ldr r5, [sp, #76] +.L6709: + movs r4, r6, lsr #3 + beq .L6767 + ldr lr, .L6976+36 + mov r1, r5 + mov r0, r7 + mov ip, #0 +.L6769: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L6770 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi +.L6770: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L6779 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #10] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #8] @ movhi +.L6779: + add ip, ip, #1 + cmp ip, r4 + sub r0, r0, #64 + add r1, r1, #16 + bne .L6769 + rsb r3, r4, r4, asl #26 + add r7, r7, r3, asl #6 + add r5, r5, r4, asl #4 +.L6767: + ands ip, r6, #7 + beq .L6149 + cmp ip, #3 + ldrls r2, [r7, #4] + bls .L6802 + ldr r2, [r7, #4] + cmp r2, #0 + beq .L6792 + ands r3, r2, #255 + ldrne lr, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r5, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r5, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r1] + strneh r3, [r5, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r2, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r5, #0] @ movhi +.L6792: + subs ip, ip, #4 + ldr r2, [r7, #0] + addne r5, r5, #8 + beq .L6149 +.L6802: + mov r1, #0 +.L6803: + movs r3, r2, lsr #24 + ldrne r4, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r0, r1, asl #1 + add r1, r1, #1 + strneh r3, [r0, r5] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L6803 + b .L6149 +.L6951: + rsb r0, r5, ip + rsb r4, r0, r7 + cmp r4, #0 + ble .L6149 + ldr lr, [sp, #4] + add r3, r5, r7 + cmp lr, r3 + bhi .L6485 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add r7, r1, r3, asl #6 + bne .L6487 + ldr r6, [sp, #100] + ldr r5, [sp, #76] +.L6489: + movs r4, r6, lsr #3 + beq .L6547 + ldr lr, .L6976+36 + mov r1, r5 + mov r0, r7 + mov ip, #0 +.L6549: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L6550 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #6] @ movhi +.L6550: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L6559 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #14] @ movhi +.L6559: + add ip, ip, #1 + cmp r4, ip + add r0, r0, #64 + add r1, r1, #16 + bne .L6549 + add r7, r7, r4, asl #6 + add r5, r5, r4, asl #4 +.L6547: + ands ip, r6, #7 + beq .L6149 + cmp ip, #3 + ldrls r1, [r7, #0] + bls .L6582 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L6572 + ands r3, r2, #255 + ldrne lr, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r5, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r5, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r1] + strneh r3, [r5, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r5, #6] @ movhi +.L6572: + subs ip, ip, #4 + ldr r1, [r7, #4] + addne r5, r5, #8 + beq .L6149 +.L6582: + mov r2, #0 +.L6583: + ands r3, r1, #255 + ldrne r4, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r0, r2, asl #1 + add r2, r2, #1 + strneh r3, [r0, r5] @ movhi + cmp ip, r2 + mov r1, r1, lsr #8 + bhi .L6583 + b .L6149 +.L6950: + rsb lr, r5, ip + rsb ip, lr, r7 + cmp ip, #0 + ble .L6149 + ldr r2, [sp, #4] + add r3, r5, r7 + cmp r2, r3 + bhi .L6355 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub r0, r0, r3, asl #5 + bne .L6357 + ldr r2, [sp, #100] + ldr sl, [sp, #76] +.L6359: + movs r8, r2, lsr #3 + beq .L6376 + ldr r7, .L6976+36 + mov r4, sl + mov r5, r0 + mov r6, #0 +.L6378: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L6379 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #0] @ movhi +.L6379: + add r6, r6, #1 + cmp r6, r8 + sub r5, r5, #32 + add r4, r4, #16 + bne .L6378 + rsb r3, r8, r8, asl #27 + add r0, r0, r3, asl #5 + add sl, sl, r8, asl #4 +.L6376: + ands lr, r2, #7 + beq .L6149 + ldr r0, [r0, #0] + ldr r4, .L6976+36 + mov ip, #0 +.L6398: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, sl] @ movhi + cmp ip, lr + mov r0, r0, asl #4 + bne .L6398 + b .L6149 +.L6949: + ldr r2, [sp, #8] + rsb lr, r5, r2 + rsb r4, lr, r7 + cmp r4, #0 + ble .L6149 + add r3, r5, r7 + ldr r5, [sp, #4] + cmp r5, r3 + bhi .L6225 + mov r3, lr, lsr #3 + mov r2, r3, asl #5 + ands r3, lr, #7 + add r6, r0, r2 + bne .L6227 + ldr r8, [sp, #100] + ldr r7, [sp, #76] +.L6229: + movs r5, r8, lsr #3 + beq .L6246 + ldr r4, .L6976+36 + mov ip, r7 + mov r0, r6 + mov lr, #0 +.L6248: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L6249 + ands r3, r2, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #14] @ movhi +.L6249: + add lr, lr, #1 + cmp r5, lr + add r0, r0, #32 + add ip, ip, #16 + bne .L6248 + add r6, r6, r5, asl #5 + add r7, r7, r5, asl #4 +.L6246: + ands lr, r8, #7 + beq .L6149 + ldr r2, [r6, #0] + ldr r4, .L6976+36 + mov r0, #0 +.L6268: + ands r3, r2, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov ip, r0, asl #1 + add r0, r0, #1 + strneh r3, [ip, r7] @ movhi + cmp r0, lr + mov r2, r2, lsr #4 + bne .L6268 + b .L6149 +.L6974: + mov r6, #0 +.L6171: + cmp lr, sl + movcc r3, #0 + movcs r3, #1 + cmp r7, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L6937 + b .L6149 +.L6172: + cmp lr, sl + cmpcc ip, r7 + bcs .L6149 +.L6937: + ldr r0, [sp, #40] + and r3, lr, #7 + mov r2, ip, asr #3 + ldr r1, [sp, #92] + mov r3, r3, asl #3 + add r5, r5, r0 + add r3, r3, r2, asl #6 + ldr r0, [sp, #52] + mov r2, lr, asr #3 + add r3, r3, r1 + mla r0, r2, r0, r3 + and r1, ip, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + add r6, r6, #1 + cmp r3, #0 + ldrne r2, .L6976+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + add r4, r4, fp + strneh r3, [r8, #0] @ movhi + cmp r9, r6 + mov lr, r4, asr #8 + mov ip, r5, asr #8 + add r8, r8, #2 + bgt .L6172 + b .L6149 +.L6433: + cmp r8, #0 + beq .L6149 + ldr r6, [sp, #0] + ldr r4, .L6976+36 + add r2, r6, r5, asl #1 + mov ip, #0 + b .L6463 +.L6958: + sub r0, r0, #32 + add r2, r2, #16 +.L6463: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L6464 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi +.L6464: + add ip, ip, #1 + cmp r8, ip + bne .L6958 + b .L6149 +.L6858: + cmp r8, #0 + beq .L6149 + ldr ip, [sp, #0] + ldr r3, .L6976+28 + ldr r4, .L6976+36 + add r2, ip, r5, asl #1 + add r0, r0, r3 + mov ip, #0 + b .L6902 +.L6959: + sub r1, r1, #64 + add r2, r2, #16 +.L6902: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L6903 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi +.L6903: + ldr lr, [r1, #0] + cmp lr, #0 + beq .L6912 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi +.L6912: + add ip, ip, #1 + cmp r8, ip + sub r0, r0, #64 + bne .L6959 + b .L6149 +.L6303: + cmp r8, #0 + beq .L6149 + ldr r6, [sp, #0] + ldr r4, .L6976+36 + add r2, r6, r5, asl #1 + mov ip, #0 + b .L6333 +.L6960: + add r0, r0, #32 + add r2, r2, #16 +.L6333: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L6334 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi +.L6334: + add ip, ip, #1 + cmp r8, ip + bne .L6960 + b .L6149 +.L6638: + cmp r6, #0 + beq .L6149 + ldr r3, .L6976+32 + ldr r7, [sp, #0] + ldr r4, .L6976+36 + add r0, r0, r3 + add r2, r7, r5, asl #1 + mov ip, #0 + b .L6682 +.L6961: + add r1, r1, #64 + add r2, r2, #16 +.L6682: + ldr lr, [r1, #0] + cmp lr, #0 + beq .L6683 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi +.L6683: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L6692 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi +.L6692: + add ip, ip, #1 + cmp r6, ip + add r0, r0, #64 + bne .L6961 + b .L6149 +.L6485: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r0, r1, r3, asl #6 + ldreq r1, [sp, #76] + beq .L6589 + cmp r2, #3 + rsb lr, r2, #8 + bhi .L6962 + subs r5, lr, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #76] + beq .L6602 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + ldr r6, .L6976+36 + mov ip, #0 +.L6603: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #76] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r7] @ movhi + cmp ip, r5 + mov r2, r2, lsr #8 + bne .L6603 + ldr ip, [sp, #76] + add r3, ip, lr, asl #1 + sub r1, r3, #8 +.L6602: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L6608 + ands r3, r2, #255 + ldrne lr, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r7, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r1, #6] @ movhi +.L6608: + add r1, r1, #8 +.L6594: + add r0, r0, #64 +.L6589: + movs r4, r4, lsr #3 + beq .L6149 + ldr ip, .L6976+36 + mov lr, #0 + b .L6618 +.L6963: + add r0, r0, #64 + add r1, r1, #16 +.L6618: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L6619 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #6] @ movhi +.L6619: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L6628 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #14] @ movhi +.L6628: + add lr, lr, #1 + cmp r4, lr + bne .L6963 + b .L6149 +.L6355: + ands r2, lr, #7 + mov r3, lr, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r4, [sp, #76] + beq .L6404 + rsbs r6, r2, #8 + ldr lr, [r0, #0] + ldreq r4, [sp, #76] + beq .L6407 + mov r3, r2, asl #2 + mov lr, lr, asl r3 + ldr r2, .L6976+36 + mov r5, #0 +.L6408: + movs r3, lr, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldrne r7, [sp, #76] + mov r4, r5, asl #1 + add r5, r5, #1 + strneh r3, [r4, r7] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L6408 + ldr lr, [sp, #76] + add r4, lr, r6, asl #1 +.L6407: + sub r0, r0, #32 +.L6404: + movs r5, ip, lsr #3 + beq .L6149 + ldr r2, .L6976+36 + mov ip, #0 + b .L6414 +.L6964: + sub r0, r0, #32 + add r4, r4, #16 +.L6414: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L6415 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #0] @ movhi +.L6415: + add ip, ip, #1 + cmp ip, r5 + bne .L6964 + b .L6149 +.L6705: + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r2, r1, r3, asl #6 + ldreq r0, [sp, #76] + beq .L6809 + cmp ip, #3 + rsb lr, ip, #8 + bhi .L6965 + subs r5, lr, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #76] + beq .L6822 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + ldr r6, .L6976+36 + mov ip, #0 +.L6823: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #76] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp r5, ip + mov r1, r1, asl #8 + bne .L6823 + ldr ip, [sp, #76] + add r3, ip, lr, asl #1 + sub r0, r3, #8 +.L6822: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L6828 + ands r3, r1, #255 + ldrne lr, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r7, .L6976+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #0] @ movhi +.L6828: + add r0, r0, #8 +.L6814: + sub r2, r2, #64 +.L6809: + movs r4, r4, lsr #3 + beq .L6149 + ldr ip, .L6976+36 + mov lr, #0 + b .L6838 +.L6966: + sub r2, r2, #64 + add r0, r0, #16 +.L6838: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L6839 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #0] @ movhi +.L6839: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L6848 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #10] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #8] @ movhi +.L6848: + add lr, lr, #1 + cmp lr, r4 + bne .L6966 + b .L6149 +.L6225: + mov r3, lr, lsr #3 + mov r2, r3, asl #5 + ands r3, lr, #7 + ldreq ip, [sp, #76] + add lr, r0, r2 + beq .L6274 + rsbs r5, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #76] + beq .L6277 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + ldr r6, .L6976+36 + mov ip, #0 +.L6278: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #76] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r7] @ movhi + cmp ip, r5 + mov r0, r0, lsr #4 + bne .L6278 + ldr r0, [sp, #76] + add ip, r0, r5, asl #1 +.L6277: + add lr, lr, #32 +.L6274: + movs r5, r4, lsr #3 + beq .L6149 + ldr r0, .L6978 + mov r4, #0 + b .L6284 +.L6967: + add lr, lr, #32 + add ip, ip, #16 +.L6284: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L6285 + ands r3, r2, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #14] @ movhi +.L6285: + add r4, r4, #1 + cmp r4, r5 + bne .L6967 + b .L6149 +.L6487: + ldr r0, [sp, #100] + rsb lr, ip, #8 + cmp r0, lr + blt .L6968 + cmp ip, #3 + bls .L6520 + cmp lr, #0 + ldr r2, [r7, #4] + ldreq r5, [sp, #76] + beq .L6524 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + ldr ip, .L6978 + mov r0, #0 +.L6525: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #76] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp lr, r0 + mov r1, r1, lsr #8 + bne .L6525 + ldr r6, [sp, #76] + add r5, r6, lr, asl #1 +.L6524: + ldr ip, [sp, #100] + add r7, r7, #64 + rsb r6, lr, ip + b .L6489 +.L6357: + ldr r3, [sp, #100] + rsb r6, r4, #8 + cmp r3, r6 + blt .L6969 + cmp r6, #0 + ldr r2, [r0, #0] + ldreq sl, [sp, #76] + beq .L6370 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + ldr r2, .L6978 + mov r5, #0 +.L6371: + movs r3, lr, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldrne r7, [sp, #76] + mov r4, r5, asl #1 + add r5, r5, #1 + strneh r3, [r4, r7] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L6371 + ldr ip, [sp, #76] + add sl, ip, r6, asl #1 +.L6370: + ldr lr, [sp, #100] + sub r0, r0, #32 + rsb r2, r6, lr + b .L6359 +.L6227: + ldr r7, [sp, #100] + rsb lr, r3, #8 + cmp r7, lr + blt .L6970 + cmp lr, #0 + ldr r2, [r6, #0] + ldreq r7, [sp, #76] + beq .L6240 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + ldr r4, .L6978 + mov ip, #0 +.L6241: + ands r3, r2, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + ldrne r7, [sp, #76] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp lr, ip + mov r2, r2, lsr #4 + bne .L6241 + ldr ip, [sp, #76] + add r7, ip, lr, asl #1 +.L6240: + ldr r0, [sp, #100] + add r6, r6, #32 + rsb r8, lr, r0 + b .L6229 +.L6707: + ldr r0, [sp, #100] + rsb lr, ip, #8 + cmp r0, lr + blt .L6971 + cmp ip, #3 + bls .L6740 + cmp lr, #0 + ldr r2, [r7, #0] + ldreq r5, [sp, #76] + beq .L6744 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr ip, .L6978 + mov r0, #0 +.L6745: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #76] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp lr, r0 + mov r2, r2, asl #8 + bne .L6745 + ldr r6, [sp, #76] + add r5, r6, lr, asl #1 +.L6744: + ldr ip, [sp, #100] + sub r7, r7, #64 + rsb r6, lr, ip + b .L6709 +.L6971: + cmp r0, #0 + ble .L6149 + cmp ip, #3 + bls .L6713 + mov r3, ip, asl #3 + ldr r2, [r7, #0] + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr ip, .L6978 + mov r0, #0 +.L6716: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #76] + ldr r5, [sp, #100] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp r5, r0 + mov r2, r2, asl #8 + bne .L6716 + b .L6149 +.L6970: + cmp r7, #0 + ble .L6149 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + ldr lr, .L6978 + mov ip, #0 +.L6234: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #76] + ldr r5, [sp, #100] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, ip + mov r0, r0, lsr #4 + bne .L6234 + b .L6149 +.L6969: + cmp r3, #0 + ble .L6149 + ldr r2, [r0, #0] + mov r3, r4, asl #2 + mov r0, r2, asl r3 + ldr lr, .L6978 + mov ip, #0 +.L6364: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #76] + ldr r5, [sp, #100] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, ip + mov r0, r0, asl #4 + bne .L6364 + b .L6149 +.L6965: + cmp lr, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #76] + beq .L6814 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + ldr r5, .L6978 + mov ip, #0 +.L6815: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldrne r6, [sp, #76] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp ip, lr + mov r1, r1, asl #8 + bne .L6815 + ldr r7, [sp, #76] + sub r2, r2, #64 + add r0, r7, lr, asl #1 + b .L6809 +.L6962: + cmp lr, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #76] + beq .L6594 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + ldr r5, .L6978 + mov ip, #0 +.L6595: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldrne r6, [sp, #76] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r6] @ movhi + cmp ip, lr + mov r2, r2, lsr #8 + bne .L6595 + ldr r7, [sp, #76] + add r0, r0, #64 + add r1, r7, lr, asl #1 + b .L6589 +.L6968: + cmp r0, #0 + ble .L6149 + cmp ip, #3 + bls .L6493 + mov r3, ip, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov r1, r2, lsr r3 + ldr ip, .L6978 + mov r0, #0 +.L6496: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #76] + ldr r5, [sp, #100] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, r0 + mov r1, r1, lsr #8 + bne .L6496 + b .L6149 +.L6975: + mov r6, #0 + b .L6207 +.L6740: + subs r4, lr, #4 + ldr r2, [r7, #4] + ldreq r1, [sp, #76] + beq .L6752 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr ip, .L6978 + mov r0, #0 +.L6753: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r5, [sp, #76] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r5] @ movhi + cmp r4, r0 + mov r2, r2, asl #8 + bne .L6753 + ldr r6, [sp, #76] + add r3, r6, lr, asl #1 + sub r1, r3, #8 +.L6752: + ldr r2, [r7, #0] + cmp r2, #0 + beq .L6758 + ands r3, r2, #255 + ldrne ip, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r5, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #0] @ movhi +.L6758: + add r5, r1, #8 + b .L6744 +.L6520: + subs r4, lr, #4 + ldr r2, [r7, #0] + ldreq r1, [sp, #76] + beq .L6532 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + ldr ip, .L6978 + mov r0, #0 +.L6533: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r5, [sp, #76] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r5] @ movhi + cmp r0, r4 + mov r1, r1, lsr #8 + bne .L6533 + ldr r6, [sp, #76] + add r3, r6, lr, asl #1 + sub r1, r3, #8 +.L6532: + ldr r2, [r7, #4] + cmp r2, #0 + beq .L6538 + ands r3, r2, #255 + ldrne ip, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r5, .L6978 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #6] @ movhi +.L6538: + add r5, r1, #8 + b .L6524 +.L6973: + ldr r4, [sp, #16] + b .L6938 +.L6972: + mov ip, fp + b .L6936 +.L6713: + ldr r6, [sp, #100] + mov r3, ip, asl #3 + ldr r1, [r7, #4] + add r2, r6, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L6720 + cmp r6, #0 + ldrne ip, .L6978 + movne r0, #0 + beq .L6149 +.L6736: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r7, [sp, #76] + ldr lr, [sp, #100] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r7] @ movhi + cmp lr, r0 + mov r1, r1, asl #8 + bne .L6736 + b .L6149 +.L6493: + ldr r6, [sp, #100] + ldr r3, [r7, #0] + add r2, r6, ip + cmp r2, #4 + mov r1, ip, asl #3 + mov r2, r3, lsr r1 + bhi .L6500 + cmp r6, #0 + ldrne ip, .L6978 + movne r0, #0 + beq .L6149 +.L6516: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r7, [sp, #76] + ldr lr, [sp, #100] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r7] @ movhi + cmp lr, r0 + mov r2, r2, lsr #8 + bne .L6516 + b .L6149 +.L6720: + rsbs ip, ip, #4 + ldreq lr, [sp, #76] + beq .L6725 + ldr lr, .L6978 + mov r0, #0 +.L6726: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #76] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r0, ip + mov r1, r1, asl #8 + bne .L6726 + ldr r5, [sp, #76] + add lr, r5, ip, asl #1 +.L6725: + ldr r6, [sp, #100] + ldr r2, [r7, #0] + subs ip, r6, ip + beq .L6149 + ldr r4, .L6978 + mov r0, #0 +.L6732: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L6732 + b .L6149 +.L6500: + rsbs ip, ip, #4 + ldreq lr, [sp, #76] + beq .L6505 + ldr lr, .L6978 + mov r0, #0 +.L6506: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #76] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L6506 + ldr r5, [sp, #76] + add lr, r5, ip, asl #1 +.L6505: + ldr r6, [sp, #100] + ldr r2, [r7, #4] + subs ip, r6, ip + beq .L6149 + ldr r4, .L6978 + mov r0, #0 +.L6512: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L6512 + b .L6149 +.L6979: + .align 2 +.L6978: + .word palette_ram_converted+512 + .size render_scanline_obj_normal_1D, .-render_scanline_obj_normal_1D + .align 2 + .global render_scanline_obj_normal_2D + .type render_scanline_obj_normal_2D, %function +render_scanline_obj_normal_2D: + @ args = 0, pretend = 0, frame = 92 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L7822 + sub sp, sp, #92 + ldrh ip, [ip, #6] + add r0, r0, r0, asl #2 + add r0, ip, r0, asl #5 + str ip, [sp, #32] + ldr ip, .L7822+4 + str r1, [sp, #12] + ldr ip, [ip, r0, asl #2] + str r2, [sp, #8] + str ip, [sp, #36] + cmp ip, #0 + ldr ip, .L7822+8 + str r3, [sp, #4] + add r0, ip, r0, asl #7 + str r0, [sp, #40] + beq .L7768 + add r0, r3, r1, asl #1 + rsb r1, r1, r2 + mov r2, #0 + str r0, [sp, #64] + str r1, [sp, #88] + str r2, [sp, #28] + mov r4, r2 +.L6983: + ldr r5, [sp, #40] + ldr r6, .L7822+12 + ldrb r3, [r4, r5] @ zero_extendqisi2 + ldr r7, .L7822+16 + mov r3, r3, asl #3 + ldrh lr, [r3, r6] + add r3, r3, r6 + ldrh r1, [r3, #2] + mov r4, lr, lsr #12 + and r2, r4, #12 + orr r0, r2, r1, lsr #14 + and ip, lr, #255 + mov r2, r1, asl #23 + cmp ip, #160 + mov r5, r2, asr #23 + ldr r2, .L7822+20 + subgt ip, ip, #256 + tst lr, #256 + ldrh r6, [r3, #4] + ldr r8, [r7, r0, asl #2] + ldr sl, [r2, r0, asl #2] + beq .L6986 + tst lr, #8192 + beq .L6988 + mov r3, r1, lsr #4 + ldr r4, .L7822+12 + add r2, r8, r8, lsr #31 + and r3, r3, #992 + tst lr, #512 + add r3, r3, r4 + mov lr, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + mov r4, r1, asr #1 + movne r0, lr, asl #1 + ldrh r7, [r3, #30] + strne r0, [sp, #48] + moveq r9, r8 + streq lr, [sp, #48] + moveq r0, r4 + movne r9, r8, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + str r7, [sp, #16] + ldrh r1, [r3, #14] + ldrh r7, [r3, #6] + ldrh fp, [r3, #22] + bge .L6993 + rsb r2, r5, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L6995 + ldr r3, [sp, #48] + ldr r5, [sp, #12] + rsb r3, r2, r3 + str r3, [sp, #48] +.L6993: + ldr r2, [sp, #8] + add r3, r5, r9 + cmp r3, r2 + blt .L6997 + rsb r9, r5, r2 + cmp r9, #0 + ble .L6995 +.L6997: + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r7, [sp, #16] + mov r3, r3, asr #16 + add r0, ip, r0 + str r3, [sp, #44] + mov ip, r2, asr #16 + ldr r3, [sp, #32] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov lr, lr, asl #8 + cmp fp, #0 + str lr, [sp, #72] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r7, r2, r5, asl #1 + rsb r0, r0, r3 + bne .L6999 + mla r3, r0, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L6995 + mov r3, r6, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L7822+24 + cmp r9, #0 + add r4, r3, r1, asl #3 + ble .L6995 + ldr r2, [sp, #48] + ldr r5, [sp, #44] + mul r3, r0, ip + mul r2, r5, r2 + ldr r6, [sp, #72] + rsb r3, r2, r3 + add r0, r6, r3 + mov lr, r0, asr #8 + cmp lr, r8 + movcs ip, fp + bcs .L7005 + b .L7818 +.L7006: + cmp lr, r8 + bcc .L7782 +.L7005: + ldr lr, [sp, #44] + add ip, ip, #1 + add r0, r0, lr + cmp r9, ip + mov lr, r0, asr #8 + add r7, r7, #2 + bne .L7006 +.L6995: + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + beq .L7768 +.L7800: + ldr r4, [sp, #28] + b .L6983 +.L6986: + ldr r2, [sp, #32] + tst r1, #8192 + rsb r0, ip, r2 + rsbne r3, r0, sl + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, r4, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L6995 + .p2align 2 +.L7067: + .word .L7063 + .word .L7064 + .word .L7065 + .word .L7066 +.L7063: + mov r3, r6, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + mov r2, r6, lsr #8 + cmp r5, r3 + ldr r3, .L7822+24 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L7795 + ldr r2, [sp, #8] + add r3, r5, r8 + cmp r2, r3 + bhi .L7149 + rsb r8, r5, r2 + cmp r8, #0 + ble .L6995 + ldr r3, [sp, #4] + movs r7, r8, lsr #3 + add r2, r3, r5, asl #1 + beq .L7152 + ldr r6, .L7822+36 + mov r4, r2 + mov r5, r0 + mov ip, #0 +.L7154: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L7155 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi +.L7155: + add ip, ip, #1 + cmp ip, r7 + add r5, r5, #32 + add r4, r4, #16 + bne .L7154 + add r0, r0, r7, asl #5 + add r2, r2, r7, asl #4 +.L7152: + ands r4, r8, #7 + beq .L6995 + ldr r0, [r0, #0] + ldr r5, .L7822+36 + mov lr, #0 +.L7174: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov ip, lr, asl #1 + add lr, lr, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r4 + mov r0, r0, lsr #4 + bne .L7174 + b .L6995 +.L7064: + mov r3, r6, asl #22 + mov r1, r0, lsr #3 + subs r2, r8, #8 + mov r3, r3, lsr #22 + submi r2, r8, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr ip, [sp, #12] + add r1, r1, r3, asl #3 + ldr r3, .L7822+24 + mov r2, r6, lsr #8 + cmp r5, ip + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L7796 + ldr r2, [sp, #8] + add r3, r5, r8 + cmp r2, r3 + bhi .L7279 + rsb r8, r5, r2 + cmp r8, #0 + ble .L6995 + ldr r3, [sp, #4] + movs r7, r8, lsr #3 + add r2, r3, r5, asl #1 + beq .L7282 + ldr r6, .L7822+36 + mov r4, r2 + mov r5, r0 + mov ip, #0 +.L7284: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L7285 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi +.L7285: + add ip, ip, #1 + cmp ip, r7 + sub r5, r5, #32 + add r4, r4, #16 + bne .L7284 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #4 +.L7282: + ands r4, r8, #7 + beq .L6995 + ldr r0, [r0, #0] + ldr r5, .L7822+36 + mov lr, #0 +.L7304: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + mov ip, lr, asl #1 + add lr, lr, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r4 + mov r0, r0, asl #4 + bne .L7304 + b .L6995 +.L7065: + mov r2, r6, asl #22 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + and r3, r0, #7 + add r2, r2, r1, asl #5 + add r3, r3, r2, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L7822+24 + cmp r5, ip + add ip, r0, r3 + blt .L7797 + ldr lr, [sp, #8] + add r3, r5, r8 + cmp lr, r3 + bhi .L7484 + rsb r8, r5, lr + cmp r8, #0 + ble .L6995 + ldr r1, [sp, #4] + movs r7, r8, lsr #3 + add r2, r1, r5, asl #1 + beq .L7487 + ldr r3, .L7822+32 + ldr r6, .L7822+36 + add r0, r0, r3 + mov r4, r2 + mov r5, ip + mov r1, #0 +.L7489: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L7490 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi +.L7490: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L7499 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi +.L7499: + add r1, r1, #1 + cmp r7, r1 + add r5, r5, #64 + add r4, r4, #16 + add r0, r0, #64 + bne .L7489 + add ip, ip, r7, asl #6 + add r2, r2, r7, asl #4 +.L7487: + ands lr, r8, #7 + beq .L6995 + cmp lr, #3 + ldrls r0, [ip, #0] + bls .L7522 + ldr r1, [ip, #0] + cmp r1, #0 + beq .L7512 + ands r3, r1, #255 + ldrne r4, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r2, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r2, #4] @ movhi + movs r3, r1, lsr #24 + ldrne r7, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r2, #6] @ movhi +.L7512: + subs lr, lr, #4 + ldr r0, [ip, #4] + addne r2, r2, #8 + beq .L6995 +.L7522: + mov r1, #0 +.L7523: + ands r3, r0, #255 + ldrne r4, .L7822+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov ip, r1, asl #1 + add r1, r1, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r1 + mov r0, r0, lsr #8 + bhi .L7523 + b .L6995 +.L7066: + subs r2, r8, #8 + submi r2, r8, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, r6, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L7822+24 + cmp r5, ip + add ip, r0, r3 + blt .L7798 + ldr lr, [sp, #8] + add r3, r5, r8 + cmp r3, lr + bcc .L7704 + rsb r8, r5, lr + cmp r8, #0 + ble .L6995 + ldr r1, [sp, #4] + movs r7, r8, lsr #3 + add sl, r1, r5, asl #1 + beq .L7707 + ldr r3, .L7822+28 + ldr r6, .L7822+36 + add r0, r0, r3 + mov r4, sl + mov r5, ip + mov r1, #0 +.L7709: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L7710 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #0] @ movhi +.L7710: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L7719 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #10] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r4, #8] @ movhi +.L7719: + add r1, r1, #1 + cmp r1, r7 + sub r5, r5, #64 + add r4, r4, #16 + sub r0, r0, #64 + bne .L7709 + rsb r3, r7, r7, asl #26 + add ip, ip, r3, asl #6 + add sl, sl, r7, asl #4 +.L7707: + ands lr, r8, #7 + beq .L6995 + cmp lr, #3 + ldrls r2, [ip, #4] + bls .L7742 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L7732 + ands r3, r2, #255 + ldrne r4, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [sl, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [sl, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [sl, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r7, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [sl, #0] @ movhi +.L7732: + subs lr, lr, #4 + ldr r2, [ip, #0] + addne sl, sl, #8 + beq .L6995 +.L7742: + mov r1, #0 +.L7743: + movs r3, r2, lsr #24 + ldrne ip, .L7822+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + mov r0, r1, asl #1 + add r1, r1, #1 + strneh r3, [r0, sl] @ movhi + cmp lr, r1 + mov r2, r2, asl #8 + bhi .L7743 + b .L6995 +.L6988: + mov r3, r1, lsr #4 + ldr r4, .L7822+12 + and r3, r3, #992 + add r3, r3, r4 + ldrh r7, [r3, #30] + add r2, r8, r8, lsr #31 + tst lr, #512 + add r1, sl, sl, lsr #31 + mov lr, r2, asr #1 + ldr r2, [sp, #12] + mov r4, r1, asr #1 + str r7, [sp, #24] + ldrh r1, [r3, #14] + ldrh r7, [r3, #6] + ldrh r3, [r3, #22] + moveq fp, r8 + moveq r9, lr + moveq r0, r4 + movne fp, r8, asl #1 + movne r9, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + str r3, [sp, #20] + bge .L7026 + rsb r2, r5, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L6995 + ldr r5, [sp, #12] + rsb r9, r2, r9 +.L7026: + ldr r2, [sp, #8] + add r3, r5, fp + cmp r3, r2 + blt .L7029 + rsb fp, r5, r2 + cmp fp, #0 + ble .L6995 +.L7029: + add ip, ip, r0 + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r0, [sp, #20] + ldr r7, [sp, #24] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + cmp r0, #0 + str r3, [sp, #52] + mov r0, r6, lsr #8 + str r2, [sp, #56] + ldr r3, [sp, #32] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov lr, lr, asl #8 + and r0, r0, #240 + str lr, [sp, #68] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r7, r2, r5, asl #1 + rsb ip, ip, r3 + str r0, [sp, #84] + bne .L7031 + mla r3, ip, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L6995 + mov r3, r6, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #3 + ldr r3, .L7822+24 + cmp fp, #0 + add r1, r3, r1, asl #2 + ble .L6995 + ldr r3, [sp, #56] + ldr r2, [sp, #52] + mul r3, ip, r3 + mul r2, r9, r2 + ldr r4, [sp, #68] + rsb r3, r2, r3 + add r0, r4, r3 + mov lr, r0, asr #8 + cmp lr, r8 + ldrcs r4, [sp, #20] + bcs .L7037 + b .L7819 +.L7038: + cmp lr, r8 + bcc .L7784 +.L7037: + ldr r5, [sp, #52] + add r4, r4, #1 + add r0, r0, r5 + cmp fp, r4 + mov lr, r0, asr #8 + add r7, r7, #2 + bne .L7038 + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + bne .L7800 +.L7768: + add sp, sp, #92 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L6999: + mov r3, r6, asl #22 + ldr r2, .L7822+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r9, #0 + str r3, [sp, #80] + ble .L6995 + mov r3, fp, asl #16 + mul r2, r0, r1 + mov fp, r3, asr #16 + ldr r4, [sp, #44] + mul r3, r0, ip + ldr r1, [sp, #48] + ldr r0, [sp, #48] + mul r1, fp, r1 + mul r0, r4, r0 + ldr r6, [sp, #72] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add r4, lr, r2 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + cmp ip, r8 + cmpcc lr, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L7015 + b .L7820 +.L7016: + cmp ip, r8 + cmpcc lr, sl + bcc .L7017 +.L7015: + ldr ip, [sp, #44] + add r6, r6, #1 + add r5, r5, ip + add r4, r4, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + add r7, r7, #2 + bne .L7016 + b .L6995 +.L7031: + mov r3, r6, asl #22 + ldr r2, .L7822+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp fp, #0 + str r3, [sp, #76] + ble .L6995 + ldr r4, [sp, #20] + mul r2, ip, r1 + mov r3, r4, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #60] + ldr r1, [sp, #60] + ldr r3, [sp, #56] + ldr r0, [sp, #52] + mul r3, ip, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr r6, [sp, #68] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add r4, lr, r2 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + cmp ip, r8 + cmpcc lr, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L7050 + b .L7821 +.L7051: + cmp ip, r8 + cmpcc lr, sl + bcc .L7053 +.L7050: + ldr ip, [sp, #52] + ldr lr, [sp, #60] + add r6, r6, #1 + add r5, r5, ip + add r4, r4, lr + cmp fp, r6 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + add r7, r7, #2 + bne .L7051 + b .L6995 +.L7803: + mov r3, ip, asr #1 + ldr r1, [sp, #76] + and r3, r3, #3 + str r3, [sp, #0] + and r0, lr, #7 + ldr r3, [sp, #76] + add r0, r1, r0, asl #2 + and r1, lr, #7 + mov r2, ip, asr #1 + add r1, r3, r1, asl #2 + mov r3, lr, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + tst ip, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne ip, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, ip] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + ldr r2, [sp, #84] + cmp r0, #0 + orr r3, r0, r2 + ldrne r0, .L7822+36 + mov r3, r3, asl #1 + ldr lr, [sp, #52] + ldrneh r3, [r3, r0] + ldr r1, [sp, #60] + add r6, r6, #1 + add r5, r5, lr + strneh r3, [r7, #0] @ movhi + add r4, r4, r1 + cmp fp, r6 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + add r7, r7, #2 + ble .L6995 +.L7053: + cmp lr, sl + cmpcc ip, r8 + bcc .L7803 + b .L6995 +.L7040: + cmp lr, r8 + bcs .L6995 +.L7784: + mov r3, lr, asr #1 + and r6, r3, #3 + mov r3, lr, asr #3 + mov r3, r3, asl #5 + mov r2, lr, asr #1 + tst lr, #1 + add ip, r3, r1 + and r5, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r5] @ zero_extendqisi2 + ldrneb r3, [ip, r6] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + ldr ip, [sp, #84] + cmp r2, #0 + orr r3, r2, ip + ldrne r2, .L7822+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldr r6, [sp, #52] + add r4, r4, #1 + strneh r3, [r7, #0] @ movhi + add r0, r0, r6 + cmp fp, r4 + mov lr, r0, asr #8 + add r7, r7, #2 + bgt .L7040 + b .L6995 +.L7008: + cmp lr, r8 + bcs .L6995 +.L7782: + ldr r1, [sp, #44] + mov r3, lr, asr #3 + add r3, r4, r3, asl #6 + add r0, r0, r1 + and r1, lr, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + add ip, ip, #1 + cmp r2, #0 + ldrne r3, .L7822+36 + mov r2, r2, asl #1 + ldrneh r2, [r2, r3] + mov lr, r0, asr #8 + strneh r2, [r7, #0] @ movhi + cmp r9, ip + add r7, r7, #2 + bgt .L7008 + b .L6995 +.L7823: + .align 2 +.L7822: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_width_table + .word obj_height_table + .word vram+65536 + .word vram+65472 + .word vram+65600 + .word palette_ram_converted+512 +.L7798: + ldr lr, [sp, #12] + rsb r1, r5, lr + rsb r4, r1, r8 + cmp r4, #0 + ble .L6995 + ldr r0, [sp, #8] + add r3, r5, r8 + cmp r0, r3 + bhi .L7551 + mov r3, r1, lsr #3 + ands r0, r1, #7 + sub r7, ip, r3, asl #6 + bne .L7553 + ldr r6, [sp, #88] + ldr r5, [sp, #64] +.L7555: + movs r4, r6, lsr #3 + beq .L7613 + ldr lr, .L7822+36 + mov r1, r5 + mov r0, r7 + mov ip, #0 +.L7615: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L7616 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi +.L7616: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L7625 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #10] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #8] @ movhi +.L7625: + add ip, ip, #1 + cmp ip, r4 + sub r0, r0, #64 + add r1, r1, #16 + bne .L7615 + rsb r3, r4, r4, asl #26 + add r7, r7, r3, asl #6 + add r5, r5, r4, asl #4 +.L7613: + ands ip, r6, #7 + beq .L6995 + cmp ip, #3 + ldrls r2, [r7, #4] + bls .L7648 + ldr r2, [r7, #4] + cmp r2, #0 + beq .L7638 + ands r3, r2, #255 + ldrne r0, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r5, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r1, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r1] + strneh r3, [r5, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r5, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r5, #0] @ movhi +.L7638: + subs ip, ip, #4 + ldr r2, [r7, #0] + addne r5, r5, #8 + beq .L6995 +.L7648: + mov r1, #0 +.L7649: + movs r3, r2, lsr #24 + ldrne r7, .L7822+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r0, r1, asl #1 + add r1, r1, #1 + strneh r3, [r0, r5] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L7649 + b .L6995 +.L7797: + ldr lr, [sp, #12] + rsb r1, r5, lr + rsb r4, r1, r8 + cmp r4, #0 + ble .L6995 + ldr r0, [sp, #8] + add r3, r5, r8 + cmp r0, r3 + bhi .L7331 + mov r3, r1, lsr #3 + ands r0, r1, #7 + add r7, ip, r3, asl #6 + bne .L7333 + ldr r6, [sp, #88] + ldr r5, [sp, #64] +.L7335: + movs r4, r6, lsr #3 + beq .L7393 + ldr lr, .L7822+36 + mov r1, r5 + mov r0, r7 + mov ip, #0 +.L7395: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L7396 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #6] @ movhi +.L7396: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L7405 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #14] @ movhi +.L7405: + add ip, ip, #1 + cmp r4, ip + add r0, r0, #64 + add r1, r1, #16 + bne .L7395 + add r7, r7, r4, asl #6 + add r5, r5, r4, asl #4 +.L7393: + ands ip, r6, #7 + beq .L6995 + cmp ip, #3 + ldrls r1, [r7, #0] + bls .L7428 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L7418 + ands r3, r2, #255 + ldrne r0, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r5, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r1, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r1] + strneh r3, [r5, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r5, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r5, #6] @ movhi +.L7418: + subs ip, ip, #4 + ldr r1, [r7, #4] + addne r5, r5, #8 + beq .L6995 +.L7428: + mov r2, #0 +.L7429: + ands r3, r1, #255 + ldrne r7, .L7822+36 + mov r3, r3, asl #1 + ldrneh r3, [r3, r7] + mov r0, r2, asl #1 + add r2, r2, #1 + strneh r3, [r0, r5] @ movhi + cmp ip, r2 + mov r1, r1, lsr #8 + bhi .L7429 + b .L6995 +.L7796: + rsb lr, r5, ip + rsb ip, lr, r8 + cmp ip, #0 + ble .L6995 + ldr r2, [sp, #8] + add r3, r5, r8 + cmp r2, r3 + bhi .L7201 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub r0, r0, r3, asl #5 + bne .L7203 + ldr r2, [sp, #88] + ldr sl, [sp, #64] +.L7205: + movs r8, r2, lsr #3 + beq .L7222 + ldr r7, .L7822+36 + mov r4, sl + mov r5, r0 + mov r6, #0 +.L7224: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L7225 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r4, #0] @ movhi +.L7225: + add r6, r6, #1 + cmp r6, r8 + sub r5, r5, #32 + add r4, r4, #16 + bne .L7224 + rsb r3, r8, r8, asl #27 + add r0, r0, r3, asl #5 + add sl, sl, r8, asl #4 +.L7222: + ands lr, r2, #7 + beq .L6995 + ldr r0, [r0, #0] + ldr r4, .L7822+36 + mov ip, #0 +.L7244: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, sl] @ movhi + cmp ip, lr + mov r0, r0, asl #4 + bne .L7244 + b .L6995 +.L7795: + ldr r4, [sp, #12] + rsb lr, r5, r4 + rsb r4, lr, r8 + cmp r4, #0 + ble .L6995 + add r3, r5, r8 + ldr r5, [sp, #8] + cmp r5, r3 + bhi .L7071 + mov r3, lr, lsr #3 + mov r2, r3, asl #5 + ands r3, lr, #7 + add r6, r0, r2 + bne .L7073 + ldr r8, [sp, #88] + ldr r7, [sp, #64] +.L7075: + movs r5, r8, lsr #3 + beq .L7092 + ldr r4, .L7822+36 + mov ip, r7 + mov r0, r6 + mov lr, #0 +.L7094: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L7095 + ands r3, r2, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [ip, #14] @ movhi +.L7095: + add lr, lr, #1 + cmp r5, lr + add r0, r0, #32 + add ip, ip, #16 + bne .L7094 + add r6, r6, r5, asl #5 + add r7, r7, r5, asl #4 +.L7092: + ands lr, r8, #7 + beq .L6995 + ldr r2, [r6, #0] + ldr r4, .L7822+36 + mov r0, #0 +.L7114: + ands r3, r2, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov ip, r0, asl #1 + add r0, r0, #1 + strneh r3, [ip, r7] @ movhi + cmp r0, lr + mov r2, r2, lsr #4 + bne .L7114 + b .L6995 +.L7820: + mov r6, #0 +.L7017: + cmp lr, sl + movcc r3, #0 + movcs r3, #1 + cmp r8, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L7783 + b .L6995 +.L7018: + cmp lr, sl + cmpcc ip, r8 + bcs .L6995 +.L7783: + and r3, lr, #7 + mov r2, ip, asr #3 + mov r3, r3, asl #3 + mov r1, lr, asr #3 + add r3, r3, r2, asl #6 + ldr r0, [sp, #44] + add r3, r3, r1, asl #10 + ldr r1, [sp, #80] + add r5, r5, r0 + add r3, r3, r1 + and r0, ip, #7 + ldrb r2, [r3, r0] @ zero_extendqisi2 + add r6, r6, #1 + cmp r2, #0 + ldrne r3, .L7822+36 + mov r2, r2, asl #1 + ldrneh r2, [r2, r3] + add r4, r4, fp + strneh r2, [r7, #0] @ movhi + cmp r9, r6 + mov lr, r4, asr #8 + mov ip, r5, asr #8 + add r7, r7, #2 + bgt .L7018 + b .L6995 +.L7279: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L6995 + ldr r7, [sp, #4] + ldr r4, .L7822+36 + add r2, r7, r5, asl #1 + mov ip, #0 + b .L7309 +.L7804: + sub r0, r0, #32 + add r2, r2, #16 +.L7309: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L7310 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi +.L7310: + add ip, ip, #1 + cmp r6, ip + bne .L7804 + b .L6995 +.L7704: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L6995 + ldr r3, .L7822+28 + ldr lr, [sp, #4] + ldr r4, .L7822+36 + add r0, r0, r3 + add r2, lr, r5, asl #1 + mov r1, #0 + b .L7748 +.L7805: + sub ip, ip, #64 + add r2, r2, #16 +.L7748: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L7749 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi +.L7749: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L7758 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi +.L7758: + add r1, r1, #1 + cmp r6, r1 + sub r0, r0, #64 + bne .L7805 + b .L6995 +.L7149: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L6995 + ldr r7, [sp, #4] + ldr r4, .L7822+36 + add r2, r7, r5, asl #1 + mov ip, #0 + b .L7179 +.L7806: + add r0, r0, #32 + add r2, r2, #16 +.L7179: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L7180 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi +.L7180: + add ip, ip, #1 + cmp r6, ip + bne .L7806 + b .L6995 +.L7484: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L6995 + ldr r3, .L7822+32 + ldr r7, [sp, #4] + ldr r4, .L7822+36 + add r0, r0, r3 + add r2, r7, r5, asl #1 + mov r1, #0 + b .L7528 +.L7807: + add ip, ip, #64 + add r2, r2, #16 +.L7528: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L7529 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #0] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #2] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #4] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #6] @ movhi +.L7529: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L7538 + ands r3, lr, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #8] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #10] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #12] @ movhi + movs r3, lr, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r2, #14] @ movhi +.L7538: + add r1, r1, #1 + cmp r6, r1 + add r0, r0, #64 + bne .L7807 + b .L6995 +.L7331: + mov r3, r1, lsr #3 + ands r2, r1, #7 + add r0, ip, r3, asl #6 + ldreq r1, [sp, #64] + beq .L7435 + cmp r2, #3 + rsb lr, r2, #8 + bhi .L7808 + subs r5, lr, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #64] + beq .L7448 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + ldr r6, .L7822+36 + mov ip, #0 +.L7449: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #64] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r7] @ movhi + cmp ip, r5 + mov r2, r2, lsr #8 + bne .L7449 + ldr ip, [sp, #64] + add r3, ip, lr, asl #1 + sub r1, r3, #8 +.L7448: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L7454 + ands r3, r2, #255 + ldrne lr, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r7, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r1, #6] @ movhi +.L7454: + add r1, r1, #8 +.L7440: + add r0, r0, #64 +.L7435: + movs r4, r4, lsr #3 + beq .L6995 + ldr ip, .L7822+36 + mov lr, #0 + b .L7464 +.L7809: + add r0, r0, #64 + add r1, r1, #16 +.L7464: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L7465 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #6] @ movhi +.L7465: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L7474 + ands r3, r2, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r1, #14] @ movhi +.L7474: + add lr, lr, #1 + cmp r4, lr + bne .L7809 + b .L6995 +.L7201: + ands r2, lr, #7 + mov r3, lr, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r4, [sp, #64] + beq .L7250 + rsbs r6, r2, #8 + ldr lr, [r0, #0] + ldreq r4, [sp, #64] + beq .L7253 + mov r3, r2, asl #2 + mov lr, lr, asl r3 + ldr r2, .L7822+36 + mov r5, #0 +.L7254: + movs r3, lr, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldrne r7, [sp, #64] + mov r4, r5, asl #1 + add r5, r5, #1 + strneh r3, [r4, r7] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L7254 + ldr lr, [sp, #64] + add r4, lr, r6, asl #1 +.L7253: + sub r0, r0, #32 +.L7250: + movs r5, ip, lsr #3 + beq .L6995 + ldr r2, .L7822+36 + mov ip, #0 + b .L7260 +.L7810: + sub r0, r0, #32 + add r4, r4, #16 +.L7260: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L7261 + ands r3, lr, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #14] @ movhi + mov r3, lr, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #12] @ movhi + mov r3, lr, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #10] @ movhi + mov r3, lr, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #8] @ movhi + mov r3, lr, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #6] @ movhi + mov r3, lr, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #4] @ movhi + mov r3, lr, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #2] @ movhi + movs r3, lr, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r2] + strneh r3, [r4, #0] @ movhi +.L7261: + add ip, ip, #1 + cmp ip, r5 + bne .L7810 + b .L6995 +.L7551: + ands r0, r1, #7 + mov r3, r1, lsr #3 + sub r2, ip, r3, asl #6 + ldreq r0, [sp, #64] + beq .L7655 + cmp r0, #3 + rsb lr, r0, #8 + bhi .L7811 + subs r5, lr, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #64] + beq .L7668 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + ldr r6, .L7822+36 + mov ip, #0 +.L7669: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #64] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp r5, ip + mov r1, r1, asl #8 + bne .L7669 + ldr ip, [sp, #64] + add r3, ip, lr, asl #1 + sub r0, r3, #8 +.L7668: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L7674 + ands r3, r1, #255 + ldrne lr, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r6] + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r7, .L7822+36 + movne r3, r3, asl #1 + ldrneh r3, [r3, r7] + strneh r3, [r0, #0] @ movhi +.L7674: + add r0, r0, #8 +.L7660: + sub r2, r2, #64 +.L7655: + movs r4, r4, lsr #3 + beq .L6995 + ldr ip, .L7822+36 + mov lr, #0 + b .L7684 +.L7812: + sub r2, r2, #64 + add r0, r0, #16 +.L7684: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L7685 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #0] @ movhi +.L7685: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L7694 + ands r3, r1, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #10] @ movhi + movs r3, r1, lsr #24 + movne r3, r3, asl #1 + ldrneh r3, [r3, ip] + strneh r3, [r0, #8] @ movhi +.L7694: + add lr, lr, #1 + cmp lr, r4 + bne .L7812 + b .L6995 +.L7071: + mov r3, lr, lsr #3 + mov r2, r3, asl #5 + ands r3, lr, #7 + ldreq ip, [sp, #64] + add lr, r0, r2 + beq .L7120 + rsbs r5, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #64] + beq .L7123 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + ldr r6, .L7824 + mov ip, #0 +.L7124: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r6] + ldrne r7, [sp, #64] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r7] @ movhi + cmp ip, r5 + mov r0, r0, lsr #4 + bne .L7124 + ldr r0, [sp, #64] + add ip, r0, r5, asl #1 +.L7123: + add lr, lr, #32 +.L7120: + movs r5, r4, lsr #3 + beq .L6995 + ldr r0, .L7824 + mov r4, #0 + b .L7130 +.L7813: + add lr, lr, #32 + add ip, ip, #16 +.L7130: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L7131 + ands r3, r2, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + orrne r3, r1, r3 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [ip, #14] @ movhi +.L7131: + add r4, r4, #1 + cmp r4, r5 + bne .L7813 + b .L6995 +.L7333: + ldr r1, [sp, #88] + rsb ip, r0, #8 + cmp r1, ip + blt .L7814 + cmp r0, #3 + bls .L7366 + cmp ip, #0 + ldr r2, [r7, #4] + ldreq r5, [sp, #64] + beq .L7370 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + ldr lr, .L7824 + mov r0, #0 +.L7371: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp ip, r0 + mov r1, r1, lsr #8 + bne .L7371 + ldr r6, [sp, #64] + add r5, r6, ip, asl #1 +.L7370: + ldr lr, [sp, #88] + add r7, r7, #64 + rsb r6, ip, lr + b .L7335 +.L7203: + ldr r3, [sp, #88] + rsb r6, r4, #8 + cmp r3, r6 + blt .L7815 + cmp r6, #0 + ldr r2, [r0, #0] + ldreq sl, [sp, #64] + beq .L7216 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + ldr r2, .L7824 + mov r5, #0 +.L7217: + movs r3, lr, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r2] + ldrne r7, [sp, #64] + mov r4, r5, asl #1 + add r5, r5, #1 + strneh r3, [r4, r7] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L7217 + ldr ip, [sp, #64] + add sl, ip, r6, asl #1 +.L7216: + ldr lr, [sp, #88] + sub r0, r0, #32 + rsb r2, r6, lr + b .L7205 +.L7073: + ldr r7, [sp, #88] + rsb lr, r3, #8 + cmp r7, lr + blt .L7816 + cmp lr, #0 + ldr r2, [r6, #0] + ldreq r7, [sp, #64] + beq .L7086 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + ldr r4, .L7824 + mov ip, #0 +.L7087: + ands r3, r2, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + ldrne r7, [sp, #64] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp lr, ip + mov r2, r2, lsr #4 + bne .L7087 + ldr ip, [sp, #64] + add r7, ip, lr, asl #1 +.L7086: + ldr r0, [sp, #88] + add r6, r6, #32 + rsb r8, lr, r0 + b .L7075 +.L7553: + ldr r1, [sp, #88] + rsb ip, r0, #8 + cmp r1, ip + blt .L7817 + cmp r0, #3 + bls .L7586 + cmp ip, #0 + ldr r2, [r7, #0] + ldreq r5, [sp, #64] + beq .L7590 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr lr, .L7824 + mov r0, #0 +.L7591: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp ip, r0 + mov r2, r2, asl #8 + bne .L7591 + ldr r6, [sp, #64] + add r5, r6, ip, asl #1 +.L7590: + ldr lr, [sp, #88] + sub r7, r7, #64 + rsb r6, ip, lr + b .L7555 +.L7817: + cmp r1, #0 + ble .L6995 + cmp r0, #3 + bls .L7559 + mov r3, r0, asl #3 + ldr r2, [r7, #0] + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr ip, .L7824 + mov r0, #0 +.L7562: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #64] + ldr r5, [sp, #88] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp r5, r0 + mov r2, r2, asl #8 + bne .L7562 + b .L6995 +.L7816: + cmp r7, #0 + ble .L6995 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + ldr lr, .L7824 + mov ip, #0 +.L7080: + ands r3, r0, #15 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + ldr r5, [sp, #88] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, ip + mov r0, r0, lsr #4 + bne .L7080 + b .L6995 +.L7815: + cmp r3, #0 + ble .L6995 + ldr r2, [r0, #0] + mov r3, r4, asl #2 + mov r0, r2, asl r3 + ldr lr, .L7824 + mov ip, #0 +.L7210: + movs r3, r0, lsr #28 + orr r3, r1, r3 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + ldr r5, [sp, #88] + mov r2, ip, asl #1 + add ip, ip, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, ip + mov r0, r0, asl #4 + bne .L7210 + b .L6995 +.L7811: + cmp lr, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #64] + beq .L7660 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + ldr r5, .L7824 + mov ip, #0 +.L7661: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldrne r6, [sp, #64] + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp ip, lr + mov r1, r1, asl #8 + bne .L7661 + ldr r7, [sp, #64] + sub r2, r2, #64 + add r0, r7, lr, asl #1 + b .L7655 +.L7808: + cmp lr, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #64] + beq .L7440 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + ldr r5, .L7824 + mov ip, #0 +.L7441: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r5] + ldrne r6, [sp, #64] + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r6] @ movhi + cmp ip, lr + mov r2, r2, lsr #8 + bne .L7441 + ldr r7, [sp, #64] + add r0, r0, #64 + add r1, r7, lr, asl #1 + b .L7435 +.L7814: + cmp r1, #0 + ble .L6995 + cmp r0, #3 + bls .L7339 + mov r3, r0, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov r1, r2, lsr r3 + ldr ip, .L7824 + mov r0, #0 +.L7342: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r4, [sp, #64] + ldr r5, [sp, #88] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, r0 + mov r1, r1, lsr #8 + bne .L7342 + b .L6995 +.L7821: + mov r6, #0 + b .L7053 +.L7586: + subs lr, ip, #4 + ldr r2, [r7, #4] + ldreq r1, [sp, #64] + beq .L7598 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + ldr r4, .L7824 + mov r0, #0 +.L7599: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + ldrne r5, [sp, #64] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r5] @ movhi + cmp lr, r0 + mov r2, r2, asl #8 + bne .L7599 + ldr r6, [sp, #64] + add r3, r6, ip, asl #1 + sub r1, r3, #8 +.L7598: + ldr r2, [r7, #0] + cmp r2, #0 + beq .L7604 + ands r3, r2, #255 + ldrne lr, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r5, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #0] @ movhi +.L7604: + add r5, r1, #8 + b .L7590 +.L7366: + subs lr, ip, #4 + ldr r2, [r7, #0] + ldreq r1, [sp, #64] + beq .L7378 + mov r3, r0, asl #3 + mov r1, r2, lsr r3 + ldr r4, .L7824 + mov r0, #0 +.L7379: + ands r3, r1, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + ldrne r5, [sp, #64] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r5] @ movhi + cmp r0, lr + mov r1, r1, lsr #8 + bne .L7379 + ldr r6, [sp, #64] + add r3, r6, ip, asl #1 + sub r1, r3, #8 +.L7378: + ldr r2, [r7, #4] + cmp r2, #0 + beq .L7384 + ands r3, r2, #255 + ldrne lr, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, lr] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r0] + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r4] + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r5, .L7824 + movne r3, r3, asl #1 + ldrneh r3, [r3, r5] + strneh r3, [r1, #6] @ movhi +.L7384: + add r5, r1, #8 + b .L7370 +.L7819: + ldr r4, [sp, #20] + b .L7784 +.L7818: + mov ip, fp + b .L7782 +.L7559: + ldr r6, [sp, #88] + mov r3, r0, asl #3 + ldr r1, [r7, #4] + add r2, r6, r0 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L7566 + cmp r6, #0 + ldrne ip, .L7824 + movne r0, #0 + beq .L6995 +.L7582: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r7, [sp, #64] + ldr lr, [sp, #88] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r7] @ movhi + cmp lr, r0 + mov r1, r1, asl #8 + bne .L7582 + b .L6995 +.L7339: + ldr r6, [sp, #88] + ldr r3, [r7, #0] + add r2, r6, r0 + cmp r2, #4 + mov r1, r0, asl #3 + mov r2, r3, lsr r1 + bhi .L7346 + cmp r6, #0 + ldrne ip, .L7824 + movne r0, #0 + beq .L6995 +.L7362: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, ip] + ldrne r7, [sp, #64] + ldr lr, [sp, #88] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r7] @ movhi + cmp lr, r0 + mov r2, r2, lsr #8 + bne .L7362 + b .L6995 +.L7566: + rsbs ip, r0, #4 + ldreq lr, [sp, #64] + beq .L7571 + ldr lr, .L7824 + mov r0, #0 +.L7572: + movs r3, r1, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r0, ip + mov r1, r1, asl #8 + bne .L7572 + ldr r5, [sp, #64] + add lr, r5, ip, asl #1 +.L7571: + ldr r6, [sp, #88] + ldr r2, [r7, #0] + subs ip, r6, ip + beq .L6995 + ldr r4, .L7824 + mov r0, #0 +.L7578: + movs r3, r2, lsr #24 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L7578 + b .L6995 +.L7346: + rsbs ip, r0, #4 + ldreq lr, [sp, #64] + beq .L7351 + ldr lr, .L7824 + mov r0, #0 +.L7352: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, lr] + ldrne r4, [sp, #64] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L7352 + ldr r5, [sp, #64] + add lr, r5, ip, asl #1 +.L7351: + ldr r6, [sp, #88] + ldr r2, [r7, #4] + subs ip, r6, ip + beq .L6995 + ldr r4, .L7824 + mov r0, #0 +.L7358: + ands r3, r2, #255 + mov r3, r3, asl #1 + ldrneh r3, [r3, r4] + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L7358 + b .L6995 +.L7825: + .align 2 +.L7824: + .word palette_ram_converted+512 + .size render_scanline_obj_normal_2D, .-render_scanline_obj_normal_2D + .align 2 + .global render_scanline_obj_color16_1D + .type render_scanline_obj_color16_1D, %function +render_scanline_obj_color16_1D: + @ args = 0, pretend = 0, frame = 112 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L8668 + sub sp, sp, #112 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #32] + ldr r5, [sp, #32] + ldrh r4, [ip, #80] + ldr ip, .L8668+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #36] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L8668+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #40] + str r1, [sp, #8] + str r2, [sp, #4] + str r3, [sp, #0] + str lr, [sp, #24] + beq .L8614 + mov r8, #0 + add r6, r3, r1, asl #1 + rsb r7, r1, r2 + str r6, [sp, #84] + str r7, [sp, #108] + str r8, [sp, #28] + mov ip, r8 +.L7829: + ldr lr, [sp, #40] + ldr r0, .L8668+12 + ldrb r3, [ip, lr] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh r4, [r3, r0] + add r3, r3, r0 + ldrh r1, [r3, #2] + mov r5, r4, lsr #12 + and r2, r5, #12 + orr r0, r2, r1, lsr #14 + and ip, r4, #255 + mov r2, r1, asl #23 + cmp ip, #160 + ldrh lr, [r3, #4] + mov r6, r2, asr #23 + ldr r3, .L8668+16 + ldr r2, .L8668+20 + subgt ip, ip, #256 + tst r4, #256 + ldr r7, [r2, r0, asl #2] + ldr sl, [r3, r0, asl #2] + beq .L7832 + tst r4, #8192 + beq .L7834 + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L8668+12 + and r3, r3, #992 + add r3, r3, r4 + add r2, r7, r7, lsr #31 + ldrh r5, [r3, #30] + mov r4, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #8] + movne r0, r4, asl #1 + str r5, [sp, #12] + mov r5, r1, asr #1 + strne r0, [sp, #56] + moveq r9, r7 + streq r4, [sp, #56] + moveq r0, r5 + movne r9, r7, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L7839 + rsb r2, r6, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L7841 + ldr r3, [sp, #56] + ldr r6, [sp, #8] + rsb r3, r2, r3 + str r3, [sp, #56] +.L7839: + ldr r2, [sp, #4] + add r3, r6, r9 + cmp r3, r2 + blt .L7843 + rsb r9, r6, r2 + cmp r9, #0 + ble .L7841 +.L7843: + mov r3, r8, asl #16 + ldr r8, [sp, #12] + mov r2, r1, asl #16 + mov r2, r2, asr #16 + mov r1, r8, asl #16 + add r0, ip, r0 + str r2, [sp, #48] + mov ip, r1, asr #16 + ldr r2, [sp, #32] + ldr r1, [sp, #0] + mov r4, r4, asl #8 + mov r3, r3, asr #16 + mov r5, r5, asl #8 + cmp fp, #0 + str r4, [sp, #92] + str r3, [sp, #44] + str r5, [sp, #52] + add r8, r1, r6, asl #1 + rsb r4, r0, r2 + bne .L7845 + mov r3, r5 + mla r3, r4, ip, r3 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L7841 + cmp r7, #0 + add r3, r7, #7 + movge r3, r7 + mov r2, lr, asl #22 + mov r3, r3, asr #3 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L8668+24 + add r0, r0, ip, asl #2 + cmp r9, #0 + add lr, r3, r0, asl #3 + ble .L7841 + ldr r3, [sp, #48] + ldr r2, [sp, #56] + mul r3, r4, r3 + ldr r4, [sp, #44] + ldr r5, [sp, #92] + mul r2, r4, r2 + rsb r3, r2, r3 + add r0, r5, r3 + mov r4, r0, asr #8 + cmp r4, r7 + movcs ip, fp + bcs .L7851 + b .L8664 +.L7852: + cmp r4, r7 + bcc .L8628 +.L7851: + ldr r6, [sp, #44] + add ip, ip, #1 + add r0, r0, r6 + cmp r9, ip + mov r4, r0, asr #8 + add r8, r8, #2 + bne .L7852 +.L7841: + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + beq .L8614 +.L8646: + ldr ip, [sp, #28] + b .L7829 +.L7832: + ldr r0, [sp, #32] + tst r1, #8192 + rsb ip, ip, r0 + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r1, asl #19 + and r3, r5, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L7841 + .p2align 2 +.L7913: + .word .L7909 + .word .L7910 + .word .L7911 + .word .L7912 +.L7909: + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r5, r3, r2 + ldr r2, [sp, #8] + and r1, ip, #7 + ldr r3, .L8668+24 + add r1, r1, r0, asl #3 + cmp r6, r2 + mov r2, lr, lsr #8 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L8641 + ldr ip, [sp, #4] + add r3, r6, r7 + cmp ip, r3 + bhi .L7995 + rsb r8, r6, ip + cmp r8, #0 + ble .L7841 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r2, lr, r6, asl #1 + beq .L7998 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L8000: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8001 + ands r3, r4, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #0] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #14] @ movhi +.L8001: + add ip, ip, #1 + cmp ip, r7 + add lr, lr, #32 + add r5, r5, #16 + bne .L8000 + add r0, r0, r7, asl #5 + add r2, r2, r7, asl #4 +.L7998: + ands lr, r8, #7 + beq .L7841 + ldr r0, [r0, #0] + mov r4, #0 +.L8020: + ands r3, r0, #15 + ldr r5, [sp, #24] + orr r3, r1, r3 + mov ip, r4, asl #1 + orr r3, r3, r5 + add r4, r4, #1 + strneh r3, [ip, r2] @ movhi + cmp r4, lr + mov r0, r0, lsr #4 + bne .L8020 + b .L7841 +.L7910: + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, r5, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + ldr r8, [sp, #8] + add r0, r0, r3, asr #3 + and r2, ip, #7 + ldr r3, .L8668+24 + add r2, r2, r0, asl #3 + mov r1, lr, lsr #8 + cmp r6, r8 + add r0, r3, r2, asl #2 + and r1, r1, #240 + blt .L8642 + ldr r2, [sp, #4] + add r3, r6, r7 + cmp r2, r3 + bhi .L8125 + rsb r8, r6, r2 + cmp r8, #0 + ble .L7841 + ldr r3, [sp, #0] + movs r7, r8, lsr #3 + add r2, r3, r6, asl #1 + beq .L8128 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L8130: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8131 + ands r3, r4, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L8131: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #32 + add r5, r5, #16 + bne .L8130 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #4 +.L8128: + ands lr, r8, #7 + beq .L7841 + ldr r0, [r0, #0] + mov r4, #0 +.L8150: + movs r3, r0, lsr #28 + ldr r5, [sp, #24] + orr r3, r1, r3 + mov ip, r4, asl #1 + orr r3, r3, r5 + add r4, r4, #1 + strneh r3, [ip, r2] @ movhi + cmp r4, lr + mov r0, r0, asl #4 + bne .L8150 + b .L7841 +.L7911: + cmp r7, #0 + add r3, r7, #7 + mov r1, lr, asl #22 + movge r3, r7 + mov r2, ip, lsr #3 + mov lr, r3, asr #3 + mov r1, r1, lsr #22 + mov r2, r2, asl #1 + mla r0, r2, lr, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr r8, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L8668+24 + cmp r6, r8 + add r1, r0, r3 + blt .L8643 + add r3, r6, r7 + ldr r7, [sp, #4] + cmp r7, r3 + bhi .L8330 + rsb r8, r6, r7 + cmp r8, #0 + ble .L7841 + ldr ip, [sp, #0] + movs r7, r8, lsr #3 + add r2, ip, r6, asl #1 + beq .L8333 + ldr r3, .L8668+32 + mov r5, r2 + add r0, r0, r3 + mov lr, r1 + mov ip, #0 +.L8335: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8336 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #0] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r5, #6] @ movhi +.L8336: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L8345 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r5, #14] @ movhi +.L8345: + add ip, ip, #1 + cmp r7, ip + add lr, lr, #64 + add r5, r5, #16 + add r0, r0, #64 + bne .L8335 + add r1, r1, r7, asl #6 + add r2, r2, r7, asl #4 +.L8333: + ands lr, r8, #7 + beq .L7841 + cmp lr, #3 + ldrls r0, [r1, #0] + bls .L8368 + ldr r0, [r1, #0] + cmp r0, #0 + beq .L8358 + ands r3, r0, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r2, #0] @ movhi + mov r3, r0, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + mov r3, r0, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + movs r3, r0, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi +.L8358: + subs lr, lr, #4 + ldr r0, [r1, #4] + addne r2, r2, #8 + beq .L7841 +.L8368: + mov r1, #0 +.L8369: + ldr ip, [sp, #24] + ands r3, r0, #255 + orr r3, r3, ip + mov ip, r1, asl #1 + add r1, r1, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r1 + mov r0, r0, lsr #8 + bhi .L8369 + b .L7841 +.L7912: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r1, ip, lsr #3 + mov r5, r2, asr #3 + mov r3, r3, asr #3 + mla r0, r5, r1, r3 + mov r2, lr, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + and r3, ip, #7 + add r3, r3, r2, asl #2 + ldr ip, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L8668+24 + cmp r6, ip + add r1, r0, r3 + blt .L8644 + add r3, r6, r7 + ldr r7, [sp, #4] + cmp r3, r7 + bcc .L8550 + rsb r8, r6, r7 + cmp r8, #0 + ble .L7841 + ldr ip, [sp, #0] + movs r7, r8, lsr #3 + add r6, ip, r6, asl #1 + beq .L8553 + ldr r3, .L8668+28 + mov r5, r6 + add r0, r0, r3 + mov lr, r1 + mov ip, #0 +.L8555: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L8556 + ands r3, r4, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L8556: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8565 + ands r3, r4, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r5, #10] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r5, #8] @ movhi +.L8565: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #64 + add r5, r5, #16 + sub r0, r0, #64 + bne .L8555 + rsb r3, r7, r7, asl #26 + add r1, r1, r3, asl #6 + add r6, r6, r7, asl #4 +.L8553: + ands ip, r8, #7 + beq .L7841 + cmp ip, #3 + ldrls r2, [r1, #4] + bls .L8588 + ldr r2, [r1, #4] + cmp r2, #0 + beq .L8578 + ands r3, r2, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r6, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r6, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r6, #2] @ movhi + movs r3, r2, lsr #24 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r6, #0] @ movhi +.L8578: + subs ip, ip, #4 + ldr r2, [r1, #0] + addne r6, r6, #8 + beq .L7841 +.L8588: + mov r1, #0 +.L8589: + ldr r0, [sp, #24] + movs r3, r2, lsr #24 + orr r3, r3, r0 + mov r0, r1, asl #1 + add r1, r1, #1 + strneh r3, [r0, r6] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L8589 + b .L7841 +.L7834: + mov r3, r1, lsr #4 + ldr r1, .L8668+12 + and r3, r3, #992 + add r3, r3, r1 + tst r4, #512 + ldrh r4, [r3, #30] + add r2, r7, r7, lsr #31 + add r1, sl, sl, lsr #31 + str r4, [sp, #20] + mov r4, r2, asr #1 + ldr r2, [sp, #8] + mov r5, r1, asr #1 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r7 + moveq r9, r4 + moveq r0, r5 + movne fp, r7, asl #1 + movne r9, r4, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + str r3, [sp, #16] + bge .L7872 + rsb r2, r6, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L7841 + ldr r6, [sp, #8] + rsb r9, r2, r9 +.L7872: + ldr r2, [sp, #4] + add r3, r6, fp + cmp r3, r2 + blt .L7875 + rsb fp, r6, r2 + cmp fp, #0 + ble .L7841 +.L7875: + mov r3, r8, asl #16 + ldr r8, [sp, #20] + add ip, ip, r0 + mov r2, r1, asl #16 + ldr r0, [sp, #16] + mov r1, r8, asl #16 + mov r2, r2, asr #16 + mov r1, r1, asr #16 + cmp r0, #0 + str r2, [sp, #68] + mov r0, lr, lsr #8 + str r1, [sp, #76] + ldr r2, [sp, #32] + ldr r1, [sp, #0] + mov r4, r4, asl #8 + mov r3, r3, asr #16 + and r0, r0, #240 + str r4, [sp, #88] + str r3, [sp, #64] + mov r5, r5, asl #8 + add r8, r1, r6, asl #1 + rsb r4, ip, r2 + str r0, [sp, #104] + bne .L7877 + ldr r3, [sp, #76] + mla r3, r4, r3, r5 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L7841 + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r1, r0, lsr #3 + mov r3, r3, asr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L8668+24 + add r0, r0, ip, asl #3 + cmp fp, #0 + add r1, r3, r0, asl #2 + ble .L7841 + ldr r3, [sp, #68] + ldr r2, [sp, #64] + mul r3, r4, r3 + mul r2, r9, r2 + ldr r4, [sp, #88] + rsb r3, r2, r3 + add r0, r4, r3 + mov r4, r0, asr #8 + cmp r4, r7 + ldrcs r5, [sp, #16] + bcs .L7883 + b .L8665 +.L7884: + cmp r4, r7 + bcc .L8630 +.L7883: + ldr r6, [sp, #64] + add r5, r5, #1 + add r0, r0, r6 + cmp fp, r5 + mov r4, r0, asr #8 + add r8, r8, #2 + bne .L7884 + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + bne .L8646 +.L8614: + add sp, sp, #112 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L7845: + cmp r7, #0 + add r1, r7, #7 + mov r2, lr, asl #22 + movge r1, r7 + ldr r3, .L8668+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp r9, #0 + str r2, [sp, #100] + str r1, [sp, #60] + ble .L7841 + mov r3, fp, asl #16 + mov fp, r3, asr #16 + ldr r3, [sp, #48] + mul r2, r4, ip + mul r3, r4, r3 + ldr r1, [sp, #56] + ldr r4, [sp, #44] + ldr r0, [sp, #56] + mul r1, fp, r1 + mul r0, r4, r0 + ldr r6, [sp, #92] + ldr ip, [sp, #52] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add lr, ip, r2 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + cmp ip, r7 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L7861 + b .L8666 +.L7862: + cmp ip, r7 + cmpcc r4, sl + bcc .L7863 +.L7861: + ldr r0, [sp, #44] + add r6, r6, #1 + add r5, r5, r0 + add lr, lr, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + add r8, r8, #2 + bne .L7862 + b .L7841 +.L7877: + cmp r7, #0 + add r1, r7, #7 + mov r2, lr, asl #22 + movge r1, r7 + ldr r3, .L8668+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp fp, #0 + str r2, [sp, #96] + str r1, [sp, #80] + ble .L7841 + ldr r6, [sp, #16] + ldr r2, [sp, #76] + mov r3, r6, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #72] + ldr r1, [sp, #72] + ldr r3, [sp, #68] + ldr r0, [sp, #64] + mul r2, r4, r2 + mul r3, r4, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr ip, [sp, #88] + rsb r2, r1, r2 + rsb r3, r0, r3 + add lr, ip, r3 + add r5, r5, r2 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + cmp r4, r7 + cmpcc r2, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L7896 + b .L8667 +.L7897: + cmp r4, r7 + cmpcc r2, sl + bcc .L7899 +.L7896: + ldr r0, [sp, #64] + ldr r1, [sp, #72] + add r6, r6, #1 + add lr, lr, r0 + add r5, r5, r1 + cmp fp, r6 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + add r8, r8, #2 + bne .L7897 + b .L7841 +.L8649: + ldr r3, [sp, #96] + and r0, r2, #7 + add r0, r3, r0, asl #2 + and r1, r2, #7 + mov r3, r2, asr #3 + ldr r2, [sp, #80] + mov ip, r4, asr #1 + mul r2, r3, r2 + and r9, ip, #3 + ldr ip, [sp, #96] + mov r3, r4, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, r4, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst r4, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, r9] @ zero_extendqisi2 + ldr r4, [sp, #104] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr ip, [sp, #24] + ldr r2, [sp, #72] + orr r3, r0, r4 + ldr r1, [sp, #64] + cmp r0, #0 + add r6, r6, #1 + orr r3, r3, ip + strneh r3, [r8, #0] @ movhi + add lr, lr, r1 + add r5, r5, r2 + cmp fp, r6 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + add r8, r8, #2 + ble .L7841 +.L7899: + cmp r2, sl + cmpcc r4, r7 + bcc .L8649 + b .L7841 +.L7886: + cmp r4, r7 + bcs .L7841 +.L8630: + mov r3, r4, asr #1 + and sl, r3, #3 + mov r3, r4, asr #3 + mov r3, r3, asl #5 + mov r2, r4, asr #1 + tst r4, #1 + add ip, r3, r1 + and r6, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r6] @ zero_extendqisi2 + ldrneb r3, [ip, sl] @ zero_extendqisi2 + ldr lr, [sp, #104] + movne r2, r3, lsr #4 + andeq r2, r3, #15 + cmp r2, #0 + orr r3, r2, lr + ldr r2, [sp, #24] + ldr ip, [sp, #64] + add r5, r5, #1 + orr r3, r3, r2 + strneh r3, [r8, #0] @ movhi + add r0, r0, ip + cmp fp, r5 + mov r4, r0, asr #8 + add r8, r8, #2 + bgt .L7886 + b .L7841 +.L7854: + cmp r4, r7 + bcs .L7841 +.L8628: + ldr r1, [sp, #44] + mov r3, r4, asr #3 + add r0, r0, r1 + add r3, lr, r3, asl #6 + and r1, r4, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r3, [sp, #24] + cmp r2, #0 + add ip, ip, #1 + orr r2, r2, r3 + strneh r2, [r8, #0] @ movhi + cmp r9, ip + mov r4, r0, asr #8 + add r8, r8, #2 + bgt .L7854 + b .L7841 +.L8669: + .align 2 +.L8668: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L8644: + rsb r0, r6, ip + rsb r4, r0, r7 + cmp r4, #0 + ble .L7841 + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bhi .L8397 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r6, r1, r3, asl #6 + bne .L8399 + ldr r5, [sp, #108] + ldr r4, [sp, #84] +.L8401: + movs lr, r5, lsr #3 + beq .L8459 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L8461: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L8462 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #0] @ movhi +.L8462: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L8471 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #10] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #8] @ movhi +.L8471: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #16 + bne .L8461 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #4 +.L8459: + ands ip, r5, #7 + beq .L7841 + cmp ip, #3 + ldrls r2, [r6, #4] + bls .L8494 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L8484 + ands r3, r2, #255 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, [sp, #24] + orrne r3, r3, r0 + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #24] + orrne r3, r3, r1 + strneh r3, [r4, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r4, #0] @ movhi +.L8484: + subs ip, ip, #4 + ldr r2, [r6, #0] + addne r4, r4, #8 + beq .L7841 +.L8494: + mov r1, #0 +.L8495: + ldr r5, [sp, #24] + movs r3, r2, lsr #24 + mov r0, r1, asl #1 + orr r3, r3, r5 + add r1, r1, #1 + strneh r3, [r0, r4] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L8495 + b .L7841 +.L8643: + rsb r0, r6, r8 + rsb r4, r0, r7 + cmp r4, #0 + ble .L7841 + ldr ip, [sp, #4] + add r3, r6, r7 + cmp ip, r3 + bhi .L8177 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add r6, r1, r3, asl #6 + bne .L8179 + ldr r5, [sp, #108] + ldr r4, [sp, #84] +.L8181: + movs lr, r5, lsr #3 + beq .L8239 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L8241: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L8242 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #6] @ movhi +.L8242: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L8251 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #14] @ movhi +.L8251: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + add r1, r1, #16 + bne .L8241 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #4 +.L8239: + ands ip, r5, #7 + beq .L7841 + cmp ip, #3 + ldrls r1, [r6, #0] + bls .L8274 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L8264 + ands r3, r2, #255 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, [sp, #24] + orrne r3, r3, r0 + strneh r3, [r4, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #24] + orrne r3, r3, r1 + strneh r3, [r4, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r4, #6] @ movhi +.L8264: + subs ip, ip, #4 + ldr r1, [r6, #4] + addne r4, r4, #8 + beq .L7841 +.L8274: + mov r2, #0 +.L8275: + ldr r5, [sp, #24] + ands r3, r1, #255 + mov r0, r2, asl #1 + orr r3, r3, r5 + add r2, r2, #1 + strneh r3, [r0, r4] @ movhi + cmp ip, r2 + mov r1, r1, lsr #8 + bhi .L8275 + b .L7841 +.L8642: + rsb r4, r6, r8 + rsb ip, r4, r7 + cmp ip, #0 + ble .L7841 + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bhi .L8047 + mov r3, r4, lsr #3 + ands lr, r4, #7 + sub r0, r0, r3, asl #5 + bne .L8049 + ldr r2, [sp, #108] + ldr r8, [sp, #84] +.L8051: + movs r7, r2, lsr #3 + beq .L8068 + mov r5, r8 + mov lr, r0 + mov r6, #0 +.L8070: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8071 + ands r3, r4, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne ip, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L8071: + add r6, r6, #1 + cmp r6, r7 + sub lr, lr, #32 + add r5, r5, #16 + bne .L8070 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r8, r8, r7, asl #4 +.L8068: + ands lr, r2, #7 + beq .L7841 + ldr r0, [r0, #0] + mov ip, #0 +.L8090: + movs r3, r0, lsr #28 + ldr r5, [sp, #24] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r5 + add ip, ip, #1 + strneh r3, [r2, r8] @ movhi + cmp ip, lr + mov r0, r0, asl #4 + bne .L8090 + b .L7841 +.L8641: + ldr r3, [sp, #8] + rsb r4, r6, r3 + rsb r5, r4, r7 + cmp r5, #0 + ble .L7841 + add r3, r6, r7 + ldr r6, [sp, #4] + cmp r6, r3 + bhi .L7917 + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add r5, r0, r2 + bne .L7919 + ldr r7, [sp, #108] + ldr r6, [sp, #84] +.L7921: + movs r4, r7, lsr #3 + beq .L7938 + mov ip, r6 + mov r0, r5 + mov lr, #0 +.L7940: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L7941 + ands r3, r2, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + ldrne r2, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r2 + strneh r3, [ip, #14] @ movhi +.L7941: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #32 + add ip, ip, #16 + bne .L7940 + add r5, r5, r4, asl #5 + add r6, r6, r4, asl #4 +.L7938: + ands lr, r7, #7 + beq .L7841 + ldr r2, [r5, #0] + mov r0, #0 +.L7960: + ands r3, r2, #15 + ldr r4, [sp, #24] + orr r3, r1, r3 + mov ip, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [ip, r6] @ movhi + cmp r0, lr + mov r2, r2, lsr #4 + bne .L7960 + b .L7841 +.L8666: + mov r6, #0 +.L7863: + cmp r4, sl + movcc r3, #0 + movcs r3, #1 + cmp r7, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L8629 + b .L7841 +.L7864: + cmp r4, sl + cmpcc ip, r7 + bcs .L7841 +.L8629: + and r3, r4, #7 + mov r2, ip, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + ldr r2, [sp, #100] + ldr r0, [sp, #60] + add r3, r3, r2 + mov r2, r4, asr #3 + mla r0, r2, r0, r3 + ldr r1, [sp, #44] + add r6, r6, #1 + add r5, r5, r1 + and r1, ip, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + ldr r0, [sp, #24] + cmp r3, #0 + orr r3, r3, r0 + strneh r3, [r8, #0] @ movhi + add lr, lr, fp + cmp r9, r6 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + add r8, r8, #2 + bgt .L7864 + b .L7841 +.L8125: + cmp r5, #0 + beq .L7841 + ldr r7, [sp, #0] + mov ip, #0 + add r2, r7, r6, asl #1 + b .L8155 +.L8650: + sub r0, r0, #32 + add r2, r2, #16 +.L8155: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L8156 + ands r3, r4, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r2, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #0] @ movhi +.L8156: + add ip, ip, #1 + cmp r5, ip + bne .L8650 + b .L7841 +.L8550: + cmp r5, #0 + beq .L7841 + ldr r3, [sp, #0] + mov ip, #0 + add r2, r3, r6, asl #1 + ldr r3, .L8668+28 + add r0, r0, r3 + b .L8594 +.L8651: + sub r1, r1, #64 + add r2, r2, #16 +.L8594: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L8595 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r2, #2] @ movhi + movs r3, r4, lsr #24 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r2, #0] @ movhi +.L8595: + ldr r4, [r1, #0] + cmp r4, #0 + beq .L8604 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r2, #14] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r2, #12] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r2, #10] @ movhi + movs r3, r4, lsr #24 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r2, #8] @ movhi +.L8604: + add ip, ip, #1 + cmp r5, ip + sub r0, r0, #64 + bne .L8651 + b .L7841 +.L7995: + cmp r5, #0 + beq .L7841 + ldr r7, [sp, #0] + mov ip, #0 + add r2, r7, r6, asl #1 + b .L8025 +.L8652: + add r0, r0, #32 + add r2, r2, #16 +.L8025: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L8026 + ands r3, r4, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #0] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r2, #2] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #12] @ movhi + movs r3, r4, lsr #28 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #14] @ movhi +.L8026: + add ip, ip, #1 + cmp r5, ip + bne .L8652 + b .L7841 +.L8330: + cmp lr, #0 + beq .L7841 + ldr r3, [sp, #0] + mov ip, #0 + add r2, r3, r6, asl #1 + ldr r3, .L8668+32 + add r0, r0, r3 + b .L8374 +.L8653: + add r1, r1, #64 + add r2, r2, #16 +.L8374: + ldr r4, [r1, #0] + cmp r4, #0 + beq .L8375 + ands r3, r4, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r2, #0] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + movs r3, r4, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi +.L8375: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L8384 + ands r3, r4, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r2, #12] @ movhi + movs r3, r4, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r2, #14] @ movhi +.L8384: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + bne .L8653 + b .L7841 +.L8177: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r0, r1, r3, asl #6 + ldreq r1, [sp, #84] + beq .L8281 + cmp r2, #3 + rsb lr, r2, #8 + bhi .L8654 + subs r5, lr, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #84] + beq .L8294 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov ip, #0 +.L8295: + ands r3, r2, #255 + ldr r1, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r3, r1 + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r6] @ movhi + cmp ip, r5 + mov r2, r2, lsr #8 + bne .L8295 + ldr r7, [sp, #84] + add r3, r7, lr, asl #1 + sub r1, r3, #8 +.L8294: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L8300 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, r3, ip + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r1, #6] @ movhi +.L8300: + add r1, r1, #8 +.L8286: + add r0, r0, #64 +.L8281: + movs lr, r4, lsr #3 + beq .L7841 + mov ip, #0 + b .L8310 +.L8655: + add r0, r0, #64 + add r1, r1, #16 +.L8310: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L8311 + ands r3, r2, #255 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r1, #6] @ movhi +.L8311: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L8320 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r1, #14] @ movhi +.L8320: + add ip, ip, #1 + cmp lr, ip + bne .L8655 + b .L7841 +.L8047: + ands r2, r4, #7 + mov r3, r4, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r5, [sp, #84] + beq .L8096 + rsbs lr, r2, #8 + ldr r4, [r0, #0] + ldreq r5, [sp, #84] + beq .L8099 + mov r3, r2, asl #2 + mov r4, r4, asl r3 + mov r6, #0 +.L8100: + movs r3, r4, lsr #28 + ldr r7, [sp, #24] + ldrne r8, [sp, #84] + orr r3, r1, r3 + mov r5, r6, asl #1 + orr r3, r3, r7 + add r6, r6, #1 + strneh r3, [r5, r8] @ movhi + cmp lr, r6 + mov r4, r4, asl #4 + bne .L8100 + ldr r2, [sp, #84] + add r5, r2, lr, asl #1 +.L8099: + sub r0, r0, #32 +.L8096: + movs ip, ip, lsr #3 + beq .L7841 + mov r2, #0 + b .L8106 +.L8656: + sub r0, r0, #32 + add r5, r5, #16 +.L8106: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L8107 + ands r3, r4, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne lr, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r5, #0] @ movhi +.L8107: + add r2, r2, #1 + cmp r2, ip + bne .L8656 + b .L7841 +.L8397: + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r2, r1, r3, asl #6 + ldreq r0, [sp, #84] + beq .L8501 + cmp ip, #3 + rsb lr, ip, #8 + bhi .L8657 + subs r5, lr, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #84] + beq .L8514 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, #0 +.L8515: + movs r3, r1, lsr #24 + ldr r0, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r3, r0 + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp r5, ip + mov r1, r1, asl #8 + bne .L8515 + ldr r7, [sp, #84] + add r3, r7, lr, asl #1 + sub r0, r3, #8 +.L8514: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L8520 + ands r3, r1, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, r3, ip + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, r3, lr + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r1, [sp, #24] + orrne r3, r3, r1 + strneh r3, [r0, #0] @ movhi +.L8520: + add r0, r0, #8 +.L8506: + sub r2, r2, #64 +.L8501: + movs lr, r4, lsr #3 + beq .L7841 + mov ip, #0 + b .L8530 +.L8658: + sub r2, r2, #64 + add r0, r0, #16 +.L8530: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L8531 + ands r3, r1, #255 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r7, [sp, #24] + orrne r3, r3, r7 + strneh r3, [r0, #0] @ movhi +.L8531: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L8540 + ands r3, r1, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r0, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #24] + orrne r3, r3, r4 + strneh r3, [r0, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r3, r5 + strneh r3, [r0, #10] @ movhi + movs r3, r1, lsr #24 + ldrne r6, [sp, #24] + orrne r3, r3, r6 + strneh r3, [r0, #8] @ movhi +.L8540: + add ip, ip, #1 + cmp ip, lr + bne .L8658 + b .L7841 +.L7917: + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add lr, r0, r2 + ldreq ip, [sp, #84] + beq .L7966 + rsbs r4, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #84] + beq .L7969 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov ip, #0 +.L7970: + ands r3, r0, #15 + ldr r6, [sp, #24] + ldrne r7, [sp, #84] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r2, r7] @ movhi + cmp ip, r4 + mov r0, r0, lsr #4 + bne .L7970 + ldr r8, [sp, #84] + add ip, r8, r4, asl #1 +.L7969: + add lr, lr, #32 +.L7966: + movs r4, r5, lsr #3 + beq .L7841 + mov r0, #0 + b .L7976 +.L8659: + add lr, lr, #32 + add ip, ip, #16 +.L7976: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L7977 + ands r3, r2, #15 + ldrne r5, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + ldrne r8, [sp, #24] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #14] @ movhi +.L7977: + add r0, r0, #1 + cmp r0, r4 + bne .L8659 + b .L7841 +.L8179: + ldr r0, [sp, #108] + rsb lr, ip, #8 + cmp r0, lr + blt .L8660 + cmp ip, #3 + bls .L8212 + cmp lr, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #84] + beq .L8216 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r0, #0 +.L8217: + ands r3, r1, #255 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + mov r2, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r2, ip] @ movhi + cmp lr, r0 + mov r1, r1, lsr #8 + bne .L8217 + ldr r0, [sp, #84] + add r4, r0, lr, asl #1 +.L8216: + ldr r3, [sp, #108] + add r6, r6, #64 + rsb r5, lr, r3 + b .L8181 +.L8049: + ldr r2, [sp, #108] + rsb r6, lr, #8 + cmp r2, r6 + blt .L8661 + cmp r6, #0 + ldr r2, [r0, #0] + ldreq r8, [sp, #84] + beq .L8062 + mov r3, lr, asl #2 + mov lr, r2, asl r3 + mov r5, #0 +.L8063: + movs r3, lr, lsr #28 + ldr r7, [sp, #24] + ldrne r8, [sp, #84] + orr r3, r1, r3 + mov r4, r5, asl #1 + orr r3, r3, r7 + add r5, r5, #1 + strneh r3, [r4, r8] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L8063 + ldr ip, [sp, #84] + add r8, ip, r6, asl #1 +.L8062: + ldr lr, [sp, #108] + sub r0, r0, #32 + rsb r2, r6, lr + b .L8051 +.L7919: + ldr r7, [sp, #108] + rsb lr, r3, #8 + cmp r7, lr + blt .L8662 + cmp lr, #0 + ldr r2, [r5, #0] + ldreq r6, [sp, #84] + beq .L7932 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov ip, #0 +.L7933: + ands r3, r2, #15 + ldr r4, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r1, r3 + mov r0, ip, asl #1 + orr r3, r3, r4 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp lr, ip + mov r2, r2, lsr #4 + bne .L7933 + ldr r7, [sp, #84] + add r6, r7, lr, asl #1 +.L7932: + ldr r8, [sp, #108] + add r5, r5, #32 + rsb r7, lr, r8 + b .L7921 +.L8399: + ldr r0, [sp, #108] + rsb lr, ip, #8 + cmp r0, lr + blt .L8663 + cmp ip, #3 + bls .L8432 + cmp lr, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #84] + beq .L8436 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L8437: + movs r3, r2, lsr #24 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + mov r1, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r1, ip] @ movhi + cmp lr, r0 + mov r2, r2, asl #8 + bne .L8437 + ldr r0, [sp, #84] + add r4, r0, lr, asl #1 +.L8436: + ldr r3, [sp, #108] + sub r6, r6, #64 + rsb r5, lr, r3 + b .L8401 +.L8663: + cmp r0, #0 + ble .L7841 + cmp ip, #3 + bls .L8405 + ldr r2, [r6, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L8408: + movs r3, r2, lsr #24 + ldr r1, [sp, #24] + ldrne r4, [sp, #84] + ldr r5, [sp, #108] + orr r3, r3, r1 + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp r5, r0 + mov r2, r2, asl #8 + bne .L8408 + b .L7841 +.L8662: + cmp r7, #0 + ble .L7841 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov ip, #0 +.L7926: + ands r3, r0, #15 + ldr r8, [sp, #24] + ldrne lr, [sp, #84] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r8 + strneh r3, [r2, lr] @ movhi + ldr r2, [sp, #108] + add ip, ip, #1 + cmp r2, ip + mov r0, r0, lsr #4 + bne .L7926 + b .L7841 +.L8661: + cmp r2, #0 + ble .L7841 + ldr r2, [r0, #0] + mov r3, lr, asl #2 + mov r0, r2, asl r3 + mov ip, #0 +.L8056: + movs r3, r0, lsr #28 + ldr r4, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r1, r3 + ldr r6, [sp, #108] + mov r2, ip, asl #1 + orr r3, r3, r4 + add ip, ip, #1 + strneh r3, [r2, r5] @ movhi + cmp r6, ip + mov r0, r0, asl #4 + bne .L8056 + b .L7841 +.L8657: + cmp lr, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #84] + beq .L8506 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, #0 +.L8507: + movs r3, r1, lsr #24 + ldr r6, [sp, #24] + ldrne r7, [sp, #84] + mov r0, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp ip, lr + mov r1, r1, asl #8 + bne .L8507 + ldr r8, [sp, #84] + sub r2, r2, #64 + add r0, r8, lr, asl #1 + b .L8501 +.L8654: + cmp lr, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #84] + beq .L8286 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov ip, #0 +.L8287: + ands r3, r2, #255 + ldr r6, [sp, #24] + ldrne r7, [sp, #84] + mov r1, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r1, r7] @ movhi + cmp ip, lr + mov r2, r2, lsr #8 + bne .L8287 + ldr r8, [sp, #84] + add r0, r0, #64 + add r1, r8, lr, asl #1 + b .L8281 +.L8660: + cmp r0, #0 + ble .L7841 + cmp ip, #3 + bls .L8185 + ldr r2, [r6, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r0, #0 +.L8188: + ands r3, r1, #255 + ldr r2, [sp, #24] + ldrne r4, [sp, #84] + ldr r5, [sp, #108] + orr r3, r3, r2 + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, r0 + mov r1, r1, lsr #8 + bne .L8188 + b .L7841 +.L8667: + mov r6, #0 + b .L7899 +.L8432: + subs r4, lr, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #84] + beq .L8444 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L8445: + movs r3, r2, lsr #24 + ldr r1, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r3, r1 + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r5] @ movhi + cmp r4, r0 + mov r2, r2, asl #8 + bne .L8445 + ldr r7, [sp, #84] + add r3, r7, lr, asl #1 + sub r1, r3, #8 +.L8444: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L8450 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, r3, ip + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r0, [sp, #24] + orrne r3, r3, r0 + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r1, #0] @ movhi +.L8450: + add r4, r1, #8 + b .L8436 +.L8212: + subs r4, lr, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #84] + beq .L8224 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r0, #0 +.L8225: + ands r3, r1, #255 + ldr r2, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r3, r2 + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r5] @ movhi + cmp r0, r4 + mov r1, r1, lsr #8 + bne .L8225 + ldr r7, [sp, #84] + add r3, r7, lr, asl #1 + sub r1, r3, #8 +.L8224: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L8230 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r3, r8 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, r3, ip + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r0, [sp, #24] + orrne r3, r3, r0 + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r3, r2 + strneh r3, [r1, #6] @ movhi +.L8230: + add r4, r1, #8 + b .L8216 +.L8665: + ldr r5, [sp, #16] + b .L8630 +.L8664: + mov ip, fp + b .L8628 +.L8405: + ldr r7, [sp, #108] + mov r3, ip, asl #3 + ldr r1, [r6, #4] + add r2, r7, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L8412 + cmp r7, #0 + movne r0, #0 + beq .L7841 +.L8428: + movs r3, r1, lsr #24 + ldr r5, [sp, #24] + ldrne r6, [sp, #84] + ldr r7, [sp, #108] + mov r2, r0, asl #1 + orr r3, r3, r5 + add r0, r0, #1 + strneh r3, [r2, r6] @ movhi + cmp r7, r0 + mov r1, r1, asl #8 + bne .L8428 + b .L7841 +.L8185: + ldr r7, [sp, #108] + ldr r3, [r6, #0] + add r2, r7, ip + cmp r2, #4 + mov r1, ip, asl #3 + mov r2, r3, lsr r1 + bhi .L8192 + cmp r7, #0 + movne r0, #0 + beq .L7841 +.L8208: + ands r3, r2, #255 + ldr r5, [sp, #24] + ldrne r6, [sp, #84] + ldr r7, [sp, #108] + mov r1, r0, asl #1 + orr r3, r3, r5 + add r0, r0, #1 + strneh r3, [r1, r6] @ movhi + cmp r7, r0 + mov r2, r2, lsr #8 + bne .L8208 + b .L7841 +.L8412: + rsbs ip, ip, #4 + ldreq lr, [sp, #84] + beq .L8417 + mov r0, #0 +.L8418: + movs r3, r1, lsr #24 + ldr r8, [sp, #24] + ldrne lr, [sp, #84] + mov r2, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r2, lr] @ movhi + cmp r0, ip + mov r1, r1, asl #8 + bne .L8418 + ldr r0, [sp, #84] + add lr, r0, ip, asl #1 +.L8417: + ldr r1, [sp, #108] + ldr r2, [r6, #0] + subs ip, r1, ip + beq .L7841 + mov r0, #0 +.L8424: + ldr r4, [sp, #24] + movs r3, r2, lsr #24 + mov r1, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L8424 + b .L7841 +.L8192: + rsbs ip, ip, #4 + ldreq lr, [sp, #84] + beq .L8197 + mov r0, #0 +.L8198: + ands r3, r2, #255 + ldr r8, [sp, #24] + ldrne lr, [sp, #84] + mov r1, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L8198 + ldr r0, [sp, #84] + add lr, r0, ip, asl #1 +.L8197: + ldr r1, [sp, #108] + ldr r2, [r6, #4] + subs ip, r1, ip + beq .L7841 + mov r0, #0 +.L8204: + ldr r4, [sp, #24] + ands r3, r2, #255 + mov r1, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L8204 + b .L7841 + .size render_scanline_obj_color16_1D, .-render_scanline_obj_color16_1D + .align 2 + .global render_scanline_obj_color16_2D + .type render_scanline_obj_color16_2D, %function +render_scanline_obj_color16_2D: + @ args = 0, pretend = 0, frame = 96 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L9512 + sub sp, sp, #96 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #36] + ldr r5, [sp, #36] + ldrh r4, [ip, #80] + ldr ip, .L9512+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #40] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L9512+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #44] + str r1, [sp, #12] + str r2, [sp, #8] + str r3, [sp, #4] + str lr, [sp, #28] + beq .L9458 + mov r8, #0 + add r6, r3, r1, asl #1 + rsb r7, r1, r2 + str r6, [sp, #68] + str r7, [sp, #92] + str r8, [sp, #32] + mov ip, r8 +.L8673: + ldr lr, [sp, #44] + ldr r0, .L9512+12 + ldrb r3, [ip, lr] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh r4, [r3, r0] + add r3, r3, r0 + ldrh r1, [r3, #2] + mov r5, r4, lsr #12 + and r2, r5, #12 + orr r0, r2, r1, lsr #14 + and ip, r4, #255 + mov r2, r1, asl #23 + cmp ip, #160 + ldrh lr, [r3, #4] + mov r6, r2, asr #23 + ldr r3, .L9512+16 + ldr r2, .L9512+20 + subgt ip, ip, #256 + tst r4, #256 + ldr r8, [r2, r0, asl #2] + ldr sl, [r3, r0, asl #2] + beq .L8676 + tst r4, #8192 + beq .L8678 + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L9512+12 + and r3, r3, #992 + add r3, r3, r4 + add r2, r8, r8, lsr #31 + ldrh r5, [r3, #30] + mov r4, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + movne r0, r4, asl #1 + str r5, [sp, #16] + mov r5, r1, asr #1 + strne r0, [sp, #52] + moveq r9, r8 + streq r4, [sp, #52] + moveq r0, r5 + movne r9, r8, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + ldrh r7, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L8683 + rsb r2, r6, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L8685 + ldr r3, [sp, #52] + ldr r6, [sp, #12] + rsb r3, r2, r3 + str r3, [sp, #52] +.L8683: + ldr r2, [sp, #8] + add r3, r6, r9 + cmp r3, r2 + blt .L8687 + rsb r9, r6, r2 + cmp r9, #0 + ble .L8685 +.L8687: + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r7, [sp, #16] + mov r3, r3, asr #16 + add r0, ip, r0 + str r3, [sp, #48] + mov ip, r2, asr #16 + ldr r3, [sp, #36] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov r4, r4, asl #8 + cmp fp, #0 + str r4, [sp, #76] + mov r1, r1, asr #16 + mov r4, r5, asl #8 + add r7, r2, r6, asl #1 + rsb r0, r0, r3 + bne .L8689 + mla r3, r0, r1, r4 + mov r1, r3, asr #8 + cmp r1, sl + bcs .L8685 + mov r3, lr, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L9512+24 + cmp r9, #0 + add lr, r3, r1, asl #3 + ble .L8685 + ldr r4, [sp, #48] + ldr r2, [sp, #52] + mul r3, r0, ip + mul r2, r4, r2 + ldr r5, [sp, #76] + rsb r3, r2, r3 + add r0, r5, r3 + mov r4, r0, asr #8 + cmp r4, r8 + movcs ip, fp + bcs .L8695 + b .L9508 +.L8696: + cmp r4, r8 + bcc .L9472 +.L8695: + ldr r6, [sp, #48] + add ip, ip, #1 + add r0, r0, r6 + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #2 + bne .L8696 +.L8685: + ldr ip, [sp, #32] + ldr lr, [sp, #40] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #32] + beq .L9458 +.L9490: + ldr ip, [sp, #32] + b .L8673 +.L8676: + ldr r2, [sp, #36] + tst r1, #8192 + rsb r0, ip, r2 + rsbne r3, r0, sl + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, r5, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L8685 + .p2align 2 +.L8757: + .word .L8753 + .word .L8754 + .word .L8755 + .word .L8756 +.L8753: + mov r3, lr, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + mov r2, lr, lsr #8 + cmp r6, r3 + ldr r3, .L9512+24 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L9485 + ldr ip, [sp, #8] + add r3, r6, r8 + cmp ip, r3 + bhi .L8839 + rsb r8, r6, ip + cmp r8, #0 + ble .L8685 + ldr lr, [sp, #4] + movs r7, r8, lsr #3 + add r2, lr, r6, asl #1 + beq .L8842 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L8844: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8845 + ands r3, r4, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #0] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #14] @ movhi +.L8845: + add ip, ip, #1 + cmp ip, r7 + add lr, lr, #32 + add r5, r5, #16 + bne .L8844 + add r0, r0, r7, asl #5 + add r2, r2, r7, asl #4 +.L8842: + ands lr, r8, #7 + beq .L8685 + ldr r0, [r0, #0] + mov r4, #0 +.L8864: + ands r3, r0, #15 + ldr r5, [sp, #28] + orr r3, r1, r3 + mov ip, r4, asl #1 + orr r3, r3, r5 + add r4, r4, #1 + strneh r3, [ip, r2] @ movhi + cmp r4, lr + mov r0, r0, lsr #4 + bne .L8864 + b .L8685 +.L8754: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + subs r2, r8, #8 + mov r3, r3, lsr #22 + submi r2, r8, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr ip, [sp, #12] + add r1, r1, r3, asl #3 + ldr r3, .L9512+24 + mov r2, lr, lsr #8 + cmp r6, ip + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L9486 + ldr r2, [sp, #8] + add r3, r6, r8 + cmp r2, r3 + bhi .L8969 + rsb r8, r6, r2 + cmp r8, #0 + ble .L8685 + ldr r3, [sp, #4] + movs r7, r8, lsr #3 + add r2, r3, r6, asl #1 + beq .L8972 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L8974: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8975 + ands r3, r4, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L8975: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #32 + add r5, r5, #16 + bne .L8974 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #4 +.L8972: + ands lr, r8, #7 + beq .L8685 + ldr r0, [r0, #0] + mov r4, #0 +.L8994: + movs r3, r0, lsr #28 + ldr r5, [sp, #28] + orr r3, r1, r3 + mov ip, r4, asl #1 + orr r3, r3, r5 + add r4, r4, #1 + strneh r3, [ip, r2] @ movhi + cmp r4, lr + mov r0, r0, asl #4 + bne .L8994 + b .L8685 +.L8755: + mov r2, lr, asl #22 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + and r3, r0, #7 + add r2, r2, r1, asl #5 + add r3, r3, r2, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L9512+24 + cmp r6, ip + add ip, r0, r3 + blt .L9487 + ldr r7, [sp, #8] + add r3, r6, r8 + cmp r7, r3 + bhi .L9174 + rsb r8, r6, r7 + cmp r8, #0 + ble .L8685 + ldr lr, [sp, #4] + movs r7, r8, lsr #3 + add r2, lr, r6, asl #1 + beq .L9177 + ldr r3, .L9512+32 + mov r5, r2 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L9179: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L9180 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #0] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #2] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #4] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r5, #6] @ movhi +.L9180: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L9189 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r5, #12] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r5, #14] @ movhi +.L9189: + add r1, r1, #1 + cmp r7, r1 + add lr, lr, #64 + add r5, r5, #16 + add r0, r0, #64 + bne .L9179 + add ip, ip, r7, asl #6 + add r2, r2, r7, asl #4 +.L9177: + ands lr, r8, #7 + beq .L8685 + cmp lr, #3 + ldrls r0, [ip, #0] + bls .L9212 + ldr r1, [ip, #0] + cmp r1, #0 + beq .L9202 + ands r3, r1, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r2, #0] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + movs r3, r1, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi +.L9202: + subs lr, lr, #4 + ldr r0, [ip, #4] + addne r2, r2, #8 + beq .L8685 +.L9212: + mov r1, #0 +.L9213: + ldr ip, [sp, #28] + ands r3, r0, #255 + orr r3, r3, ip + mov ip, r1, asl #1 + add r1, r1, #1 + strneh r3, [ip, r2] @ movhi + cmp lr, r1 + mov r0, r0, lsr #8 + bhi .L9213 + b .L8685 +.L8756: + subs r2, r8, #8 + submi r2, r8, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, lr, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L9512+24 + cmp r6, ip + add ip, r0, r3 + blt .L9488 + ldr r7, [sp, #8] + add r3, r6, r8 + cmp r3, r7 + bcc .L9394 + rsb r8, r6, r7 + cmp r8, #0 + ble .L8685 + ldr lr, [sp, #4] + movs r7, r8, lsr #3 + add r6, lr, r6, asl #1 + beq .L9397 + ldr r3, .L9512+28 + mov r5, r6 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L9399: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L9400 + ands r3, r4, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L9400: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L9409 + ands r3, r4, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r5, #10] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r5, #8] @ movhi +.L9409: + add r1, r1, #1 + cmp r1, r7 + sub lr, lr, #64 + add r5, r5, #16 + sub r0, r0, #64 + bne .L9399 + rsb r3, r7, r7, asl #26 + add ip, ip, r3, asl #6 + add r6, r6, r7, asl #4 +.L9397: + ands lr, r8, #7 + beq .L8685 + cmp lr, #3 + ldrls r2, [ip, #4] + bls .L9432 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L9422 + ands r3, r2, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r6, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r6, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r6, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r0, [sp, #28] + orrne r3, r3, r0 + strneh r3, [r6, #0] @ movhi +.L9422: + subs lr, lr, #4 + ldr r2, [ip, #0] + addne r6, r6, #8 + beq .L8685 +.L9432: + mov r1, #0 +.L9433: + ldr r4, [sp, #28] + movs r3, r2, lsr #24 + mov r0, r1, asl #1 + orr r3, r3, r4 + add r1, r1, #1 + strneh r3, [r0, r6] @ movhi + cmp lr, r1 + mov r2, r2, asl #8 + bhi .L9433 + b .L8685 +.L8678: + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L9512+12 + and r3, r3, #992 + add r3, r3, r4 + ldrh r5, [r3, #30] + add r2, r8, r8, lsr #31 + mov r4, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + str r5, [sp, #24] + ldrh r7, [r3, #6] + mov r5, r1, asr #1 + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r8 + moveq r9, r4 + moveq r0, r5 + movne fp, r8, asl #1 + movne r9, r4, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + str r3, [sp, #20] + bge .L8716 + rsb r2, r6, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L8685 + ldr r6, [sp, #12] + rsb r9, r2, r9 +.L8716: + ldr r2, [sp, #8] + add r3, r6, fp + cmp r3, r2 + blt .L8719 + rsb fp, r6, r2 + cmp fp, #0 + ble .L8685 +.L8719: + add ip, ip, r0 + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r0, [sp, #20] + ldr r7, [sp, #24] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + cmp r0, #0 + str r3, [sp, #56] + mov r0, lr, lsr #8 + str r2, [sp, #60] + ldr r3, [sp, #36] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov r4, r4, asl #8 + and r0, r0, #240 + str r4, [sp, #72] + mov r1, r1, asr #16 + mov r4, r5, asl #8 + add r7, r2, r6, asl #1 + rsb ip, ip, r3 + str r0, [sp, #88] + bne .L8721 + mla r3, ip, r1, r4 + mov r1, r3, asr #8 + cmp r1, sl + bcs .L8685 + mov r3, lr, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #3 + ldr r3, .L9512+24 + cmp fp, #0 + add r1, r3, r1, asl #2 + ble .L8685 + ldr r3, [sp, #60] + ldr r2, [sp, #56] + mul r3, ip, r3 + mul r2, r9, r2 + ldr r4, [sp, #72] + rsb r3, r2, r3 + add r0, r4, r3 + mov r4, r0, asr #8 + cmp r4, r8 + ldrcs r5, [sp, #20] + bcs .L8727 + b .L9509 +.L8728: + cmp r4, r8 + bcc .L9474 +.L8727: + ldr r6, [sp, #56] + add r5, r5, #1 + add r0, r0, r6 + cmp fp, r5 + mov r4, r0, asr #8 + add r7, r7, #2 + bne .L8728 + ldr ip, [sp, #32] + ldr lr, [sp, #40] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #32] + bne .L9490 +.L9458: + add sp, sp, #96 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L8689: + mov r3, lr, asl #22 + ldr r2, .L9512+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r9, #0 + str r3, [sp, #84] + ble .L8685 + mov r3, fp, asl #16 + mul r2, r0, r1 + mov fp, r3, asr #16 + ldr r5, [sp, #48] + mul r3, r0, ip + ldr r1, [sp, #52] + ldr r0, [sp, #52] + mul r1, fp, r1 + mul r0, r5, r0 + ldr r6, [sp, #76] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add lr, r4, r2 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + cmp ip, r8 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L8705 + b .L9510 +.L8706: + cmp ip, r8 + cmpcc r4, sl + bcc .L8707 +.L8705: + ldr ip, [sp, #48] + add r6, r6, #1 + add r5, r5, ip + add lr, lr, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + add r7, r7, #2 + bne .L8706 + b .L8685 +.L8721: + mov r3, lr, asl #22 + ldr r2, .L9512+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp fp, #0 + str r3, [sp, #80] + ble .L8685 + ldr r5, [sp, #20] + mul r2, ip, r1 + mov r3, r5, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #64] + ldr r1, [sp, #64] + ldr r3, [sp, #60] + ldr r0, [sp, #56] + mul r3, ip, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr r6, [sp, #72] + rsb r3, r0, r3 + rsb r2, r1, r2 + add lr, r6, r3 + add r5, r4, r2 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + cmp ip, r8 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L8740 + b .L9511 +.L8741: + cmp ip, r8 + cmpcc r4, sl + bcc .L8743 +.L8740: + ldr ip, [sp, #56] + ldr r0, [sp, #64] + add r6, r6, #1 + add lr, lr, ip + add r5, r5, r0 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #2 + bne .L8741 + b .L8685 +.L9493: + mov r3, ip, asr #1 + ldr r1, [sp, #80] + and r3, r3, #3 + and r0, r4, #7 + str r3, [sp, #0] + ldr r3, [sp, #80] + add r0, r1, r0, asl #2 + and r1, r4, #7 + mov r2, ip, asr #1 + add r1, r3, r1, asl #2 + mov r3, r4, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + tst ip, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne r4, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, r4] @ zero_extendqisi2 + ldr r2, [sp, #88] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + cmp r0, #0 + orr r3, r0, r2 + ldr r0, [sp, #28] + ldr ip, [sp, #56] + ldr r1, [sp, #64] + add r6, r6, #1 + orr r3, r3, r0 + strneh r3, [r7, #0] @ movhi + add lr, lr, ip + add r5, r5, r1 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #2 + ble .L8685 +.L8743: + cmp r4, sl + cmpcc ip, r8 + bcc .L9493 + b .L8685 +.L8730: + cmp r4, r8 + bcs .L8685 +.L9474: + mov r3, r4, asr #1 + and sl, r3, #3 + mov r3, r4, asr #3 + mov r3, r3, asl #5 + mov r2, r4, asr #1 + tst r4, #1 + add ip, r3, r1 + and r6, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r6] @ zero_extendqisi2 + ldrneb r3, [ip, sl] @ zero_extendqisi2 + ldr lr, [sp, #88] + movne r2, r3, lsr #4 + andeq r2, r3, #15 + cmp r2, #0 + orr r3, r2, lr + ldr r2, [sp, #28] + ldr ip, [sp, #56] + add r5, r5, #1 + orr r3, r3, r2 + strneh r3, [r7, #0] @ movhi + add r0, r0, ip + cmp fp, r5 + mov r4, r0, asr #8 + add r7, r7, #2 + bgt .L8730 + b .L8685 +.L8698: + cmp r4, r8 + bcs .L8685 +.L9472: + ldr r1, [sp, #48] + mov r3, r4, asr #3 + add r0, r0, r1 + add r3, lr, r3, asl #6 + and r1, r4, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r3, [sp, #28] + cmp r2, #0 + add ip, ip, #1 + orr r2, r2, r3 + strneh r2, [r7, #0] @ movhi + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #2 + bgt .L8698 + b .L8685 +.L9488: + ldr lr, [sp, #12] + rsb r1, r6, lr + rsb r4, r1, r8 + cmp r4, #0 + ble .L8685 + ldr r0, [sp, #8] + add r3, r6, r8 + cmp r0, r3 + bhi .L9241 + mov r3, r1, lsr #3 + ands r0, r1, #7 + sub r6, ip, r3, asl #6 + bne .L9243 + ldr r5, [sp, #92] + ldr r4, [sp, #68] +.L9245: + movs lr, r5, lsr #3 + beq .L9303 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L9305: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9306 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #0] @ movhi +.L9306: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9315 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #12] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #10] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #8] @ movhi +.L9315: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #16 + bne .L9305 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #4 +.L9303: + ands ip, r5, #7 + beq .L8685 + cmp ip, #3 + ldrls r2, [r6, #4] + bls .L9338 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L9328 + ands r3, r2, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r4, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, [sp, #28] + orrne r3, r3, r0 + strneh r3, [r4, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r3, r1 + strneh r3, [r4, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r4, #0] @ movhi +.L9328: + subs ip, ip, #4 + ldr r2, [r6, #0] + addne r4, r4, #8 + beq .L8685 +.L9338: + mov r1, #0 +.L9339: + ldr r5, [sp, #28] + movs r3, r2, lsr #24 + mov r0, r1, asl #1 + orr r3, r3, r5 + add r1, r1, #1 + strneh r3, [r0, r4] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L9339 + b .L8685 +.L9513: + .align 2 +.L9512: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L9487: + ldr lr, [sp, #12] + rsb r1, r6, lr + rsb r4, r1, r8 + cmp r4, #0 + ble .L8685 + ldr r0, [sp, #8] + add r3, r6, r8 + cmp r0, r3 + bhi .L9021 + mov r3, r1, lsr #3 + ands r0, r1, #7 + add r6, ip, r3, asl #6 + bne .L9023 + ldr r5, [sp, #92] + ldr r4, [sp, #68] +.L9025: + movs lr, r5, lsr #3 + beq .L9083 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L9085: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9086 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #6] @ movhi +.L9086: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9095 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #14] @ movhi +.L9095: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + add r1, r1, #16 + bne .L9085 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #4 +.L9083: + ands ip, r5, #7 + beq .L8685 + cmp ip, #3 + ldrls r1, [r6, #0] + bls .L9118 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L9108 + ands r3, r2, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r4, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r0, [sp, #28] + orrne r3, r3, r0 + strneh r3, [r4, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r3, r1 + strneh r3, [r4, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r4, #6] @ movhi +.L9108: + subs ip, ip, #4 + ldr r1, [r6, #4] + addne r4, r4, #8 + beq .L8685 +.L9118: + mov r2, #0 +.L9119: + ldr r5, [sp, #28] + ands r3, r1, #255 + mov r0, r2, asl #1 + orr r3, r3, r5 + add r2, r2, #1 + strneh r3, [r0, r4] @ movhi + cmp ip, r2 + mov r1, r1, lsr #8 + bhi .L9119 + b .L8685 +.L9486: + rsb r4, r6, ip + rsb ip, r4, r8 + cmp ip, #0 + ble .L8685 + ldr lr, [sp, #8] + add r3, r6, r8 + cmp lr, r3 + bhi .L8891 + mov r3, r4, lsr #3 + ands lr, r4, #7 + sub r0, r0, r3, asl #5 + bne .L8893 + ldr r2, [sp, #92] + ldr r8, [sp, #68] +.L8895: + movs r7, r2, lsr #3 + beq .L8912 + mov r5, r8 + mov lr, r0 + mov r6, #0 +.L8914: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L8915 + ands r3, r4, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, ip + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r4 + strneh r3, [r5, #0] @ movhi +.L8915: + add r6, r6, #1 + cmp r6, r7 + sub lr, lr, #32 + add r5, r5, #16 + bne .L8914 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r8, r8, r7, asl #4 +.L8912: + ands lr, r2, #7 + beq .L8685 + ldr r0, [r0, #0] + mov ip, #0 +.L8934: + movs r3, r0, lsr #28 + ldr r5, [sp, #28] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r5 + add ip, ip, #1 + strneh r3, [r2, r8] @ movhi + cmp ip, lr + mov r0, r0, asl #4 + bne .L8934 + b .L8685 +.L9485: + ldr r5, [sp, #12] + rsb r4, r6, r5 + rsb r5, r4, r8 + cmp r5, #0 + ble .L8685 + add r3, r6, r8 + ldr r6, [sp, #8] + cmp r6, r3 + bhi .L8761 + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add r5, r0, r2 + bne .L8763 + ldr r7, [sp, #92] + ldr r6, [sp, #68] +.L8765: + movs r4, r7, lsr #3 + beq .L8782 + mov ip, r6 + mov r0, r5 + mov lr, #0 +.L8784: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L8785 + ands r3, r2, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + ldrne r2, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r2 + strneh r3, [ip, #14] @ movhi +.L8785: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #32 + add ip, ip, #16 + bne .L8784 + add r5, r5, r4, asl #5 + add r6, r6, r4, asl #4 +.L8782: + ands lr, r7, #7 + beq .L8685 + ldr r2, [r5, #0] + mov r0, #0 +.L8804: + ands r3, r2, #15 + ldr r4, [sp, #28] + orr r3, r1, r3 + mov ip, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [ip, r6] @ movhi + cmp r0, lr + mov r2, r2, lsr #4 + bne .L8804 + b .L8685 +.L9510: + mov r6, #0 +.L8707: + cmp r4, sl + movcc r3, #0 + movcs r3, #1 + cmp r8, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L9473 + b .L8685 +.L8708: + cmp r4, sl + cmpcc ip, r8 + bcs .L8685 +.L9473: + and r3, r4, #7 + mov r2, ip, asr #3 + mov r3, r3, asl #3 + mov r1, r4, asr #3 + add r3, r3, r2, asl #6 + ldr r0, [sp, #48] + add r3, r3, r1, asl #10 + ldr r1, [sp, #84] + add r5, r5, r0 + add r3, r3, r1 + and r0, ip, #7 + ldrb r2, [r3, r0] @ zero_extendqisi2 + ldr r3, [sp, #28] + cmp r2, #0 + add r6, r6, #1 + orr r2, r2, r3 + strneh r2, [r7, #0] @ movhi + add lr, lr, fp + cmp r9, r6 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + add r7, r7, #2 + bgt .L8708 + b .L8685 +.L8969: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L8685 + ldr r7, [sp, #4] + mov ip, #0 + add r2, r7, r6, asl #1 + b .L8999 +.L9494: + sub r0, r0, #32 + add r2, r2, #16 +.L8999: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L9000 + ands r3, r4, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [r2, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + movs r3, r4, lsr #28 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #0] @ movhi +.L9000: + add ip, ip, #1 + cmp lr, ip + bne .L9494 + b .L8685 +.L9394: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L8685 + ldr r5, [sp, #4] + ldr r3, .L9512+28 + add r2, r5, r6, asl #1 + add r0, r0, r3 + mov r1, #0 + b .L9438 +.L9495: + sub ip, ip, #64 + add r2, r2, #16 +.L9438: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L9439 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r2, #2] @ movhi + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r2, #0] @ movhi +.L9439: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L9448 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r2, #14] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r2, #12] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r2, #10] @ movhi + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r2, #8] @ movhi +.L9448: + add r1, r1, #1 + cmp lr, r1 + sub r0, r0, #64 + bne .L9495 + b .L8685 +.L8839: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L8685 + ldr r7, [sp, #4] + mov ip, #0 + add r2, r7, r6, asl #1 + b .L8869 +.L9496: + add r0, r0, #32 + add r2, r2, #16 +.L8869: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L8870 + ands r3, r4, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #0] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [r2, #2] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #4] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #6] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r2, #12] @ movhi + movs r3, r4, lsr #28 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r2, #14] @ movhi +.L8870: + add ip, ip, #1 + cmp lr, ip + bne .L9496 + b .L8685 +.L9174: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L8685 + ldr r1, [sp, #4] + ldr r3, .L9512+32 + add r2, r1, r6, asl #1 + add r0, r0, r3 + mov r1, #0 + b .L9218 +.L9497: + add ip, ip, #64 + add r2, r2, #16 +.L9218: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L9219 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r2, #0] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r2, #2] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r2, #4] @ movhi + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r2, #6] @ movhi +.L9219: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L9228 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r2, #8] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r2, #10] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r2, #12] @ movhi + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r2, #14] @ movhi +.L9228: + add r1, r1, #1 + cmp lr, r1 + add r0, r0, #64 + bne .L9497 + b .L8685 +.L9021: + mov r3, r1, lsr #3 + ands r2, r1, #7 + add r0, ip, r3, asl #6 + ldreq r1, [sp, #68] + beq .L9125 + cmp r2, #3 + rsb lr, r2, #8 + bhi .L9498 + subs r5, lr, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #68] + beq .L9138 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov ip, #0 +.L9139: + ands r3, r2, #255 + ldr r1, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r3, r1 + mov r1, ip, asl #1 + add ip, ip, #1 + strneh r3, [r1, r6] @ movhi + cmp ip, r5 + mov r2, r2, lsr #8 + bne .L9139 + ldr r7, [sp, #68] + add r3, r7, lr, asl #1 + sub r1, r3, #8 +.L9138: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9144 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, r3, ip + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r3, r2 + strneh r3, [r1, #6] @ movhi +.L9144: + add r1, r1, #8 +.L9130: + add r0, r0, #64 +.L9125: + movs lr, r4, lsr #3 + beq .L8685 + mov ip, #0 + b .L9154 +.L9499: + add r0, r0, #64 + add r1, r1, #16 +.L9154: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9155 + ands r3, r2, #255 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #6] @ movhi +.L9155: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9164 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r1, #10] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r1, #12] @ movhi + movs r3, r2, lsr #24 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r1, #14] @ movhi +.L9164: + add ip, ip, #1 + cmp lr, ip + bne .L9499 + b .L8685 +.L8891: + ands r2, r4, #7 + mov r3, r4, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r5, [sp, #68] + beq .L8940 + rsbs lr, r2, #8 + ldr r4, [r0, #0] + ldreq r5, [sp, #68] + beq .L8943 + mov r3, r2, asl #2 + mov r4, r4, asl r3 + mov r6, #0 +.L8944: + movs r3, r4, lsr #28 + ldr r7, [sp, #28] + ldrne r8, [sp, #68] + orr r3, r1, r3 + mov r5, r6, asl #1 + orr r3, r3, r7 + add r6, r6, #1 + strneh r3, [r5, r8] @ movhi + cmp lr, r6 + mov r4, r4, asl #4 + bne .L8944 + ldr r2, [sp, #68] + add r5, r2, lr, asl #1 +.L8943: + sub r0, r0, #32 +.L8940: + movs ip, ip, lsr #3 + beq .L8685 + mov r2, #0 + b .L8950 +.L9500: + sub r0, r0, #32 + add r5, r5, #16 +.L8950: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L8951 + ands r3, r4, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #14] @ movhi + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r5, #12] @ movhi + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r5, #10] @ movhi + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne lr, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r5, #8] @ movhi + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [r5, #6] @ movhi + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [r5, #4] @ movhi + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [r5, #2] @ movhi + movs r3, r4, lsr #28 + ldrne lr, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, lr + strneh r3, [r5, #0] @ movhi +.L8951: + add r2, r2, #1 + cmp r2, ip + bne .L9500 + b .L8685 +.L9241: + ands r0, r1, #7 + mov r3, r1, lsr #3 + sub r2, ip, r3, asl #6 + ldreq r0, [sp, #68] + beq .L9345 + cmp r0, #3 + rsb lr, r0, #8 + bhi .L9501 + subs r5, lr, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #68] + beq .L9358 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, #0 +.L9359: + movs r3, r1, lsr #24 + ldr r0, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r3, r0 + mov r0, ip, asl #1 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp r5, ip + mov r1, r1, asl #8 + bne .L9359 + ldr r7, [sp, #68] + add r3, r7, lr, asl #1 + sub r0, r3, #8 +.L9358: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L9364 + ands r3, r1, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, r3, ip + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r1, [sp, #28] + orrne r3, r3, r1 + strneh r3, [r0, #0] @ movhi +.L9364: + add r0, r0, #8 +.L9350: + sub r2, r2, #64 +.L9345: + movs lr, r4, lsr #3 + beq .L8685 + mov ip, #0 + b .L9374 +.L9502: + sub r2, r2, #64 + add r0, r0, #16 +.L9374: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L9375 + ands r3, r1, #255 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r0, #6] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r0, #4] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r0, #2] @ movhi + movs r3, r1, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r0, #0] @ movhi +.L9375: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L9384 + ands r3, r1, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r0, #14] @ movhi + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r3, r4 + strneh r3, [r0, #12] @ movhi + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r3, r5 + strneh r3, [r0, #10] @ movhi + movs r3, r1, lsr #24 + ldrne r6, [sp, #28] + orrne r3, r3, r6 + strneh r3, [r0, #8] @ movhi +.L9384: + add ip, ip, #1 + cmp ip, lr + bne .L9502 + b .L8685 +.L8761: + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add lr, r0, r2 + ldreq ip, [sp, #68] + beq .L8810 + rsbs r4, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #68] + beq .L8813 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov ip, #0 +.L8814: + ands r3, r0, #15 + ldr r6, [sp, #28] + ldrne r7, [sp, #68] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r2, r7] @ movhi + cmp ip, r4 + mov r0, r0, lsr #4 + bne .L8814 + ldr r8, [sp, #68] + add ip, r8, r4, asl #1 +.L8813: + add lr, lr, #32 +.L8810: + movs r4, r5, lsr #3 + beq .L8685 + mov r0, #0 + b .L8820 +.L9503: + add lr, lr, #32 + add ip, ip, #16 +.L8820: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L8821 + ands r3, r2, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [ip, #0] @ movhi + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [ip, #2] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [ip, #4] @ movhi + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #6] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r5 + strneh r3, [ip, #8] @ movhi + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r6 + strneh r3, [ip, #10] @ movhi + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r7 + strneh r3, [ip, #12] @ movhi + movs r3, r2, lsr #28 + ldrne r8, [sp, #28] + orrne r3, r1, r3 + orrne r3, r3, r8 + strneh r3, [ip, #14] @ movhi +.L8821: + add r0, r0, #1 + cmp r0, r4 + bne .L9503 + b .L8685 +.L9023: + ldr r1, [sp, #92] + rsb ip, r0, #8 + cmp r1, ip + blt .L9504 + cmp r0, #3 + bls .L9056 + cmp ip, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #68] + beq .L9060 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r0, #0 +.L9061: + ands r3, r1, #255 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + mov r2, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r2, lr] @ movhi + cmp ip, r0 + mov r1, r1, lsr #8 + bne .L9061 + ldr r0, [sp, #68] + add r4, r0, ip, asl #1 +.L9060: + ldr r1, [sp, #92] + add r6, r6, #64 + rsb r5, ip, r1 + b .L9025 +.L8893: + ldr r2, [sp, #92] + rsb r6, lr, #8 + cmp r2, r6 + blt .L9505 + cmp r6, #0 + ldr r2, [r0, #0] + ldreq r8, [sp, #68] + beq .L8906 + mov r3, lr, asl #2 + mov lr, r2, asl r3 + mov r5, #0 +.L8907: + movs r3, lr, lsr #28 + ldr r7, [sp, #28] + ldrne r8, [sp, #68] + orr r3, r1, r3 + mov r4, r5, asl #1 + orr r3, r3, r7 + add r5, r5, #1 + strneh r3, [r4, r8] @ movhi + cmp r6, r5 + mov lr, lr, asl #4 + bne .L8907 + ldr ip, [sp, #68] + add r8, ip, r6, asl #1 +.L8906: + ldr lr, [sp, #92] + sub r0, r0, #32 + rsb r2, r6, lr + b .L8895 +.L8763: + ldr r7, [sp, #92] + rsb lr, r3, #8 + cmp r7, lr + blt .L9506 + cmp lr, #0 + ldr r2, [r5, #0] + ldreq r6, [sp, #68] + beq .L8776 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov ip, #0 +.L8777: + ands r3, r2, #15 + ldr r4, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r1, r3 + mov r0, ip, asl #1 + orr r3, r3, r4 + add ip, ip, #1 + strneh r3, [r0, r6] @ movhi + cmp lr, ip + mov r2, r2, lsr #4 + bne .L8777 + ldr r7, [sp, #68] + add r6, r7, lr, asl #1 +.L8776: + ldr r8, [sp, #92] + add r5, r5, #32 + rsb r7, lr, r8 + b .L8765 +.L9243: + ldr r1, [sp, #92] + rsb ip, r0, #8 + cmp r1, ip + blt .L9507 + cmp r0, #3 + bls .L9276 + cmp ip, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #68] + beq .L9280 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L9281: + movs r3, r2, lsr #24 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + mov r1, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp ip, r0 + mov r2, r2, asl #8 + bne .L9281 + ldr r0, [sp, #68] + add r4, r0, ip, asl #1 +.L9280: + ldr r1, [sp, #92] + sub r6, r6, #64 + rsb r5, ip, r1 + b .L9245 +.L9507: + cmp r1, #0 + ble .L8685 + cmp r0, #3 + bls .L9249 + mov r3, r0, asl #3 + ldr r2, [r6, #0] + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L9252: + movs r3, r2, lsr #24 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + ldr r6, [sp, #92] + mov r1, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [r1, r5] @ movhi + cmp r6, r0 + mov r2, r2, asl #8 + bne .L9252 + b .L8685 +.L9506: + cmp r7, #0 + ble .L8685 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov ip, #0 +.L8770: + ands r3, r0, #15 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + orr r3, r1, r3 + mov r2, ip, asl #1 + orr r3, r3, r8 + strneh r3, [r2, lr] @ movhi + ldr r2, [sp, #92] + add ip, ip, #1 + cmp r2, ip + mov r0, r0, lsr #4 + bne .L8770 + b .L8685 +.L9505: + cmp r2, #0 + ble .L8685 + ldr r2, [r0, #0] + mov r3, lr, asl #2 + mov r0, r2, asl r3 + mov ip, #0 +.L8900: + movs r3, r0, lsr #28 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + orr r3, r1, r3 + ldr r6, [sp, #92] + mov r2, ip, asl #1 + orr r3, r3, r4 + add ip, ip, #1 + strneh r3, [r2, r5] @ movhi + cmp r6, ip + mov r0, r0, asl #4 + bne .L8900 + b .L8685 +.L9501: + cmp lr, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #68] + beq .L9350 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov ip, #0 +.L9351: + movs r3, r1, lsr #24 + ldr r6, [sp, #28] + ldrne r7, [sp, #68] + mov r0, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r0, r7] @ movhi + cmp ip, lr + mov r1, r1, asl #8 + bne .L9351 + ldr r8, [sp, #68] + sub r2, r2, #64 + add r0, r8, lr, asl #1 + b .L9345 +.L9498: + cmp lr, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #68] + beq .L9130 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov ip, #0 +.L9131: + ands r3, r2, #255 + ldr r6, [sp, #28] + ldrne r7, [sp, #68] + mov r1, ip, asl #1 + orr r3, r3, r6 + add ip, ip, #1 + strneh r3, [r1, r7] @ movhi + cmp ip, lr + mov r2, r2, lsr #8 + bne .L9131 + ldr r8, [sp, #68] + add r0, r0, #64 + add r1, r8, lr, asl #1 + b .L9125 +.L9504: + cmp r1, #0 + ble .L8685 + cmp r0, #3 + bls .L9029 + mov r3, r0, asl #3 + ldr r2, [r6, #4] + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r0, #0 +.L9032: + ands r3, r1, #255 + ldr r2, [sp, #28] + ldrne r4, [sp, #68] + ldr r5, [sp, #92] + orr r3, r3, r2 + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r5, r0 + mov r1, r1, lsr #8 + bne .L9032 + b .L8685 +.L9511: + mov r6, #0 + b .L8743 +.L9276: + subs lr, ip, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #68] + beq .L9288 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r0, #0 +.L9289: + movs r3, r2, lsr #24 + ldr r1, [sp, #28] + ldrne r4, [sp, #68] + orr r3, r3, r1 + mov r1, r0, asl #1 + add r0, r0, #1 + strneh r3, [r1, r4] @ movhi + cmp lr, r0 + mov r2, r2, asl #8 + bne .L9289 + ldr r5, [sp, #68] + add r3, r5, ip, asl #1 + sub r1, r3, #8 +.L9288: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L9294 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r1, #2] @ movhi + movs r3, r2, lsr #24 + ldrne r0, [sp, #28] + orrne r3, r3, r0 + strneh r3, [r1, #0] @ movhi +.L9294: + add r4, r1, #8 + b .L9280 +.L9056: + subs lr, ip, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #68] + beq .L9068 + mov r3, r0, asl #3 + mov r1, r2, lsr r3 + mov r0, #0 +.L9069: + ands r3, r1, #255 + ldr r2, [sp, #28] + ldrne r4, [sp, #68] + orr r3, r3, r2 + mov r2, r0, asl #1 + add r0, r0, #1 + strneh r3, [r2, r4] @ movhi + cmp r0, lr + mov r1, r1, lsr #8 + bne .L9069 + ldr r5, [sp, #68] + add r3, r5, ip, asl #1 + sub r1, r3, #8 +.L9068: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L9074 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r3, r7 + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r3, r8 + strneh r3, [r1, #2] @ movhi + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, r3, lr + strneh r3, [r1, #4] @ movhi + movs r3, r2, lsr #24 + ldrne r0, [sp, #28] + orrne r3, r3, r0 + strneh r3, [r1, #6] @ movhi +.L9074: + add r4, r1, #8 + b .L9060 +.L9509: + ldr r5, [sp, #20] + b .L9474 +.L9508: + mov ip, fp + b .L9472 +.L9249: + ldr r7, [sp, #92] + mov r3, r0, asl #3 + ldr r1, [r6, #4] + add r2, r7, r0 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L9256 + cmp r7, #0 + movne r0, #0 + beq .L8685 +.L9272: + movs r3, r1, lsr #24 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + ldr r7, [sp, #92] + mov r2, r0, asl #1 + orr r3, r3, r5 + add r0, r0, #1 + strneh r3, [r2, r6] @ movhi + cmp r7, r0 + mov r1, r1, asl #8 + bne .L9272 + b .L8685 +.L9029: + ldr r7, [sp, #92] + ldr r3, [r6, #0] + add r2, r7, r0 + cmp r2, #4 + mov r1, r0, asl #3 + mov r2, r3, lsr r1 + bhi .L9036 + cmp r7, #0 + movne r0, #0 + beq .L8685 +.L9052: + ands r3, r2, #255 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + ldr r7, [sp, #92] + mov r1, r0, asl #1 + orr r3, r3, r5 + add r0, r0, #1 + strneh r3, [r1, r6] @ movhi + cmp r7, r0 + mov r2, r2, lsr #8 + bne .L9052 + b .L8685 +.L9256: + rsbs ip, r0, #4 + ldreq lr, [sp, #68] + beq .L9261 + mov r0, #0 +.L9262: + movs r3, r1, lsr #24 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + mov r2, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r2, lr] @ movhi + cmp r0, ip + mov r1, r1, asl #8 + bne .L9262 + ldr r0, [sp, #68] + add lr, r0, ip, asl #1 +.L9261: + ldr r1, [sp, #92] + ldr r2, [r6, #0] + subs ip, r1, ip + beq .L8685 + mov r0, #0 +.L9268: + ldr r4, [sp, #28] + movs r3, r2, lsr #24 + mov r1, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L9268 + b .L8685 +.L9036: + rsbs ip, r0, #4 + ldreq lr, [sp, #68] + beq .L9041 + mov r0, #0 +.L9042: + ands r3, r2, #255 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + mov r1, r0, asl #1 + orr r3, r3, r8 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L9042 + ldr r0, [sp, #68] + add lr, r0, ip, asl #1 +.L9041: + ldr r1, [sp, #92] + ldr r2, [r6, #4] + subs ip, r1, ip + beq .L8685 + mov r0, #0 +.L9048: + ldr r4, [sp, #28] + ands r3, r2, #255 + mov r1, r0, asl #1 + orr r3, r3, r4 + add r0, r0, #1 + strneh r3, [r1, lr] @ movhi + cmp r0, ip + mov r2, r2, lsr #8 + bne .L9048 + b .L8685 + .size render_scanline_obj_color16_2D, .-render_scanline_obj_color16_2D + .align 2 + .global render_scanline_obj_color32_1D + .type render_scanline_obj_color32_1D, %function +render_scanline_obj_color32_1D: + @ args = 0, pretend = 0, frame = 112 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L10356 + sub sp, sp, #112 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #32] + ldr r5, [sp, #32] + ldrh r4, [ip, #80] + ldr ip, .L10356+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #36] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L10356+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #40] + str r1, [sp, #8] + str r2, [sp, #4] + str r3, [sp, #0] + str lr, [sp, #24] + beq .L10302 + mov r8, #0 + add r6, r3, r1, asl #2 + rsb r7, r1, r2 + str r6, [sp, #84] + str r7, [sp, #108] + str r8, [sp, #28] + mov ip, r8 +.L9517: + ldr lr, [sp, #40] + ldr r0, .L10356+12 + ldrb r3, [ip, lr] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh r4, [r3, r0] + add r3, r3, r0 + ldrh r1, [r3, #2] + mov r5, r4, lsr #12 + and r2, r5, #12 + orr r0, r2, r1, lsr #14 + and ip, r4, #255 + mov r2, r1, asl #23 + cmp ip, #160 + ldrh lr, [r3, #4] + mov r6, r2, asr #23 + ldr r3, .L10356+16 + ldr r2, .L10356+20 + subgt ip, ip, #256 + tst r4, #256 + ldr r7, [r2, r0, asl #2] + ldr sl, [r3, r0, asl #2] + beq .L9520 + tst r4, #8192 + beq .L9522 + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L10356+12 + and r3, r3, #992 + add r3, r3, r4 + add r2, r7, r7, lsr #31 + ldrh r5, [r3, #30] + mov r4, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #8] + movne r0, r4, asl #1 + str r5, [sp, #12] + mov r5, r1, asr #1 + strne r0, [sp, #56] + moveq r9, r7 + streq r4, [sp, #56] + moveq r0, r5 + movne r9, r7, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L9527 + rsb r2, r6, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L9529 + ldr r3, [sp, #56] + ldr r6, [sp, #8] + rsb r3, r2, r3 + str r3, [sp, #56] +.L9527: + ldr r2, [sp, #4] + add r3, r6, r9 + cmp r3, r2 + blt .L9531 + rsb r9, r6, r2 + cmp r9, #0 + ble .L9529 +.L9531: + mov r3, r8, asl #16 + ldr r8, [sp, #12] + mov r2, r1, asl #16 + mov r2, r2, asr #16 + mov r1, r8, asl #16 + add r0, ip, r0 + str r2, [sp, #48] + mov ip, r1, asr #16 + ldr r2, [sp, #32] + ldr r1, [sp, #0] + mov r4, r4, asl #8 + mov r3, r3, asr #16 + mov r5, r5, asl #8 + cmp fp, #0 + str r4, [sp, #92] + str r3, [sp, #44] + str r5, [sp, #52] + add r8, r1, r6, asl #2 + rsb r4, r0, r2 + bne .L9533 + mov r3, r5 + mla r3, r4, ip, r3 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L9529 + cmp r7, #0 + add r3, r7, #7 + movge r3, r7 + mov r2, lr, asl #22 + mov r3, r3, asr #3 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L10356+24 + add r0, r0, ip, asl #2 + cmp r9, #0 + add lr, r3, r0, asl #3 + ble .L9529 + ldr r3, [sp, #48] + ldr r2, [sp, #56] + mul r3, r4, r3 + ldr r4, [sp, #44] + ldr r5, [sp, #92] + mul r2, r4, r2 + rsb r3, r2, r3 + add r0, r5, r3 + mov r4, r0, asr #8 + cmp r4, r7 + movcs ip, fp + bcs .L9539 + b .L10352 +.L9540: + cmp r4, r7 + bcc .L10316 +.L9539: + ldr r6, [sp, #44] + add ip, ip, #1 + add r0, r0, r6 + cmp r9, ip + mov r4, r0, asr #8 + add r8, r8, #4 + bne .L9540 +.L9529: + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + beq .L10302 +.L10334: + ldr ip, [sp, #28] + b .L9517 +.L9520: + ldr r0, [sp, #32] + tst r1, #8192 + rsb ip, ip, r0 + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r1, asl #19 + and r3, r5, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L9529 + .p2align 2 +.L9601: + .word .L9597 + .word .L9598 + .word .L9599 + .word .L9600 +.L9597: + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r5, r3, r2 + ldr r2, [sp, #8] + and r1, ip, #7 + ldr r3, .L10356+24 + add r1, r1, r0, asl #3 + cmp r6, r2 + mov r2, lr, lsr #8 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L10329 + ldr ip, [sp, #4] + add r3, r6, r7 + cmp ip, r3 + bhi .L9683 + rsb r7, r6, ip + cmp r7, #0 + ble .L9529 + ldr lr, [sp, #0] + movs r8, r7, lsr #3 + add r2, lr, r6, asl #2 + beq .L9686 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L9688: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L9689 + ands r3, r4, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] +.L9689: + add ip, ip, #1 + cmp ip, r8 + add lr, lr, #32 + add r5, r5, #32 + bne .L9688 + mov r3, r8, asl #5 + add r0, r0, r3 + add r2, r2, r3 +.L9686: + ands lr, r7, #7 + beq .L9529 + ldr r0, [r0, #0] + mov ip, #0 +.L9708: + ldr r5, [sp, #24] + ands r3, r0, #15 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [r2, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, lsr #4 + bne .L9708 + b .L9529 +.L9598: + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, r5, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + ldr r8, [sp, #8] + add r0, r0, r3, asr #3 + and r2, ip, #7 + ldr r3, .L10356+24 + add r2, r2, r0, asl #3 + mov r1, lr, lsr #8 + cmp r6, r8 + add r0, r3, r2, asl #2 + and r1, r1, #240 + blt .L10330 + ldr ip, [sp, #4] + add r3, r6, r7 + cmp ip, r3 + bhi .L9813 + rsb r8, r6, ip + cmp r8, #0 + ble .L9529 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r2, lr, r6, asl #2 + beq .L9816 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L9818: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L9819 + ands r3, r4, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L9819: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #32 + add r5, r5, #32 + bne .L9818 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #5 +.L9816: + ands lr, r8, #7 + beq .L9529 + ldr r0, [r0, #0] + mov ip, #0 +.L9838: + ldr r5, [sp, #24] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [r2, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, asl #4 + bne .L9838 + b .L9529 +.L9599: + cmp r7, #0 + add r3, r7, #7 + mov r1, lr, asl #22 + movge r3, r7 + mov r2, ip, lsr #3 + mov lr, r3, asr #3 + mov r1, r1, lsr #22 + mov r2, r2, asl #1 + mla r0, r2, lr, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr r8, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L10356+24 + cmp r6, r8 + add r1, r0, r3 + blt .L10331 + ldr r8, [sp, #4] + add r3, r6, r7 + cmp r8, r3 + bhi .L10018 + rsb r8, r6, r8 + cmp r8, #0 + ble .L9529 + ldr ip, [sp, #0] + movs r7, r8, lsr #3 + add r2, ip, r6, asl #2 + beq .L10021 + ldr r3, .L10356+32 + mov r5, r2 + add r0, r0, r3 + mov lr, r1 + mov ip, #0 +.L10023: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10024 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #8] + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r5, #12] +.L10024: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L10033 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r5, #28] +.L10033: + add ip, ip, #1 + cmp r7, ip + add lr, lr, #64 + add r5, r5, #32 + add r0, r0, #64 + bne .L10023 + add r1, r1, r7, asl #6 + add r2, r2, r7, asl #5 +.L10021: + ands ip, r8, #7 + beq .L9529 + cmp ip, #3 + ldrls r0, [r1, #0] + bls .L10056 + ldr r0, [r1, #0] + cmp r0, #0 + beq .L10046 + ands r3, r0, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r2, #0] + mov r3, r0, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r2, #4] + mov r3, r0, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r2, #8] + movs r3, r0, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r2, #12] +.L10046: + subs ip, ip, #4 + ldr r0, [r1, #4] + addne r2, r2, #16 + beq .L9529 +.L10056: + mov r1, #0 +.L10057: + ldr lr, [sp, #24] + ands r3, r0, #255 + orr r3, lr, r3 + strne r3, [r2, r1, asl #2] + add r1, r1, #1 + cmp ip, r1 + mov r0, r0, lsr #8 + bhi .L10057 + b .L9529 +.L9600: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r1, ip, lsr #3 + mov r5, r2, asr #3 + mov r3, r3, asr #3 + mla r0, r5, r1, r3 + mov r2, lr, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + and r3, ip, #7 + add r3, r3, r2, asl #2 + ldr ip, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L10356+24 + cmp r6, ip + add r1, r0, r3 + blt .L10332 + add r3, r6, r7 + ldr r7, [sp, #4] + cmp r3, r7 + bcc .L10238 + rsb r8, r6, r7 + cmp r8, #0 + ble .L9529 + ldr ip, [sp, #0] + movs r7, r8, lsr #3 + add r6, ip, r6, asl #2 + beq .L10241 + ldr r3, .L10356+28 + mov r5, r6 + add r0, r0, r3 + mov lr, r1 + mov ip, #0 +.L10243: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L10244 + ands r3, r4, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r5, #0] +.L10244: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10253 + ands r3, r4, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r5, #20] + movs r3, r4, lsr #24 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r5, #16] +.L10253: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #64 + add r5, r5, #32 + sub r0, r0, #64 + bne .L10243 + rsb r3, r7, r7, asl #26 + add r1, r1, r3, asl #6 + add r6, r6, r7, asl #5 +.L10241: + ands r0, r8, #7 + beq .L9529 + cmp r0, #3 + ldrls r2, [r1, #4] + bls .L10276 + ldr r2, [r1, #4] + cmp r2, #0 + beq .L10266 + ands r3, r2, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r6, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r6, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r6, #4] + movs r3, r2, lsr #24 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r6, #0] +.L10266: + subs r0, r0, #4 + ldr r2, [r1, #0] + addne r6, r6, #16 + beq .L9529 +.L10276: + mov r1, #0 +.L10277: + ldr lr, [sp, #24] + movs r3, r2, lsr #24 + orr r3, lr, r3 + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L10277 + b .L9529 +.L9522: + mov r3, r1, lsr #4 + ldr r2, .L10356+12 + and r3, r3, #992 + add r3, r3, r2 + tst r4, #512 + ldrh r4, [r3, #30] + add r2, r7, r7, lsr #31 + add r1, sl, sl, lsr #31 + str r4, [sp, #20] + mov r4, r2, asr #1 + ldr r2, [sp, #8] + mov r5, r1, asr #1 + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r7 + moveq r9, r4 + moveq r0, r5 + movne fp, r7, asl #1 + movne r9, r4, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + str r3, [sp, #16] + bge .L9560 + rsb r2, r6, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L9529 + ldr r6, [sp, #8] + rsb r9, r2, r9 +.L9560: + ldr r2, [sp, #4] + add r3, r6, fp + cmp r3, r2 + blt .L9563 + rsb fp, r6, r2 + cmp fp, #0 + ble .L9529 +.L9563: + mov r3, r8, asl #16 + ldr r8, [sp, #20] + add ip, ip, r0 + mov r2, r1, asl #16 + ldr r0, [sp, #16] + mov r1, r8, asl #16 + mov r2, r2, asr #16 + mov r1, r1, asr #16 + cmp r0, #0 + str r2, [sp, #68] + mov r0, lr, lsr #8 + str r1, [sp, #76] + ldr r2, [sp, #32] + ldr r1, [sp, #0] + mov r4, r4, asl #8 + mov r3, r3, asr #16 + and r0, r0, #240 + str r4, [sp, #88] + str r3, [sp, #64] + mov r5, r5, asl #8 + add r8, r1, r6, asl #2 + rsb r4, ip, r2 + str r0, [sp, #104] + bne .L9565 + ldr r3, [sp, #76] + mla r3, r4, r3, r5 + mov r0, r3, asr #8 + cmp r0, sl + bcs .L9529 + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r1, r0, lsr #3 + mov r3, r3, asr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L10356+24 + add r0, r0, ip, asl #3 + cmp fp, #0 + add r1, r3, r0, asl #2 + ble .L9529 + ldr r3, [sp, #68] + ldr r2, [sp, #64] + mul r3, r4, r3 + mul r2, r9, r2 + ldr r4, [sp, #88] + rsb r3, r2, r3 + add r0, r4, r3 + mov r4, r0, asr #8 + cmp r4, r7 + ldrcs r5, [sp, #16] + bcs .L9571 + b .L10353 +.L9572: + cmp r4, r7 + bcc .L10318 +.L9571: + ldr r6, [sp, #64] + add r5, r5, #1 + add r0, r0, r6 + cmp fp, r5 + mov r4, r0, asr #8 + add r8, r8, #4 + bne .L9572 + ldr r0, [sp, #28] + ldr r1, [sp, #36] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #28] + bne .L10334 +.L10302: + add sp, sp, #112 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L9533: + cmp r7, #0 + add r1, r7, #7 + mov r2, lr, asl #22 + movge r1, r7 + ldr r3, .L10356+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp r9, #0 + str r2, [sp, #100] + str r1, [sp, #60] + ble .L9529 + mov r3, fp, asl #16 + mov fp, r3, asr #16 + ldr r6, [sp, #44] + ldr r3, [sp, #48] + ldr r0, [sp, #56] + ldr r1, [sp, #56] + mul r0, r6, r0 + mul r3, r4, r3 + mul r2, r4, ip + mul r1, fp, r1 + rsb r3, r0, r3 + ldr ip, [sp, #92] + ldr r0, [sp, #52] + rsb r2, r1, r2 + add r5, ip, r3 + add lr, r0, r2 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + cmp ip, r7 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L9549 + b .L10354 +.L9550: + cmp ip, r7 + cmpcc r4, sl + bcc .L9551 +.L9549: + ldr r1, [sp, #44] + add r6, r6, #1 + add r5, r5, r1 + add lr, lr, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + add r8, r8, #4 + bne .L9550 + b .L9529 +.L9565: + cmp r7, #0 + add r1, r7, #7 + mov r2, lr, asl #22 + movge r1, r7 + ldr r3, .L10356+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp fp, #0 + str r2, [sp, #96] + str r1, [sp, #80] + ble .L9529 + ldr r6, [sp, #16] + ldr r2, [sp, #76] + mov r3, r6, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #72] + ldr r1, [sp, #72] + ldr r3, [sp, #68] + ldr r0, [sp, #64] + mul r2, r4, r2 + mul r3, r4, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr ip, [sp, #88] + rsb r2, r1, r2 + rsb r3, r0, r3 + add lr, ip, r3 + add r5, r5, r2 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + cmp r4, r7 + cmpcc r2, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L9584 + b .L10355 +.L9585: + cmp r4, r7 + cmpcc r2, sl + bcc .L9587 +.L9584: + ldr r0, [sp, #64] + ldr r1, [sp, #72] + add r6, r6, #1 + add lr, lr, r0 + add r5, r5, r1 + cmp fp, r6 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + add r8, r8, #4 + bne .L9585 + b .L9529 +.L10337: + ldr r3, [sp, #96] + and r0, r2, #7 + add r0, r3, r0, asl #2 + and r1, r2, #7 + mov r3, r2, asr #3 + ldr r2, [sp, #80] + mov ip, r4, asr #1 + mul r2, r3, r2 + and r9, ip, #3 + ldr ip, [sp, #96] + mov r3, r4, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, r4, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst r4, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, r9] @ zero_extendqisi2 + ldr r4, [sp, #24] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr ip, [sp, #104] + ldr r2, [sp, #72] + orr r3, r0, r4 + ldr r1, [sp, #64] + cmp r0, #0 + add r6, r6, #1 + orr r3, ip, r3 + strne r3, [r8, #0] + add lr, lr, r1 + add r5, r5, r2 + cmp fp, r6 + mov r4, lr, asr #8 + mov r2, r5, asr #8 + add r8, r8, #4 + ble .L9529 +.L9587: + cmp r2, sl + cmpcc r4, r7 + bcc .L10337 + b .L9529 +.L9574: + cmp r4, r7 + bcs .L9529 +.L10318: + mov r3, r4, asr #1 + and sl, r3, #3 + mov r3, r4, asr #3 + mov r3, r3, asl #5 + mov r2, r4, asr #1 + tst r4, #1 + add ip, r3, r1 + and r6, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r6] @ zero_extendqisi2 + ldrneb r3, [ip, sl] @ zero_extendqisi2 + ldr lr, [sp, #24] + movne r2, r3, lsr #4 + andeq r2, r3, #15 + cmp r2, #0 + orr r3, r2, lr + ldr r2, [sp, #104] + ldr ip, [sp, #64] + add r5, r5, #1 + orr r3, r2, r3 + strne r3, [r8, #0] + add r0, r0, ip + cmp fp, r5 + mov r4, r0, asr #8 + add r8, r8, #4 + bgt .L9574 + b .L9529 +.L9542: + cmp r4, r7 + bcs .L9529 +.L10316: + ldr r1, [sp, #44] + mov r3, r4, asr #3 + add r0, r0, r1 + add r3, lr, r3, asl #6 + and r1, r4, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #24] + cmp r2, #0 + add ip, ip, #1 + orr r3, r5, r2 + strne r3, [r8, #0] + cmp r9, ip + mov r4, r0, asr #8 + add r8, r8, #4 + bgt .L9542 + b .L9529 +.L10357: + .align 2 +.L10356: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L10332: + rsb r0, r6, ip + rsb r4, r0, r7 + cmp r4, #0 + ble .L9529 + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bhi .L10085 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r6, r1, r3, asl #6 + bne .L10087 + ldr r5, [sp, #108] + ldr r4, [sp, #84] +.L10089: + movs lr, r5, lsr #3 + beq .L10147 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L10149: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10150 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #0] +.L10150: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L10159 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #28] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #24] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #20] + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #16] +.L10159: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #32 + bne .L10149 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #5 +.L10147: + ands r0, r5, #7 + beq .L9529 + cmp r0, #3 + ldrls r2, [r6, #4] + bls .L10182 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L10172 + ands r3, r2, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #24] + orrne r3, r1, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r4, #0] +.L10172: + subs r0, r0, #4 + ldr r2, [r6, #0] + addne r4, r4, #16 + beq .L9529 +.L10182: + mov r1, #0 +.L10183: + ldr r5, [sp, #24] + movs r3, r2, lsr #24 + orr r3, r5, r3 + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L10183 + b .L9529 +.L10331: + rsb r0, r6, r8 + rsb lr, r0, r7 + cmp lr, #0 + ble .L9529 + ldr ip, [sp, #4] + add r3, r6, r7 + cmp ip, r3 + bhi .L9865 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add r6, r1, r3, asl #6 + bne .L9867 + ldr r5, [sp, #108] + ldr r4, [sp, #84] +.L9869: + movs lr, r5, lsr #3 + beq .L9927 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L9929: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9930 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #12] +.L9930: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9939 + ands r3, r2, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #28] +.L9939: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + add r1, r1, #32 + bne .L9929 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #5 +.L9927: + ands r0, r5, #7 + beq .L9529 + cmp r0, #3 + ldrls r1, [r6, #0] + bls .L9962 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L9952 + ands r3, r2, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #24] + orrne r3, r1, r3 + strne r3, [r4, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r4, #12] +.L9952: + subs r0, r0, #4 + ldr r1, [r6, #4] + addne r4, r4, #16 + beq .L9529 +.L9962: + mov r2, #0 +.L9963: + ldr r5, [sp, #24] + ands r3, r1, #255 + orr r3, r5, r3 + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bhi .L9963 + b .L9529 +.L10330: + rsb r4, r6, r8 + rsb ip, r4, r7 + cmp ip, #0 + ble .L9529 + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bhi .L9735 + mov r3, r4, lsr #3 + ands lr, r4, #7 + sub r0, r0, r3, asl #5 + bne .L9737 + ldr r2, [sp, #108] + ldr ip, [sp, #84] +.L9739: + movs r7, r2, lsr #3 + beq .L9756 + mov r5, ip + mov lr, r0 + mov r6, #0 +.L9758: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L9759 + ands r3, r4, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L9759: + add r6, r6, #1 + cmp r6, r7 + sub lr, lr, #32 + add r5, r5, #32 + bne .L9758 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add ip, ip, r7, asl #5 +.L9756: + ands lr, r2, #7 + beq .L9529 + ldr r0, [r0, #0] + mov r2, #0 +.L9778: + ldr r5, [sp, #24] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r0, r0, asl #4 + bne .L9778 + b .L9529 +.L10329: + ldr r3, [sp, #8] + rsb r4, r6, r3 + rsb r5, r4, r7 + cmp r5, #0 + ble .L9529 + add r3, r6, r7 + ldr r6, [sp, #4] + cmp r6, r3 + bhi .L9605 + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add r5, r0, r2 + bne .L9607 + ldr r7, [sp, #108] + ldr r6, [sp, #84] +.L9609: + movs r4, r7, lsr #3 + beq .L9626 + mov ip, r6 + mov r0, r5 + mov lr, #0 +.L9628: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9629 + ands r3, r2, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #24] + movs r3, r2, lsr #28 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + orrne r3, r1, r3 + strne r3, [ip, #28] +.L9629: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #32 + add ip, ip, #32 + bne .L9628 + mov r3, r4, asl #5 + add r5, r5, r3 + add r6, r6, r3 +.L9626: + ands ip, r7, #7 + beq .L9529 + ldr r2, [r5, #0] + mov r0, #0 +.L9648: + ldr r4, [sp, #24] + ands r3, r2, #15 + orr r3, r4, r3 + orr r3, r1, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp r0, ip + mov r2, r2, lsr #4 + bne .L9648 + b .L9529 +.L10354: + mov r6, #0 +.L9551: + cmp r4, sl + movcc r3, #0 + movcs r3, #1 + cmp r7, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L10317 + b .L9529 +.L9552: + cmp r4, sl + cmpcc ip, r7 + bcs .L9529 +.L10317: + ldr r2, [sp, #44] + and r3, r4, #7 + add r5, r5, r2 + ldr r0, [sp, #100] + mov r2, ip, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + add r3, r3, r0 + ldr r0, [sp, #60] + mov r2, r4, asr #3 + mla r0, r2, r0, r3 + and r1, ip, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + ldr r1, [sp, #24] + cmp r3, #0 + add r6, r6, #1 + orr r3, r1, r3 + strne r3, [r8, #0] + add lr, lr, fp + cmp r9, r6 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + add r8, r8, #4 + bgt .L9552 + b .L9529 +.L9813: + cmp r5, #0 + beq .L9529 + ldr r7, [sp, #0] + mov ip, #0 + add r2, r7, r6, asl #2 + b .L9843 +.L10338: + sub r0, r0, #32 + add r2, r2, #32 +.L9843: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L9844 + ands r3, r4, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r2, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #4] + movs r3, r4, lsr #28 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #0] +.L9844: + add ip, ip, #1 + cmp r5, ip + bne .L10338 + b .L9529 +.L10238: + cmp r5, #0 + beq .L9529 + ldr r3, [sp, #0] + mov ip, #0 + add r2, r3, r6, asl #2 + ldr r3, .L10356+28 + add r0, r0, r3 + b .L10282 +.L10339: + sub r1, r1, #64 + add r2, r2, #32 +.L10282: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L10283 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r2, #4] + movs r3, r4, lsr #24 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r2, #0] +.L10283: + ldr r4, [r1, #0] + cmp r4, #0 + beq .L10292 + ands r3, r4, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r2, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r2, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r2, #20] + movs r3, r4, lsr #24 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r2, #16] +.L10292: + add ip, ip, #1 + cmp r5, ip + sub r0, r0, #64 + bne .L10339 + b .L9529 +.L9683: + cmp r5, #0 + beq .L9529 + ldr r7, [sp, #0] + mov ip, #0 + add r2, r7, r6, asl #2 + b .L9713 +.L10340: + add r0, r0, #32 + add r2, r2, #32 +.L9713: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L9714 + ands r3, r4, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r2, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #24] + movs r3, r4, lsr #28 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #28] +.L9714: + add ip, ip, #1 + cmp r5, ip + bne .L10340 + b .L9529 +.L10018: + cmp lr, #0 + beq .L9529 + ldr r3, [sp, #0] + mov ip, #0 + add r2, r3, r6, asl #2 + ldr r3, .L10356+32 + add r0, r0, r3 + b .L10062 +.L10341: + add r1, r1, #64 + add r2, r2, #32 +.L10062: + ldr r4, [r1, #0] + cmp r4, #0 + beq .L10063 + ands r3, r4, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r2, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r2, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r2, #8] + movs r3, r4, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r2, #12] +.L10063: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L10072 + ands r3, r4, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r2, #24] + movs r3, r4, lsr #24 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r2, #28] +.L10072: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + bne .L10341 + b .L9529 +.L9865: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r0, r1, r3, asl #6 + ldreq r1, [sp, #84] + beq .L9969 + cmp r2, #3 + rsb ip, r2, #8 + bhi .L10342 + subs r4, ip, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #84] + beq .L9982 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov r1, #0 +.L9983: + ands r3, r2, #255 + ldr r5, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r5, r3 + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r1, r4 + mov r2, r2, lsr #8 + bne .L9983 + ldr r7, [sp, #84] + add r3, r7, ip, asl #2 + sub r1, r3, #16 +.L9982: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L9988 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r1, #12] +.L9988: + add r1, r1, #16 +.L9974: + add r0, r0, #64 +.L9969: + movs lr, lr, lsr #3 + beq .L9529 + mov ip, #0 + b .L9998 +.L10343: + add r0, r0, #64 + add r1, r1, #32 +.L9998: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L9999 + ands r3, r2, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r1, #12] +.L9999: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10008 + ands r3, r2, #255 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r1, #28] +.L10008: + add ip, ip, #1 + cmp lr, ip + bne .L10343 + b .L9529 +.L9735: + ands r2, r4, #7 + mov r3, r4, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r5, [sp, #84] + beq .L9784 + rsbs r5, r2, #8 + ldr lr, [r0, #0] + ldreq r5, [sp, #84] + beq .L9787 + mov r3, r2, asl #2 + mov r4, lr, asl r3 + mov lr, #0 +.L9788: + ldr r6, [sp, #24] + movs r3, r4, lsr #28 + ldrne r7, [sp, #84] + orr r3, r6, r3 + orr r3, r1, r3 + strne r3, [r7, lr, asl #2] + add lr, lr, #1 + cmp r5, lr + mov r4, r4, asl #4 + bne .L9788 + ldr r8, [sp, #84] + add r5, r8, r5, asl #2 +.L9787: + sub r0, r0, #32 +.L9784: + movs ip, ip, lsr #3 + beq .L9529 + mov r2, #0 + b .L9794 +.L10344: + sub r0, r0, #32 + add r5, r5, #32 +.L9794: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L9795 + ands r3, r4, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L9795: + add r2, r2, #1 + cmp r2, ip + bne .L10344 + b .L9529 +.L10085: + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r2, r1, r3, asl #6 + ldreq r0, [sp, #84] + beq .L10189 + cmp ip, #3 + rsb lr, ip, #8 + bhi .L10345 + subs r5, lr, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #84] + beq .L10202 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r0, #0 +.L10203: + movs r3, r1, lsr #24 + ldr ip, [sp, #24] + ldrne r6, [sp, #84] + orr r3, ip, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp r5, r0 + mov r1, r1, asl #8 + bne .L10203 + ldr r7, [sp, #84] + add r3, r7, lr, asl #2 + sub r0, r3, #16 +.L10202: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L10208 + ands r3, r1, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r1, [sp, #24] + orrne r3, r1, r3 + strne r3, [r0, #0] +.L10208: + add r0, r0, #16 +.L10194: + sub r2, r2, #64 +.L10189: + movs lr, r4, lsr #3 + beq .L9529 + mov ip, #0 + b .L10218 +.L10346: + sub r2, r2, #64 + add r0, r0, #32 +.L10218: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L10219 + ands r3, r1, #255 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + strne r3, [r0, #0] +.L10219: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L10228 + ands r3, r1, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r0, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #24] + orrne r3, r4, r3 + strne r3, [r0, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + strne r3, [r0, #20] + movs r3, r1, lsr #24 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + strne r3, [r0, #16] +.L10228: + add ip, ip, #1 + cmp ip, lr + bne .L10346 + b .L9529 +.L9605: + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add lr, r0, r2 + ldreq ip, [sp, #84] + beq .L9654 + rsbs r4, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #84] + beq .L9657 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L9658: + ldr r6, [sp, #24] + ands r3, r0, #15 + ldrne r7, [sp, #84] + orr r3, r6, r3 + orr r3, r1, r3 + strne r3, [r7, r2, asl #2] + add r2, r2, #1 + cmp r2, r4 + mov r0, r0, lsr #4 + bne .L9658 + ldr r8, [sp, #84] + add ip, r8, r4, asl #2 +.L9657: + add lr, lr, #32 +.L9654: + movs r4, r5, lsr #3 + beq .L9529 + mov r0, #0 + b .L9664 +.L10347: + add lr, lr, #32 + add ip, ip, #32 +.L9664: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L9665 + ands r3, r2, #15 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [ip, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [ip, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [ip, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #24] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [ip, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #24] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [ip, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #24] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [ip, #24] + movs r3, r2, lsr #28 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #28] +.L9665: + add r0, r0, #1 + cmp r0, r4 + bne .L10347 + b .L9529 +.L9867: + ldr lr, [sp, #108] + rsb r0, ip, #8 + cmp lr, r0 + blt .L10348 + cmp ip, #3 + bls .L9900 + cmp r0, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #84] + beq .L9904 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L9905: + ands r3, r1, #255 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bne .L9905 + ldr lr, [sp, #84] + add r4, lr, r0, asl #2 +.L9904: + ldr r3, [sp, #108] + add r6, r6, #64 + rsb r5, r0, r3 + b .L9869 +.L9737: + ldr r2, [sp, #108] + rsb r5, lr, #8 + cmp r2, r5 + blt .L10349 + cmp r5, #0 + ldr r2, [r0, #0] + ldreq ip, [sp, #84] + beq .L9750 + mov r3, lr, asl #2 + mov r4, r2, asl r3 + mov lr, #0 +.L9751: + ldr r7, [sp, #24] + movs r3, r4, lsr #28 + ldrne r8, [sp, #84] + orr r3, r7, r3 + orr r3, r1, r3 + strne r3, [r8, lr, asl #2] + add lr, lr, #1 + cmp r5, lr + mov r4, r4, asl #4 + bne .L9751 + ldr lr, [sp, #84] + add ip, lr, r5, asl #2 +.L9750: + ldr r3, [sp, #108] + sub r0, r0, #32 + rsb r2, r5, r3 + b .L9739 +.L9607: + ldr r7, [sp, #108] + rsb lr, r3, #8 + cmp r7, lr + blt .L10350 + cmp lr, #0 + ldr r2, [r5, #0] + ldreq r6, [sp, #84] + beq .L9620 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov r0, #0 +.L9621: + ldr r4, [sp, #24] + ands r3, r2, #15 + ldrne r6, [sp, #84] + orr r3, r4, r3 + orr r3, r1, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp lr, r0 + mov r2, r2, lsr #4 + bne .L9621 + ldr r7, [sp, #84] + add r6, r7, lr, asl #2 +.L9620: + ldr r8, [sp, #108] + add r5, r5, #32 + rsb r7, lr, r8 + b .L9609 +.L10087: + ldr r1, [sp, #108] + rsb r0, ip, #8 + cmp r1, r0 + blt .L10351 + cmp ip, #3 + bls .L10120 + cmp r0, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #84] + beq .L10124 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10125: + movs r3, r2, lsr #24 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + orr r3, r8, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bne .L10125 + ldr lr, [sp, #84] + add r4, lr, r0, asl #2 +.L10124: + ldr r3, [sp, #108] + sub r6, r6, #64 + rsb r5, r0, r3 + b .L10089 +.L10351: + cmp r1, #0 + ble .L9529 + cmp ip, #3 + bls .L10093 + ldr r2, [r6, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10096: + movs r3, r2, lsr #24 + ldr r4, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r4, r3 + ldr r6, [sp, #108] + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp r6, r1 + mov r2, r2, asl #8 + bne .L10096 + b .L9529 +.L10350: + cmp r7, #0 + ble .L9529 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L9614: + ldr r8, [sp, #24] + ands r3, r0, #15 + ldrne ip, [sp, #84] + orr r3, r8, r3 + orr r3, r1, r3 + ldr lr, [sp, #108] + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp lr, r2 + mov r0, r0, lsr #4 + bne .L9614 + b .L9529 +.L10349: + cmp r2, #0 + ble .L9529 + ldr r2, [r0, #0] + mov r3, lr, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L9744: + ldr r4, [sp, #24] + movs r3, r0, lsr #28 + ldrne r5, [sp, #84] + orr r3, r4, r3 + orr r3, r1, r3 + ldr r6, [sp, #108] + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r6, r2 + mov r0, r0, asl #4 + bne .L9744 + b .L9529 +.L10345: + cmp lr, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #84] + beq .L10194 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r0, #0 +.L10195: + movs r3, r1, lsr #24 + ldr r6, [sp, #24] + ldrne r7, [sp, #84] + orr r3, r6, r3 + strne r3, [r7, r0, asl #2] + add r0, r0, #1 + cmp r0, lr + mov r1, r1, asl #8 + bne .L10195 + ldr r8, [sp, #84] + sub r2, r2, #64 + add r0, r8, lr, asl #2 + b .L10189 +.L10342: + cmp ip, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #84] + beq .L9974 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov r1, #0 +.L9975: + ands r3, r2, #255 + ldr r6, [sp, #24] + ldrne r7, [sp, #84] + orr r3, r6, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r1, ip + mov r2, r2, lsr #8 + bne .L9975 + ldr r8, [sp, #84] + add r0, r0, #64 + add r1, r8, ip, asl #2 + b .L9969 +.L10348: + cmp lr, #0 + ble .L9529 + cmp ip, #3 + bls .L9873 + ldr r2, [r6, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L9876: + ands r3, r1, #255 + ldr r0, [sp, #24] + ldrne r4, [sp, #84] + orr r3, r0, r3 + ldr r5, [sp, #108] + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r5, r2 + mov r1, r1, lsr #8 + bne .L9876 + b .L9529 +.L10355: + mov r6, #0 + b .L9587 +.L10120: + subs lr, r0, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #84] + beq .L10132 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10133: + movs r3, r2, lsr #24 + ldr r4, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r4, r3 + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, asl #8 + bne .L10133 + ldr r7, [sp, #84] + add r3, r7, r0, asl #2 + sub r1, r3, #16 +.L10132: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L10138 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r1, #0] +.L10138: + add r4, r1, #16 + b .L10124 +.L9900: + subs lr, r0, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #84] + beq .L9912 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L9913: + ands r3, r1, #255 + ldr r4, [sp, #24] + ldrne r5, [sp, #84] + orr r3, r4, r3 + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r1, r1, lsr #8 + bne .L9913 + ldr r7, [sp, #84] + add r3, r7, r0, asl #2 + sub r1, r3, #16 +.L9912: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L9918 + ands r3, r2, #255 + ldrne r8, [sp, #24] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #24] + orrne r3, ip, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #24] + orrne r3, lr, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #24] + orrne r3, r2, r3 + strne r3, [r1, #12] +.L9918: + add r4, r1, #16 + b .L9904 +.L10353: + ldr r5, [sp, #16] + b .L10318 +.L10352: + mov ip, fp + b .L10316 +.L10093: + ldr r7, [sp, #108] + mov r3, ip, asl #3 + ldr r1, [r6, #4] + add r2, r7, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L10100 + cmp r7, #0 + movne r2, #0 + beq .L9529 +.L10116: + movs r3, r1, lsr #24 + ldr r5, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r5, r3 + ldr r7, [sp, #108] + strne r3, [r6, r2, asl #2] + add r2, r2, #1 + cmp r7, r2 + mov r1, r1, asl #8 + bne .L10116 + b .L9529 +.L9873: + ldr r7, [sp, #108] + ldr r3, [r6, #0] + add r2, r7, ip + cmp r2, #4 + mov r1, ip, asl #3 + mov r2, r3, lsr r1 + bhi .L9880 + cmp r7, #0 + movne r1, #0 + beq .L9529 +.L9896: + ands r3, r2, #255 + ldr r5, [sp, #24] + ldrne r6, [sp, #84] + orr r3, r5, r3 + ldr r7, [sp, #108] + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r7, r1 + mov r2, r2, lsr #8 + bne .L9896 + b .L9529 +.L10100: + rsbs r0, ip, #4 + ldreq ip, [sp, #84] + beq .L10105 + mov r2, #0 +.L10106: + movs r3, r1, lsr #24 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, r0 + mov r1, r1, asl #8 + bne .L10106 + ldr lr, [sp, #84] + add ip, lr, r0, asl #2 +.L10105: + ldr r1, [sp, #108] + ldr r2, [r6, #0] + subs r0, r1, r0 + beq .L9529 + mov r1, #0 +.L10112: + ldr r4, [sp, #24] + movs r3, r2, lsr #24 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, asl #8 + bne .L10112 + b .L9529 +.L9880: + rsbs r0, ip, #4 + ldreq ip, [sp, #84] + beq .L9885 + mov r1, #0 +.L9886: + ands r3, r2, #255 + ldr r8, [sp, #24] + ldrne ip, [sp, #84] + orr r3, r8, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L9886 + ldr lr, [sp, #84] + add ip, lr, r0, asl #2 +.L9885: + ldr r1, [sp, #108] + ldr r2, [r6, #4] + subs r0, r1, r0 + beq .L9529 + mov r1, #0 +.L9892: + ldr r4, [sp, #24] + ands r3, r2, #255 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L9892 + b .L9529 + .size render_scanline_obj_color32_1D, .-render_scanline_obj_color32_1D + .align 2 + .global render_scanline_obj_color32_2D + .type render_scanline_obj_color32_2D, %function +render_scanline_obj_color32_2D: + @ args = 0, pretend = 0, frame = 96 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L11200 + sub sp, sp, #96 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #36] + ldr r5, [sp, #36] + ldrh r4, [ip, #80] + ldr ip, .L11200+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #40] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L11200+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #44] + str r1, [sp, #12] + str r2, [sp, #8] + str r3, [sp, #4] + str lr, [sp, #28] + beq .L11146 + mov r8, #0 + add r6, r3, r1, asl #2 + rsb r7, r1, r2 + str r6, [sp, #68] + str r7, [sp, #92] + str r8, [sp, #32] + mov ip, r8 +.L10361: + ldr lr, [sp, #44] + ldr r0, .L11200+12 + ldrb r3, [ip, lr] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh r4, [r3, r0] + add r3, r3, r0 + ldrh r1, [r3, #2] + mov r5, r4, lsr #12 + and r2, r5, #12 + orr r0, r2, r1, lsr #14 + and ip, r4, #255 + mov r2, r1, asl #23 + cmp ip, #160 + ldrh lr, [r3, #4] + mov r6, r2, asr #23 + ldr r3, .L11200+16 + ldr r2, .L11200+20 + subgt ip, ip, #256 + tst r4, #256 + ldr r8, [r2, r0, asl #2] + ldr sl, [r3, r0, asl #2] + beq .L10364 + tst r4, #8192 + beq .L10366 + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L11200+12 + and r3, r3, #992 + add r3, r3, r4 + add r2, r8, r8, lsr #31 + ldrh r5, [r3, #30] + mov r4, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + movne r0, r4, asl #1 + str r5, [sp, #16] + mov r5, r1, asr #1 + strne r0, [sp, #52] + moveq r9, r8 + streq r4, [sp, #52] + moveq r0, r5 + movne r9, r8, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + ldrh r7, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L10371 + rsb r2, r6, r2 + rsb r9, r2, r9 + cmp r9, #0 + ble .L10373 + ldr r3, [sp, #52] + ldr r6, [sp, #12] + rsb r3, r2, r3 + str r3, [sp, #52] +.L10371: + ldr r2, [sp, #8] + add r3, r6, r9 + cmp r3, r2 + blt .L10375 + rsb r9, r6, r2 + cmp r9, #0 + ble .L10373 +.L10375: + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r7, [sp, #16] + mov r3, r3, asr #16 + add r0, ip, r0 + str r3, [sp, #48] + mov ip, r2, asr #16 + ldr r3, [sp, #36] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov r4, r4, asl #8 + cmp fp, #0 + str r4, [sp, #76] + mov r1, r1, asr #16 + mov r4, r5, asl #8 + add r7, r2, r6, asl #2 + rsb r0, r0, r3 + bne .L10377 + mla r3, r0, r1, r4 + mov r1, r3, asr #8 + cmp r1, sl + bcs .L10373 + mov r3, lr, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L11200+24 + cmp r9, #0 + add lr, r3, r1, asl #3 + ble .L10373 + ldr r4, [sp, #48] + ldr r2, [sp, #52] + mul r3, r0, ip + mul r2, r4, r2 + ldr r5, [sp, #76] + rsb r3, r2, r3 + add r0, r5, r3 + mov r4, r0, asr #8 + cmp r4, r8 + movcs ip, fp + bcs .L10383 + b .L11196 +.L10384: + cmp r4, r8 + bcc .L11160 +.L10383: + ldr r6, [sp, #48] + add ip, ip, #1 + add r0, r0, r6 + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #4 + bne .L10384 +.L10373: + ldr ip, [sp, #32] + ldr lr, [sp, #40] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #32] + beq .L11146 +.L11178: + ldr ip, [sp, #32] + b .L10361 +.L10364: + ldr r2, [sp, #36] + tst r1, #8192 + rsb r0, ip, r2 + rsbne r3, r0, sl + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, r5, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L10373 + .p2align 2 +.L10445: + .word .L10441 + .word .L10442 + .word .L10443 + .word .L10444 +.L10441: + mov r3, lr, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + mov r2, lr, lsr #8 + cmp r6, r3 + ldr r3, .L11200+24 + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L11173 + ldr ip, [sp, #8] + add r3, r6, r8 + cmp ip, r3 + bhi .L10527 + rsb r7, r6, ip + cmp r7, #0 + ble .L10373 + ldr lr, [sp, #4] + movs r8, r7, lsr #3 + add r2, lr, r6, asl #2 + beq .L10530 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L10532: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10533 + ands r3, r4, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] +.L10533: + add ip, ip, #1 + cmp ip, r8 + add lr, lr, #32 + add r5, r5, #32 + bne .L10532 + mov r3, r8, asl #5 + add r0, r0, r3 + add r2, r2, r3 +.L10530: + ands lr, r7, #7 + beq .L10373 + ldr r0, [r0, #0] + mov ip, #0 +.L10552: + ldr r5, [sp, #28] + ands r3, r0, #15 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [r2, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, lsr #4 + bne .L10552 + b .L10373 +.L10442: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + subs r2, r8, #8 + mov r3, r3, lsr #22 + submi r2, r8, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr ip, [sp, #12] + add r1, r1, r3, asl #3 + ldr r3, .L11200+24 + mov r2, lr, lsr #8 + cmp r6, ip + add r0, r3, r1, asl #2 + and r1, r2, #240 + blt .L11174 + ldr ip, [sp, #8] + add r3, r6, r8 + cmp ip, r3 + bhi .L10657 + rsb r8, r6, ip + cmp r8, #0 + ble .L10373 + ldr lr, [sp, #4] + movs r7, r8, lsr #3 + add r2, lr, r6, asl #2 + beq .L10660 + mov r5, r2 + mov lr, r0 + mov ip, #0 +.L10662: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10663 + ands r3, r4, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L10663: + add ip, ip, #1 + cmp ip, r7 + sub lr, lr, #32 + add r5, r5, #32 + bne .L10662 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r2, r2, r7, asl #5 +.L10660: + ands lr, r8, #7 + beq .L10373 + ldr r0, [r0, #0] + mov ip, #0 +.L10682: + ldr r5, [sp, #28] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [r2, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, asl #4 + bne .L10682 + b .L10373 +.L10443: + mov r2, lr, asl #22 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + and r3, r0, #7 + add r2, r2, r1, asl #5 + add r3, r3, r2, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L11200+24 + cmp r6, ip + add ip, r0, r3 + blt .L11175 + ldr lr, [sp, #8] + add r3, r6, r8 + cmp lr, r3 + bhi .L10862 + rsb r8, r6, lr + cmp r8, #0 + ble .L10373 + ldr r1, [sp, #4] + movs r7, r8, lsr #3 + add r2, r1, r6, asl #2 + beq .L10865 + ldr r3, .L11200+32 + mov r5, r2 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L10867: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10868 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #8] + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r5, #12] +.L10868: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L10877 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r5, #28] +.L10877: + add r1, r1, #1 + cmp r7, r1 + add lr, lr, #64 + add r5, r5, #32 + add r0, r0, #64 + bne .L10867 + add ip, ip, r7, asl #6 + add r2, r2, r7, asl #5 +.L10865: + ands lr, r8, #7 + beq .L10373 + cmp lr, #3 + ldrls r0, [ip, #0] + bls .L10900 + ldr r1, [ip, #0] + cmp r1, #0 + beq .L10890 + ands r3, r1, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r2, #0] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r2, #4] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r2, #8] + movs r3, r1, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r2, #12] +.L10890: + subs lr, lr, #4 + ldr r0, [ip, #4] + addne r2, r2, #16 + beq .L10373 +.L10900: + mov r1, #0 +.L10901: + ldr ip, [sp, #28] + ands r3, r0, #255 + orr r3, ip, r3 + strne r3, [r2, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r0, r0, lsr #8 + bhi .L10901 + b .L10373 +.L10444: + subs r2, r8, #8 + submi r2, r8, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, lr, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L11200+24 + cmp r6, ip + add ip, r0, r3 + blt .L11176 + ldr lr, [sp, #8] + add r3, r6, r8 + cmp r3, lr + bcc .L11082 + rsb r8, r6, lr + cmp r8, #0 + ble .L10373 + ldr r1, [sp, #4] + movs r7, r8, lsr #3 + add r6, r1, r6, asl #2 + beq .L11085 + ldr r3, .L11200+28 + mov r5, r6 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L11087: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L11088 + ands r3, r4, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r5, #0] +.L11088: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L11097 + ands r3, r4, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r5, #20] + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r5, #16] +.L11097: + add r1, r1, #1 + cmp r1, r7 + sub lr, lr, #64 + add r5, r5, #32 + sub r0, r0, #64 + bne .L11087 + rsb r3, r7, r7, asl #26 + add ip, ip, r3, asl #6 + add r6, r6, r7, asl #5 +.L11085: + ands r0, r8, #7 + beq .L10373 + cmp r0, #3 + ldrls r2, [ip, #4] + bls .L11120 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L11110 + ands r3, r2, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r6, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r6, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r6, #4] + movs r3, r2, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r6, #0] +.L11110: + subs r0, r0, #4 + ldr r2, [ip, #0] + addne r6, r6, #16 + beq .L10373 +.L11120: + mov r1, #0 +.L11121: + ldr r4, [sp, #28] + movs r3, r2, lsr #24 + orr r3, r4, r3 + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L11121 + b .L10373 +.L10366: + mov r3, r1, lsr #4 + ldr r1, .L11200+12 + and r3, r3, #992 + add r3, r3, r1 + tst r4, #512 + ldrh r4, [r3, #30] + add r2, r8, r8, lsr #31 + add r1, sl, sl, lsr #31 + str r4, [sp, #24] + mov r4, r2, asr #1 + ldr r2, [sp, #12] + mov r5, r1, asr #1 + ldrh r7, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r8 + moveq r9, r4 + moveq r0, r5 + movne fp, r8, asl #1 + movne r9, r4, asl #1 + movne r0, r5, asl #1 + cmp r6, r2 + str r3, [sp, #20] + bge .L10404 + rsb r2, r6, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L10373 + ldr r6, [sp, #12] + rsb r9, r2, r9 +.L10404: + ldr r2, [sp, #8] + add r3, r6, fp + cmp r3, r2 + blt .L10407 + rsb fp, r6, r2 + cmp fp, #0 + ble .L10373 +.L10407: + add ip, ip, r0 + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r0, [sp, #20] + ldr r7, [sp, #24] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + cmp r0, #0 + str r3, [sp, #56] + mov r0, lr, lsr #8 + str r2, [sp, #60] + ldr r3, [sp, #36] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov r4, r4, asl #8 + and r0, r0, #240 + str r4, [sp, #72] + mov r1, r1, asr #16 + mov r4, r5, asl #8 + add r7, r2, r6, asl #2 + rsb ip, ip, r3 + str r0, [sp, #88] + bne .L10409 + mla r3, ip, r1, r4 + mov r1, r3, asr #8 + cmp r1, sl + bcs .L10373 + mov r3, lr, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #3 + ldr r3, .L11200+24 + cmp fp, #0 + add r1, r3, r1, asl #2 + ble .L10373 + ldr r3, [sp, #60] + ldr r2, [sp, #56] + mul r3, ip, r3 + mul r2, r9, r2 + ldr r4, [sp, #72] + rsb r3, r2, r3 + add r0, r4, r3 + mov r4, r0, asr #8 + cmp r4, r8 + ldrcs r5, [sp, #20] + bcs .L10415 + b .L11197 +.L10416: + cmp r4, r8 + bcc .L11162 +.L10415: + ldr r6, [sp, #56] + add r5, r5, #1 + add r0, r0, r6 + cmp fp, r5 + mov r4, r0, asr #8 + add r7, r7, #4 + bne .L10416 + ldr ip, [sp, #32] + ldr lr, [sp, #40] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #32] + bne .L11178 +.L11146: + add sp, sp, #96 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L10377: + mov r3, lr, asl #22 + ldr r2, .L11200+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r9, #0 + str r3, [sp, #84] + ble .L10373 + mov r3, fp, asl #16 + mul r2, r0, r1 + mov fp, r3, asr #16 + ldr r6, [sp, #48] + mul r3, r0, ip + ldr r1, [sp, #52] + ldr r0, [sp, #52] + mul r1, fp, r1 + mul r0, r6, r0 + ldr ip, [sp, #76] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, ip, r3 + add lr, r4, r2 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + cmp ip, r8 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L10393 + b .L11198 +.L10394: + cmp ip, r8 + cmpcc r4, sl + bcc .L10395 +.L10393: + ldr r0, [sp, #48] + add r6, r6, #1 + add r5, r5, r0 + add lr, lr, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + add r7, r7, #4 + bne .L10394 + b .L10373 +.L10409: + mov r3, lr, asl #22 + ldr r2, .L11200+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp fp, #0 + str r3, [sp, #80] + ble .L10373 + ldr r5, [sp, #20] + mul r2, ip, r1 + mov r3, r5, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #64] + ldr r1, [sp, #64] + ldr r3, [sp, #60] + ldr r0, [sp, #56] + mul r3, ip, r3 + mul r1, r9, r1 + mul r0, r9, r0 + ldr r6, [sp, #72] + rsb r3, r0, r3 + rsb r2, r1, r2 + add lr, r6, r3 + add r5, r4, r2 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + cmp ip, r8 + cmpcc r4, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L10428 + b .L11199 +.L10429: + cmp ip, r8 + cmpcc r4, sl + bcc .L10431 +.L10428: + ldr ip, [sp, #56] + ldr r0, [sp, #64] + add r6, r6, #1 + add lr, lr, ip + add r5, r5, r0 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #4 + bne .L10429 + b .L10373 +.L11181: + mov r3, ip, asr #1 + ldr r1, [sp, #80] + and r3, r3, #3 + and r0, r4, #7 + str r3, [sp, #0] + ldr r3, [sp, #80] + add r0, r1, r0, asl #2 + and r1, r4, #7 + mov r2, ip, asr #1 + add r1, r3, r1, asl #2 + mov r3, r4, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + tst ip, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne r4, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, r4] @ zero_extendqisi2 + ldr r2, [sp, #28] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + cmp r0, #0 + orr r3, r0, r2 + ldr r0, [sp, #88] + ldr ip, [sp, #56] + ldr r1, [sp, #64] + add r6, r6, #1 + orr r3, r0, r3 + strne r3, [r7, #0] + add lr, lr, ip + add r5, r5, r1 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #4 + ble .L10373 +.L10431: + cmp r4, sl + cmpcc ip, r8 + bcc .L11181 + b .L10373 +.L10418: + cmp r4, r8 + bcs .L10373 +.L11162: + mov r3, r4, asr #1 + and sl, r3, #3 + mov r3, r4, asr #3 + mov r3, r3, asl #5 + mov r2, r4, asr #1 + tst r4, #1 + add ip, r3, r1 + and r6, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r6] @ zero_extendqisi2 + ldrneb r3, [ip, sl] @ zero_extendqisi2 + ldr lr, [sp, #28] + movne r2, r3, lsr #4 + andeq r2, r3, #15 + cmp r2, #0 + orr r3, r2, lr + ldr r2, [sp, #88] + ldr ip, [sp, #56] + add r5, r5, #1 + orr r3, r2, r3 + strne r3, [r7, #0] + add r0, r0, ip + cmp fp, r5 + mov r4, r0, asr #8 + add r7, r7, #4 + bgt .L10418 + b .L10373 +.L10386: + cmp r4, r8 + bcs .L10373 +.L11160: + ldr r1, [sp, #48] + mov r3, r4, asr #3 + add r0, r0, r1 + add r3, lr, r3, asl #6 + and r1, r4, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #28] + cmp r2, #0 + add ip, ip, #1 + orr r3, r5, r2 + strne r3, [r7, #0] + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #4 + bgt .L10386 + b .L10373 +.L11176: + ldr lr, [sp, #12] + rsb r1, r6, lr + rsb lr, r1, r8 + cmp lr, #0 + ble .L10373 + ldr r0, [sp, #8] + add r3, r6, r8 + cmp r0, r3 + bhi .L10929 + mov r3, r1, lsr #3 + ands r0, r1, #7 + sub r6, ip, r3, asl #6 + bne .L10931 + ldr r5, [sp, #92] + ldr r4, [sp, #68] +.L10933: + movs lr, r5, lsr #3 + beq .L10991 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L10993: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10994 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] +.L10994: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L11003 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #28] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #24] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #20] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #16] +.L11003: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #32 + bne .L10993 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #5 +.L10991: + ands r0, r5, #7 + beq .L10373 + cmp r0, #3 + ldrls r2, [r6, #4] + bls .L11026 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L11016 + ands r3, r2, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r1, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #0] +.L11016: + subs r0, r0, #4 + ldr r2, [r6, #0] + addne r4, r4, #16 + beq .L10373 +.L11026: + mov r1, #0 +.L11027: + ldr r5, [sp, #28] + movs r3, r2, lsr #24 + orr r3, r5, r3 + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L11027 + b .L10373 +.L11201: + .align 2 +.L11200: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L11175: + ldr lr, [sp, #12] + rsb r1, r6, lr + rsb lr, r1, r8 + cmp lr, #0 + ble .L10373 + ldr r0, [sp, #8] + add r3, r6, r8 + cmp r0, r3 + bhi .L10709 + mov r3, r1, lsr #3 + ands r0, r1, #7 + add r6, ip, r3, asl #6 + bne .L10711 + ldr r5, [sp, #92] + ldr r4, [sp, #68] +.L10713: + movs lr, r5, lsr #3 + beq .L10771 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L10773: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L10774 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #12] +.L10774: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10783 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #28] +.L10783: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + add r1, r1, #32 + bne .L10773 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #5 +.L10771: + ands r0, r5, #7 + beq .L10373 + cmp r0, #3 + ldrls r1, [r6, #0] + bls .L10806 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L10796 + ands r3, r2, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r1, r3 + strne r3, [r4, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #12] +.L10796: + subs r0, r0, #4 + ldr r1, [r6, #4] + addne r4, r4, #16 + beq .L10373 +.L10806: + mov r2, #0 +.L10807: + ldr r5, [sp, #28] + ands r3, r1, #255 + orr r3, r5, r3 + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bhi .L10807 + b .L10373 +.L11174: + rsb r4, r6, ip + rsb ip, r4, r8 + cmp ip, #0 + ble .L10373 + ldr lr, [sp, #8] + add r3, r6, r8 + cmp lr, r3 + bhi .L10579 + mov r3, r4, lsr #3 + ands lr, r4, #7 + sub r0, r0, r3, asl #5 + bne .L10581 + ldr r2, [sp, #92] + ldr ip, [sp, #68] +.L10583: + movs r7, r2, lsr #3 + beq .L10600 + mov r5, ip + mov lr, r0 + mov r6, #0 +.L10602: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L10603 + ands r3, r4, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L10603: + add r6, r6, #1 + cmp r6, r7 + sub lr, lr, #32 + add r5, r5, #32 + bne .L10602 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add ip, ip, r7, asl #5 +.L10600: + ands lr, r2, #7 + beq .L10373 + ldr r0, [r0, #0] + mov r2, #0 +.L10622: + ldr r5, [sp, #28] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r1, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r0, r0, asl #4 + bne .L10622 + b .L10373 +.L11173: + ldr r5, [sp, #12] + rsb r4, r6, r5 + rsb r5, r4, r8 + cmp r5, #0 + ble .L10373 + add r3, r6, r8 + ldr r6, [sp, #8] + cmp r6, r3 + bhi .L10449 + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add r5, r0, r2 + bne .L10451 + ldr r7, [sp, #92] + ldr r6, [sp, #68] +.L10453: + movs r4, r7, lsr #3 + beq .L10470 + mov ip, r6 + mov r0, r5 + mov lr, #0 +.L10472: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L10473 + ands r3, r2, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #24] + movs r3, r2, lsr #28 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r1, r3 + strne r3, [ip, #28] +.L10473: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #32 + add ip, ip, #32 + bne .L10472 + mov r3, r4, asl #5 + add r5, r5, r3 + add r6, r6, r3 +.L10470: + ands ip, r7, #7 + beq .L10373 + ldr r2, [r5, #0] + mov r0, #0 +.L10492: + ldr r4, [sp, #28] + ands r3, r2, #15 + orr r3, r4, r3 + orr r3, r1, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp r0, ip + mov r2, r2, lsr #4 + bne .L10492 + b .L10373 +.L11198: + mov r6, #0 +.L10395: + cmp r4, sl + movcc r3, #0 + movcs r3, #1 + cmp r8, ip + orrls r3, r3, #1 + cmp r3, #0 + beq .L11161 + b .L10373 +.L10396: + cmp r4, sl + cmpcc ip, r8 + bcs .L10373 +.L11161: + ldr r1, [sp, #48] + and r3, r4, #7 + mov r2, ip, asr #3 + mov r3, r3, asl #3 + add r5, r5, r1 + add r3, r3, r2, asl #6 + mov r1, r4, asr #3 + ldr r2, [sp, #84] + add r3, r3, r1, asl #10 + and r0, ip, #7 + add r3, r3, r2 + ldrb r2, [r3, r0] @ zero_extendqisi2 + ldr r0, [sp, #28] + cmp r2, #0 + add r6, r6, #1 + orr r3, r0, r2 + strne r3, [r7, #0] + add lr, lr, fp + cmp r9, r6 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + add r7, r7, #4 + bgt .L10396 + b .L10373 +.L10657: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L10373 + ldr r7, [sp, #4] + mov ip, #0 + add r2, r7, r6, asl #2 + b .L10687 +.L11182: + sub r0, r0, #32 + add r2, r2, #32 +.L10687: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L10688 + ands r3, r4, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [r2, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #4] + movs r3, r4, lsr #28 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #0] +.L10688: + add ip, ip, #1 + cmp lr, ip + bne .L11182 + b .L10373 +.L11082: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L10373 + ldr r5, [sp, #4] + ldr r3, .L11200+28 + add r2, r5, r6, asl #2 + add r0, r0, r3 + mov r1, #0 + b .L11126 +.L11183: + sub ip, ip, #64 + add r2, r2, #32 +.L11126: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L11127 + ands r3, r4, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r2, #4] + movs r3, r4, lsr #24 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r2, #0] +.L11127: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L11136 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r2, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r2, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r2, #20] + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r2, #16] +.L11136: + add r1, r1, #1 + cmp lr, r1 + sub r0, r0, #64 + bne .L11183 + b .L10373 +.L10527: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L10373 + ldr r7, [sp, #4] + mov ip, #0 + add r2, r7, r6, asl #2 + b .L10557 +.L11184: + add r0, r0, #32 + add r2, r2, #32 +.L10557: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L10558 + ands r3, r4, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [r2, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r2, #24] + movs r3, r4, lsr #28 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r2, #28] +.L10558: + add ip, ip, #1 + cmp lr, ip + bne .L11184 + b .L10373 +.L10862: + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs lr, r3, asr #3 + beq .L10373 + ldr r1, [sp, #4] + ldr r3, .L11200+32 + add r2, r1, r6, asl #2 + add r0, r0, r3 + mov r1, #0 + b .L10906 +.L11185: + add ip, ip, #64 + add r2, r2, #32 +.L10906: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L10907 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r2, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r2, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r2, #8] + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r2, #12] +.L10907: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L10916 + ands r3, r4, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r2, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r2, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r2, #24] + movs r3, r4, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r2, #28] +.L10916: + add r1, r1, #1 + cmp lr, r1 + add r0, r0, #64 + bne .L11185 + b .L10373 +.L10709: + mov r3, r1, lsr #3 + ands r2, r1, #7 + add r0, ip, r3, asl #6 + ldreq r1, [sp, #68] + beq .L10813 + cmp r2, #3 + rsb ip, r2, #8 + bhi .L11186 + subs r4, ip, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #68] + beq .L10826 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov r1, #0 +.L10827: + ands r3, r2, #255 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r5, r3 + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r1, r4 + mov r2, r2, lsr #8 + bne .L10827 + ldr r7, [sp, #68] + add r3, r7, ip, asl #2 + sub r1, r3, #16 +.L10826: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10832 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #12] +.L10832: + add r1, r1, #16 +.L10818: + add r0, r0, #64 +.L10813: + movs lr, lr, lsr #3 + beq .L10373 + mov ip, #0 + b .L10842 +.L11187: + add r0, r0, #64 + add r1, r1, #32 +.L10842: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L10843 + ands r3, r2, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r1, #12] +.L10843: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L10852 + ands r3, r2, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #28] +.L10852: + add ip, ip, #1 + cmp lr, ip + bne .L11187 + b .L10373 +.L10579: + ands r2, r4, #7 + mov r3, r4, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r5, [sp, #68] + beq .L10628 + rsbs r5, r2, #8 + ldr lr, [r0, #0] + ldreq r5, [sp, #68] + beq .L10631 + mov r3, r2, asl #2 + mov r4, lr, asl r3 + mov lr, #0 +.L10632: + ldr r6, [sp, #28] + movs r3, r4, lsr #28 + ldrne r7, [sp, #68] + orr r3, r6, r3 + orr r3, r1, r3 + strne r3, [r7, lr, asl #2] + add lr, lr, #1 + cmp r5, lr + mov r4, r4, asl #4 + bne .L10632 + ldr r8, [sp, #68] + add r5, r8, r5, asl #2 +.L10631: + sub r0, r0, #32 +.L10628: + movs ip, ip, lsr #3 + beq .L10373 + mov r2, #0 + b .L10638 +.L11188: + sub r0, r0, #32 + add r5, r5, #32 +.L10638: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L10639 + ands r3, r4, #15 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + orrne r3, r1, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [r5, #0] +.L10639: + add r2, r2, #1 + cmp r2, ip + bne .L11188 + b .L10373 +.L10929: + ands r0, r1, #7 + mov r3, r1, lsr #3 + sub r2, ip, r3, asl #6 + ldreq r0, [sp, #68] + beq .L11033 + cmp r0, #3 + rsb ip, r0, #8 + bhi .L11189 + subs r4, ip, #4 + ldr r1, [r2, #4] + ldreq r0, [sp, #68] + beq .L11046 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r0, #0 +.L11047: + movs r3, r1, lsr #24 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r5, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp r4, r0 + mov r1, r1, asl #8 + bne .L11047 + ldr r7, [sp, #68] + add r3, r7, ip, asl #2 + sub r0, r3, #16 +.L11046: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L11052 + ands r3, r1, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r0, #0] +.L11052: + add r0, r0, #16 +.L11038: + sub r2, r2, #64 +.L11033: + movs lr, lr, lsr #3 + beq .L10373 + mov ip, #0 + b .L11062 +.L11190: + sub r2, r2, #64 + add r0, r0, #32 +.L11062: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L11063 + ands r3, r1, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r1, [sp, #28] + orrne r3, r1, r3 + strne r3, [r0, #0] +.L11063: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L11072 + ands r3, r1, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r0, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r0, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + strne r3, [r0, #20] + movs r3, r1, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r0, #16] +.L11072: + add ip, ip, #1 + cmp ip, lr + bne .L11190 + b .L10373 +.L10449: + mov r3, r4, lsr #3 + mov r2, r3, asl #5 + ands r3, r4, #7 + add lr, r0, r2 + ldreq ip, [sp, #68] + beq .L10498 + rsbs r4, r3, #8 + ldr r0, [r0, r2] + ldreq ip, [sp, #68] + beq .L10501 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L10502: + ldr r6, [sp, #28] + ands r3, r0, #15 + ldrne r7, [sp, #68] + orr r3, r6, r3 + orr r3, r1, r3 + strne r3, [r7, r2, asl #2] + add r2, r2, #1 + cmp r2, r4 + mov r0, r0, lsr #4 + bne .L10502 + ldr r8, [sp, #68] + add ip, r8, r4, asl #2 +.L10501: + add lr, lr, #32 +.L10498: + movs r4, r5, lsr #3 + beq .L10373 + mov r0, #0 + b .L10508 +.L11191: + add lr, lr, #32 + add ip, ip, #32 +.L10508: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L10509 + ands r3, r2, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [ip, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [ip, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [ip, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r1, r3 + strne r3, [ip, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r6, [sp, #28] + orrne r3, r6, r3 + orrne r3, r1, r3 + strne r3, [ip, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r1, r3 + strne r3, [ip, #24] + movs r3, r2, lsr #28 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r1, r3 + strne r3, [ip, #28] +.L10509: + add r0, r0, #1 + cmp r0, r4 + bne .L11191 + b .L10373 +.L10711: + ldr r1, [sp, #92] + rsb ip, r0, #8 + cmp r1, ip + blt .L11192 + cmp r0, #3 + bls .L10744 + cmp ip, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #68] + beq .L10748 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L10749: + ands r3, r1, #255 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + orr r3, r8, r3 + strne r3, [lr, r2, asl #2] + add r2, r2, #1 + cmp ip, r2 + mov r1, r1, lsr #8 + bne .L10749 + ldr r0, [sp, #68] + add r4, r0, ip, asl #2 +.L10748: + ldr r3, [sp, #92] + add r6, r6, #64 + rsb r5, ip, r3 + b .L10713 +.L10581: + ldr r2, [sp, #92] + rsb r5, lr, #8 + cmp r2, r5 + blt .L11193 + cmp r5, #0 + ldr r2, [r0, #0] + ldreq ip, [sp, #68] + beq .L10594 + mov r3, lr, asl #2 + mov r4, r2, asl r3 + mov lr, #0 +.L10595: + ldr r7, [sp, #28] + movs r3, r4, lsr #28 + ldrne r8, [sp, #68] + orr r3, r7, r3 + orr r3, r1, r3 + strne r3, [r8, lr, asl #2] + add lr, lr, #1 + cmp r5, lr + mov r4, r4, asl #4 + bne .L10595 + ldr lr, [sp, #68] + add ip, lr, r5, asl #2 +.L10594: + ldr r3, [sp, #92] + sub r0, r0, #32 + rsb r2, r5, r3 + b .L10583 +.L10451: + ldr r7, [sp, #92] + rsb lr, r3, #8 + cmp r7, lr + blt .L11194 + cmp lr, #0 + ldr r2, [r5, #0] + ldreq r6, [sp, #68] + beq .L10464 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov r0, #0 +.L10465: + ldr r4, [sp, #28] + ands r3, r2, #15 + ldrne r6, [sp, #68] + orr r3, r4, r3 + orr r3, r1, r3 + strne r3, [r6, r0, asl #2] + add r0, r0, #1 + cmp lr, r0 + mov r2, r2, lsr #4 + bne .L10465 + ldr r7, [sp, #68] + add r6, r7, lr, asl #2 +.L10464: + ldr r8, [sp, #92] + add r5, r5, #32 + rsb r7, lr, r8 + b .L10453 +.L10931: + ldr r1, [sp, #92] + rsb ip, r0, #8 + cmp r1, ip + blt .L11195 + cmp r0, #3 + bls .L10964 + cmp ip, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #68] + beq .L10968 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10969: + movs r3, r2, lsr #24 + ldr r8, [sp, #28] + ldrne lr, [sp, #68] + orr r3, r8, r3 + strne r3, [lr, r1, asl #2] + add r1, r1, #1 + cmp ip, r1 + mov r2, r2, asl #8 + bne .L10969 + ldr r0, [sp, #68] + add r4, r0, ip, asl #2 +.L10968: + ldr r3, [sp, #92] + sub r6, r6, #64 + rsb r5, ip, r3 + b .L10933 +.L11195: + cmp r1, #0 + ble .L10373 + cmp r0, #3 + bls .L10937 + ldr r2, [r6, #0] + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10940: + movs r3, r2, lsr #24 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + orr r3, r4, r3 + ldr r6, [sp, #92] + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp r6, r1 + mov r2, r2, asl #8 + bne .L10940 + b .L10373 +.L11194: + cmp r7, #0 + ble .L10373 + ldr r2, [r0, r2] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L10458: + ldr r8, [sp, #28] + ands r3, r0, #15 + ldrne ip, [sp, #68] + orr r3, r8, r3 + orr r3, r1, r3 + ldr lr, [sp, #92] + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp lr, r2 + mov r0, r0, lsr #4 + bne .L10458 + b .L10373 +.L11193: + cmp r2, #0 + ble .L10373 + ldr r2, [r0, #0] + mov r3, lr, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L10588: + ldr r4, [sp, #28] + movs r3, r0, lsr #28 + ldrne r5, [sp, #68] + orr r3, r4, r3 + orr r3, r1, r3 + ldr r6, [sp, #92] + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r6, r2 + mov r0, r0, asl #4 + bne .L10588 + b .L10373 +.L11189: + cmp ip, #0 + ldr r1, [r2, #0] + ldreq r0, [sp, #68] + beq .L11038 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r1, asl r3 + mov r0, #0 +.L11039: + movs r3, r1, lsr #24 + ldr r6, [sp, #28] + ldrne r7, [sp, #68] + orr r3, r6, r3 + strne r3, [r7, r0, asl #2] + add r0, r0, #1 + cmp r0, ip + mov r1, r1, asl #8 + bne .L11039 + ldr r8, [sp, #68] + sub r2, r2, #64 + add r0, r8, ip, asl #2 + b .L11033 +.L11186: + cmp ip, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #68] + beq .L10818 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov r1, #0 +.L10819: + ands r3, r2, #255 + ldr r6, [sp, #28] + ldrne r7, [sp, #68] + orr r3, r6, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r1, ip + mov r2, r2, lsr #8 + bne .L10819 + ldr r8, [sp, #68] + add r0, r0, #64 + add r1, r8, ip, asl #2 + b .L10813 +.L11192: + cmp r1, #0 + ble .L10373 + cmp r0, #3 + bls .L10717 + ldr r2, [r6, #4] + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L10720: + ands r3, r1, #255 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + orr r3, r4, r3 + ldr r6, [sp, #92] + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r6, r2 + mov r1, r1, lsr #8 + bne .L10720 + b .L10373 +.L11199: + mov r6, #0 + b .L10431 +.L10964: + subs lr, ip, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #68] + beq .L10976 + mov r3, r0, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L10977: + movs r3, r2, lsr #24 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + orr r3, r4, r3 + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, asl #8 + bne .L10977 + ldr r7, [sp, #68] + add r3, r7, ip, asl #2 + sub r1, r3, #16 +.L10976: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L10982 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r0, [sp, #28] + orrne r3, r0, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r1, #0] +.L10982: + add r4, r1, #16 + b .L10968 +.L10744: + subs lr, ip, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #68] + beq .L10756 + mov r3, r0, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L10757: + ands r3, r1, #255 + ldr r4, [sp, #28] + ldrne r5, [sp, #68] + orr r3, r4, r3 + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r1, r1, lsr #8 + bne .L10757 + ldr r7, [sp, #68] + add r3, r7, ip, asl #2 + sub r1, r3, #16 +.L10756: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L10762 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r0, [sp, #28] + orrne r3, r0, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r1, #12] +.L10762: + add r4, r1, #16 + b .L10748 +.L11197: + ldr r5, [sp, #20] + b .L11162 +.L11196: + mov ip, fp + b .L11160 +.L10937: + ldr r7, [sp, #92] + mov r3, r0, asl #3 + ldr r1, [r6, #4] + add r2, r7, r0 + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L10944 + cmp r7, #0 + movne r2, #0 + beq .L10373 +.L10960: + movs r3, r1, lsr #24 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r5, r3 + ldr r7, [sp, #92] + strne r3, [r6, r2, asl #2] + add r2, r2, #1 + cmp r7, r2 + mov r1, r1, asl #8 + bne .L10960 + b .L10373 +.L10717: + ldr r7, [sp, #92] + ldr r3, [r6, #0] + add r2, r7, r0 + cmp r2, #4 + mov r1, r0, asl #3 + mov r2, r3, lsr r1 + bhi .L10724 + cmp r7, #0 + movne r1, #0 + beq .L10373 +.L10740: + ands r3, r2, #255 + ldr r5, [sp, #28] + ldrne r6, [sp, #68] + orr r3, r5, r3 + ldr r7, [sp, #92] + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r7, r1 + mov r2, r2, lsr #8 + bne .L10740 + b .L10373 +.L10944: + rsbs r0, r0, #4 + ldreq ip, [sp, #68] + beq .L10949 + mov r2, #0 +.L10950: + movs r3, r1, lsr #24 + ldr r8, [sp, #28] + ldrne ip, [sp, #68] + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, r0 + mov r1, r1, asl #8 + bne .L10950 + ldr lr, [sp, #68] + add ip, lr, r0, asl #2 +.L10949: + ldr r1, [sp, #92] + ldr r2, [r6, #0] + subs r0, r1, r0 + beq .L10373 + mov r1, #0 +.L10956: + ldr r4, [sp, #28] + movs r3, r2, lsr #24 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, asl #8 + bne .L10956 + b .L10373 +.L10724: + rsbs r0, r0, #4 + ldreq ip, [sp, #68] + beq .L10729 + mov r1, #0 +.L10730: + ands r3, r2, #255 + ldr r8, [sp, #28] + ldrne ip, [sp, #68] + orr r3, r8, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L10730 + ldr lr, [sp, #68] + add ip, lr, r0, asl #2 +.L10729: + ldr r1, [sp, #92] + ldr r2, [r6, #4] + subs r0, r1, r0 + beq .L10373 + mov r1, #0 +.L10736: + ldr r4, [sp, #28] + ands r3, r2, #255 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L10736 + b .L10373 + .size render_scanline_obj_color32_2D, .-render_scanline_obj_color32_2D + .align 2 + .global render_scanline_obj_alpha_obj_1D + .type render_scanline_obj_alpha_obj_1D, %function +render_scanline_obj_alpha_obj_1D: + @ args = 0, pretend = 0, frame = 96 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L12434 + sub sp, sp, #96 + ldrh lr, [r5, #80] + mov r4, r0 + mov ip, lr, lsr #11 + and ip, ip, #2 + mov lr, lr, asl #27 + orr ip, ip, lr, lsr #31 + mov ip, ip, asl #9 + orr ip, ip, #256 + tst ip, #512 + str r1, [sp, #8] + str ip, [sp, #20] + str r2, [sp, #4] + str r3, [sp, #0] + beq .L12407 + ldrh r5, [r5, #6] + add r3, r0, r0, asl #2 + ldr r2, .L12434+4 + add r3, r5, r3, asl #5 + ldr r2, [r2, r3, asl #2] + str r5, [sp, #32] + str r2, [sp, #36] + cmp r2, #0 + ldr r2, .L12434+8 + add r3, r2, r3, asl #7 + str r3, [sp, #40] + beq .L12381 + ldr r1, [sp, #8] + ldmia sp, {r0, r2} @ phole ldm + mov r3, #0 + add r0, r0, r1, asl #2 + rsb r2, r1, r2 + str r0, [sp, #68] + str r2, [sp, #92] + str r3, [sp, #24] + mov r4, r3 +.L11207: + ldr r5, [sp, #40] + ldr r6, .L12434+20 + ldrb r3, [r4, r5] @ zero_extendqisi2 + ldr r8, .L12434+12 + mov r3, r3, asl #3 + ldrh lr, [r3, r6] + add r3, r3, r6 + ldrh r4, [r3, #2] + and r0, lr, #255 + mov r5, lr, lsr #12 + and r2, r5, #12 + cmp r0, #160 + ldrh r3, [r3, #4] + ldr sl, .L12434+16 + orr r1, r2, r4, lsr #14 + subgt r0, r0, #256 + mov r2, r4, asl #23 + tst lr, #256 + str r3, [sp, #28] + mov r6, r2, asr #23 + ldr r7, [r8, r1, asl #2] + ldr r9, [sl, r1, asl #2] + beq .L11210 + tst lr, #8192 + beq .L11212 + ldr fp, .L12434+20 + mov r3, r4, lsr #4 + add r2, r7, r7, lsr #31 + and r3, r3, #992 + tst lr, #512 + add r3, r3, fp + mov lr, r2, asr #1 + add r1, r9, r9, lsr #31 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + ldrh sl, [r3, #30] + ldrh r5, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq r8, r7 + moveq fp, lr + moveq ip, r4 + movne r8, r7, asl #1 + movne fp, lr, asl #1 + movne ip, r4, asl #1 + cmp r6, r2 + str r3, [sp, #12] + bge .L11217 + rsb r2, r6, r2 + rsb r8, r2, r8 + cmp r8, #0 + ble .L11219 + ldr r6, [sp, #8] + rsb fp, r2, fp +.L11217: + ldr r2, [sp, #4] + add r3, r6, r8 + cmp r3, r2 + blt .L11221 + rsb r8, r6, r2 + cmp r8, #0 + ble .L11219 +.L11221: + mov r3, r5, asl #16 + mov r2, r1, asl #16 + ldr r5, [sp, #12] + mov r1, sl, asl #16 + mov lr, lr, asl #8 + add r0, r0, ip + str lr, [sp, #80] + mov ip, r1, asr #16 + ldr lr, [sp, #0] + ldr r1, [sp, #32] + cmp r5, #0 + mov r2, r2, asr #16 + add r5, lr, r6, asl #2 + mov sl, r3, asr #16 + str r2, [sp, #44] + mov r4, r4, asl #8 + rsb lr, r0, r1 + bne .L11223 + mla r3, lr, ip, r4 + mov r0, r3, asr #8 + cmp r0, r9 + bcs .L11219 + cmp r7, #0 + ldr r4, [sp, #28] + add r3, r7, #7 + movge r3, r7 + mov r3, r3, asr #3 + mov r2, r4, asl #22 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L12434+24 + add r0, r0, ip, asl #2 + cmp r8, #0 + add r6, r3, r0, asl #3 + ble .L11219 + ldr r3, [sp, #44] + mul r2, sl, fp + mul r3, lr, r3 + ldr r9, [sp, #80] + rsb r3, r2, r3 + add r0, r9, r3 + mov r2, r0, asr #8 + cmp r7, r2 + ldrls lr, [sp, #12] + bls .L11229 + b .L12431 +.L11230: + cmp r7, r2 + bhi .L12395 +.L11229: + add lr, lr, #1 + add r0, r0, sl + cmp r8, lr + mov r2, r0, asr #8 + add r5, r5, #4 + bne .L11230 +.L11219: + ldr r9, [sp, #24] + ldr sl, [sp, #36] + add r9, r9, #1 + cmp r9, sl + str r9, [sp, #24] + beq .L12381 + ldr r4, [sp, #24] + b .L11207 +.L11210: + ldr r1, [sp, #32] + tst r4, #8192 + rsb ip, r0, r1 + rsbne r3, ip, r9 + subne ip, r3, #1 + mov r2, r4, asl #19 + and r3, r5, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L11219 + .p2align 2 +.L11300: + .word .L11296 + .word .L11297 + .word .L11298 + .word .L11299 +.L11296: + ldr r4, [sp, #28] + cmp r7, #0 + add r3, r7, #7 + mov r2, r4, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r5, r3, r2 + ldr r8, [sp, #8] + and r1, ip, #7 + ldr r3, .L12434+24 + add r1, r1, r0, asl #3 + cmp r6, r8 + mov r2, r4, lsr #8 + add r0, r3, r1, asl #2 + and r8, r2, #240 + bge .L11301 + ldr r9, [sp, #8] + rsb lr, r6, r9 + rsb r5, lr, r7 + cmp r5, #0 + ble .L11219 + ldr sl, [sp, #4] + add r3, r6, r7 + cmp sl, r3 + bhi .L11304 + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add r6, r0, r1 + bne .L11306 + ldr sl, [sp, #92] + ldr r4, [sp, #68] +.L11308: + movs r7, sl, lsr #3 + beq .L11329 + mov r0, r4 + mov lr, r6 + mov r5, #0 +.L11331: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L11332 + ands r3, r1, #15 + beq .L11334 + ldr r2, [r0, #0] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L11334: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L11338 + ldr r2, [r0, #4] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L11338: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L11342 + ldr r2, [r0, #8] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L11342: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L11346 + ldr r2, [r0, #12] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L11346: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L11350 + ldr r2, [r0, #16] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L11350: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L11354 + ldr r2, [r0, #20] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L11354: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L11358 + ldr r2, [r0, #24] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L11358: + movs r3, r1, lsr #28 + beq .L11332 + ldr r2, [r0, #28] + orr r1, r8, r3 + tst r2, #256 + ldrne ip, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, ip, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L11332: + add r5, r5, #1 + cmp r5, r7 + add lr, lr, #32 + add r0, r0, #32 + bne .L11331 + mov r3, r7, asl #5 + add r6, r6, r3 + add r4, r4, r3 +.L11329: + ands r5, sl, #7 + beq .L11219 + ldr ip, [r6, #0] + mov lr, #0 +.L11367: + ands r3, ip, #15 + beq .L11368 + ldr r1, [r4, #0] + ldr sl, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L11368: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L11367 + b .L11219 +.L11297: + ldr r5, [sp, #28] + cmp r7, #0 + add r3, r7, #7 + mov r2, r5, asl #22 + movge r3, r7 + mov r5, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, r5, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + ldr r8, [sp, #8] + ldr r9, [sp, #28] + add r0, r0, r3, asr #3 + and r2, ip, #7 + ldr r3, .L12434+24 + add r2, r2, r0, asl #3 + cmp r6, r8 + mov r1, r9, lsr #8 + add r0, r3, r2, asl #2 + and r8, r1, #240 + bge .L11505 + ldr sl, [sp, #8] + rsb lr, r6, sl + rsb sl, lr, r7 + cmp sl, #0 + ble .L11219 + ldr fp, [sp, #4] + add r3, r6, r7 + cmp fp, r3 + bhi .L11508 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub ip, r0, r3, asl #5 + bne .L11510 + ldr sl, [sp, #92] + ldr r5, [sp, #68] +.L11512: + movs r7, sl, lsr #3 + beq .L11533 + mov r0, r5 + mov r4, ip + mov r6, #0 +.L11535: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L11536 + ands r3, r1, #15 + beq .L11538 + ldr r2, [r0, #28] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L11538: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L11542 + ldr r2, [r0, #24] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L11542: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L11546 + ldr r2, [r0, #20] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L11546: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L11550 + ldr r2, [r0, #16] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L11550: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L11554 + ldr r2, [r0, #12] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L11554: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L11558 + ldr r2, [r0, #8] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L11558: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L11562 + ldr r2, [r0, #4] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L11562: + movs r3, r1, lsr #28 + beq .L11536 + ldr r2, [r0, #0] + orr r1, r8, r3 + tst r2, #256 + ldrne lr, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, lr, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L11536: + add r6, r6, #1 + cmp r7, r6 + sub r4, r4, #32 + add r0, r0, #32 + bne .L11535 + rsb r3, r7, r7, asl #27 + add ip, ip, r3, asl #5 + add r5, r5, r7, asl #5 +.L11533: + ands r4, sl, #7 + beq .L11219 + ldr ip, [ip, #0] + mov lr, #0 +.L11571: + movs r3, ip, lsr #28 + beq .L11572 + ldr r1, [r5, #0] + ldr sl, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L11572: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r5, r5, #4 + bne .L11571 + b .L11219 +.L11298: + ldr r5, [sp, #28] + cmp r7, #0 + add r3, r7, #7 + mov r2, ip, lsr #3 + movge r3, r7 + mov r1, r5, asl #22 + mov r4, r3, asr #3 + mov r2, r2, asl #1 + mov r1, r1, lsr #22 + mla r0, r2, r4, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr r8, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L12434+24 + cmp r6, r8 + add ip, r0, r3 + bge .L11709 + rsb r0, r6, r8 + rsb r8, r0, r7 + cmp r8, #0 + ble .L11219 + ldr r9, [sp, #4] + add r3, r6, r7 + cmp r9, r3 + bhi .L11712 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r7, ip, r3, asl #6 + bne .L11714 + ldr r6, [sp, #92] + ldr r4, [sp, #68] +.L11716: + movs r5, r6, lsr #3 + beq .L11794 + mov r1, r4 + mov ip, r7 + mov lr, #0 +.L11796: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L11797 + ands r0, r2, #255 + beq .L11799 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L11799: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L11803 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L11803: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L11807 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L11807: + movs r0, r2, lsr #24 + beq .L11797 + ldr r2, [r1, #12] + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r0 + orrne r2, sl, r0 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L11797: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L11814 + ands r0, r2, #255 + beq .L11816 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L11816: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L11820 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L11820: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L11824 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L11824: + movs r2, r2, lsr #24 + beq .L11814 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L11814: + add lr, lr, #1 + cmp lr, r5 + add ip, ip, #64 + add r1, r1, #32 + bne .L11796 + add r7, r7, r5, asl #6 + add r4, r4, r5, asl #5 +.L11794: + ands r5, r6, #7 + beq .L11219 + cmp r5, #3 + ldrls ip, [r7, #0] + bls .L11853 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L11835 + ands r1, r2, #255 + beq .L11837 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #20] + ldreq lr, [sp, #20] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L11837: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L11841 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r0, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L11841: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L11845 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L11845: + movs r1, r2, lsr #24 + beq .L11835 + ldr r2, [r4, #12] + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r1 + orrne r2, sl, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L11835: + subs r5, r5, #4 + ldr ip, [r7, #4] + addne r4, r4, #16 + beq .L11219 +.L11853: + mov lr, #0 +.L11854: + ands r3, ip, #255 + beq .L11855 + ldr r2, [r4, #0] + ldr r0, [sp, #20] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r4, #0] + streq r1, [r4, #0] +.L11855: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, lsr #8 + add r4, r4, #4 + bhi .L11854 + b .L11219 +.L12435: + .align 2 +.L12434: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word obj_width_table + .word obj_height_table + .word oam_ram + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L11299: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r5, r2, asr #3 + mov r3, r3, asr #3 + mov r1, ip, lsr #3 + mla r0, r5, r1, r3 + ldr sl, [sp, #28] + and r3, ip, #7 + mov r2, sl, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + add r3, r3, r2, asl #2 + ldr fp, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L12434+24 + cmp r6, fp + add ip, r0, r3 + bge .L12045 + rsb r0, r6, fp + rsb r8, r0, r7 + cmp r8, #0 + ble .L11219 + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bhi .L12048 + mov r3, r0, lsr #3 + ands lr, r0, #7 + sub r8, ip, r3, asl #6 + bne .L12050 + ldr r7, [sp, #92] + ldr r4, [sp, #68] +.L12052: + movs r6, r7, lsr #3 + beq .L12130 + mov r0, r4 + mov lr, r8 + mov r5, #0 +.L12132: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L12133 + ands r1, r2, #255 + beq .L12135 + ldr r3, [r0, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12135: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L12139 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12139: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L12143 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12143: + movs r2, r2, lsr #24 + beq .L12133 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12133: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L12150 + ands ip, r1, #255 + beq .L12152 + ldr r2, [r0, #28] + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12152: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L12156 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12156: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L12160 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12160: + movs r1, r1, lsr #24 + beq .L12150 + ldr r2, [r0, #16] + tst r2, #256 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, ip, r1 + orrne r2, fp, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12150: + add r5, r5, #1 + cmp r5, r6 + sub lr, lr, #64 + add r0, r0, #32 + bne .L12132 + rsb r3, r6, r6, asl #26 + add r8, r8, r3, asl #6 + add r4, r4, r6, asl #5 +.L12130: + ands r5, r7, #7 + beq .L11219 + cmp r5, #3 + ldrls ip, [r8, #4] + bls .L12189 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L12171 + ands r1, r2, #255 + beq .L12173 + ldr r3, [r4, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r0, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r0, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L12173: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L12177 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L12177: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L12181 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L12181: + movs r2, r2, lsr #24 + beq .L12171 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L12171: + subs r5, r5, #4 + ldr ip, [r8, #0] + addne r4, r4, #16 + beq .L11219 +.L12189: + mov lr, #0 +.L12190: + movs r3, ip, lsr #24 + beq .L12191 + ldr r2, [r4, #0] + ldr r0, [sp, #20] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r4, #0] + streq r1, [r4, #0] +.L12191: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, asl #8 + add r4, r4, #4 + bhi .L12190 + b .L11219 +.L11212: + ldr ip, .L12434+20 + mov r3, r4, lsr #4 + add r2, r7, r7, lsr #31 + and r3, r3, #992 + tst lr, #512 + add r3, r3, ip + mov lr, r2, asr #1 + add r1, r9, r9, lsr #31 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + ldrh sl, [r3, #30] + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r7 + moveq r5, lr + moveq ip, r4 + movne fp, r7, asl #1 + movne r5, lr, asl #1 + movne ip, r4, asl #1 + cmp r6, r2 + str r3, [sp, #16] + bge .L11254 + rsb r2, r6, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L11219 + ldr r6, [sp, #8] + rsb r5, r2, r5 +.L11254: + ldr r2, [sp, #4] + add r3, r6, fp + cmp r3, r2 + blt .L11257 + rsb fp, r6, r2 + cmp fp, #0 + ble .L11219 +.L11257: + mov r3, r8, asl #16 + mov r2, r1, asl #16 + ldr r8, [sp, #16] + mov r1, sl, asl #16 + ldr sl, [sp, #28] + mov lr, lr, asl #8 + add ip, r0, ip + cmp r8, #0 + mov r0, sl, lsr #8 + mov r8, r1, asr #16 + str lr, [sp, #88] + ldr r1, [sp, #32] + ldr lr, [sp, #0] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + and r0, r0, #240 + add sl, lr, r6, asl #2 + str r3, [sp, #52] + str r2, [sp, #56] + mov r4, r4, asl #8 + rsb lr, ip, r1 + str r0, [sp, #84] + bne .L11259 + mla r3, lr, r8, r4 + mov r0, r3, asr #8 + cmp r0, r9 + bcs .L11219 + ldr r4, [sp, #28] + cmp r7, #0 + add r3, r7, #7 + mov r2, r4, asl #22 + movge r3, r7 + mov r3, r3, asr #3 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L12434+24 + add r0, r0, ip, asl #3 + cmp fp, #0 + add r6, r3, r0, asl #2 + ble .L11219 + ldr r3, [sp, #56] + ldr r2, [sp, #52] + mul r3, lr, r3 + mul r2, r5, r2 + ldr r5, [sp, #88] + rsb r3, r2, r3 + add ip, r5, r3 + mov r1, ip, asr #8 + cmp r1, r7 + ldrcc r4, [sp, #16] + ldrcs r4, [sp, #16] + bcs .L11266 + b .L12397 +.L11267: + cmp r7, r2 + bhi .L11268 +.L11266: + ldr r8, [sp, #52] + add r4, r4, #1 + add ip, ip, r8 + cmp fp, r4 + mov r2, ip, asr #8 + add sl, sl, #4 + bne .L11267 + b .L11219 +.L12381: + add sp, sp, #96 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L11223: + ldr r0, [sp, #28] + cmp r7, #0 + add r1, r7, #7 + mov r2, r0, asl #22 + movge r1, r7 + ldr r3, .L12434+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp r8, #0 + str r2, [sp, #76] + str r1, [sp, #48] + ble .L11219 + ldr r1, [sp, #12] + mul r2, lr, ip + mov r3, r1, asl #16 + mov r6, r3, asr #16 + ldr r3, [sp, #44] + mul r1, r6, fp + mul r0, sl, fp + mul r3, lr, r3 + ldr fp, [sp, #80] + rsb r3, r0, r3 + rsb r2, r1, r2 + add ip, fp, r3 + add lr, r4, r2 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + cmp r1, r7 + cmpcc r0, r9 + movcs r3, #0 + movcc r3, #1 + movcs r4, r3 + bcs .L11241 + b .L12432 +.L11242: + cmp r7, r1 + cmphi r9, r0 + bhi .L11244 +.L11241: + add r4, r4, #1 + add ip, ip, sl + add lr, lr, r6 + cmp r8, r4 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + add r5, r5, #4 + bne .L11242 + b .L11219 +.L12410: + and r3, r0, #7 + mov r2, r1, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + ldr r2, [sp, #76] + and r1, r1, #7 + add r3, r3, r2 + mov r2, r0, asr #3 + ldr r0, [sp, #48] + mla r0, r2, r0, r3 + ldrb r0, [r0, r1] @ zero_extendqisi2 + cmp r0, #0 + beq .L11247 + ldr r3, [r5, #0] + ldr fp, [sp, #20] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r2, fp, r2 + orr r1, fp, r3, asl #16 + tst r3, #256 + orr r2, r0, r2 + orr r1, r0, r1 + strne r2, [r5, #0] + streq r1, [r5, #0] +.L11247: + add r4, r4, #1 + add ip, ip, sl + add lr, lr, r6 + cmp r8, r4 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + add r5, r5, #4 + ble .L11219 +.L11244: + cmp r9, r0 + cmphi r7, r1 + bhi .L12410 + b .L11219 +.L11259: + ldr r3, [sp, #28] + cmp r7, #0 + add r1, r7, #7 + mov r2, r3, asl #22 + movge r1, r7 + ldr r3, .L12434+24 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp fp, #0 + str r2, [sp, #72] + str r1, [sp, #64] + ble .L11219 + ldr r6, [sp, #16] + ldr r0, [sp, #52] + mov r3, r6, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #60] + ldr r1, [sp, #60] + ldr r3, [sp, #56] + mul r2, lr, r8 + mul r1, r5, r1 + mul r0, r5, r0 + mul r3, lr, r3 + ldr r8, [sp, #88] + rsb r2, r1, r2 + rsb r3, r0, r3 + add r6, r8, r3 + add r5, r4, r2 + mov r3, r5, asr #8 + mov r4, r6, asr #8 + cmp r4, r7 + cmpcc r3, r9 + movcs r2, #0 + movcc r2, #1 + movcs r8, r2 + bcs .L11281 + b .L12433 +.L11282: + cmp r7, r4 + cmphi r9, r3 + bhi .L11284 +.L11281: + ldr ip, [sp, #52] + ldr lr, [sp, #60] + add r8, r8, #1 + add r6, r6, ip + add r5, r5, lr + cmp fp, r8 + mov r4, r6, asr #8 + mov r3, r5, asr #8 + add sl, sl, #4 + bne .L11282 + b .L11219 +.L12412: + ldr r2, [sp, #64] + and r0, r3, #7 + and ip, r3, #7 + mov r3, r3, asr #3 + mul r2, r3, r2 + ldr r3, [sp, #72] + ldr r1, [sp, #72] + add ip, r3, ip, asl #2 + mov r3, r4, asr #3 + add r0, r1, r0, asl #2 + mov lr, r4, asr #1 + mov r1, r4, asr #1 + add r2, r2, r3, asl #5 + tst r4, #1 + add r3, r0, r2 + and lr, lr, #3 + add r0, ip, r2 + and r1, r1, #3 + ldreqb r3, [r0, r1] @ zero_extendqisi2 + ldrneb r3, [r3, lr] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + ldr r4, [sp, #84] + cmp r0, #0 + orr r0, r0, r4 + beq .L11290 + ldr r2, [sl, #0] + ldr ip, [sp, #20] + mov r3, r2, lsr #16 + orr r1, ip, r0 + mov r3, r3, asl #16 + orr r0, ip, r0 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [sl, #0] + streq r0, [sl, #0] +.L11290: + ldr lr, [sp, #52] + ldr r0, [sp, #60] + add r8, r8, #1 + add r6, r6, lr + add r5, r5, r0 + cmp fp, r8 + add sl, sl, #4 + mov r4, r6, asr #8 + mov r3, r5, asr #8 + ble .L11219 +.L11284: + cmp r9, r3 + cmphi r7, r4 + bhi .L12412 + b .L11219 +.L11269: + cmp r7, r1 + bls .L11219 +.L12397: + mov r3, r1, asr #1 + and lr, r3, #3 + mov r3, r1, asr #3 + mov r3, r3, asl #5 + mov r2, r1, asr #1 + tst r1, #1 + and r0, r2, #3 + add r1, r3, r6 + add r2, r3, r6 + ldreqb r3, [r2, r0] @ zero_extendqisi2 + ldrneb r3, [r1, lr] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + ldr r9, [sp, #84] + cmp r2, #0 + orr r3, r2, r9 + beq .L11274 + ldr r2, [sl, #0] + ldr lr, [sp, #20] + tst r2, #256 + orr r1, lr, r3 + orr r0, lr, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r1, r3, r1 + orr r3, r0, r2, asl #16 + strne r1, [sl, #0] + streq r3, [sl, #0] +.L11274: + ldr r0, [sp, #52] + add r4, r4, #1 + add ip, ip, r0 + cmp fp, r4 + add sl, sl, #4 + mov r1, ip, asr #8 + bgt .L11269 + b .L11219 +.L11232: + cmp r7, r2 + bls .L11219 +.L12395: + mov r3, r2, asr #3 + add r3, r6, r3, asl #6 + and r2, r2, #7 + ldrb ip, [r3, r2] @ zero_extendqisi2 + cmp ip, #0 + beq .L11234 + ldr r3, [r5, #0] + ldr fp, [sp, #20] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r2, fp, r2 + orr r1, fp, r3, asl #16 + orr r4, ip, r2 + tst r3, #256 + orr r2, ip, r1 + strne r4, [r5, #0] + streq r2, [r5, #0] +.L11234: + add lr, lr, #1 + add r0, r0, sl + cmp r8, lr + add r5, r5, #4 + mov r2, r0, asr #8 + bgt .L11232 + b .L11219 +.L12045: + add r3, r6, r7 + ldr r7, [sp, #4] + cmp r3, r7 + bcs .L12413 + cmp r5, #0 + beq .L11219 + ldr r2, [sp, #0] + ldr r3, .L12434+28 + add r1, r2, r6, asl #2 + add r0, r0, r3 + mov r6, #0 + b .L12345 +.L12414: + sub ip, ip, #64 + add r1, r1, #32 +.L12345: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L12346 + ands lr, r2, #255 + beq .L12348 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L12348: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L12352 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L12352: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L12356 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L12356: + movs r2, r2, lsr #24 + beq .L12346 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r4, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r4, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L12346: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L12363 + ands r4, lr, #255 + beq .L12365 + ldr r2, [r1, #28] + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r8, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r7, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L12365: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L12369 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L12369: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L12373 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq r4, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, r4, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L12373: + movs lr, lr, lsr #24 + beq .L12363 + ldr r2, [r1, #16] + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r8, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L12363: + add r6, r6, #1 + cmp r5, r6 + sub r0, r0, #64 + bne .L12414 + b .L11219 +.L11709: + add r3, r6, r7 + ldr r7, [sp, #4] + cmp r7, r3 + bls .L12415 + cmp r4, #0 + beq .L11219 + ldr fp, [sp, #0] + ldr r3, .L12434+32 + add r1, fp, r6, asl #2 + add r0, r0, r3 + mov r5, #0 + b .L12009 +.L12416: + add ip, ip, #64 + add r1, r1, #32 +.L12009: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L12010 + ands lr, r2, #255 + beq .L12012 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L12012: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L12016 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L12016: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L12020 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L12020: + movs lr, r2, lsr #24 + beq .L12010 + ldr r2, [r1, #12] + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, lr + orrne r2, r6, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L12010: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L12027 + ands lr, r2, #255 + beq .L12029 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L12029: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L12033 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L12033: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L12037 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L12037: + movs r2, r2, lsr #24 + beq .L12027 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L12027: + add r5, r5, #1 + cmp r4, r5 + add r0, r0, #64 + bne .L12416 + b .L11219 +.L11505: + ldr r1, [sp, #4] + add r3, r6, r7 + cmp r1, r3 + bls .L12417 + cmp r5, #0 + beq .L11219 + ldr fp, [sp, #0] + mov ip, #0 + add r1, fp, r6, asl #2 + b .L11674 +.L12418: + sub r0, r0, #32 + add r1, r1, #32 +.L11674: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L11675 + ands r3, lr, #15 + beq .L11677 + ldr r2, [r1, #28] + orr r4, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, r4 + orrne r2, r6, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L11677: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L11681 + ldr r2, [r1, #24] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L11681: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L11685 + ldr r2, [r1, #20] + orr r4, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, r4 + orrne r2, fp, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L11685: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L11689 + ldr r2, [r1, #16] + orr r4, r8, r3 + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r4 + orrne r2, r7, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L11689: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L11693 + ldr r2, [r1, #12] + orr r4, r8, r3 + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, sl, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L11693: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L11697 + ldr r2, [r1, #8] + orr r4, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, r4 + orrne r2, r6, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L11697: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L11701 + ldr r2, [r1, #4] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L11701: + movs r3, lr, lsr #28 + beq .L11675 + ldr r2, [r1, #0] + orr lr, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r4, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r4, lr + orrne r2, fp, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L11675: + add ip, ip, #1 + cmp r5, ip + bne .L12418 + b .L11219 +.L11301: + ldr lr, [sp, #4] + add r3, r6, r7 + cmp lr, r3 + bls .L12419 + cmp r5, #0 + beq .L11219 + ldr fp, [sp, #0] + mov ip, #0 + add r1, fp, r6, asl #2 + b .L11470 +.L12420: + add r0, r0, #32 + add r1, r1, #32 +.L11470: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L11471 + ands r3, lr, #15 + beq .L11473 + ldr r2, [r1, #0] + orr r4, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, r4 + orrne r2, r6, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L11473: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L11477 + ldr r2, [r1, #4] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L11477: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L11481 + ldr r2, [r1, #8] + orr r4, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, r4 + orrne r2, fp, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L11481: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L11485 + ldr r2, [r1, #12] + orr r4, r8, r3 + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r4 + orrne r2, r7, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L11485: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L11489 + ldr r2, [r1, #16] + orr r4, r8, r3 + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, sl, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L11489: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L11493 + ldr r2, [r1, #20] + orr r4, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, r4 + orrne r2, r6, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L11493: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L11497 + ldr r2, [r1, #24] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L11497: + movs r3, lr, lsr #28 + beq .L11471 + ldr r2, [r1, #28] + orr lr, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r4, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r4, lr + orrne r2, fp, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L11471: + add ip, ip, #1 + cmp r5, ip + bne .L12420 + b .L11219 +.L12407: + add sp, sp, #96 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_color32_1D +.L12419: + rsb ip, r6, lr + cmp ip, #0 + ble .L11219 + ldr r1, [sp, #0] + movs sl, ip, lsr #3 + add r7, r1, r6, asl #2 + beq .L11425 + mov r4, r7 + mov r6, r0 + mov r1, #0 +.L11427: + ldr lr, [r6, #0] + cmp lr, #0 + beq .L11428 + ands r3, lr, #15 + beq .L11430 + ldr r2, [r4, #0] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L11430: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L11434 + ldr r2, [r4, #4] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L11434: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L11438 + ldr r2, [r4, #8] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L11438: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L11442 + ldr r2, [r4, #12] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L11442: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L11446 + ldr r2, [r4, #16] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L11446: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L11450 + ldr r2, [r4, #20] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L11450: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L11454 + ldr r2, [r4, #24] + orr r5, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L11454: + movs r3, lr, lsr #28 + beq .L11428 + ldr r2, [r4, #28] + orr lr, r8, r3 + tst r2, #256 + ldrne r5, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r5, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L11428: + add r1, r1, #1 + cmp sl, r1 + add r6, r6, #32 + add r4, r4, #32 + bne .L11427 + mov r3, sl, asl #5 + add r0, r0, r3 + add r7, r7, r3 +.L11425: + ands r4, ip, #7 + beq .L11219 + ldr ip, [r0, #0] + mov lr, #0 +.L11463: + ands r3, ip, #15 + beq .L11464 + ldr r1, [r7, #0] + ldr sl, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r7, #0] + streq r2, [r7, #0] +.L11464: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, lsr #4 + add r7, r7, #4 + bne .L11463 + b .L11219 +.L12417: + rsb sl, r6, r1 + cmp sl, #0 + ble .L11219 + ldr r2, [sp, #0] + movs r7, sl, lsr #3 + add r6, r2, r6, asl #2 + beq .L11629 + mov lr, r6 + mov r5, r0 + mov ip, #0 +.L11631: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L11632 + ands r3, r1, #15 + beq .L11634 + ldr r2, [lr, #28] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #28] + streq r3, [lr, #28] +.L11634: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L11638 + ldr r2, [lr, #24] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #24] + streq r3, [lr, #24] +.L11638: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L11642 + ldr r2, [lr, #20] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #20] + streq r3, [lr, #20] +.L11642: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L11646 + ldr r2, [lr, #16] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #16] + streq r3, [lr, #16] +.L11646: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L11650 + ldr r2, [lr, #12] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L11650: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L11654 + ldr r2, [lr, #8] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L11654: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L11658 + ldr r2, [lr, #4] + orr r4, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L11658: + movs r3, r1, lsr #28 + beq .L11632 + ldr r2, [lr, #0] + orr r1, r8, r3 + tst r2, #256 + ldrne r4, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, r4, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L11632: + add ip, ip, #1 + cmp r7, ip + sub r5, r5, #32 + add lr, lr, #32 + bne .L11631 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r6, r6, r7, asl #5 +.L11629: + ands r4, sl, #7 + beq .L11219 + ldr ip, [r0, #0] + mov lr, #0 +.L11667: + movs r3, ip, lsr #28 + beq .L11668 + ldr r1, [r6, #0] + ldr sl, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r6, #0] + streq r2, [r6, #0] +.L11668: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r6, r6, #4 + bne .L11667 + b .L11219 +.L12415: + rsb r8, r6, r7 + cmp r8, #0 + ble .L11219 + ldr r9, [sp, #0] + movs r7, r8, lsr #3 + add r6, r9, r6, asl #2 + beq .L11942 + ldr r3, .L12436 + mov lr, r6 + add r0, r0, r3 + mov r5, ip + mov r1, #0 +.L11944: + ldr r2, [r5, #0] + cmp r2, #0 + beq .L11945 + ands r4, r2, #255 + beq .L11947 + ldr r3, [lr, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L11947: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L11951 + ldr r3, [lr, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L11951: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L11955 + ldr r3, [lr, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L11955: + movs r4, r2, lsr #24 + beq .L11945 + ldr r2, [lr, #12] + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r4 + orrne r2, sl, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L11945: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L11962 + ands r4, r2, #255 + beq .L11964 + ldr r3, [lr, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #16] + streq r3, [lr, #16] +.L11964: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L11968 + ldr r3, [lr, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #20] + streq r3, [lr, #20] +.L11968: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L11972 + ldr r3, [lr, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #24] + streq r3, [lr, #24] +.L11972: + movs r2, r2, lsr #24 + beq .L11962 + ldr r3, [lr, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [lr, #28] + streq r3, [lr, #28] +.L11962: + add r1, r1, #1 + cmp r7, r1 + add r5, r5, #64 + add lr, lr, #32 + add r0, r0, #64 + bne .L11944 + add ip, ip, r7, asl #6 + add r6, r6, r7, asl #5 +.L11942: + ands r4, r8, #7 + beq .L11219 + cmp r4, #3 + ldrls ip, [ip, #0] + bls .L12001 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L11983 + ands r1, r2, #255 + beq .L11985 + ldr r3, [r6, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L11985: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L11989 + ldr r3, [r6, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r0, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r0, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L11989: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L11993 + ldr r3, [r6, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L11993: + movs r1, r2, lsr #24 + beq .L11983 + ldr r2, [r6, #12] + tst r2, #256 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, r8, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L11983: + subs r4, r4, #4 + ldr ip, [ip, #4] + addne r6, r6, #16 + beq .L11219 +.L12001: + mov lr, #0 +.L12002: + ands r3, ip, #255 + beq .L12003 + ldr r2, [r6, #0] + ldr sl, [sp, #20] + tst r2, #256 + orr r1, sl, r3 + orr r0, sl, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r6, #0] + streq r1, [r6, #0] +.L12003: + add lr, lr, #1 + cmp lr, r4 + mov ip, ip, lsr #8 + add r6, r6, #4 + bcc .L12002 + b .L11219 +.L12413: + rsb sl, r6, r7 + cmp sl, #0 + ble .L11219 + ldr r9, [sp, #0] + movs r8, sl, lsr #3 + add r7, r9, r6, asl #2 + beq .L12278 + ldr r3, .L12436+4 + mov r4, r7 + add r0, r0, r3 + mov r6, ip + mov r1, #0 +.L12280: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L12281 + ands lr, r2, #255 + beq .L12283 + ldr r3, [r4, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, r5, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L12283: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L12287 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, fp, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L12287: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L12291 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L12291: + movs r2, r2, lsr #24 + beq .L12281 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq lr, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L12281: + ldr lr, [r6, #0] + cmp lr, #0 + beq .L12298 + ands r5, lr, #255 + beq .L12300 + ldr r2, [r4, #28] + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L12300: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L12304 + ldr r3, [r4, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L12304: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L12308 + ldr r3, [r4, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L12308: + movs lr, lr, lsr #24 + beq .L12298 + ldr r2, [r4, #16] + tst r2, #256 + ldrne r9, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L12298: + add r1, r1, #1 + cmp r8, r1 + sub r6, r6, #64 + add r4, r4, #32 + sub r0, r0, #64 + bne .L12280 + rsb r3, r8, r8, asl #26 + add ip, ip, r3, asl #6 + add r7, r7, r8, asl #5 +.L12278: + ands r4, sl, #7 + beq .L11219 + cmp r4, #3 + ldrls ip, [ip, #4] + bls .L12337 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L12319 + ands r1, r2, #255 + beq .L12321 + ldr r3, [r7, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r0, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r0, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #12] + streq r3, [r7, #12] +.L12321: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L12325 + ldr r3, [r7, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #8] + streq r3, [r7, #8] +.L12325: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L12329 + ldr r3, [r7, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #4] + streq r3, [r7, #4] +.L12329: + movs r2, r2, lsr #24 + beq .L12319 + ldr r3, [r7, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r7, #0] + streq r3, [r7, #0] +.L12319: + subs r4, r4, #4 + ldr ip, [ip, #0] + addne r7, r7, #16 + beq .L11219 +.L12337: + mov lr, #0 +.L12338: + movs r3, ip, lsr #24 + beq .L12339 + ldr r2, [r7, #0] + ldr r0, [sp, #20] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r7, #0] + streq r1, [r7, #0] +.L12339: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #8 + add r7, r7, #4 + bhi .L12338 + b .L11219 +.L12048: + mov r3, r0, lsr #3 + ands r2, r0, #7 + sub r4, ip, r3, asl #6 + ldreq r0, [sp, #68] + beq .L12198 + cmp r2, #3 + rsb r6, r2, #8 + bhi .L12421 + subs r7, r6, #4 + ldr r1, [r4, #4] + ldreq r1, [sp, #68] + beq .L12213 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #68] + mov r5, #0 +.L12214: + movs r3, ip, lsr #24 + beq .L12215 + ldr r2, [lr, #0] + ldr r9, [sp, #20] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12215: + add r5, r5, #1 + cmp r7, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12214 + ldr sl, [sp, #68] + add r3, sl, r6, asl #2 + sub r1, r3, #16 +.L12213: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L12221 + ands r0, r2, #255 + beq .L12223 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L12223: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L12227 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L12227: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L12231 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L12231: + movs r2, r2, lsr #24 + beq .L12221 + ldr r3, [r1, #0] + tst r3, #256 + beq .L12236 + mov r3, r3, lsr #16 + ldr r9, [sp, #20] + mov r3, r3, asl #16 + orr r3, r9, r3 + orr r3, r2, r3 + str r3, [r1, #0] +.L12221: + add r0, r1, #16 +.L12203: + sub r4, r4, #64 +.L12198: + movs r5, r8, lsr #3 + beq .L11219 + mov lr, #0 + b .L12239 +.L12422: + sub r4, r4, #64 + add r0, r0, #32 +.L12239: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L12240 + ands r1, r2, #255 + beq .L12242 + ldr r3, [r0, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12242: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L12246 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #20] + ldreq r8, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12246: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L12250 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12250: + movs r2, r2, lsr #24 + beq .L12240 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12240: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L12257 + ands ip, r1, #255 + beq .L12259 + ldr r2, [r0, #28] + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, ip + orrne r2, r6, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12259: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L12263 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12263: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L12267 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12267: + movs r1, r1, lsr #24 + beq .L12257 + ldr r2, [r0, #16] + tst r2, #256 + ldrne ip, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, r1 + orrne r2, ip, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12257: + add lr, lr, #1 + cmp lr, r5 + bne .L12422 + b .L11219 +.L11712: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r4, ip, r3, asl #6 + ldreq r1, [sp, #68] + beq .L11862 + cmp r2, #3 + rsb r6, r2, #8 + bhi .L12423 + subs r7, r6, #4 + ldr r1, [r4, #0] + ldreq r1, [sp, #68] + beq .L11877 + mov r3, r2, asl #3 + mov ip, r1, lsr r3 + ldr lr, [sp, #68] + mov r5, #0 +.L11878: + ands r3, ip, #255 + beq .L11879 + ldr r2, [lr, #0] + ldr r9, [sp, #20] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11879: + add r5, r5, #1 + cmp r7, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11878 + ldr sl, [sp, #68] + add r3, sl, r6, asl #2 + sub r1, r3, #16 +.L11877: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L11885 + ands r0, r2, #255 + beq .L11887 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L11887: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L11891 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L11891: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L11895 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L11895: + movs r2, r2, lsr #24 + beq .L11885 + ldr r3, [r1, #12] + tst r3, #256 + beq .L11900 + mov r3, r3, lsr #16 + ldr r9, [sp, #20] + mov r3, r3, asl #16 + orr r3, r9, r3 + orr r3, r2, r3 + str r3, [r1, #12] +.L11885: + add r1, r1, #16 +.L11867: + add r4, r4, #64 +.L11862: + movs lr, r8, lsr #3 + beq .L11219 + mov ip, #0 + b .L11903 +.L12424: + add r4, r4, #64 + add r1, r1, #32 +.L11903: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L11904 + ands r0, r2, #255 + beq .L11906 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L11906: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L11910 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #20] + ldreq r8, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L11910: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L11914 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L11914: + movs r0, r2, lsr #24 + beq .L11904 + ldr r2, [r1, #12] + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r5, r0 + orrne r2, fp, r0 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L11904: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L11921 + ands r0, r2, #255 + beq .L11923 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L11923: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L11927 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L11927: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L11931 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L11931: + movs r2, r2, lsr #24 + beq .L11921 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r0, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L11921: + add ip, ip, #1 + cmp ip, lr + bne .L12424 + b .L11219 +.L11508: + ands r2, lr, #7 + mov r3, lr, lsr #3 + sub ip, r0, r3, asl #5 + ldreq r0, [sp, #68] + beq .L11579 + rsbs r6, r2, #8 + ldr r1, [ip, #0] + ldreq r0, [sp, #68] + beq .L11582 + mov r3, r2, asl #2 + mov lr, r1, asl r3 + ldr r4, [sp, #68] + mov r5, #0 +.L11583: + movs r3, lr, lsr #28 + beq .L11584 + ldr r1, [r4, #0] + ldr fp, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, fp, r2 + mov r3, r3, asl #16 + orr r2, fp, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L11584: + add r5, r5, #1 + cmp r5, r6 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L11583 + ldr lr, [sp, #68] + add r0, lr, r6, asl #2 +.L11582: + sub ip, ip, #32 +.L11579: + movs r5, sl, lsr #3 + beq .L11219 + mov r4, #0 + b .L11591 +.L12437: + .align 2 +.L12436: + .word vram+65600 + .word vram+65472 +.L12425: + sub ip, ip, #32 + add r0, r0, #32 +.L11591: + ldr r1, [ip, #0] + cmp r1, #0 + beq .L11592 + ands r3, r1, #15 + beq .L11594 + ldr r2, [r0, #28] + orr lr, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, lr + orrne r2, r6, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L11594: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L11598 + ldr r2, [r0, #24] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L11598: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L11602 + ldr r2, [r0, #20] + orr lr, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, lr + orrne r2, fp, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L11602: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L11606 + ldr r2, [r0, #16] + orr lr, r8, r3 + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L11606: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L11610 + ldr r2, [r0, #12] + orr lr, r8, r3 + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, lr + orrne r2, sl, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L11610: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L11614 + ldr r2, [r0, #8] + orr lr, r8, r3 + tst r2, #256 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, lr + orrne r2, r6, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L11614: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L11618 + ldr r2, [r0, #4] + orr lr, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L11618: + movs r3, r1, lsr #28 + beq .L11592 + ldr r2, [r0, #0] + orr r1, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq lr, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, lr, r1 + orrne r2, fp, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L11592: + add r4, r4, #1 + cmp r5, r4 + bne .L12425 + b .L11219 +.L11304: + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add r6, r0, r1 + ldreq r0, [sp, #68] + beq .L11375 + rsbs r7, r3, #8 + ldr r0, [r0, r1] + ldreq r0, [sp, #68] + beq .L11378 + mov r3, r3, asl #2 + mov ip, r0, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11379: + ands r3, ip, #15 + beq .L11380 + ldr r1, [lr, #0] + ldr fp, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, fp, r2 + mov r3, r3, asl #16 + orr r2, fp, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L11380: + add r4, r4, #1 + cmp r7, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L11379 + ldr ip, [sp, #68] + add r0, ip, r7, asl #2 +.L11378: + add r6, r6, #32 +.L11375: + movs r4, r5, lsr #3 + beq .L11219 + mov lr, #0 + b .L11387 +.L12426: + add r6, r6, #32 + add r0, r0, #32 +.L11387: + ldr r1, [r6, #0] + cmp r1, #0 + beq .L11388 + ands r3, r1, #15 + beq .L11390 + ldr r2, [r0, #0] + orr ip, r8, r3 + tst r2, #256 + ldrne r5, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, ip + orrne r2, r5, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L11390: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L11394 + ldr r2, [r0, #4] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L11394: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L11398 + ldr r2, [r0, #8] + orr ip, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq r5, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r5, ip + orrne r2, fp, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L11398: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L11402 + ldr r2, [r0, #12] + orr ip, r8, r3 + tst r2, #256 + ldrne r7, [sp, #20] + ldreq r9, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L11402: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L11406 + ldr r2, [r0, #16] + orr ip, r8, r3 + tst r2, #256 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, fp, ip + orrne r2, sl, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L11406: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L11410 + ldr r2, [r0, #20] + orr ip, r8, r3 + tst r2, #256 + ldrne r5, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r7, ip + orrne r2, r5, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L11410: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L11414 + ldr r2, [r0, #24] + orr ip, r8, r3 + tst r2, #256 + ldrne r9, [sp, #20] + ldreq sl, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L11414: + movs r3, r1, lsr #28 + beq .L11388 + ldr r2, [r0, #28] + orr r1, r8, r3 + tst r2, #256 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, ip, r1 + orrne r2, fp, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L11388: + add lr, lr, #1 + cmp r4, lr + bne .L12426 + b .L11219 +.L11268: + mov r1, r2 + b .L12397 +.L11510: + ldr lr, [sp, #92] + rsb r6, r4, #8 + cmp lr, r6 + blt .L12427 + cmp r6, #0 + ldr r2, [ip, #0] + ldreq r5, [sp, #68] + beq .L11525 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + ldr r4, [sp, #68] + mov r5, #0 +.L11526: + movs r3, lr, lsr #28 + beq .L11527 + ldr r1, [r4, #0] + ldr r7, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, r7, r2 + mov r3, r3, asl #16 + orr r2, r7, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L11527: + add r5, r5, #1 + cmp r6, r5 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L11526 + ldr r9, [sp, #68] + add r5, r9, r6, asl #2 +.L11525: + ldr fp, [sp, #92] + sub ip, ip, #32 + rsb sl, r6, fp + b .L11512 +.L12050: + ldr r0, [sp, #92] + rsb r5, lr, #8 + cmp r0, r5 + blt .L12428 + cmp lr, #3 + bls .L12091 + cmp r5, #0 + ldr r2, [r8, #0] + ldreq r4, [sp, #68] + beq .L12095 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #68] + mov r4, #0 +.L12096: + movs r3, ip, lsr #24 + beq .L12097 + ldr r2, [lr, #0] + ldr r7, [sp, #20] + tst r2, #256 + orr r1, r7, r3 + orr r0, r7, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12097: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12096 + ldr sl, [sp, #68] + add r4, sl, r5, asl #2 +.L12095: + ldr ip, [sp, #92] + sub r8, r8, #64 + rsb r7, r5, ip + b .L12052 +.L11714: + ldr sl, [sp, #92] + rsb r5, lr, #8 + cmp sl, r5 + blt .L12429 + cmp lr, #3 + bls .L11755 + cmp r5, #0 + ldr r2, [r7, #4] + ldreq r4, [sp, #68] + beq .L11759 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11760: + ands r3, ip, #255 + beq .L11761 + ldr r2, [lr, #0] + ldr r6, [sp, #20] + tst r2, #256 + orr r1, r6, r3 + orr r0, r6, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11761: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11760 + ldr r9, [sp, #68] + add r4, r9, r5, asl #2 +.L11759: + ldr fp, [sp, #92] + add r7, r7, #64 + rsb r6, r5, fp + b .L11716 +.L11306: + ldr fp, [sp, #92] + rsb r5, r3, #8 + cmp fp, r5 + blt .L12430 + cmp r5, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #68] + beq .L11321 + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11322: + ands r3, ip, #15 + beq .L11323 + ldr r1, [lr, #0] + ldr r7, [sp, #20] + orr r2, r8, r3 + mov r3, r1, lsr #16 + orr r0, r7, r2 + mov r3, r3, asl #16 + orr r2, r7, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L11323: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L11322 + ldr r9, [sp, #68] + add r4, r9, r5, asl #2 +.L11321: + ldr fp, [sp, #92] + add r6, r6, #32 + rsb sl, r5, fp + b .L11308 +.L12423: + cmp r6, #0 + ldr r1, [r4, #4] + ldreq r1, [sp, #68] + beq .L11867 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, lsr r3 + ldr lr, [sp, #68] + mov r5, #0 +.L11868: + ands r3, ip, #255 + beq .L11869 + ldr r2, [lr, #0] + ldr r7, [sp, #20] + tst r2, #256 + orr r1, r7, r3 + orr r0, r7, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11869: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11868 + ldr sl, [sp, #68] + add r4, r4, #64 + add r1, sl, r6, asl #2 + b .L11862 +.L12430: + cmp fp, #0 + ble .L11219 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11313: + ands r3, ip, #15 + beq .L11314 + ldr r1, [lr, #0] + orr r2, r8, r3 + ldr r3, [sp, #20] + ldr r5, [sp, #20] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r5, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L11314: + ldr r6, [sp, #92] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L11313 + b .L11219 +.L12421: + cmp r6, #0 + ldr r1, [r4, #0] + ldreq r0, [sp, #68] + beq .L12203 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #68] + mov r5, #0 +.L12204: + movs r3, ip, lsr #24 + beq .L12205 + ldr r2, [lr, #0] + ldr r7, [sp, #20] + tst r2, #256 + orr r1, r7, r3 + orr r0, r7, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12205: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12204 + ldr sl, [sp, #68] + sub r4, r4, #64 + add r0, sl, r6, asl #2 + b .L12198 +.L12428: + cmp r0, #0 + ble .L11219 + cmp lr, #3 + bls .L12056 + mov r3, lr, asl #3 + ldr r2, [r8, #0] + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #68] + mov r4, #0 +.L12059: + movs r3, ip, lsr #24 + beq .L12060 + ldr r2, [lr, #0] + ldr r5, [sp, #20] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12060: + ldr r6, [sp, #92] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12059 + b .L11219 +.L12429: + cmp sl, #0 + ble .L11219 + cmp lr, #3 + bls .L11720 + mov r3, lr, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11723: + ands r3, ip, #255 + beq .L11724 + ldr r2, [lr, #0] + ldr fp, [sp, #20] + tst r2, #256 + orr r1, fp, r3 + orr r0, fp, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11724: + ldr r0, [sp, #92] + add r4, r4, #1 + cmp r0, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11723 + b .L11219 +.L12427: + cmp lr, #0 + ble .L11219 + ldr r2, [ip, #0] + mov r3, r4, asl #2 + mov ip, r2, asl r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11517: + movs r3, ip, lsr #28 + beq .L11518 + ldr r1, [lr, #0] + orr r2, r8, r3 + ldr r3, [sp, #20] + ldr r5, [sp, #20] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r5, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L11518: + ldr r6, [sp, #92] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #4 + add lr, lr, #4 + bne .L11517 + b .L11219 +.L12433: + mov r8, #0 + b .L11284 +.L12432: + mov r4, #0 + b .L11244 +.L12091: + subs r6, r5, #4 + ldr r2, [r8, #4] + ldreq r2, [sp, #68] + beq .L12105 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #68] + mov r4, #0 +.L12106: + movs r3, ip, lsr #24 + beq .L12107 + ldr r2, [lr, #0] + ldr r9, [sp, #20] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12107: + add r4, r4, #1 + cmp r4, r6 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12106 + ldr sl, [sp, #68] + add r3, sl, r5, asl #2 + sub r2, r3, #16 +.L12105: + ldr r1, [r8, #0] + cmp r1, #0 + beq .L12113 + ands r0, r1, #255 + beq .L12115 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne fp, [sp, #20] + ldreq ip, [sp, #20] + movne r3, r3, asl #16 + orrne r3, fp, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L12115: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L12119 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #20] + ldreq r4, [sp, #20] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r4, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L12119: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L12123 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #20] + ldreq r7, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L12123: + movs r1, r1, lsr #24 + beq .L12113 + ldr r3, [r2, #0] + tst r3, #256 + beq .L12128 + mov r3, r3, lsr #16 + ldr r9, [sp, #20] + mov r3, r3, asl #16 + orr r3, r9, r3 + orr r3, r1, r3 + str r3, [r2, #0] +.L12113: + add r4, r2, #16 + b .L12095 +.L11755: + subs r6, r5, #4 + ldr r2, [r7, #0] + ldreq r2, [sp, #68] + beq .L11769 + mov r3, lr, asl #3 + mov ip, r2, lsr r3 + ldr lr, [sp, #68] + mov r4, #0 +.L11770: + ands r3, ip, #255 + beq .L11771 + ldr r2, [lr, #0] + ldr r8, [sp, #20] + tst r2, #256 + orr r1, r8, r3 + orr r0, r8, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11771: + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11770 + ldr r9, [sp, #68] + add r3, r9, r5, asl #2 + sub r2, r3, #16 +.L11769: + ldr r1, [r7, #4] + cmp r1, #0 + beq .L11777 + ands r0, r1, #255 + beq .L11779 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #20] + ldreq fp, [sp, #20] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, fp, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L11779: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L11783 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #20] + ldreq lr, [sp, #20] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L11783: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L11787 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #20] + ldreq r6, [sp, #20] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L11787: + movs r1, r1, lsr #24 + beq .L11777 + ldr r3, [r2, #12] + tst r3, #256 + beq .L11792 + mov r3, r3, lsr #16 + ldr r8, [sp, #20] + mov r3, r3, asl #16 + orr r3, r8, r3 + orr r3, r1, r3 + str r3, [r2, #12] +.L11777: + add r4, r2, #16 + b .L11759 +.L12431: + ldr lr, [sp, #12] + b .L12395 +.L12056: + ldr r7, [sp, #92] + mov r3, lr, asl #3 + ldr r1, [r8, #4] + add r2, r7, lr + sub r3, r3, #32 + cmp r2, #4 + mov ip, r1, asl r3 + bhi .L12065 + cmp r7, #0 + ldrne lr, [sp, #68] + movne r4, #0 + beq .L11219 +.L12085: + movs r3, ip, lsr #24 + beq .L12086 + ldr r2, [lr, #0] + ldr r5, [sp, #20] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12086: + ldr r6, [sp, #92] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12085 + b .L11219 +.L11720: + ldr r1, [sp, #92] + ldr r3, [r7, #0] + add r2, r1, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov ip, r3, lsr r1 + bhi .L11729 + ldr r2, [sp, #92] + cmp r2, #0 + ldrne lr, [sp, #68] + movne r4, #0 + beq .L11219 +.L11749: + ands r3, ip, #255 + beq .L11750 + ldr r2, [lr, #0] + ldr fp, [sp, #20] + tst r2, #256 + orr r1, fp, r3 + orr r0, fp, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11750: + ldr r0, [sp, #92] + add r4, r4, #1 + cmp r0, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11749 + b .L11219 +.L11729: + rsbs r5, lr, #4 + ldreq lr, [sp, #68] + beq .L11734 + ldr lr, [sp, #68] + mov r4, #0 +.L11735: + ands r3, ip, #255 + beq .L11736 + ldr r2, [lr, #0] + ldr r6, [sp, #20] + tst r2, #256 + orr r1, r6, r3 + orr r0, r6, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11736: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11735 + ldr r8, [sp, #68] + add lr, r8, r5, asl #2 +.L11734: + ldr r9, [sp, #92] + ldr ip, [r7, #4] + subs r5, r9, r5 + beq .L11219 + mov r4, #0 +.L11743: + ands r3, ip, #255 + beq .L11744 + ldr r2, [lr, #0] + ldr sl, [sp, #20] + tst r2, #256 + orr r1, sl, r3 + orr r0, sl, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L11744: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L11743 + b .L11219 +.L12065: + rsbs r5, lr, #4 + ldreq lr, [sp, #68] + beq .L12070 + ldr lr, [sp, #68] + mov r4, #0 +.L12071: + movs r3, ip, lsr #24 + beq .L12072 + ldr r2, [lr, #0] + ldr r9, [sp, #20] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12072: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12071 + ldr sl, [sp, #68] + add lr, sl, r5, asl #2 +.L12070: + ldr fp, [sp, #92] + ldr ip, [r8, #0] + subs r5, fp, r5 + beq .L11219 + mov r4, #0 +.L12079: + movs r3, ip, lsr #24 + beq .L12080 + ldr r2, [lr, #0] + ldr r0, [sp, #20] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12080: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L12079 + b .L11219 +.L11900: + ldr fp, [sp, #20] + orr r3, fp, r3, asl #16 + orr r3, r2, r3 + str r3, [r1, #12] + add r1, r1, #16 + b .L11867 +.L12236: + ldr fp, [sp, #20] + add r0, r1, #16 + orr r3, fp, r3, asl #16 + orr r3, r2, r3 + str r3, [r1, #0] + b .L12203 +.L12128: + ldr fp, [sp, #20] + add r4, r2, #16 + orr r3, fp, r3, asl #16 + orr r3, r1, r3 + str r3, [r2, #0] + b .L12095 +.L11792: + ldr sl, [sp, #20] + add r4, r2, #16 + orr r3, sl, r3, asl #16 + orr r3, r1, r3 + str r3, [r2, #12] + b .L11759 + .size render_scanline_obj_alpha_obj_1D, .-render_scanline_obj_alpha_obj_1D + .align 2 + .global render_scanline_obj_alpha_obj_2D + .type render_scanline_obj_alpha_obj_2D, %function +render_scanline_obj_alpha_obj_2D: + @ args = 0, pretend = 0, frame = 88 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L13670 + sub sp, sp, #88 + ldrh lr, [r5, #80] + mov r4, r0 + mov ip, lr, lsr #11 + and ip, ip, #2 + mov lr, lr, asl #27 + orr ip, ip, lr, lsr #31 + mov ip, ip, asl #9 + orr ip, ip, #256 + tst ip, #512 + str r1, [sp, #12] + str ip, [sp, #24] + str r2, [sp, #8] + str r3, [sp, #4] + beq .L13643 + ldrh r5, [r5, #6] + add r3, r0, r0, asl #2 + ldr r2, .L13670+4 + add r3, r5, r3, asl #5 + ldr r2, [r2, r3, asl #2] + str r5, [sp, #32] + str r2, [sp, #36] + cmp r2, #0 + ldr r2, .L13670+8 + add r3, r2, r3, asl #7 + str r3, [sp, #40] + beq .L13617 + ldr r1, [sp, #12] + ldmib sp, {r0, r2} @ phole ldm + mov r3, #0 + add r0, r0, r1, asl #2 + rsb r2, r1, r2 + str r0, [sp, #60] + str r2, [sp, #80] + str r3, [sp, #28] + mov r4, r3 +.L12443: + ldr r5, [sp, #40] + ldr r6, .L13670+20 + ldrb r3, [r4, r5] @ zero_extendqisi2 + ldr r7, .L13670+12 + mov r3, r3, asl #3 + ldrh lr, [r3, r6] + add r3, r3, r6 + ldrh r1, [r3, #2] + mov r4, lr, lsr #12 + and r2, r4, #12 + orr r0, r2, r1, lsr #14 + and ip, lr, #255 + mov r2, r1, asl #23 + cmp ip, #160 + mov r5, r2, asr #23 + ldr r2, .L13670+16 + subgt ip, ip, #256 + tst lr, #256 + ldrh r9, [r3, #4] + ldr r8, [r7, r0, asl #2] + ldr sl, [r2, r0, asl #2] + beq .L12446 + tst lr, #8192 + beq .L12448 + mov r3, r1, lsr #4 + ldr r4, .L13670+20 + and r3, r3, #992 + add r3, r3, r4 + add r2, r8, r8, lsr #31 + tst lr, #512 + ldrh r6, [r3, #30] + mov lr, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + mov r4, r1, asr #1 + movne r0, lr, asl #1 + str r6, [sp, #16] + strne r0, [sp, #44] + moveq r6, r8 + streq lr, [sp, #44] + moveq r0, r4 + movne r6, r8, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + ldrh fp, [r3, #6] + ldrh r1, [r3, #14] + ldrh r7, [r3, #22] + bge .L12453 + rsb r2, r5, r2 + rsb r6, r2, r6 + cmp r6, #0 + ble .L12455 + ldr r3, [sp, #44] + ldr r5, [sp, #12] + rsb r3, r2, r3 + str r3, [sp, #44] +.L12453: + ldr r2, [sp, #8] + add r3, r5, r6 + cmp r3, r2 + blt .L12457 + rsb r6, r5, r2 + cmp r6, #0 + ble .L12455 +.L12457: + add r0, ip, r0 + ldr ip, [sp, #16] + mov r2, r1, asl #16 + mov r3, fp, asl #16 + mov r1, ip, asl #16 + mov fp, r3, asr #16 + mov ip, r2, asr #16 + ldr r3, [sp, #32] + ldr r2, [sp, #4] + mov lr, lr, asl #8 + cmp r7, #0 + str lr, [sp, #72] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r5, r2, r5, asl #2 + rsb r0, r0, r3 + bne .L12459 + mla r3, r0, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L12455 + mov r3, r9, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L13670+24 + cmp r6, #0 + add sl, r3, r1, asl #3 + ble .L12455 + ldr r2, [sp, #44] + mul r3, r0, ip + mul r2, fp, r2 + ldr r4, [sp, #72] + rsb r3, r2, r3 + add r0, r4, r3 + mov r2, r0, asr #8 + cmp r8, r2 + movls lr, r7 + bls .L12465 + b .L13667 +.L12466: + cmp r8, r2 + bhi .L13631 +.L12465: + add lr, lr, #1 + add r0, r0, fp + cmp r6, lr + mov r2, r0, asr #8 + add r5, r5, #4 + bne .L12466 +.L12455: + ldr r5, [sp, #28] + ldr r6, [sp, #36] + add r5, r5, #1 + cmp r5, r6 + str r5, [sp, #28] + beq .L13617 + ldr r4, [sp, #28] + b .L12443 +.L12446: + ldr r2, [sp, #32] + tst r1, #8192 + rsb r0, ip, r2 + rsbne r3, r0, sl + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, r4, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L12455 + .p2align 2 +.L12536: + .word .L12532 + .word .L12533 + .word .L12534 + .word .L12535 +.L12532: + mov r3, r9, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + mov r2, r9, lsr #8 + cmp r5, r3 + ldr r3, .L13670+24 + and r6, r2, #240 + add ip, r3, r1, asl #2 + bge .L12537 + ldr r4, [sp, #12] + rsb lr, r5, r4 + rsb r7, lr, r8 + cmp r7, #0 + ble .L12455 + add r3, r5, r8 + ldr r5, [sp, #8] + cmp r5, r3 + bhi .L12540 + mov r3, lr, lsr #3 + mov r0, r3, asl #5 + ands r3, lr, #7 + add r7, ip, r0 + bne .L12542 + ldr sl, [sp, #80] + ldr r4, [sp, #60] +.L12544: + movs r8, sl, lsr #3 + beq .L12565 + mov r0, r4 + mov lr, r7 + mov r5, #0 +.L12567: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L12568 + ands r3, r1, #15 + beq .L12570 + ldr r2, [r0, #0] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12570: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L12574 + ldr r2, [r0, #4] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12574: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L12578 + ldr r2, [r0, #8] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12578: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L12582 + ldr r2, [r0, #12] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12582: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L12586 + ldr r2, [r0, #16] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12586: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L12590 + ldr r2, [r0, #20] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12590: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L12594 + ldr r2, [r0, #24] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12594: + movs r3, r1, lsr #28 + beq .L12568 + ldr r2, [r0, #28] + orr r1, r6, r3 + tst r2, #256 + ldrne ip, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, ip, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12568: + add r5, r5, #1 + cmp r5, r8 + add lr, lr, #32 + add r0, r0, #32 + bne .L12567 + mov r3, r8, asl #5 + add r7, r7, r3 + add r4, r4, r3 +.L12565: + ands r5, sl, #7 + beq .L12455 + ldr ip, [r7, #0] + mov lr, #0 +.L12603: + ands r3, ip, #15 + beq .L12604 + ldr r1, [r4, #0] + ldr sl, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L12604: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L12603 + b .L12455 +.L12533: + mov r3, r9, asl #22 + mov r1, r0, lsr #3 + subs r2, r8, #8 + mov r3, r3, lsr #22 + submi r2, r8, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr ip, [sp, #12] + add r1, r1, r3, asl #3 + ldr r3, .L13670+24 + mov r2, r9, lsr #8 + cmp r5, ip + add r0, r3, r1, asl #2 + and r6, r2, #240 + bge .L12741 + rsb lr, r5, ip + rsb r7, lr, r8 + cmp r7, #0 + ble .L12455 + ldr r1, [sp, #8] + add r3, r5, r8 + cmp r1, r3 + bhi .L12744 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub ip, r0, r3, asl #5 + bne .L12746 + ldr sl, [sp, #80] + ldr r5, [sp, #60] +.L12748: + movs r8, sl, lsr #3 + beq .L12769 + mov r0, r5 + mov r4, ip + mov r7, #0 +.L12771: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L12772 + ands r3, r1, #15 + beq .L12774 + ldr r2, [r0, #28] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12774: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L12778 + ldr r2, [r0, #24] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12778: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L12782 + ldr r2, [r0, #20] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12782: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L12786 + ldr r2, [r0, #16] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12786: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L12790 + ldr r2, [r0, #12] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12790: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L12794 + ldr r2, [r0, #8] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12794: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L12798 + ldr r2, [r0, #4] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12798: + movs r3, r1, lsr #28 + beq .L12772 + ldr r2, [r0, #0] + orr r1, r6, r3 + tst r2, #256 + ldrne lr, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, lr, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12772: + add r7, r7, #1 + cmp r8, r7 + sub r4, r4, #32 + add r0, r0, #32 + bne .L12771 + rsb r3, r8, r8, asl #27 + add ip, ip, r3, asl #5 + add r5, r5, r8, asl #5 +.L12769: + ands r4, sl, #7 + beq .L12455 + ldr ip, [ip, #0] + mov lr, #0 +.L12807: + movs r3, ip, lsr #28 + beq .L12808 + ldr r1, [r5, #0] + ldr sl, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L12808: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r5, r5, #4 + bne .L12807 + b .L12455 +.L12534: + mov r2, r9, asl #22 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + and r3, r0, #7 + add r2, r2, r1, asl #5 + add r3, r3, r2, asl #2 + ldr ip, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L13670+24 + cmp r5, ip + add ip, r0, r3 + bge .L12945 + ldr lr, [sp, #12] + rsb r0, r5, lr + rsb r7, r0, r8 + cmp r7, #0 + ble .L12455 + ldr r1, [sp, #8] + add r3, r5, r8 + cmp r1, r3 + bhi .L12948 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r7, ip, r3, asl #6 + bne .L12950 + ldr r6, [sp, #80] + ldr r4, [sp, #60] +.L12952: + movs r5, r6, lsr #3 + beq .L13030 + mov r1, r4 + mov ip, r7 + mov lr, #0 +.L13032: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L13033 + ands r0, r2, #255 + beq .L13035 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13035: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13039 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13039: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13043 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13043: + movs r0, r2, lsr #24 + beq .L13033 + ldr r2, [r1, #12] + tst r2, #256 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r0 + orrne r2, r8, r0 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13033: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L13050 + ands r0, r2, #255 + beq .L13052 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L13052: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13056 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L13056: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13060 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L13060: + movs r2, r2, lsr #24 + beq .L13050 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq r0, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, r0, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L13050: + add lr, lr, #1 + cmp lr, r5 + add ip, ip, #64 + add r1, r1, #32 + bne .L13032 + add r7, r7, r5, asl #6 + add r4, r4, r5, asl #5 +.L13030: + ands r5, r6, #7 + beq .L12455 + cmp r5, #3 + ldrls ip, [r7, #0] + bls .L13089 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L13071 + ands r1, r2, #255 + beq .L13073 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L13073: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13077 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L13077: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13081 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L13081: + movs r1, r2, lsr #24 + beq .L13071 + ldr r2, [r4, #12] + tst r2, #256 + ldrne r0, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, r1 + orrne r2, r0, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L13071: + subs r5, r5, #4 + ldr ip, [r7, #4] + addne r4, r4, #16 + beq .L12455 +.L13089: + mov lr, #0 +.L13090: + ands r3, ip, #255 + beq .L13091 + ldr r2, [r4, #0] + ldr r7, [sp, #24] + tst r2, #256 + orr r1, r7, r3 + orr r0, r7, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r4, #0] + streq r1, [r4, #0] +.L13091: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, lsr #8 + add r4, r4, #4 + bhi .L13090 + b .L12455 +.L13671: + .align 2 +.L13670: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word obj_width_table + .word obj_height_table + .word oam_ram + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L12535: + subs r2, r8, #8 + submi r2, r8, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, r9, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + add r1, r1, r2, asl #1 + and r3, r0, #7 + add r3, r3, r1, asl #2 + ldr r1, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L13670+24 + cmp r5, r1 + add ip, r0, r3 + bge .L13281 + rsb r0, r5, r1 + rsb r7, r0, r8 + cmp r7, #0 + ble .L12455 + ldr r2, [sp, #8] + add r3, r5, r8 + cmp r2, r3 + bhi .L13284 + mov r3, r0, lsr #3 + ands lr, r0, #7 + sub r8, ip, r3, asl #6 + bne .L13286 + ldr r7, [sp, #80] + ldr r4, [sp, #60] +.L13288: + movs r6, r7, lsr #3 + beq .L13366 + mov r0, r4 + mov lr, r8 + mov r5, #0 +.L13368: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L13369 + ands r1, r2, #255 + beq .L13371 + ldr r3, [r0, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L13371: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13375 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L13375: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13379 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq ip, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L13379: + movs r2, r2, lsr #24 + beq .L13369 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r1, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L13369: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L13386 + ands ip, r1, #255 + beq .L13388 + ldr r2, [r0, #28] + tst r2, #256 + ldrne sl, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, ip + orrne r2, sl, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L13388: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L13392 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq ip, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L13392: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L13396 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L13396: + movs r1, r1, lsr #24 + beq .L13386 + ldr r2, [r0, #16] + tst r2, #256 + ldrne ip, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r1 + orrne r2, ip, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L13386: + add r5, r5, #1 + cmp r5, r6 + sub lr, lr, #64 + add r0, r0, #32 + bne .L13368 + rsb r3, r6, r6, asl #26 + add r8, r8, r3, asl #6 + add r4, r4, r6, asl #5 +.L13366: + ands r5, r7, #7 + beq .L12455 + cmp r5, #3 + ldrls ip, [r8, #4] + bls .L13425 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L13407 + ands r1, r2, #255 + beq .L13409 + ldr r3, [r4, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq ip, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L13409: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13413 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #24] + ldreq r0, [sp, #24] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r0, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L13413: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13417 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L13417: + movs r2, r2, lsr #24 + beq .L13407 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L13407: + subs r5, r5, #4 + ldr ip, [r8, #0] + addne r4, r4, #16 + beq .L12455 +.L13425: + mov lr, #0 +.L13426: + movs r3, ip, lsr #24 + beq .L13427 + ldr r2, [r4, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r4, #0] + streq r1, [r4, #0] +.L13427: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, asl #8 + add r4, r4, #4 + bhi .L13426 + b .L12455 +.L12448: + mov r3, r1, lsr #4 + ldr r4, .L13670+20 + and r3, r3, #992 + add r3, r3, r4 + add r2, r8, r8, lsr #31 + tst lr, #512 + ldrh r6, [r3, #30] + mov lr, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #12] + mov r4, r1, asr #1 + movne r0, r8, asl #1 + str r6, [sp, #20] + strne r0, [sp, #84] + streq r8, [sp, #84] + moveq r6, lr + moveq r0, r4 + movne r6, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + ldrh r7, [r3, #6] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + bge .L12490 + ldr r3, [sp, #84] + rsb r2, r5, r2 + rsb r3, r2, r3 + cmp r3, #0 + str r3, [sp, #84] + ble .L12455 + ldr r5, [sp, #12] + rsb r6, r2, r6 +.L12490: + ldr r2, [sp, #84] + add r3, r5, r2 + ldr r2, [sp, #8] + cmp r3, r2 + blt .L12493 + rsb r3, r5, r2 + cmp r3, #0 + str r3, [sp, #84] + ble .L12455 +.L12493: + mov r3, r7, asl #16 + mov r2, r1, asl #16 + ldr r7, [sp, #20] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + add ip, ip, r0 + str r3, [sp, #48] + mov r0, r9, lsr #8 + str r2, [sp, #52] + ldr r3, [sp, #32] + ldr r2, [sp, #4] + mov r1, r7, asl #16 + mov lr, lr, asl #8 + and r0, r0, #240 + cmp fp, #0 + str lr, [sp, #64] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r7, r2, r5, asl #2 + rsb ip, ip, r3 + str r0, [sp, #76] + bne .L12495 + mla r3, ip, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L12455 + mov r3, r9, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + ldr r4, [sp, #84] + add r1, r1, r3, asl #3 + ldr r3, .L13670+24 + cmp r4, #0 + add r5, r3, r1, asl #2 + ble .L12455 + ldr r3, [sp, #52] + ldr r2, [sp, #48] + mul r3, ip, r3 + mul r2, r6, r2 + ldr r6, [sp, #64] + rsb r3, r2, r3 + add ip, r6, r3 + mov r1, ip, asr #8 + cmp r1, r8 + movcc r4, fp + movcs r4, fp + bcs .L12502 + b .L13633 +.L12503: + cmp r8, r2 + bhi .L12504 +.L12502: + ldr r9, [sp, #48] + ldr sl, [sp, #84] + add r4, r4, #1 + add ip, ip, r9 + cmp sl, r4 + mov r2, ip, asr #8 + add r7, r7, #4 + bne .L12503 + b .L12455 +.L13617: + add sp, sp, #88 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L12459: + mov r3, r9, asl #22 + ldr r2, .L13670+24 + mov r3, r3, lsr #22 + cmp r6, #0 + add r9, r2, r3, asl #5 + ble .L12455 + mov r3, r7, asl #16 + mul r2, r0, r1 + mov r7, r3, asr #16 + mul r3, r0, ip + ldr r0, [sp, #44] + ldr r1, [sp, #44] + mul r0, fp, r0 + mul r1, r7, r1 + rsb r3, r0, r3 + ldr r0, [sp, #72] + rsb r2, r1, r2 + add ip, r0, r3 + add r0, lr, r2 + mov r1, r0, asr #8 + mov lr, ip, asr #8 + cmp lr, r8 + cmpcc r1, sl + movcs r3, #0 + movcc r3, #1 + movcs r4, r3 + bcs .L12477 + b .L13668 +.L12478: + cmp r8, lr + cmphi sl, r1 + bhi .L12480 +.L12477: + add r4, r4, #1 + add ip, ip, fp + add r0, r0, r7 + cmp r6, r4 + mov lr, ip, asr #8 + mov r1, r0, asr #8 + add r5, r5, #4 + bne .L12478 + b .L12455 +.L13646: + and r3, r1, #7 + mov r2, lr, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + mov r1, r1, asr #3 + add r3, r3, r1, asl #10 + and r2, lr, #7 + add r3, r3, r9 + ldrb lr, [r3, r2] @ zero_extendqisi2 + cmp lr, #0 + beq .L12483 + ldr r3, [r5, #0] + ldr r1, [sp, #24] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r2, r1, r2 + orr r1, r1, r3, asl #16 + orr r2, lr, r2 + tst r3, #256 + orr r1, lr, r1 + str r2, [sp, #0] + strne r2, [r5, #0] + streq r1, [r5, #0] +.L12483: + add r4, r4, #1 + add ip, ip, fp + add r0, r0, r7 + cmp r6, r4 + mov lr, ip, asr #8 + mov r1, r0, asr #8 + add r5, r5, #4 + ble .L12455 +.L12480: + cmp sl, r1 + cmphi r8, lr + bhi .L13646 + b .L12455 +.L12495: + mov r3, r9, asl #22 + ldr r4, [sp, #84] + ldr r2, .L13670+24 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r4, #0 + str r3, [sp, #68] + ble .L12455 + mov r3, fp, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #56] + mul r2, ip, r1 + ldr r3, [sp, #52] + ldr r1, [sp, #56] + ldr r0, [sp, #48] + mul r3, ip, r3 + mul r1, r6, r1 + mul r0, r6, r0 + ldr r6, [sp, #64] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, r6, r3 + add r4, lr, r2 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + cmp ip, r8 + cmpcc lr, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L12517 + b .L13669 +.L12518: + cmp r8, ip + cmphi sl, lr + bhi .L12520 +.L12517: + ldr ip, [sp, #56] + ldr r9, [sp, #48] + ldr r0, [sp, #84] + add r6, r6, #1 + add r4, r4, ip + add r5, r5, r9 + cmp r0, r6 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + add r7, r7, #4 + bne .L12518 + b .L12455 +.L13648: + mov r3, ip, asr #1 + ldr r2, [sp, #68] + and fp, r3, #3 + ldr r3, [sp, #68] + and r1, lr, #7 + and r0, lr, #7 + add r1, r2, r1, asl #2 + add r0, r3, r0, asl #2 + mov r2, ip, asr #1 + mov r3, lr, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + add r3, r3, r2, asl #5 + add r0, r0, r3 + tst ip, #1 + add r1, r1, r3 + ldrneb r3, [r1, fp] @ zero_extendqisi2 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr r9, [sp, #76] + cmp r0, #0 + orr r0, r0, r9 + beq .L12526 + ldr r2, [r7, #0] + ldr ip, [sp, #24] + mov r3, r2, lsr #16 + orr r1, ip, r0 + mov r3, r3, asl #16 + orr r0, ip, r0 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L12526: + ldr lr, [sp, #48] + ldr r0, [sp, #56] + ldr r1, [sp, #84] + add r6, r6, #1 + add r5, r5, lr + add r4, r4, r0 + cmp r1, r6 + add r7, r7, #4 + mov ip, r5, asr #8 + mov lr, r4, asr #8 + ble .L12455 +.L12520: + cmp sl, lr + cmphi r8, ip + bhi .L13648 + b .L12455 +.L12505: + cmp r8, r1 + bls .L12455 +.L13633: + mov r3, r1, asr #1 + and lr, r3, #3 + mov r3, r1, asr #3 + mov r3, r3, asl #5 + mov r2, r1, asr #1 + tst r1, #1 + and r0, r2, #3 + add r1, r3, r5 + add r2, r3, r5 + ldreqb r3, [r2, r0] @ zero_extendqisi2 + ldrneb r3, [r1, lr] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + ldr lr, [sp, #76] + cmp r2, #0 + orr r3, r2, lr + beq .L12510 + ldr r2, [r7, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r1, r3, r1 + orr r3, r0, r2, asl #16 + strne r1, [r7, #0] + streq r3, [r7, #0] +.L12510: + ldr r1, [sp, #48] + ldr r2, [sp, #84] + add r4, r4, #1 + add ip, ip, r1 + cmp r2, r4 + add r7, r7, #4 + mov r1, ip, asr #8 + bgt .L12505 + b .L12455 +.L12468: + cmp r8, r2 + bls .L12455 +.L13631: + mov r3, r2, asr #3 + add r3, sl, r3, asl #6 + and r2, r2, #7 + ldrb ip, [r3, r2] @ zero_extendqisi2 + cmp ip, #0 + beq .L12470 + ldr r3, [r5, #0] + ldr r7, [sp, #24] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r2, r7, r2 + orr r1, r7, r3, asl #16 + orr r4, ip, r2 + tst r3, #256 + orr r2, ip, r1 + strne r4, [r5, #0] + streq r2, [r5, #0] +.L12470: + add lr, lr, #1 + add r0, r0, fp + cmp r6, lr + add r5, r5, #4 + mov r2, r0, asr #8 + bgt .L12468 + b .L12455 +.L13281: + ldr r9, [sp, #8] + add r3, r5, r8 + cmp r3, r9 + bcs .L13649 + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L12455 + ldr r2, [sp, #4] + ldr r3, .L13670+28 + add r1, r2, r5, asl #2 + add r0, r0, r3 + mov r5, #0 + b .L13581 +.L13650: + sub ip, ip, #64 + add r1, r1, #32 +.L13581: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L13582 + ands lr, r2, #255 + beq .L13584 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13584: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L13588 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13588: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L13592 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq r4, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, r4, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13592: + movs r2, r2, lsr #24 + beq .L13582 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13582: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L13599 + ands r4, lr, #255 + beq .L13601 + ldr r2, [r1, #28] + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L13601: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L13605 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L13605: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L13609 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L13609: + movs lr, lr, lsr #24 + beq .L13599 + ldr r2, [r1, #16] + tst r2, #256 + ldrne sl, [sp, #24] + ldreq r4, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r4, lr + orrne r2, sl, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L13599: + add r5, r5, #1 + cmp r6, r5 + sub r0, r0, #64 + bne .L13650 + b .L12455 +.L12945: + ldr r9, [sp, #8] + add r3, r5, r8 + cmp r9, r3 + bls .L13651 + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r6, r3, asr #3 + beq .L12455 + ldr r2, [sp, #4] + ldr r3, .L13670+32 + add r1, r2, r5, asl #2 + add r0, r0, r3 + mov r4, #0 + b .L13245 +.L13652: + add ip, ip, #64 + add r1, r1, #32 +.L13245: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L13246 + ands lr, r2, #255 + beq .L13248 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13248: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L13252 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13252: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L13256 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq r5, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, r5, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13256: + movs lr, r2, lsr #24 + beq .L13246 + ldr r2, [r1, #12] + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13246: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L13263 + ands lr, r2, #255 + beq .L13265 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L13265: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L13269 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r7, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L13269: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L13273 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L13273: + movs r2, r2, lsr #24 + beq .L13263 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L13263: + add r4, r4, #1 + cmp r6, r4 + add r0, r0, #64 + bne .L13652 + b .L12455 +.L12741: + ldr ip, [sp, #8] + add r3, r5, r8 + cmp ip, r3 + bls .L13653 + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r7, r3, asr #3 + beq .L12455 + ldr ip, [sp, #4] + add r1, ip, r5, asl #2 + mov ip, #0 + b .L12910 +.L13654: + sub r0, r0, #32 + add r1, r1, #32 +.L12910: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L12911 + ands r3, lr, #15 + beq .L12913 + ldr r2, [r1, #28] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L12913: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L12917 + ldr r2, [r1, #24] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L12917: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L12921 + ldr r2, [r1, #20] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L12921: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L12925 + ldr r2, [r1, #16] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L12925: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L12929 + ldr r2, [r1, #12] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L12929: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L12933 + ldr r2, [r1, #8] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L12933: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L12937 + ldr r2, [r1, #4] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L12937: + movs r3, lr, lsr #28 + beq .L12911 + ldr r2, [r1, #0] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L12911: + add ip, ip, #1 + cmp r7, ip + bne .L13654 + b .L12455 +.L12537: + ldr lr, [sp, #8] + add r3, r5, r8 + cmp lr, r3 + bls .L13655 + cmp r8, #0 + add r3, r8, #7 + movge r3, r8 + movs r7, r3, asr #3 + beq .L12455 + ldr lr, [sp, #4] + mov r0, #0 + add r1, lr, r5, asl #2 + b .L12706 +.L13656: + add ip, ip, #32 + add r1, r1, #32 +.L12706: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L12707 + ands r3, lr, #15 + beq .L12709 + ldr r2, [r1, #0] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L12709: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L12713 + ldr r2, [r1, #4] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L12713: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L12717 + ldr r2, [r1, #8] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L12717: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L12721 + ldr r2, [r1, #12] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L12721: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L12725 + ldr r2, [r1, #16] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L12725: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L12729 + ldr r2, [r1, #20] + orr r4, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L12729: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L12733 + ldr r2, [r1, #24] + orr r4, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r4 + orrne r2, r5, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L12733: + movs r3, lr, lsr #28 + beq .L12707 + ldr r2, [r1, #28] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L12707: + add r0, r0, #1 + cmp r7, r0 + bne .L13656 + b .L12455 +.L13643: + add sp, sp, #88 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_color32_2D +.L13655: + rsb r0, r5, lr + cmp r0, #0 + ble .L12455 + ldr r1, [sp, #4] + movs sl, r0, lsr #3 + add r8, r1, r5, asl #2 + beq .L12661 + mov r4, r8 + mov r7, ip + mov r1, #0 +.L12663: + ldr lr, [r7, #0] + cmp lr, #0 + beq .L12664 + ands r3, lr, #15 + beq .L12666 + ldr r2, [r4, #0] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L12666: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L12670 + ldr r2, [r4, #4] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L12670: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L12674 + ldr r2, [r4, #8] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L12674: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L12678 + ldr r2, [r4, #12] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L12678: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L12682 + ldr r2, [r4, #16] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L12682: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L12686 + ldr r2, [r4, #20] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L12686: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L12690 + ldr r2, [r4, #24] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L12690: + movs r3, lr, lsr #28 + beq .L12664 + ldr r2, [r4, #28] + orr lr, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r5, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L12664: + add r1, r1, #1 + cmp sl, r1 + add r7, r7, #32 + add r4, r4, #32 + bne .L12663 + mov r3, sl, asl #5 + add ip, ip, r3 + add r8, r8, r3 +.L12661: + ands r4, r0, #7 + beq .L12455 + ldr ip, [ip, #0] + mov lr, #0 +.L12699: + ands r3, ip, #15 + beq .L12700 + ldr r1, [r8, #0] + ldr sl, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L12700: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, lsr #4 + add r8, r8, #4 + bne .L12699 + b .L12455 +.L13653: + rsb sl, r5, ip + cmp sl, #0 + ble .L12455 + ldr lr, [sp, #4] + movs ip, sl, lsr #3 + add r8, lr, r5, asl #2 + beq .L12865 + mov r4, r8 + mov r7, r0 + mov r1, #0 +.L12867: + ldr lr, [r7, #0] + cmp lr, #0 + beq .L12868 + ands r3, lr, #15 + beq .L12870 + ldr r2, [r4, #28] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L12870: + mov r3, lr, lsr #4 + ands r3, r3, #15 + beq .L12874 + ldr r2, [r4, #24] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L12874: + mov r3, lr, lsr #8 + ands r3, r3, #15 + beq .L12878 + ldr r2, [r4, #20] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L12878: + mov r3, lr, lsr #12 + ands r3, r3, #15 + beq .L12882 + ldr r2, [r4, #16] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L12882: + mov r3, lr, lsr #16 + ands r3, r3, #15 + beq .L12886 + ldr r2, [r4, #12] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L12886: + mov r3, lr, lsr #20 + ands r3, r3, #15 + beq .L12890 + ldr r2, [r4, #8] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L12890: + mov r3, lr, lsr #24 + ands r3, r3, #15 + beq .L12894 + ldr r2, [r4, #4] + orr r5, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L12894: + movs r3, lr, lsr #28 + beq .L12868 + ldr r2, [r4, #0] + orr lr, r6, r3 + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r5, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L12868: + add r1, r1, #1 + cmp ip, r1 + sub r7, r7, #32 + add r4, r4, #32 + bne .L12867 + rsb r3, ip, ip, asl #27 + add r0, r0, r3, asl #5 + add r8, r8, ip, asl #5 +.L12865: + ands r4, sl, #7 + beq .L12455 + ldr ip, [r0, #0] + mov lr, #0 +.L12903: + movs r3, ip, lsr #28 + beq .L12904 + ldr r1, [r8, #0] + ldr sl, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, sl, r2 + mov r3, r3, asl #16 + orr r2, sl, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L12904: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r8, r8, #4 + bne .L12903 + b .L12455 +.L13651: + rsb r8, r5, r9 + cmp r8, #0 + ble .L12455 + ldr sl, [sp, #4] + movs r7, r8, lsr #3 + add r6, sl, r5, asl #2 + beq .L13178 + ldr r3, .L13672 + mov lr, r6 + add r0, r0, r3 + mov r5, ip + mov r1, #0 +.L13180: + ldr r2, [r5, #0] + cmp r2, #0 + beq .L13181 + ands r4, r2, #255 + beq .L13183 + ldr r3, [lr, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L13183: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L13187 + ldr r3, [lr, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L13187: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L13191 + ldr r3, [lr, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L13191: + movs r4, r2, lsr #24 + beq .L13181 + ldr r2, [lr, #12] + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r4 + orrne r2, r9, r4 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L13181: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L13198 + ands r4, r2, #255 + beq .L13200 + ldr r3, [lr, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #16] + streq r3, [lr, #16] +.L13200: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L13204 + ldr r3, [lr, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #20] + streq r3, [lr, #20] +.L13204: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L13208 + ldr r3, [lr, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r4, r3 + strne r3, [lr, #24] + streq r3, [lr, #24] +.L13208: + movs r2, r2, lsr #24 + beq .L13198 + ldr r3, [lr, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [lr, #28] + streq r3, [lr, #28] +.L13198: + add r1, r1, #1 + cmp r7, r1 + add r5, r5, #64 + add lr, lr, #32 + add r0, r0, #64 + bne .L13180 + add ip, ip, r7, asl #6 + add r6, r6, r7, asl #5 +.L13178: + ands r4, r8, #7 + beq .L12455 + cmp r4, #3 + ldrls ip, [ip, #0] + bls .L13237 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L13219 + ands r1, r2, #255 + beq .L13221 + ldr r3, [r6, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L13221: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13225 + ldr r3, [r6, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r0, [sp, #24] + ldreq r5, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L13225: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13229 + ldr r3, [r6, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L13229: + movs r1, r2, lsr #24 + beq .L13219 + ldr r2, [r6, #12] + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r1 + orrne r2, r9, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L13219: + subs r4, r4, #4 + ldr ip, [ip, #4] + addne r6, r6, #16 + beq .L12455 +.L13237: + mov lr, #0 +.L13238: + ands r3, ip, #255 + beq .L13239 + ldr r2, [r6, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r6, #0] + streq r1, [r6, #0] +.L13239: + add lr, lr, #1 + cmp lr, r4 + mov ip, ip, lsr #8 + add r6, r6, #4 + bcc .L13238 + b .L12455 +.L13649: + rsb sl, r5, r9 + cmp sl, #0 + ble .L12455 + ldr lr, [sp, #4] + movs r8, sl, lsr #3 + add r7, lr, r5, asl #2 + beq .L13514 + ldr r3, .L13672+4 + mov r4, r7 + add r0, r0, r3 + mov r6, ip + mov r1, #0 +.L13516: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L13517 + ands lr, r2, #255 + beq .L13519 + ldr r3, [r4, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L13519: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L13523 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L13523: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L13527 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, lr, r3 + orreq r3, lr, r3 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L13527: + movs r2, r2, lsr #24 + beq .L13517 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne lr, [sp, #24] + ldreq r5, [sp, #24] + movne r3, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L13517: + ldr lr, [r6, #0] + cmp lr, #0 + beq .L13534 + ands r5, lr, #255 + beq .L13536 + ldr r2, [r4, #28] + tst r2, #256 + ldrne r9, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, r5 + orrne r2, r9, r5 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L13536: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L13540 + ldr r3, [r4, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L13540: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L13544 + ldr r3, [r4, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L13544: + movs lr, lr, lsr #24 + beq .L13534 + ldr r2, [r4, #16] + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r9, lr + orrne r2, r5, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L13534: + add r1, r1, #1 + cmp r8, r1 + sub r6, r6, #64 + add r4, r4, #32 + sub r0, r0, #64 + bne .L13516 + rsb r3, r8, r8, asl #26 + add ip, ip, r3, asl #6 + add r7, r7, r8, asl #5 +.L13514: + ands r4, sl, #7 + beq .L12455 + cmp r4, #3 + ldrls ip, [ip, #4] + bls .L13573 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L13555 + ands r1, r2, #255 + beq .L13557 + ldr r3, [r7, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #12] + streq r3, [r7, #12] +.L13557: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13561 + ldr r3, [r7, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r0, [sp, #24] + ldreq r5, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r5, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #8] + streq r3, [r7, #8] +.L13561: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13565 + ldr r3, [r7, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r7, #4] + streq r3, [r7, #4] +.L13565: + movs r2, r2, lsr #24 + beq .L13555 + ldr r3, [r7, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r7, #0] + streq r3, [r7, #0] +.L13555: + subs r4, r4, #4 + ldr ip, [ip, #0] + addne r7, r7, #16 + beq .L12455 +.L13573: + mov lr, #0 +.L13574: + movs r3, ip, lsr #24 + beq .L13575 + ldr r2, [r7, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [r7, #0] + streq r1, [r7, #0] +.L13575: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #8 + add r7, r7, #4 + bhi .L13574 + b .L12455 +.L13284: + mov r3, r0, lsr #3 + ands r2, r0, #7 + sub r4, ip, r3, asl #6 + ldreq r0, [sp, #60] + beq .L13434 + cmp r2, #3 + rsb r6, r2, #8 + bhi .L13657 + subs r8, r6, #4 + ldr r1, [r4, #4] + ldreq r1, [sp, #60] + beq .L13449 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #60] + mov r5, #0 +.L13450: + movs r3, ip, lsr #24 + beq .L13451 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13451: + add r5, r5, #1 + cmp r8, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13450 + ldr sl, [sp, #60] + add r3, sl, r6, asl #2 + sub r1, r3, #16 +.L13449: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L13457 + ands r0, r2, #255 + beq .L13459 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13459: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13463 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13463: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13467 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13467: + movs r2, r2, lsr #24 + beq .L13457 + ldr r3, [r1, #0] + tst r3, #256 + beq .L13472 + mov r3, r3, lsr #16 + ldr sl, [sp, #24] + mov r3, r3, asl #16 + orr r3, sl, r3 + orr r3, r2, r3 + str r3, [r1, #0] +.L13457: + add r0, r1, #16 +.L13439: + sub r4, r4, #64 +.L13434: + movs r5, r7, lsr #3 + beq .L12455 + mov lr, #0 + b .L13475 +.L13658: + sub r4, r4, #64 + add r0, r0, #32 +.L13475: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L13476 + ands r1, r2, #255 + beq .L13478 + ldr r3, [r0, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r6, [sp, #24] + ldreq r7, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r6, r3 + orreq r3, r7, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L13478: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L13482 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L13482: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L13486 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne sl, [sp, #24] + ldreq ip, [sp, #24] + movne r3, r3, asl #16 + orrne r3, sl, r3 + orreq r3, ip, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r1, r3 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L13486: + movs r2, r2, lsr #24 + beq .L13476 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r1, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L13476: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L13493 + ands ip, r1, #255 + beq .L13495 + ldr r2, [r0, #28] + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L13495: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L13499 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L13499: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L13503 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L13503: + movs r1, r1, lsr #24 + beq .L13493 + ldr r2, [r0, #16] + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, r1 + orrne r2, r7, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L13493: + add lr, lr, #1 + cmp lr, r5 + bne .L13658 + b .L12455 +.L12948: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r4, ip, r3, asl #6 + ldreq r1, [sp, #60] + beq .L13098 + cmp r2, #3 + rsb r6, r2, #8 + bhi .L13659 + subs r8, r6, #4 + ldr r1, [r4, #0] + ldreq r1, [sp, #60] + beq .L13113 + mov r3, r2, asl #3 + mov ip, r1, lsr r3 + ldr lr, [sp, #60] + mov r5, #0 +.L13114: + ands r3, ip, #255 + beq .L13115 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13115: + add r5, r5, #1 + cmp r8, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L13114 + ldr sl, [sp, #60] + add r3, sl, r6, asl #2 + sub r1, r3, #16 +.L13113: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L13121 + ands r0, r2, #255 + beq .L13123 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13123: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13127 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13127: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13131 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13131: + movs r2, r2, lsr #24 + beq .L13121 + ldr r3, [r1, #12] + tst r3, #256 + beq .L13136 + mov r3, r3, lsr #16 + ldr sl, [sp, #24] + mov r3, r3, asl #16 + orr r3, sl, r3 + orr r3, r2, r3 + str r3, [r1, #12] +.L13121: + add r1, r1, #16 +.L13103: + add r4, r4, #64 +.L13098: + movs lr, r7, lsr #3 + beq .L12455 + mov ip, #0 + b .L13139 +.L13660: + add r4, r4, #64 + add r1, r1, #32 +.L13139: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L13140 + ands r0, r2, #255 + beq .L13142 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13142: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13146 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13146: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13150 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13150: + movs r0, r2, lsr #24 + beq .L13140 + ldr r2, [r1, #12] + tst r2, #256 + ldrne r5, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r6, r0 + orrne r2, r5, r0 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13140: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L13157 + ands r0, r2, #255 + beq .L13159 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L13159: + mov r3, r2, lsr #8 + ands r0, r3, #255 + beq .L13163 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r9, r3 + orreq r3, sl, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L13163: + mov r3, r2, lsr #16 + ands r0, r3, #255 + beq .L13167 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r5, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r5, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L13167: + movs r2, r2, lsr #24 + beq .L13157 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r8, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r2, r3 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L13157: + add ip, ip, #1 + cmp ip, lr + bne .L13660 + b .L12455 +.L12744: + ands r2, lr, #7 + mov r3, lr, lsr #3 + sub ip, r0, r3, asl #5 + ldreq r0, [sp, #60] + beq .L12815 + rsbs r8, r2, #8 + ldr r1, [ip, #0] + ldreq r0, [sp, #60] + beq .L12818 + mov r3, r2, asl #2 + mov lr, r1, asl r3 + ldr r4, [sp, #60] + mov r5, #0 +.L12819: + movs r3, lr, lsr #28 + beq .L12820 + ldr r1, [r4, #0] + orr r2, r6, r3 + ldr r3, [sp, #24] + ldr r9, [sp, #24] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r9, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L12820: + add r5, r5, #1 + cmp r5, r8 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L12819 + ldr sl, [sp, #60] + add r0, sl, r8, asl #2 +.L12818: + sub ip, ip, #32 +.L12815: + movs r5, r7, lsr #3 + beq .L12455 + mov r4, #0 + b .L12827 +.L13673: + .align 2 +.L13672: + .word vram+65600 + .word vram+65472 +.L13661: + sub ip, ip, #32 + add r0, r0, #32 +.L12827: + ldr r1, [ip, #0] + cmp r1, #0 + beq .L12828 + ands r3, r1, #15 + beq .L12830 + ldr r2, [r0, #28] + orr lr, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12830: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L12834 + ldr r2, [r0, #24] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12834: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L12838 + ldr r2, [r0, #20] + orr lr, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12838: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L12842 + ldr r2, [r0, #16] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12842: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L12846 + ldr r2, [r0, #12] + orr lr, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12846: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L12850 + ldr r2, [r0, #8] + orr lr, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, lr + orrne r2, r9, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12850: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L12854 + ldr r2, [r0, #4] + orr lr, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, lr + orrne r2, r7, lr + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12854: + movs r3, r1, lsr #28 + beq .L12828 + ldr r2, [r0, #0] + orr r1, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r1 + orrne r2, r9, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12828: + add r4, r4, #1 + cmp r5, r4 + bne .L13661 + b .L12455 +.L12540: + mov r3, lr, lsr #3 + mov r0, r3, asl #5 + ands r3, lr, #7 + add r5, ip, r0 + ldreq r0, [sp, #60] + beq .L12611 + rsbs r8, r3, #8 + ldr r0, [ip, r0] + ldreq r0, [sp, #60] + beq .L12614 + mov r3, r3, asl #2 + mov ip, r0, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12615: + ands r3, ip, #15 + beq .L12616 + ldr r1, [lr, #0] + orr r2, r6, r3 + ldr r3, [sp, #24] + ldr r9, [sp, #24] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r9, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L12616: + add r4, r4, #1 + cmp r8, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L12615 + ldr sl, [sp, #60] + add r0, sl, r8, asl #2 +.L12614: + add r5, r5, #32 +.L12611: + movs r4, r7, lsr #3 + beq .L12455 + mov lr, #0 + b .L12623 +.L13662: + add r5, r5, #32 + add r0, r0, #32 +.L12623: + ldr r1, [r5, #0] + cmp r1, #0 + beq .L12624 + ands r3, r1, #15 + beq .L12626 + ldr r2, [r0, #0] + orr ip, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L12626: + mov r3, r1, lsr #4 + ands r3, r3, #15 + beq .L12630 + ldr r2, [r0, #4] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L12630: + mov r3, r1, lsr #8 + ands r3, r3, #15 + beq .L12634 + ldr r2, [r0, #8] + orr ip, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L12634: + mov r3, r1, lsr #12 + ands r3, r3, #15 + beq .L12638 + ldr r2, [r0, #12] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L12638: + mov r3, r1, lsr #16 + ands r3, r3, #15 + beq .L12642 + ldr r2, [r0, #16] + orr ip, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L12642: + mov r3, r1, lsr #20 + ands r3, r3, #15 + beq .L12646 + ldr r2, [r0, #20] + orr ip, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, ip + orrne r2, r9, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L12646: + mov r3, r1, lsr #24 + ands r3, r3, #15 + beq .L12650 + ldr r2, [r0, #24] + orr ip, r6, r3 + tst r2, #256 + ldrne r7, [sp, #24] + ldreq r8, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, r8, ip + orrne r2, r7, ip + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L12650: + movs r3, r1, lsr #28 + beq .L12624 + ldr r2, [r0, #28] + orr r1, r6, r3 + tst r2, #256 + ldrne r9, [sp, #24] + ldreq sl, [sp, #24] + movne r3, r2, lsr #16 + movne r3, r3, asl #16 + orreq r3, sl, r1 + orrne r2, r9, r1 + orrne r3, r3, r2 + orreq r3, r3, r2, asl #16 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L12624: + add lr, lr, #1 + cmp r4, lr + bne .L13662 + b .L12455 +.L12504: + mov r1, r2 + b .L13633 +.L12746: + ldr r2, [sp, #80] + rsb r7, r4, #8 + cmp r2, r7 + blt .L13663 + cmp r7, #0 + ldr r2, [ip, #0] + ldreq r5, [sp, #60] + beq .L12761 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + ldr r4, [sp, #60] + mov r5, #0 +.L12762: + movs r3, lr, lsr #28 + beq .L12763 + ldr r1, [r4, #0] + ldr r8, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r8, r2 + mov r3, r3, asl #16 + orr r2, r8, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L12763: + add r5, r5, #1 + cmp r7, r5 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L12762 + ldr r9, [sp, #60] + add r5, r9, r7, asl #2 +.L12761: + ldr lr, [sp, #80] + sub ip, ip, #32 + rsb sl, r7, lr + b .L12748 +.L13286: + ldr r3, [sp, #80] + rsb r5, lr, #8 + cmp r3, r5 + blt .L13664 + cmp lr, #3 + bls .L13327 + cmp r5, #0 + ldr r2, [r8, #0] + ldreq r4, [sp, #60] + beq .L13331 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #60] + mov r4, #0 +.L13332: + movs r3, ip, lsr #24 + beq .L13333 + ldr r2, [lr, #0] + ldr r7, [sp, #24] + tst r2, #256 + orr r1, r7, r3 + orr r0, r7, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13333: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13332 + ldr ip, [sp, #60] + add r4, ip, r5, asl #2 +.L13331: + ldr r0, [sp, #80] + sub r8, r8, #64 + rsb r7, r5, r0 + b .L13288 +.L12950: + ldr r2, [sp, #80] + rsb r5, lr, #8 + cmp r2, r5 + blt .L13665 + cmp lr, #3 + bls .L12991 + cmp r5, #0 + ldr r2, [r7, #4] + ldreq r4, [sp, #60] + beq .L12995 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12996: + ands r3, ip, #255 + beq .L12997 + ldr r2, [lr, #0] + ldr r8, [sp, #24] + tst r2, #256 + orr r1, r8, r3 + orr r0, r8, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12997: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L12996 + ldr ip, [sp, #60] + add r4, ip, r5, asl #2 +.L12995: + ldr r0, [sp, #80] + add r7, r7, #64 + rsb r6, r5, r0 + b .L12952 +.L12542: + ldr r8, [sp, #80] + rsb r5, r3, #8 + cmp r8, r5 + blt .L13666 + cmp r5, #0 + ldr r2, [r7, #0] + ldreq r4, [sp, #60] + beq .L12557 + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12558: + ands r3, ip, #15 + beq .L12559 + ldr r1, [lr, #0] + orr r2, r6, r3 + ldr r3, [sp, #24] + ldr r8, [sp, #24] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r8, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L12559: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L12558 + ldr r9, [sp, #60] + add r4, r9, r5, asl #2 +.L12557: + ldr ip, [sp, #80] + add r7, r7, #32 + rsb sl, r5, ip + b .L12544 +.L13659: + cmp r6, #0 + ldr r1, [r4, #4] + ldreq r1, [sp, #60] + beq .L13103 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, lsr r3 + ldr lr, [sp, #60] + mov r5, #0 +.L13104: + ands r3, ip, #255 + beq .L13105 + ldr r2, [lr, #0] + ldr r8, [sp, #24] + tst r2, #256 + orr r1, r8, r3 + orr r0, r8, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13105: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L13104 + ldr ip, [sp, #60] + add r4, r4, #64 + add r1, ip, r6, asl #2 + b .L13098 +.L13666: + cmp r8, #0 + ble .L12455 + ldr r2, [ip, r0] + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12549: + ands r3, ip, #15 + beq .L12550 + ldr r1, [lr, #0] + ldr r9, [sp, #24] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r9, r2 + mov r3, r3, asl #16 + orr r2, r9, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L12550: + ldr sl, [sp, #80] + add r4, r4, #1 + cmp sl, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L12549 + b .L12455 +.L13657: + cmp r6, #0 + ldr r1, [r4, #0] + ldreq r0, [sp, #60] + beq .L13439 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #60] + mov r5, #0 +.L13440: + movs r3, ip, lsr #24 + beq .L13441 + ldr r2, [lr, #0] + ldr r8, [sp, #24] + tst r2, #256 + orr r1, r8, r3 + orr r0, r8, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13441: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13440 + ldr ip, [sp, #60] + sub r4, r4, #64 + add r0, ip, r6, asl #2 + b .L13434 +.L13664: + cmp r3, #0 + ble .L12455 + cmp lr, #3 + bls .L13292 + mov r3, lr, asl #3 + ldr r2, [r8, #0] + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #60] + mov r4, #0 +.L13295: + movs r3, ip, lsr #24 + beq .L13296 + ldr r2, [lr, #0] + ldr r5, [sp, #24] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13296: + ldr r6, [sp, #80] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13295 + b .L12455 +.L13665: + cmp r2, #0 + ble .L12455 + cmp lr, #3 + bls .L12956 + mov r3, lr, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12959: + ands r3, ip, #255 + beq .L12960 + ldr r2, [lr, #0] + ldr r5, [sp, #24] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12960: + ldr r6, [sp, #80] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L12959 + b .L12455 +.L13663: + cmp r2, #0 + ble .L12455 + ldr r2, [ip, #0] + mov r3, r4, asl #2 + mov ip, r2, asl r3 + ldr lr, [sp, #60] + mov r4, #0 +.L12753: + movs r3, ip, lsr #28 + beq .L12754 + ldr r1, [lr, #0] + orr r2, r6, r3 + ldr r3, [sp, #24] + ldr r5, [sp, #24] + orr r0, r3, r2 + mov r3, r1, lsr #16 + mov r3, r3, asl #16 + orr r2, r5, r2 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L12754: + ldr r7, [sp, #80] + add r4, r4, #1 + cmp r7, r4 + mov ip, ip, asl #4 + add lr, lr, #4 + bne .L12753 + b .L12455 +.L13669: + mov r6, #0 + b .L12520 +.L13668: + mov r4, #0 + b .L12480 +.L13327: + subs r6, r5, #4 + ldr r2, [r8, #4] + ldreq r2, [sp, #60] + beq .L13341 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #60] + mov r4, #0 +.L13342: + movs r3, ip, lsr #24 + beq .L13343 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13343: + add r4, r4, #1 + cmp r4, r6 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13342 + ldr sl, [sp, #60] + add r3, sl, r5, asl #2 + sub r2, r3, #16 +.L13341: + ldr r1, [r8, #0] + cmp r1, #0 + beq .L13349 + ands r0, r1, #255 + beq .L13351 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L13351: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L13355 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L13355: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L13359 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r7, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r7, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L13359: + movs r1, r1, lsr #24 + beq .L13349 + ldr r3, [r2, #0] + tst r3, #256 + beq .L13364 + mov r3, r3, lsr #16 + ldr sl, [sp, #24] + mov r3, r3, asl #16 + orr r3, sl, r3 + orr r3, r1, r3 + str r3, [r2, #0] +.L13349: + add r4, r2, #16 + b .L13331 +.L12991: + subs r6, r5, #4 + ldr r2, [r7, #0] + ldreq r2, [sp, #60] + beq .L13005 + mov r3, lr, asl #3 + mov ip, r2, lsr r3 + ldr lr, [sp, #60] + mov r4, #0 +.L13006: + ands r3, ip, #255 + beq .L13007 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13007: + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L13006 + ldr sl, [sp, #60] + add r3, sl, r5, asl #2 + sub r2, r3, #16 +.L13005: + ldr r1, [r7, #4] + cmp r1, #0 + beq .L13013 + ands r0, r1, #255 + beq .L13015 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne ip, [sp, #24] + ldreq lr, [sp, #24] + movne r3, r3, asl #16 + orrne r3, ip, r3 + orreq r3, lr, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L13015: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L13019 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r4, [sp, #24] + ldreq r6, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r6, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L13019: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L13023 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + ldrne r8, [sp, #24] + ldreq r9, [sp, #24] + movne r3, r3, asl #16 + orrne r3, r8, r3 + orreq r3, r9, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r0, r3 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L13023: + movs r1, r1, lsr #24 + beq .L13013 + ldr r3, [r2, #12] + tst r3, #256 + beq .L13028 + mov r3, r3, lsr #16 + ldr sl, [sp, #24] + mov r3, r3, asl #16 + orr r3, sl, r3 + orr r3, r1, r3 + str r3, [r2, #12] +.L13013: + add r4, r2, #16 + b .L12995 +.L13667: + mov lr, r7 + b .L13631 +.L13292: + ldr r7, [sp, #80] + mov r3, lr, asl #3 + ldr r1, [r8, #4] + add r2, r7, lr + sub r3, r3, #32 + cmp r2, #4 + mov ip, r1, asl r3 + bhi .L13301 + cmp r7, #0 + ldrne lr, [sp, #60] + movne r4, #0 + beq .L12455 +.L13321: + movs r3, ip, lsr #24 + beq .L13322 + ldr r2, [lr, #0] + ldr r5, [sp, #24] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13322: + ldr r6, [sp, #80] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13321 + b .L12455 +.L12956: + ldr r8, [sp, #80] + ldr r3, [r7, #0] + add r2, r8, lr + mov r1, lr, asl #3 + cmp r2, #4 + mov ip, r3, lsr r1 + bhi .L12965 + cmp r8, #0 + ldrne lr, [sp, #60] + movne r4, #0 + beq .L12455 +.L12985: + ands r3, ip, #255 + beq .L12986 + ldr r2, [lr, #0] + ldr r5, [sp, #24] + tst r2, #256 + orr r1, r5, r3 + orr r0, r5, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12986: + ldr r6, [sp, #80] + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L12985 + b .L12455 +.L12965: + rsbs r5, lr, #4 + ldreq lr, [sp, #60] + beq .L12970 + ldr lr, [sp, #60] + mov r4, #0 +.L12971: + ands r3, ip, #255 + beq .L12972 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12972: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L12971 + ldr sl, [sp, #60] + add lr, sl, r5, asl #2 +.L12970: + ldr ip, [sp, #80] + subs r5, ip, r5 + ldr ip, [r7, #4] + beq .L12455 + mov r4, #0 +.L12979: + ands r3, ip, #255 + beq .L12980 + ldr r2, [lr, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L12980: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L12979 + b .L12455 +.L13301: + rsbs r5, lr, #4 + ldreq lr, [sp, #60] + beq .L13306 + ldr lr, [sp, #60] + mov r4, #0 +.L13307: + movs r3, ip, lsr #24 + beq .L13308 + ldr r2, [lr, #0] + ldr r9, [sp, #24] + tst r2, #256 + orr r1, r9, r3 + orr r0, r9, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13308: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13307 + ldr sl, [sp, #60] + add lr, sl, r5, asl #2 +.L13306: + ldr ip, [sp, #80] + subs r5, ip, r5 + ldr ip, [r8, #0] + beq .L12455 + mov r4, #0 +.L13315: + movs r3, ip, lsr #24 + beq .L13316 + ldr r2, [lr, #0] + ldr r0, [sp, #24] + tst r2, #256 + orr r1, r0, r3 + orr r0, r0, r3 + mov r3, r2, lsr #16 + mov r3, r3, asl #16 + orr r3, r3, r1 + orr r1, r0, r2, asl #16 + strne r3, [lr, #0] + streq r1, [lr, #0] +.L13316: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L13315 + b .L12455 +.L13136: + ldr lr, [sp, #24] + orr r3, lr, r3, asl #16 + orr r3, r2, r3 + str r3, [r1, #12] + add r1, r1, #16 + b .L13103 +.L13472: + ldr lr, [sp, #24] + add r0, r1, #16 + orr r3, lr, r3, asl #16 + orr r3, r2, r3 + str r3, [r1, #0] + b .L13439 +.L13364: + ldr lr, [sp, #24] + add r4, r2, #16 + orr r3, lr, r3, asl #16 + orr r3, r1, r3 + str r3, [r2, #0] + b .L13331 +.L13028: + ldr lr, [sp, #24] + add r4, r2, #16 + orr r3, lr, r3, asl #16 + orr r3, r1, r3 + str r3, [r2, #12] + b .L12995 + .size render_scanline_obj_alpha_obj_2D, .-render_scanline_obj_alpha_obj_2D + .align 2 + .global render_scanline_obj_partial_alpha_1D + .type render_scanline_obj_partial_alpha_1D, %function +render_scanline_obj_partial_alpha_1D: + @ args = 0, pretend = 0, frame = 148 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L15733 + sub sp, sp, #148 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #40] + ldr r5, [sp, #40] + ldrh r4, [ip, #80] + ldr ip, .L15733+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #44] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L15733+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #48] + str r1, [sp, #8] + str r2, [sp, #4] + str r3, [sp, #0] + str lr, [sp, #28] + beq .L15634 + mov ip, #0 + add r7, r3, r1, asl #2 + rsb r8, r1, r2 + str r7, [sp, #108] + str r8, [sp, #144] + str ip, [sp, #32] + mov lr, ip +.L13677: + ldr r0, [sp, #48] + ldr r1, .L15733+12 + ldrb r3, [lr, r0] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh lr, [r3, r1] + add r3, r3, r1 + ldrh r4, [r3, #2] + mov r0, lr, lsr #12 + and r2, r0, #12 + ldrh r3, [r3, #4] + orr r1, r2, r4, lsr #14 + and ip, lr, #255 + mov r2, r4, asl #23 + cmp ip, #160 + str r3, [sp, #36] + mov r5, r2, asr #23 + ldr r3, .L15733+16 + ldr r2, .L15733+20 + subgt ip, ip, #256 + tst lr, #3072 + ldr r7, [r2, r1, asl #2] + ldr sl, [r3, r1, asl #2] + beq .L13680 + tst lr, #256 + beq .L13682 + tst lr, #8192 + beq .L13684 + mov r3, r4, lsr #4 + ldr r4, .L15733+12 + add r2, r7, r7, lsr #31 + and r3, r3, #992 + tst lr, #512 + add r3, r3, r4 + mov lr, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + ldrh r9, [r3, #30] + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq r6, r7 + moveq fp, lr + moveq r0, r4 + movne r6, r7, asl #1 + movne fp, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + str r3, [sp, #12] + bge .L13689 + rsb r2, r5, r2 + rsb r6, r2, r6 + cmp r6, #0 + ble .L13691 + ldr r5, [sp, #8] + rsb fp, r2, fp +.L13689: + ldr r2, [sp, #4] + add r3, r5, r6 + cmp r3, r2 + blt .L13693 + rsb r6, r5, r2 + cmp r6, #0 + ble .L13691 +.L13693: + mov r2, r1, asl #16 + mov r3, r8, asl #16 + mov r2, r2, asr #16 + ldr r8, [sp, #12] + add r0, ip, r0 + str r2, [sp, #52] + ldr ip, [sp, #0] + ldr r2, [sp, #40] + mov r1, r9, asl #16 + mov lr, lr, asl #8 + cmp r8, #0 + str lr, [sp, #128] + mov r9, r3, asr #16 + mov r1, r1, asr #16 + mov r4, r4, asl #8 + add r5, ip, r5, asl #2 + rsb lr, r0, r2 + bne .L13695 + mla r3, lr, r1, r4 + mov r2, r3, asr #8 + cmp r2, sl + bcs .L13691 + cmp r7, #0 + ldr r4, [sp, #36] + add r3, r7, #7 + movge r3, r7 + mov r1, r4, asl #22 + mov r3, r3, asr #3 + mov r0, r2, lsr #3 + mov r3, r3, asl #1 + mov r1, r1, lsr #22 + mla ip, r3, r0, r1 + and r2, r2, #7 + ldr r8, .L15733+24 + add r2, r2, ip, asl #2 + cmp r6, #0 + add r4, r8, r2, asl #3 + ble .L13691 + ldr r3, [sp, #52] + mul r2, r9, fp + mul r3, lr, r3 + ldr ip, [sp, #128] + rsb r3, r2, r3 + add r0, ip, r3 + mov r2, r0, asr #8 + cmp r2, r7 + ldrcs ip, [sp, #12] + bcs .L13701 + b .L15725 +.L13702: + cmp r2, r7 + bcc .L15660 +.L13701: + add ip, ip, #1 + add r0, r0, r9 + cmp r6, ip + mov r2, r0, asr #8 + add r5, r5, #4 + bne .L13702 +.L13691: + ldr r0, [sp, #32] + ldr r1, [sp, #44] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #32] + beq .L15634 +.L15686: + ldr lr, [sp, #32] + b .L13677 +.L13680: + tst lr, #256 + beq .L14852 + tst lr, #8192 + beq .L14854 + mov r3, r4, lsr #4 + ldr r4, .L15733+12 + add r1, sl, sl, lsr #31 + and r3, r3, #992 + add r3, r3, r4 + add r2, r7, r7, lsr #31 + mov r4, r1, asr #1 + ldr r1, [sp, #8] + tst lr, #512 + ldrh r8, [r3, #30] + mov lr, r2, asr #1 + moveq r9, r7 + moveq r6, lr + moveq r0, r4 + movne r9, r7, asl #1 + movne r6, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r1 + str r8, [sp, #20] + ldrh r2, [r3, #14] + ldrh r8, [r3, #6] + ldrh fp, [r3, #22] + bge .L14859 + rsb r1, r5, r1 + rsb r9, r1, r9 + cmp r9, #0 + ble .L13691 + ldr r5, [sp, #8] + rsb r6, r1, r6 +.L14859: + ldr r1, [sp, #4] + add r3, r5, r9 + cmp r3, r1 + blt .L14862 + rsb r9, r5, r1 + cmp r9, #0 + ble .L13691 +.L14862: + mov r2, r2, asl #16 + mov r3, r8, asl #16 + mov r2, r2, asr #16 + ldr r8, [sp, #20] + mov lr, lr, asl #8 + str r2, [sp, #76] + str lr, [sp, #80] + ldr r2, [sp, #40] + ldr lr, [sp, #0] + add r0, ip, r0 + mov r1, r8, asl #16 + mov r3, r3, asr #16 + cmp fp, #0 + add r8, lr, r5, asl #2 + str r3, [sp, #72] + mov r1, r1, asr #16 + mov ip, r4, asl #8 + rsb lr, r0, r2 + bne .L14864 + mla r3, lr, r1, ip + mov r2, r3, asr #8 + cmp r2, sl + bcs .L13691 + cmp r7, #0 + ldr r4, [sp, #36] + add r3, r7, #7 + movge r3, r7 + mov r1, r4, asl #22 + mov r3, r3, asr #3 + mov r0, r2, lsr #3 + mov r3, r3, asl #1 + mov r1, r1, lsr #22 + mla ip, r3, r0, r1 + and r2, r2, #7 + ldr r5, .L15733+24 + add r2, r2, ip, asl #2 + cmp r9, #0 + add r4, r5, r2, asl #3 + ble .L13691 + ldr r3, [sp, #76] + ldr r2, [sp, #72] + mul r3, lr, r3 + mul r2, r6, r2 + ldr ip, [sp, #80] + rsb r3, r2, r3 + add r0, ip, r3 + mov lr, r0, asr #8 + cmp lr, r7 + movcs ip, fp + bcs .L14870 + b .L15726 +.L14871: + cmp lr, r7 + bcc .L15672 +.L14870: + ldr lr, [sp, #72] + add ip, ip, #1 + add r0, r0, lr + cmp r9, ip + mov lr, r0, asr #8 + add r8, r8, #4 + bne .L14871 + ldr r0, [sp, #32] + ldr r1, [sp, #44] + add r0, r0, #1 + cmp r0, r1 + str r0, [sp, #32] + bne .L15686 +.L15634: + add sp, sp, #148 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L13682: + ldr r1, [sp, #40] + tst r4, #8192 + rsb ip, ip, r1 + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r4, asl #19 + and r3, r0, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L13691 + .p2align 2 +.L13771: + .word .L13767 + .word .L13768 + .word .L13769 + .word .L13770 +.L14852: + ldr lr, [sp, #40] + tst r4, #8192 + rsb ip, ip, lr + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r4, asl #19 + and r3, r0, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L13691 + .p2align 2 +.L14933: + .word .L14929 + .word .L14930 + .word .L14931 + .word .L14932 +.L14854: + mov r3, r4, lsr #4 + ldr r1, .L15733+12 + and r3, r3, #992 + add r3, r3, r1 + ldrh r4, [r3, #30] + add r1, sl, sl, lsr #31 + add r2, r7, r7, lsr #31 + str r4, [sp, #24] + mov r4, r1, asr #1 + ldr r1, [sp, #8] + tst lr, #512 + mov lr, r2, asr #1 + moveq fp, r7 + moveq r6, lr + moveq r0, r4 + movne fp, r7, asl #1 + movne r6, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r1 + ldrh r8, [r3, #6] + ldrh r2, [r3, #14] + ldrh r9, [r3, #22] + bge .L14891 + rsb r1, r5, r1 + rsb fp, r1, fp + cmp fp, #0 + ble .L13691 + ldr r5, [sp, #8] + rsb r6, r1, r6 +.L14891: + ldr r1, [sp, #4] + add r3, r5, fp + cmp r3, r1 + blt .L14894 + rsb fp, r5, r1 + cmp fp, #0 + ble .L13691 +.L14894: + mov r3, r8, asl #16 + ldr r8, [sp, #24] + mov r2, r2, asl #16 + mov r1, r8, asl #16 + ldr r8, [sp, #36] + mov r2, r2, asr #16 + mov lr, lr, asl #8 + add ip, ip, r0 + str r2, [sp, #92] + mov r0, r8, lsr #8 + str lr, [sp, #100] + ldr r2, [sp, #40] + ldr lr, [sp, #0] + mov r3, r3, asr #16 + and r0, r0, #240 + cmp r9, #0 + add r8, lr, r5, asl #2 + str r3, [sp, #88] + mov r1, r1, asr #16 + mov r4, r4, asl #8 + rsb lr, ip, r2 + str r0, [sp, #136] + bne .L14896 + mla r3, lr, r1, r4 + mov r3, r3, asr #8 + cmp r3, sl + bcs .L13691 + ldr r4, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r1, r4, asl #22 + movge r2, r7 + mov r1, r1, lsr #22 + mov r0, r3, lsr #3 + mov r2, r2, asr #3 + mla ip, r2, r0, r1 + and r3, r3, #7 + ldr r5, .L15733+24 + add r3, r3, ip, asl #3 + cmp fp, #0 + add r1, r5, r3, asl #2 + ble .L13691 + ldr r3, [sp, #92] + ldr r2, [sp, #88] + mul r3, lr, r3 + mul r2, r6, r2 + ldr ip, [sp, #100] + rsb r3, r2, r3 + add r0, ip, r3 + mov r3, r0, asr #8 + cmp r3, r7 + mov lr, r3 + movcs r4, r9 + bcs .L14902 + b .L15727 +.L14903: + cmp r3, r7 + bcc .L14904 +.L14902: + ldr lr, [sp, #88] + add r4, r4, #1 + add r0, r0, lr + mov r3, r0, asr #8 + cmp fp, r4 + add r8, r8, #4 + mov lr, r3 + bne .L14903 + b .L13691 +.L13684: + mov r3, r4, lsr #4 + ldr r4, .L15733+12 + add r2, r7, r7, lsr #31 + and r3, r3, #992 + tst lr, #512 + add r3, r3, r4 + mov lr, r2, asr #1 + add r1, sl, sl, lsr #31 + ldr r2, [sp, #8] + mov r4, r1, asr #1 + ldrh r9, [r3, #30] + ldrh r8, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, r7 + moveq r6, lr + moveq r0, r4 + movne fp, r7, asl #1 + movne r6, lr, asl #1 + movne r0, r4, asl #1 + cmp r5, r2 + str r3, [sp, #16] + bge .L13726 + rsb r2, r5, r2 + rsb fp, r2, fp + cmp fp, #0 + ble .L13691 + ldr r5, [sp, #8] + rsb r6, r2, r6 +.L13726: + ldr r2, [sp, #4] + add r3, r5, fp + cmp r3, r2 + blt .L13729 + rsb fp, r5, r2 + cmp fp, #0 + ble .L13691 +.L13729: + mov r3, r8, asl #16 + ldr r8, [sp, #16] + mov r2, r1, asl #16 + cmp r8, #0 + ldr r8, [sp, #36] + mov lr, lr, asl #8 + add ip, ip, r0 + str lr, [sp, #132] + mov r0, r8, lsr #8 + ldr lr, [sp, #0] + mov r8, r2, asr #16 + ldr r2, [sp, #40] + mov r1, r9, asl #16 + mov r3, r3, asr #16 + and r0, r0, #240 + add r9, lr, r5, asl #2 + str r3, [sp, #60] + mov r1, r1, asr #16 + mov r4, r4, asl #8 + rsb lr, ip, r2 + str r0, [sp, #140] + bne .L13731 + mla r3, lr, r1, r4 + mov r3, r3, asr #8 + cmp r3, sl + bcs .L13691 + ldr r4, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r1, r4, asl #22 + movge r2, r7 + mov r0, r3, lsr #3 + mov r1, r1, lsr #22 + mov r2, r2, asr #3 + mla ip, r2, r0, r1 + and r3, r3, #7 + add r3, r3, ip, asl #3 + ldr ip, .L15733+24 + cmp fp, #0 + add r5, ip, r3, asl #2 + ble .L13691 + ldr r2, [sp, #60] + mul r3, lr, r8 + mul r2, r6, r2 + ldr lr, [sp, #132] + rsb r3, r2, r3 + add ip, lr, r3 + mov r1, ip, asr #8 + cmp r1, r7 + ldrcs lr, [sp, #16] + bcs .L13737 + b .L15728 +.L13738: + cmp r1, r7 + bcc .L15662 +.L13737: + ldr r0, [sp, #60] + add lr, lr, #1 + add ip, ip, r0 + cmp fp, lr + mov r1, ip, asr #8 + add r9, r9, #4 + bne .L13738 + b .L13691 +.L13740: + cmp r1, r7 + bcs .L13691 +.L15662: + mov r3, r1, asr #1 + and r4, r3, #3 + mov r3, r1, asr #3 + mov r3, r3, asl #5 + mov r2, r1, asr #1 + and r0, r2, #3 + tst r1, #1 + add r2, r3, r5 + add r1, r3, r5 + ldrneb r3, [r1, r4] @ zero_extendqisi2 + ldreqb r3, [r2, r0] @ zero_extendqisi2 + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr r1, [sp, #140] + cmp r0, #0 + orr r0, r0, r1 + beq .L13745 + ldr r2, [r9, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r9, #0] + streq r0, [r9, #0] +.L13745: + ldr r2, [sp, #60] + add lr, lr, #1 + add ip, ip, r2 + cmp fp, lr + add r9, r9, #4 + mov r1, ip, asr #8 + bgt .L13740 + b .L13691 +.L13731: + ldr r5, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r3, r5, asl #22 + movge r2, r7 + ldr ip, .L15733+24 + mov r3, r3, lsr #22 + mov r2, r2, asr #3 + add r3, ip, r3, asl #5 + mov r2, r2, asl #5 + cmp fp, #0 + str r3, [sp, #120] + str r2, [sp, #68] + ble .L13691 + ldr r0, [sp, #16] + mul r2, lr, r1 + mov r3, r0, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #64] + ldr r1, [sp, #64] + ldr r0, [sp, #60] + mul r1, r6, r1 + mul r3, lr, r8 + mul r0, r6, r0 + rsb r2, r1, r2 + ldr r1, [sp, #132] + rsb r3, r0, r3 + add r5, r4, r2 + add r6, r1, r3 + mov r4, r6, asr #8 + mov r3, r5, asr #8 + cmp r4, r7 + cmpcc r3, sl + movcs r2, #0 + movcc r2, #1 + movcs r8, r2 + bcs .L13752 + b .L15729 +.L13753: + cmp r4, r7 + cmpcc r3, sl + bcc .L13754 +.L13752: + ldr r3, [sp, #64] + ldr r2, [sp, #60] + add r8, r8, #1 + add r6, r6, r2 + add r5, r5, r3 + cmp fp, r8 + mov r4, r6, asr #8 + mov r3, r5, asr #8 + add r9, r9, #4 + bne .L13753 + b .L13691 +.L14896: + ldr r0, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r3, r0, asl #22 + movge r2, r7 + ldr r5, .L15733+24 + mov r3, r3, lsr #22 + mov r2, r2, asr #3 + add r3, r5, r3, asl #5 + mov r2, r2, asl #5 + cmp fp, #0 + str r3, [sp, #112] + str r2, [sp, #104] + ble .L13691 + mov r3, r9, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #96] + mul r2, lr, r1 + ldr r3, [sp, #92] + ldr r1, [sp, #96] + ldr r0, [sp, #88] + mul r3, lr, r3 + mul r1, r6, r1 + mul r0, r6, r0 + ldr ip, [sp, #100] + rsb r2, r1, r2 + rsb r3, r0, r3 + add r5, ip, r3 + add r4, r4, r2 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + cmp lr, r7 + cmpcc r2, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L14916 + b .L15730 +.L14917: + cmp lr, r7 + cmpcc r2, sl + bcc .L14918 +.L14916: + ldr lr, [sp, #88] + ldr r0, [sp, #96] + add r6, r6, #1 + add r5, r5, lr + add r4, r4, r0 + cmp fp, r6 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + add r8, r8, #4 + bne .L14917 + b .L13691 +.L14873: + cmp lr, r7 + bcs .L13691 +.L15672: + ldr r1, [sp, #72] + mov r3, lr, asr #3 + add r0, r0, r1 + add r3, r4, r3, asl #6 + and r1, lr, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #28] + cmp r2, #0 + add ip, ip, #1 + orr r3, r5, r2 + strne r3, [r8, #0] + cmp r9, ip + mov lr, r0, asr #8 + add r8, r8, #4 + bgt .L14873 + b .L13691 +.L13704: + cmp r2, r7 + bcs .L13691 +.L15660: + mov r3, r2, asr #3 + add r3, r4, r3, asl #6 + and r2, r2, #7 + ldrb lr, [r3, r2] @ zero_extendqisi2 + cmp lr, #0 + beq .L13706 + ldr r3, [r5, #0] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r1, lr, r3, asl #16 + orr r2, r2, #768 + tst r3, #256 + orr r2, lr, r2 + orr r1, r1, #768 + strne r2, [r5, #0] + streq r1, [r5, #0] +.L13706: + add ip, ip, #1 + add r0, r0, r9 + cmp r6, ip + add r5, r5, #4 + mov r2, r0, asr #8 + bgt .L13704 + b .L13691 +.L13695: + ldr r0, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r3, r0, asl #22 + movge r2, r7 + ldr r8, .L15733+24 + mov r3, r3, lsr #22 + mov r2, r2, asr #3 + add r3, r8, r3, asl #5 + mov r2, r2, asl #6 + cmp r6, #0 + str r3, [sp, #124] + str r2, [sp, #56] + ble .L13691 + ldr ip, [sp, #12] + mul r2, lr, r1 + mov r3, ip, asl #16 + mov r8, r3, asr #16 + ldr r3, [sp, #52] + mul r1, r8, fp + mul r3, lr, r3 + mul r0, r9, fp + ldr lr, [sp, #128] + rsb r3, r0, r3 + rsb r2, r1, r2 + add ip, lr, r3 + add lr, r4, r2 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + cmp r1, r7 + cmpcc r0, sl + movcs r3, #0 + movcc r3, #1 + movcs r4, r3 + bcs .L13713 + b .L15731 +.L13714: + cmp r1, r7 + cmpcc r0, sl + bcc .L13715 +.L13713: + add r4, r4, #1 + add ip, ip, r9 + add lr, lr, r8 + cmp r6, r4 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + add r5, r5, #4 + bne .L13714 + b .L13691 +.L14864: + ldr r0, [sp, #36] + cmp r7, #0 + add r2, r7, #7 + mov r3, r0, asl #22 + movge r2, r7 + ldr r4, .L15733+24 + mov r3, r3, lsr #22 + mov r2, r2, asr #3 + add r3, r4, r3, asl #5 + mov r2, r2, asl #6 + cmp r9, #0 + str r3, [sp, #116] + str r2, [sp, #84] + ble .L13691 + mov r3, fp, asl #16 + mov fp, r3, asr #16 + ldr r0, [sp, #72] + ldr r3, [sp, #76] + mul r2, lr, r1 + mul r3, lr, r3 + mul r1, fp, r6 + mul r0, r6, r0 + ldr lr, [sp, #80] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, lr, r3 + add ip, ip, r2 + mov r4, r5, asr #8 + mov lr, ip, asr #8 + cmp r4, r7 + cmpcc lr, sl + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L14880 + b .L15732 +.L14881: + cmp r4, r7 + cmpcc lr, sl + bcc .L14882 +.L14880: + ldr r0, [sp, #72] + add r6, r6, #1 + add r5, r5, r0 + add ip, ip, fp + cmp r9, r6 + mov r4, r5, asr #8 + mov lr, ip, asr #8 + add r8, r8, #4 + bne .L14881 + b .L13691 +.L14929: + ldr r0, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r2, r0, asl #22 + movge r3, r7 + mov r4, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r4, r3, r2 + ldr r8, [sp, #36] + ldr r2, [sp, #8] + and r1, ip, #7 + ldr ip, .L15733+24 + add r1, r1, r0, asl #3 + mov r3, r8, lsr #8 + cmp r5, r2 + and r6, r3, #240 + add r0, ip, r1, asl #2 + bge .L14934 + rsb lr, r5, r2 + rsb r4, lr, r7 + cmp r4, #0 + ble .L13691 + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bhi .L14937 + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add r4, r0, r1 + bne .L14939 + ldr r5, [sp, #144] + ldr r7, [sp, #108] +.L14941: + movs lr, r5, lsr #3 + beq .L14958 + mov r1, r7 + mov r0, r4 + mov ip, #0 +.L14960: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L14961 + ands r3, r2, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #28 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r1, #28] +.L14961: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #32 + add r1, r1, #32 + bne .L14960 + mov r3, lr, asl #5 + add r4, r4, r3 + add r7, r7, r3 +.L14958: + ands r0, r5, #7 + beq .L13691 + ldr r2, [r4, #0] + mov r1, #0 +.L14980: + ldr r4, [sp, #28] + ands r3, r2, #15 + orr r3, r4, r3 + orr r3, r6, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #4 + bne .L14980 + b .L13691 +.L14930: + ldr lr, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r2, lr, asl #22 + movge r3, r7 + mov r4, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, r4, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + add r0, r0, r3, asr #3 + and r2, ip, #7 + add r2, r2, r0, asl #3 + ldr r0, [sp, #8] + ldr r1, .L15733+24 + cmp r5, r0 + mov r3, lr, lsr #8 + and r6, r3, #240 + add r0, r1, r2, asl #2 + bge .L15064 + ldr r2, [sp, #8] + rsb lr, r5, r2 + rsb r1, lr, r7 + cmp r1, #0 + ble .L13691 + ldr r4, [sp, #4] + add r3, r5, r7 + cmp r4, r3 + bhi .L15067 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub r0, r0, r3, asl #5 + bne .L15069 + ldr r2, [sp, #144] + ldr r1, [sp, #108] +.L15071: + movs r8, r2, lsr #3 + beq .L15088 + mov r4, r1 + mov r5, r0 + mov r7, #0 +.L15090: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L15091 + ands r3, lr, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + movs r3, lr, lsr #28 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] +.L15091: + add r7, r7, #1 + cmp r7, r8 + sub r5, r5, #32 + add r4, r4, #32 + bne .L15090 + rsb r3, r8, r8, asl #27 + add r0, r0, r3, asl #5 + add r1, r1, r8, asl #5 +.L15088: + ands lr, r2, #7 + beq .L13691 + ldr r0, [r0, #0] + mov r2, #0 +.L15110: + ldr r4, [sp, #28] + movs r3, r0, lsr #28 + orr r3, r4, r3 + orr r3, r6, r3 + strne r3, [r1, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r0, r0, asl #4 + bne .L15110 + b .L13691 +.L15734: + .align 2 +.L15733: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 +.L14931: + ldr lr, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r2, ip, lsr #3 + movge r3, r7 + mov r1, lr, asl #22 + mov r4, r3, asr #3 + mov r2, r2, asl #1 + mov r1, r1, lsr #22 + mla r0, r2, r4, r1 + and r3, ip, #7 + ldr r1, [sp, #8] + add r3, r3, r0, asl #2 + ldr r2, .L15733+24 + mov r0, r3, asl #3 + cmp r5, r1 + add ip, r0, r2 + bge .L15194 + rsb r0, r5, r1 + rsb lr, r0, r7 + cmp lr, #0 + ble .L13691 + ldr r4, [sp, #4] + add r3, r5, r7 + cmp r4, r3 + bhi .L15197 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r6, ip, r3, asl #6 + bne .L15199 + ldr r5, [sp, #144] + ldr r4, [sp, #108] +.L15201: + movs lr, r5, lsr #3 + beq .L15259 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L15261: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L15262 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #12] +.L15262: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L15271 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #28] +.L15271: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #64 + add r1, r1, #32 + bne .L15261 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #5 +.L15259: + ands r0, r5, #7 + beq .L13691 + cmp r0, #3 + ldrls r1, [r6, #0] + bls .L15294 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L15284 + ands r3, r2, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r1, r3 + strne r3, [r4, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #12] +.L15284: + subs r0, r0, #4 + ldr r1, [r6, #4] + addne r4, r4, #16 + beq .L13691 +.L15294: + mov r2, #0 +.L15295: + ldr r5, [sp, #28] + ands r3, r1, #255 + orr r3, r5, r3 + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bhi .L15295 + b .L13691 +.L13769: + ldr r4, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r1, r4, asl #22 + movge r3, r7 + mov r2, ip, lsr #3 + mov r4, r3, asr #3 + mov r2, r2, asl #1 + mov r1, r1, lsr #22 + mla r0, r2, r4, r1 + and r3, ip, #7 + ldr r8, [sp, #8] + add r3, r3, r0, asl #2 + ldr lr, .L15733+24 + mov r0, r3, asl #3 + cmp r5, r8 + add ip, r0, lr + bge .L14180 + rsb r0, r5, r8 + rsb r8, r0, r7 + cmp r8, #0 + ble .L13691 + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bhi .L14183 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r7, ip, r3, asl #6 + bne .L14185 + ldr r6, [sp, #144] + ldr r4, [sp, #108] +.L14187: + movs r5, r6, lsr #3 + beq .L14265 + mov r0, r4 + mov ip, r7 + mov lr, #0 +.L14267: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L14268 + ands r1, r2, #255 + beq .L14270 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L14270: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14274 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L14274: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14278 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L14278: + movs r2, r2, lsr #24 + beq .L14268 + ldr r1, [r0, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L14268: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L14285 + ands r1, r2, #255 + beq .L14287 + ldr r3, [r0, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L14287: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14291 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L14291: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14295 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L14295: + movs r2, r2, lsr #24 + beq .L14285 + ldr r3, [r0, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L14285: + add lr, lr, #1 + cmp r5, lr + add ip, ip, #64 + add r0, r0, #32 + bne .L14267 + add r7, r7, r5, asl #6 + add r4, r4, r5, asl #5 +.L14265: + ands r5, r6, #7 + beq .L13691 + cmp r5, #3 + ldrls ip, [r7, #0] + bls .L14324 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L14306 + ands r1, r2, #255 + beq .L14308 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L14308: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14312 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L14312: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14316 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L14316: + movs r2, r2, lsr #24 + beq .L14306 + ldr r1, [r4, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L14306: + subs r5, r5, #4 + ldr ip, [r7, #4] + addne r4, r4, #16 + beq .L13691 +.L14324: + mov lr, #0 +.L14325: + ands r0, ip, #255 + beq .L14326 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L14326: + add lr, lr, #1 + cmp lr, r5 + mov ip, ip, lsr #8 + add r4, r4, #4 + bcc .L14325 + b .L13691 +.L13767: + ldr r4, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r2, r4, asl #22 + movge r3, r7 + mov r8, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, r8, r3, r2 + and r1, ip, #7 + ldr ip, [sp, #8] + ldr lr, .L15733+24 + add r1, r1, r0, asl #3 + mov r3, r4, lsr #8 + cmp r5, ip + and r6, r3, #240 + add r0, lr, r1, asl #2 + bge .L13772 + rsb lr, r5, ip + rsb r8, lr, r7 + cmp r8, #0 + ble .L13691 + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bhi .L13775 + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add r8, r0, r1 + bne .L13777 + ldr sl, [sp, #144] + ldr r4, [sp, #108] +.L13779: + movs r7, sl, lsr #3 + beq .L13800 + mov ip, r4 + mov lr, r8 + mov r5, #0 +.L13802: + ldr r0, [lr, #0] + cmp r0, #0 + beq .L13803 + ands r2, r0, #15 + beq .L13805 + ldr r1, [ip, #0] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L13805: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L13809 + ldr r1, [ip, #4] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L13809: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L13813 + ldr r1, [ip, #8] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L13813: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L13817 + ldr r1, [ip, #12] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L13817: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L13821 + ldr r1, [ip, #16] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L13821: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L13825 + ldr r1, [ip, #20] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L13825: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L13829 + ldr r1, [ip, #24] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L13829: + movs r2, r0, lsr #28 + beq .L13803 + ldr r1, [ip, #28] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L13803: + add r5, r5, #1 + cmp r7, r5 + add lr, lr, #32 + add ip, ip, #32 + bne .L13802 + mov r3, r7, asl #5 + add r8, r8, r3 + add r4, r4, r3 +.L13800: + ands r5, sl, #7 + beq .L13691 + ldr ip, [r8, #0] + mov lr, #0 +.L13838: + ands r3, ip, #15 + beq .L13839 + ldr r1, [r4, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L13839: + add lr, lr, #1 + cmp r5, lr + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L13838 + b .L13691 +.L13770: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r6, r2, asr #3 + mov r3, r3, asr #3 + mov r1, ip, lsr #3 + mla r0, r6, r1, r3 + ldr r3, [sp, #36] + ldr r4, [sp, #8] + mov r2, r3, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + and r3, ip, #7 + add r3, r3, r2, asl #2 + ldr r8, .L15733+24 + mov r0, r3, asl #3 + cmp r5, r4 + add ip, r0, r8 + bge .L14516 + rsb r0, r5, r4 + rsb r8, r0, r7 + cmp r8, #0 + ble .L13691 + ldr lr, [sp, #4] + add r3, r5, r7 + cmp lr, r3 + bhi .L14519 + mov r3, r0, lsr #3 + ands lr, r0, #7 + sub r8, ip, r3, asl #6 + bne .L14521 + ldr r7, [sp, #144] + ldr r4, [sp, #108] +.L14523: + movs r6, r7, lsr #3 + beq .L14601 + mov ip, r4 + mov lr, r8 + mov r5, #0 +.L14603: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L14604 + ands r1, r2, #255 + beq .L14606 + ldr r3, [ip, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L14606: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14610 + ldr r3, [ip, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L14610: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14614 + ldr r3, [ip, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L14614: + movs r2, r2, lsr #24 + beq .L14604 + ldr r3, [ip, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L14604: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L14621 + ands r2, r1, #255 + beq .L14623 + ldr r0, [ip, #28] + tst r0, #256 + movne r3, r0, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r0, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L14623: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L14627 + ldr r3, [ip, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L14627: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L14631 + ldr r3, [ip, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L14631: + movs r2, r1, lsr #24 + beq .L14621 + ldr r1, [ip, #16] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L14621: + add r5, r5, #1 + cmp r5, r6 + sub lr, lr, #64 + add ip, ip, #32 + bne .L14603 + rsb r3, r6, r6, asl #26 + add r8, r8, r3, asl #6 + add r4, r4, r6, asl #5 +.L14601: + ands r5, r7, #7 + beq .L13691 + cmp r5, #3 + ldrls ip, [r8, #4] + bls .L14660 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L14642 + ands r1, r2, #255 + beq .L14644 + ldr r3, [r4, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L14644: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14648 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L14648: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14652 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L14652: + movs r2, r2, lsr #24 + beq .L14642 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L14642: + subs r5, r5, #4 + ldr ip, [r8, #0] + addne r4, r4, #16 + beq .L13691 +.L14660: + mov lr, #0 +.L14661: + movs r0, ip, lsr #24 + beq .L14662 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L14662: + add lr, lr, #1 + cmp lr, r5 + mov ip, ip, asl #8 + add r4, r4, #4 + bcc .L14661 + b .L13691 +.L14932: + cmp r7, #0 + add r2, r7, #7 + movge r2, r7 + subs r3, r7, #8 + submi r3, r7, #1 + mov r4, r2, asr #3 + mov r3, r3, asr #3 + mov r1, ip, lsr #3 + mla r0, r4, r1, r3 + ldr r1, [sp, #36] + and r3, ip, #7 + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + add r3, r3, r2, asl #2 + ldr r2, [sp, #8] + mov r0, r3, asl #3 + ldr r3, .L15733+24 + cmp r5, r2 + add r2, r0, r3 + bge .L15414 + ldr r4, [sp, #8] + rsb r0, r5, r4 + rsb lr, r0, r7 + cmp lr, #0 + ble .L13691 + add r3, r5, r7 + ldr r5, [sp, #4] + cmp r5, r3 + bhi .L15417 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r6, r2, r3, asl #6 + bne .L15419 + ldr r5, [sp, #144] + ldr r4, [sp, #108] +.L15421: + movs lr, r5, lsr #3 + beq .L15479 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L15481: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L15482 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] +.L15482: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L15491 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #28] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #24] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #20] + movs r3, r2, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #16] +.L15491: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #32 + bne .L15481 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #5 +.L15479: + ands r0, r5, #7 + beq .L13691 + cmp r0, #3 + ldrls r2, [r6, #4] + bls .L15514 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L15504 + ands r3, r2, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #28] + orrne r3, r1, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #0] +.L15504: + subs r0, r0, #4 + ldr r2, [r6, #0] + addne r4, r4, #16 + beq .L13691 +.L15514: + mov r1, #0 +.L15515: + ldr r5, [sp, #28] + movs r3, r2, lsr #24 + orr r3, r5, r3 + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L15515 + b .L13691 +.L13768: + ldr r4, [sp, #36] + cmp r7, #0 + add r3, r7, #7 + mov r2, r4, asl #22 + movge r3, r7 + mov r8, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, r8, r1, r2 + subs r3, r7, #8 + submi r3, r7, #1 + and r2, ip, #7 + ldr ip, [sp, #8] + add r0, r0, r3, asr #3 + ldr lr, .L15733+24 + add r2, r2, r0, asl #3 + mov r3, r4, lsr #8 + cmp r5, ip + and r6, r3, #240 + add r0, lr, r2, asl #2 + bge .L13976 + rsb lr, r5, ip + rsb r8, lr, r7 + cmp r8, #0 + ble .L13691 + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bhi .L13979 + mov r3, lr, lsr #3 + ands r4, lr, #7 + sub ip, r0, r3, asl #5 + bne .L13981 + ldr sl, [sp, #144] + ldr r5, [sp, #108] +.L13983: + movs r8, sl, lsr #3 + beq .L14004 + mov lr, r5 + mov r4, ip + mov r7, #0 +.L14006: + ldr r0, [r4, #0] + cmp r0, #0 + beq .L14007 + ands r2, r0, #15 + beq .L14009 + ldr r1, [lr, #28] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #28] + streq r3, [lr, #28] +.L14009: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L14013 + ldr r1, [lr, #24] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #24] + streq r3, [lr, #24] +.L14013: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L14017 + ldr r1, [lr, #20] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #20] + streq r3, [lr, #20] +.L14017: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L14021 + ldr r1, [lr, #16] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #16] + streq r3, [lr, #16] +.L14021: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L14025 + ldr r1, [lr, #12] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L14025: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L14029 + ldr r1, [lr, #8] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L14029: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L14033 + ldr r1, [lr, #4] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L14033: + movs r2, r0, lsr #28 + beq .L14007 + ldr r1, [lr, #0] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L14007: + add r7, r7, #1 + cmp r8, r7 + sub r4, r4, #32 + add lr, lr, #32 + bne .L14006 + rsb r3, r8, r8, asl #27 + add ip, ip, r3, asl #5 + add r5, r5, r8, asl #5 +.L14004: + ands r4, sl, #7 + beq .L13691 + ldr ip, [ip, #0] + mov lr, #0 +.L14042: + movs r3, ip, lsr #28 + beq .L14043 + ldr r1, [r5, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L14043: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r5, r5, #4 + bne .L14042 + b .L13691 +.L13976: + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bls .L15693 + cmp r8, #0 + beq .L13691 + ldr r3, [sp, #0] + mov ip, #0 + add r1, r3, r5, asl #2 + b .L14145 +.L15694: + sub r0, r0, #32 + add r1, r1, #32 +.L14145: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L14146 + ands r2, r4, #15 + beq .L14148 + ldr lr, [r1, #28] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L14148: + mov r3, r4, lsr #4 + ands r2, r3, #15 + beq .L14152 + ldr lr, [r1, #24] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L14152: + mov r3, r4, lsr #8 + ands r2, r3, #15 + beq .L14156 + ldr lr, [r1, #20] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L14156: + mov r3, r4, lsr #12 + ands r2, r3, #15 + beq .L14160 + ldr lr, [r1, #16] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L14160: + mov r3, r4, lsr #16 + ands r2, r3, #15 + beq .L14164 + ldr lr, [r1, #12] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L14164: + mov r3, r4, lsr #20 + ands r2, r3, #15 + beq .L14168 + ldr lr, [r1, #8] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L14168: + mov r3, r4, lsr #24 + ands r2, r3, #15 + beq .L14172 + ldr lr, [r1, #4] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L14172: + movs r2, r4, lsr #28 + beq .L14146 + ldr lr, [r1, #0] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L14146: + add ip, ip, #1 + cmp r8, ip + bne .L15694 + b .L13691 +.L14934: + ldr ip, [sp, #4] + add r3, r5, r7 + cmp ip, r3 + bls .L15695 + cmp r4, #0 + beq .L13691 + ldr r3, [sp, #0] + mov r2, #0 + add r1, r3, r5, asl #2 + b .L15045 +.L15696: + add r0, r0, #32 + add r1, r1, #32 +.L15045: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L15046 + ands r3, lr, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #0] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #4] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #8] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r1, #12] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #16] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #20] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #24] + movs r3, lr, lsr #28 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r1, #28] +.L15046: + add r2, r2, #1 + cmp r4, r2 + bne .L15696 + b .L13691 +.L15194: + ldr r8, [sp, #4] + add r3, r5, r7 + cmp r8, r3 + bls .L15697 + cmp r4, #0 + beq .L13691 + ldr lr, [sp, #0] + ldr r3, .L15735+4 + add r1, lr, r5, asl #2 + add r0, r0, r3 + mov r2, #0 + b .L15394 +.L15698: + add ip, ip, #64 + add r1, r1, #32 +.L15394: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L15395 + ands r3, lr, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #0] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #8] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #12] +.L15395: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L15404 + ands r3, lr, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #16] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #24] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #28] +.L15404: + add r2, r2, #1 + cmp r4, r2 + add r0, r0, #64 + bne .L15698 + b .L13691 +.L13772: + ldr r1, [sp, #4] + add r3, r5, r7 + cmp r1, r3 + bls .L15699 + cmp r8, #0 + beq .L13691 + ldr r3, [sp, #0] + mov ip, #0 + add r1, r3, r5, asl #2 + b .L13941 +.L15700: + add r0, r0, #32 + add r1, r1, #32 +.L13941: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L13942 + ands r2, r4, #15 + beq .L13944 + ldr lr, [r1, #0] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L13944: + mov r3, r4, lsr #4 + ands r2, r3, #15 + beq .L13948 + ldr lr, [r1, #4] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L13948: + mov r3, r4, lsr #8 + ands r2, r3, #15 + beq .L13952 + ldr lr, [r1, #8] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L13952: + mov r3, r4, lsr #12 + ands r2, r3, #15 + beq .L13956 + ldr lr, [r1, #12] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L13956: + mov r3, r4, lsr #16 + ands r2, r3, #15 + beq .L13960 + ldr lr, [r1, #16] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L13960: + mov r3, r4, lsr #20 + ands r2, r3, #15 + beq .L13964 + ldr lr, [r1, #20] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L13964: + mov r3, r4, lsr #24 + ands r2, r3, #15 + beq .L13968 + ldr lr, [r1, #24] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L13968: + movs r2, r4, lsr #28 + beq .L13942 + ldr lr, [r1, #28] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L13942: + add ip, ip, #1 + cmp r8, ip + bne .L15700 + b .L13691 +.L15064: + ldr ip, [sp, #4] + add r3, r5, r7 + cmp ip, r3 + bls .L15701 + cmp r4, #0 + beq .L13691 + ldr r3, [sp, #0] + mov r2, #0 + add r1, r3, r5, asl #2 + b .L15175 +.L15702: + sub r0, r0, #32 + add r1, r1, #32 +.L15175: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L15176 + ands r3, lr, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #28] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #24] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #20] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r1, #16] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #12] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #8] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #4] + movs r3, lr, lsr #28 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r1, #0] +.L15176: + add r2, r2, #1 + cmp r4, r2 + bne .L15702 + b .L13691 +.L14516: + ldr r4, [sp, #4] + add r3, r5, r7 + cmp r4, r3 + bls .L15703 + cmp r6, #0 + beq .L13691 + ldr r2, [sp, #0] + ldr r3, .L15735 + add r1, r2, r5, asl #2 + add r0, r0, r3 + mov r5, #0 + b .L14816 +.L15704: + sub ip, ip, #64 + add r1, r1, #32 +.L14816: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L14817 + ands lr, r2, #255 + beq .L14819 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L14819: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14823 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L14823: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14827 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L14827: + movs r2, r2, lsr #24 + beq .L14817 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L14817: + ldr lr, [ip, #0] + cmp lr, #0 + beq .L14834 + ands r2, lr, #255 + beq .L14836 + ldr r4, [r1, #28] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L14836: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L14840 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L14840: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L14844 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L14844: + movs r2, lr, lsr #24 + beq .L14834 + ldr lr, [r1, #16] + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L14834: + add r5, r5, #1 + cmp r6, r5 + sub r0, r0, #64 + bne .L15704 + b .L13691 +.L14180: + ldr r8, [sp, #4] + add r3, r5, r7 + cmp r8, r3 + bls .L15705 + cmp r4, #0 + beq .L13691 + ldr r2, [sp, #0] + ldr r3, .L15735+4 + add r1, r2, r5, asl #2 + add r0, r0, r3 + mov r5, #0 + b .L14480 +.L15706: + add ip, ip, #64 + add r1, r1, #32 +.L14480: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L14481 + ands lr, r2, #255 + beq .L14483 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L14483: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14487 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L14487: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14491 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L14491: + movs r2, r2, lsr #24 + beq .L14481 + ldr lr, [r1, #12] + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L14481: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L14498 + ands lr, r2, #255 + beq .L14500 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L14500: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14504 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L14504: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14508 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L14508: + movs r2, r2, lsr #24 + beq .L14498 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L14498: + add r5, r5, #1 + cmp r4, r5 + add r0, r0, #64 + bne .L15706 + b .L13691 +.L15414: + ldr r8, [sp, #4] + add r3, r5, r7 + cmp r3, r8 + bcs .L15707 + cmp r4, #0 + beq .L13691 + ldr r3, [sp, #0] + mov ip, #0 + add r1, r3, r5, asl #2 + ldr r3, .L15735 + add r0, r0, r3 + b .L15614 +.L15708: + sub r2, r2, #64 + add r1, r1, #32 +.L15614: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L15615 + ands r3, lr, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #12] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #4] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #0] +.L15615: + ldr lr, [r2, #0] + cmp lr, #0 + beq .L15624 + ands r3, lr, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #28] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #24] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #20] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #16] +.L15624: + add ip, ip, #1 + cmp r4, ip + sub r0, r0, #64 + bne .L15708 + b .L13691 +.L15729: + mov r8, #0 +.L13754: + cmp sl, r3 + cmphi r7, r4 + bhi .L15663 + b .L13691 +.L13755: + cmp r3, sl + cmpcc r4, r7 + bcs .L13691 +.L15663: + ldr r2, [sp, #68] + and r0, r3, #7 + and ip, r3, #7 + mov r3, r3, asr #3 + mul r2, r3, r2 + ldr r3, [sp, #120] + ldr r1, [sp, #120] + add ip, r3, ip, asl #2 + mov r3, r4, asr #3 + add r0, r1, r0, asl #2 + mov lr, r4, asr #1 + mov r1, r4, asr #1 + add r2, r2, r3, asl #5 + tst r4, #1 + add r3, r0, r2 + and lr, lr, #3 + add r0, ip, r2 + and r1, r1, #3 + ldreqb r3, [r0, r1] @ zero_extendqisi2 + ldrneb r3, [r3, lr] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + ldr r4, [sp, #140] + cmp r0, #0 + orr r0, r0, r4 + beq .L13761 + ldr r2, [r9, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r9, #0] + streq r0, [r9, #0] +.L13761: + ldr ip, [sp, #60] + ldr lr, [sp, #64] + add r8, r8, #1 + add r6, r6, ip + add r5, r5, lr + cmp fp, r8 + add r9, r9, #4 + mov r4, r6, asr #8 + mov r3, r5, asr #8 + bgt .L13755 + b .L13691 +.L15732: + mov r6, #0 +.L14882: + cmp sl, lr + cmphi r7, r4 + bhi .L15673 + b .L13691 +.L14883: + cmp lr, sl + cmpcc r4, r7 + bcs .L13691 +.L15673: + and r3, lr, #7 + mov r2, r4, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + ldr r2, [sp, #116] + ldr r0, [sp, #84] + add r3, r3, r2 + mov r2, lr, asr #3 + mla r0, r2, r0, r3 + ldr r1, [sp, #72] + add r6, r6, #1 + add r5, r5, r1 + and r1, r4, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + ldr r0, [sp, #28] + cmp r3, #0 + orr r3, r0, r3 + strne r3, [r8, #0] + add ip, ip, fp + cmp r9, r6 + mov lr, ip, asr #8 + mov r4, r5, asr #8 + add r8, r8, #4 + bgt .L14883 + b .L13691 +.L15730: + mov r6, #0 +.L14918: + cmp sl, r2 + cmphi r7, lr + bhi .L15675 + b .L13691 +.L14919: + cmp r2, sl + cmpcc lr, r7 + bcs .L13691 +.L15675: + ldr r1, [sp, #112] + and r0, r2, #7 + add r0, r1, r0, asl #2 + mov r3, r2, asr #3 + and r1, r2, #7 + ldr r2, [sp, #104] + mov ip, lr, asr #1 + mul r2, r3, r2 + and r9, ip, #3 + ldr ip, [sp, #112] + mov r3, lr, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, lr, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst lr, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, r9] @ zero_extendqisi2 + ldr r2, [sp, #28] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr ip, [sp, #136] + ldr lr, [sp, #88] + orr r3, r0, r2 + ldr r1, [sp, #96] + cmp r0, #0 + add r6, r6, #1 + orr r3, ip, r3 + strne r3, [r8, #0] + add r5, r5, lr + add r4, r4, r1 + cmp fp, r6 + mov lr, r5, asr #8 + mov r2, r4, asr #8 + add r8, r8, #4 + bgt .L14919 + b .L13691 +.L15731: + mov r4, #0 +.L13715: + cmp sl, r0 + cmphi r7, r1 + bhi .L15661 + b .L13691 +.L13716: + cmp r0, sl + cmpcc r1, r7 + bcs .L13691 +.L15661: + and r3, r0, #7 + mov r2, r1, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + ldr r2, [sp, #124] + and r1, r1, #7 + add r3, r3, r2 + mov r2, r0, asr #3 + ldr r0, [sp, #56] + mla r0, r2, r0, r3 + ldrb r0, [r0, r1] @ zero_extendqisi2 + cmp r0, #0 + beq .L13719 + ldr r3, [r5, #0] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r1, r0, r3, asl #16 + orr r2, r2, #768 + tst r3, #256 + orr r2, r0, r2 + orr r1, r1, #768 + strne r2, [r5, #0] + streq r1, [r5, #0] +.L13719: + add r4, r4, #1 + add ip, ip, r9 + add lr, lr, r8 + cmp r6, r4 + mov r1, ip, asr #8 + mov r0, lr, asr #8 + add r5, r5, #4 + bgt .L13716 + b .L13691 +.L15707: + rsb r7, r5, r8 + cmp r7, #0 + ble .L13691 + ldr ip, [sp, #0] + movs r6, r7, lsr #3 + add r1, ip, r5, asl #2 + beq .L15573 + ldr r3, .L15735 + mov r4, r1 + add r0, r0, r3 + mov r5, r2 + mov ip, #0 +.L15575: + ldr lr, [r0, #68] + cmp lr, #0 + beq .L15576 + ands r3, lr, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #12] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #8] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #4] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #0] +.L15576: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L15585 + ands r3, lr, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #28] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #24] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r4, #20] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #16] +.L15585: + add ip, ip, #1 + cmp ip, r6 + sub r5, r5, #64 + add r4, r4, #32 + sub r0, r0, #64 + bne .L15575 + rsb r3, r6, r6, asl #26 + add r2, r2, r3, asl #6 + add r1, r1, r6, asl #5 +.L15573: + ands ip, r7, #7 + beq .L13691 + cmp ip, #3 + ldrls r2, [r2, #4] + bls .L15608 + ldr r0, [r2, #4] + cmp r0, #0 + beq .L15598 + ands r3, r0, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #12] + mov r3, r0, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #8] + mov r3, r0, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r0, lsr #24 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] +.L15598: + subs ip, ip, #4 + ldr r2, [r2, #0] + addne r1, r1, #16 + beq .L13691 +.L15608: + mov r0, #0 +.L15609: + ldr lr, [sp, #28] + movs r3, r2, lsr #24 + orr r3, lr, r3 + strne r3, [r1, r0, asl #2] + add r0, r0, #1 + cmp ip, r0 + mov r2, r2, asl #8 + bhi .L15609 + b .L13691 +.L15699: + rsb ip, r5, r1 + cmp ip, #0 + ble .L13691 + ldr r2, [sp, #0] + movs sl, ip, lsr #3 + add r8, r2, r5, asl #2 + beq .L13896 + mov r5, r8 + mov r7, r0 + mov r1, #0 +.L13898: + ldr r4, [r7, #0] + cmp r4, #0 + beq .L13899 + ands r2, r4, #15 + beq .L13901 + ldr lr, [r5, #0] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #0] + streq r3, [r5, #0] +.L13901: + mov r3, r4, lsr #4 + ands r2, r3, #15 + beq .L13905 + ldr lr, [r5, #4] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #4] + streq r3, [r5, #4] +.L13905: + mov r3, r4, lsr #8 + ands r2, r3, #15 + beq .L13909 + ldr lr, [r5, #8] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #8] + streq r3, [r5, #8] +.L13909: + mov r3, r4, lsr #12 + ands r2, r3, #15 + beq .L13913 + ldr lr, [r5, #12] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #12] + streq r3, [r5, #12] +.L13913: + mov r3, r4, lsr #16 + ands r2, r3, #15 + beq .L13917 + ldr lr, [r5, #16] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #16] + streq r3, [r5, #16] +.L13917: + mov r3, r4, lsr #20 + ands r2, r3, #15 + beq .L13921 + ldr lr, [r5, #20] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #20] + streq r3, [r5, #20] +.L13921: + mov r3, r4, lsr #24 + ands r2, r3, #15 + beq .L13925 + ldr lr, [r5, #24] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #24] + streq r3, [r5, #24] +.L13925: + movs r2, r4, lsr #28 + beq .L13899 + ldr lr, [r5, #28] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #28] + streq r3, [r5, #28] +.L13899: + add r1, r1, #1 + cmp sl, r1 + add r7, r7, #32 + add r5, r5, #32 + bne .L13898 + mov r3, sl, asl #5 + add r0, r0, r3 + add r8, r8, r3 +.L13896: + ands r4, ip, #7 + beq .L13691 + ldr ip, [r0, #0] + mov lr, #0 +.L13934: + ands r3, ip, #15 + beq .L13935 + ldr r1, [r8, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L13935: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, lsr #4 + add r8, r8, #4 + bne .L13934 + b .L13691 +.L15736: + .align 2 +.L15735: + .word vram+65472 + .word vram+65600 +.L15703: + rsb sl, r5, r4 + cmp sl, #0 + ble .L13691 + ldr lr, [sp, #0] + movs r8, sl, lsr #3 + add r7, lr, r5, asl #2 + beq .L14749 + ldr r3, .L15735 + mov r5, r7 + add r0, r0, r3 + mov r6, ip + mov r1, #0 +.L14751: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L14752 + ands lr, r2, #255 + beq .L14754 + ldr r3, [r5, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r5, #12] + streq r3, [r5, #12] +.L14754: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14758 + ldr r3, [r5, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r5, #8] + streq r3, [r5, #8] +.L14758: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14762 + ldr r3, [r5, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r5, #4] + streq r3, [r5, #4] +.L14762: + movs r2, r2, lsr #24 + beq .L14752 + ldr r3, [r5, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r5, #0] + streq r3, [r5, #0] +.L14752: + ldr lr, [r6, #0] + cmp lr, #0 + beq .L14769 + ands r2, lr, #255 + beq .L14771 + ldr r4, [r5, #28] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r5, #28] + streq r3, [r5, #28] +.L14771: + mov r3, lr, lsr #8 + ands r2, r3, #255 + beq .L14775 + ldr r3, [r5, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r5, #24] + streq r3, [r5, #24] +.L14775: + mov r3, lr, lsr #16 + ands r2, r3, #255 + beq .L14779 + ldr r3, [r5, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r5, #20] + streq r3, [r5, #20] +.L14779: + movs r2, lr, lsr #24 + beq .L14769 + ldr lr, [r5, #16] + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #16] + streq r3, [r5, #16] +.L14769: + add r1, r1, #1 + cmp r1, r8 + sub r6, r6, #64 + add r5, r5, #32 + sub r0, r0, #64 + bne .L14751 + rsb r3, r8, r8, asl #26 + add ip, ip, r3, asl #6 + add r7, r7, r8, asl #5 +.L14749: + ands r4, sl, #7 + beq .L13691 + cmp r4, #3 + ldrls ip, [ip, #4] + bls .L14808 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L14790 + ands r1, r2, #255 + beq .L14792 + ldr r3, [r7, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #12] + streq r3, [r7, #12] +.L14792: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14796 + ldr r3, [r7, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #8] + streq r3, [r7, #8] +.L14796: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14800 + ldr r3, [r7, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #4] + streq r3, [r7, #4] +.L14800: + movs r2, r2, lsr #24 + beq .L14790 + ldr r3, [r7, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r7, #0] + streq r3, [r7, #0] +.L14790: + subs r4, r4, #4 + ldr ip, [ip, #0] + addne r7, r7, #16 + beq .L13691 +.L14808: + mov lr, #0 +.L14809: + movs r0, ip, lsr #24 + beq .L14810 + ldr r2, [r7, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L14810: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, asl #8 + add r7, r7, #4 + bhi .L14809 + b .L13691 +.L15695: + rsb r7, r5, ip + cmp r7, #0 + ble .L13691 + ldr lr, [sp, #0] + movs r8, r7, lsr #3 + add r1, lr, r5, asl #2 + beq .L15018 + mov r4, r1 + mov r5, r0 + mov ip, #0 +.L15020: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L15021 + ands r3, lr, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + movs r3, lr, lsr #28 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] +.L15021: + add ip, ip, #1 + cmp r8, ip + add r5, r5, #32 + add r4, r4, #32 + bne .L15020 + mov r3, r8, asl #5 + add r0, r0, r3 + add r1, r1, r3 +.L15018: + ands lr, r7, #7 + beq .L13691 + ldr r0, [r0, #0] + mov ip, #0 +.L15040: + ldr r2, [sp, #28] + ands r3, r0, #15 + orr r3, r2, r3 + orr r3, r6, r3 + strne r3, [r1, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, lsr #4 + bne .L15040 + b .L13691 +.L15705: + rsb r8, r5, r8 + cmp r8, #0 + ble .L13691 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r6, lr, r5, asl #2 + beq .L14413 + ldr r3, .L15735+4 + mov r4, r6 + add r0, r0, r3 + mov r5, ip + mov r1, #0 +.L14415: + ldr r2, [r5, #0] + cmp r2, #0 + beq .L14416 + ands lr, r2, #255 + beq .L14418 + ldr r3, [r4, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L14418: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14422 + ldr r3, [r4, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L14422: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14426 + ldr r3, [r4, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L14426: + movs r2, r2, lsr #24 + beq .L14416 + ldr lr, [r4, #12] + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L14416: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L14433 + ands lr, r2, #255 + beq .L14435 + ldr r3, [r4, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L14435: + mov r3, r2, lsr #8 + ands lr, r3, #255 + beq .L14439 + ldr r3, [r4, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L14439: + mov r3, r2, lsr #16 + ands lr, r3, #255 + beq .L14443 + ldr r3, [r4, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, lr, r3, asl #16 + orrne r3, lr, r3 + orreq r3, r3, #768 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L14443: + movs r2, r2, lsr #24 + beq .L14433 + ldr r3, [r4, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L14433: + add r1, r1, #1 + cmp r1, r7 + add r5, r5, #64 + add r4, r4, #32 + add r0, r0, #64 + bne .L14415 + add ip, ip, r7, asl #6 + add r6, r6, r7, asl #5 +.L14413: + ands r4, r8, #7 + beq .L13691 + cmp r4, #3 + ldrls ip, [ip, #0] + bls .L14472 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L14454 + ands r1, r2, #255 + beq .L14456 + ldr r3, [r6, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L14456: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14460 + ldr r3, [r6, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L14460: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14464 + ldr r3, [r6, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L14464: + movs r2, r2, lsr #24 + beq .L14454 + ldr r1, [r6, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L14454: + subs r4, r4, #4 + ldr ip, [ip, #4] + addne r6, r6, #16 + beq .L13691 +.L14472: + mov lr, #0 +.L14473: + ands r0, ip, #255 + beq .L14474 + ldr r2, [r6, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r6, #0] + streq r0, [r6, #0] +.L14474: + add lr, lr, #1 + cmp r4, lr + mov ip, ip, lsr #8 + add r6, r6, #4 + bhi .L14473 + b .L13691 +.L15697: + rsb r8, r5, r8 + cmp r8, #0 + ble .L13691 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r1, lr, r5, asl #2 + beq .L15353 + ldr r3, .L15735+4 + mov r4, r1 + add r0, r0, r3 + mov r5, ip + mov r6, #0 +.L15355: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L15356 + ands r3, lr, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #0] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #4] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #8] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #12] +.L15356: + ldr lr, [r0, #-60] + cmp lr, #0 + beq .L15365 + ands r3, lr, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #16] + mov r3, lr, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #20] + mov r3, lr, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r4, #24] + movs r3, lr, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r4, #28] +.L15365: + add r6, r6, #1 + cmp r6, r7 + add r5, r5, #64 + add r4, r4, #32 + add r0, r0, #64 + bne .L15355 + add ip, ip, r7, asl #6 + add r1, r1, r7, asl #5 +.L15353: + ands lr, r8, #7 + beq .L13691 + cmp lr, #3 + ldrls ip, [ip, #0] + bls .L15388 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L15378 + ands r3, r2, #255 + ldrne r0, [sp, #28] + orrne r3, r0, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #12] +.L15378: + subs lr, lr, #4 + ldr ip, [ip, #4] + addne r1, r1, #16 + beq .L13691 +.L15388: + mov r0, #0 +.L15389: + ldr r8, [sp, #28] + ands r3, ip, #255 + orr r3, r8, r3 + strne r3, [r1, r0, asl #2] + add r0, r0, #1 + cmp lr, r0 + mov ip, ip, lsr #8 + bhi .L15389 + b .L13691 +.L15701: + rsb r8, r5, ip + cmp r8, #0 + ble .L13691 + ldr lr, [sp, #0] + movs r7, r8, lsr #3 + add r1, lr, r5, asl #2 + beq .L15148 + mov r4, r1 + mov r5, r0 + mov ip, #0 +.L15150: + ldr lr, [r5, #0] + cmp lr, #0 + beq .L15151 + ands r3, lr, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + movs r3, lr, lsr #28 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] +.L15151: + add ip, ip, #1 + cmp ip, r7 + sub r5, r5, #32 + add r4, r4, #32 + bne .L15150 + rsb r3, r7, r7, asl #27 + add r0, r0, r3, asl #5 + add r1, r1, r7, asl #5 +.L15148: + ands lr, r8, #7 + beq .L13691 + ldr r0, [r0, #0] + mov ip, #0 +.L15170: + ldr r2, [sp, #28] + movs r3, r0, lsr #28 + orr r3, r2, r3 + orr r3, r6, r3 + strne r3, [r1, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, asl #4 + bne .L15170 + b .L13691 +.L15693: + rsb sl, r5, r1 + cmp sl, #0 + ble .L13691 + ldr r2, [sp, #0] + movs ip, sl, lsr #3 + add r8, r2, r5, asl #2 + beq .L14100 + mov r5, r8 + mov r7, r0 + mov r1, #0 +.L14102: + ldr r4, [r7, #0] + cmp r4, #0 + beq .L14103 + ands r2, r4, #15 + beq .L14105 + ldr lr, [r5, #28] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #28] + streq r3, [r5, #28] +.L14105: + mov r3, r4, lsr #4 + ands r2, r3, #15 + beq .L14109 + ldr lr, [r5, #24] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #24] + streq r3, [r5, #24] +.L14109: + mov r3, r4, lsr #8 + ands r2, r3, #15 + beq .L14113 + ldr lr, [r5, #20] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #20] + streq r3, [r5, #20] +.L14113: + mov r3, r4, lsr #12 + ands r2, r3, #15 + beq .L14117 + ldr lr, [r5, #16] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #16] + streq r3, [r5, #16] +.L14117: + mov r3, r4, lsr #16 + ands r2, r3, #15 + beq .L14121 + ldr lr, [r5, #12] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #12] + streq r3, [r5, #12] +.L14121: + mov r3, r4, lsr #20 + ands r2, r3, #15 + beq .L14125 + ldr lr, [r5, #8] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #8] + streq r3, [r5, #8] +.L14125: + mov r3, r4, lsr #24 + ands r2, r3, #15 + beq .L14129 + ldr lr, [r5, #4] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #4] + streq r3, [r5, #4] +.L14129: + movs r2, r4, lsr #28 + beq .L14103 + ldr lr, [r5, #0] + orr r2, r6, r2 + tst lr, #256 + movne r3, lr, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, lr, asl #16 + strne r3, [r5, #0] + streq r3, [r5, #0] +.L14103: + add r1, r1, #1 + cmp ip, r1 + sub r7, r7, #32 + add r5, r5, #32 + bne .L14102 + rsb r3, ip, ip, asl #27 + add r0, r0, r3, asl #5 + add r8, r8, ip, asl #5 +.L14100: + ands r4, sl, #7 + beq .L13691 + ldr ip, [r0, #0] + mov lr, #0 +.L14138: + movs r3, ip, lsr #28 + beq .L14139 + ldr r1, [r8, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L14139: + add lr, lr, #1 + cmp lr, r4 + mov ip, ip, asl #4 + add r8, r8, #4 + bne .L14138 + b .L13691 +.L15727: + mov r4, r9 +.L14904: + cmp r7, r3 + bhi .L15674 + b .L13691 +.L14905: + cmp lr, r7 + bcs .L13691 +.L15674: + mov r3, lr, asr #1 + and r6, r3, #3 + mov r3, lr, asr #3 + mov r3, r3, asl #5 + mov r2, lr, asr #1 + tst lr, #1 + add ip, r3, r1 + and r5, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r5] @ zero_extendqisi2 + ldrneb r3, [ip, r6] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + ldr r5, [sp, #28] + ldr r3, [sp, #88] + ldr ip, [sp, #136] + add r0, r0, r3 + orr r3, r2, r5 + cmp r2, #0 + add r4, r4, #1 + orr r3, ip, r3 + strne r3, [r8, #0] + cmp fp, r4 + mov lr, r0, asr #8 + add r8, r8, #4 + bgt .L14905 + b .L13691 +.L14183: + mov r3, r0, lsr #3 + ands r2, r0, #7 + add r4, ip, r3, asl #6 + ldreq r0, [sp, #108] + bne .L15709 +.L14333: + movs lr, r8, lsr #3 + beq .L13691 + mov ip, #0 + b .L14374 +.L15710: + add r4, r4, #64 + add r0, r0, #32 +.L14374: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L14375 + ands r1, r2, #255 + beq .L14377 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L14377: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14381 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L14381: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14385 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L14385: + movs r2, r2, lsr #24 + beq .L14375 + ldr r1, [r0, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L14375: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L14392 + ands r1, r2, #255 + beq .L14394 + ldr r3, [r0, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L14394: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14398 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L14398: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14402 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L14402: + movs r2, r2, lsr #24 + beq .L14392 + ldr r3, [r0, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L14392: + add ip, ip, #1 + cmp ip, lr + bne .L15710 + b .L13691 +.L13775: + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add r5, r0, r1 + ldreq ip, [sp, #108] + bne .L15711 +.L13846: + movs r4, r8, lsr #3 + beq .L13691 + mov lr, #0 + b .L13858 +.L15712: + add r5, r5, #32 + add ip, ip, #32 +.L13858: + ldr r0, [r5, #0] + cmp r0, #0 + beq .L13859 + ands r2, r0, #15 + beq .L13861 + ldr r1, [ip, #0] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L13861: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L13865 + ldr r1, [ip, #4] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L13865: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L13869 + ldr r1, [ip, #8] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L13869: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L13873 + ldr r1, [ip, #12] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L13873: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L13877 + ldr r1, [ip, #16] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L13877: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L13881 + ldr r1, [ip, #20] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L13881: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L13885 + ldr r1, [ip, #24] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L13885: + movs r2, r0, lsr #28 + beq .L13859 + ldr r1, [ip, #28] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L13859: + add lr, lr, #1 + cmp r4, lr + bne .L15712 + b .L13691 +.L15417: + mov r3, r0, lsr #3 + ands r1, r0, #7 + sub r2, r2, r3, asl #6 + ldreq r0, [sp, #108] + bne .L15713 +.L15521: + movs lr, lr, lsr #3 + beq .L13691 + mov ip, #0 + b .L15550 +.L15714: + sub r2, r2, #64 + add r0, r0, #32 +.L15550: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L15551 + ands r3, r1, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r0, #0] +.L15551: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L15560 + ands r3, r1, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r0, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r0, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r0, #20] + movs r3, r1, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r0, #16] +.L15560: + add ip, ip, #1 + cmp ip, lr + bne .L15714 + b .L13691 +.L14519: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub r4, ip, r3, asl #6 + ldreq ip, [sp, #108] + bne .L15715 +.L14669: + movs r5, r8, lsr #3 + beq .L13691 + mov lr, #0 + b .L14710 +.L15716: + sub r4, r4, #64 + add ip, ip, #32 +.L14710: + ldr r2, [r4, #4] + cmp r2, #0 + beq .L14711 + ands r1, r2, #255 + beq .L14713 + ldr r3, [ip, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L14713: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L14717 + ldr r3, [ip, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L14717: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L14721 + ldr r3, [ip, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L14721: + movs r2, r2, lsr #24 + beq .L14711 + ldr r3, [ip, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L14711: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L14728 + ands r2, r1, #255 + beq .L14730 + ldr r0, [ip, #28] + tst r0, #256 + movne r3, r0, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r0, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L14730: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L14734 + ldr r3, [ip, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L14734: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L14738 + ldr r3, [ip, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L14738: + movs r2, r1, lsr #24 + beq .L14728 + ldr r1, [ip, #16] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L14728: + add lr, lr, #1 + cmp r5, lr + bne .L15716 + b .L13691 +.L13979: + mov r3, lr, lsr #3 + ands r2, lr, #7 + sub ip, r0, r3, asl #5 + ldreq lr, [sp, #108] + bne .L15717 +.L14050: + movs r5, r8, lsr #3 + beq .L13691 + mov r4, #0 + b .L14062 +.L15718: + sub ip, ip, #32 + add lr, lr, #32 +.L14062: + ldr r0, [ip, #0] + cmp r0, #0 + beq .L14063 + ands r2, r0, #15 + beq .L14065 + ldr r1, [lr, #28] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #28] + streq r3, [lr, #28] +.L14065: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L14069 + ldr r1, [lr, #24] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #24] + streq r3, [lr, #24] +.L14069: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L14073 + ldr r1, [lr, #20] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #20] + streq r3, [lr, #20] +.L14073: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L14077 + ldr r1, [lr, #16] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #16] + streq r3, [lr, #16] +.L14077: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L14081 + ldr r1, [lr, #12] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L14081: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L14085 + ldr r1, [lr, #8] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L14085: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L14089 + ldr r1, [lr, #4] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L14089: + movs r2, r0, lsr #28 + beq .L14063 + ldr r1, [lr, #0] + orr r2, r6, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L14063: + add r4, r4, #1 + cmp r4, r5 + bne .L15718 + b .L13691 +.L14937: + mov r3, lr, lsr #3 + mov r1, r3, asl #5 + ands r3, lr, #7 + add lr, r0, r1 + ldreq r1, [sp, #108] + bne .L15719 +.L14986: + movs ip, r4, lsr #3 + beq .L13691 + mov r0, #0 + b .L14996 +.L15720: + add lr, lr, #32 + add r1, r1, #32 +.L14996: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L14997 + ands r3, r2, #15 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + orrne r3, r6, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + orrne r3, r6, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #28 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r1, #28] +.L14997: + add r0, r0, #1 + cmp r0, ip + bne .L15720 + b .L13691 +.L15197: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r0, ip, r3, asl #6 + ldreq r1, [sp, #108] + bne .L15721 +.L15301: + movs lr, lr, lsr #3 + beq .L13691 + mov ip, #0 + b .L15330 +.L15722: + add r0, r0, #64 + add r1, r1, #32 +.L15330: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L15331 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #12] +.L15331: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L15340 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #28] +.L15340: + add ip, ip, #1 + cmp ip, lr + bne .L15722 + b .L13691 +.L15067: + ands r2, lr, #7 + mov r3, lr, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r4, [sp, #108] + bne .L15723 +.L15116: + movs r1, r1, lsr #3 + beq .L13691 + mov r2, #0 + b .L15126 +.L15724: + sub r0, r0, #32 + add r4, r4, #32 +.L15126: + ldr lr, [r0, #0] + cmp lr, #0 + beq .L15127 + ands r3, lr, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #28] + mov r3, lr, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r4, #24] + mov r3, lr, lsr #8 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r4, #20] + mov r3, lr, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #16] + mov r3, lr, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + orrne r3, r6, r3 + strne r3, [r4, #12] + mov r3, lr, lsr #20 + ands r3, r3, #15 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + orrne r3, r6, r3 + strne r3, [r4, #8] + mov r3, lr, lsr #24 + ands r3, r3, #15 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + orrne r3, r6, r3 + strne r3, [r4, #4] + movs r3, lr, lsr #28 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + orrne r3, r6, r3 + strne r3, [r4, #0] +.L15127: + add r2, r2, #1 + cmp r1, r2 + bne .L15724 + b .L13691 +.L15723: + rsbs ip, r2, #8 + ldr lr, [r0, #0] + ldreq r4, [sp, #108] + beq .L15119 + mov r3, r2, asl #2 + mov lr, lr, asl r3 + mov r4, #0 +.L15120: + ldr r5, [sp, #28] + movs r3, lr, lsr #28 + ldrne r7, [sp, #108] + orr r3, r5, r3 + orr r3, r6, r3 + strne r3, [r7, r4, asl #2] + add r4, r4, #1 + cmp ip, r4 + mov lr, lr, asl #4 + bne .L15120 + ldr r8, [sp, #108] + add r4, r8, ip, asl #2 +.L15119: + sub r0, r0, #32 + b .L15116 +.L15721: + cmp r2, #3 + rsb ip, r2, #8 + bls .L15302 + cmp ip, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #108] + beq .L15306 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov r1, #0 +.L15307: + ands r3, r2, #255 + ldr r7, [sp, #28] + ldrne r8, [sp, #108] + orr r3, r7, r3 + strne r3, [r8, r1, asl #2] + add r1, r1, #1 + cmp r1, ip + mov r2, r2, lsr #8 + bne .L15307 + ldr r2, [sp, #108] + add r1, r2, ip, asl #2 +.L15306: + add r0, r0, #64 + b .L15301 +.L15719: + rsbs r5, r3, #8 + ldr r0, [r0, r1] + ldreq r1, [sp, #108] + beq .L14989 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L14990: + ldr r7, [sp, #28] + ands r3, r0, #15 + ldrne r8, [sp, #108] + orr r3, r7, r3 + orr r3, r6, r3 + strne r3, [r8, r2, asl #2] + add r2, r2, #1 + cmp r2, r5 + mov r0, r0, lsr #4 + bne .L14990 + ldr ip, [sp, #108] + add r1, ip, r5, asl #2 +.L14989: + add lr, lr, #32 + b .L14986 +.L15715: + cmp r2, #3 + rsb r6, r2, #8 + bls .L14670 + cmp r6, #0 + ldr r1, [r4, #0] + ldreq ip, [sp, #108] + beq .L14674 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #108] + mov r5, #0 +.L14675: + movs r0, ip, lsr #24 + beq .L14676 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14676: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14675 + ldr r2, [sp, #108] + add ip, r2, r6, asl #2 +.L14674: + sub r4, r4, #64 + b .L14669 +.L15713: + cmp r1, #3 + rsb ip, r1, #8 + bls .L15522 + cmp ip, #0 + ldr r0, [r2, #0] + ldreq r0, [sp, #108] + beq .L15526 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r1, r0, asl r3 + mov r0, #0 +.L15527: + movs r3, r1, lsr #24 + ldr r7, [sp, #28] + ldrne r8, [sp, #108] + orr r3, r7, r3 + strne r3, [r8, r0, asl #2] + add r0, r0, #1 + cmp ip, r0 + mov r1, r1, asl #8 + bne .L15527 + ldr r1, [sp, #108] + add r0, r1, ip, asl #2 +.L15526: + sub r2, r2, #64 + b .L15521 +.L15717: + rsbs r7, r2, #8 + ldr r1, [ip, #0] + ldreq lr, [sp, #108] + beq .L14053 + mov r3, r2, asl #2 + mov lr, r1, asl r3 + ldr r4, [sp, #108] + mov r5, #0 +.L14054: + movs r3, lr, lsr #28 + beq .L14055 + ldr r1, [r4, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L14055: + add r5, r5, #1 + cmp r5, r7 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L14054 + ldr r0, [sp, #108] + add lr, r0, r7, asl #2 +.L14053: + sub ip, ip, #32 + b .L14050 +.L15711: + rsbs r7, r3, #8 + ldr r0, [r0, r1] + ldreq ip, [sp, #108] + beq .L13849 + mov r3, r3, asl #2 + mov ip, r0, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L13850: + ands r3, ip, #15 + beq .L13851 + ldr r1, [lr, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L13851: + add r4, r4, #1 + cmp r7, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L13850 + ldr lr, [sp, #108] + add ip, lr, r7, asl #2 +.L13849: + add r5, r5, #32 + b .L13846 +.L15709: + cmp r2, #3 + rsb r6, r2, #8 + bls .L14334 + cmp r6, #0 + ldr r1, [r4, #4] + ldreq r0, [sp, #108] + beq .L14338 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, lsr r3 + ldr lr, [sp, #108] + mov r5, #0 +.L14339: + ands r0, ip, #255 + beq .L14340 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14340: + add r5, r5, #1 + cmp r6, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14339 + ldr r7, [sp, #108] + add r0, r7, r6, asl #2 +.L14338: + add r4, r4, #64 + b .L14333 +.L14185: + ldr r2, [sp, #144] + rsb r5, lr, #8 + cmp r2, r5 + bge .L14188 + cmp r2, #0 + ble .L13691 + cmp lr, #3 + bls .L14191 + mov r3, lr, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14194: + ands r0, ip, #255 + beq .L14195 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14195: + ldr r3, [sp, #144] + add r4, r4, #1 + cmp r3, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14194 + b .L13691 +.L15069: + ldr r7, [sp, #144] + rsb r5, r4, #8 + cmp r7, r5 + bge .L15072 + cmp r7, #0 + ble .L13691 + ldr r2, [r0, #0] + mov r3, r4, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L15076: + ldr r8, [sp, #28] + movs r3, r0, lsr #28 + ldrne ip, [sp, #108] + orr r3, r8, r3 + orr r3, r6, r3 + ldr lr, [sp, #144] + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp lr, r2 + mov r0, r0, asl #4 + bne .L15076 + b .L13691 +.L15419: + ldr r7, [sp, #144] + rsb r0, ip, #8 + cmp r7, r0 + bge .L15422 + cmp r7, #0 + ble .L13691 + cmp ip, #3 + bls .L15425 + ldr r2, [r6, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L15428: + movs r3, r2, lsr #24 + ldr r8, [sp, #28] + ldrne ip, [sp, #108] + orr r3, r8, r3 + ldr lr, [sp, #144] + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, asl #8 + bne .L15428 + b .L13691 +.L13981: + ldr r2, [sp, #144] + rsb r7, r4, #8 + cmp r2, r7 + bge .L13984 + cmp r2, #0 + ble .L13691 + ldr r2, [ip, #0] + mov r3, r4, asl #2 + mov ip, r2, asl r3 + ldr lr, [sp, #108] + mov r4, #0 +.L13988: + movs r3, ip, lsr #28 + beq .L13989 + ldr r1, [lr, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L13989: + ldr r3, [sp, #144] + add r4, r4, #1 + cmp r3, r4 + mov ip, ip, asl #4 + add lr, lr, #4 + bne .L13988 + b .L13691 +.L14521: + ldr r0, [sp, #144] + rsb r5, lr, #8 + cmp r0, r5 + bge .L14524 + cmp r0, #0 + ble .L13691 + cmp lr, #3 + bls .L14527 + mov r3, lr, asl #3 + ldr r2, [r8, #0] + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14530: + movs r0, ip, lsr #24 + beq .L14531 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14531: + ldr r1, [sp, #144] + add r4, r4, #1 + cmp r1, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14530 + b .L13691 +.L14939: + ldr r2, [sp, #144] + rsb lr, r3, #8 + cmp r2, lr + bge .L14942 + cmp r2, #0 + ble .L13691 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L14946: + ldr r4, [sp, #28] + ands r3, r0, #15 + ldrne r5, [sp, #108] + orr r3, r4, r3 + orr r3, r6, r3 + ldr r7, [sp, #144] + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r7, r2 + mov r0, r0, lsr #4 + bne .L14946 + b .L13691 +.L13777: + ldr r2, [sp, #144] + rsb r5, r3, #8 + cmp r2, r5 + bge .L13780 + cmp r2, #0 + ble .L13691 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L13784: + ands r3, ip, #15 + beq .L13785 + ldr r1, [lr, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L13785: + ldr r3, [sp, #144] + add r4, r4, #1 + cmp r3, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L13784 + b .L13691 +.L15199: + ldr r5, [sp, #144] + rsb r0, lr, #8 + cmp r5, r0 + bge .L15202 + cmp r5, #0 + ble .L13691 + cmp lr, #3 + bls .L15205 + ldr r2, [r6, #4] + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L15208: + ands r3, r1, #255 + ldr r7, [sp, #28] + ldrne r8, [sp, #108] + orr r3, r7, r3 + ldr ip, [sp, #144] + strne r3, [r8, r2, asl #2] + add r2, r2, #1 + cmp ip, r2 + mov r1, r1, lsr #8 + bne .L15208 + b .L13691 +.L13984: + cmp r7, #0 + ldr r2, [ip, #0] + ldreq r5, [sp, #108] + beq .L13996 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + ldr r4, [sp, #108] + mov r5, #0 +.L13997: + movs r3, lr, lsr #28 + beq .L13998 + ldr r1, [r4, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L13998: + add r5, r5, #1 + cmp r7, r5 + mov lr, lr, asl #4 + add r4, r4, #4 + bne .L13997 + ldr r4, [sp, #108] + add r5, r4, r7, asl #2 +.L13996: + ldr r8, [sp, #144] + sub ip, ip, #32 + rsb sl, r7, r8 + b .L13983 +.L14188: + cmp lr, #3 + bls .L14226 + cmp r5, #0 + ldr r2, [r7, #4] + ldreq r4, [sp, #108] + beq .L14230 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14231: + ands r0, ip, #255 + beq .L14232 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14232: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14231 + ldr r2, [sp, #108] + add r4, r2, r5, asl #2 +.L14230: + ldr r3, [sp, #144] + add r7, r7, #64 + rsb r6, r5, r3 + b .L14187 +.L14524: + cmp lr, #3 + bls .L14562 + cmp r5, #0 + ldr r2, [r8, #0] + ldreq r4, [sp, #108] + beq .L14566 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14567: + movs r0, ip, lsr #24 + beq .L14568 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14568: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14567 + ldr lr, [sp, #108] + add r4, lr, r5, asl #2 +.L14566: + ldr r0, [sp, #144] + sub r8, r8, #64 + rsb r7, r5, r0 + b .L14523 +.L15302: + subs r4, ip, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #108] + beq .L15314 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov r1, #0 +.L15315: + ands r3, r2, #255 + ldr r5, [sp, #28] + ldrne r7, [sp, #108] + orr r3, r5, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r4, r1 + mov r2, r2, lsr #8 + bne .L15315 + ldr r8, [sp, #108] + add r3, r8, ip, asl #2 + sub r1, r3, #16 +.L15314: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L15320 + ands r3, r2, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #12] +.L15320: + add r1, r1, #16 + add r0, r0, #64 + b .L15301 +.L15522: + subs r4, ip, #4 + ldr r0, [r2, #4] + ldreq r0, [sp, #108] + beq .L15534 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r1, r0, asl r3 + mov r0, #0 +.L15535: + movs r3, r1, lsr #24 + ldr r5, [sp, #28] + ldrne r7, [sp, #108] + orr r3, r5, r3 + strne r3, [r7, r0, asl #2] + add r0, r0, #1 + cmp r0, r4 + mov r1, r1, asl #8 + bne .L15535 + ldr r8, [sp, #108] + add r3, r8, ip, asl #2 + sub r0, r3, #16 +.L15534: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L15540 + ands r3, r1, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #28] + orrne r3, r4, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #28] + orrne r3, r5, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r0, #0] +.L15540: + add r0, r0, #16 + sub r2, r2, #64 + b .L15521 +.L15202: + cmp lr, #3 + bls .L15232 + cmp r0, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #108] + beq .L15236 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L15237: + ands r3, r1, #255 + ldr r7, [sp, #28] + ldrne r8, [sp, #108] + orr r3, r7, r3 + strne r3, [r8, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bne .L15237 + ldr ip, [sp, #108] + add r4, ip, r0, asl #2 +.L15236: + ldr r1, [sp, #144] + add r6, r6, #64 + rsb r5, r0, r1 + b .L15201 +.L13780: + cmp r5, #0 + ldr r2, [r8, #0] + ldreq r4, [sp, #108] + beq .L13792 + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L13793: + ands r3, ip, #15 + beq .L13794 + ldr r1, [lr, #0] + orr r2, r6, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [lr, #0] + streq r2, [lr, #0] +.L13794: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #4 + add lr, lr, #4 + bne .L13793 + ldr r7, [sp, #108] + add r4, r7, r5, asl #2 +.L13792: + ldr ip, [sp, #144] + add r8, r8, #32 + rsb sl, r5, ip + b .L13779 +.L15422: + cmp ip, #3 + bls .L15452 + cmp r0, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #108] + beq .L15456 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L15457: + movs r3, r2, lsr #24 + ldr r7, [sp, #28] + ldrne r8, [sp, #108] + orr r3, r7, r3 + strne r3, [r8, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bne .L15457 + ldr ip, [sp, #108] + add r4, ip, r0, asl #2 +.L15456: + ldr r3, [sp, #144] + sub r6, r6, #64 + rsb r5, r0, r3 + b .L15421 +.L15072: + cmp r5, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #108] + beq .L15082 + mov r3, r4, asl #2 + mov lr, r2, asl r3 + mov r4, #0 +.L15083: + ldr r1, [sp, #28] + movs r3, lr, lsr #28 + ldrne r2, [sp, #108] + orr r3, r1, r3 + orr r3, r6, r3 + strne r3, [r2, r4, asl #2] + add r4, r4, #1 + cmp r5, r4 + mov lr, lr, asl #4 + bne .L15083 + ldr r3, [sp, #108] + add r1, r3, r5, asl #2 +.L15082: + ldr r4, [sp, #144] + sub r0, r0, #32 + rsb r2, r5, r4 + b .L15071 +.L14334: + subs r7, r6, #4 + ldr r1, [r4, #0] + ldreq r2, [sp, #108] + beq .L14348 + mov r3, r2, asl #3 + mov ip, r1, lsr r3 + ldr lr, [sp, #108] + mov r5, #0 +.L14349: + ands r0, ip, #255 + beq .L14350 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14350: + add r5, r5, #1 + cmp r7, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14349 + ldr r5, [sp, #108] + add r3, r5, r6, asl #2 + sub r2, r3, #16 +.L14348: + ldr r1, [r4, #4] + cmp r1, #0 + beq .L14356 + ands r0, r1, #255 + beq .L14358 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L14358: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L14362 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L14362: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L14366 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L14366: + movs r1, r1, lsr #24 + beq .L14356 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #12] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #12] +.L14356: + add r0, r2, #16 + add r4, r4, #64 + b .L14333 +.L14670: + subs r7, r6, #4 + ldr r1, [r4, #4] + ldreq r2, [sp, #108] + beq .L14684 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr lr, [sp, #108] + mov r5, #0 +.L14685: + movs r0, ip, lsr #24 + beq .L14686 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14686: + add r5, r5, #1 + cmp r5, r7 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14685 + ldr r1, [sp, #108] + add r3, r1, r6, asl #2 + sub r2, r3, #16 +.L14684: + ldr r1, [r4, #0] + cmp r1, #0 + beq .L14692 + ands r0, r1, #255 + beq .L14694 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L14694: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L14698 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L14698: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L14702 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L14702: + movs r1, r1, lsr #24 + beq .L14692 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #0] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #0] +.L14692: + add ip, r2, #16 + sub r4, r4, #64 + b .L14669 +.L14942: + cmp lr, #0 + ldr r2, [r4, #0] + ldreq r7, [sp, #108] + beq .L14952 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov r1, #0 +.L14953: + ldr r8, [sp, #28] + ands r3, r2, #15 + ldrne ip, [sp, #108] + orr r3, r8, r3 + orr r3, r6, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, lsr #4 + bne .L14953 + ldr r0, [sp, #108] + add r7, r0, lr, asl #2 +.L14952: + ldr r1, [sp, #144] + add r4, r4, #32 + rsb r5, lr, r1 + b .L14941 +.L15726: + mov ip, fp + b .L15672 +.L15725: + ldr ip, [sp, #12] + b .L15660 +.L15728: + ldr lr, [sp, #16] + b .L15662 +.L15452: + subs lr, r0, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #108] + beq .L15464 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L15465: + movs r3, r2, lsr #24 + ldr r4, [sp, #28] + ldrne r5, [sp, #108] + orr r3, r4, r3 + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp r1, lr + mov r2, r2, asl #8 + bne .L15465 + ldr r7, [sp, #108] + add r3, r7, r0, asl #2 + sub r1, r3, #16 +.L15464: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L15470 + ands r3, r2, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #28] + orrne r3, r2, r3 + strne r3, [r1, #0] +.L15470: + add r4, r1, #16 + b .L15456 +.L15232: + subs ip, r0, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #108] + beq .L15244 + mov r3, lr, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L15245: + ands r3, r1, #255 + ldr lr, [sp, #28] + ldrne r4, [sp, #108] + orr r3, lr, r3 + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp ip, r2 + mov r1, r1, lsr #8 + bne .L15245 + ldr r5, [sp, #108] + add r3, r5, r0, asl #2 + sub r1, r3, #16 +.L15244: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L15250 + ands r3, r2, #255 + ldrne r7, [sp, #28] + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #28] + orrne r3, r8, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne ip, [sp, #28] + orrne r3, ip, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne lr, [sp, #28] + orrne r3, lr, r3 + strne r3, [r1, #12] +.L15250: + add r4, r1, #16 + b .L15236 +.L14562: + subs r6, r5, #4 + ldr r2, [r8, #4] + ldreq r2, [sp, #108] + beq .L14576 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14577: + movs r0, ip, lsr #24 + beq .L14578 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14578: + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14577 + ldr ip, [sp, #108] + add r3, ip, r5, asl #2 + sub r2, r3, #16 +.L14576: + ldr r1, [r8, #0] + cmp r1, #0 + beq .L14584 + ands r0, r1, #255 + beq .L14586 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L14586: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L14590 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L14590: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L14594 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L14594: + movs r1, r1, lsr #24 + beq .L14584 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #0] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #0] +.L14584: + add r4, r2, #16 + b .L14566 +.L14226: + subs r6, r5, #4 + ldr r2, [r7, #0] + ldreq r2, [sp, #108] + beq .L14240 + mov r3, lr, asl #3 + mov ip, r2, lsr r3 + ldr lr, [sp, #108] + mov r4, #0 +.L14241: + ands r0, ip, #255 + beq .L14242 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14242: + add r4, r4, #1 + cmp r4, r6 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14241 + ldr r1, [sp, #108] + add r3, r1, r5, asl #2 + sub r2, r3, #16 +.L14240: + ldr r1, [r7, #4] + cmp r1, #0 + beq .L14248 + ands r0, r1, #255 + beq .L14250 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L14250: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L14254 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L14254: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L14258 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L14258: + movs r1, r1, lsr #24 + beq .L14248 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #12] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #12] +.L14248: + add r4, r2, #16 + b .L14230 +.L15205: + ldr r0, [sp, #144] + ldr r3, [r6, #0] + add r2, r0, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov r2, r3, lsr r1 + bhi .L15212 + cmp r0, #0 + movne r1, #0 + beq .L13691 +.L15228: + ands r3, r2, #255 + ldr r0, [sp, #28] + ldrne r4, [sp, #108] + orr r3, r0, r3 + ldr r5, [sp, #144] + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r5, r1 + mov r2, r2, lsr #8 + bne .L15228 + b .L13691 +.L14527: + ldr r4, [sp, #144] + mov r3, lr, asl #3 + ldr r1, [r8, #4] + add r2, r4, lr + sub r3, r3, #32 + cmp r2, #4 + mov ip, r1, asl r3 + bhi .L14536 + cmp r4, #0 + ldrne lr, [sp, #108] + movne r4, #0 + beq .L13691 +.L14556: + movs r0, ip, lsr #24 + beq .L14557 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14557: + ldr r8, [sp, #144] + add r4, r4, #1 + cmp r8, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14556 + b .L13691 +.L15425: + ldr r0, [sp, #144] + mov r3, ip, asl #3 + ldr r1, [r6, #4] + add r2, r0, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L15432 + cmp r0, #0 + movne r2, #0 + beq .L13691 +.L15448: + movs r3, r1, lsr #24 + ldr r0, [sp, #28] + ldrne r4, [sp, #108] + orr r3, r0, r3 + ldr r5, [sp, #144] + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r5, r2 + mov r1, r1, asl #8 + bne .L15448 + b .L13691 +.L14191: + ldr r4, [sp, #144] + ldr r3, [r7, #0] + add r2, r4, lr + mov r1, lr, asl #3 + cmp r2, #4 + mov ip, r3, lsr r1 + bhi .L14200 + cmp r4, #0 + ldrne lr, [sp, #108] + movne r4, #0 + beq .L13691 +.L14220: + ands r0, ip, #255 + beq .L14221 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14221: + ldr r0, [sp, #144] + add r4, r4, #1 + cmp r0, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14220 + b .L13691 +.L14200: + rsbs r4, lr, #4 + ldreq lr, [sp, #108] + beq .L14205 + ldr lr, [sp, #108] + mov r5, #0 +.L14206: + ands r0, ip, #255 + beq .L14207 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14207: + add r5, r5, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14206 + ldr r5, [sp, #108] + add lr, r5, r4, asl #2 +.L14205: + ldr r8, [sp, #144] + ldr ip, [r7, #4] + subs r5, r8, r4 + beq .L13691 + mov r4, #0 +.L14214: + ands r0, ip, #255 + beq .L14215 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14215: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L14214 + b .L13691 +.L15432: + rsbs r0, ip, #4 + ldreq ip, [sp, #108] + beq .L15437 + mov r2, #0 +.L15438: + movs r3, r1, lsr #24 + ldr r4, [sp, #28] + ldrne r5, [sp, #108] + orr r3, r4, r3 + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r2, r0 + mov r1, r1, asl #8 + bne .L15438 + ldr r7, [sp, #108] + add ip, r7, r0, asl #2 +.L15437: + ldr r8, [sp, #144] + ldr r2, [r6, #0] + subs r0, r8, r0 + beq .L13691 + mov r1, #0 +.L15444: + ldr lr, [sp, #28] + movs r3, r2, lsr #24 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, asl #8 + bne .L15444 + b .L13691 +.L14536: + rsbs r4, lr, #4 + ldreq lr, [sp, #108] + beq .L14541 + ldr lr, [sp, #108] + mov r5, #0 +.L14542: + movs r0, ip, lsr #24 + beq .L14543 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14543: + add r5, r5, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14542 + ldr r5, [sp, #108] + add lr, r5, r4, asl #2 +.L14541: + ldr r7, [sp, #144] + ldr ip, [r8, #0] + subs r5, r7, r4 + beq .L13691 + mov r4, #0 +.L14550: + movs r0, ip, lsr #24 + beq .L14551 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L14551: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L14550 + b .L13691 +.L15212: + rsbs r0, lr, #4 + ldreq ip, [sp, #108] + beq .L15217 + mov r1, #0 +.L15218: + ands r3, r2, #255 + ldr r4, [sp, #28] + ldrne r5, [sp, #108] + orr r3, r4, r3 + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L15218 + ldr r7, [sp, #108] + add ip, r7, r0, asl #2 +.L15217: + ldr r8, [sp, #144] + ldr r2, [r6, #4] + subs r0, r8, r0 + beq .L13691 + mov r1, #0 +.L15224: + ldr lr, [sp, #28] + ands r3, r2, #255 + orr r3, lr, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L15224 + b .L13691 + .size render_scanline_obj_partial_alpha_1D, .-render_scanline_obj_partial_alpha_1D + .align 2 + .global render_scanline_obj_partial_alpha_2D + .type render_scanline_obj_partial_alpha_2D, %function +render_scanline_obj_partial_alpha_2D: + @ args = 0, pretend = 0, frame = 140 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L17801 + sub sp, sp, #140 + ldrh r4, [ip, #6] + add r0, r0, r0, asl #2 + str r4, [sp, #60] + ldr r5, [sp, #60] + ldrh r4, [ip, #80] + ldr ip, .L17801+4 + add r0, r5, r0, asl #5 + ldr ip, [ip, r0, asl #2] + mov lr, r4, lsr #11 + and lr, lr, #2 + mov r4, r4, asl #27 + str ip, [sp, #64] + orr lr, lr, r4, lsr #31 + cmp ip, #0 + ldr ip, .L17801+8 + mov lr, lr, asl #9 + add r0, ip, r0, asl #7 + orr lr, lr, #256 + str r0, [sp, #68] + str r1, [sp, #12] + str r2, [sp, #8] + str r3, [sp, #4] + str lr, [sp, #52] + beq .L17699 + mov ip, #0 + add r7, r3, r1, asl #2 + rsb r8, r1, r2 + str r7, [sp, #96] + str r8, [sp, #128] + str ip, [sp, #56] + mov lr, ip +.L15740: + ldr r0, [sp, #68] + ldr r1, .L17801+12 + ldrb r3, [lr, r0] @ zero_extendqisi2 + mov r3, r3, asl #3 + ldrh r4, [r3, r1] + add r3, r3, r1 + ldrh r1, [r3, #2] + mov ip, r4, lsr #12 + and r2, ip, #12 + orr r0, r2, r1, lsr #14 + and r5, r4, #255 + mov r2, r1, asl #23 + cmp r5, #160 + ldrh lr, [r3, #4] + mov r6, r2, asr #23 + ldr r3, .L17801+16 + ldr r2, .L17801+20 + subgt r5, r5, #256 + tst r4, #3072 + ldr sl, [r2, r0, asl #2] + ldr r8, [r3, r0, asl #2] + beq .L15743 + tst r4, #256 + beq .L15745 + tst r4, #8192 + beq .L15747 + tst r4, #512 + mov r3, r1, lsr #4 + ldr r4, .L17801+12 + and r3, r3, #992 + add r3, r3, r4 + add r2, sl, sl, lsr #31 + ldrh r7, [r3, #30] + mov r4, r2, asr #1 + add r1, r8, r8, lsr #31 + ldr r2, [sp, #12] + mov r9, r1, asr #1 + ldrh fp, [r3, #6] + ldrh r1, [r3, #14] + ldrh r3, [r3, #22] + str r7, [sp, #20] + moveq ip, r4 + moveq r7, sl + moveq r0, r9 + movne r7, sl, asl #1 + movne ip, r4, asl #1 + movne r0, r9, asl #1 + cmp r6, r2 + str r3, [sp, #16] + bge .L15752 + rsb r2, r6, r2 + rsb r7, r2, r7 + cmp r7, #0 + ble .L15754 + ldr r6, [sp, #12] + rsb ip, r2, ip +.L15752: + ldr r2, [sp, #8] + add r3, r6, r7 + cmp r3, r2 + blt .L15756 + rsb r7, r6, r2 + cmp r7, #0 + ble .L15754 +.L15756: + add r0, r5, r0 + ldr r5, [sp, #20] + mov r2, r1, asl #16 + mov r1, r5, asl #16 + ldr r5, [sp, #16] + mov r3, fp, asl #16 + cmp r5, #0 + mov fp, r3, asr #16 + mov r5, r2, asr #16 + ldr r3, [sp, #60] + ldr r2, [sp, #4] + mov r4, r4, asl #8 + str r4, [sp, #100] + mov r1, r1, asr #16 + mov r4, r9, asl #8 + add r6, r2, r6, asl #2 + rsb r0, r0, r3 + bne .L15758 + mla r3, r0, r1, r4 + mov r2, r3, asr #8 + cmp r2, r8 + bcs .L15754 + mov r3, lr, asl #22 + mov r1, r2, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r1, asl #5 + and r2, r2, #7 + ldr r4, .L17801+24 + add r2, r2, r3, asl #2 + cmp r7, #0 + add lr, r4, r2, asl #3 + ble .L15754 + mul r3, r0, r5 + mul r2, fp, ip + ldr r5, [sp, #100] + rsb r3, r2, r3 + add r0, r5, r3 + mov r2, r0, asr #8 + cmp r2, sl + ldrcs ip, [sp, #16] + bcs .L15764 + b .L17793 +.L15765: + cmp r2, sl + bcc .L15766 +.L15764: + add ip, ip, #1 + add r0, r0, fp + cmp r7, ip + mov r2, r0, asr #8 + add r6, r6, #4 + bne .L15765 +.L15754: + ldr ip, [sp, #56] + ldr lr, [sp, #64] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #56] + beq .L17699 +.L17751: + ldr lr, [sp, #56] + b .L15740 +.L15743: + tst r4, #256 + beq .L16917 + tst r4, #8192 + beq .L16919 + mov r3, r1, lsr #4 + ldr r7, .L17801+12 + and r3, r3, #992 + add r3, r3, r7 + add r1, r8, r8, lsr #31 + ldrh ip, [r3, #30] + mov r7, r1, asr #1 + ldrh r0, [r3, #6] + add r2, sl, sl, lsr #31 + ldr r1, [sp, #12] + tst r4, #512 + mov r4, r2, asr #1 + str ip, [sp, #36] + str r0, [sp, #32] + moveq r9, sl + moveq ip, r4 + moveq r0, r7 + movne r9, sl, asl #1 + movne ip, r4, asl #1 + movne r0, r7, asl #1 + cmp r6, r1 + ldrh r2, [r3, #14] + ldrh fp, [r3, #22] + bge .L16924 + rsb r1, r6, r1 + rsb r9, r1, r9 + cmp r9, #0 + ble .L15754 + ldr r6, [sp, #12] + rsb ip, r1, ip +.L16924: + ldr r1, [sp, #8] + add r3, r6, r9 + cmp r3, r1 + blt .L16927 + rsb r9, r6, r1 + cmp r9, #0 + ble .L15754 +.L16927: + add r0, r5, r0 + ldr r5, [sp, #32] + mov r2, r2, asl #16 + mov r3, r5, asl #16 + ldr r5, [sp, #36] + mov r3, r3, asr #16 + mov r1, r5, asl #16 + str r3, [sp, #80] + mov r5, r2, asr #16 + ldr r3, [sp, #60] + ldr r2, [sp, #4] + mov r4, r4, asl #8 + cmp fp, #0 + str r4, [sp, #132] + mov r1, r1, asr #16 + mov r4, r7, asl #8 + rsb r0, r0, r3 + add r7, r2, r6, asl #2 + bne .L16929 + mla r3, r0, r1, r4 + mov r2, r3, asr #8 + cmp r2, r8 + bcs .L15754 + mov r3, lr, asl #22 + mov r1, r2, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r1, asl #5 + and r2, r2, #7 + ldr r4, .L17801+24 + add r2, r2, r3, asl #2 + cmp r9, #0 + add lr, r4, r2, asl #3 + ble .L15754 + ldr r2, [sp, #80] + mul r3, r0, r5 + mul r2, ip, r2 + ldr r5, [sp, #132] + rsb r3, r2, r3 + add r0, r5, r3 + mov r4, r0, asr #8 + cmp r4, sl + movcs ip, fp + bcs .L16935 + b .L17794 +.L16936: + cmp r4, sl + bcc .L17737 +.L16935: + ldr r8, [sp, #80] + add ip, ip, #1 + add r0, r0, r8 + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #4 + bne .L16936 + ldr ip, [sp, #56] + ldr lr, [sp, #64] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #56] + bne .L17751 +.L17699: + add sp, sp, #140 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L15745: + ldr r2, [sp, #60] + tst r1, #8192 + rsb r0, r5, r2 + rsbne r3, r0, r8 + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, ip, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L15754 + .p2align 2 +.L15836: + .word .L15832 + .word .L15833 + .word .L15834 + .word .L15835 +.L16917: + ldr r2, [sp, #60] + tst r1, #8192 + rsb r0, r5, r2 + rsbne r3, r0, r8 + subne r0, r3, #1 + mov r2, r1, asl #19 + and r3, ip, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L15754 + .p2align 2 +.L16998: + .word .L16994 + .word .L16995 + .word .L16996 + .word .L16997 +.L16919: + mov r3, r1, lsr #4 + ldr r1, .L17801+12 + and r3, r3, #992 + add r3, r3, r1 + tst r4, #512 + add r1, r8, r8, lsr #31 + ldrh r4, [r3, #30] + mov r7, r1, asr #1 + add r2, sl, sl, lsr #31 + ldr r1, [sp, #12] + ldrh ip, [r3, #6] + str r4, [sp, #48] + mov r4, r2, asr #1 + ldrh r2, [r3, #14] + ldrh r3, [r3, #22] + moveq fp, sl + moveq r9, r4 + moveq r0, r7 + movne fp, sl, asl #1 + movne r9, r4, asl #1 + movne r0, r7, asl #1 + cmp r6, r1 + str ip, [sp, #40] + str r3, [sp, #44] + bge .L16956 + rsb r1, r6, r1 + rsb fp, r1, fp + cmp fp, #0 + ble .L15754 + ldr r6, [sp, #12] + rsb r9, r1, r9 +.L16956: + ldr ip, [sp, #8] + add r3, r6, fp + cmp r3, ip + blt .L16959 + rsb fp, r6, ip + cmp fp, #0 + ble .L15754 +.L16959: + add ip, r5, r0 + ldr r0, [sp, #40] + ldr r5, [sp, #48] + mov r3, r0, asl #16 + ldr r0, [sp, #44] + mov r2, r2, asl #16 + mov r3, r3, asr #16 + mov r1, r5, asl #16 + cmp r0, #0 + str r3, [sp, #84] + mov r0, lr, lsr #8 + mov r5, r2, asr #16 + ldr r3, [sp, #60] + ldr r2, [sp, #4] + mov r4, r4, asl #8 + and r0, r0, #240 + str r4, [sp, #92] + mov r1, r1, asr #16 + mov r4, r7, asl #8 + rsb ip, ip, r3 + add r7, r2, r6, asl #2 + str r0, [sp, #116] + bne .L16961 + mla r3, ip, r1, r4 + mov r2, r3, asr #8 + cmp r2, r8 + bcs .L15754 + mov r3, lr, asl #22 + mov r1, r2, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r1, asl #5 + and r2, r2, #7 + ldr r4, .L17801+24 + add r2, r2, r3, asl #3 + cmp fp, #0 + add r1, r4, r2, asl #2 + ble .L15754 + ldr r2, [sp, #84] + mul r3, ip, r5 + mul r2, r9, r2 + ldr r5, [sp, #92] + rsb r3, r2, r3 + add r0, r5, r3 + mov r3, r0, asr #8 + cmp r3, sl + mov r4, r3 + ldrcs r5, [sp, #44] + bcs .L16967 + b .L17795 +.L16968: + cmp r3, sl + bcc .L16969 +.L16967: + ldr r8, [sp, #84] + add r5, r5, #1 + add r0, r0, r8 + mov r3, r0, asr #8 + cmp fp, r5 + add r7, r7, #4 + mov r4, r3 + bne .L16968 + b .L15754 +.L15747: + mov r3, r1, lsr #4 + ldr r7, .L17801+12 + and r3, r3, #992 + add r3, r3, r7 + add r1, r8, r8, lsr #31 + tst r4, #512 + ldrh r0, [r3, #6] + add r2, sl, sl, lsr #31 + mov r7, r1, asr #1 + ldrh ip, [r3, #30] + ldrh r1, [r3, #14] + ldrh fp, [r3, #22] + ldr r3, [sp, #12] + mov r4, r2, asr #1 + movne r2, sl, asl #1 + str r0, [sp, #24] + streq sl, [sp, #136] + moveq r9, r4 + moveq r0, r7 + strne r2, [sp, #136] + movne r9, r4, asl #1 + movne r0, r7, asl #1 + cmp r6, r3 + str ip, [sp, #28] + bge .L15790 + ldr ip, [sp, #136] + rsb r2, r6, r3 + rsb ip, r2, ip + cmp ip, #0 + str ip, [sp, #136] + ble .L15754 + rsb r9, r2, r9 + mov r6, r3 +.L15790: + ldr r2, [sp, #136] + ldr ip, [sp, #8] + add r3, r6, r2 + cmp r3, ip + blt .L15793 + rsb r2, r6, ip + cmp r2, #0 + str r2, [sp, #136] + ble .L15754 +.L15793: + add ip, r5, r0 + ldr r5, [sp, #24] + ldr r0, [sp, #28] + mov r3, r5, asl #16 + mov r2, r1, asl #16 + mov r3, r3, asr #16 + mov r1, r0, asl #16 + str r3, [sp, #72] + mov r0, lr, lsr #8 + mov r5, r2, asr #16 + ldr r3, [sp, #60] + ldr r2, [sp, #4] + mov r4, r4, asl #8 + and r0, r0, #240 + cmp fp, #0 + str r4, [sp, #124] + mov r1, r1, asr #16 + mov r4, r7, asl #8 + rsb ip, ip, r3 + add r7, r2, r6, asl #2 + str r0, [sp, #120] + bne .L15795 + mla r3, ip, r1, r4 + mov r2, r3, asr #8 + cmp r2, r8 + bcs .L15754 + mov r3, lr, asl #22 + mov r1, r2, lsr #3 + mov r3, r3, lsr #22 + ldr r4, [sp, #136] + add r3, r3, r1, asl #5 + and r2, r2, #7 + ldr r8, .L17801+24 + add r2, r2, r3, asl #3 + cmp r4, #0 + add lr, r8, r2, asl #2 + ble .L15754 + ldr r2, [sp, #72] + mul r3, ip, r5 + mul r2, r9, r2 + ldr r0, [sp, #124] + rsb r3, r2, r3 + add ip, r0, r3 + mov r3, ip, asr #8 + cmp r3, sl + mov r1, r3 + movcs r4, fp + bcs .L15801 + b .L17796 +.L15802: + cmp r3, sl + bcc .L15803 +.L15801: + ldr r1, [sp, #72] + ldr r2, [sp, #136] + add ip, ip, r1 + add r4, r4, #1 + mov r3, ip, asr #8 + cmp r2, r4 + add r7, r7, #4 + mov r1, r3 + bne .L15802 + b .L15754 +.L15795: + mov r3, lr, asl #22 + ldr r0, .L17801+24 + ldr lr, [sp, #136] + mov r3, r3, lsr #22 + add r3, r0, r3, asl #5 + cmp lr, #0 + str r3, [sp, #112] + ble .L15754 + mov r3, fp, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #76] + mul r2, ip, r1 + ldr r1, [sp, #76] + ldr r0, [sp, #72] + mul r1, r9, r1 + mul r3, ip, r5 + mul r0, r9, r0 + rsb r2, r1, r2 + ldr r1, [sp, #124] + rsb r3, r0, r3 + add lr, r1, r3 + add r5, r4, r2 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + cmp ip, sl + cmpcc r4, r8 + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L15817 + b .L17797 +.L15818: + cmp ip, sl + cmpcc r4, r8 + bcc .L15820 +.L15817: + ldr r2, [sp, #72] + ldr r3, [sp, #76] + ldr r0, [sp, #136] + add r6, r6, #1 + add lr, lr, r2 + add r5, r5, r3 + cmp r0, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #4 + bne .L15818 + b .L15754 +.L17755: + mov r3, ip, asr #1 + ldr r2, [sp, #112] + and fp, r3, #3 + ldr r3, [sp, #112] + and r1, r4, #7 + and r0, r4, #7 + add r1, r2, r1, asl #2 + add r0, r3, r0, asl #2 + mov r2, ip, asr #1 + mov r3, r4, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + add r3, r3, r2, asl #5 + add r0, r0, r3 + tst ip, #1 + add r1, r1, r3 + ldrneb r3, [r1, fp] @ zero_extendqisi2 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr r4, [sp, #120] + cmp r0, #0 + orr r0, r0, r4 + beq .L15826 + ldr r2, [r7, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L15826: + ldr ip, [sp, #72] + ldr r0, [sp, #76] + ldr r1, [sp, #136] + add r6, r6, #1 + add lr, lr, ip + add r5, r5, r0 + cmp r1, r6 + add r7, r7, #4 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + ble .L15754 +.L15820: + cmp r4, r8 + cmpcc ip, sl + bcc .L17755 + b .L15754 +.L16961: + mov r3, lr, asl #22 + ldr lr, .L17801+24 + mov r3, r3, lsr #22 + add r3, lr, r3, asl #5 + cmp fp, #0 + str r3, [sp, #104] + ble .L15754 + ldr r0, [sp, #44] + mul r2, ip, r1 + mov r3, r0, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #88] + ldr r1, [sp, #88] + ldr r0, [sp, #84] + mul r1, r9, r1 + mul r3, ip, r5 + mul r0, r9, r0 + rsb r2, r1, r2 + ldr r1, [sp, #92] + rsb r3, r0, r3 + add lr, r1, r3 + add r5, r4, r2 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + cmp ip, sl + movcs r3, #0 + movcc r3, #1 + cmp r8, r4 + movls r3, #0 + cmp r3, #0 + moveq r6, r3 + beq .L16981 + b .L17798 +.L16982: + cmp ip, sl + cmpcc r4, r8 + bcc .L16983 +.L16981: + ldr r2, [sp, #84] + ldr r3, [sp, #88] + add r6, r6, #1 + add lr, lr, r2 + add r5, r5, r3 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #4 + bne .L16982 + b .L15754 +.L16938: + cmp r4, sl + bcs .L15754 +.L17737: + ldr r1, [sp, #80] + mov r3, r4, asr #3 + add r0, r0, r1 + add r3, lr, r3, asl #6 + and r1, r4, #7 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #52] + cmp r2, #0 + add ip, ip, #1 + orr r3, r5, r2 + strne r3, [r7, #0] + cmp r9, ip + mov r4, r0, asr #8 + add r7, r7, #4 + bgt .L16938 + b .L15754 +.L15758: + mov r3, lr, asl #22 + ldr r2, .L17801+24 + mov r3, r3, lsr #22 + cmp r7, #0 + add lr, r2, r3, asl #5 + ble .L15754 + ldr r2, [sp, #16] + mov r3, r2, asl #16 + mov r9, r3, asr #16 + mul r2, r0, r1 + mul r3, r0, r5 + mul r1, r9, ip + mul r0, fp, ip + ldr r5, [sp, #100] + rsb r2, r1, r2 + rsb r3, r0, r3 + add r0, r5, r3 + add r5, r4, r2 + mov r1, r5, asr #8 + mov r4, r0, asr #8 + cmp r4, sl + cmpcc r1, r8 + movcs r3, #0 + movcc r3, #1 + movcs ip, r3 + bcs .L15777 + b .L17799 +.L15778: + cmp r4, sl + cmpcc r1, r8 + bcc .L15780 +.L15777: + add ip, ip, #1 + add r0, r0, fp + add r5, r5, r9 + cmp r7, ip + mov r4, r0, asr #8 + mov r1, r5, asr #8 + add r6, r6, #4 + bne .L15778 + b .L15754 +.L17758: + and r3, r1, #7 + mov r2, r4, asr #3 + mov r3, r3, asl #3 + add r3, r3, r2, asl #6 + mov r1, r1, asr #3 + add r3, r3, r1, asl #10 + and r2, r4, #7 + add r3, r3, lr + ldrb r4, [r3, r2] @ zero_extendqisi2 + cmp r4, #0 + beq .L15783 + ldr r3, [r6, #0] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r1, r4, r3, asl #16 + orr r2, r2, #768 + tst r3, #256 + orr r2, r4, r2 + orr r1, r1, #768 + strne r2, [r6, #0] + streq r1, [r6, #0] +.L15783: + add ip, ip, #1 + add r0, r0, fp + add r5, r5, r9 + cmp r7, ip + mov r4, r0, asr #8 + mov r1, r5, asr #8 + add r6, r6, #4 + ble .L15754 +.L15780: + cmp r1, r8 + cmpcc r4, sl + bcc .L17758 + b .L15754 +.L16929: + mov r3, lr, asl #22 + ldr lr, .L17801+24 + mov r3, r3, lsr #22 + add r3, lr, r3, asl #5 + cmp r9, #0 + str r3, [sp, #108] + ble .L15754 + mov r3, fp, asl #16 + mul r2, r0, r1 + mov fp, r3, asr #16 + mul r3, r0, r5 + ldr r0, [sp, #80] + mul r1, fp, ip + mul r0, ip, r0 + rsb r3, r0, r3 + ldr r0, [sp, #132] + rsb r2, r1, r2 + add r5, r0, r3 + add lr, r4, r2 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + cmp ip, sl + cmpcc r4, r8 + movcs r3, #0 + movcc r3, #1 + movcs r6, r3 + bcs .L16945 + b .L17800 +.L16946: + cmp ip, sl + cmpcc r4, r8 + bcc .L16948 +.L16945: + ldr r1, [sp, #80] + add r6, r6, #1 + add r5, r5, r1 + add lr, lr, fp + cmp r9, r6 + mov ip, r5, asr #8 + mov r4, lr, asr #8 + add r7, r7, #4 + bne .L16946 + b .L15754 +.L17760: + ldr r2, [sp, #80] + and r3, r4, #7 + add r5, r5, r2 + mov r3, r3, asl #3 + mov r2, ip, asr #3 + mov r1, r4, asr #3 + add r3, r3, r2, asl #6 + add r3, r3, r1, asl #10 + ldr r1, [sp, #108] + and r0, ip, #7 + add r3, r3, r1 + ldrb r2, [r3, r0] @ zero_extendqisi2 + ldr r0, [sp, #52] + cmp r2, #0 + add r6, r6, #1 + orr r3, r0, r2 + strne r3, [r7, #0] + add lr, lr, fp + cmp r9, r6 + mov r4, lr, asr #8 + mov ip, r5, asr #8 + add r7, r7, #4 + ble .L15754 +.L16948: + cmp r4, r8 + cmpcc ip, sl + bcc .L17760 + b .L15754 +.L16994: + mov r3, lr, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + ldr r4, .L17801+24 + cmp r6, r3 + mov r3, lr, lsr #8 + and r7, r3, #240 + add r0, r4, r1, asl #2 + bge .L16999 + ldr r5, [sp, #12] + rsb r4, r6, r5 + rsb lr, r4, sl + cmp lr, #0 + ble .L15754 + ldr r8, [sp, #8] + add r3, r6, sl + cmp r8, r3 + bhi .L17002 + mov r3, r4, lsr #3 + mov r1, r3, asl #5 + ands r3, r4, #7 + add r4, r0, r1 + bne .L17004 + ldr r5, [sp, #128] + ldr r6, [sp, #96] +.L17006: + movs lr, r5, lsr #3 + beq .L17023 + mov r1, r6 + mov r0, r4 + mov ip, #0 +.L17025: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L17026 + ands r3, r2, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #28 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r1, #28] +.L17026: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #32 + add r1, r1, #32 + bne .L17025 + mov r3, lr, asl #5 + add r4, r4, r3 + add r6, r6, r3 +.L17023: + ands r0, r5, #7 + beq .L15754 + ldr r2, [r4, #0] + mov r1, #0 +.L17045: + ldr r4, [sp, #52] + ands r3, r2, #15 + orr r3, r4, r3 + orr r3, r7, r3 + strne r3, [r6, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #4 + bne .L17045 + b .L15754 +.L16995: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + subs r2, sl, #8 + mov r3, r3, lsr #22 + submi r2, sl, #1 + add r3, r3, r1, asl #5 + ldr r5, [sp, #12] + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr r8, .L17801+24 + add r1, r1, r3, asl #3 + cmp r6, r5 + mov r3, lr, lsr #8 + and r7, r3, #240 + add r0, r8, r1, asl #2 + bge .L17129 + rsb r4, r6, r5 + rsb r1, r4, sl + cmp r1, #0 + ble .L15754 + ldr ip, [sp, #8] + add r3, r6, sl + cmp ip, r3 + bhi .L17132 + mov r3, r4, lsr #3 + ands r5, r4, #7 + sub r0, r0, r3, asl #5 + bne .L17134 + ldr r2, [sp, #128] + ldr r1, [sp, #96] +.L17136: + movs r8, r2, lsr #3 + beq .L17153 + mov r5, r1 + mov r6, r0 + mov lr, #0 +.L17155: + ldr r4, [r6, #0] + cmp r4, #0 + beq .L17156 + ands r3, r4, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + orrne r3, r7, r3 + strne r3, [r5, #0] +.L17156: + add lr, lr, #1 + cmp lr, r8 + sub r6, r6, #32 + add r5, r5, #32 + bne .L17155 + rsb r3, r8, r8, asl #27 + add r0, r0, r3, asl #5 + add r1, r1, r8, asl #5 +.L17153: + ands lr, r2, #7 + beq .L15754 + ldr r0, [r0, #0] + mov r2, #0 +.L17175: + ldr r5, [sp, #52] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r7, r3 + strne r3, [r1, r2, asl #2] + add r2, r2, #1 + cmp r2, lr + mov r0, r0, asl #4 + bne .L17175 + b .L15754 +.L17802: + .align 2 +.L17801: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word oam_ram + .word obj_height_table + .word obj_width_table + .word vram+65536 +.L16996: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + mov r3, r3, lsr #22 + and r2, r0, #7 + add r3, r3, r1, asl #5 + ldr r5, [sp, #12] + add r2, r2, r3, asl #2 + ldr r7, .L17801+24 + mov r0, r2, asl #3 + cmp r6, r5 + add ip, r0, r7 + bge .L17259 + rsb r0, r6, r5 + rsb lr, r0, sl + cmp lr, #0 + ble .L15754 + ldr r8, [sp, #8] + add r3, r6, sl + cmp r8, r3 + bhi .L17262 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r6, ip, r3, asl #6 + bne .L17264 + ldr r5, [sp, #128] + ldr r4, [sp, #96] +.L17266: + movs lr, r5, lsr #3 + beq .L17324 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L17326: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L17327 + ands r3, r2, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #12] +.L17327: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L17336 + ands r3, r2, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #28] +.L17336: + add ip, ip, #1 + cmp lr, ip + add r0, r0, #64 + add r1, r1, #32 + bne .L17326 + add r6, r6, lr, asl #6 + add r4, r4, lr, asl #5 +.L17324: + ands r0, r5, #7 + beq .L15754 + cmp r0, #3 + ldrls r1, [r6, #0] + bls .L17359 + ldr r2, [r6, #0] + cmp r2, #0 + beq .L17349 + ands r3, r2, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r4, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + strne r3, [r4, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #52] + orrne r3, r1, r3 + strne r3, [r4, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r4, #12] +.L17349: + subs r0, r0, #4 + ldr r1, [r6, #4] + addne r4, r4, #16 + beq .L15754 +.L17359: + mov r2, #0 +.L17360: + ldr r5, [sp, #52] + ands r3, r1, #255 + orr r3, r5, r3 + strne r3, [r4, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bhi .L17360 + b .L15754 +.L15834: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + mov r3, r3, lsr #22 + and r2, r0, #7 + add r3, r3, r1, asl #5 + ldr r4, [sp, #12] + add r2, r2, r3, asl #2 + ldr r5, .L17801+24 + mov r0, r2, asl #3 + cmp r6, r4 + add ip, r0, r5 + bge .L16245 + rsb r0, r6, r4 + rsb r7, r0, sl + cmp r7, #0 + ble .L15754 + ldr r8, [sp, #8] + add r3, r6, sl + cmp r8, r3 + bhi .L16248 + mov r3, r0, lsr #3 + ands lr, r0, #7 + add r7, ip, r3, asl #6 + bne .L16250 + ldr r6, [sp, #128] + ldr lr, [sp, #96] +.L16252: + movs r5, r6, lsr #3 + beq .L16330 + mov r0, lr + mov ip, r7 + mov r4, #0 +.L16332: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L16333 + ands r1, r2, #255 + beq .L16335 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L16335: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16339 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L16339: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16343 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L16343: + movs r2, r2, lsr #24 + beq .L16333 + ldr r1, [r0, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L16333: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L16350 + ands r1, r2, #255 + beq .L16352 + ldr r3, [r0, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L16352: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16356 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L16356: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16360 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L16360: + movs r2, r2, lsr #24 + beq .L16350 + ldr r3, [r0, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L16350: + add r4, r4, #1 + cmp r4, r5 + add ip, ip, #64 + add r0, r0, #32 + bne .L16332 + add r7, r7, r5, asl #6 + add lr, lr, r5, asl #5 +.L16330: + ands r5, r6, #7 + beq .L15754 + cmp r5, #3 + ldrls ip, [r7, #0] + bls .L16389 + ldr r2, [r7, #0] + cmp r2, #0 + beq .L16371 + ands r1, r2, #255 + beq .L16373 + ldr r3, [lr, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [lr, #0] + streq r3, [lr, #0] +.L16373: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16377 + ldr r3, [lr, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [lr, #4] + streq r3, [lr, #4] +.L16377: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16381 + ldr r3, [lr, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [lr, #8] + streq r3, [lr, #8] +.L16381: + movs r2, r2, lsr #24 + beq .L16371 + ldr r1, [lr, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [lr, #12] + streq r3, [lr, #12] +.L16371: + subs r5, r5, #4 + ldr ip, [r7, #4] + addne lr, lr, #16 + beq .L15754 +.L16389: + mov r4, #0 +.L16390: + ands r0, ip, #255 + beq .L16391 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16391: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bhi .L16390 + b .L15754 +.L15832: + mov r3, lr, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + add r1, r1, r3, asl #3 + ldr r3, [sp, #12] + ldr r4, .L17801+24 + cmp r6, r3 + mov r3, lr, lsr #8 + and r7, r3, #240 + add r0, r4, r1, asl #2 + bge .L15837 + ldr r5, [sp, #12] + rsb r4, r6, r5 + rsb r8, r4, sl + cmp r8, #0 + ble .L15754 + ldr ip, [sp, #8] + add r3, r6, sl + cmp ip, r3 + bhi .L15840 + mov r3, r4, lsr #3 + mov r1, r3, asl #5 + ands r3, r4, #7 + add r8, r0, r1 + bne .L15842 + ldr sl, [sp, #128] + ldr r5, [sp, #96] +.L15844: + movs r6, sl, lsr #3 + beq .L15865 + mov ip, r5 + mov lr, r8 + mov r4, #0 +.L15867: + ldr r0, [lr, #0] + cmp r0, #0 + beq .L15868 + ands r2, r0, #15 + beq .L15870 + ldr r1, [ip, #0] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L15870: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L15874 + ldr r1, [ip, #4] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L15874: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L15878 + ldr r1, [ip, #8] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L15878: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L15882 + ldr r1, [ip, #12] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L15882: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L15886 + ldr r1, [ip, #16] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L15886: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L15890 + ldr r1, [ip, #20] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L15890: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L15894 + ldr r1, [ip, #24] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L15894: + movs r2, r0, lsr #28 + beq .L15868 + ldr r1, [ip, #28] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L15868: + add r4, r4, #1 + cmp r6, r4 + add lr, lr, #32 + add ip, ip, #32 + bne .L15867 + mov r3, r6, asl #5 + add r8, r8, r3 + add r5, r5, r3 +.L15865: + ands lr, sl, #7 + beq .L15754 + ldr ip, [r8, #0] + mov r4, #0 +.L15903: + ands r3, ip, #15 + beq .L15904 + ldr r1, [r5, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L15904: + add r4, r4, #1 + cmp lr, r4 + mov ip, ip, lsr #4 + add r5, r5, #4 + bne .L15903 + b .L15754 +.L15835: + subs r2, sl, #8 + submi r2, sl, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, lr, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + mov r0, r3, asl #3 + ldr r3, [sp, #12] + ldr r4, .L17801+24 + cmp r6, r3 + add ip, r0, r4 + bge .L16581 + rsb r0, r6, r3 + rsb r7, r0, sl + cmp r7, #0 + ble .L15754 + ldr r5, [sp, #8] + add r3, r6, sl + cmp r5, r3 + bhi .L16584 + mov r3, r0, lsr #3 + ands lr, r0, #7 + sub r8, ip, r3, asl #6 + bne .L16586 + ldr r7, [sp, #128] + ldr r5, [sp, #96] +.L16588: + movs r6, r7, lsr #3 + beq .L16666 + mov ip, r5 + mov lr, r8 + mov r4, #0 +.L16668: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L16669 + ands r1, r2, #255 + beq .L16671 + ldr r3, [ip, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L16671: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16675 + ldr r3, [ip, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L16675: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16679 + ldr r3, [ip, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L16679: + movs r2, r2, lsr #24 + beq .L16669 + ldr r3, [ip, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L16669: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L16686 + ands r2, r1, #255 + beq .L16688 + ldr r0, [ip, #28] + tst r0, #256 + movne r3, r0, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r0, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L16688: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L16692 + ldr r3, [ip, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L16692: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L16696 + ldr r3, [ip, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L16696: + movs r2, r1, lsr #24 + beq .L16686 + ldr r1, [ip, #16] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L16686: + add r4, r4, #1 + cmp r6, r4 + sub lr, lr, #64 + add ip, ip, #32 + bne .L16668 + rsb r3, r6, r6, asl #26 + add r8, r8, r3, asl #6 + add r5, r5, r6, asl #5 +.L16666: + ands lr, r7, #7 + beq .L15754 + cmp lr, #3 + ldrls ip, [r8, #4] + bls .L16725 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L16707 + ands r1, r2, #255 + beq .L16709 + ldr r3, [r5, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r5, #12] + streq r3, [r5, #12] +.L16709: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16713 + ldr r3, [r5, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r5, #8] + streq r3, [r5, #8] +.L16713: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16717 + ldr r3, [r5, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r5, #4] + streq r3, [r5, #4] +.L16717: + movs r2, r2, lsr #24 + beq .L16707 + ldr r3, [r5, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r5, #0] + streq r3, [r5, #0] +.L16707: + subs lr, lr, #4 + ldr ip, [r8, #0] + addne r5, r5, #16 + beq .L15754 +.L16725: + mov r4, #0 +.L16726: + movs r0, ip, lsr #24 + beq .L16727 + ldr r2, [r5, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r5, #0] + streq r0, [r5, #0] +.L16727: + add r4, r4, #1 + cmp r4, lr + mov ip, ip, asl #8 + add r5, r5, #4 + bcc .L16726 + b .L15754 +.L16997: + subs r2, sl, #8 + submi r2, sl, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, lr, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + add r1, r1, r2, asl #1 + and r3, r0, #7 + ldr r5, [sp, #12] + add r3, r3, r1, asl #2 + ldr r7, .L17801+24 + mov r0, r3, asl #3 + cmp r6, r5 + add r2, r0, r7 + bge .L17479 + rsb r0, r6, r5 + rsb lr, r0, sl + cmp lr, #0 + ble .L15754 + ldr r8, [sp, #8] + add r3, r6, sl + cmp r8, r3 + bhi .L17482 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r6, r2, r3, asl #6 + bne .L17484 + ldr r5, [sp, #128] + ldr r4, [sp, #96] +.L17486: + movs lr, r5, lsr #3 + beq .L17544 + mov r1, r4 + mov r0, r6 + mov ip, #0 +.L17546: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L17547 + ands r3, r2, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #0] +.L17547: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L17556 + ands r3, r2, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #28] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #24] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #20] + movs r3, r2, lsr #24 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #16] +.L17556: + add ip, ip, #1 + cmp ip, lr + sub r0, r0, #64 + add r1, r1, #32 + bne .L17546 + rsb r3, lr, lr, asl #26 + add r6, r6, r3, asl #6 + add r4, r4, lr, asl #5 +.L17544: + ands r0, r5, #7 + beq .L15754 + cmp r0, #3 + ldrls r2, [r6, #4] + bls .L17579 + ldr r2, [r6, #4] + cmp r2, #0 + beq .L17569 + ands r3, r2, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r4, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + strne r3, [r4, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r1, [sp, #52] + orrne r3, r1, r3 + strne r3, [r4, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r4, #0] +.L17569: + subs r0, r0, #4 + ldr r2, [r6, #0] + addne r4, r4, #16 + beq .L15754 +.L17579: + mov r1, #0 +.L17580: + ldr r5, [sp, #52] + movs r3, r2, lsr #24 + orr r3, r5, r3 + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bhi .L17580 + b .L15754 +.L15833: + mov r3, lr, asl #22 + mov r1, r0, lsr #3 + subs r2, sl, #8 + mov r3, r3, lsr #22 + submi r2, sl, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr ip, [sp, #12] + add r1, r1, r3, asl #3 + mov r3, lr, lsr #8 + ldr lr, .L17801+24 + cmp r6, ip + and r7, r3, #240 + add r0, lr, r1, asl #2 + bge .L16041 + rsb r4, r6, ip + rsb lr, r4, sl + cmp lr, #0 + ble .L15754 + ldr r1, [sp, #8] + add r3, r6, sl + cmp r1, r3 + bhi .L16044 + mov r3, r4, lsr #3 + ands lr, r4, #7 + sub ip, r0, r3, asl #5 + bne .L16046 + ldr sl, [sp, #128] + ldr r5, [sp, #96] +.L16048: + movs r8, sl, lsr #3 + beq .L16069 + mov r4, r5 + mov lr, ip + mov r6, #0 +.L16071: + ldr r0, [lr, #0] + cmp r0, #0 + beq .L16072 + ands r2, r0, #15 + beq .L16074 + ldr r1, [r4, #28] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L16074: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L16078 + ldr r1, [r4, #24] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L16078: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L16082 + ldr r1, [r4, #20] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L16082: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L16086 + ldr r1, [r4, #16] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L16086: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L16090 + ldr r1, [r4, #12] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L16090: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L16094 + ldr r1, [r4, #8] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L16094: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L16098 + ldr r1, [r4, #4] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L16098: + movs r2, r0, lsr #28 + beq .L16072 + ldr r1, [r4, #0] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L16072: + add r6, r6, #1 + cmp r8, r6 + sub lr, lr, #32 + add r4, r4, #32 + bne .L16071 + rsb r3, r8, r8, asl #27 + add ip, ip, r3, asl #5 + add r5, r5, r8, asl #5 +.L16069: + ands lr, sl, #7 + beq .L15754 + ldr ip, [ip, #0] + mov r4, #0 +.L16107: + movs r3, ip, lsr #28 + beq .L16108 + ldr r1, [r5, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L16108: + add r4, r4, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r5, r5, #4 + bne .L16107 + b .L15754 +.L16041: + ldr r1, [sp, #8] + add r3, r6, sl + cmp r1, r3 + bls .L17761 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs lr, r3, asr #3 + beq .L15754 + ldr r3, [sp, #4] + mov ip, #0 + add r1, r3, r6, asl #2 + b .L16210 +.L17762: + sub r0, r0, #32 + add r1, r1, #32 +.L16210: + ldr r5, [r0, #0] + cmp r5, #0 + beq .L16211 + ands r2, r5, #15 + beq .L16213 + ldr r4, [r1, #28] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L16213: + mov r3, r5, lsr #4 + ands r2, r3, #15 + beq .L16217 + ldr r4, [r1, #24] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L16217: + mov r3, r5, lsr #8 + ands r2, r3, #15 + beq .L16221 + ldr r4, [r1, #20] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L16221: + mov r3, r5, lsr #12 + ands r2, r3, #15 + beq .L16225 + ldr r4, [r1, #16] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L16225: + mov r3, r5, lsr #16 + ands r2, r3, #15 + beq .L16229 + ldr r4, [r1, #12] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L16229: + mov r3, r5, lsr #20 + ands r2, r3, #15 + beq .L16233 + ldr r4, [r1, #8] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L16233: + mov r3, r5, lsr #24 + ands r2, r3, #15 + beq .L16237 + ldr r4, [r1, #4] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L16237: + movs r2, r5, lsr #28 + beq .L16211 + ldr r4, [r1, #0] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L16211: + add ip, ip, #1 + cmp lr, ip + bne .L17762 + b .L15754 +.L16999: + ldr ip, [sp, #8] + add r3, r6, sl + cmp ip, r3 + bls .L17763 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs ip, r3, asr #3 + beq .L15754 + ldr r8, [sp, #4] + mov r2, #0 + add r1, r8, r6, asl #2 + b .L17110 +.L17764: + add r0, r0, #32 + add r1, r1, #32 +.L17110: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L17111 + ands r3, r4, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r4, lsr #28 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + orrne r3, r7, r3 + strne r3, [r1, #28] +.L17111: + add r2, r2, #1 + cmp ip, r2 + bne .L17764 + b .L15754 +.L17259: + ldr r8, [sp, #8] + add r3, r6, sl + cmp r8, r3 + bls .L17765 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs lr, r3, asr #3 + beq .L15754 + ldr r3, [sp, #4] + mov r2, #0 + add r1, r3, r6, asl #2 + ldr r3, .L17803+4 + add r0, r0, r3 + b .L17459 +.L17766: + add ip, ip, #64 + add r1, r1, #32 +.L17459: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L17460 + ands r3, r4, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #8] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r1, #12] +.L17460: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L17469 + ands r3, r4, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #24] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r1, #28] +.L17469: + add r2, r2, #1 + cmp lr, r2 + add r0, r0, #64 + bne .L17766 + b .L15754 +.L15837: + ldr r4, [sp, #8] + add r3, r6, sl + cmp r4, r3 + bls .L17767 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs lr, r3, asr #3 + beq .L15754 + ldr r8, [sp, #4] + mov ip, #0 + add r1, r8, r6, asl #2 + b .L16006 +.L17768: + add r0, r0, #32 + add r1, r1, #32 +.L16006: + ldr r5, [r0, #0] + cmp r5, #0 + beq .L16007 + ands r2, r5, #15 + beq .L16009 + ldr r4, [r1, #0] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L16009: + mov r3, r5, lsr #4 + ands r2, r3, #15 + beq .L16013 + ldr r4, [r1, #4] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L16013: + mov r3, r5, lsr #8 + ands r2, r3, #15 + beq .L16017 + ldr r4, [r1, #8] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L16017: + mov r3, r5, lsr #12 + ands r2, r3, #15 + beq .L16021 + ldr r4, [r1, #12] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L16021: + mov r3, r5, lsr #16 + ands r2, r3, #15 + beq .L16025 + ldr r4, [r1, #16] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L16025: + mov r3, r5, lsr #20 + ands r2, r3, #15 + beq .L16029 + ldr r4, [r1, #20] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L16029: + mov r3, r5, lsr #24 + ands r2, r3, #15 + beq .L16033 + ldr r4, [r1, #24] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L16033: + movs r2, r5, lsr #28 + beq .L16007 + ldr r4, [r1, #28] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L16007: + add ip, ip, #1 + cmp lr, ip + bne .L17768 + b .L15754 +.L17129: + ldr lr, [sp, #8] + add r3, r6, sl + cmp lr, r3 + bls .L17769 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs ip, r3, asr #3 + beq .L15754 + ldr r8, [sp, #4] + mov r2, #0 + add r1, r8, r6, asl #2 + b .L17240 +.L17770: + sub r0, r0, #32 + add r1, r1, #32 +.L17240: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L17241 + ands r3, r4, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + orrne r3, r7, r3 + strne r3, [r1, #0] +.L17241: + add r2, r2, #1 + cmp ip, r2 + bne .L17770 + b .L15754 +.L16581: + ldr r2, [sp, #8] + add r3, r6, sl + cmp r2, r3 + bls .L17771 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs r7, r3, asr #3 + beq .L15754 + ldr r4, [sp, #4] + ldr r3, .L17803 + add r1, r4, r6, asl #2 + add r0, r0, r3 + mov lr, #0 + b .L16881 +.L17772: + sub ip, ip, #64 + add r1, r1, #32 +.L16881: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L16882 + ands r4, r2, #255 + beq .L16884 + ldr r3, [r1, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L16884: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16888 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L16888: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16892 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L16892: + movs r2, r2, lsr #24 + beq .L16882 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L16882: + ldr r4, [ip, #0] + cmp r4, #0 + beq .L16899 + ands r2, r4, #255 + beq .L16901 + ldr r5, [r1, #28] + tst r5, #256 + movne r3, r5, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r5, asl #16 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L16901: + mov r3, r4, lsr #8 + ands r2, r3, #255 + beq .L16905 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L16905: + mov r3, r4, lsr #16 + ands r2, r3, #255 + beq .L16909 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L16909: + movs r2, r4, lsr #24 + beq .L16899 + ldr r4, [r1, #16] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L16899: + add lr, lr, #1 + cmp r7, lr + sub r0, r0, #64 + bne .L17772 + b .L15754 +.L16245: + ldr r7, [sp, #8] + add r3, r6, sl + cmp r7, r3 + bls .L17773 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs r5, r3, asr #3 + beq .L15754 + ldr r2, [sp, #4] + ldr r3, .L17803+4 + add r1, r2, r6, asl #2 + add r0, r0, r3 + mov lr, #0 + b .L16545 +.L17774: + add ip, ip, #64 + add r1, r1, #32 +.L16545: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L16546 + ands r4, r2, #255 + beq .L16548 + ldr r3, [r1, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #0] + streq r3, [r1, #0] +.L16548: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16552 + ldr r3, [r1, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #4] + streq r3, [r1, #4] +.L16552: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16556 + ldr r3, [r1, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #8] + streq r3, [r1, #8] +.L16556: + movs r2, r2, lsr #24 + beq .L16546 + ldr r4, [r1, #12] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r1, #12] + streq r3, [r1, #12] +.L16546: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L16563 + ands r4, r2, #255 + beq .L16565 + ldr r3, [r1, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #16] + streq r3, [r1, #16] +.L16565: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16569 + ldr r3, [r1, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #20] + streq r3, [r1, #20] +.L16569: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16573 + ldr r3, [r1, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r1, #24] + streq r3, [r1, #24] +.L16573: + movs r2, r2, lsr #24 + beq .L16563 + ldr r3, [r1, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r1, #28] + streq r3, [r1, #28] +.L16563: + add lr, lr, #1 + cmp r5, lr + add r0, r0, #64 + bne .L17774 + b .L15754 +.L17479: + ldr r8, [sp, #8] + add r3, r6, sl + cmp r3, r8 + bcs .L17775 + cmp sl, #0 + add r3, sl, #7 + movge r3, sl + movs lr, r3, asr #3 + beq .L15754 + ldr r5, [sp, #4] + ldr r3, .L17803 + add r1, r5, r6, asl #2 + add r0, r0, r3 + mov ip, #0 + b .L17679 +.L17776: + sub r2, r2, #64 + add r1, r1, #32 +.L17679: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L17680 + ands r3, r4, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #4] + movs r3, r4, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #0] +.L17680: + ldr r4, [r2, #0] + cmp r4, #0 + beq .L17689 + ands r3, r4, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #20] + movs r3, r4, lsr #24 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #16] +.L17689: + add ip, ip, #1 + cmp lr, ip + sub r0, r0, #64 + bne .L17776 + b .L15754 +.L17798: + mov r6, #0 +.L16983: + cmp r8, r4 + cmphi sl, ip + bhi .L17740 + b .L15754 +.L16984: + cmp r4, r8 + cmpcc ip, sl + bcs .L15754 +.L17740: + mov r3, ip, asr #1 + ldr r1, [sp, #104] + and r3, r3, #3 + and r0, r4, #7 + str r3, [sp, #0] + ldr r3, [sp, #104] + add r0, r1, r0, asl #2 + and r1, r4, #7 + mov r2, ip, asr #1 + add r1, r3, r1, asl #2 + mov r3, r4, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, ip, asr #3 + tst ip, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne r4, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, r4] @ zero_extendqisi2 + ldr r2, [sp, #52] + movne r0, r3, lsr #4 + andeq r0, r3, #15 + cmp r0, #0 + orr r3, r0, r2 + ldr r0, [sp, #116] + ldr ip, [sp, #84] + ldr r1, [sp, #88] + add r6, r6, #1 + orr r3, r0, r3 + strne r3, [r7, #0] + add lr, lr, ip + add r5, r5, r1 + cmp fp, r6 + mov ip, lr, asr #8 + mov r4, r5, asr #8 + add r7, r7, #4 + bgt .L16984 + b .L15754 +.L17775: + rsb r7, r6, r8 + cmp r7, #0 + ble .L15754 + ldr ip, [sp, #4] + movs lr, r7, lsr #3 + add r1, ip, r6, asl #2 + beq .L17638 + ldr r3, .L17803 + mov r5, r1 + add r0, r0, r3 + mov r6, r2 + mov ip, #0 +.L17640: + ldr r4, [r0, #68] + cmp r4, #0 + beq .L17641 + ands r3, r4, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r5, #0] +.L17641: + ldr r4, [r6, #0] + cmp r4, #0 + beq .L17650 + ands r3, r4, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r5, #20] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r5, #16] +.L17650: + add ip, ip, #1 + cmp lr, ip + sub r6, r6, #64 + add r5, r5, #32 + sub r0, r0, #64 + bne .L17640 + rsb r3, lr, lr, asl #26 + add r2, r2, r3, asl #6 + add r1, r1, lr, asl #5 +.L17638: + ands ip, r7, #7 + beq .L15754 + cmp ip, #3 + ldrls r2, [r2, #4] + bls .L17673 + ldr r0, [r2, #4] + cmp r0, #0 + beq .L17663 + ands r3, r0, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #12] + mov r3, r0, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, r0, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #4] + movs r3, r0, lsr #24 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + strne r3, [r1, #0] +.L17663: + subs ip, ip, #4 + ldr r2, [r2, #0] + addne r1, r1, #16 + beq .L15754 +.L17673: + mov r0, #0 +.L17674: + ldr r4, [sp, #52] + movs r3, r2, lsr #24 + orr r3, r4, r3 + strne r3, [r1, r0, asl #2] + add r0, r0, #1 + cmp ip, r0 + mov r2, r2, asl #8 + bhi .L17674 + b .L15754 +.L17767: + rsb ip, r6, r4 + cmp ip, #0 + ble .L15754 + ldr r5, [sp, #4] + movs sl, ip, lsr #3 + add r8, r5, r6, asl #2 + beq .L15961 + mov r6, r8 + mov lr, r0 + mov r1, #0 +.L15963: + ldr r5, [lr, #0] + cmp r5, #0 + beq .L15964 + ands r2, r5, #15 + beq .L15966 + ldr r4, [r6, #0] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L15966: + mov r3, r5, lsr #4 + ands r2, r3, #15 + beq .L15970 + ldr r4, [r6, #4] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L15970: + mov r3, r5, lsr #8 + ands r2, r3, #15 + beq .L15974 + ldr r4, [r6, #8] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L15974: + mov r3, r5, lsr #12 + ands r2, r3, #15 + beq .L15978 + ldr r4, [r6, #12] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L15978: + mov r3, r5, lsr #16 + ands r2, r3, #15 + beq .L15982 + ldr r4, [r6, #16] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #16] + streq r3, [r6, #16] +.L15982: + mov r3, r5, lsr #20 + ands r2, r3, #15 + beq .L15986 + ldr r4, [r6, #20] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #20] + streq r3, [r6, #20] +.L15986: + mov r3, r5, lsr #24 + ands r2, r3, #15 + beq .L15990 + ldr r4, [r6, #24] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #24] + streq r3, [r6, #24] +.L15990: + movs r2, r5, lsr #28 + beq .L15964 + ldr r4, [r6, #28] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #28] + streq r3, [r6, #28] +.L15964: + add r1, r1, #1 + cmp r1, sl + add lr, lr, #32 + add r6, r6, #32 + bne .L15963 + mov r3, sl, asl #5 + add r0, r0, r3 + add r8, r8, r3 +.L15961: + ands lr, ip, #7 + beq .L15754 + ldr ip, [r0, #0] + mov r4, #0 +.L15999: + ands r3, ip, #15 + beq .L16000 + ldr r1, [r8, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L16000: + add r4, r4, #1 + cmp lr, r4 + mov ip, ip, lsr #4 + add r8, r8, #4 + bne .L15999 + b .L15754 +.L17804: + .align 2 +.L17803: + .word vram+65472 + .word vram+65600 +.L17771: + rsb sl, r6, r2 + cmp sl, #0 + ble .L15754 + ldr r3, [sp, #4] + movs r8, sl, lsr #3 + add r7, r3, r6, asl #2 + beq .L16814 + ldr r3, .L17803 + mov r6, r7 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L16816: + ldr r2, [r0, #68] + cmp r2, #0 + beq .L16817 + ands r4, r2, #255 + beq .L16819 + ldr r3, [r6, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L16819: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16823 + ldr r3, [r6, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L16823: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16827 + ldr r3, [r6, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L16827: + movs r2, r2, lsr #24 + beq .L16817 + ldr r3, [r6, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L16817: + ldr r4, [lr, #0] + cmp r4, #0 + beq .L16834 + ands r2, r4, #255 + beq .L16836 + ldr r5, [r6, #28] + tst r5, #256 + movne r3, r5, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r5, asl #16 + strne r3, [r6, #28] + streq r3, [r6, #28] +.L16836: + mov r3, r4, lsr #8 + ands r2, r3, #255 + beq .L16840 + ldr r3, [r6, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r6, #24] + streq r3, [r6, #24] +.L16840: + mov r3, r4, lsr #16 + ands r2, r3, #255 + beq .L16844 + ldr r3, [r6, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r6, #20] + streq r3, [r6, #20] +.L16844: + movs r2, r4, lsr #24 + beq .L16834 + ldr r4, [r6, #16] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #16] + streq r3, [r6, #16] +.L16834: + add r1, r1, #1 + cmp r1, r8 + sub lr, lr, #64 + add r6, r6, #32 + sub r0, r0, #64 + bne .L16816 + rsb r3, r8, r8, asl #26 + add ip, ip, r3, asl #6 + add r7, r7, r8, asl #5 +.L16814: + ands lr, sl, #7 + beq .L15754 + cmp lr, #3 + ldrls ip, [ip, #4] + bls .L16873 + ldr r2, [ip, #4] + cmp r2, #0 + beq .L16855 + ands r1, r2, #255 + beq .L16857 + ldr r3, [r7, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #12] + streq r3, [r7, #12] +.L16857: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16861 + ldr r3, [r7, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #8] + streq r3, [r7, #8] +.L16861: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16865 + ldr r3, [r7, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r7, #4] + streq r3, [r7, #4] +.L16865: + movs r2, r2, lsr #24 + beq .L16855 + ldr r3, [r7, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r7, #0] + streq r3, [r7, #0] +.L16855: + subs lr, lr, #4 + ldr ip, [ip, #0] + addne r7, r7, #16 + beq .L15754 +.L16873: + mov r4, #0 +.L16874: + movs r0, ip, lsr #24 + beq .L16875 + ldr r2, [r7, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L16875: + add r4, r4, #1 + cmp lr, r4 + mov ip, ip, asl #8 + add r7, r7, #4 + bhi .L16874 + b .L15754 +.L17763: + rsb lr, r6, ip + cmp lr, #0 + ble .L15754 + ldr r2, [sp, #4] + movs r8, lr, lsr #3 + add r1, r2, r6, asl #2 + beq .L17083 + mov r5, r1 + mov r6, r0 + mov ip, #0 +.L17085: + ldr r4, [r6, #0] + cmp r4, #0 + beq .L17086 + ands r3, r4, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #28 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + orrne r3, r7, r3 + strne r3, [r5, #28] +.L17086: + add ip, ip, #1 + cmp ip, r8 + add r6, r6, #32 + add r5, r5, #32 + bne .L17085 + mov r3, r8, asl #5 + add r0, r0, r3 + add r1, r1, r3 +.L17083: + ands lr, lr, #7 + beq .L15754 + ldr r0, [r0, #0] + mov ip, #0 +.L17105: + ldr r5, [sp, #52] + ands r3, r0, #15 + orr r3, r5, r3 + orr r3, r7, r3 + strne r3, [r1, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, lsr #4 + bne .L17105 + b .L15754 +.L17773: + rsb r8, r6, r7 + cmp r8, #0 + ble .L15754 + ldr lr, [sp, #4] + movs r7, r8, lsr #3 + add r6, lr, r6, asl #2 + beq .L16478 + ldr r3, .L17803+4 + mov r5, r6 + add r0, r0, r3 + mov lr, ip + mov r1, #0 +.L16480: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L16481 + ands r4, r2, #255 + beq .L16483 + ldr r3, [r5, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #0] + streq r3, [r5, #0] +.L16483: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16487 + ldr r3, [r5, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #4] + streq r3, [r5, #4] +.L16487: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16491 + ldr r3, [r5, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #8] + streq r3, [r5, #8] +.L16491: + movs r2, r2, lsr #24 + beq .L16481 + ldr r4, [r5, #12] + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r5, #12] + streq r3, [r5, #12] +.L16481: + ldr r2, [r0, #-60] + cmp r2, #0 + beq .L16498 + ands r4, r2, #255 + beq .L16500 + ldr r3, [r5, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #16] + streq r3, [r5, #16] +.L16500: + mov r3, r2, lsr #8 + ands r4, r3, #255 + beq .L16504 + ldr r3, [r5, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #20] + streq r3, [r5, #20] +.L16504: + mov r3, r2, lsr #16 + ands r4, r3, #255 + beq .L16508 + ldr r3, [r5, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r4, r3, asl #16 + orrne r3, r4, r3 + orreq r3, r3, #768 + strne r3, [r5, #24] + streq r3, [r5, #24] +.L16508: + movs r2, r2, lsr #24 + beq .L16498 + ldr r3, [r5, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r5, #28] + streq r3, [r5, #28] +.L16498: + add r1, r1, #1 + cmp r7, r1 + add lr, lr, #64 + add r5, r5, #32 + add r0, r0, #64 + bne .L16480 + add ip, ip, r7, asl #6 + add r6, r6, r7, asl #5 +.L16478: + ands lr, r8, #7 + beq .L15754 + cmp lr, #3 + ldrls ip, [ip, #0] + bls .L16537 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L16519 + ands r1, r2, #255 + beq .L16521 + ldr r3, [r6, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L16521: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16525 + ldr r3, [r6, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L16525: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16529 + ldr r3, [r6, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L16529: + movs r2, r2, lsr #24 + beq .L16519 + ldr r1, [r6, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L16519: + subs lr, lr, #4 + ldr ip, [ip, #4] + addne r6, r6, #16 + beq .L15754 +.L16537: + mov r4, #0 +.L16538: + ands r0, ip, #255 + beq .L16539 + ldr r2, [r6, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r6, #0] + streq r0, [r6, #0] +.L16539: + add r4, r4, #1 + cmp r4, lr + mov ip, ip, lsr #8 + add r6, r6, #4 + bcc .L16538 + b .L15754 +.L17765: + rsb r8, r6, r8 + cmp r8, #0 + ble .L15754 + ldr r2, [sp, #4] + movs lr, r8, lsr #3 + add r1, r2, r6, asl #2 + beq .L17418 + ldr r3, .L17803+4 + mov r5, r1 + add r0, r0, r3 + mov r6, ip + mov r7, #0 +.L17420: + ldr r4, [r6, #0] + cmp r4, #0 + beq .L17421 + ands r3, r4, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #0] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #4] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #8] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r5, #12] +.L17421: + ldr r4, [r0, #-60] + cmp r4, #0 + beq .L17430 + ands r3, r4, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #8 + ands r3, r3, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #16 + ands r3, r3, #255 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r5, #24] + movs r3, r4, lsr #24 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r5, #28] +.L17430: + add r7, r7, #1 + cmp lr, r7 + add r6, r6, #64 + add r5, r5, #32 + add r0, r0, #64 + bne .L17420 + add ip, ip, lr, asl #6 + add r1, r1, lr, asl #5 +.L17418: + ands lr, r8, #7 + beq .L15754 + cmp lr, #3 + ldrls ip, [ip, #0] + bls .L17453 + ldr r2, [ip, #0] + cmp r2, #0 + beq .L17443 + ands r3, r2, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r0, [sp, #52] + orrne r3, r0, r3 + strne r3, [r1, #12] +.L17443: + subs lr, lr, #4 + ldr ip, [ip, #4] + addne r1, r1, #16 + beq .L15754 +.L17453: + mov r0, #0 +.L17454: + ldr r2, [sp, #52] + ands r3, ip, #255 + orr r3, r2, r3 + strne r3, [r1, r0, asl #2] + add r0, r0, #1 + cmp lr, r0 + mov ip, ip, lsr #8 + bhi .L17454 + b .L15754 +.L17769: + rsb r8, r6, lr + cmp r8, #0 + ble .L15754 + ldr r2, [sp, #4] + movs lr, r8, lsr #3 + add r1, r2, r6, asl #2 + beq .L17213 + mov r5, r1 + mov r6, r0 + mov ip, #0 +.L17215: + ldr r4, [r6, #0] + cmp r4, #0 + beq .L17216 + ands r3, r4, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + orrne r3, r7, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + orrne r3, r7, r3 + strne r3, [r5, #0] +.L17216: + add ip, ip, #1 + cmp ip, lr + sub r6, r6, #32 + add r5, r5, #32 + bne .L17215 + rsb r3, lr, lr, asl #27 + add r0, r0, r3, asl #5 + add r1, r1, lr, asl #5 +.L17213: + ands lr, r8, #7 + beq .L15754 + ldr r0, [r0, #0] + mov ip, #0 +.L17235: + ldr r5, [sp, #52] + movs r3, r0, lsr #28 + orr r3, r5, r3 + orr r3, r7, r3 + strne r3, [r1, ip, asl #2] + add ip, ip, #1 + cmp ip, lr + mov r0, r0, asl #4 + bne .L17235 + b .L15754 +.L17761: + rsb sl, r6, r1 + cmp sl, #0 + ble .L15754 + ldr r2, [sp, #4] + movs ip, sl, lsr #3 + add r8, r2, r6, asl #2 + beq .L16165 + mov r6, r8 + mov lr, r0 + mov r1, #0 +.L16167: + ldr r5, [lr, #0] + cmp r5, #0 + beq .L16168 + ands r2, r5, #15 + beq .L16170 + ldr r4, [r6, #28] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #28] + streq r3, [r6, #28] +.L16170: + mov r3, r5, lsr #4 + ands r2, r3, #15 + beq .L16174 + ldr r4, [r6, #24] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #24] + streq r3, [r6, #24] +.L16174: + mov r3, r5, lsr #8 + ands r2, r3, #15 + beq .L16178 + ldr r4, [r6, #20] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #20] + streq r3, [r6, #20] +.L16178: + mov r3, r5, lsr #12 + ands r2, r3, #15 + beq .L16182 + ldr r4, [r6, #16] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #16] + streq r3, [r6, #16] +.L16182: + mov r3, r5, lsr #16 + ands r2, r3, #15 + beq .L16186 + ldr r4, [r6, #12] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #12] + streq r3, [r6, #12] +.L16186: + mov r3, r5, lsr #20 + ands r2, r3, #15 + beq .L16190 + ldr r4, [r6, #8] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #8] + streq r3, [r6, #8] +.L16190: + mov r3, r5, lsr #24 + ands r2, r3, #15 + beq .L16194 + ldr r4, [r6, #4] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #4] + streq r3, [r6, #4] +.L16194: + movs r2, r5, lsr #28 + beq .L16168 + ldr r4, [r6, #0] + orr r2, r7, r2 + tst r4, #256 + movne r3, r4, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r4, asl #16 + strne r3, [r6, #0] + streq r3, [r6, #0] +.L16168: + add r1, r1, #1 + cmp ip, r1 + sub lr, lr, #32 + add r6, r6, #32 + bne .L16167 + rsb r3, ip, ip, asl #27 + add r0, r0, r3, asl #5 + add r8, r8, ip, asl #5 +.L16165: + ands lr, sl, #7 + beq .L15754 + ldr ip, [r0, #0] + mov r4, #0 +.L16203: + movs r3, ip, lsr #28 + beq .L16204 + ldr r1, [r8, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r8, #0] + streq r2, [r8, #0] +.L16204: + add r4, r4, #1 + cmp r4, lr + mov ip, ip, asl #4 + add r8, r8, #4 + bne .L16203 + b .L15754 +.L17795: + ldr r5, [sp, #44] +.L16969: + cmp sl, r3 + bhi .L17739 + b .L15754 +.L16970: + cmp r4, sl + bcs .L15754 +.L17739: + mov r3, r4, asr #1 + and r8, r3, #3 + mov r3, r4, asr #3 + mov r3, r3, asl #5 + mov r2, r4, asr #1 + tst r4, #1 + add ip, r3, r1 + and r6, r2, #3 + add r2, r3, r1 + ldreqb r3, [r2, r6] @ zero_extendqisi2 + ldrneb r3, [ip, r8] @ zero_extendqisi2 + ldr lr, [sp, #52] + movne r2, r3, lsr #4 + andeq r2, r3, #15 + cmp r2, #0 + orr r3, r2, lr + ldr r2, [sp, #116] + ldr ip, [sp, #84] + add r5, r5, #1 + orr r3, r2, r3 + strne r3, [r7, #0] + add r0, r0, ip + cmp fp, r5 + mov r4, r0, asr #8 + add r7, r7, #4 + bgt .L16970 + b .L15754 +.L17796: + mov r4, fp +.L15803: + cmp sl, r3 + bhi .L17727 + b .L15754 +.L15804: + cmp r1, sl + bcs .L15754 +.L17727: + mov r3, r1, asr #1 + and r5, r3, #3 + mov r3, r1, asr #3 + mov r3, r3, asl #5 + mov r2, r1, asr #1 + and r0, r2, #3 + tst r1, #1 + add r2, r3, lr + add r1, r3, lr + ldrneb r3, [r1, r5] @ zero_extendqisi2 + ldreqb r3, [r2, r0] @ zero_extendqisi2 + movne r0, r3, lsr #4 + andeq r0, r3, #15 + ldr r3, [sp, #120] + cmp r0, #0 + orr r0, r0, r3 + beq .L15810 + ldr r2, [r7, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r7, #0] + streq r0, [r7, #0] +.L15810: + ldr r5, [sp, #72] + ldr r8, [sp, #136] + add r4, r4, #1 + add ip, ip, r5 + cmp r8, r4 + add r7, r7, #4 + mov r1, ip, asr #8 + bgt .L15804 + b .L15754 +.L17793: + ldr ip, [sp, #16] +.L15766: + cmp sl, r2 + bhi .L17725 + b .L15754 +.L15767: + cmp r2, sl + bcs .L15754 +.L17725: + mov r3, r2, asr #3 + add r3, lr, r3, asl #6 + and r2, r2, #7 + ldrb r4, [r3, r2] @ zero_extendqisi2 + cmp r4, #0 + beq .L15770 + ldr r3, [r6, #0] + mov r2, r3, lsr #16 + mov r2, r2, asl #16 + orr r1, r4, r3, asl #16 + orr r2, r2, #768 + tst r3, #256 + orr r2, r4, r2 + orr r1, r1, #768 + strne r2, [r6, #0] + streq r1, [r6, #0] +.L15770: + add ip, ip, #1 + add r0, r0, fp + cmp r7, ip + add r6, r6, #4 + mov r2, r0, asr #8 + bgt .L15767 + b .L15754 +.L15840: + mov r3, r4, lsr #3 + mov r1, r3, asl #5 + ands r3, r4, #7 + add lr, r0, r1 + ldreq ip, [sp, #96] + bne .L17777 +.L15911: + movs r5, r8, lsr #3 + beq .L15754 + mov r4, #0 + b .L15923 +.L17778: + add lr, lr, #32 + add ip, ip, #32 +.L15923: + ldr r0, [lr, #0] + cmp r0, #0 + beq .L15924 + ands r2, r0, #15 + beq .L15926 + ldr r1, [ip, #0] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L15926: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L15930 + ldr r1, [ip, #4] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L15930: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L15934 + ldr r1, [ip, #8] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L15934: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L15938 + ldr r1, [ip, #12] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L15938: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L15942 + ldr r1, [ip, #16] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L15942: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L15946 + ldr r1, [ip, #20] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L15946: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L15950 + ldr r1, [ip, #24] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L15950: + movs r2, r0, lsr #28 + beq .L15924 + ldr r1, [ip, #28] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L15924: + add r4, r4, #1 + cmp r5, r4 + bne .L17778 + b .L15754 +.L16584: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub lr, ip, r3, asl #6 + ldreq ip, [sp, #96] + bne .L17779 +.L16734: + movs r5, r7, lsr #3 + beq .L15754 + mov r4, #0 + b .L16775 +.L17780: + sub lr, lr, #64 + add ip, ip, #32 +.L16775: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L16776 + ands r1, r2, #255 + beq .L16778 + ldr r3, [ip, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #12] + streq r3, [ip, #12] +.L16778: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16782 + ldr r3, [ip, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #8] + streq r3, [ip, #8] +.L16782: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16786 + ldr r3, [ip, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [ip, #4] + streq r3, [ip, #4] +.L16786: + movs r2, r2, lsr #24 + beq .L16776 + ldr r3, [ip, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #0] + streq r3, [ip, #0] +.L16776: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L16793 + ands r2, r1, #255 + beq .L16795 + ldr r0, [ip, #28] + tst r0, #256 + movne r3, r0, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r0, asl #16 + strne r3, [ip, #28] + streq r3, [ip, #28] +.L16795: + mov r3, r1, lsr #8 + ands r2, r3, #255 + beq .L16799 + ldr r3, [ip, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #24] + streq r3, [ip, #24] +.L16799: + mov r3, r1, lsr #16 + ands r2, r3, #255 + beq .L16803 + ldr r3, [ip, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [ip, #20] + streq r3, [ip, #20] +.L16803: + movs r2, r1, lsr #24 + beq .L16793 + ldr r1, [ip, #16] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [ip, #16] + streq r3, [ip, #16] +.L16793: + add r4, r4, #1 + cmp r5, r4 + bne .L17780 + b .L15754 +.L17262: + ands r2, r0, #7 + mov r3, r0, lsr #3 + add r0, ip, r3, asl #6 + ldreq r1, [sp, #96] + bne .L17781 +.L17366: + movs lr, lr, lsr #3 + beq .L15754 + mov ip, #0 + b .L17395 +.L17782: + add r0, r0, #64 + add r1, r1, #32 +.L17395: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L17396 + ands r3, r2, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #12] +.L17396: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L17405 + ands r3, r2, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #28] +.L17405: + add ip, ip, #1 + cmp lr, ip + bne .L17782 + b .L15754 +.L17002: + mov r3, r4, lsr #3 + mov r1, r3, asl #5 + ands r3, r4, #7 + add r4, r0, r1 + ldreq r1, [sp, #96] + bne .L17783 +.L17051: + movs ip, lr, lsr #3 + beq .L15754 + mov r0, #0 + b .L17061 +.L17784: + add r4, r4, #32 + add r1, r1, #32 +.L17061: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L17062 + ands r3, r2, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #4 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #8 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #12 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #16 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #16] + mov r3, r2, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r1, #20] + mov r3, r2, lsr #24 + ands r3, r3, #15 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + orrne r3, r7, r3 + strne r3, [r1, #24] + movs r3, r2, lsr #28 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r1, #28] +.L17062: + add r0, r0, #1 + cmp ip, r0 + bne .L17784 + b .L15754 +.L16248: + mov r3, r0, lsr #3 + ands r2, r0, #7 + add lr, ip, r3, asl #6 + ldreq r0, [sp, #96] + bne .L17785 +.L16398: + movs r4, r7, lsr #3 + beq .L15754 + mov ip, #0 + b .L16439 +.L17786: + add lr, lr, #64 + add r0, r0, #32 +.L16439: + ldr r2, [lr, #0] + cmp r2, #0 + beq .L16440 + ands r1, r2, #255 + beq .L16442 + ldr r3, [r0, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #0] + streq r3, [r0, #0] +.L16442: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16446 + ldr r3, [r0, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #4] + streq r3, [r0, #4] +.L16446: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16450 + ldr r3, [r0, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #8] + streq r3, [r0, #8] +.L16450: + movs r2, r2, lsr #24 + beq .L16440 + ldr r1, [r0, #12] + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r0, #12] + streq r3, [r0, #12] +.L16440: + ldr r2, [lr, #4] + cmp r2, #0 + beq .L16457 + ands r1, r2, #255 + beq .L16459 + ldr r3, [r0, #16] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #16] + streq r3, [r0, #16] +.L16459: + mov r3, r2, lsr #8 + ands r1, r3, #255 + beq .L16463 + ldr r3, [r0, #20] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #20] + streq r3, [r0, #20] +.L16463: + mov r3, r2, lsr #16 + ands r1, r3, #255 + beq .L16467 + ldr r3, [r0, #24] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r1, r3, asl #16 + orrne r3, r1, r3 + orreq r3, r3, #768 + strne r3, [r0, #24] + streq r3, [r0, #24] +.L16467: + movs r2, r2, lsr #24 + beq .L16457 + ldr r3, [r0, #28] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r2, r3, asl #16 + orrne r3, r2, r3 + orreq r3, r3, #768 + strne r3, [r0, #28] + streq r3, [r0, #28] +.L16457: + add ip, ip, #1 + cmp ip, r4 + bne .L17786 + b .L15754 +.L17132: + ands r2, r4, #7 + mov r3, r4, lsr #3 + sub r0, r0, r3, asl #5 + ldreq r5, [sp, #96] + bne .L17787 +.L17181: + movs r1, r1, lsr #3 + beq .L15754 + mov r2, #0 + b .L17191 +.L17788: + sub r0, r0, #32 + add r5, r5, #32 +.L17191: + ldr r4, [r0, #0] + cmp r4, #0 + beq .L17192 + ands r3, r4, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r5, #28] + mov r3, r4, lsr #4 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #24] + mov r3, r4, lsr #8 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r5, #20] + mov r3, r4, lsr #12 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r5, #16] + mov r3, r4, lsr #16 + ands r3, r3, #15 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #12] + mov r3, r4, lsr #20 + ands r3, r3, #15 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + orrne r3, r7, r3 + strne r3, [r5, #8] + mov r3, r4, lsr #24 + ands r3, r3, #15 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + orrne r3, r7, r3 + strne r3, [r5, #4] + movs r3, r4, lsr #28 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + orrne r3, r7, r3 + strne r3, [r5, #0] +.L17192: + add r2, r2, #1 + cmp r2, r1 + bne .L17788 + b .L15754 +.L16044: + mov r3, r4, lsr #3 + ands r2, r4, #7 + sub ip, r0, r3, asl #5 + ldreq r4, [sp, #96] + bne .L17789 +.L16115: + movs r5, lr, lsr #3 + beq .L15754 + mov lr, #0 + b .L16127 +.L17790: + sub ip, ip, #32 + add r4, r4, #32 +.L16127: + ldr r0, [ip, #0] + cmp r0, #0 + beq .L16128 + ands r2, r0, #15 + beq .L16130 + ldr r1, [r4, #28] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #28] + streq r3, [r4, #28] +.L16130: + mov r3, r0, lsr #4 + ands r2, r3, #15 + beq .L16134 + ldr r1, [r4, #24] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #24] + streq r3, [r4, #24] +.L16134: + mov r3, r0, lsr #8 + ands r2, r3, #15 + beq .L16138 + ldr r1, [r4, #20] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #20] + streq r3, [r4, #20] +.L16138: + mov r3, r0, lsr #12 + ands r2, r3, #15 + beq .L16142 + ldr r1, [r4, #16] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #16] + streq r3, [r4, #16] +.L16142: + mov r3, r0, lsr #16 + ands r2, r3, #15 + beq .L16146 + ldr r1, [r4, #12] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #12] + streq r3, [r4, #12] +.L16146: + mov r3, r0, lsr #20 + ands r2, r3, #15 + beq .L16150 + ldr r1, [r4, #8] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #8] + streq r3, [r4, #8] +.L16150: + mov r3, r0, lsr #24 + ands r2, r3, #15 + beq .L16154 + ldr r1, [r4, #4] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #4] + streq r3, [r4, #4] +.L16154: + movs r2, r0, lsr #28 + beq .L16128 + ldr r1, [r4, #0] + orr r2, r7, r2 + tst r1, #256 + movne r3, r1, lsr #16 + movne r3, r3, asl #16 + orreq r3, r2, #768 + orrne r2, r2, #768 + orrne r3, r3, r2 + orreq r3, r3, r1, asl #16 + strne r3, [r4, #0] + streq r3, [r4, #0] +.L16128: + add lr, lr, #1 + cmp lr, r5 + bne .L17790 + b .L15754 +.L17482: + mov r3, r0, lsr #3 + ands r1, r0, #7 + sub r2, r2, r3, asl #6 + ldreq r0, [sp, #96] + bne .L17791 +.L17586: + movs lr, lr, lsr #3 + beq .L15754 + mov ip, #0 + b .L17615 +.L17792: + sub r2, r2, #64 + add r0, r0, #32 +.L17615: + ldr r1, [r2, #4] + cmp r1, #0 + beq .L17616 + ands r3, r1, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r0, #0] +.L17616: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L17625 + ands r3, r1, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r0, #28] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r0, #24] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r0, #20] + movs r3, r1, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r0, #16] +.L17625: + add ip, ip, #1 + cmp ip, lr + bne .L17792 + b .L15754 +.L17791: + cmp r1, #3 + rsb ip, r1, #8 + bls .L17587 + cmp ip, #0 + ldr r0, [r2, #0] + ldreq r0, [sp, #96] + beq .L17591 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r1, r0, asl r3 + mov r0, #0 +.L17592: + movs r3, r1, lsr #24 + ldr r7, [sp, #52] + ldrne r8, [sp, #96] + orr r3, r7, r3 + strne r3, [r8, r0, asl #2] + add r0, r0, #1 + cmp r0, ip + mov r1, r1, asl #8 + bne .L17592 + ldr r1, [sp, #96] + add r0, r1, ip, asl #2 +.L17591: + sub r2, r2, #64 + b .L17586 +.L17789: + rsbs r8, r2, #8 + ldr r1, [ip, #0] + ldreq r4, [sp, #96] + beq .L16118 + mov r3, r2, asl #2 + mov r4, r1, asl r3 + ldr r5, [sp, #96] + mov r6, #0 +.L16119: + movs r3, r4, lsr #28 + beq .L16120 + ldr r1, [r5, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L16120: + add r6, r6, #1 + cmp r6, r8 + mov r4, r4, asl #4 + add r5, r5, #4 + bne .L16119 + ldr r0, [sp, #96] + add r4, r0, r8, asl #2 +.L16118: + sub ip, ip, #32 + b .L16115 +.L17787: + rsbs ip, r2, #8 + ldr lr, [r0, #0] + ldreq r5, [sp, #96] + beq .L17184 + mov r3, r2, asl #2 + mov r4, lr, asl r3 + mov r5, #0 +.L17185: + ldr r8, [sp, #52] + movs r3, r4, lsr #28 + ldrne lr, [sp, #96] + orr r3, r8, r3 + orr r3, r7, r3 + strne r3, [lr, r5, asl #2] + add r5, r5, #1 + cmp ip, r5 + mov r4, r4, asl #4 + bne .L17185 + ldr r2, [sp, #96] + add r5, r2, ip, asl #2 +.L17184: + sub r0, r0, #32 + b .L17181 +.L17783: + rsbs r5, r3, #8 + ldr r0, [r0, r1] + ldreq r1, [sp, #96] + beq .L17054 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L17055: + ldr r8, [sp, #52] + ands r3, r0, #15 + ldrne ip, [sp, #96] + orr r3, r8, r3 + orr r3, r7, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, r5 + mov r0, r0, lsr #4 + bne .L17055 + ldr r0, [sp, #96] + add r1, r0, r5, asl #2 +.L17054: + add r4, r4, #32 + b .L17051 +.L17781: + cmp r2, #3 + rsb ip, r2, #8 + bls .L17367 + cmp ip, #0 + ldr r1, [r0, #4] + ldreq r1, [sp, #96] + beq .L17371 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r2, r1, lsr r3 + mov r1, #0 +.L17372: + ands r3, r2, #255 + ldr r7, [sp, #52] + ldrne r8, [sp, #96] + orr r3, r7, r3 + strne r3, [r8, r1, asl #2] + add r1, r1, #1 + cmp r1, ip + mov r2, r2, lsr #8 + bne .L17372 + ldr r2, [sp, #96] + add r1, r2, ip, asl #2 +.L17371: + add r0, r0, #64 + b .L17366 +.L17785: + cmp r2, #3 + rsb r6, r2, #8 + bls .L16399 + cmp r6, #0 + ldr r1, [lr, #4] + ldreq r0, [sp, #96] + beq .L16403 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, lsr r3 + ldr r4, [sp, #96] + mov r5, #0 +.L16404: + ands r0, ip, #255 + beq .L16405 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L16405: + add r5, r5, #1 + cmp r5, r6 + mov ip, ip, lsr #8 + add r4, r4, #4 + bne .L16404 + ldr r5, [sp, #96] + add r0, r5, r6, asl #2 +.L16403: + add lr, lr, #64 + b .L16398 +.L17779: + cmp r2, #3 + rsb r6, r2, #8 + bls .L16735 + cmp r6, #0 + ldr r1, [lr, #0] + ldreq ip, [sp, #96] + beq .L16739 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr r4, [sp, #96] + mov r5, #0 +.L16740: + movs r0, ip, lsr #24 + beq .L16741 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L16741: + add r5, r5, #1 + cmp r6, r5 + mov ip, ip, asl #8 + add r4, r4, #4 + bne .L16740 + ldr r1, [sp, #96] + add ip, r1, r6, asl #2 +.L16739: + sub lr, lr, #64 + b .L16734 +.L17777: + rsbs r6, r3, #8 + ldr r0, [r0, r1] + ldreq ip, [sp, #96] + beq .L15914 + mov r3, r3, asl #2 + mov ip, r0, lsr r3 + ldr r4, [sp, #96] + mov r5, #0 +.L15915: + ands r3, ip, #15 + beq .L15916 + ldr r1, [r4, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L15916: + add r5, r5, #1 + cmp r6, r5 + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L15915 + ldr r3, [sp, #96] + add ip, r3, r6, asl #2 +.L15914: + add lr, lr, #32 + b .L15911 +.L15842: + ldr lr, [sp, #128] + rsb r6, r3, #8 + cmp lr, r6 + bge .L15845 + cmp lr, #0 + ble .L15754 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr r4, [sp, #96] + mov lr, #0 +.L15849: + ands r3, ip, #15 + beq .L15850 + ldr r1, [r4, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L15850: + ldr r0, [sp, #128] + add lr, lr, #1 + cmp r0, lr + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L15849 + b .L15754 +.L16586: + ldr r7, [sp, #128] + rsb r6, lr, #8 + cmp r7, r6 + bge .L16589 + cmp r7, #0 + ble .L15754 + cmp lr, #3 + bls .L16592 + mov r3, lr, asl #3 + ldr r2, [r8, #0] + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16595: + movs r0, ip, lsr #24 + beq .L16596 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16596: + ldr r8, [sp, #128] + add r4, r4, #1 + cmp r8, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16595 + b .L15754 +.L17484: + ldr lr, [sp, #128] + rsb r0, ip, #8 + cmp lr, r0 + bge .L17487 + cmp lr, #0 + ble .L15754 + cmp ip, #3 + bls .L17490 + ldr r2, [r6, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L17493: + movs r3, r2, lsr #24 + ldr r0, [sp, #52] + ldrne r4, [sp, #96] + orr r3, r0, r3 + ldr r5, [sp, #128] + strne r3, [r4, r1, asl #2] + add r1, r1, #1 + cmp r5, r1 + mov r2, r2, asl #8 + bne .L17493 + b .L15754 +.L16046: + ldr r2, [sp, #128] + rsb r6, lr, #8 + cmp r2, r6 + bge .L16049 + cmp r2, #0 + ble .L15754 + ldr r2, [ip, #0] + mov r3, lr, asl #2 + mov ip, r2, asl r3 + ldr r4, [sp, #96] + mov lr, #0 +.L16053: + movs r3, ip, lsr #28 + beq .L16054 + ldr r1, [r4, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L16054: + ldr r3, [sp, #128] + add lr, lr, #1 + cmp r3, lr + mov ip, ip, asl #4 + add r4, r4, #4 + bne .L16053 + b .L15754 +.L17134: + ldr r1, [sp, #128] + rsb lr, r5, #8 + cmp r1, lr + bge .L17137 + cmp r1, #0 + ble .L15754 + ldr r2, [r0, #0] + mov r3, r5, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L17141: + ldr r4, [sp, #52] + movs r3, r0, lsr #28 + ldrne r5, [sp, #96] + orr r3, r4, r3 + orr r3, r7, r3 + ldr r8, [sp, #128] + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r8, r2 + mov r0, r0, asl #4 + bne .L17141 + b .L15754 +.L17264: + ldr ip, [sp, #128] + rsb r0, lr, #8 + cmp ip, r0 + bge .L17267 + cmp ip, #0 + ble .L15754 + cmp lr, #3 + bls .L17270 + ldr r2, [r6, #4] + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L17273: + ands r3, r1, #255 + ldr lr, [sp, #52] + ldrne r0, [sp, #96] + orr r3, lr, r3 + strne r3, [r0, r2, asl #2] + ldr r3, [sp, #128] + add r2, r2, #1 + cmp r3, r2 + mov r1, r1, lsr #8 + bne .L17273 + b .L15754 +.L17004: + ldr ip, [sp, #128] + rsb lr, r3, #8 + cmp ip, lr + bge .L17007 + cmp ip, #0 + ble .L15754 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L17011: + ldr lr, [sp, #52] + ands r3, r0, #15 + ldrne r1, [sp, #96] + orr r3, lr, r3 + orr r3, r7, r3 + strne r3, [r1, r2, asl #2] + ldr r3, [sp, #128] + add r2, r2, #1 + cmp r3, r2 + mov r0, r0, lsr #4 + bne .L17011 + b .L15754 +.L16250: + ldr ip, [sp, #128] + rsb r5, lr, #8 + cmp ip, r5 + bge .L16253 + cmp ip, #0 + ble .L15754 + cmp lr, #3 + bls .L16256 + mov r3, lr, asl #3 + ldr r2, [r7, #4] + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16259: + ands r0, ip, #255 + beq .L16260 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16260: + ldr r0, [sp, #128] + add r4, r4, #1 + cmp r0, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16259 + b .L15754 +.L16399: + subs r8, r6, #4 + ldr r1, [lr, #0] + ldreq r2, [sp, #96] + beq .L16413 + mov r3, r2, asl #3 + mov ip, r1, lsr r3 + ldr r4, [sp, #96] + mov r5, #0 +.L16414: + ands r0, ip, #255 + beq .L16415 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L16415: + add r5, r5, #1 + cmp r8, r5 + mov ip, ip, lsr #8 + add r4, r4, #4 + bne .L16414 + ldr r4, [sp, #96] + add r3, r4, r6, asl #2 + sub r2, r3, #16 +.L16413: + ldr r1, [lr, #4] + cmp r1, #0 + beq .L16421 + ands r0, r1, #255 + beq .L16423 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L16423: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L16427 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L16427: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L16431 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L16431: + movs r1, r1, lsr #24 + beq .L16421 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #12] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #12] +.L16421: + add r0, r2, #16 + add lr, lr, #64 + b .L16398 +.L16735: + subs r8, r6, #4 + ldr r1, [lr, #4] + ldreq r2, [sp, #96] + beq .L16749 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov ip, r1, asl r3 + ldr r4, [sp, #96] + mov r5, #0 +.L16750: + movs r0, ip, lsr #24 + beq .L16751 + ldr r2, [r4, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [r4, #0] + streq r0, [r4, #0] +.L16751: + add r5, r5, #1 + cmp r8, r5 + mov ip, ip, asl #8 + add r4, r4, #4 + bne .L16750 + ldr r0, [sp, #96] + add r3, r0, r6, asl #2 + sub r2, r3, #16 +.L16749: + ldr r1, [lr, #0] + cmp r1, #0 + beq .L16757 + ands r0, r1, #255 + beq .L16759 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L16759: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L16763 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L16763: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L16767 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L16767: + movs r1, r1, lsr #24 + beq .L16757 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #0] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #0] +.L16757: + add ip, r2, #16 + sub lr, lr, #64 + b .L16734 +.L15845: + cmp r6, #0 + ldr r2, [r8, #0] + ldreq r5, [sp, #96] + beq .L15857 + mov r3, r3, asl #2 + mov ip, r2, lsr r3 + ldr r4, [sp, #96] + mov lr, #0 +.L15858: + ands r3, ip, #15 + beq .L15859 + ldr r1, [r4, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r4, #0] + streq r2, [r4, #0] +.L15859: + add lr, lr, #1 + cmp r6, lr + mov ip, ip, lsr #4 + add r4, r4, #4 + bne .L15858 + ldr r1, [sp, #96] + add r5, r1, r6, asl #2 +.L15857: + ldr r2, [sp, #128] + add r8, r8, #32 + rsb sl, r6, r2 + b .L15844 +.L17587: + subs r4, ip, #4 + ldr r0, [r2, #4] + ldreq r0, [sp, #96] + beq .L17599 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r1, r0, asl r3 + mov r0, #0 +.L17600: + movs r3, r1, lsr #24 + ldr r5, [sp, #52] + ldrne r7, [sp, #96] + orr r3, r5, r3 + strne r3, [r7, r0, asl #2] + add r0, r0, #1 + cmp r4, r0 + mov r1, r1, asl #8 + bne .L17600 + ldr r8, [sp, #96] + add r3, r8, ip, asl #2 + sub r0, r3, #16 +.L17599: + ldr r1, [r2, #0] + cmp r1, #0 + beq .L17605 + ands r3, r1, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r0, #12] + mov r3, r1, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r0, #8] + mov r3, r1, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r0, #4] + movs r3, r1, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r0, #0] +.L17605: + add r0, r0, #16 + sub r2, r2, #64 + b .L17586 +.L16589: + cmp lr, #3 + bls .L16627 + cmp r6, #0 + ldr r2, [r8, #0] + ldreq r5, [sp, #96] + beq .L16631 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16632: + movs r0, ip, lsr #24 + beq .L16633 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16633: + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16632 + ldr r7, [sp, #96] + add r5, r7, r6, asl #2 +.L16631: + ldr ip, [sp, #128] + sub r8, r8, #64 + rsb r7, r6, ip + b .L16588 +.L17487: + cmp ip, #3 + bls .L17517 + cmp r0, #0 + ldr r2, [r6, #0] + ldreq r4, [sp, #96] + beq .L17521 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L17522: + movs r3, r2, lsr #24 + ldr ip, [sp, #52] + ldrne lr, [sp, #96] + orr r3, ip, r3 + strne r3, [lr, r1, asl #2] + add r1, r1, #1 + cmp r0, r1 + mov r2, r2, asl #8 + bne .L17522 + ldr r1, [sp, #96] + add r4, r1, r0, asl #2 +.L17521: + ldr r3, [sp, #128] + sub r6, r6, #64 + rsb r5, r0, r3 + b .L17486 +.L16253: + cmp lr, #3 + bls .L16291 + cmp r5, #0 + ldr r2, [r7, #4] + ldreq lr, [sp, #96] + beq .L16295 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, lsr r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16296: + ands r0, ip, #255 + beq .L16297 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16297: + add r4, r4, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16296 + ldr r2, [sp, #96] + add lr, r2, r5, asl #2 +.L16295: + ldr r3, [sp, #128] + add r7, r7, #64 + rsb r6, r5, r3 + b .L16252 +.L17367: + subs r4, ip, #4 + ldr r1, [r0, #0] + ldreq r1, [sp, #96] + beq .L17379 + mov r3, r2, asl #3 + mov r2, r1, lsr r3 + mov r1, #0 +.L17380: + ands r3, r2, #255 + ldr r5, [sp, #52] + ldrne r7, [sp, #96] + orr r3, r5, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r1, r4 + mov r2, r2, lsr #8 + bne .L17380 + ldr r8, [sp, #96] + add r3, r8, ip, asl #2 + sub r1, r3, #16 +.L17379: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L17385 + ands r3, r2, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne r4, [sp, #52] + orrne r3, r4, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne r5, [sp, #52] + orrne r3, r5, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r7, [sp, #52] + orrne r3, r7, r3 + strne r3, [r1, #12] +.L17385: + add r1, r1, #16 + add r0, r0, #64 + b .L17366 +.L17007: + cmp lr, #0 + ldr r2, [r4, #0] + ldreq r6, [sp, #96] + beq .L17017 + mov r3, r3, asl #2 + mov r2, r2, lsr r3 + mov r1, #0 +.L17018: + ldr r5, [sp, #52] + ands r3, r2, #15 + ldrne r8, [sp, #96] + orr r3, r5, r3 + orr r3, r7, r3 + strne r3, [r8, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, lsr #4 + bne .L17018 + ldr ip, [sp, #96] + add r6, ip, lr, asl #2 +.L17017: + ldr r0, [sp, #128] + add r4, r4, #32 + rsb r5, lr, r0 + b .L17006 +.L16049: + cmp r6, #0 + ldr r2, [ip, #0] + ldreq r5, [sp, #96] + beq .L16061 + mov r3, lr, asl #2 + mov r4, r2, asl r3 + ldr r5, [sp, #96] + mov lr, #0 +.L16062: + movs r3, r4, lsr #28 + beq .L16063 + ldr r1, [r5, #0] + orr r2, r7, r3 + mov r3, r1, lsr #16 + orr r0, r2, #768 + mov r3, r3, asl #16 + orr r2, r2, #768 + tst r1, #256 + orr r3, r3, r0 + orr r2, r2, r1, asl #16 + strne r3, [r5, #0] + streq r2, [r5, #0] +.L16063: + add lr, lr, #1 + cmp r6, lr + mov r4, r4, asl #4 + add r5, r5, #4 + bne .L16062 + ldr r4, [sp, #96] + add r5, r4, r6, asl #2 +.L16061: + ldr r8, [sp, #128] + sub ip, ip, #32 + rsb sl, r6, r8 + b .L16048 +.L17137: + cmp lr, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #96] + beq .L17147 + mov r3, r5, asl #2 + mov r4, r2, asl r3 + mov r5, #0 +.L17148: + ldr ip, [sp, #52] + movs r3, r4, lsr #28 + ldrne r1, [sp, #96] + orr r3, ip, r3 + orr r3, r7, r3 + strne r3, [r1, r5, asl #2] + add r5, r5, #1 + cmp lr, r5 + mov r4, r4, asl #4 + bne .L17148 + ldr r2, [sp, #96] + add r1, r2, lr, asl #2 +.L17147: + ldr r3, [sp, #128] + sub r0, r0, #32 + rsb r2, lr, r3 + b .L17136 +.L17267: + cmp lr, #3 + bls .L17297 + cmp r0, #0 + ldr r2, [r6, #4] + ldreq r4, [sp, #96] + beq .L17301 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L17302: + ands r3, r1, #255 + ldr ip, [sp, #52] + ldrne lr, [sp, #96] + orr r3, ip, r3 + strne r3, [lr, r2, asl #2] + add r2, r2, #1 + cmp r0, r2 + mov r1, r1, lsr #8 + bne .L17302 + ldr r1, [sp, #96] + add r4, r1, r0, asl #2 +.L17301: + ldr r3, [sp, #128] + add r6, r6, #64 + rsb r5, r0, r3 + b .L17266 +.L17797: + mov r6, #0 + b .L15820 +.L17800: + mov r6, #0 + b .L16948 +.L17799: + mov ip, #0 + b .L15780 +.L17794: + mov ip, fp + b .L17737 +.L17297: + subs ip, r0, #4 + ldr r2, [r6, #0] + ldreq r1, [sp, #96] + beq .L17309 + mov r3, lr, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L17310: + ands r3, r1, #255 + ldr r4, [sp, #52] + ldrne r5, [sp, #96] + orr r3, r4, r3 + strne r3, [r5, r2, asl #2] + add r2, r2, #1 + cmp r2, ip + mov r1, r1, lsr #8 + bne .L17310 + ldr r7, [sp, #96] + add r3, r7, r0, asl #2 + sub r1, r3, #16 +.L17309: + ldr r2, [r6, #4] + cmp r2, #0 + beq .L17315 + ands r3, r2, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #0] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r1, #4] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + strne r3, [r1, #8] + movs r3, r2, lsr #24 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r1, #12] +.L17315: + add r4, r1, #16 + b .L17301 +.L16291: + subs r6, r5, #4 + ldr r2, [r7, #0] + ldreq r2, [sp, #96] + beq .L16305 + mov r3, lr, asl #3 + mov ip, r2, lsr r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16306: + ands r0, ip, #255 + beq .L16307 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16307: + add r4, r4, #1 + cmp r6, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16306 + ldr r1, [sp, #96] + add r3, r1, r5, asl #2 + sub r2, r3, #16 +.L16305: + ldr r1, [r7, #4] + cmp r1, #0 + beq .L16313 + ands r0, r1, #255 + beq .L16315 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #0] + streq r3, [r2, #0] +.L16315: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L16319 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L16319: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L16323 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L16323: + movs r1, r1, lsr #24 + beq .L16313 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #12] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #12] +.L16313: + add lr, r2, #16 + b .L16295 +.L17517: + subs lr, r0, #4 + ldr r2, [r6, #4] + ldreq r1, [sp, #96] + beq .L17529 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L17530: + movs r3, r2, lsr #24 + ldr r4, [sp, #52] + ldrne r5, [sp, #96] + orr r3, r4, r3 + strne r3, [r5, r1, asl #2] + add r1, r1, #1 + cmp lr, r1 + mov r2, r2, asl #8 + bne .L17530 + ldr r7, [sp, #96] + add r3, r7, r0, asl #2 + sub r1, r3, #16 +.L17529: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L17535 + ands r3, r2, #255 + ldrne r8, [sp, #52] + orrne r3, r8, r3 + strne r3, [r1, #12] + mov r3, r2, lsr #8 + ands r3, r3, #255 + ldrne ip, [sp, #52] + orrne r3, ip, r3 + strne r3, [r1, #8] + mov r3, r2, lsr #16 + ands r3, r3, #255 + ldrne lr, [sp, #52] + orrne r3, lr, r3 + strne r3, [r1, #4] + movs r3, r2, lsr #24 + ldrne r2, [sp, #52] + orrne r3, r2, r3 + strne r3, [r1, #0] +.L17535: + add r4, r1, #16 + b .L17521 +.L16627: + subs r5, r6, #4 + ldr r2, [r8, #4] + ldreq r2, [sp, #96] + beq .L16641 + mov r3, lr, asl #3 + sub r3, r3, #32 + mov ip, r2, asl r3 + ldr lr, [sp, #96] + mov r4, #0 +.L16642: + movs r0, ip, lsr #24 + beq .L16643 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16643: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16642 + ldr r4, [sp, #96] + add r3, r4, r6, asl #2 + sub r2, r3, #16 +.L16641: + ldr r1, [r8, #0] + cmp r1, #0 + beq .L16649 + ands r0, r1, #255 + beq .L16651 + ldr r3, [r2, #12] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #12] + streq r3, [r2, #12] +.L16651: + mov r3, r1, lsr #8 + ands r0, r3, #255 + beq .L16655 + ldr r3, [r2, #8] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #8] + streq r3, [r2, #8] +.L16655: + mov r3, r1, lsr #16 + ands r0, r3, #255 + beq .L16659 + ldr r3, [r2, #4] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orreq r3, r0, r3, asl #16 + orrne r3, r0, r3 + orreq r3, r3, #768 + strne r3, [r2, #4] + streq r3, [r2, #4] +.L16659: + movs r1, r1, lsr #24 + beq .L16649 + ldr r3, [r2, #0] + tst r3, #256 + movne r3, r3, lsr #16 + movne r3, r3, asl #16 + orrne r3, r3, #768 + orrne r3, r1, r3 + strne r3, [r2, #0] + orreq r3, r1, r3, asl #16 + orreq r3, r3, #768 + streq r3, [r2, #0] +.L16649: + add r5, r2, #16 + b .L16631 +.L17490: + ldr r7, [sp, #128] + mov r3, ip, asl #3 + ldr r1, [r6, #4] + add r2, r7, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L17497 + cmp r7, #0 + movne r2, #0 + beq .L15754 +.L17513: + movs r3, r1, lsr #24 + ldr r5, [sp, #52] + ldrne r7, [sp, #96] + orr r3, r5, r3 + ldr r8, [sp, #128] + strne r3, [r7, r2, asl #2] + add r2, r2, #1 + cmp r8, r2 + mov r1, r1, asl #8 + bne .L17513 + b .L15754 +.L16592: + ldr ip, [sp, #128] + mov r3, lr, asl #3 + add r2, ip, lr + ldr r1, [r8, #4] + sub r3, r3, #32 + cmp r2, #4 + mov ip, r1, asl r3 + bhi .L16601 + ldr lr, [sp, #128] + cmp lr, #0 + ldrne lr, [sp, #96] + movne r4, #0 + beq .L15754 +.L16621: + movs r0, ip, lsr #24 + beq .L16622 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16622: + ldr r2, [sp, #128] + add r4, r4, #1 + cmp r2, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16621 + b .L15754 +.L17270: + ldr r4, [sp, #128] + ldr r3, [r6, #0] + add r2, r4, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov r2, r3, lsr r1 + bhi .L17277 + cmp r4, #0 + movne r1, #0 + beq .L15754 +.L17293: + ands r3, r2, #255 + ldr r5, [sp, #52] + ldrne r7, [sp, #96] + orr r3, r5, r3 + ldr r8, [sp, #128] + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r8, r1 + mov r2, r2, lsr #8 + bne .L17293 + b .L15754 +.L16256: + ldr r1, [sp, #128] + ldr r3, [r7, #0] + add r2, r1, lr + cmp r2, #4 + mov r1, lr, asl #3 + mov ip, r3, lsr r1 + bhi .L16265 + ldr r2, [sp, #128] + cmp r2, #0 + ldrne lr, [sp, #96] + movne r4, #0 + beq .L15754 +.L16285: + ands r0, ip, #255 + beq .L16286 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16286: + ldr r0, [sp, #128] + add r4, r4, #1 + cmp r0, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16285 + b .L15754 +.L16265: + rsbs r4, lr, #4 + ldreq lr, [sp, #96] + beq .L16270 + ldr lr, [sp, #96] + mov r5, #0 +.L16271: + ands r0, ip, #255 + beq .L16272 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16272: + add r5, r5, #1 + cmp r5, r4 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16271 + ldr r3, [sp, #96] + add lr, r3, r4, asl #2 +.L16270: + ldr r8, [sp, #128] + ldr ip, [r7, #4] + subs r5, r8, r4 + beq .L15754 + mov r4, #0 +.L16279: + ands r0, ip, #255 + beq .L16280 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16280: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, lsr #8 + add lr, lr, #4 + bne .L16279 + b .L15754 +.L17277: + rsbs r0, lr, #4 + ldreq ip, [sp, #96] + beq .L17282 + mov r1, #0 +.L17283: + ands r3, r2, #255 + ldr r5, [sp, #52] + ldrne r7, [sp, #96] + orr r3, r5, r3 + strne r3, [r7, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L17283 + ldr r8, [sp, #96] + add ip, r8, r0, asl #2 +.L17282: + ldr lr, [sp, #128] + ldr r2, [r6, #4] + subs r0, lr, r0 + beq .L15754 + mov r1, #0 +.L17289: + ldr r4, [sp, #52] + ands r3, r2, #255 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, lsr #8 + bne .L17289 + b .L15754 +.L16601: + rsbs r4, lr, #4 + ldreq lr, [sp, #96] + beq .L16606 + ldr lr, [sp, #96] + mov r5, #0 +.L16607: + movs r0, ip, lsr #24 + beq .L16608 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16608: + add r5, r5, #1 + cmp r5, r4 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16607 + ldr r0, [sp, #96] + add lr, r0, r4, asl #2 +.L16606: + ldr r1, [sp, #128] + ldr ip, [r8, #0] + subs r5, r1, r4 + beq .L15754 + mov r4, #0 +.L16615: + movs r0, ip, lsr #24 + beq .L16616 + ldr r2, [lr, #0] + orr r1, r0, #768 + mov r3, r2, lsr #16 + orr r0, r0, #768 + mov r3, r3, asl #16 + tst r2, #256 + orr r3, r3, r1 + orr r0, r0, r2, asl #16 + strne r3, [lr, #0] + streq r0, [lr, #0] +.L16616: + add r4, r4, #1 + cmp r4, r5 + mov ip, ip, asl #8 + add lr, lr, #4 + bne .L16615 + b .L15754 +.L17497: + rsbs r0, ip, #4 + ldreq ip, [sp, #96] + beq .L17502 + mov r2, #0 +.L17503: + movs r3, r1, lsr #24 + ldr r8, [sp, #52] + ldrne ip, [sp, #96] + orr r3, r8, r3 + strne r3, [ip, r2, asl #2] + add r2, r2, #1 + cmp r2, r0 + mov r1, r1, asl #8 + bne .L17503 + ldr lr, [sp, #96] + add ip, lr, r0, asl #2 +.L17502: + ldr r1, [sp, #128] + ldr r2, [r6, #0] + subs r0, r1, r0 + beq .L15754 + mov r1, #0 +.L17509: + ldr r4, [sp, #52] + movs r3, r2, lsr #24 + orr r3, r4, r3 + strne r3, [ip, r1, asl #2] + add r1, r1, #1 + cmp r1, r0 + mov r2, r2, asl #8 + bne .L17509 + b .L15754 + .size render_scanline_obj_partial_alpha_2D, .-render_scanline_obj_partial_alpha_2D + .align 2 + .global order_obj + .type order_obj, %function +order_obj: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r9, .L17848 + mov sl, r0 + mov ip, #0 +.L17806: + add r3, ip, ip, asl #2 + add r2, r9, r3, asl #7 + mov r3, #0 +.L17807: + add r3, r3, #1 + mov r1, #0 + cmp r3, #160 + str r1, [r2], #4 + bne .L17807 + add ip, ip, #1 + cmp ip, #5 + bne .L17806 + ldr fp, .L17848+4 + mov r3, fp + add r2, fp, #640 +.L17810: + str r1, [r3], #4 + cmp r3, r2 + bne .L17810 + ldr r5, .L17848+8 + mov r6, #127 +.L17812: + ldrh r2, [r5, #8] + ldrh r7, [r5, #12] + and r1, r2, #49152 + and r3, r2, #768 + cmp r3, #512 + cmpne r1, #49152 + beq .L17813 + mov r3, r2, lsr #10 + and r0, r3, #3 + cmp r0, #3 + beq .L17813 + cmp sl, #2 + bls .L17816 + mov r3, r7, asl #22 + mov r3, r3, lsr #22 + cmp r3, #512 + bcc .L17813 +.L17816: + ldrh r4, [r5, #10] + and ip, r2, #255 + mov r3, r4, lsr #14 + orr r3, r3, r1, lsr #12 + ldr r1, .L17848+12 + cmp ip, #160 + subgt ip, ip, #256 + ldr r1, [r1, r3, asl #2] + tst r2, #512 + ldr r2, .L17848+16 + movne r1, r1, asl #1 + ldr r2, [r2, r3, asl #2] + add lr, ip, r1 + movne r2, r2, asl #1 + cmp lr, #0 + movle r3, #0 + movgt r3, #1 + cmp ip, #159 + movgt r3, #0 + cmp r3, #0 + beq .L17813 + mov r3, r4, asl #23 + mov r3, r3, asr #23 + add r2, r2, r3 + cmp r2, #0 + movle r1, #0 + movgt r1, #1 + cmp r3, #239 + movgt r1, #0 + cmp r1, #0 + beq .L17813 + cmp ip, #0 + movlt ip, #0 + cmp lr, #160 + movge lr, #160 + mov r3, r7, lsr #10 + cmp r0, #1 + and r3, r3, #3 + beq .L17847 + cmp r0, #2 + moveq r3, #4 + cmp lr, ip + ble .L17813 + add r3, r3, r3, asl #2 + ldr r2, .L17848+20 + rsb r1, ip, lr + add r3, ip, r3, asl #5 + mov r0, ip + add r1, ip, r1 + add lr, r2, r3, asl #7 + and r4, r6, #255 + add ip, r9, r3, asl #2 +.L17833: + ldr r2, [ip, #0] + add r0, r0, #1 + add r3, r2, #1 + cmp r0, r1 + strb r4, [lr, r2] + str r3, [ip], #4 + add lr, lr, #128 + bne .L17833 +.L17813: + sub r6, r6, #1 + cmn r6, #1 + sub r5, r5, #8 + bne .L17812 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L17847: + cmp lr, ip + ble .L17813 + add r3, r3, r3, asl #2 + ldr r2, .L17848+20 + add r3, ip, r3, asl #5 + rsb r1, ip, lr + mov r4, ip + add r8, ip, r1 + add r0, r2, r3, asl #7 + and r7, r6, #255 + add lr, r9, r3, asl #2 + add ip, fp, ip, asl #2 +.L17829: + ldr r3, [lr, #0] + ldr r2, [ip, #0] + add r4, r4, #1 + add r1, r3, #1 + add r2, r2, #1 + cmp r4, r8 + strb r7, [r0, r3] + str r1, [lr], #4 + str r2, [ip], #4 + add r0, r0, #128 + bne .L17829 + sub r6, r6, #1 + cmn r6, #1 + sub r5, r5, #8 + bne .L17812 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L17849: + .align 2 +.L17848: + .word obj_priority_count + .word obj_alpha_count + .word oam_ram+1008 + .word obj_height_table + .word obj_width_table + .word obj_priority_list + .size order_obj, .-order_obj + .align 2 + .global order_layers + .type order_layers, %function +order_layers: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} + ldr r6, .L17989 + ldr r3, .L17989+4 + ldrh r2, [r6, #6] + ldr sl, .L17989+8 + add r4, r3, r2, asl #2 + and r3, r0, #8 + mov r1, #0 + cmp r3, #0 + and ip, r0, #1 + and r7, r0, #16 + and r2, r0, #4 + ldr r8, .L17989+12 + mov r5, r1 + mov lr, #3 + and r0, r0, #2 + str r1, [sl, #0] + bne .L17967 + cmp ip, #0 + beq .L17979 + cmp r0, #0 + bne .L17985 + cmp r2, #0 + bne .L17988 +.L17851: + ldrh r3, [r6, #8] + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17855 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17855: + subs lr, lr, #1 + bcs .L17851 +.L17869: + str r5, [sl, #0] + ldmfd sp!, {r4, r5, r6, r7, r8, sl, pc} +.L17967: + cmp ip, #0 + beq .L17969 + cmp r0, #0 + bne .L17975 + cmp r2, #0 + bne .L17978 +.L17884: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #8] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17875 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17875: + subs lr, lr, #1 + bcc .L17869 + b .L17884 +.L17969: + cmp r0, #0 + bne .L17971 + cmp r2, #0 + bne .L17974 +.L17890: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17883 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17883: + subs lr, lr, #1 + bcc .L17869 + b .L17890 +.L17979: + cmp r0, #0 + bne .L17981 + cmp r2, #0 + bne .L17984 +.L17935: + ldr r3, [r4, #1920] + sub r4, r4, #640 + cmp r3, #0 + beq .L17930 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17930: + subs lr, lr, #1 + bcc .L17869 + b .L17935 +.L17985: + cmp r2, #0 + bne .L17987 +.L17958: + ldrh r3, [r6, #10] + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldrh r3, [r6, #8] + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17951 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17951: + subs lr, lr, #1 + bcc .L17869 + b .L17958 +.L17987: + ldrh r3, [r6, #12] + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldrh r3, [r6, #8] + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + beq .L17957 + cmp r7, #0 + orrne r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17957: + sub lr, lr, #1 + cmn lr, #1 + sub r4, r4, #640 + bne .L17987 + b .L17869 +.L17975: + cmp r2, #0 + bne .L17977 +.L17917: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldrh r3, [r6, #8] + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + beq .L17909 + cmp r7, #0 + orrne r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17909: + sub lr, lr, #1 + cmn lr, #1 + sub r4, r4, #640 + bne .L17917 + b .L17869 +.L17977: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #12] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldrh r3, [r6, #8] + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + beq .L17916 + cmp r7, #0 + orrne r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17916: + sub lr, lr, #1 + cmn lr, #1 + sub r4, r4, #640 + bne .L17977 + b .L17869 +.L17978: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #12] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #8] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + beq .L17923 + cmp r7, #0 + orrne r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17923: + sub lr, lr, #1 + cmn lr, #1 + sub r4, r4, #640 + bne .L17978 + b .L17869 +.L17971: + cmp r2, #0 + bne .L17973 +.L17897: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldr r3, [r4, #1920] + sub r4, r4, #640 + cmp r3, #0 + beq .L17889 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17889: + subs lr, lr, #1 + bcc .L17869 + b .L17897 +.L17973: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #12] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldr r3, [r4, #1920] + cmp r3, #0 + beq .L17896 + cmp r7, #0 + orrne r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17896: + sub lr, lr, #1 + cmn lr, #1 + sub r4, r4, #640 + bne .L17973 + b .L17869 +.L17974: + ldrh r3, [r6, #14] + and r3, r3, #3 + cmp r3, lr + moveq r3, #3 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #12] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17902 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17902: + subs lr, lr, #1 + bcc .L17869 + b .L17974 +.L17981: + cmp r2, #0 + bne .L17983 +.L17941: + ldrh r3, [r6, #10] + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldr r3, [r4, #1920] + sub r4, r4, #640 + cmp r3, #0 + beq .L17934 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17934: + subs lr, lr, #1 + bcc .L17869 + b .L17941 +.L17983: + ldrh r3, [r6, #12] + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #10] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #1 + streq r3, [r8, r5, asl #2] + addeq r5, r5, r3 + ldr r3, [r4, #1920] + sub r4, r4, #640 + cmp r3, #0 + beq .L17940 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17940: + subs lr, lr, #1 + bcc .L17869 + b .L17983 +.L17984: + ldrh r3, [r6, #12] + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17945 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17945: + subs lr, lr, #1 + bcc .L17869 + b .L17984 +.L17988: + ldrh r3, [r6, #12] + and r3, r3, #3 + cmp r3, lr + moveq r3, #2 + streq r3, [r8, r5, asl #2] + ldrh r3, [r6, #8] + addeq r5, r5, #1 + and r3, r3, #3 + cmp r3, lr + moveq r3, #0 + streq r3, [r8, r5, asl #2] + ldr r3, [r4, #1920] + addeq r5, r5, #1 + cmp r3, #0 + sub r4, r4, #640 + beq .L17963 + cmp r7, #0 + orr r3, lr, #4 + strne r3, [r8, r5, asl #2] + addne r5, r5, #1 +.L17963: + subs lr, lr, #1 + bcc .L17869 + b .L17988 +.L17990: + .align 2 +.L17989: + .word io_registers + .word obj_priority_count + .word layer_count + .word layer_order + .size order_layers, .-order_layers + .align 2 + .global fill_line_normal + .type fill_line_normal, %function +fill_line_normal: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + str lr, [sp, #-4]! + mov r0, r0, asl #16 + mov lr, r3 + cmp r2, r3 + ldr r3, .L17997 + mov r0, r0, lsr #15 + ldrh ip, [r0, r3] + ldrcs pc, [sp], #4 + rsb r3, r2, lr + add r1, r1, r2, asl #1 + mov r0, #0 +.L17994: + add r0, r0, #1 + cmp r0, r3 + strh ip, [r1], #2 @ movhi + bne .L17994 + ldr pc, [sp], #4 +.L17998: + .align 2 +.L17997: + .word palette_ram_converted + .size fill_line_normal, .-fill_line_normal + .align 2 + .global fill_line_alpha + .type fill_line_alpha, %function +fill_line_alpha: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + mov r0, r0, asl #16 + cmp r2, r3 + @ lr needed for prologue + mov r0, r0, lsr #16 + bxcs lr + rsb r3, r2, r3 + add r1, r1, r2, asl #2 + mov ip, #0 +.L18002: + add ip, ip, #1 + cmp ip, r3 + str r0, [r1], #4 + bne .L18002 + bx lr + .size fill_line_alpha, .-fill_line_alpha + .align 2 + .global fill_line_color16 + .type fill_line_color16, %function +fill_line_color16: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + mov r0, r0, asl #16 + cmp r2, r3 + @ lr needed for prologue + mov r0, r0, lsr #16 + bxcs lr + rsb r3, r2, r3 + add r1, r1, r2, asl #1 + mov ip, #0 +.L18008: + add ip, ip, #1 + cmp ip, r3 + strh r0, [r1], #2 @ movhi + bne .L18008 + bx lr + .size fill_line_color16, .-fill_line_color16 + .align 2 + .global fill_line_color32 + .type fill_line_color32, %function +fill_line_color32: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + mov r0, r0, asl #16 + cmp r2, r3 + @ lr needed for prologue + mov r0, r0, lsr #16 + bxcs lr + rsb r3, r2, r3 + add r1, r1, r2, asl #2 + mov ip, #0 +.L18014: + add ip, ip, #1 + cmp ip, r3 + str r0, [r1], #4 + bne .L18014 + bx lr + .size fill_line_color32, .-fill_line_color32 + .align 2 + .global expand_blend + .type expand_blend, %function + +expand_blend: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + mov r6, r0 # r6 = screen_src_ptr + ldr r0, .L18042 # r0 = io_registers + mov lr, r1 # lr = screen_dest_ptr + ldrh ip, [r0, #82] # ip = REG_BLDALPHA + sub sp, sp, #4 # make room on stack for 1 word + mov r1, ip, lsr #8 # r1 = REG_BLDALPHA >> 8 + and r1, r1, #31 # r1 = (REG_BLDALPHA >> 8) & 0x1F = blend_b + and ip, ip, #31 # ip = REG_BLDALPHA & 0x1F = blend_a + cmp ip, #16 # if(blend_a > 16) + movcs ip, #16 # blend_a = 16 + cmp r1, #16 # fp = blend_b + movcc fp, r1 # if(blend_b > 16) + movcs fp, #16 # blend_b = 16 + add r0, fp, ip # r0 = blend_a + blend_b + cmp r0, #16 # if((blend_a + blend_b) > 16) + str ip, [sp, #0] # save blend_a to stack + bls .L18018 # goto blend w/o saturation + + subs r8, r3, r2 # r8 = end - start + beq .L18040 # if((end - start) == 0) we're already done + + ldr r7, .L18042+4 # r7 = palette_ram_converted + ldr sl, .L18042+8 # sl = 0x4000200 + add r4, r6, r2, asl #2 # r4 = screen_src_ptr + (start * 4) + add r5, lr, r2, asl #1 # r5 = screen_dest_ptr + (start * 2) + mov r6, #0 # r6 = 0 + b .L18022 + +.L18023: + mov r3, r0, asl #23 + mov r3, r3, lsr #23 + mov r3, r3, asl #1 + ldrh r3, [r3, r7] + add r6, r6, #1 + cmp r8, r6 + strh r3, [r5, #0] @ movhi + beq .L18040 + +.L18041: # next_iteration + add r4, r4, #4 # screen_src_ptr++ + add r5, r5, #2 # screen_dest_ptr++ + +.L18022: # blend w/o saturation + ldr r0, [r4, #0] # r0 = *screen_src_ptr = pixel_source + ldr r3, .L18042+8 # r3 = 0x4000200 + and r3, r0, r3 # r3 = (pixel_source & 0x400200) + cmp r3, sl # if(r3 == 0x4000200) + bne .L18023 # if not, don't perform blending + ldr r3, .L18042+12 # r3 = 0x3FE + mov r2, r0, lsr #15 # r2 = pixel_source >> 15 + and r3, r2, r3 # r3 = (pixel_source >> 15) & 0x3FE = low_color_i + ldrh r1, [r3, r7] # r1 = palette_ram_converted[low_color_i] = low_color + mov r0, r0, asl #23 # r0 = r0 << 23 + ldr ip, .L18042+16 # ip = 0x7EF81F + orr r1, r1, r1, asl #16 # r1 = (low_color << 16) | low_color = low_split + mov r0, r0, lsr #23 # r0 = pixel_source & 0x1FF + and ip, r1, ip # ip = low_split & 0x7EF81F = pixel_bottom + mov r0, r0, asl #1 # r0 = (pixel_source & 0x1FF) << 1 = high_color_i + ldrh r2, [r0, r7] # r2 = palette_ram_converted[high_color_i] = high_color + mul lr, fp, ip # lr = pixel_bottom * blend_b + ldr r3, .L18042+16 # r3 = 0x7EF81F + orr r2, r2, r2, asl #16 # r2 = (high_color << 16) | high_color = high_split + ldr r1, [sp, #0] # r1 = blend_a + and r3, r2, r3 # r3 = high_split & 0x7EF81F = pixel_top + mla r1, r3, r1, lr # r1 = (pixel_top * blend_a) + (pixel_bottom * blend_b) + ldr r2, .L18042+20 # r2 = 0x8010020 + mov r1, r1, lsr #4 # r1 = ((pixel_top * blend_a) + (pixel_bottom * blend_b)) >> 4 + and r2, r1, r2 # r2 = test any saturation on result + cmp r2, #0 # if(!saturation) + beq .L18025 # goto finish_iteration + tst r1, #134217728 + orrne r1, r1, #132120576 + tst r1, #65536 + orrne r1, r1, #63488 + tst r1, #32 + orrne r1, r1, #31 + +.L18025: # finish_iteration + ldr r3, .L18042+16 # r3 = 0x7EF81F + add r6, r6, #1 # i++ + and r3, r1, r3 # r3 = pixel_result_dilate & 0x7EF81F + orr r3, r3, r3, lsr #16 # r3 = (pixel_result_dilate >> 16) | pixel_result_dilate + cmp r8, r6 # *screen_dest_ptr = pixel_result + strh r3, [r5, #0] @ movhi # if(i != end) + bne .L18041 # goto next_iteration +.L18040: + add sp, sp, #4 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + +.L18018: # blend w/o saturation + subs r9, r3, r2 + beq .L18040 + ldr sl, .L18042+4 + add r4, lr, r2, asl #1 + mov r7, #0 + add lr, r6, r2, asl #2 + b .L18035 +.L18036: + ldrh r3, [r3, sl] + strh r3, [r4, #0] @ movhi +.L18038: + add r7, r7, #1 + cmp r9, r7 + add lr, lr, #4 + add r4, r4, #2 + beq .L18040 + +.L18035: + ldr r1, [lr, #0] + ldr ip, .L18042+12 + mov r3, r1, asl #23 + ldr r0, .L18042+8 + mov r2, r1, lsr #15 + mov r3, r3, lsr #23 + and r0, r1, r0 + and ip, r2, ip + mov r2, r3, asl #1 + mov r3, r1, asl #23 + ldr r1, .L18042+8 + ldr r6, .L18042+16 + mov r3, r3, lsr #23 + cmp r0, r1 + mov r8, r6 + mov r5, r6 + mov r3, r3, asl #1 + bne .L18036 + ldrh r3, [ip, sl] + ldrh r2, [r2, sl] + orr r3, r3, r3, asl #16 + and r6, r3, r6 + mul r1, fp, r6 + orr r2, r2, r2, asl #16 + ldr r3, [sp, #0] + and r8, r2, r8 + mla r3, r8, r3, r1 + mov r3, r3, lsr #4 + and r5, r3, r5 + orr r2, r5, r5, lsr #16 + strh r2, [r4, #0] @ movhi + b .L18038 + +.L18043: + .align 2 + +.L18042: + .word io_registers + .word palette_ram_converted + .word 67109376 + .word 1022 + .word 132184095 + .word 134283296 + .size expand_blend, .-expand_blend + .align 2 + .global expand_darken + .type expand_darken, %function +expand_darken: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L18053 + stmfd sp!, {r4, r5, r6, r7, r8, lr} + mov lr, r2 + ldrh r2, [ip, #84] + and r2, r2, #31 + rsb r2, r2, #16 + cmp r2, #0 + movge r8, r2 + movlt r8, #0 + subs r6, r3, lr + ldmeqfd sp!, {r4, r5, r6, r7, r8, pc} + mov r3, lr, asl #1 + ldr r7, .L18053+4 + add ip, r3, r1 + add r0, r3, r0 + mov r5, #0 +.L18047: + ldrh r3, [r0, #0] + ldr r4, .L18053+8 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, r7] + mov lr, r4 + orrne r3, r3, r3, asl #16 + andne r4, r3, r4 + mulne r2, r8, r4 + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + movne r2, r2, lsr #4 + andne lr, r2, lr + ldreqh r1, [r1, r7] + orrne r3, lr, lr, lsr #16 + add r5, r5, #1 + strneh r3, [ip, #0] @ movhi + streqh r1, [ip, #0] @ movhi + cmp r6, r5 + add r0, r0, #2 + add ip, ip, #2 + bne .L18047 + ldmfd sp!, {r4, r5, r6, r7, r8, pc} +.L18054: + .align 2 +.L18053: + .word io_registers + .word palette_ram_converted + .word 132184095 + .size expand_darken, .-expand_darken + .align 2 + .global expand_brighten + .type expand_brighten, %function +expand_brighten: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} + mov lr, r2 + ldr r2, .L18064 + ldr r7, .L18064+4 + ldrh ip, [r2, #84] + and ip, ip, #31 + cmp ip, #16 + movcs ip, #16 + rsb r2, ip, ip, asl #6 + add r2, ip, r2, asl #5 + rsb r2, r2, r2, asl #16 + mov r2, r2, lsr #4 + subs r6, r3, lr + and r7, r2, r7 + rsb r8, ip, #16 + ldmeqfd sp!, {r4, r5, r6, r7, r8, sl, pc} + mov r3, lr, asl #1 + ldr sl, .L18064+8 + add ip, r3, r1 + add r0, r3, r0 + mov r5, #0 +.L18058: + ldrh r3, [r0, #0] + ldr r4, .L18064+4 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, sl] + mov lr, r4 + orrne r3, r3, r3, asl #16 + andne r4, r3, r4 + mulne r2, r4, r8 + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + addne r2, r7, r2, lsr #4 + andne lr, r2, lr + ldreqh r1, [r1, sl] + orrne r3, lr, lr, lsr #16 + add r5, r5, #1 + strneh r3, [ip, #0] @ movhi + streqh r1, [ip, #0] @ movhi + cmp r6, r5 + add r0, r0, #2 + add ip, ip, #2 + bne .L18058 + ldmfd sp!, {r4, r5, r6, r7, r8, sl, pc} +.L18065: + .align 2 +.L18064: + .word io_registers + .word 132184095 + .word palette_ram_converted + .size expand_brighten, .-expand_brighten + .align 2 + .global expand_darken_partial_alpha + .type expand_darken_partial_alpha, %function +expand_darken_partial_alpha: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r4, .L18099 + mov r6, r0 + ldrh r0, [r4, #82] + ldrh lr, [r4, #84] + mov ip, r0, lsr #8 + and ip, ip, #31 + and r0, r0, #31 + sub sp, sp, #16 + cmp r0, #16 + movcs r0, #16 + cmp ip, #16 + movcs ip, #16 + and lr, lr, #31 + str r0, [sp, #4] + rsb lr, lr, #16 + add r0, ip, r0 + cmp lr, #0 + movlt lr, #0 + cmp r0, #16 + str ip, [sp, #8] + str lr, [sp, #0] + bls .L18067 + subs r8, r3, r2 + beq .L18093 + ldr r7, .L18099+4 + add r4, r6, r2, asl #2 + add r5, r1, r2, asl #1 + mov r6, #0 + b .L18071 +.L18095: + ldr r3, .L18099+8 + ldr r2, .L18099+8 + and r3, r0, r3 + cmp r3, r2 + beq .L18094 + mov r3, r0, asl #23 + mov r3, r3, lsr #23 + mov r3, r3, asl #1 + ldrh r2, [r3, r7] + ldr r1, .L18099+12 + orr r2, r2, r2, asl #16 + ldr r0, [sp, #0] + and r1, r2, r1 + mul r0, r1, r0 + ldr r3, .L18099+12 + mov r0, r0, lsr #4 + and r3, r0, r3 + orr r3, r3, r3, lsr #16 + strh r3, [r5, #0] @ movhi +.L18083: + add r6, r6, #1 + cmp r8, r6 + beq .L18093 +.L18096: + add r4, r4, #4 + add r5, r5, #2 +.L18071: + ldr r0, [r4, #0] + tst r0, #512 + bne .L18095 + mov r3, r0, asl #23 + mov r3, r3, lsr #23 + mov r3, r3, asl #1 + ldrh r3, [r3, r7] + add r6, r6, #1 + cmp r8, r6 + strh r3, [r5, #0] @ movhi + bne .L18096 +.L18093: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18067: + subs r3, r3, r2 + str r3, [sp, #12] + beq .L18093 + ldr fp, .L18099+4 + add r4, r1, r2, asl #1 + add r0, r6, r2, asl #2 + mov sl, #0 + b .L18086 +.L18098: + ldr r5, .L18099+16 + mov r3, r1, lsr #15 + and r5, r3, r5 + mov r3, r1, asl #23 + mov r3, r3, lsr #23 + mov r7, r3, asl #1 + ldr r3, .L18099+8 + ldr r9, .L18099+12 + mov r2, r1, asl #23 + mov r2, r2, lsr #23 + cmp lr, r3 + mov r2, r2, asl #1 + mov r8, r9 + mov ip, r9 + mov r6, r9 + beq .L18097 + ldrh r3, [r2, fp] + ldr r2, [sp, #0] + orr r3, r3, r3, asl #16 + and ip, r3, r9 + mul r2, ip, r2 + mov r2, r2, lsr #4 + and r1, r2, r9 + orr r3, r1, r1, lsr #16 + strh r3, [r4, #0] @ movhi +.L18091: + ldr ip, [sp, #12] + add sl, sl, #1 + cmp ip, sl + add r0, r0, #4 + add r4, r4, #2 + beq .L18093 +.L18086: + ldr r1, [r0, #0] + ldr lr, .L18099+8 + mov r3, r1, asl #23 + mov r3, r3, lsr #23 + tst r1, #512 + and lr, r1, lr + mov r3, r3, asl #1 + bne .L18098 + ldrh r3, [r3, fp] + strh r3, [r4, #0] @ movhi + b .L18091 +.L18097: + ldrh r3, [r5, fp] + ldr r1, [sp, #8] + orr r3, r3, r3, asl #16 + and r9, r3, r9 + ldrh r2, [r7, fp] + mul r1, r9, r1 + orr r2, r2, r2, asl #16 + ldr r3, [sp, #4] + and r8, r2, r8 + mla r3, r8, r3, r1 + mov r3, r3, lsr #4 + and r6, r3, ip + orr r2, r6, r6, lsr #16 + strh r2, [r4, #0] @ movhi + b .L18091 +.L18094: + ldr r3, .L18099+16 + mov r2, r0, lsr #15 + and r3, r2, r3 + ldrh r1, [r3, r7] + mov r0, r0, asl #23 + ldr ip, .L18099+12 + orr r1, r1, r1, asl #16 + mov r0, r0, lsr #23 + ldr lr, [sp, #8] + and ip, r1, ip + mov r0, r0, asl #1 + ldrh r2, [r0, r7] + mul lr, ip, lr + ldr r3, .L18099+12 + orr r2, r2, r2, asl #16 + ldr r1, [sp, #4] + and r3, r2, r3 + mla r1, r3, r1, lr + ldr r2, .L18099+20 + mov r1, r1, lsr #4 + and r2, r1, r2 + cmp r2, #0 + beq .L18076 + tst r1, #134217728 + orrne r1, r1, #132120576 + tst r1, #65536 + orrne r1, r1, #63488 + tst r1, #32 + orrne r1, r1, #31 +.L18076: + ldr r3, .L18099+12 + and r3, r1, r3 + orr r3, r3, r3, lsr #16 + strh r3, [r5, #0] @ movhi + b .L18083 +.L18100: + .align 2 +.L18099: + .word io_registers + .word palette_ram_converted + .word 67109376 + .word 132184095 + .word 1022 + .word 134283296 + .size expand_darken_partial_alpha, .-expand_darken_partial_alpha + .align 2 + .global expand_brighten_partial_alpha + .type expand_brighten_partial_alpha, %function +expand_brighten_partial_alpha: + @ args = 0, pretend = 0, frame = 20 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr ip, .L18134 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldrh r5, [ip, #84] + ldrh r4, [ip, #82] + and r5, r5, #31 + cmp r5, #16 + movge r5, #16 + mov lr, r4, lsr #8 + rsb ip, r5, r5, asl #6 + add ip, r5, ip, asl #5 + and lr, lr, #31 + and r4, r4, #31 + sub sp, sp, #20 + cmp r4, #16 + movcs r4, #16 + cmp lr, #16 + movcs lr, #16 + rsb ip, ip, ip, asl #16 + ldr r6, .L18134+4 + str lr, [sp, #12] + mov ip, ip, asr #4 + add lr, lr, r4 + and r6, ip, r6 + rsb r5, r5, #16 + cmp lr, #16 + str r4, [sp, #8] + str r6, [sp, #0] + str r5, [sp, #4] + bls .L18102 + subs r8, r3, r2 + beq .L18128 + ldr r7, .L18134+8 + add r4, r1, r2, asl #1 + add r5, r0, r2, asl #2 + mov r6, #0 + b .L18106 +.L18130: + ldr r3, .L18134+12 + ldr r2, .L18134+12 + and r3, r0, r3 + cmp r3, r2 + beq .L18129 + mov r3, r0, asl #23 + mov r3, r3, lsr #23 + mov r3, r3, asl #1 + ldrh r2, [r3, r7] + ldr r1, .L18134+4 + orr r2, r2, r2, asl #16 + ldr r0, [sp, #4] + and r1, r2, r1 + mul r0, r1, r0 + ldr lr, [sp, #0] + ldr r3, .L18134+4 + add r0, lr, r0, lsr #4 + and r3, r0, r3 + orr r3, r3, r3, lsr #16 + strh r3, [r4, #0] @ movhi +.L18118: + add r6, r6, #1 + cmp r8, r6 + beq .L18128 +.L18131: + add r5, r5, #4 + add r4, r4, #2 +.L18106: + ldr r0, [r5, #0] + tst r0, #512 + bne .L18130 + mov r3, r0, asl #23 + mov r3, r3, lsr #23 + mov r3, r3, asl #1 + ldrh r3, [r3, r7] + add r6, r6, #1 + cmp r8, r6 + strh r3, [r4, #0] @ movhi + bne .L18131 +.L18128: + add sp, sp, #20 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18102: + subs r3, r3, r2 + str r3, [sp, #16] + beq .L18128 + ldr fp, .L18134+8 + add r5, r1, r2, asl #1 + add r0, r0, r2, asl #2 + mov sl, #0 + b .L18121 +.L18133: + ldr r4, .L18134+16 + mov r3, r1, lsr #15 + and r4, r3, r4 + mov r3, r1, asl #23 + mov r3, r3, lsr #23 + mov r7, r3, asl #1 + ldr r3, .L18134+12 + ldr r9, .L18134+4 + mov r2, r1, asl #23 + mov r2, r2, lsr #23 + cmp lr, r3 + mov r2, r2, asl #1 + mov r8, r9 + mov ip, r9 + beq .L18132 + ldrh r3, [r2, fp] + ldr r2, [sp, #4] + orr r3, r3, r3, asl #16 + and ip, r3, r9 + mul r2, ip, r2 + ldr r4, [sp, #0] + add r2, r4, r2, lsr #4 + and r1, r2, r9 + orr r3, r1, r1, lsr #16 + strh r3, [r5, #0] @ movhi +.L18126: + ldr r6, [sp, #16] + add sl, sl, #1 + cmp r6, sl + add r0, r0, #4 + add r5, r5, #2 + beq .L18128 +.L18121: + ldr r1, [r0, #0] + ldr lr, .L18134+12 + mov r3, r1, asl #23 + mov r3, r3, lsr #23 + tst r1, #512 + and lr, r1, lr + mov r3, r3, asl #1 + bne .L18133 + ldrh r3, [r3, fp] + strh r3, [r5, #0] @ movhi + b .L18126 +.L18132: + ldrh r3, [r4, fp] + ldr r1, [sp, #12] + orr r3, r3, r3, asl #16 + and r9, r3, r9 + ldrh r2, [r7, fp] + mul r1, r9, r1 + orr r2, r2, r2, asl #16 + ldr r3, [sp, #8] + and r8, r2, r8 + mla r3, r8, r3, r1 + mov r3, r3, lsr #4 + and r6, r3, ip + orr r2, r6, r6, lsr #16 + strh r2, [r5, #0] @ movhi + b .L18126 +.L18129: + ldr r3, .L18134+16 + mov r2, r0, lsr #15 + and r3, r2, r3 + ldrh r1, [r3, r7] + mov r0, r0, asl #23 + ldr ip, .L18134+4 + orr r1, r1, r1, asl #16 + mov r0, r0, lsr #23 + ldr lr, [sp, #12] + and ip, r1, ip + mov r0, r0, asl #1 + ldrh r2, [r0, r7] + mul lr, ip, lr + ldr r3, .L18134+4 + orr r2, r2, r2, asl #16 + ldr r1, [sp, #8] + and r3, r2, r3 + mla r1, r3, r1, lr + ldr r2, .L18134+20 + mov r1, r1, lsr #4 + and r2, r1, r2 + cmp r2, #0 + beq .L18111 + tst r1, #134217728 + orrne r1, r1, #132120576 + tst r1, #65536 + orrne r1, r1, #63488 + tst r1, #32 + orrne r1, r1, #31 +.L18111: + ldr r3, .L18134+4 + and r3, r1, r3 + orr r3, r3, r3, lsr #16 + strh r3, [r4, #0] @ movhi + b .L18118 +.L18135: + .align 2 +.L18134: + .word io_registers + .word 132184095 + .word palette_ram_converted + .word 67109376 + .word 1022 + .word 134283296 + .size expand_brighten_partial_alpha, .-expand_brighten_partial_alpha + .align 2 + .global render_scanline_bitmap + .type render_scanline_bitmap, %function +render_scanline_bitmap: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr r3, .L18153 + and r2, r1, #7 + ldrh ip, [r3, #0] + ldr r3, .L18153+4 + stmfd sp!, {r4, r5, r6, r7, r8, sl, lr} + add sl, r3, r2, asl #2 + mov r4, r0 + mov r3, #0 +.L18137: + strh ip, [r3, r4] @ movhi + add r3, r3, #2 + cmp r3, #480 + bne .L18137 + ldr r8, .L18153+8 + ldr r3, [r8, #0] + cmp r3, #0 + ldmeqfd sp!, {r4, r5, r6, r7, r8, sl, pc} + ldr r6, .L18153+12 + and r7, r1, #64 + mov r5, #0 + b .L18141 +.L18152: + bl render_scanline_obj_normal_1D +.L18146: + ldr r3, [r8, #0] + add r5, r5, #1 + cmp r3, r5 + add r6, r6, #4 + bls .L18151 +.L18141: + ldr ip, [r6, #0] + mov r1, #240 + ands r0, ip, #4 + mov r2, r4 + beq .L18142 + sub r1, r1, #240 + bic ip, ip, #4 + cmp r7, r1 + mov r2, #240 + mov r3, r4 + mov r0, ip + bne .L18152 + mov r3, r4 + mov r0, ip + mov r1, r7 + mov r2, #240 + bl render_scanline_obj_normal_2D + ldr r3, [r8, #0] + add r5, r5, #1 + cmp r3, r5 + add r6, r6, #4 + bhi .L18141 +.L18151: + ldmfd sp!, {r4, r5, r6, r7, r8, sl, pc} +.L18142: + mov lr, pc + ldr pc, [sl, #0] + b .L18146 +.L18154: + .align 2 +.L18153: + .word palette_ram_converted + .word bitmap_mode_renderers-12 + .word layer_count + .word layer_order + .size render_scanline_bitmap, .-render_scanline_bitmap + .align 2 + .global render_scanline_conditional_bitmap + .type render_scanline_conditional_bitmap, %function +render_scanline_conditional_bitmap: + @ args = 12, pretend = 0, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + mov ip, r3 + ldr r3, .L18173 + cmp r0, r1 + mov r6, r0 + sub sp, sp, #4 + mov r7, r1 + mov r8, r2 + ldrh r0, [r3, #0] + bcs .L18156 + add r2, r2, r6, asl #1 + mov r3, #0 + rsb r1, r6, r1 +.L18158: + add r3, r3, #1 + cmp r1, r3 + strh r0, [r2], #2 @ movhi + bne .L18158 +.L18156: + ldr fp, .L18173+4 + ldr r3, [fp, #0] + cmp r3, #0 + beq .L18169 + ldr r3, [sp, #40] + ldr r5, .L18173+8 + and r3, r3, #64 + and r9, ip, #16 + and sl, ip, #4 + mov r4, #0 + str r3, [sp, #0] + b .L18161 +.L18172: + cmp r9, #0 + bic ip, r0, #4 + beq .L18164 + ldr lr, [sp, #0] + mov r0, ip + cmp lr, #0 + mov r1, r6 + mov r2, r7 + mov r3, r8 + beq .L18166 + bl render_scanline_obj_normal_1D +.L18164: + ldr r3, [fp, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L18169 +.L18161: + ldr r0, [r5, #0] + tst r0, #4 + bne .L18172 + cmp sl, #0 + mov r0, r6 + mov r1, r7 + mov r2, r8 + beq .L18164 + ldr r3, [sp, #48] + mov lr, pc + ldr pc, [r3, #0] + ldr r3, [fp, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bhi .L18161 +.L18169: + add sp, sp, #4 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18166: + mov r0, ip + mov r1, r6 + mov r2, r7 + mov r3, r8 + bl render_scanline_obj_normal_2D + b .L18164 +.L18174: + .align 2 +.L18173: + .word palette_ram_converted + .word layer_count + .word layer_order + .size render_scanline_conditional_bitmap, .-render_scanline_conditional_bitmap + .align 2 + .global set_gba_resolution + .type set_gba_resolution, %function +set_gba_resolution: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + ldr r2, .L18180 + @ lr needed for prologue + ldr r3, [r2, #0] + cmp r3, r0 + bxeq lr + cmp r0, #2 + str r0, [r2, #0] + bxhi lr + ldr r3, .L18180+4 + mov r2, #240 + str r2, [r3, #0] + ldr r3, .L18180+8 + mov r1, #160 + str r1, [r3, #0] + bx lr +.L18181: + .align 2 +.L18180: + .word screen_scale + .word small_resolution_width + .word small_resolution_height + .size set_gba_resolution, .-set_gba_resolution + .align 2 + .global clear_screen + .type clear_screen, %function +clear_screen: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + ldr r3, .L18192 + stmfd sp!, {r4, lr} + ldr r2, [r3, #0] + mov r0, r0, asl #16 + ldrh r3, [r2, #16] + ldr r1, [r2, #8] + ldr r4, [r2, #12] + rsb ip, r1, r3, lsr #1 + ldr r3, [r2, #20] + cmp r4, #0 + movne lr, ip, asl #1 + mov r0, r0, lsr #16 + movne r2, r3 + movne ip, #0 + ldmeqfd sp!, {r4, pc} +.L18185: + cmp r1, #0 + movne r3, #0 + beq .L18188 +.L18187: + add r3, r3, #1 + cmp r1, r3 + strh r0, [r2], #2 @ movhi + bhi .L18187 +.L18188: + add ip, ip, #1 + cmp r4, ip + ldmlsfd sp!, {r4, pc} + add r2, r2, lr + b .L18185 +.L18193: + .align 2 +.L18192: + .word screen + .size clear_screen, .-clear_screen + .align 2 + .global blit_to_screen + .type blit_to_screen, %function +blit_to_screen: + @ args = 4, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, lr} + mov r4, r1 + ldr r1, .L18206 + subs r7, r2, #0 + ldr ip, [r1, #0] + mov lr, r3 + ldrh r2, [ip, #16] + ldr ip, [ip, #20] + mov r2, r2, lsr #1 + rsb r1, r4, r2 + ldmeqfd sp!, {r4, r5, r6, r7, r8, pc} + ldr r3, [sp, #24] + mov r6, r1, asl #1 + mla r2, r3, r2, lr + mov r5, r4, asl #1 + add r2, ip, r2, asl #1 + mov r3, #0 +.L18197: + cmp r4, #0 + movne lr, r2 + movne ip, r0 + movne r1, #0 + beq .L18201 +.L18199: + add r1, r1, #1 + ldrh r8, [ip], #2 + cmp r4, r1 + strh r8, [lr], #2 @ movhi + bne .L18199 + add r2, r2, r5 + add r0, r0, r5 +.L18201: + add r3, r3, #1 + cmp r7, r3 + ldmeqfd sp!, {r4, r5, r6, r7, r8, pc} + add r2, r2, r6 + b .L18197 +.L18207: + .align 2 +.L18206: + .word screen + .size blit_to_screen, .-blit_to_screen + .align 2 + .global print_string_ext + .type print_string_ext, %function +print_string_ext: + @ args = 16, pretend = 0, frame = 12 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr ip, .L18247 + sub sp, sp, #12 + ldr sl, [sp, #48] + ldr r4, [ip, #0] + add lr, sl, #10 + cmp lr, r4 + mov r1, r1, asl #16 + mov r2, r2, asl #16 + mov fp, r0 + mov r9, r3 + mov r4, r1, lsr #16 + mov lr, r2, lsr #16 + ldrb ip, [r0, #0] @ zero_extendqisi2 + bcs .L18240 + cmp ip, #0 + beq .L18240 + ldr r2, .L18247+4 + ldr r0, [sp, #56] + ldr r2, [r2, #0] + ldr r3, .L18247+8 + mla r0, sl, r0, r9 + ldr r3, [r3, #0] + str r2, [sp, #0] + ldr r2, [sp, #56] + str r3, [sp, #8] + add r1, r2, r2, asl #2 + ldr r3, [sp, #52] + mov r1, r1, asl #2 + str r1, [sp, #4] + add r6, r3, r0, asl #1 + mov r1, r2, asl #1 + mov r5, r9 + mov r7, #0 + mov r8, #1 +.L18212: + cmp ip, #10 + beq .L18246 + ldr r3, .L18247+12 + mov r0, r6 + ldr r2, [r3, ip, asl #2] + ldr r3, .L18247+16 + mov ip, #0 + add r2, r3, r2, asl #1 +.L18216: + ldrh r3, [r2, #0] + add ip, ip, #1 + tst r3, #32768 + streqh lr, [r0, #0] @ movhi + strneh r4, [r0, #0] @ movhi + tst r3, #16384 + streqh lr, [r0, #2] @ movhi + strneh r4, [r0, #2] @ movhi + tst r3, #8192 + streqh lr, [r0, #4] @ movhi + strneh r4, [r0, #4] @ movhi + tst r3, #4096 + streqh lr, [r0, #6] @ movhi + strneh r4, [r0, #6] @ movhi + tst r3, #2048 + streqh lr, [r0, #8] @ movhi + strneh r4, [r0, #8] @ movhi + tst r3, #1024 + strneh r4, [r0, #10] @ movhi + streqh lr, [r0, #10] @ movhi + cmp ip, #10 + add r0, r0, r1 + add r2, r2, #2 + bne .L18216 + add r3, r1, r6 + add r2, r1, r1, asl #3 + add r3, r3, r2 + ldr r2, [sp, #4] + add r5, r5, #6 + rsb r3, r2, r3 + add r6, r3, #12 +.L18215: + ldrb ip, [fp, r8] @ zero_extendqisi2 + ldr r0, [sp, #60] + add r7, r7, #1 + cmp r7, r0 + movcs r3, #0 + movcc r3, #1 + cmp ip, #0 + movne r3, #0 + ldr r2, [sp, #8] + cmp r3, #0 + add r3, r5, #6 + movne ip, #32 + addeq r8, r8, #1 + cmp r3, r2 + bcs .L18240 + cmp ip, #0 + bne .L18212 +.L18240: + add sp, sp, #12 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18246: + ldr r2, [sp, #56] + add sl, sl, #10 + mla r2, sl, r2, r9 + ldr r0, [sp, #0] + mov r5, r9 + ldr r3, [r0, #20] + add r6, r3, r2, asl #1 + b .L18215 +.L18248: + .align 2 +.L18247: + .word resolution_height + .word screen + .word resolution_width + .word _font_offset + .word _font_bits + .size print_string_ext, .-print_string_ext + .align 2 + .global debug_screen_clear + .type debug_screen_clear, %function +debug_screen_clear: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + @ lr needed for prologue + bx lr + .size debug_screen_clear, .-debug_screen_clear + .align 2 + .global debug_screen_start + .type debug_screen_start, %function +debug_screen_start: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + @ lr needed for prologue + bx lr + .size debug_screen_start, .-debug_screen_start + .align 2 + .global debug_screen_end + .type debug_screen_end, %function +debug_screen_end: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + @ lr needed for prologue + bx lr + .size debug_screen_end, .-debug_screen_end + .align 2 + .global debug_screen_update + .type debug_screen_update, %function +debug_screen_update: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + @ lr needed for prologue + bx lr + .size debug_screen_update, .-debug_screen_update + .align 2 + .global video_write_mem_savestate + .type video_write_mem_savestate, %function +video_write_mem_savestate: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, lr} + ldr r4, .L18259 + ldr r1, .L18259+4 + mov r2, #8 + ldr r0, [r4, #0] + bl memcpy + ldr r3, [r4, #0] + ldr r1, .L18259+8 + add r3, r3, #8 + mov r0, r3 + mov r2, #8 + str r3, [r4, #0] + bl memcpy + ldr r3, [r4, #0] + add r3, r3, #8 + str r3, [r4, #0] + ldmfd sp!, {r4, pc} +.L18260: + .align 2 +.L18259: + .word write_mem_ptr + .word affine_reference_x + .word affine_reference_y + .size video_write_mem_savestate, .-video_write_mem_savestate + .align 2 + .global video_read_savestate + .type video_read_savestate, %function +video_read_savestate: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, lr} + mov r3, r0 + mov r4, r0 + mov r1, #8 + mov r2, #1 + ldr r0, .L18263 + bl fread + ldr r0, .L18263+4 + mov r3, r4 + mov r1, #8 + mov r2, #1 + ldmfd sp!, {r4, lr} + b fread +.L18264: + .align 2 +.L18263: + .word affine_reference_x + .word affine_reference_y + .size video_read_savestate, .-video_read_savestate + .section .rodata.str1.4,"aMS",%progbits,1 + .align 2 +.LC0: + .ascii "\012\000" + .text + .align 2 + .global debug_screen_newline + .type debug_screen_newline, %function +debug_screen_newline: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + @ link register save eliminated. + ldr r3, .L18267 + ldr r1, .L18267+4 + ldr r0, [r3, #0] + @ lr needed for prologue + b fprintf +.L18268: + .align 2 +.L18267: + .word stderr + .word .LC0 + .size debug_screen_newline, .-debug_screen_newline + .align 2 + .global debug_screen_printf + .type debug_screen_printf, %function +debug_screen_printf: + @ args = 4, pretend = 16, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 1 + stmfd sp!, {r0, r1, r2, r3} + str lr, [sp, #-4]! + ldr r3, .L18271 + sub sp, sp, #4 + add ip, sp, #12 + ldr r0, [r3, #0] + mov r2, ip + ldr r1, [sp, #8] + str ip, [sp, #0] + bl vfprintf + add sp, sp, #4 + ldr lr, [sp], #4 + add sp, sp, #16 + bx lr +.L18272: + .align 2 +.L18271: + .word stderr + .size debug_screen_printf, .-debug_screen_printf + .align 2 + .global debug_screen_printl + .type debug_screen_printl, %function +debug_screen_printl: + @ args = 4, pretend = 16, frame = 4 + @ frame_needed = 0, uses_anonymous_args = 1 + stmfd sp!, {r0, r1, r2, r3} + str lr, [sp, #-4]! + sub sp, sp, #4 + add r3, sp, #12 + ldr r0, [sp, #8] + mov r1, r3 + str r3, [sp, #0] + bl debug_screen_printf + ldr r0, .L18275 + bl debug_screen_printf + add sp, sp, #4 + ldr lr, [sp], #4 + add sp, sp, #16 + bx lr +.L18276: + .align 2 +.L18275: + .word .LC0 + .size debug_screen_printl, .-debug_screen_printl + .align 2 + .global copy_screen + .type copy_screen, %function +copy_screen: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, lr} + mov r0, #76800 + bl malloc + ldr r3, .L18279 + mov r2, #76800 + ldr ip, [r3, #0] + mov r4, r0 + ldr r1, [ip, #20] + bl memcpy + mov r0, r4 + ldmfd sp!, {r4, pc} +.L18280: + .align 2 +.L18279: + .word screen + .size copy_screen, .-copy_screen + .align 2 + .global video_resolution_small + .type video_resolution_small, %function +video_resolution_small: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, lr} + ldr r4, .L18286 + ldr r3, .L18286+4 + ldr r2, [r4, #0] + ldr r7, .L18286+8 + sub sp, sp, #16 + str r2, [r3, #0] + ldr r0, [r7, #0] + bl SDL_FreeSurface + mov r0, #0 + mov r1, r0 + bl SDL_GP2X_AllowGfxMemory + ldr r3, [r4, #0] + ldr r6, .L18286+12 + ldr r5, .L18286+16 + cmp r3, #0 + mov r1, #320 + mov r0, r1 + mov r2, #16 + ldrne r1, [r5, #0] + ldrne r0, [r6, #0] + mov r3, #1 + bl SDL_SetVideoMode + ldr r3, .L18286+20 + ldr ip, .L18286+24 + str r0, [r3, #0] + ldr r1, [r6, #0] + ldr r2, [r5, #0] + mov r3, #16 + mov r4, #0 + mov r0, #1 + str ip, [sp, #8] + str ip, [sp, #0] + str ip, [sp, #4] + str r4, [sp, #12] + bl SDL_CreateRGBSurface + str r0, [r7, #0] + mov r0, r4 + bl SDL_ShowCursor + bl gp2x_load_mmuhack + ldr r1, [r6, #0] + ldr r0, [r5, #0] + ldr r3, .L18286+28 + ldr r2, .L18286+32 + str r1, [r3, #0] + str r0, [r2, #0] + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, pc} +.L18287: + .align 2 +.L18286: + .word screen_scale + .word current_scale + .word screen + .word small_resolution_width + .word small_resolution_height + .word hw_screen + .word 65535 + .word resolution_width + .word resolution_height + .size video_resolution_small, .-video_resolution_small + .align 2 + .global video_resolution_large + .type video_resolution_large, %function +video_resolution_large: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, lr} + ldr r3, .L18290 + ldr r5, .L18290+4 + mov r4, #0 + sub sp, sp, #16 + str r4, [r3, #0] + ldr r0, [r5, #0] + bl SDL_FreeSurface + mov r0, r4 + mov r1, r4 + bl SDL_GP2X_AllowGfxMemory + mov r1, #240 + mov r2, #16 + mov r3, #1 + mov r0, #320 + bl SDL_SetVideoMode + ldr r3, .L18290+8 + ldr ip, .L18290+12 + str r0, [r3, #0] + mov r1, #320 + mov r2, #240 + mov r3, #16 + mov r0, #1 + str ip, [sp, #8] + str ip, [sp, #0] + str ip, [sp, #4] + str r4, [sp, #12] + bl SDL_CreateRGBSurface + ldr r3, .L18290+16 + mov r2, #320 + str r2, [r3, #0] + ldr r3, .L18290+20 + mov r1, #240 + str r0, [r5, #0] + str r1, [r3, #0] + mov r0, r4 + bl SDL_ShowCursor + add sp, sp, #16 + ldmfd sp!, {r4, r5, lr} + b gp2x_load_mmuhack +.L18291: + .align 2 +.L18290: + .word current_scale + .word screen + .word hw_screen + .word 65535 + .word resolution_width + .word resolution_height + .size video_resolution_large, .-video_resolution_large + .align 2 + .global init_video + .type init_video, %function +init_video: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, lr} + ldr r0, .L18294 + sub sp, sp, #16 + bl SDL_Init + mov r0, #0 + mov r1, r0 + bl SDL_GP2X_AllowGfxMemory + mov r1, #240 + mov r2, #16 + mov r3, #1 + mov r0, #320 + bl SDL_SetVideoMode + ldr r3, .L18294+4 + ldr ip, .L18294+8 + str r0, [r3, #0] + mov r4, #0 + mov r1, #240 + mov r2, #160 + mov r3, #16 + mov r0, #1 + str ip, [sp, #8] + str ip, [sp, #0] + str ip, [sp, #4] + str r4, [sp, #12] + bl SDL_CreateRGBSurface + ldr r3, .L18294+12 + str r0, [r3, #0] + bl gp2x_load_mmuhack + mov r0, r4 + add sp, sp, #16 + ldmfd sp!, {r4, lr} + b SDL_ShowCursor +.L18295: + .align 2 +.L18294: + .word 1049120 + .word hw_screen + .word 65535 + .word screen + .size init_video, .-init_video + .align 2 + .global flip_screen + .type flip_screen, %function +flip_screen: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, lr} + ldr r2, .L18304 + mov r1, #0 + ldr r0, [r2, #0] + sub sp, sp, #16 + cmp r0, r1 + mov r3, r1 + bne .L18297 + ldr r2, .L18304+4 + ldr r0, .L18304+8 + ldr ip, [r2, #0] + ldr r2, [r0, #0] + cmp ip, r2 + beq .L18303 +.L18297: + ldr r2, .L18304+12 + ldr ip, .L18304+16 + ldr r0, [r2, #0] + ldr r2, [ip, #0] + bl SDL_UpperBlit +.L18302: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, pc} +.L18303: + ldr r2, .L18304+20 + ldr r0, .L18304+24 + ldr ip, [r2, #0] + ldr r2, [r0, #0] + cmp ip, r2 + bne .L18297 + ldr ip, .L18304+28 + ldr r3, .L18304+12 + ldr r1, .L18304+16 + ldmia ip, {r4-r5} + str r4, [sp, #8] + str r5, [sp, #12] + ldr r4, .L18304+32 + ldr r2, [r1, #0] + ldr r0, [r3, #0] + add r1, sp, #8 + mov r3, sp + ldmia r4, {r5-r6} + stmia sp, {r5-r6} + bl SDL_UpperBlit + b .L18302 +.L18305: + .align 2 +.L18304: + .word screen_scale + .word resolution_width + .word small_resolution_width + .word screen + .word hw_screen + .word resolution_height + .word small_resolution_height + .word C.626.17650 + .word C.627.17651 + .size flip_screen, .-flip_screen + .align 2 + .global update_screen + .type update_screen, %function +update_screen: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, lr} + ldr r2, .L18315 + mov r1, #0 + ldr r0, [r2, #0] + sub sp, sp, #16 + cmp r0, r1 + mov r3, r1 + bne .L18313 + ldr r2, .L18315+4 + ldr r0, [r2, #0] + cmp r0, r1 + bne .L18309 + ldr r2, .L18315+8 + ldr r0, .L18315+12 + ldr ip, [r2, #0] + ldr r2, [r0, #0] + cmp ip, r2 + beq .L18314 +.L18309: + ldr r2, .L18315+16 + ldr ip, .L18315+20 + ldr r0, [r2, #0] + ldr r2, [ip, #0] + bl SDL_UpperBlit +.L18313: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, pc} +.L18314: + ldr r2, .L18315+24 + ldr r0, .L18315+28 + ldr ip, [r2, #0] + ldr r2, [r0, #0] + cmp ip, r2 + bne .L18309 + ldr ip, .L18315+32 + ldr r3, .L18315+16 + ldr r1, .L18315+20 + ldmia ip, {r4-r5} + str r4, [sp, #8] + str r5, [sp, #12] + ldr r4, .L18315+36 + ldr r2, [r1, #0] + ldr r0, [r3, #0] + add r1, sp, #8 + mov r3, sp + ldmia r4, {r5-r6} + stmia sp, {r5-r6} + bl SDL_UpperBlit + b .L18313 +.L18316: + .align 2 +.L18315: + .word skip_next_frame + .word screen_scale + .word resolution_width + .word small_resolution_width + .word screen + .word hw_screen + .word resolution_height + .word small_resolution_height + .word C.626.17650 + .word C.627.17651 + .size update_screen, .-update_screen + .align 2 + .global render_scanline_conditional_tile + .type render_scanline_conditional_tile, %function +render_scanline_conditional_tile: + @ args = 12, pretend = 0, frame = 976 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r9, .L18810 + sub sp, sp, #976 + ldr lr, [r9, #0] + mov r6, r0 + cmp lr, #0 + mov r8, r1 + mov sl, r2 + mov r7, r3 + ldr fp, [sp, #1012] + ldr r0, [sp, #1016] + beq .L18318 + tst r3, #31 + bne .L18774 +.L18318: + mov r3, r0, lsr #6 + and r2, r3, #3 + ldr r3, .L18810+4 + cmp r2, #2 + ldrh ip, [r3, #0] + beq .L18660 + cmp r2, #3 + beq .L18775 +.L18659: + mov r3, ip, asl #16 + cmp r6, r8 + mov r3, r3, lsr #16 + bcs .L18666 + rsb r1, r6, r8 + add r0, sl, r6, asl #1 + mov ip, #0 +.L18665: + add ip, ip, #1 + cmp ip, r1 + strh r3, [r0], #2 @ movhi + bne .L18665 +.L18666: + add sp, sp, #976 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18774: + ldr r1, .L18810+8 + ldr r2, .L18810+12 + ldrh r3, [r1, #6] + ldr r1, [r2, r3, asl #2] + cmp r1, #0 + bne .L18776 +.L18454: + mov r3, r0, lsr #6 + and r3, r3, #3 + cmp r3, #2 + beq .L18488 + cmp r3, #3 + beq .L18489 + cmp r3, #1 + beq .L18777 +.L18486: + ldr r1, .L18810+24 + ands r3, r7, #16 + ldr ip, [r1, #0] + moveq r4, r3 + ldreq r2, .L18810+24 + beq .L18626 + ldr r2, .L18810+24 + mov r4, #0 +.L18638: + tst ip, #4 + mov r3, #1 + bne .L18642 + ands r5, r7, r3, asl ip + bne .L18778 + add r4, r4, #1 + cmp lr, r4 + ldr ip, [r2, #4]! + bne .L18638 + ldr r3, .L18810+4 + cmp r6, r8 + ldrh r3, [r3, #0] + bcs .L18666 + rsb r1, r6, r8 + add r0, sl, r6, asl #1 + mov ip, r5 +.L18641: + add ip, ip, #1 + cmp ip, r1 + strh r3, [r0], #2 @ movhi + bne .L18641 + b .L18666 +.L18660: + ldr r2, .L18810+8 + ldrh r3, [r2, #80] + tst r3, #32 + beq .L18659 + ldrh r3, [r2, #84] + ldr r1, .L18810+16 + and r3, r3, #31 + cmp r3, #16 + movcs r3, #16 + orr r2, ip, ip, asl #16 + and r1, r2, r1 + rsb r0, r3, #16 + rsb r2, r3, r3, asl #6 + mul ip, r1, r0 + add r3, r3, r2, asl #5 + rsb r3, r3, r3, asl #16 + ldr r1, .L18810+16 + mov r3, r3, lsr #4 + and r1, r3, r1 + ldr r2, .L18810+16 + add r1, r1, ip, lsr #4 + and r2, r1, r2 + orr ip, r2, r2, lsr #16 + b .L18659 +.L18775: + ldr r2, .L18810+8 + ldrh r3, [r2, #80] + tst r3, #32 + beq .L18659 + ldrh r3, [r2, #84] + ldr r0, .L18810+16 + and r3, r3, #31 + orr r2, ip, ip, asl #16 + rsb r3, r3, #16 + and r0, r2, r0 + cmp r3, #0 + movlt r3, #0 + mul r1, r3, r0 + ldr r2, .L18810+16 + mov r1, r1, lsr #4 + and r2, r1, r2 + orr ip, r2, r2, lsr #16 + b .L18659 +.L18776: + mov r3, r0, lsr #6 + and r3, r3, #3 + cmp r3, #2 + beq .L18325 + cmp r3, #3 + beq .L18326 + cmp r3, #1 + beq .L18779 +.L18323: + ldr r5, .L18810+24 + ands r3, r7, #16 + ldr r2, [r5, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18452 + ldr r1, .L18810+24 + mov r4, #0 +.L18465: + tst r2, #4 + mov r3, #1 + bne .L18780 + ands r3, r7, r3, asl r2 + bne .L18781 + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18465 + cmp r6, r8 + bcs .L18499 + add r5, sp, #16 + add r2, r5, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18468: + add r3, r3, #1 + cmp r1, r3 + str r0, [r2], #4 + bne .L18468 +.L18499: + add r0, sp, #16 + mov r1, sl + mov r2, r6 + mov r3, r8 + bl expand_blend + b .L18666 +.L18452: + tst r2, #4 + bne .L18451 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18782 +.L18451: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18452 + cmp r6, r8 + bcs .L18499 + add r0, sp, #16 + mov r3, #0 + add r2, r0, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18456: + add r3, r3, #1 + cmp r3, r1 + str r0, [r2], #4 + bne .L18456 + b .L18499 +.L18626: + tst ip, #4 + bne .L18625 + mov r3, #1 + ands r3, r7, r3, asl ip + bne .L18783 +.L18625: + add r4, r4, #1 + cmp lr, r4 + ldr ip, [r2, #4]! + bne .L18626 + ldr r3, .L18810+4 + cmp r6, r8 + ldrh r3, [r3, #0] + bcs .L18666 + rsb r1, r6, r8 + add r0, sl, r6, asl #1 + mov ip, #0 +.L18629: + add ip, ip, #1 + cmp ip, r1 + strh r3, [r0], #2 @ movhi + bne .L18629 + b .L18666 +.L18777: + tst r7, #32 + beq .L18486 + ldr r5, .L18810+8 + ldr r3, .L18810+20 + ldrh r2, [r5, #82] + and r3, r2, r3 + cmp r3, #31 + beq .L18486 + ldrh r3, [r5, #80] + tst r3, #63 + beq .L18486 + tst r3, #16128 + beq .L18486 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18497 + ldr r1, .L18810+24 + mov r5, #0 +.L18510: + tst r2, #4 + mov r3, #1 + bne .L18784 + ands r3, r7, r3, asl r2 + bne .L18785 + add r5, r5, #1 + cmp lr, r5 + ldr r2, [r1, #4]! + bne .L18510 + cmp r6, r8 + bcs .L18499 + add r5, sp, #16 + add r2, r5, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18513: + add r3, r3, #1 + cmp r1, r3 + str r0, [r2], #4 + bne .L18513 + b .L18499 +.L18779: + tst r7, #32 + beq .L18323 + ldr r3, .L18810+8 + ldrh r2, [r3, #82] + ldr r3, .L18810+20 + and r3, r2, r3 + cmp r3, #31 + beq .L18323 + ldr r5, .L18810+8 + ldrh r3, [r5, #80] + tst r3, #63 + beq .L18323 + tst r3, #16128 + beq .L18323 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18334 + ldr r1, .L18810+24 + mov r5, #0 +.L18347: + tst r2, #4 + mov r3, #1 + bne .L18786 + ands r3, r7, r3, asl r2 + bne .L18787 + add r5, r5, #1 + cmp lr, r5 + ldr r2, [r1, #4]! + bne .L18347 + cmp r6, r8 + bcs .L18499 + add r5, sp, #16 + add r2, r5, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18350: + add r3, r3, #1 + cmp r3, r1 + str r0, [r2], #4 + bne .L18350 + b .L18499 +.L18497: + tst r2, #4 + bne .L18496 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18788 +.L18496: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18497 + cmp r6, r8 + bcs .L18499 + add r1, sp, #16 + mov r3, #0 + add r2, r1, r6, asl #2 + mov r0, r3 + rsb r1, r6, r8 +.L18501: + add r3, r3, #1 + cmp r3, r1 + str r0, [r2], #4 + bne .L18501 + b .L18499 +.L18334: + tst r2, #4 + bne .L18333 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18789 +.L18333: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18334 + cmp r6, r8 + bcs .L18499 + add r1, sp, #16 + mov r3, #0 + add r2, r1, r6, asl #2 + mov r0, r3 + rsb r1, r6, r8 +.L18338: + add r3, r3, #1 + cmp r3, r1 + str r0, [r2], #4 + bne .L18338 + b .L18499 +.L18488: + tst r7, #32 + beq .L18486 + ldr r5, .L18810+8 + ldrh r3, [r5, #84] + tst r3, #31 + beq .L18486 + ldrh r3, [r5, #80] + tst r3, #63 + beq .L18486 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18537 + mov r3, #0 + ldr r1, .L18810+24 + str r3, [sp, #8] +.L18550: + tst r2, #4 + mov r3, #1 + bne .L18790 + ands r3, r7, r3, asl r2 + bne .L18791 + ldr r2, [sp, #8] + add r2, r2, #1 + cmp lr, r2 + str r2, [sp, #8] + ldr r2, [r1, #4]! + bne .L18550 + cmp r6, r8 + bcs .L18679 + mov r2, r3 + rsb r5, r6, r8 + add r3, sl, r6, asl #1 +.L18553: + add r2, r2, #1 + mov r0, #0 @ movhi + cmp r5, r2 + strh r0, [r3], #2 @ movhi + bne .L18553 +.L18539: + ldr r3, .L18810+8 + ldr r8, .L18810+16 + ldrh r2, [r3, #84] + and r2, r2, #31 + cmp r2, #16 + movcs r2, #16 + rsb r3, r2, r2, asl #6 + add r3, r2, r3, asl #5 + rsb r3, r3, r3, asl #16 + mov r3, r3, lsr #4 + cmp r5, #0 + and r8, r3, r8 + rsb r7, r2, #16 + beq .L18666 + ldr r9, .L18810+4 + add r0, sl, r6, asl #1 + mov r4, #0 +.L18572: + ldrh r3, [r0, #0] + ldr lr, .L18810+16 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, r9] + mov ip, lr + orrne r3, r3, r3, asl #16 + andne lr, r3, lr + mulne r2, lr, r7 + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + addne r2, r8, r2, lsr #4 + andne ip, r2, ip + ldreqh r1, [r1, r9] + orrne r3, ip, ip, lsr #16 + add r4, r4, #1 + strneh r3, [r0, #0] @ movhi + streqh r1, [r0, #0] @ movhi + cmp r5, r4 + add r0, r0, #2 + bne .L18572 + b .L18666 +.L18537: + tst r2, #4 + bne .L18536 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18792 +.L18536: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18537 + cmp r6, r8 + bcs .L18679 + rsb r5, r6, r8 + add r2, sl, r6, asl #1 + mov r3, #0 +.L18541: + add r3, r3, #1 + mov r1, #0 @ movhi + cmp r3, r5 + strh r1, [r2], #2 @ movhi + bne .L18541 + b .L18539 +.L18336: +.L18325: + tst r7, #32 + beq .L18323 + ldr r5, .L18810+8 + ldrh r3, [r5, #84] + tst r3, #31 + beq .L18323 + ldrh r3, [r5, #80] + tst r3, #63 + beq .L18323 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18375 + ldr r1, .L18810+24 + mov r5, #0 +.L18388: + tst r2, #4 + mov r3, #1 + bne .L18793 + ands r3, r7, r3, asl r2 + bne .L18794 + add r5, r5, #1 + cmp lr, r5 + ldr r2, [r1, #4]! + bne .L18388 + cmp r6, r8 + bcs .L18377 + add r5, sp, #16 + add r2, r5, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18391: + add r3, r3, #1 + cmp r1, r3 + str r0, [r2], #4 + bne .L18391 +.L18377: + add r0, sp, #16 + mov r1, sl + mov r2, r6 + mov r3, r8 + bl expand_brighten_partial_alpha + b .L18666 +.L18375: + tst r2, #4 + bne .L18374 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18795 +.L18374: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18375 + cmp r6, r8 + bcs .L18377 + add r1, sp, #16 + mov r3, #0 + add r2, r1, r6, asl #2 + mov r0, r3 + rsb r1, r6, r8 +.L18379: + add r3, r3, #1 + cmp r1, r3 + str r0, [r2], #4 + bne .L18379 + b .L18377 +.L18489: + tst r7, #32 + beq .L18486 + ldr r5, .L18810+8 + ldrh r3, [r5, #84] + tst r3, #31 + beq .L18486 + ldrh r2, [r5, #80] + tst r2, #63 + beq .L18486 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18583 + mov r3, #0 + ldr r1, .L18810+24 + str r3, [sp, #12] +.L18596: + tst r2, #4 + mov r3, #1 + bne .L18796 + ands r3, r7, r3, asl r2 + bne .L18797 + ldr r2, [sp, #12] + add r2, r2, #1 + cmp lr, r2 + str r2, [sp, #12] + ldr r2, [r1, #4]! + bne .L18596 + cmp r6, r8 + bcs .L18682 + mov r2, r3 + rsb r5, r6, r8 + add r3, sl, r6, asl #1 +.L18599: + add r2, r2, #1 + mov r0, #0 @ movhi + cmp r5, r2 + strh r0, [r3], #2 @ movhi + bne .L18599 +.L18585: + ldr r0, .L18810+8 + ldrh r3, [r0, #84] + and r3, r3, #31 + rsb r3, r3, #16 + cmp r3, #0 + movge r7, r3 + movlt r7, #0 + cmp r5, #0 + beq .L18666 + ldr r8, .L18810+4 + add r0, sl, r6, asl #1 + mov r4, #0 +.L18618: + ldrh r3, [r0, #0] + ldr lr, .L18810+16 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, r8] + mov ip, lr + orrne r3, r3, r3, asl #16 + andne lr, r3, lr + mulne r2, r7, lr + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + movne r2, r2, lsr #4 + andne ip, r2, ip + ldreqh r1, [r1, r8] + orrne r3, ip, ip, lsr #16 + add r4, r4, #1 + strneh r3, [r0, #0] @ movhi + streqh r1, [r0, #0] @ movhi + cmp r5, r4 + add r0, r0, #2 + bne .L18618 + b .L18666 +.L18583: + tst r2, #4 + bne .L18582 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18798 +.L18582: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18583 + cmp r6, r8 + bcs .L18682 + rsb r5, r6, r8 + add r2, sl, r6, asl #1 + mov r3, #0 +.L18587: + add r3, r3, #1 + mov r1, #0 @ movhi + cmp r5, r3 + strh r1, [r2], #2 @ movhi + bne .L18587 + b .L18585 +.L18326: + tst r7, #32 + beq .L18323 + ldr r5, .L18810+8 + ldrh r3, [r5, #84] + tst r3, #31 + beq .L18323 + ldrh r3, [r5, #80] + tst r3, #63 + beq .L18323 + ldr r0, .L18810+24 + ands r3, r7, #16 + ldr r2, [r0, #0] + moveq r4, r3 + ldreq r1, .L18810+24 + beq .L18415 + ldr r1, .L18810+24 + mov r5, #0 +.L18428: + tst r2, #4 + mov r3, #1 + bne .L18799 + ands r3, r7, r3, asl r2 + bne .L18800 + add r5, r5, #1 + cmp lr, r5 + ldr r2, [r1, #4]! + bne .L18428 + cmp r6, r8 + bcs .L18417 + add r5, sp, #16 + add r2, r5, r6, asl #2 + rsb r1, r6, r8 + mov r0, r3 +.L18431: + add r3, r3, #1 + cmp r3, r1 + str r0, [r2], #4 + bne .L18431 +.L18417: + add r0, sp, #16 + mov r1, sl + mov r2, r6 + mov r3, r8 + bl expand_darken_partial_alpha + b .L18666 +.L18415: + tst r2, #4 + bne .L18414 + mov r3, #1 + ands r3, r7, r3, asl r2 + bne .L18801 +.L18414: + add r4, r4, #1 + cmp lr, r4 + ldr r2, [r1, #4]! + bne .L18415 + cmp r6, r8 + bcs .L18417 + add r1, sp, #16 + mov r3, #0 + add r2, r1, r6, asl #2 + mov r0, r3 + rsb r1, r6, r8 +.L18419: + add r3, r3, #1 + cmp r1, r3 + str r0, [r2], #4 + bne .L18419 + b .L18417 +.L18780: + cmp r6, r8 + addcc r0, sp, #16 + movcc r3, #0 + addcc r1, r0, r6, asl #2 + movcc ip, r3 + rsbcc r0, r6, r8 + bcs .L18472 +.L18474: + add r3, r3, #1 + cmp r3, r0 + str ip, [r1], #4 + bne .L18474 +.L18472: + tst fp, #64 + bic r0, r2, #4 + beq .L18475 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_1D +.L18477: + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18499 + ldr r2, .L18810+24 + and fp, fp, #64 + add r4, r2, r4, asl #2 + b .L18479 +.L18802: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + mov r0, ip + beq .L18482 + bl render_scanline_obj_partial_alpha_1D +.L18484: + ldr r3, [r9, #0] + add r5, r5, #1 + cmp r3, r5 + add r4, r4, #4 + bls .L18499 +.L18479: + ldr ip, [r4, #4] + tst ip, #4 + bne .L18802 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r3, [sp, #1020] + mov r0, ip + mov r1, r6 + add ip, r3, ip, asl #5 + mov r2, r8 + add r3, sp, #16 + beq .L18484 + mov lr, pc + ldr pc, [ip, #28] + b .L18484 +.L18482: + mov r0, ip + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18484 +.L18642: + ldr r3, .L18810+4 + cmp r6, r8 + ldrh r0, [r3, #0] + bcs .L18645 + add r2, sl, r6, asl #1 + mov r3, #0 + rsb r1, r6, r8 +.L18647: + add r3, r3, #1 + cmp r3, r1 + strh r0, [r2], #2 @ movhi + bne .L18647 +.L18645: + tst fp, #64 + bic r0, ip, #4 + beq .L18648 + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_normal_1D +.L18650: + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18666 + ldr r0, .L18810+24 + and fp, fp, #64 + add r4, r0, r4, asl #2 + b .L18652 +.L18803: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + mov r3, sl + mov r0, ip + beq .L18655 + bl render_scanline_obj_normal_1D +.L18657: + ldr r3, [r9, #0] + add r5, r5, #1 + cmp r3, r5 + add r4, r4, #4 + bls .L18666 +.L18652: + ldr ip, [r4, #4] + tst ip, #4 + bne .L18803 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r1, [sp, #1020] + mov r0, ip + mov r2, r8 + add ip, r1, ip, asl #5 + mov r3, sl + mov r1, r6 + beq .L18657 + mov lr, pc + ldr pc, [ip, #4] + b .L18657 +.L18655: + mov r0, ip + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_normal_2D + b .L18657 +.L18783: + mov r3, sl + ldr r5, [sp, #1020] + mov r0, ip + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [r5, ip, asl #5] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18666 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 + b .L18633 +.L18634: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bls .L18666 +.L18633: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18634 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + mov r3, sl + mov r1, r6 + mov r2, r8 + beq .L18634 + mov lr, pc + ldr pc, [ip, #4] + b .L18634 +.L18781: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] + b .L18477 +.L18778: + mov r0, ip + mov r1, r6 + mov r2, r8 + mov r3, sl + ldr r5, [sp, #1020] + mov lr, pc + ldr pc, [r5, ip, asl #5] + b .L18650 +.L18782: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18499 + ldr r2, .L18810+24 + add r4, r2, r4, asl #2 + b .L18460 +.L18461: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bls .L18499 +.L18460: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18461 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + beq .L18461 + mov lr, pc + ldr pc, [ip, #28] + b .L18461 +.L18648: + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_normal_2D + b .L18650 +.L18475: + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18477 +.L18792: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + mov r3, sl + mov r2, r8 + mov lr, pc + ldr pc, [ip, #16] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18679 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 +.L18545: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + add r4, r4, #4 + bne .L18546 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + mov r3, sl + mov r1, r6 + mov r2, r8 + movne lr, pc + ldrne pc, [ip, #20] +.L18546: + ldr r3, [r9, #0] + cmp r3, r5 + bhi .L18545 +.L18679: + rsb r5, r6, r8 + b .L18539 +.L18795: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + add r3, sp, #16 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18377 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 +.L18383: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18384 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + movne lr, pc + ldrne pc, [ip, #28] +.L18384: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bhi .L18383 + b .L18377 +.L18791: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + mov r3, sl + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #16] + rsb r5, r6, r8 +.L18562: + ldr r2, [sp, #8] + ldr r3, [r9, #0] + add r4, r2, #1 + cmp r4, r3 + bcs .L18539 + ldr r3, .L18810+24 + and fp, fp, #64 + add r3, r3, r2, asl #2 + mov r0, r3 + str r3, [sp, #0] + b .L18564 +.L18804: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + mov r3, sl + mov r0, ip + beq .L18567 + bl render_scanline_obj_color16_1D +.L18569: + ldr r2, [sp, #0] + ldr r3, [r9, #0] + add r4, r4, #1 + add r2, r2, #4 + cmp r3, r4 + str r2, [sp, #0] + bls .L18539 + ldr r0, [sp, #0] +.L18564: + ldr ip, [r0, #4] + tst ip, #4 + bne .L18804 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r1, [sp, #1020] + mov r0, ip + mov r2, r8 + add ip, r1, ip, asl #5 + mov r3, sl + mov r1, r6 + beq .L18569 + mov lr, pc + ldr pc, [ip, #20] + b .L18569 +.L18567: + mov r0, ip + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_2D + b .L18569 +.L18811: + .align 2 +.L18810: + .word layer_count + .word palette_ram_converted + .word io_registers + .word obj_alpha_count + .word 132184095 + .word 7967 + .word layer_order +.L18790: + cmp r6, r8 + rsbcs r5, r6, r8 + bcs .L18557 + add r1, sl, r6, asl #1 + mov r3, #0 + rsb r5, r6, r8 +.L18559: + add r3, r3, #1 + mov r0, #0 @ movhi + cmp r5, r3 + strh r0, [r1], #2 @ movhi + bne .L18559 +.L18557: + tst fp, #64 + bic r0, r2, #4 + beq .L18560 + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_1D + b .L18562 +.L18794: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] +.L18400: + ldr r3, [r9, #0] + add r4, r5, #1 + cmp r4, r3 + bcs .L18377 + ldr r2, .L18810+24 + and fp, fp, #64 + add r5, r2, r5, asl #2 + b .L18402 +.L18805: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + mov r0, ip + beq .L18405 + bl render_scanline_obj_partial_alpha_1D +.L18407: + ldr r3, [r9, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L18377 +.L18402: + ldr ip, [r5, #4] + tst ip, #4 + bne .L18805 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r3, [sp, #1020] + mov r0, ip + mov r1, r6 + add ip, r3, ip, asl #5 + mov r2, r8 + add r3, sp, #16 + beq .L18407 + mov lr, pc + ldr pc, [ip, #28] + b .L18407 +.L18405: + mov r0, ip + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18407 +.L18793: + cmp r6, r8 + addcc r0, sp, #16 + movcc r3, #0 + addcc r1, r0, r6, asl #2 + movcc ip, r3 + rsbcc r0, r6, r8 + bcs .L18395 +.L18397: + add r3, r3, #1 + cmp r0, r3 + str ip, [r1], #4 + bne .L18397 +.L18395: + tst fp, #64 + bic r0, r2, #4 + beq .L18398 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_1D + b .L18400 +.L18801: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + add r3, sp, #16 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18417 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 +.L18423: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18424 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + movne lr, pc + ldrne pc, [ip, #28] +.L18424: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bhi .L18423 + b .L18417 +.L18560: + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_2D + b .L18562 +.L18398: + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18400 +.L18798: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + mov r3, sl + mov r2, r8 + mov lr, pc + ldr pc, [ip, #16] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18682 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 +.L18591: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + add r4, r4, #4 + bne .L18592 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + mov r3, sl + mov r1, r6 + mov r2, r8 + movne lr, pc + ldrne pc, [ip, #20] +.L18592: + ldr r3, [r9, #0] + cmp r3, r5 + bhi .L18591 +.L18682: + rsb r5, r6, r8 + b .L18585 +.L18797: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + mov r3, sl + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #16] + rsb r5, r6, r8 +.L18608: + ldr r2, [sp, #12] + ldr r3, [r9, #0] + add r4, r2, #1 + cmp r4, r3 + bcs .L18585 + ldr r3, .L18810+24 + and fp, fp, #64 + add r3, r3, r2, asl #2 + str r3, [sp, #4] + b .L18610 +.L18806: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + mov r3, sl + mov r0, ip + beq .L18613 + bl render_scanline_obj_color16_1D +.L18615: + ldr r2, [sp, #4] + ldr r3, [r9, #0] + add r4, r4, #1 + add r2, r2, #4 + cmp r3, r4 + str r2, [sp, #4] + bls .L18585 +.L18610: + ldr r0, [sp, #4] + ldr ip, [r0, #4] + tst ip, #4 + bne .L18806 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r1, [sp, #1020] + mov r0, ip + mov r2, r8 + add ip, r1, ip, asl #5 + mov r3, sl + mov r1, r6 + beq .L18615 + mov lr, pc + ldr pc, [ip, #20] + b .L18615 +.L18613: + mov r0, ip + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_2D + b .L18615 +.L18796: + cmp r6, r8 + rsbcs r5, r6, r8 + bcs .L18603 + add r1, sl, r6, asl #1 + mov r3, #0 + rsb r5, r6, r8 +.L18605: + add r3, r3, #1 + mov r0, #0 @ movhi + cmp r3, r5 + strh r0, [r1], #2 @ movhi + bne .L18605 +.L18603: + tst fp, #64 + bic r0, r2, #4 + beq .L18606 + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_1D + b .L18608 +.L18789: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + add r3, sp, #16 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #8] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18499 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 + b .L18342 +.L18343: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bls .L18499 +.L18342: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18343 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + beq .L18343 + mov lr, pc + ldr pc, [ip, #12] + b .L18343 +.L18787: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #8] +.L18359: + ldr r3, [r9, #0] + add r4, r5, #1 + cmp r4, r3 + bcs .L18499 + ldr r2, .L18810+24 + and fp, fp, #64 + add r5, r2, r5, asl #2 + b .L18361 +.L18807: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + mov r0, ip + beq .L18364 + bl render_scanline_obj_alpha_obj_1D +.L18366: + ldr r3, [r9, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L18499 +.L18361: + ldr ip, [r5, #4] + tst ip, #4 + bne .L18807 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r3, [sp, #1020] + mov r0, ip + mov r1, r6 + add ip, r3, ip, asl #5 + mov r2, r8 + add r3, sp, #16 + beq .L18366 + mov lr, pc + ldr pc, [ip, #12] + b .L18366 +.L18364: + mov r0, ip + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_2D + b .L18366 +.L18786: + cmp r6, r8 + addcc r0, sp, #16 + movcc r3, #0 + addcc r1, r0, r6, asl #2 + movcc ip, r3 + rsbcc r0, r6, r8 + bcs .L18354 +.L18356: + add r3, r3, #1 + cmp r3, r0 + str ip, [r1], #4 + bne .L18356 +.L18354: + tst fp, #64 + bic r0, r2, #4 + beq .L18357 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_1D + b .L18359 +.L18784: + cmp r6, r8 + addcc r0, sp, #16 + movcc r3, #0 + addcc r1, r0, r6, asl #2 + movcc ip, r3 + rsbcc r0, r6, r8 + bcs .L18517 +.L18519: + add r3, r3, #1 + cmp r3, r0 + str ip, [r1], #4 + bne .L18519 +.L18517: + tst fp, #64 + bic r0, r2, #4 + beq .L18520 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_1D +.L18522: + ldr r3, [r9, #0] + add r4, r5, #1 + cmp r4, r3 + bcs .L18499 + ldr r2, .L18810+24 + and fp, fp, #64 + add r5, r2, r5, asl #2 + b .L18524 +.L18808: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + mov r0, ip + beq .L18527 + bl render_scanline_obj_alpha_obj_1D +.L18529: + ldr r3, [r9, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L18499 +.L18524: + ldr ip, [r5, #4] + tst ip, #4 + bne .L18808 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r3, [sp, #1020] + mov r0, ip + mov r1, r6 + add ip, r3, ip, asl #5 + mov r2, r8 + add r3, sp, #16 + beq .L18529 + mov lr, pc + ldr pc, [ip, #12] + b .L18529 +.L18788: + ldr r3, [sp, #1020] + mov r0, r2 + add ip, r3, r2, asl #5 + mov r1, r6 + add r3, sp, #16 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #8] + ldr r3, [r9, #0] + add r5, r4, #1 + cmp r5, r3 + bcs .L18499 + ldr r0, .L18810+24 + add r4, r0, r4, asl #2 + b .L18505 +.L18506: + ldr r3, [r9, #0] + add r4, r4, #4 + cmp r3, r5 + bls .L18499 +.L18505: + ldr r2, [r4, #4] + add r5, r5, #1 + tst r2, #4 + bne .L18506 + mov r3, #1 + ands r3, r7, r3, asl r2 + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + beq .L18506 + mov lr, pc + ldr pc, [ip, #12] + b .L18506 +.L18527: + mov r0, ip + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_2D + b .L18529 +.L18520: + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_2D + b .L18522 +.L18357: + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_alpha_obj_2D + b .L18359 +.L18800: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #24] +.L18440: + ldr r3, [r9, #0] + add r4, r5, #1 + cmp r4, r3 + bcs .L18417 + ldr r2, .L18810+24 + and fp, fp, #64 + add r5, r2, r5, asl #2 + b .L18442 +.L18809: + bic ip, ip, #4 + cmp fp, #0 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + mov r0, ip + beq .L18445 + bl render_scanline_obj_partial_alpha_1D +.L18447: + ldr r3, [r9, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L18417 +.L18442: + ldr ip, [r5, #4] + tst ip, #4 + bne .L18809 + mov r3, #1 + ands r3, r7, r3, asl ip + ldr r3, [sp, #1020] + mov r0, ip + mov r1, r6 + add ip, r3, ip, asl #5 + mov r2, r8 + add r3, sp, #16 + beq .L18447 + mov lr, pc + ldr pc, [ip, #28] + b .L18447 +.L18445: + mov r0, ip + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18447 +.L18799: + cmp r6, r8 + addcc r0, sp, #16 + movcc r3, #0 + addcc r1, r0, r6, asl #2 + movcc ip, r3 + rsbcc r0, r6, r8 + bcs .L18435 +.L18437: + add r3, r3, #1 + cmp r3, r0 + str ip, [r1], #4 + bne .L18437 +.L18435: + tst fp, #64 + bic r0, r2, #4 + beq .L18438 + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_1D + b .L18440 +.L18785: + ldr r1, [sp, #1020] + mov r0, r2 + add ip, r1, r2, asl #5 + add r3, sp, #16 + mov r1, r6 + mov r2, r8 + mov lr, pc + ldr pc, [ip, #8] + b .L18522 +.L18606: + mov r1, r6 + mov r2, r8 + mov r3, sl + bl render_scanline_obj_color16_2D + b .L18608 +.L18438: + mov r1, r6 + mov r2, r8 + add r3, sp, #16 + bl render_scanline_obj_partial_alpha_2D + b .L18440 + .size render_scanline_conditional_tile, .-render_scanline_conditional_tile + .align 2 + .global render_scanline_obj_copy_tile_2D + .type render_scanline_obj_copy_tile_2D, %function +render_scanline_obj_copy_tile_2D: + @ args = 0, pretend = 0, frame = 596 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L19654 + add r0, r0, r0, asl #2 + ldrh r4, [r5, #6] + ldr ip, .L19654+4 + add r0, r4, r0, asl #5 + ldrh r6, [r5, #0] + sub sp, sp, #608 + ldr ip, [ip, r0, asl #2] + str r6, [sp, #56] + str ip, [sp, #80] + cmp ip, #0 + ldr ip, [sp, #56] + ldrh r6, [r5, #74] + str r4, [sp, #76] + ldr lr, .L19654+8 + and r4, ip, #7 + ldr ip, .L19654+12 + ldrh r5, [r5, #80] + add r4, ip, r4, asl #7 + add r0, lr, r0, asl #7 + mov r6, r6, lsr #8 + str r4, [sp, #64] + str r0, [sp, #84] + str r1, [sp, #28] + str r2, [sp, #24] + str r3, [sp, #20] + str r6, [sp, #60] + str r5, [sp, #52] + beq .L19604 + rsb r0, r1, r2 + add lr, r3, r1, asl #1 + mov r1, #0 + mov r2, r1 + str lr, [sp, #104] + str r0, [sp, #124] + str r1, [sp, #72] + b .L18815 +.L18819: + ldr lr, [sp, #72] + ldr r0, [sp, #80] + add lr, lr, #1 + cmp r0, lr + str lr, [sp, #72] + beq .L19604 + ldr r2, [sp, #72] +.L18815: + ldr r4, [sp, #84] + ldr r5, .L19654+16 + ldrb r3, [r2, r4] @ zero_extendqisi2 + ldr lr, .L19654+20 + mov r3, r3, asl #3 + ldrh r6, [r3, r5] + add r3, r3, r5 + ldrh r7, [r3, #2] + mov r9, r6, lsr #12 + and r2, r9, #12 + orr sl, r2, r7, lsr #14 + mov r1, r7, asl #23 + ldr fp, [lr, sl, asl #2] + ands ip, r6, #512 + mov r8, r1, asr #23 + ldr r0, [sp, #24] + ldr r5, [sp, #28] + addne r1, r8, fp, asl #1 + addeq r1, r8, fp + ldr r2, [sp, #28] + cmp r8, r5 + movcs r5, r8 + cmp r1, r0 + movcs r1, r0 + str ip, [sp, #32] + ldrh ip, [r3, #4] + cmp r0, r5 + movls r3, #0 + movhi r3, #1 + cmp r2, r1 + movcs r3, #0 + cmp r3, #0 + beq .L18819 + ldr lr, [sp, #56] + add r4, sp, #128 + str lr, [sp, #0] + ldr lr, [sp, #52] + mov r0, r5 + str lr, [sp, #4] + ldr lr, [sp, #64] + ldr r3, [sp, #60] + mov r2, r4 + str ip, [sp, #12] + str lr, [sp, #8] + bl render_scanline_conditional_tile + and r0, r6, #255 + cmp r0, #160 + ldr r3, .L19654+24 + add r5, r4, r5, asl #1 + subgt r0, r0, #256 + tst r6, #256 + str r5, [sp, #68] + ldr ip, [sp, #12] + ldr sl, [r3, sl, asl #2] + beq .L18823 + tst r6, #8192 + beq .L18825 + mov r3, r7, lsr #4 + ldr r2, .L19654+16 + and r3, r3, #992 + add r3, r3, r2 + ldr r1, [sp, #32] + ldrh r4, [r3, #30] + cmp r1, #0 + add r1, sl, sl, lsr #31 + ldrh r5, [r3, #6] + add r2, fp, fp, lsr #31 + str r4, [sp, #40] + mov r4, r1, asr #1 + ldr r1, [sp, #28] + mov lr, r2, asr #1 + str r5, [sp, #36] + moveq r9, fp + moveq r7, lr + moveq r5, r4 + movne r9, fp, asl #1 + movne r7, lr, asl #1 + movne r5, r4, asl #1 + cmp r8, r1 + ldrh r2, [r3, #14] + ldrh r6, [r3, #22] + bge .L18830 + rsb r1, r8, r1 + rsb r9, r1, r9 + cmp r9, #0 + ble .L18819 + ldr r8, [sp, #28] + rsb r7, r1, r7 +.L18830: + ldr r1, [sp, #24] + add r3, r8, r9 + cmp r3, r1 + bge .L19632 +.L18833: + add r0, r0, r5 + ldr r5, [sp, #36] + mov r2, r2, asl #16 + mov r3, r5, asl #16 + ldr r5, [sp, #40] + mov r3, r3, asr #16 + mov r1, r5, asl #16 + str r3, [sp, #88] + mov r5, r2, asr #16 + ldr r3, [sp, #76] + ldr r2, [sp, #20] + mov lr, lr, asl #8 + cmp r6, #0 + str lr, [sp, #112] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r8, r2, r8, asl #1 + rsb r0, r0, r3 + beq .L19633 + mov r3, ip, asl #22 + ldr r2, .L19654+28 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r9, #0 + str r3, [sp, #120] + ble .L18819 + mov r3, r6, asl #16 + mul r2, r0, r1 + mov r6, r3, asr #16 + mul r3, r0, r5 + ldr r0, [sp, #88] + mul r1, r6, r7 + mul r0, r7, r0 + ldr ip, [sp, #112] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r5, ip, r3 + add r4, lr, r2 + mov ip, r4, asr #8 + mov lr, r5, asr #8 + cmp lr, fp + cmpcc ip, sl + movcs r3, #0 + movcc r3, #1 + movcs r7, r3 + bcc .L19634 +.L18851: + ldr lr, [sp, #88] + ldr r0, [sp, #68] + add r7, r7, #1 + add r5, r5, lr + add r4, r4, r6 + add r0, r0, #2 + cmp r9, r7 + mov lr, r5, asr #8 + mov ip, r4, asr #8 + add r8, r8, #2 + str r0, [sp, #68] + beq .L18819 + cmp lr, fp + cmpcc ip, sl + bcs .L18851 + cmp ip, sl + cmpcc lr, fp + bcs .L18819 +.L19635: + ldr r1, [sp, #88] + and r3, ip, #7 + mov r2, lr, asr #3 + mov r3, r3, asl #3 + add r5, r5, r1 + add r3, r3, r2, asl #6 + mov r1, ip, asr #3 + ldr r2, [sp, #120] + add r3, r3, r1, asl #10 + add r3, r3, r2 + and r0, lr, #7 + ldrb r2, [r3, r0] @ zero_extendqisi2 + ldr r0, [sp, #68] + cmp r2, #0 + ldrne r3, [sp, #68] + add r7, r7, #1 + ldrneh r3, [r3, #0] + add r4, r4, r6 + strneh r3, [r8, #0] @ movhi + add r0, r0, #2 + cmp r9, r7 + mov ip, r4, asr #8 + mov lr, r5, asr #8 + add r8, r8, #2 + str r0, [sp, #68] + ble .L18819 +.L18854: + cmp ip, sl + cmpcc lr, fp + bcc .L19635 + b .L18819 +.L18823: + ldr r4, [sp, #76] + tst r7, #8192 + rsb r0, r0, r4 + rsbne r3, r0, sl + subne r0, r3, #1 + mov r2, r7, asl #19 + and r3, r9, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L18819 + .p2align 2 +.L18903: + .word .L18899 + .word .L18900 + .word .L18901 + .word .L18902 +.L19604: + add sp, sp, #608 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L18825: + mov r3, r7, lsr #4 + ldr r2, .L19654+16 + and r3, r3, #992 + add r3, r3, r2 + ldr r1, [sp, #32] + ldrh r4, [r3, #30] + cmp r1, #0 + add r1, sl, sl, lsr #31 + ldrh r5, [r3, #6] + add r2, fp, fp, lsr #31 + str r4, [sp, #48] + mov r4, r1, asr #1 + ldr r1, [sp, #28] + mov lr, r2, asr #1 + str r5, [sp, #44] + moveq r6, fp + moveq r7, lr + moveq r5, r4 + movne r6, fp, asl #1 + movne r7, lr, asl #1 + movne r5, r4, asl #1 + cmp r8, r1 + ldrh r2, [r3, #14] + ldrh r9, [r3, #22] + bge .L18862 + rsb r1, r8, r1 + rsb r6, r1, r6 + cmp r6, #0 + ble .L18819 + ldr r8, [sp, #28] + rsb r7, r1, r7 +.L18862: + ldr r1, [sp, #24] + add r3, r8, r6 + cmp r3, r1 + bge .L19636 +.L18865: + add r0, r0, r5 + ldr r5, [sp, #44] + mov r2, r2, asl #16 + mov r3, r5, asl #16 + mov r3, r3, asr #16 + mov r2, r2, asr #16 + ldr r5, [sp, #48] + str r3, [sp, #92] + str r2, [sp, #96] + ldr r3, [sp, #76] + ldr r2, [sp, #20] + mov lr, lr, asl #8 + mov r1, r5, asl #16 + cmp r9, #0 + str lr, [sp, #108] + mov r1, r1, asr #16 + mov lr, r4, asl #8 + add r8, r2, r8, asl #1 + rsb r0, r0, r3 + beq .L19637 + mov r3, ip, asl #22 + ldr r2, .L19654+28 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + cmp r6, #0 + str r3, [sp, #116] + ble .L18819 + mov r3, r9, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #100] + ldr r3, [sp, #96] + mul r2, r0, r1 + mul r3, r0, r3 + ldr r0, [sp, #92] + ldr r1, [sp, #100] + mul r0, r7, r0 + mul r1, r7, r1 + rsb r3, r0, r3 + ldr r0, [sp, #108] + rsb r2, r1, r2 + add r5, r0, r3 + add r4, lr, r2 + mov ip, r4, asr #8 + mov lr, r5, asr #8 + cmp lr, fp + cmpcc ip, sl + movcs r3, #0 + movcc r3, #1 + movcs r7, r3 + bcc .L19638 +.L18886: + ldr r3, [sp, #68] + ldr r1, [sp, #92] + ldr r2, [sp, #100] + add r7, r7, #1 + add r5, r5, r1 + add r4, r4, r2 + add r3, r3, #2 + cmp r6, r7 + mov lr, r5, asr #8 + mov ip, r4, asr #8 + add r8, r8, #2 + str r3, [sp, #68] + beq .L18819 + cmp lr, fp + cmpcc ip, sl + bcs .L18886 + cmp ip, sl + cmpcc lr, fp + bcs .L18819 +.L19639: + mov r3, lr, asr #1 + ldr r1, [sp, #116] + and r3, r3, #3 + and r0, ip, #7 + str r3, [sp, #16] + ldr r3, [sp, #116] + add r0, r1, r0, asl #2 + and r1, ip, #7 + mov r2, lr, asr #1 + add r1, r3, r1, asl #2 + mov r3, ip, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, lr, asr #3 + tst lr, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne ip, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, ip] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + cmp r0, #0 + ldrne r2, [sp, #68] + ldr lr, [sp, #92] + ldrneh r2, [r2, #0] + ldr r3, [sp, #68] + ldr r1, [sp, #100] + add r7, r7, #1 + strneh r2, [r8, #0] @ movhi + add r5, r5, lr + add r4, r4, r1 + add r3, r3, #2 + cmp r6, r7 + mov lr, r5, asr #8 + mov ip, r4, asr #8 + add r8, r8, #2 + str r3, [sp, #68] + ble .L18819 +.L18889: + cmp ip, sl + cmpcc lr, fp + bcc .L19639 + b .L18819 +.L19636: + rsb r6, r8, r1 + cmp r6, #0 + bgt .L18865 + b .L18819 +.L19632: + rsb r9, r8, r1 + cmp r9, #0 + bgt .L18833 + b .L18819 +.L19633: + mla r3, r0, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L18819 + mov r3, ip, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L19654+28 + cmp r9, #0 + add r4, r3, r1, asl #3 + ble .L18819 + ldr r2, [sp, #88] + mul r3, r0, r5 + mul r2, r7, r2 + ldr r5, [sp, #112] + rsb r3, r2, r3 + add r0, r5, r3 + mov ip, r0, asr #8 + cmp ip, fp + movcs lr, r6 + bcc .L19640 +.L18841: + ldr r1, [sp, #68] + ldr r6, [sp, #88] + add lr, lr, #1 + add r0, r0, r6 + add r1, r1, #2 + cmp r9, lr + mov ip, r0, asr #8 + add r8, r8, #2 + str r1, [sp, #68] + beq .L18819 + cmp ip, fp + bcs .L18841 + b .L19618 +.L19637: + mla r3, r0, r1, lr + mov r1, r3, asr #8 + cmp r1, sl + bcs .L18819 + mov r3, ip, asl #22 + mov r2, r1, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #3 + ldr r3, .L19654+28 + cmp r6, #0 + add r5, r3, r1, asl #2 + ble .L18819 + ldr r3, [sp, #96] + ldr r2, [sp, #92] + mul r3, r0, r3 + mul r2, r7, r2 + ldr r4, [sp, #108] + rsb r3, r2, r3 + add r0, r4, r3 + mov ip, r0, asr #8 + cmp ip, fp + movcs r1, r9 + bcc .L19641 +.L18873: + ldr ip, [sp, #92] + ldr lr, [sp, #68] + add r1, r1, #1 + add r0, r0, ip + add lr, lr, #2 + cmp r6, r1 + mov ip, r0, asr #8 + add r8, r8, #2 + str lr, [sp, #68] + beq .L18819 + cmp ip, fp + bcs .L18873 + b .L19620 +.L18902: + subs r2, fp, #8 + submi r2, fp, #1 + mov r3, r0, lsr #3 + mov r2, r2, asr #3 + mov r1, ip, asl #22 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + ldr lr, [sp, #28] + mov r0, r3, asl #3 + ldr r3, .L19654+28 + cmp r8, lr + add r7, r0, r3 + blt .L19642 + ldr r4, [sp, #24] + add r3, r8, fp + cmp r4, r3 + bhi .L19540 + rsb r9, r8, r4 + cmp r9, #0 + ble .L18819 + ldr r5, [sp, #20] + movs sl, r9, lsr #3 + add r1, r5, r8, asl #1 + beq .L19543 + ldr r3, .L19654+32 + ldr r4, [sp, #68] + add r0, r0, r3 + mov lr, r1 + mov r5, r7 + mov r2, #0 +.L19545: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L19546 + tst ip, #255 + ldrneh r6, [r4, #6] + mov r3, ip, lsr #8 + strneh r6, [lr, #6] @ movhi + tst r3, #255 + ldrneh r3, [r4, #4] + strneh r3, [lr, #4] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrneh r6, [r4, #2] + strneh r6, [lr, #2] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r4, #0] + strneh ip, [lr, #0] @ movhi +.L19546: + ldr ip, [r5, #0] + cmp ip, #0 + beq .L19555 + tst ip, #255 + ldrneh r3, [r4, #14] + strneh r3, [lr, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r6, [r4, #12] + mov r3, ip, lsr #16 + strneh r6, [lr, #12] @ movhi + tst r3, #255 + ldrneh r3, [r4, #10] + strneh r3, [lr, #10] @ movhi + movs ip, ip, lsr #24 + ldrneh r6, [r4, #8] + strneh r6, [lr, #8] @ movhi +.L19555: + add r2, r2, #1 + cmp sl, r2 + sub r5, r5, #64 + add lr, lr, #16 + add r4, r4, #16 + sub r0, r0, #64 + bne .L19545 + ldr ip, [sp, #68] + mov r3, sl, asl #4 + rsb r2, sl, sl, asl #26 + add ip, ip, r3 + add r1, r1, r3 + add r7, r7, r2, asl #6 + str ip, [sp, #68] +.L19543: + ands ip, r9, #7 + beq .L18819 + cmp ip, #3 + ldrls r2, [r7, #4] + bls .L19578 + ldr r2, [r7, #4] + cmp r2, #0 + beq .L19568 + tst r2, #255 + ldrne lr, [sp, #68] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #6] + strneh lr, [r1, #6] @ movhi + tst r3, #255 + ldrne r0, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #4] + strneh r0, [r1, #4] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #0] + strneh r4, [r1, #0] @ movhi +.L19568: + subs ip, ip, #4 + ldr r2, [r7, #0] + beq .L18819 + ldr r5, [sp, #68] + add r1, r1, #8 + add r5, r5, #8 + str r5, [sp, #68] +.L19578: + mov r3, #0 +.L19579: + movs r6, r2, lsr #24 + ldrne lr, [sp, #68] + mov r0, r3, asl #1 + ldrneh lr, [r0, lr] + add r3, r3, #1 + strneh lr, [r0, r1] @ movhi + cmp ip, r3 + mov r2, r2, asl #8 + bhi .L19579 + b .L18819 +.L18899: + mov r3, ip, asl #22 + mov r2, r0, lsr #3 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + ldr r5, [sp, #28] + add r1, r1, r3, asl #3 + ldr r3, .L19654+28 + cmp r8, r5 + add r0, r3, r1, asl #2 + blt .L19643 + ldr r4, [sp, #24] + add r3, r8, fp + cmp r4, r3 + bhi .L18985 + rsb r7, r8, r4 + cmp r7, #0 + ble .L18819 + ldr r6, [sp, #20] + movs r5, r7, lsr #3 + add r1, r6, r8, asl #1 + beq .L18988 + ldr lr, [sp, #68] + mov ip, r1 + mov r4, r0 + mov r2, #0 +.L18990: + ldr r3, [r4, #0] + cmp r3, #0 + beq .L18991 + tst r3, #15 + ldrneh r6, [lr, #0] + strneh r6, [ip, #0] @ movhi + tst r3, #240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + tst r3, #3840 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r3, #61440 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r3, #983040 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r3, #15728640 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r3, #251658240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [lr, #14] + strneh r3, [ip, #14] @ movhi +.L18991: + add r2, r2, #1 + cmp r2, r5 + add r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L18990 + ldr r4, [sp, #68] + mov r3, r5, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r5, asl #5 + str r4, [sp, #68] +.L18988: + ands ip, r7, #7 + beq .L18819 + ldr r0, [r0, #0] + mov r2, #0 +.L19010: + tst r0, #15 + ldrne r5, [sp, #68] + mov r3, r2, asl #1 + ldrneh r5, [r3, r5] + add r2, r2, #1 + strneh r5, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, lsr #4 + bne .L19010 + b .L18819 +.L18900: + mov r3, ip, asl #22 + mov r1, r0, lsr #3 + subs r2, fp, #8 + mov r3, r3, lsr #22 + submi r2, fp, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr lr, [sp, #28] + add r1, r1, r3, asl #3 + ldr r3, .L19654+28 + cmp r8, lr + add r0, r3, r1, asl #2 + blt .L19644 + ldr lr, [sp, #24] + add r3, r8, fp + cmp lr, r3 + bhi .L19115 + rsb r7, r8, lr + cmp r7, #0 + ble .L18819 + ldr r2, [sp, #20] + movs r3, r7, lsr #3 + add r1, r2, r8, asl #1 + beq .L19118 + ldr lr, [sp, #68] + mov ip, r1 + mov r4, r0 + mov r5, #0 +.L19120: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L19121 + tst r2, #15 + ldrneh r6, [lr, #14] + strneh r6, [ip, #14] @ movhi + tst r2, #240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L19121: + add r5, r5, #1 + cmp r5, r3 + sub r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L19120 + ldr r4, [sp, #68] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r4, [sp, #68] +.L19118: + ands ip, r7, #7 + beq .L18819 + ldr r0, [r0, #0] + mov r2, #0 +.L19140: + movs r5, r0, lsr #28 + ldrne r6, [sp, #68] + mov r3, r2, asl #1 + ldrneh r6, [r3, r6] + add r2, r2, #1 + strneh r6, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L19140 + b .L18819 +.L18901: + mov r2, ip, asl #22 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + add r2, r2, r1, asl #5 + and r3, r0, #7 + add r3, r3, r2, asl #2 + ldr r1, [sp, #28] + mov r0, r3, asl #3 + ldr r3, .L19654+28 + cmp r8, r1 + add r2, r0, r3 + blt .L19645 + ldr r4, [sp, #24] + add r3, r8, fp + cmp r4, r3 + bhi .L19320 + rsb r9, r8, r4 + cmp r9, #0 + ble .L18819 + ldr r5, [sp, #20] + movs sl, r9, lsr #3 + add r1, r5, r8, asl #1 + beq .L19323 + ldr r3, .L19654+36 + ldr r4, [sp, #68] + add r0, r0, r3 + mov lr, r1 + mov r5, r2 + mov r7, #0 +.L19325: + ldr ip, [r5, #0] + cmp ip, #0 + beq .L19326 + tst ip, #255 + ldrneh r6, [r4, #0] + mov r3, ip, lsr #8 + strneh r6, [lr, #0] @ movhi + tst r3, #255 + ldrneh r3, [r4, #2] + strneh r3, [lr, #2] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrneh r6, [r4, #4] + strneh r6, [lr, #4] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r4, #6] + strneh ip, [lr, #6] @ movhi +.L19326: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L19335 + tst ip, #255 + ldrneh r3, [r4, #8] + strneh r3, [lr, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r6, [r4, #10] + mov r3, ip, lsr #16 + strneh r6, [lr, #10] @ movhi + tst r3, #255 + ldrneh r3, [r4, #12] + strneh r3, [lr, #12] @ movhi + movs ip, ip, lsr #24 + ldrneh r6, [r4, #14] + strneh r6, [lr, #14] @ movhi +.L19335: + add r7, r7, #1 + cmp r7, sl + add r5, r5, #64 + add lr, lr, #16 + add r4, r4, #16 + add r0, r0, #64 + bne .L19325 + ldr ip, [sp, #68] + mov r3, sl, asl #4 + add ip, ip, r3 + add r1, r1, r3 + add r2, r2, sl, asl #6 + str ip, [sp, #68] +.L19323: + ands ip, r9, #7 + beq .L18819 + cmp ip, #3 + ldrls r3, [r2, #0] + bls .L19358 + ldr r0, [r2, #0] + cmp r0, #0 + beq .L19348 + tst r0, #255 + ldrne lr, [sp, #68] + mov r3, r0, lsr #8 + ldrneh lr, [lr, #0] + strneh lr, [r1, #0] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #2] + strneh r3, [r1, #2] @ movhi + mov r3, r0, lsr #16 + tst r3, #255 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + movs r0, r0, lsr #24 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #6] + strneh r5, [r1, #6] @ movhi +.L19348: + subs ip, ip, #4 + ldr r3, [r2, #4] + beq .L18819 + ldr r6, [sp, #68] + add r1, r1, #8 + add r6, r6, #8 + str r6, [sp, #68] +.L19358: + mov r2, #0 +.L19359: + tst r3, #255 + ldrne lr, [sp, #68] + mov r0, r2, asl #1 + ldrneh lr, [r0, lr] + add r2, r2, #1 + strneh lr, [r0, r1] @ movhi + cmp ip, r2 + mov r3, r3, lsr #8 + bhi .L19359 + b .L18819 +.L19645: + rsb r0, r8, r1 + rsb lr, r0, fp + cmp lr, #0 + ble .L18819 + ldr r4, [sp, #24] + add r3, r8, fp + cmp r4, r3 + bhi .L19167 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add r8, r2, r3, asl #6 + bne .L19169 + ldr r7, [sp, #124] + ldr r5, [sp, #104] +.L19171: + movs r4, r7, lsr #3 + beq .L19229 + ldr r0, [sp, #68] + mov r1, r5 + mov ip, r8 + mov lr, #0 +.L19231: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19232 + tst r2, #255 + ldrneh r3, [r0, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #2] + mov r3, r2, lsr #16 + strneh r6, [r1, #2] @ movhi + tst r3, #255 + ldrneh r3, [r0, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #6] + strneh r6, [r1, #6] @ movhi +.L19232: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L19241 + tst r2, #255 + ldrneh r3, [r0, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #10] + mov r3, r2, lsr #16 + strneh r6, [r1, #10] @ movhi + tst r3, #255 + ldrneh r3, [r0, #12] + strneh r3, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #14] + strneh r6, [r1, #14] @ movhi +.L19241: + add lr, lr, #1 + cmp lr, r4 + add ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L19231 + ldr ip, [sp, #68] + mov r3, r4, asl #4 + add ip, ip, r3 + add r5, r5, r3 + add r8, r8, r4, asl #6 + str ip, [sp, #68] +.L19229: + ands r0, r7, #7 + beq .L18819 + cmp r0, #3 + ldrls r3, [r8, #0] + bls .L19264 + ldr r2, [r8, #0] + cmp r2, #0 + beq .L19254 + tst r2, #255 + ldrne lr, [sp, #68] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #0] + strneh lr, [r5, #0] @ movhi + tst r3, #255 + ldrne r1, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r1, [r1, #2] + strneh r1, [r5, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #4] + strneh r3, [r5, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #6] + strneh r4, [r5, #6] @ movhi +.L19254: + subs r0, r0, #4 + ldr r3, [r8, #4] + beq .L18819 + ldr r6, [sp, #68] + add r5, r5, #8 + add r6, r6, #8 + str r6, [sp, #68] +.L19264: + mov r2, #0 +.L19265: + tst r3, #255 + ldrne ip, [sp, #68] + mov r1, r2, asl #1 + ldrneh ip, [r1, ip] + add r2, r2, #1 + strneh ip, [r1, r5] @ movhi + cmp r0, r2 + mov r3, r3, lsr #8 + bhi .L19265 + b .L18819 +.L19655: + .align 2 +.L19654: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word tile_mode_renderers + .word oam_ram + .word obj_width_table + .word obj_height_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L19644: + rsb ip, r8, lr + rsb r1, ip, fp + cmp r1, #0 + ble .L18819 + ldr r2, [sp, #24] + add r3, r8, fp + cmp r2, r3 + bhi .L19037 + mov r3, ip, lsr #3 + ands r4, ip, #7 + sub r0, r0, r3, asl #5 + bne .L19039 + ldr r7, [sp, #124] + ldr r1, [sp, #104] +.L19041: + movs r3, r7, lsr #3 + beq .L19058 + ldr lr, [sp, #68] + mov ip, r1 + mov r4, r0 + mov r5, #0 +.L19060: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L19061 + tst r2, #15 + ldrneh r6, [lr, #14] + strneh r6, [ip, #14] @ movhi + tst r2, #240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L19061: + add r5, r5, #1 + cmp r5, r3 + sub r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L19060 + ldr r4, [sp, #68] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r4, [sp, #68] +.L19058: + ands ip, r7, #7 + beq .L18819 + ldr r0, [r0, #0] + mov r2, #0 +.L19080: + movs r5, r0, lsr #28 + ldrne r6, [sp, #68] + mov r3, r2, asl #1 + ldrneh r6, [r3, r6] + add r2, r2, #1 + strneh r6, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L19080 + b .L18819 +.L19643: + rsb ip, r8, r5 + rsb lr, ip, fp + cmp lr, #0 + ble .L18819 + ldr r6, [sp, #24] + add r3, r8, fp + cmp r6, r3 + bhi .L18907 + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + add r4, r0, r1 + bne .L18909 + ldr r7, [sp, #124] + ldr r5, [sp, #104] +.L18911: + movs lr, r7, lsr #3 + beq .L18928 + ldr r1, [sp, #68] + mov r2, r5 + mov r0, r4 + mov ip, #0 +.L18930: + ldr r3, [r0, #0] + cmp r3, #0 + beq .L18931 + tst r3, #15 + ldrneh r6, [r1, #0] + strneh r6, [r2, #0] @ movhi + tst r3, #240 + ldrneh r6, [r1, #2] + strneh r6, [r2, #2] @ movhi + tst r3, #3840 + ldrneh r6, [r1, #4] + strneh r6, [r2, #4] @ movhi + tst r3, #61440 + ldrneh r6, [r1, #6] + strneh r6, [r2, #6] @ movhi + tst r3, #983040 + ldrneh r6, [r1, #8] + strneh r6, [r2, #8] @ movhi + tst r3, #15728640 + ldrneh r6, [r1, #10] + strneh r6, [r2, #10] @ movhi + tst r3, #251658240 + ldrneh r6, [r1, #12] + strneh r6, [r2, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [r1, #14] + strneh r3, [r2, #14] @ movhi +.L18931: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + bne .L18930 + ldr r6, [sp, #68] + mov r3, lr, asl #4 + add r6, r6, r3 + add r5, r5, r3 + add r4, r4, lr, asl #5 + str r6, [sp, #68] +.L18928: + ands r0, r7, #7 + beq .L18819 + ldr r3, [r4, #0] + mov r1, #0 +.L18950: + tst r3, #15 + ldrne ip, [sp, #68] + mov r2, r1, asl #1 + ldrneh ip, [r2, ip] + add r1, r1, #1 + strneh ip, [r2, r5] @ movhi + cmp r1, r0 + mov r3, r3, lsr #4 + bne .L18950 + b .L18819 +.L18876: + cmp ip, fp + bcs .L18819 +.L19620: + mov r3, ip, asr #1 + and r4, r3, #3 + mov r3, ip, asr #3 + mov r3, r3, asl #5 + mov r2, ip, asr #1 + tst ip, #1 + and lr, r2, #3 + add ip, r3, r5 + add r2, r3, r5 + ldreqb r3, [r2, lr] @ zero_extendqisi2 + ldrneb r3, [ip, r4] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + cmp r2, #0 + ldrne r4, [sp, #68] + ldr lr, [sp, #68] + ldrneh r4, [r4, #0] + ldr r3, [sp, #92] + add r1, r1, #1 + strneh r4, [r8, #0] @ movhi + add r0, r0, r3 + add lr, lr, #2 + cmp r6, r1 + mov ip, r0, asr #8 + add r8, r8, #2 + str lr, [sp, #68] + bgt .L18876 + b .L18819 +.L18844: + cmp ip, fp + bcs .L18819 +.L19618: + ldr r2, [sp, #88] + mov r3, ip, asr #3 + add r3, r4, r3, asl #6 + and r1, ip, #7 + add r0, r0, r2 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #68] + cmp r2, #0 + ldrne r3, [sp, #68] + add lr, lr, #1 + ldrneh r3, [r3, #0] + add r5, r5, #2 + strneh r3, [r8, #0] @ movhi + cmp r9, lr + mov ip, r0, asr #8 + add r8, r8, #2 + str r5, [sp, #68] + bgt .L18844 + b .L18819 +.L19642: + rsb r0, r8, lr + rsb lr, r0, fp + cmp lr, #0 + ble .L18819 + ldr r1, [sp, #24] + add r3, r8, fp + cmp r1, r3 + bhi .L19387 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r8, r7, r3, asl #6 + bne .L19389 + ldr r7, [sp, #124] + ldr r5, [sp, #104] +.L19391: + movs r4, r7, lsr #3 + beq .L19449 + ldr r0, [sp, #68] + mov r1, r5 + mov ip, r8 + mov lr, #0 +.L19451: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L19452 + tst r2, #255 + ldrneh r3, [r0, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #4] + mov r3, r2, lsr #16 + strneh r6, [r1, #4] @ movhi + tst r3, #255 + ldrneh r3, [r0, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #0] + strneh r6, [r1, #0] @ movhi +.L19452: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19461 + tst r2, #255 + ldrneh r3, [r0, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #12] + mov r3, r2, lsr #16 + strneh r6, [r1, #12] @ movhi + tst r3, #255 + ldrneh r3, [r0, #10] + strneh r3, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #8] + strneh r6, [r1, #8] @ movhi +.L19461: + add lr, lr, #1 + cmp lr, r4 + sub ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L19451 + ldr ip, [sp, #68] + mov r3, r4, asl #4 + rsb r2, r4, r4, asl #26 + add ip, ip, r3 + add r5, r5, r3 + add r8, r8, r2, asl #6 + str ip, [sp, #68] +.L19449: + ands ip, r7, #7 + beq .L18819 + cmp ip, #3 + ldrls r2, [r8, #4] + bls .L19484 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L19474 + tst r2, #255 + ldrne lr, [sp, #68] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #6] + strneh lr, [r5, #6] @ movhi + tst r3, #255 + ldrne r0, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #4] + strneh r0, [r5, #4] @ movhi + tst r3, #255 + ldrne r1, [sp, #68] + ldrneh r1, [r1, #2] + strneh r1, [r5, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r2, [sp, #68] + ldrneh r2, [r2, #0] + strneh r2, [r5, #0] @ movhi +.L19474: + subs ip, ip, #4 + ldr r2, [r8, #0] + beq .L18819 + ldr r3, [sp, #68] + add r5, r5, #8 + add r3, r3, #8 + str r3, [sp, #68] +.L19484: + mov r1, #0 +.L19485: + movs r4, r2, lsr #24 + ldrne r6, [sp, #68] + mov r0, r1, asl #1 + ldrneh r6, [r0, r6] + add r1, r1, #1 + strneh r6, [r0, r5] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L19485 + b .L18819 +.L18985: + cmp fp, #0 + add r3, fp, #7 + movge r3, fp + movs r3, r3, asr #3 + beq .L18819 + ldr r6, [sp, #20] + mov r2, #0 + add r1, r6, r8, asl #1 + b .L19015 +.L19646: + ldr ip, [sp, #68] + add r0, r0, #32 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #68] +.L19015: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L19016 + tst ip, #15 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #0] + strneh lr, [r1, #0] @ movhi + tst ip, #240 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst ip, #3840 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + tst ip, #61440 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi + tst ip, #983040 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #8] + strneh lr, [r1, #8] @ movhi + tst ip, #15728640 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst ip, #251658240 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs ip, ip, lsr #28 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L19016: + add r2, r2, #1 + cmp r3, r2 + bne .L19646 + b .L18819 +.L19115: + cmp fp, #0 + add r3, fp, #7 + movge r3, fp + movs r3, r3, asr #3 + beq .L18819 + ldr ip, [sp, #20] + add r1, ip, r8, asl #1 + mov ip, #0 + b .L19145 +.L19647: + ldr lr, [sp, #68] + sub r0, r0, #32 + add lr, lr, #16 + add r1, r1, #16 + str lr, [sp, #68] +.L19145: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L19146 + tst r2, #15 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #14] + strneh lr, [r1, #14] @ movhi + tst r2, #240 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r2, #3840 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + tst r2, #61440 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi + tst r2, #983040 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #6] + strneh lr, [r1, #6] @ movhi + tst r2, #15728640 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r2, #251658240 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #28 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L19146: + add ip, ip, #1 + cmp r3, ip + bne .L19647 + b .L18819 +.L19540: + cmp fp, #0 + add r3, fp, #7 + movge r3, fp + movs lr, r3, asr #3 + beq .L18819 + ldr r2, [sp, #20] + ldr r3, .L19654+32 + add r1, r2, r8, asl #1 + add r0, r0, r3 + mov r2, #0 + b .L19584 +.L19648: + ldr ip, [sp, #68] + sub r7, r7, #64 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #68] +.L19584: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L19585 + tst ip, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L19585: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L19594 + tst ip, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #14] + strneh r3, [r1, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi +.L19594: + add r2, r2, #1 + cmp lr, r2 + sub r0, r0, #64 + bne .L19648 + b .L18819 +.L19320: + cmp fp, #0 + add r3, fp, #7 + movge r3, fp + movs r4, r3, asr #3 + beq .L18819 + ldr r3, [sp, #20] + mov lr, #0 + add r1, r3, r8, asl #1 + ldr r3, .L19654+36 + add r0, r0, r3 + b .L19364 +.L19649: + ldr ip, [sp, #68] + add r2, r2, #64 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #68] +.L19364: + ldr ip, [r2, #0] + cmp ip, #0 + beq .L19365 + tst ip, #255 + ldrne r5, [sp, #68] + mov r3, ip, lsr #8 + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi + tst r3, #255 + ldrne r6, [sp, #68] + mov r3, ip, lsr #16 + ldrneh r6, [r6, #2] + strneh r6, [r1, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + movs ip, ip, lsr #24 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #6] + strneh r5, [r1, #6] @ movhi +.L19365: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L19374 + tst ip, #255 + ldrne r6, [sp, #68] + mov r3, ip, lsr #8 + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #10] + strneh r3, [r1, #10] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L19374: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #64 + bne .L19649 + b .L18819 +.L19167: + ands r1, r0, #7 + mov r3, r0, lsr #3 + add ip, r2, r3, asl #6 + ldreq r1, [sp, #104] + beq .L19271 + cmp r1, #3 + rsb r0, r1, #8 + bls .L19272 + cmp r0, #0 + ldr r2, [ip, #4] + ldreq r1, [sp, #104] + beq .L19276 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r3, r2, lsr r3 + mov r1, #0 +.L19277: + tst r3, #255 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, lsr #8 + bne .L19277 + ldr r6, [sp, #68] + mov r3, r0, asl #1 + ldr r0, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r1, r0, r3 +.L19276: + add ip, ip, #64 +.L19271: + movs lr, lr, lsr #3 + beq .L18819 + mov r0, #0 + b .L19300 +.L19650: + ldr r2, [sp, #68] + add ip, ip, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #68] +.L19300: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19301 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L19301: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L19310 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L19310: + add r0, r0, #1 + cmp r0, lr + bne .L19650 + b .L18819 +.L19037: + mov r3, ip, lsr #3 + ands r2, ip, #7 + sub r0, r0, r3, asl #5 + ldreq r3, [sp, #104] + beq .L19086 + rsbs r4, r2, #8 + ldr ip, [r0, #0] + ldreq r3, [sp, #104] + beq .L19089 + mov r3, r2, asl #2 + mov r3, ip, asl r3 + mov lr, #0 +.L19090: + movs ip, r3, lsr #28 + ldrne r2, [sp, #68] + mov ip, lr, asl #1 + ldrneh r5, [ip, r2] + ldrne r2, [sp, #104] + add lr, lr, #1 + strneh r5, [ip, r2] @ movhi + cmp lr, r4 + mov r3, r3, asl #4 + bne .L19090 + ldr r6, [sp, #68] + mov r3, r4, asl #1 + ldr ip, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r3, ip, r3 +.L19089: + sub r0, r0, #32 +.L19086: + movs r1, r1, lsr #3 + beq .L18819 + mov r2, #0 + b .L19096 +.L19651: + ldr ip, [sp, #68] + sub r0, r0, #32 + add ip, ip, #16 + add r3, r3, #16 + str ip, [sp, #68] +.L19096: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L19097 + tst ip, #15 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #14] + strneh lr, [r3, #14] @ movhi + tst ip, #240 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #12] + strneh r4, [r3, #12] @ movhi + tst ip, #3840 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #10] + strneh r5, [r3, #10] @ movhi + tst ip, #61440 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #8] + strneh r6, [r3, #8] @ movhi + tst ip, #983040 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #6] + strneh lr, [r3, #6] @ movhi + tst ip, #15728640 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #4] + strneh r4, [r3, #4] @ movhi + tst ip, #251658240 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r3, #2] @ movhi + movs ip, ip, lsr #28 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #0] + strneh r6, [r3, #0] @ movhi +.L19097: + add r2, r2, #1 + cmp r2, r1 + bne .L19651 + b .L18819 +.L18907: + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + ldreq r3, [sp, #104] + add ip, r0, r1 + beq .L18956 + rsbs r4, r3, #8 + ldr r0, [r0, r1] + ldreq r3, [sp, #104] + beq .L18959 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L18960: + tst r0, #15 + ldrne r1, [sp, #68] + mov r3, r2, asl #1 + ldrneh r5, [r3, r1] + ldrne r1, [sp, #104] + add r2, r2, #1 + strneh r5, [r3, r1] @ movhi + cmp r4, r2 + mov r0, r0, lsr #4 + bne .L18960 + ldr r6, [sp, #68] + mov r3, r4, asl #1 + ldr r0, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r3, r0, r3 +.L18959: + add ip, ip, #32 +.L18956: + movs r0, lr, lsr #3 + beq .L18819 + mov r1, #0 + b .L18966 +.L19652: + ldr r2, [sp, #68] + add ip, ip, #32 + add r2, r2, #16 + add r3, r3, #16 + str r2, [sp, #68] +.L18966: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L18967 + tst r2, #15 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #0] + strneh r4, [r3, #0] @ movhi + tst r2, #240 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r3, #2] @ movhi + tst r2, #3840 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #4] + strneh r6, [r3, #4] @ movhi + tst r2, #61440 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #6] + strneh lr, [r3, #6] @ movhi + tst r2, #983040 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #8] + strneh r4, [r3, #8] @ movhi + tst r2, #15728640 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #10] + strneh r5, [r3, #10] @ movhi + tst r2, #251658240 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #12] + strneh r6, [r3, #12] @ movhi + movs r2, r2, lsr #28 + ldrne lr, [sp, #68] + ldrneh lr, [lr, #14] + strneh lr, [r3, #14] @ movhi +.L18967: + add r1, r1, #1 + cmp r1, r0 + bne .L19652 + b .L18819 +.L19387: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub ip, r7, r3, asl #6 + ldreq r1, [sp, #104] + beq .L19491 + cmp r2, #3 + rsb r0, r2, #8 + bls .L19492 + cmp r0, #0 + ldr r1, [ip, #0] + ldreq r1, [sp, #104] + beq .L19496 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L19497: + movs r2, r3, lsr #24 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, asl #8 + bne .L19497 + ldr r6, [sp, #68] + mov r3, r0, asl #1 + ldr r0, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r1, r0, r3 +.L19496: + sub ip, ip, #64 +.L19491: + movs lr, lr, lsr #3 + beq .L18819 + mov r0, #0 + b .L19520 +.L19653: + ldr r2, [sp, #68] + sub ip, ip, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #68] +.L19520: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L19521 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L19521: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19530 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi +.L19530: + add r0, r0, #1 + cmp r0, lr + bne .L19653 + b .L18819 +.L18909: + ldr lr, [sp, #124] + rsb ip, r3, #8 + cmp lr, ip + bge .L18912 + cmp lr, #0 + ble .L18819 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L18916: + tst r0, #15 + ldrne r1, [sp, #68] + mov r3, r2, asl #1 + ldrneh r4, [r3, r1] + ldr r5, [sp, #124] + ldrne r1, [sp, #104] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r5, r2 + mov r0, r0, lsr #4 + bne .L18916 + b .L18819 +.L19389: + ldr r2, [sp, #124] + rsb lr, ip, #8 + cmp r2, lr + bge .L19392 + cmp r2, #0 + ble .L18819 + cmp ip, #3 + bls .L19395 + ldr r2, [r8, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L19398: + movs r3, r2, lsr #24 + ldrne r4, [sp, #68] + mov r3, r1, asl #1 + ldrneh r5, [r3, r4] + ldr r6, [sp, #124] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r3, r4] @ movhi + cmp r6, r1 + mov r2, r2, asl #8 + bne .L19398 + b .L18819 +.L19169: + ldr r5, [sp, #124] + rsb lr, ip, #8 + cmp r5, lr + bge .L19172 + cmp r5, #0 + ble .L18819 + cmp ip, #3 + bls .L19175 + ldr r2, [r8, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L19178: + tst r1, #255 + ldrne r6, [sp, #68] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #124] + ldrne r6, [sp, #104] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r1, r1, lsr #8 + bne .L19178 + b .L18819 +.L19039: + ldr r3, [sp, #124] + rsb lr, r4, #8 + cmp r3, lr + bge .L19042 + cmp r3, #0 + ble .L18819 + ldr r2, [r0, #0] + mov r3, r4, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L19046: + movs r4, r0, lsr #28 + ldrne r5, [sp, #68] + mov r3, r2, asl #1 + ldrneh r6, [r3, r5] + ldr ip, [sp, #124] + ldrne r5, [sp, #104] + add r2, r2, #1 + strneh r6, [r3, r5] @ movhi + cmp ip, r2 + mov r0, r0, asl #4 + bne .L19046 + b .L18819 +.L19172: + cmp ip, #3 + bls .L19202 + cmp lr, #0 + ldr r2, [r8, #4] + ldreq r5, [sp, #104] + beq .L19206 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L19207: + tst r1, #255 + ldrne r0, [sp, #68] + mov r3, r2, asl #1 + ldrneh r4, [r3, r0] + ldrne r0, [sp, #104] + add r2, r2, #1 + strneh r4, [r3, r0] @ movhi + cmp lr, r2 + mov r1, r1, lsr #8 + bne .L19207 + ldr r5, [sp, #68] + mov r3, lr, asl #1 + ldr r6, [sp, #104] + add r5, r5, r3 + str r5, [sp, #68] + add r5, r3, r6 +.L19206: + ldr ip, [sp, #124] + add r8, r8, #64 + rsb r7, lr, ip + b .L19171 +.L19272: + subs r4, r0, #4 + ldr r2, [ip, #0] + ldreq r1, [sp, #104] + beq .L19284 + mov r3, r1, asl #3 + mov r3, r2, lsr r3 + mov r1, #0 +.L19285: + tst r3, #255 + ldrne r5, [sp, #68] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r5, [sp, #104] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp r1, r4 + mov r3, r3, lsr #8 + bne .L19285 + mov r3, r0, asl #1 + ldr r0, [sp, #68] + ldr r1, [sp, #104] + add r2, r0, r3 + sub r2, r2, #8 + add r3, r1, r3 + str r2, [sp, #68] + sub r1, r3, #8 +.L19284: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L19290 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L19290: + ldr r0, [sp, #68] + add r1, r1, #8 + add r0, r0, #8 + add ip, ip, #64 + str r0, [sp, #68] + b .L19271 +.L18912: + cmp ip, #0 + ldr r2, [r4, #0] + ldreq r5, [sp, #104] + beq .L18922 + mov r3, r3, asl #2 + mov r3, r2, lsr r3 + mov r1, #0 +.L18923: + tst r3, #15 + ldrne r6, [sp, #68] + mov r2, r1, asl #1 + ldrneh lr, [r2, r6] + ldrne r6, [sp, #104] + add r1, r1, #1 + strneh lr, [r2, r6] @ movhi + cmp ip, r1 + mov r3, r3, lsr #4 + bne .L18923 + ldr r0, [sp, #68] + mov r3, ip, asl #1 + ldr r1, [sp, #104] + add r0, r0, r3 + str r0, [sp, #68] + add r5, r3, r1 +.L18922: + ldr r2, [sp, #124] + add r4, r4, #32 + rsb r7, ip, r2 + b .L18911 +.L19042: + cmp lr, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #104] + beq .L19052 + mov r3, r4, asl #2 + mov r3, r2, asl r3 + mov ip, #0 +.L19053: + movs r1, r3, lsr #28 + ldrne r4, [sp, #68] + mov r2, ip, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add ip, ip, #1 + strneh r5, [r2, r4] @ movhi + cmp lr, ip + mov r3, r3, asl #4 + bne .L19053 + ldr r6, [sp, #68] + mov r3, lr, asl #1 + ldr ip, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r1, r3, ip +.L19052: + ldr r2, [sp, #124] + sub r0, r0, #32 + rsb r7, lr, r2 + b .L19041 +.L19492: + subs r4, r0, #4 + ldr r1, [ip, #4] + ldreq r1, [sp, #104] + beq .L19504 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L19505: + movs r2, r3, lsr #24 + ldrne r5, [sp, #68] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r5, [sp, #104] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp r1, r4 + mov r3, r3, asl #8 + bne .L19505 + mov r3, r0, asl #1 + ldr r0, [sp, #68] + ldr r1, [sp, #104] + add r2, r0, r3 + sub r2, r2, #8 + add r3, r1, r3 + str r2, [sp, #68] + sub r1, r3, #8 +.L19504: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19510 + tst r2, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #68] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L19510: + ldr r0, [sp, #68] + add r1, r1, #8 + add r0, r0, #8 + sub ip, ip, #64 + str r0, [sp, #68] + b .L19491 +.L19392: + cmp ip, #3 + bls .L19422 + cmp lr, #0 + ldr r2, [r8, #0] + ldreq r5, [sp, #104] + beq .L19426 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L19427: + movs r0, r3, lsr #24 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp lr, r1 + mov r3, r3, asl #8 + bne .L19427 + ldr r6, [sp, #68] + mov r3, lr, asl #1 + ldr ip, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r5, ip, r3 +.L19426: + ldr ip, [sp, #124] + sub r8, r8, #64 + rsb r7, lr, ip + b .L19391 +.L19638: + mov r7, #0 + b .L18889 +.L19634: + mov r7, #0 + b .L18854 +.L19202: + subs r0, lr, #4 + ldr r2, [r8, #0] + ldreq r1, [sp, #104] + beq .L19214 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L19215: + tst r1, #255 + ldrne ip, [sp, #68] + mov r3, r2, asl #1 + ldrneh r4, [r3, ip] + ldrne ip, [sp, #104] + add r2, r2, #1 + strneh r4, [r3, ip] @ movhi + cmp r2, r0 + mov r1, r1, lsr #8 + bne .L19215 + ldr r5, [sp, #68] + mov r3, lr, asl #1 + ldr r6, [sp, #104] + add r2, r5, r3 + sub r2, r2, #8 + add r3, r6, r3 + str r2, [sp, #68] + sub r1, r3, #8 +.L19214: + ldr r2, [r8, #4] + cmp r2, #0 + beq .L19220 + tst r2, #255 + ldrne ip, [sp, #68] + mov r3, r2, lsr #8 + ldrneh ip, [ip, #0] + strneh ip, [r1, #0] @ movhi + tst r3, #255 + ldrne r0, [sp, #68] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #2] + strneh r0, [r1, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #6] + strneh r4, [r1, #6] @ movhi +.L19220: + ldr r6, [sp, #68] + add r5, r1, #8 + add r6, r6, #8 + str r6, [sp, #68] + b .L19206 +.L19422: + subs r0, lr, #4 + ldr r2, [r8, #4] + ldreq r1, [sp, #104] + beq .L19434 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L19435: + movs r2, r3, lsr #24 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, asl #8 + bne .L19435 + ldr r6, [sp, #68] + mov r3, lr, asl #1 + ldr ip, [sp, #104] + add r2, r6, r3 + sub r2, r2, #8 + add r3, ip, r3 + str r2, [sp, #68] + sub r1, r3, #8 +.L19434: + ldr r2, [r8, #0] + cmp r2, #0 + beq .L19440 + tst r2, #255 + ldrne r0, [sp, #68] + mov r3, r2, lsr #8 + ldrneh r0, [r0, #6] + strneh r0, [r1, #6] @ movhi + tst r3, #255 + ldrne r3, [sp, #68] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + tst r3, #255 + ldrne r4, [sp, #68] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r5, [sp, #68] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L19440: + ldr r6, [sp, #68] + add r5, r1, #8 + add r6, r6, #8 + str r6, [sp, #68] + b .L19426 +.L19641: + mov r1, r9 + b .L19620 +.L19640: + mov lr, r6 + b .L19618 +.L19175: + ldr r0, [sp, #124] + ldr r3, [r8, #0] + add r2, r0, ip + mov r1, ip, asl #3 + cmp r2, #4 + mov r3, r3, lsr r1 + bhi .L19182 + cmp r0, #0 + movne r1, #0 + beq .L18819 +.L19198: + tst r3, #255 + ldrne r5, [sp, #68] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldr ip, [sp, #124] + ldrne r5, [sp, #104] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L19198 + b .L18819 +.L19395: + ldr lr, [sp, #124] + mov r3, ip, asl #3 + ldr r1, [r8, #4] + add r2, lr, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L19402 + cmp lr, #0 + movne r2, #0 + beq .L18819 +.L19418: + movs r5, r1, lsr #24 + ldrne r6, [sp, #68] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #124] + ldrne r6, [sp, #104] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r1, r1, asl #8 + bne .L19418 + b .L18819 +.L19182: + rsbs r0, ip, #4 + ldreq ip, [sp, #104] + beq .L19187 + mov r1, #0 +.L19188: + tst r3, #255 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #104] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L19188 + ldr r6, [sp, #68] + mov r3, r0, asl #1 + ldr lr, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add ip, r3, lr +.L19187: + ldr r1, [sp, #124] + ldr r3, [r8, #4] + subs r0, r1, r0 + beq .L18819 + mov r1, #0 +.L19194: + tst r3, #255 + ldrne r4, [sp, #68] + mov r2, r1, asl #1 + ldrneh r4, [r2, r4] + add r1, r1, #1 + strneh r4, [r2, ip] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L19194 + b .L18819 +.L19402: + rsbs r0, ip, #4 + ldreq r3, [sp, #104] + beq .L19407 + mov r2, #0 +.L19408: + movs r3, r1, lsr #24 + ldrne r4, [sp, #68] + mov r3, r2, asl #1 + ldrneh r5, [r3, r4] + ldrne r4, [sp, #104] + add r2, r2, #1 + strneh r5, [r3, r4] @ movhi + cmp r2, r0 + mov r1, r1, asl #8 + bne .L19408 + ldr r6, [sp, #68] + mov r3, r0, asl #1 + ldr ip, [sp, #104] + add r6, r6, r3 + str r6, [sp, #68] + add r3, r3, ip +.L19407: + ldr lr, [sp, #124] + ldr r2, [r8, #0] + subs ip, lr, r0 + beq .L18819 + mov r0, #0 +.L19414: + movs r1, r2, lsr #24 + ldrne r4, [sp, #68] + mov r1, r0, asl #1 + ldrneh r4, [r1, r4] + add r0, r0, #1 + strneh r4, [r1, r3] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L19414 + b .L18819 + .size render_scanline_obj_copy_tile_2D, .-render_scanline_obj_copy_tile_2D + .align 2 + .global render_scanline_obj_copy_tile_1D + .type render_scanline_obj_copy_tile_1D, %function +render_scanline_obj_copy_tile_1D: + @ args = 0, pretend = 0, frame = 592 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r5, .L20498 + add r0, r0, r0, asl #2 + ldrh r4, [r5, #6] + ldr ip, .L20498+4 + add r0, r4, r0, asl #5 + ldrh r6, [r5, #0] + sub sp, sp, #604 + ldr ip, [ip, r0, asl #2] + str r6, [sp, #44] + str ip, [sp, #68] + cmp ip, #0 + ldr ip, [sp, #44] + ldrh r6, [r5, #74] + str r4, [sp, #64] + ldr lr, .L20498+8 + and r4, ip, #7 + ldr ip, .L20498+12 + ldrh r5, [r5, #80] + add r4, ip, r4, asl #7 + add r0, lr, r0, asl #7 + mov r6, r6, lsr #8 + str r4, [sp, #52] + str r0, [sp, #72] + str r1, [sp, #20] + str r2, [sp, #16] + str r3, [sp, #12] + str r6, [sp, #48] + str r5, [sp, #40] + beq .L20448 + rsb r0, r1, r2 + add lr, r3, r1, asl #1 + mov r1, #0 + mov r2, r1 + str lr, [sp, #100] + str r0, [sp, #120] + str r1, [sp, #60] + b .L19659 +.L19663: + ldr lr, [sp, #60] + ldr r0, [sp, #68] + add lr, lr, #1 + cmp r0, lr + str lr, [sp, #60] + beq .L20448 + ldr r2, [sp, #60] +.L19659: + ldr r4, [sp, #72] + ldr r5, .L20498+16 + ldrb r3, [r2, r4] @ zero_extendqisi2 + ldr lr, .L20498+20 + mov r3, r3, asl #3 + ldrh r6, [r3, r5] + add r3, r3, r5 + ldrh r7, [r3, #2] + mov fp, r6, lsr #12 + and r2, fp, #12 + orr sl, r2, r7, lsr #14 + mov r1, r7, asl #23 + ldr r9, [lr, sl, asl #2] + ands ip, r6, #512 + mov r8, r1, asr #23 + ldr r0, [sp, #16] + ldr r5, [sp, #20] + addne r1, r8, r9, asl #1 + addeq r1, r8, r9 + ldrh r3, [r3, #4] + ldr r2, [sp, #20] + cmp r8, r5 + movcs r5, r8 + cmp r1, r0 + movcs r1, r0 + str r3, [sp, #24] + cmp r0, r5 + movls r3, #0 + movhi r3, #1 + cmp r2, r1 + movcs r3, #0 + cmp r3, #0 + str ip, [sp, #28] + beq .L19663 + ldr ip, [sp, #44] + add r4, sp, #124 + str ip, [sp, #0] + ldr lr, [sp, #40] + ldr ip, [sp, #52] + mov r0, r5 + ldr r3, [sp, #48] + mov r2, r4 + str lr, [sp, #4] + str ip, [sp, #8] + bl render_scanline_conditional_tile + and r0, r6, #255 + cmp r0, #160 + ldr r3, .L20498+24 + add r5, r4, r5, asl #1 + subgt r0, r0, #256 + tst r6, #256 + str r5, [sp, #56] + ldr sl, [r3, sl, asl #2] + beq .L19667 + tst r6, #8192 + beq .L19669 + mov r3, r7, lsr #4 + ldr r1, .L20498+16 + ldr lr, [sp, #28] + and r3, r3, #992 + add r3, r3, r1 + add r1, sl, sl, lsr #31 + cmp lr, #0 + ldrh r4, [r3, #30] + mov lr, r1, asr #1 + add r2, r9, r9, lsr #31 + ldr r1, [sp, #20] + mov ip, r2, asr #1 + str r4, [sp, #32] + moveq fp, r9 + moveq r5, ip + moveq r4, lr + movne fp, r9, asl #1 + movne r5, ip, asl #1 + movne r4, lr, asl #1 + cmp r8, r1 + ldrh r7, [r3, #6] + ldrh r2, [r3, #14] + ldrh r6, [r3, #22] + bge .L19674 + rsb r1, r8, r1 + rsb fp, r1, fp + cmp fp, #0 + ble .L19663 + ldr r8, [sp, #20] + rsb r5, r1, r5 +.L19674: + ldr r1, [sp, #16] + add r3, r8, fp + cmp r3, r1 + bge .L20476 +.L19677: + add r0, r0, r4 + ldr r4, [sp, #32] + mov ip, ip, asl #8 + mov r1, r4, asl #16 + mov r3, r7, asl #16 + mov r4, r1, asr #16 + str ip, [sp, #108] + ldr r1, [sp, #64] + mov ip, lr, asl #8 + ldr lr, [sp, #12] + mov r2, r2, asl #16 + mov r3, r3, asr #16 + cmp r6, #0 + add r8, lr, r8, asl #1 + str r3, [sp, #76] + mov r7, r2, asr #16 + rsb lr, r0, r1 + beq .L20477 + ldr r0, [sp, #24] + cmp r9, #0 + add r1, r9, #7 + mov r2, r0, asl #22 + movge r1, r9 + ldr r3, .L20498+28 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp fp, #0 + str r2, [sp, #116] + str r1, [sp, #80] + ble .L19663 + mov r3, r6, asl #16 + mov r6, r3, asr #16 + ldr r0, [sp, #76] + mul r2, lr, r4 + mul r1, r6, r5 + mul r3, lr, r7 + mul r0, r5, r0 + rsb r2, r1, r2 + ldr r1, [sp, #108] + rsb r3, r0, r3 + add r5, r1, r3 + add r4, ip, r2 + mov lr, r5, asr #8 + mov ip, r4, asr #8 + cmp lr, r9 + cmpcc ip, sl + movcs r3, #0 + movcc r3, #1 + movcs r7, r3 + bcc .L20478 +.L19695: + ldr r3, [sp, #56] + ldr r2, [sp, #76] + add r7, r7, #1 + add r5, r5, r2 + add r4, r4, r6 + add r3, r3, #2 + cmp fp, r7 + mov lr, r5, asr #8 + mov ip, r4, asr #8 + add r8, r8, #2 + str r3, [sp, #56] + beq .L19663 + cmp lr, r9 + cmpcc ip, sl + bcs .L19695 + cmp ip, sl + cmpcc lr, r9 + bcs .L19663 +.L20479: + ldr r0, [sp, #76] + and r3, ip, #7 + mov r2, lr, asr #3 + ldr r1, [sp, #116] + mov r3, r3, asl #3 + add r5, r5, r0 + add r3, r3, r2, asl #6 + ldr r0, [sp, #80] + mov r2, ip, asr #3 + add r3, r3, r1 + mla r0, r2, r0, r3 + and r1, lr, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + add r7, r7, #1 + cmp r3, #0 + ldrne r2, [sp, #56] + ldr r3, [sp, #56] + ldrneh r2, [r2, #0] + add r4, r4, r6 + strneh r2, [r8, #0] @ movhi + add r3, r3, #2 + cmp fp, r7 + mov ip, r4, asr #8 + mov lr, r5, asr #8 + add r8, r8, #2 + str r3, [sp, #56] + ble .L19663 +.L19698: + cmp ip, sl + cmpcc lr, r9 + bcc .L20479 + b .L19663 +.L19667: + ldr lr, [sp, #64] + tst r7, #8192 + rsb ip, r0, lr + rsbne r3, ip, sl + subne ip, r3, #1 + mov r2, r7, asl #19 + and r3, fp, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L19663 + .p2align 2 +.L19747: + .word .L19743 + .word .L19744 + .word .L19745 + .word .L19746 +.L20448: + add sp, sp, #604 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L19669: + ldr r5, .L20498+16 + mov r3, r7, lsr #4 + and r3, r3, #992 + add r3, r3, r5 + ldr r4, [sp, #28] + add r1, sl, sl, lsr #31 + ldrh r6, [r3, #30] + mov lr, r1, asr #1 + add r2, r9, r9, lsr #31 + ldr r1, [sp, #20] + cmp r4, #0 + mov ip, r2, asr #1 + str r6, [sp, #36] + moveq r5, ip + moveq r6, r9 + moveq r4, lr + movne r6, r9, asl #1 + movne r5, ip, asl #1 + movne r4, lr, asl #1 + cmp r8, r1 + ldrh r7, [r3, #6] + ldrh r2, [r3, #14] + ldrh fp, [r3, #22] + bge .L19706 + rsb r1, r8, r1 + rsb r6, r1, r6 + cmp r6, #0 + ble .L19663 + ldr r8, [sp, #20] + rsb r5, r1, r5 +.L19706: + ldr r1, [sp, #16] + add r3, r8, r6 + cmp r3, r1 + bge .L20480 +.L19709: + add r0, r0, r4 + ldr r4, [sp, #36] + mov ip, ip, asl #8 + mov r1, r4, asl #16 + mov r3, r7, asl #16 + mov r2, r2, asl #16 + mov r4, r1, asr #16 + str ip, [sp, #104] + ldr r1, [sp, #64] + mov ip, lr, asl #8 + ldr lr, [sp, #12] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + cmp fp, #0 + add r8, lr, r8, asl #1 + str r3, [sp, #84] + str r2, [sp, #88] + rsb lr, r0, r1 + beq .L20481 + ldr r0, [sp, #24] + cmp r9, #0 + add r1, r9, #7 + mov r2, r0, asl #22 + movge r1, r9 + ldr r3, .L20498+28 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp r6, #0 + str r2, [sp, #112] + str r1, [sp, #96] + ble .L19663 + mov r3, fp, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #92] + ldr r1, [sp, #92] + ldr r3, [sp, #88] + ldr r0, [sp, #84] + mul r2, lr, r4 + mul r1, r5, r1 + mul r3, lr, r3 + mul r0, r5, r0 + rsb r2, r1, r2 + ldr r1, [sp, #104] + rsb r3, r0, r3 + add r5, r1, r3 + add r4, ip, r2 + mov lr, r5, asr #8 + mov r3, r4, asr #8 + cmp lr, r9 + cmpcc r3, sl + movcs r2, #0 + movcc r2, #1 + movcs r7, r2 + bcc .L20482 +.L19730: + ldr r3, [sp, #92] + ldr ip, [sp, #56] + ldr r2, [sp, #84] + add r7, r7, #1 + add r5, r5, r2 + add r4, r4, r3 + add ip, ip, #2 + cmp r6, r7 + mov lr, r5, asr #8 + mov r3, r4, asr #8 + add r8, r8, #2 + str ip, [sp, #56] + beq .L19663 + cmp lr, r9 + cmpcc r3, sl + bcs .L19730 + cmp r3, sl + cmpcc lr, r9 + bcs .L19663 +.L20483: + ldr r1, [sp, #112] + and r0, r3, #7 + ldr r2, [sp, #96] + add r0, r1, r0, asl #2 + and r1, r3, #7 + mov r3, r3, asr #3 + mov ip, lr, asr #1 + mul r2, r3, r2 + and fp, ip, #3 + ldr ip, [sp, #112] + mov r3, lr, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, lr, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst lr, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, fp] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + cmp r0, #0 + ldrne r2, [sp, #56] + ldr lr, [sp, #84] + ldrneh r2, [r2, #0] + ldr ip, [sp, #56] + ldr r1, [sp, #92] + add r7, r7, #1 + strneh r2, [r8, #0] @ movhi + add r5, r5, lr + add r4, r4, r1 + add ip, ip, #2 + cmp r6, r7 + mov lr, r5, asr #8 + mov r3, r4, asr #8 + add r8, r8, #2 + str ip, [sp, #56] + ble .L19663 +.L19733: + cmp r3, sl + cmpcc lr, r9 + bcc .L20483 + b .L19663 +.L20480: + rsb r6, r8, r1 + cmp r6, #0 + bgt .L19709 + b .L19663 +.L20476: + rsb fp, r8, r1 + cmp fp, #0 + bgt .L19677 + b .L19663 +.L20477: + mla r3, lr, r4, ip + mov r0, r3, asr #8 + cmp r0, sl + bcs .L19663 + cmp r9, #0 + ldr r4, [sp, #24] + add r3, r9, #7 + movge r3, r9 + mov r2, r4, asl #22 + mov r3, r3, asr #3 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L20498+28 + add r0, r0, ip, asl #2 + cmp fp, #0 + add r4, r3, r0, asl #3 + ble .L19663 + ldr r2, [sp, #76] + mul r3, lr, r7 + mul r2, r5, r2 + ldr r5, [sp, #108] + rsb r3, r2, r3 + add r0, r5, r3 + mov ip, r0, asr #8 + cmp ip, r9 + movcs lr, r6 + bcc .L20484 +.L19685: + ldr r1, [sp, #56] + ldr r6, [sp, #76] + add lr, lr, #1 + add r0, r0, r6 + add r1, r1, #2 + cmp fp, lr + mov ip, r0, asr #8 + add r8, r8, #2 + str r1, [sp, #56] + beq .L19663 + cmp ip, r9 + bcs .L19685 + b .L20462 +.L20481: + mla r3, lr, r4, ip + mov r0, r3, asr #8 + cmp r0, sl + bcs .L19663 + ldr r4, [sp, #24] + cmp r9, #0 + add r3, r9, #7 + mov r2, r4, asl #22 + movge r3, r9 + mov r3, r3, asr #3 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L20498+28 + add r0, r0, ip, asl #3 + cmp r6, #0 + add r7, r3, r0, asl #2 + ble .L19663 + ldr r3, [sp, #88] + ldr r2, [sp, #84] + mul r3, lr, r3 + mul r2, r5, r2 + ldr r5, [sp, #104] + rsb r3, r2, r3 + add r0, r5, r3 + mov ip, r0, asr #8 + cmp ip, r9 + movcs r1, fp + bcc .L20485 +.L19717: + ldr ip, [sp, #84] + ldr lr, [sp, #56] + add r1, r1, #1 + add r0, r0, ip + add lr, lr, #2 + cmp r6, r1 + mov ip, r0, asr #8 + add r8, r8, #2 + str lr, [sp, #56] + beq .L19663 + cmp ip, r9 + bcs .L19717 + b .L20464 +.L19746: + cmp r9, #0 + add r2, r9, #7 + movge r2, r9 + subs r3, r9, #8 + submi r3, r9, #1 + mov lr, r2, asr #3 + mov r3, r3, asr #3 + mov r1, ip, lsr #3 + mla r0, lr, r1, r3 + ldr r1, [sp, #24] + and r3, ip, #7 + mov r2, r1, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + add r3, r3, r2, asl #2 + ldr r2, [sp, #20] + mov r0, r3, asl #3 + ldr r3, .L20498+28 + cmp r8, r2 + add r7, r0, r3 + blt .L20486 + ldr r4, [sp, #16] + add r3, r8, r9 + cmp r4, r3 + bhi .L20384 + rsb r9, r8, r4 + cmp r9, #0 + ble .L19663 + ldr r5, [sp, #12] + movs sl, r9, lsr #3 + add r1, r5, r8, asl #1 + beq .L20387 + ldr r3, .L20498+32 + ldr r4, [sp, #56] + add r0, r0, r3 + mov lr, r1 + mov r5, r7 + mov r2, #0 +.L20389: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L20390 + tst ip, #255 + ldrneh r6, [r4, #6] + mov r3, ip, lsr #8 + strneh r6, [lr, #6] @ movhi + tst r3, #255 + ldrneh r3, [r4, #4] + strneh r3, [lr, #4] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrneh r6, [r4, #2] + strneh r6, [lr, #2] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r4, #0] + strneh ip, [lr, #0] @ movhi +.L20390: + ldr ip, [r5, #0] + cmp ip, #0 + beq .L20399 + tst ip, #255 + ldrneh r3, [r4, #14] + strneh r3, [lr, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r6, [r4, #12] + mov r3, ip, lsr #16 + strneh r6, [lr, #12] @ movhi + tst r3, #255 + ldrneh r3, [r4, #10] + strneh r3, [lr, #10] @ movhi + movs ip, ip, lsr #24 + ldrneh r6, [r4, #8] + strneh r6, [lr, #8] @ movhi +.L20399: + add r2, r2, #1 + cmp sl, r2 + sub r5, r5, #64 + add lr, lr, #16 + add r4, r4, #16 + sub r0, r0, #64 + bne .L20389 + ldr ip, [sp, #56] + mov r3, sl, asl #4 + rsb r2, sl, sl, asl #26 + add ip, ip, r3 + add r1, r1, r3 + add r7, r7, r2, asl #6 + str ip, [sp, #56] +.L20387: + ands ip, r9, #7 + beq .L19663 + cmp ip, #3 + ldrls r2, [r7, #4] + bls .L20422 + ldr r2, [r7, #4] + cmp r2, #0 + beq .L20412 + tst r2, #255 + ldrne lr, [sp, #56] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #6] + strneh lr, [r1, #6] @ movhi + tst r3, #255 + ldrne r0, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #4] + strneh r0, [r1, #4] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #0] + strneh r4, [r1, #0] @ movhi +.L20412: + subs ip, ip, #4 + ldr r2, [r7, #0] + beq .L19663 + ldr r5, [sp, #56] + add r1, r1, #8 + add r5, r5, #8 + str r5, [sp, #56] +.L20422: + mov r3, #0 +.L20423: + movs r6, r2, lsr #24 + ldrne lr, [sp, #56] + mov r0, r3, asl #1 + ldrneh lr, [r0, lr] + add r3, r3, #1 + strneh lr, [r0, r1] @ movhi + cmp ip, r3 + mov r2, r2, asl #8 + bhi .L20423 + b .L19663 +.L19743: + ldr r0, [sp, #24] + cmp r9, #0 + add r3, r9, #7 + mov r2, r0, asl #22 + movge r3, r9 + mov lr, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, lr, r3, r2 + ldr r2, [sp, #20] + and r1, ip, #7 + ldr r3, .L20498+28 + add r1, r1, r0, asl #3 + cmp r8, r2 + add r0, r3, r1, asl #2 + blt .L20487 + ldr r4, [sp, #16] + add r3, r8, r9 + cmp r4, r3 + bhi .L19829 + rsb r7, r8, r4 + cmp r7, #0 + ble .L19663 + ldr r6, [sp, #12] + movs r5, r7, lsr #3 + add r1, r6, r8, asl #1 + beq .L19832 + ldr lr, [sp, #56] + mov ip, r1 + mov r4, r0 + mov r2, #0 +.L19834: + ldr r3, [r4, #0] + cmp r3, #0 + beq .L19835 + tst r3, #15 + ldrneh r6, [lr, #0] + strneh r6, [ip, #0] @ movhi + tst r3, #240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + tst r3, #3840 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r3, #61440 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r3, #983040 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r3, #15728640 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r3, #251658240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [lr, #14] + strneh r3, [ip, #14] @ movhi +.L19835: + add r2, r2, #1 + cmp r2, r5 + add r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L19834 + ldr r4, [sp, #56] + mov r3, r5, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r5, asl #5 + str r4, [sp, #56] +.L19832: + ands ip, r7, #7 + beq .L19663 + ldr r0, [r0, #0] + mov r2, #0 +.L19854: + tst r0, #15 + ldrne r5, [sp, #56] + mov r3, r2, asl #1 + ldrneh r5, [r3, r5] + add r2, r2, #1 + strneh r5, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, lsr #4 + bne .L19854 + b .L19663 +.L19744: + ldr lr, [sp, #24] + cmp r9, #0 + add r3, r9, #7 + mov r2, lr, asl #22 + movge r3, r9 + mov lr, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, lr, r1, r2 + subs r3, r9, #8 + submi r3, r9, #1 + add r0, r0, r3, asr #3 + and r2, ip, #7 + add r2, r2, r0, asl #3 + ldr r0, [sp, #20] + ldr r3, .L20498+28 + cmp r8, r0 + add r0, r3, r2, asl #2 + blt .L20488 + ldr r1, [sp, #16] + add r3, r8, r9 + cmp r1, r3 + bhi .L19959 + rsb r7, r8, r1 + cmp r7, #0 + ble .L19663 + ldr r2, [sp, #12] + movs r3, r7, lsr #3 + add r1, r2, r8, asl #1 + beq .L19962 + ldr lr, [sp, #56] + mov ip, r1 + mov r4, r0 + mov r5, #0 +.L19964: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L19965 + tst r2, #15 + ldrneh r6, [lr, #14] + strneh r6, [ip, #14] @ movhi + tst r2, #240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L19965: + add r5, r5, #1 + cmp r5, r3 + sub r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L19964 + ldr r4, [sp, #56] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r4, [sp, #56] +.L19962: + ands ip, r7, #7 + beq .L19663 + ldr r0, [r0, #0] + mov r2, #0 +.L19984: + movs r5, r0, lsr #28 + ldrne r6, [sp, #56] + mov r3, r2, asl #1 + ldrneh r6, [r3, r6] + add r2, r2, #1 + strneh r6, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L19984 + b .L19663 +.L19745: + ldr r4, [sp, #24] + cmp r9, #0 + add r3, r9, #7 + mov r1, r4, asl #22 + movge r3, r9 + mov r2, ip, lsr #3 + mov r4, r3, asr #3 + mov r2, r2, asl #1 + mov r1, r1, lsr #22 + mla r0, r2, r4, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr r5, [sp, #20] + mov r0, r3, asl #3 + ldr r3, .L20498+28 + cmp r8, r5 + add r2, r0, r3 + blt .L20489 + ldr r5, [sp, #16] + add r3, r8, r9 + cmp r5, r3 + bhi .L20164 + rsb r9, r8, r5 + cmp r9, #0 + ble .L19663 + ldr r6, [sp, #12] + movs sl, r9, lsr #3 + add r1, r6, r8, asl #1 + beq .L20167 + ldr r3, .L20498+36 + ldr r4, [sp, #56] + add r0, r0, r3 + mov lr, r1 + mov r5, r2 + mov r7, #0 +.L20169: + ldr ip, [r5, #0] + cmp ip, #0 + beq .L20170 + tst ip, #255 + ldrneh r3, [r4, #0] + strneh r3, [lr, #0] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r6, [r4, #2] + mov r3, ip, lsr #16 + strneh r6, [lr, #2] @ movhi + tst r3, #255 + ldrneh r3, [r4, #4] + strneh r3, [lr, #4] @ movhi + movs ip, ip, lsr #24 + ldrneh r6, [r4, #6] + strneh r6, [lr, #6] @ movhi +.L20170: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L20179 + tst ip, #255 + ldrneh r3, [r4, #8] + strneh r3, [lr, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r6, [r4, #10] + mov r3, ip, lsr #16 + strneh r6, [lr, #10] @ movhi + tst r3, #255 + ldrneh r3, [r4, #12] + strneh r3, [lr, #12] @ movhi + movs ip, ip, lsr #24 + ldrneh r6, [r4, #14] + strneh r6, [lr, #14] @ movhi +.L20179: + add r7, r7, #1 + cmp r7, sl + add r5, r5, #64 + add lr, lr, #16 + add r4, r4, #16 + add r0, r0, #64 + bne .L20169 + ldr ip, [sp, #56] + mov r3, sl, asl #4 + add ip, ip, r3 + add r1, r1, r3 + add r2, r2, sl, asl #6 + str ip, [sp, #56] +.L20167: + ands ip, r9, #7 + beq .L19663 + cmp ip, #3 + ldrls r3, [r2, #0] + bls .L20202 + ldr r0, [r2, #0] + cmp r0, #0 + beq .L20192 + tst r0, #255 + ldrne lr, [sp, #56] + mov r3, r0, lsr #8 + ldrneh lr, [lr, #0] + strneh lr, [r1, #0] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #2] + strneh r3, [r1, #2] @ movhi + mov r3, r0, lsr #16 + tst r3, #255 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + movs r0, r0, lsr #24 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #6] + strneh r5, [r1, #6] @ movhi +.L20192: + subs ip, ip, #4 + ldr r3, [r2, #4] + beq .L19663 + ldr r6, [sp, #56] + add r1, r1, #8 + add r6, r6, #8 + str r6, [sp, #56] +.L20202: + mov r2, #0 +.L20203: + tst r3, #255 + ldrne lr, [sp, #56] + mov r0, r2, asl #1 + ldrneh lr, [r0, lr] + add r2, r2, #1 + strneh lr, [r0, r1] @ movhi + cmp ip, r2 + mov r3, r3, lsr #8 + bhi .L20203 + b .L19663 +.L20499: + .align 2 +.L20498: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word tile_mode_renderers + .word oam_ram + .word obj_width_table + .word obj_height_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L20489: + rsb r0, r8, r5 + rsb lr, r0, r9 + cmp lr, #0 + ble .L19663 + ldr r6, [sp, #16] + add r3, r8, r9 + cmp r6, r3 + bhi .L20011 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add r8, r2, r3, asl #6 + bne .L20013 + ldr r7, [sp, #120] + ldr r5, [sp, #100] +.L20015: + movs r4, r7, lsr #3 + beq .L20073 + ldr r0, [sp, #56] + mov r1, r5 + mov ip, r8 + mov lr, #0 +.L20075: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L20076 + tst r2, #255 + ldrneh r3, [r0, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #2] + mov r3, r2, lsr #16 + strneh r6, [r1, #2] @ movhi + tst r3, #255 + ldrneh r3, [r0, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #6] + strneh r6, [r1, #6] @ movhi +.L20076: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L20085 + tst r2, #255 + ldrneh r3, [r0, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #10] + mov r3, r2, lsr #16 + strneh r6, [r1, #10] @ movhi + tst r3, #255 + ldrneh r3, [r0, #12] + strneh r3, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #14] + strneh r6, [r1, #14] @ movhi +.L20085: + add lr, lr, #1 + cmp lr, r4 + add ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L20075 + ldr ip, [sp, #56] + mov r3, r4, asl #4 + add ip, ip, r3 + add r5, r5, r3 + add r8, r8, r4, asl #6 + str ip, [sp, #56] +.L20073: + ands r0, r7, #7 + beq .L19663 + cmp r0, #3 + ldrls r3, [r8, #0] + bls .L20108 + ldr r2, [r8, #0] + cmp r2, #0 + beq .L20098 + tst r2, #255 + ldrne lr, [sp, #56] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #0] + strneh lr, [r5, #0] @ movhi + tst r3, #255 + ldrne r1, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r1, [r1, #2] + strneh r1, [r5, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #4] + strneh r3, [r5, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #6] + strneh r4, [r5, #6] @ movhi +.L20098: + subs r0, r0, #4 + ldr r3, [r8, #4] + beq .L19663 + ldr r6, [sp, #56] + add r5, r5, #8 + add r6, r6, #8 + str r6, [sp, #56] +.L20108: + mov r2, #0 +.L20109: + tst r3, #255 + ldrne ip, [sp, #56] + mov r1, r2, asl #1 + ldrneh ip, [r1, ip] + add r2, r2, #1 + strneh ip, [r1, r5] @ movhi + cmp r0, r2 + mov r3, r3, lsr #8 + bhi .L20109 + b .L19663 +.L20488: + ldr r1, [sp, #20] + rsb ip, r8, r1 + rsb r1, ip, r9 + cmp r1, #0 + ble .L19663 + ldr r2, [sp, #16] + add r3, r8, r9 + cmp r2, r3 + bhi .L19881 + mov r3, ip, lsr #3 + ands r4, ip, #7 + sub r0, r0, r3, asl #5 + bne .L19883 + ldr r7, [sp, #120] + ldr r1, [sp, #100] +.L19885: + movs r3, r7, lsr #3 + beq .L19902 + ldr lr, [sp, #56] + mov ip, r1 + mov r4, r0 + mov r5, #0 +.L19904: + ldr r2, [r4, #0] + cmp r2, #0 + beq .L19905 + tst r2, #15 + ldrneh r6, [lr, #14] + strneh r6, [ip, #14] @ movhi + tst r2, #240 + ldrneh r6, [lr, #12] + strneh r6, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r6, [lr, #10] + strneh r6, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r6, [lr, #8] + strneh r6, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r6, [lr, #6] + strneh r6, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r6, [lr, #4] + strneh r6, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r6, [lr, #2] + strneh r6, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L19905: + add r5, r5, #1 + cmp r5, r3 + sub r4, r4, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L19904 + ldr r4, [sp, #56] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r4, r4, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r4, [sp, #56] +.L19902: + ands ip, r7, #7 + beq .L19663 + ldr r0, [r0, #0] + mov r2, #0 +.L19924: + movs r5, r0, lsr #28 + ldrne r6, [sp, #56] + mov r3, r2, asl #1 + ldrneh r6, [r3, r6] + add r2, r2, #1 + strneh r6, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L19924 + b .L19663 +.L20487: + rsb ip, r8, r2 + rsb lr, ip, r9 + cmp lr, #0 + ble .L19663 + ldr r4, [sp, #16] + add r3, r8, r9 + cmp r4, r3 + bhi .L19751 + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + add r4, r0, r1 + bne .L19753 + ldr r7, [sp, #120] + ldr r5, [sp, #100] +.L19755: + movs lr, r7, lsr #3 + beq .L19772 + ldr r1, [sp, #56] + mov r2, r5 + mov r0, r4 + mov ip, #0 +.L19774: + ldr r3, [r0, #0] + cmp r3, #0 + beq .L19775 + tst r3, #15 + ldrneh r6, [r1, #0] + strneh r6, [r2, #0] @ movhi + tst r3, #240 + ldrneh r6, [r1, #2] + strneh r6, [r2, #2] @ movhi + tst r3, #3840 + ldrneh r6, [r1, #4] + strneh r6, [r2, #4] @ movhi + tst r3, #61440 + ldrneh r6, [r1, #6] + strneh r6, [r2, #6] @ movhi + tst r3, #983040 + ldrneh r6, [r1, #8] + strneh r6, [r2, #8] @ movhi + tst r3, #15728640 + ldrneh r6, [r1, #10] + strneh r6, [r2, #10] @ movhi + tst r3, #251658240 + ldrneh r6, [r1, #12] + strneh r6, [r2, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [r1, #14] + strneh r3, [r2, #14] @ movhi +.L19775: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + bne .L19774 + ldr r6, [sp, #56] + mov r3, lr, asl #4 + add r6, r6, r3 + add r5, r5, r3 + add r4, r4, lr, asl #5 + str r6, [sp, #56] +.L19772: + ands r0, r7, #7 + beq .L19663 + ldr r3, [r4, #0] + mov r1, #0 +.L19794: + tst r3, #15 + ldrne ip, [sp, #56] + mov r2, r1, asl #1 + ldrneh ip, [r2, ip] + add r1, r1, #1 + strneh ip, [r2, r5] @ movhi + cmp r1, r0 + mov r3, r3, lsr #4 + bne .L19794 + b .L19663 +.L19720: + cmp ip, r9 + bcs .L19663 +.L20464: + mov r3, ip, asr #1 + and r4, r3, #3 + mov r3, ip, asr #3 + mov r3, r3, asl #5 + mov r2, ip, asr #1 + tst ip, #1 + and lr, r2, #3 + add ip, r3, r7 + add r2, r3, r7 + ldreqb r3, [r2, lr] @ zero_extendqisi2 + ldrneb r3, [ip, r4] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + cmp r2, #0 + ldrne r4, [sp, #56] + ldr r5, [sp, #56] + ldrneh r4, [r4, #0] + ldr r3, [sp, #84] + add r1, r1, #1 + strneh r4, [r8, #0] @ movhi + add r0, r0, r3 + add r5, r5, #2 + cmp r6, r1 + mov ip, r0, asr #8 + add r8, r8, #2 + str r5, [sp, #56] + bgt .L19720 + b .L19663 +.L19688: + cmp ip, r9 + bcs .L19663 +.L20462: + ldr r2, [sp, #76] + mov r3, ip, asr #3 + add r3, r4, r3, asl #6 + and r1, ip, #7 + add r0, r0, r2 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r5, [sp, #56] + cmp r2, #0 + ldrne r3, [sp, #56] + add lr, lr, #1 + ldrneh r3, [r3, #0] + add r5, r5, #2 + strneh r3, [r8, #0] @ movhi + cmp fp, lr + mov ip, r0, asr #8 + add r8, r8, #2 + str r5, [sp, #56] + bgt .L19688 + b .L19663 +.L20486: + rsb r0, r8, r2 + rsb lr, r0, r9 + cmp lr, #0 + ble .L19663 + ldr r4, [sp, #16] + add r3, r8, r9 + cmp r4, r3 + bhi .L20231 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub r8, r7, r3, asl #6 + bne .L20233 + ldr r7, [sp, #120] + ldr r5, [sp, #100] +.L20235: + movs r4, r7, lsr #3 + beq .L20293 + ldr r0, [sp, #56] + mov r1, r5 + mov ip, r8 + mov lr, #0 +.L20295: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L20296 + tst r2, #255 + ldrneh r3, [r0, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #4] + mov r3, r2, lsr #16 + strneh r6, [r1, #4] @ movhi + tst r3, #255 + ldrneh r3, [r0, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #0] + strneh r6, [r1, #0] @ movhi +.L20296: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L20305 + tst r2, #255 + ldrneh r3, [r0, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r6, [r0, #12] + mov r3, r2, lsr #16 + strneh r6, [r1, #12] @ movhi + tst r3, #255 + ldrneh r3, [r0, #10] + strneh r3, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrneh r6, [r0, #8] + strneh r6, [r1, #8] @ movhi +.L20305: + add lr, lr, #1 + cmp lr, r4 + sub ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L20295 + ldr ip, [sp, #56] + mov r3, r4, asl #4 + rsb r2, r4, r4, asl #26 + add ip, ip, r3 + add r5, r5, r3 + add r8, r8, r2, asl #6 + str ip, [sp, #56] +.L20293: + ands ip, r7, #7 + beq .L19663 + cmp ip, #3 + ldrls r2, [r8, #4] + bls .L20328 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L20318 + tst r2, #255 + ldrne lr, [sp, #56] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #6] + strneh lr, [r5, #6] @ movhi + tst r3, #255 + ldrne r0, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #4] + strneh r0, [r5, #4] @ movhi + tst r3, #255 + ldrne r1, [sp, #56] + ldrneh r1, [r1, #2] + strneh r1, [r5, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r2, [sp, #56] + ldrneh r2, [r2, #0] + strneh r2, [r5, #0] @ movhi +.L20318: + subs ip, ip, #4 + ldr r2, [r8, #0] + beq .L19663 + ldr r3, [sp, #56] + add r5, r5, #8 + add r3, r3, #8 + str r3, [sp, #56] +.L20328: + mov r1, #0 +.L20329: + movs r4, r2, lsr #24 + ldrne r6, [sp, #56] + mov r0, r1, asl #1 + ldrneh r6, [r0, r6] + add r1, r1, #1 + strneh r6, [r0, r5] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L20329 + b .L19663 +.L19829: + cmp lr, #0 + beq .L19663 + ldr r6, [sp, #12] + mov r3, #0 + add r1, r6, r8, asl #1 + b .L19859 +.L20490: + ldr ip, [sp, #56] + add r0, r0, #32 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #56] +.L19859: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L19860 + tst ip, #15 + ldrne r2, [sp, #56] + ldrneh r2, [r2, #0] + strneh r2, [r1, #0] @ movhi + tst ip, #240 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst ip, #3840 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + tst ip, #61440 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi + tst ip, #983040 + ldrne r2, [sp, #56] + ldrneh r2, [r2, #8] + strneh r2, [r1, #8] @ movhi + tst ip, #15728640 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst ip, #251658240 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs ip, ip, lsr #28 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L19860: + add r3, r3, #1 + cmp lr, r3 + bne .L20490 + b .L19663 +.L19959: + cmp lr, #0 + beq .L19663 + ldr ip, [sp, #12] + mov r3, #0 + add r1, ip, r8, asl #1 + b .L19989 +.L20491: + ldr r2, [sp, #56] + sub r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #56] +.L19989: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L19990 + tst r2, #15 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #14] + strneh r4, [r1, #14] @ movhi + tst r2, #240 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + tst r2, #3840 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #10] + strneh r6, [r1, #10] @ movhi + tst r2, #61440 + ldrne ip, [sp, #56] + ldrneh ip, [ip, #8] + strneh ip, [r1, #8] @ movhi + tst r2, #983040 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #6] + strneh r4, [r1, #6] @ movhi + tst r2, #15728640 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + tst r2, #251658240 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #2] + strneh r6, [r1, #2] @ movhi + movs r2, r2, lsr #28 + ldrne ip, [sp, #56] + ldrneh ip, [ip, #0] + strneh ip, [r1, #0] @ movhi +.L19990: + add r3, r3, #1 + cmp lr, r3 + bne .L20491 + b .L19663 +.L20384: + cmp lr, #0 + beq .L19663 + ldr r2, [sp, #12] + ldr r3, .L20498+32 + add r1, r2, r8, asl #1 + add r0, r0, r3 + mov r2, #0 + b .L20428 +.L20492: + ldr ip, [sp, #56] + sub r7, r7, #64 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #56] +.L20428: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L20429 + tst ip, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L20429: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L20438 + tst ip, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #14] + strneh r3, [r1, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi +.L20438: + add r2, r2, #1 + cmp lr, r2 + sub r0, r0, #64 + bne .L20492 + b .L19663 +.L20164: + cmp r4, #0 + beq .L19663 + ldr r3, [sp, #12] + mov lr, #0 + add r1, r3, r8, asl #1 + ldr r3, .L20498+36 + add r0, r0, r3 + b .L20208 +.L20493: + ldr ip, [sp, #56] + add r2, r2, #64 + add ip, ip, #16 + add r1, r1, #16 + str ip, [sp, #56] +.L20208: + ldr ip, [r2, #0] + cmp ip, #0 + beq .L20209 + tst ip, #255 + ldrne r5, [sp, #56] + mov r3, ip, lsr #8 + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi + tst r3, #255 + ldrne r6, [sp, #56] + mov r3, ip, lsr #16 + ldrneh r6, [r6, #2] + strneh r6, [r1, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + movs ip, ip, lsr #24 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #6] + strneh r5, [r1, #6] @ movhi +.L20209: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L20218 + tst ip, #255 + ldrne r6, [sp, #56] + mov r3, ip, lsr #8 + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #10] + strneh r3, [r1, #10] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs ip, ip, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L20218: + add lr, lr, #1 + cmp r4, lr + add r0, r0, #64 + bne .L20493 + b .L19663 +.L20011: + ands r1, r0, #7 + mov r3, r0, lsr #3 + add ip, r2, r3, asl #6 + ldreq r1, [sp, #100] + beq .L20115 + cmp r1, #3 + rsb r0, r1, #8 + bls .L20116 + cmp r0, #0 + ldr r2, [ip, #4] + ldreq r1, [sp, #100] + beq .L20120 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r3, r2, lsr r3 + mov r1, #0 +.L20121: + tst r3, #255 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, lsr #8 + bne .L20121 + ldr r6, [sp, #56] + mov r3, r0, asl #1 + ldr r0, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r1, r0, r3 +.L20120: + add ip, ip, #64 +.L20115: + movs lr, lr, lsr #3 + beq .L19663 + mov r0, #0 + b .L20144 +.L20494: + ldr r2, [sp, #56] + add ip, ip, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #56] +.L20144: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L20145 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L20145: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L20154 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L20154: + add r0, r0, #1 + cmp r0, lr + bne .L20494 + b .L19663 +.L19881: + mov r3, ip, lsr #3 + ands r2, ip, #7 + sub r0, r0, r3, asl #5 + ldreq r3, [sp, #100] + beq .L19930 + rsbs r4, r2, #8 + ldr ip, [r0, #0] + ldreq r3, [sp, #100] + beq .L19933 + mov r3, r2, asl #2 + mov r3, ip, asl r3 + mov lr, #0 +.L19934: + movs ip, r3, lsr #28 + ldrne r2, [sp, #56] + mov ip, lr, asl #1 + ldrneh r5, [ip, r2] + ldrne r2, [sp, #100] + add lr, lr, #1 + strneh r5, [ip, r2] @ movhi + cmp lr, r4 + mov r3, r3, asl #4 + bne .L19934 + ldr r6, [sp, #56] + mov r3, r4, asl #1 + ldr ip, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r3, ip, r3 +.L19933: + sub r0, r0, #32 +.L19930: + movs r1, r1, lsr #3 + beq .L19663 + mov r2, #0 + b .L19940 +.L20495: + ldr ip, [sp, #56] + sub r0, r0, #32 + add ip, ip, #16 + add r3, r3, #16 + str ip, [sp, #56] +.L19940: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L19941 + tst ip, #15 + ldrne lr, [sp, #56] + ldrneh lr, [lr, #14] + strneh lr, [r3, #14] @ movhi + tst ip, #240 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #12] + strneh r4, [r3, #12] @ movhi + tst ip, #3840 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #10] + strneh r5, [r3, #10] @ movhi + tst ip, #61440 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #8] + strneh r6, [r3, #8] @ movhi + tst ip, #983040 + ldrne lr, [sp, #56] + ldrneh lr, [lr, #6] + strneh lr, [r3, #6] @ movhi + tst ip, #15728640 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #4] + strneh r4, [r3, #4] @ movhi + tst ip, #251658240 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #2] + strneh r5, [r3, #2] @ movhi + movs ip, ip, lsr #28 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #0] + strneh r6, [r3, #0] @ movhi +.L19941: + add r2, r2, #1 + cmp r2, r1 + bne .L20495 + b .L19663 +.L19751: + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + ldreq r3, [sp, #100] + add ip, r0, r1 + beq .L19800 + rsbs r4, r3, #8 + ldr r0, [r0, r1] + ldreq r3, [sp, #100] + beq .L19803 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L19804: + tst r0, #15 + ldrne r1, [sp, #56] + mov r3, r2, asl #1 + ldrneh r5, [r3, r1] + ldrne r1, [sp, #100] + add r2, r2, #1 + strneh r5, [r3, r1] @ movhi + cmp r4, r2 + mov r0, r0, lsr #4 + bne .L19804 + ldr r6, [sp, #56] + mov r3, r4, asl #1 + ldr r0, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r3, r0, r3 +.L19803: + add ip, ip, #32 +.L19800: + movs r0, lr, lsr #3 + beq .L19663 + mov r1, #0 + b .L19810 +.L20496: + ldr r2, [sp, #56] + add ip, ip, #32 + add r2, r2, #16 + add r3, r3, #16 + str r2, [sp, #56] +.L19810: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L19811 + tst r2, #15 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #0] + strneh r4, [r3, #0] @ movhi + tst r2, #240 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #2] + strneh r5, [r3, #2] @ movhi + tst r2, #3840 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #4] + strneh r6, [r3, #4] @ movhi + tst r2, #61440 + ldrne lr, [sp, #56] + ldrneh lr, [lr, #6] + strneh lr, [r3, #6] @ movhi + tst r2, #983040 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #8] + strneh r4, [r3, #8] @ movhi + tst r2, #15728640 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #10] + strneh r5, [r3, #10] @ movhi + tst r2, #251658240 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #12] + strneh r6, [r3, #12] @ movhi + movs r2, r2, lsr #28 + ldrne lr, [sp, #56] + ldrneh lr, [lr, #14] + strneh lr, [r3, #14] @ movhi +.L19811: + add r1, r1, #1 + cmp r1, r0 + bne .L20496 + b .L19663 +.L20231: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub ip, r7, r3, asl #6 + ldreq r1, [sp, #100] + beq .L20335 + cmp r2, #3 + rsb r0, r2, #8 + bls .L20336 + cmp r0, #0 + ldr r1, [ip, #0] + ldreq r1, [sp, #100] + beq .L20340 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L20341: + movs r2, r3, lsr #24 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, asl #8 + bne .L20341 + ldr r6, [sp, #56] + mov r3, r0, asl #1 + ldr r0, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r1, r0, r3 +.L20340: + sub ip, ip, #64 +.L20335: + movs lr, lr, lsr #3 + beq .L19663 + mov r0, #0 + b .L20364 +.L20497: + ldr r2, [sp, #56] + sub ip, ip, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #56] +.L20364: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L20365 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L20365: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L20374 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi +.L20374: + add r0, r0, #1 + cmp r0, lr + bne .L20497 + b .L19663 +.L19753: + ldr r5, [sp, #120] + rsb ip, r3, #8 + cmp r5, ip + bge .L19756 + cmp r5, #0 + ble .L19663 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L19760: + tst r0, #15 + ldrne r6, [sp, #56] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #120] + ldrne r6, [sp, #100] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r0, r0, lsr #4 + bne .L19760 + b .L19663 +.L20233: + ldr r5, [sp, #120] + rsb lr, ip, #8 + cmp r5, lr + bge .L20236 + cmp r5, #0 + ble .L19663 + cmp ip, #3 + bls .L20239 + ldr r2, [r8, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L20242: + movs r6, r2, lsr #24 + ldrne ip, [sp, #56] + mov r3, r1, asl #1 + ldrneh lr, [r3, ip] + ldr r0, [sp, #120] + ldrne ip, [sp, #100] + add r1, r1, #1 + strneh lr, [r3, ip] @ movhi + cmp r0, r1 + mov r2, r2, asl #8 + bne .L20242 + b .L19663 +.L20013: + ldr r0, [sp, #120] + rsb lr, ip, #8 + cmp r0, lr + bge .L20016 + cmp r0, #0 + ble .L19663 + cmp ip, #3 + bls .L20019 + ldr r2, [r8, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L20022: + tst r1, #255 + ldrne r4, [sp, #56] + mov r3, r2, asl #1 + ldrneh r5, [r3, r4] + ldr r6, [sp, #120] + ldrne r4, [sp, #100] + add r2, r2, #1 + strneh r5, [r3, r4] @ movhi + cmp r6, r2 + mov r1, r1, lsr #8 + bne .L20022 + b .L19663 +.L19883: + ldr r3, [sp, #120] + rsb lr, r4, #8 + cmp r3, lr + bge .L19886 + cmp r3, #0 + ble .L19663 + ldr r2, [r0, #0] + mov r3, r4, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L19890: + movs r4, r0, lsr #28 + ldrne r5, [sp, #56] + mov r3, r2, asl #1 + ldrneh r6, [r3, r5] + ldr ip, [sp, #120] + ldrne r5, [sp, #100] + add r2, r2, #1 + strneh r6, [r3, r5] @ movhi + cmp ip, r2 + mov r0, r0, asl #4 + bne .L19890 + b .L19663 +.L20016: + cmp ip, #3 + bls .L20046 + cmp lr, #0 + ldr r2, [r8, #4] + ldreq r5, [sp, #100] + beq .L20050 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L20051: + tst r1, #255 + ldrne r0, [sp, #56] + mov r3, r2, asl #1 + ldrneh r4, [r3, r0] + ldrne r0, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, r0] @ movhi + cmp lr, r2 + mov r1, r1, lsr #8 + bne .L20051 + ldr r5, [sp, #56] + mov r3, lr, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #56] + add r5, r3, r6 +.L20050: + ldr ip, [sp, #120] + add r8, r8, #64 + rsb r7, lr, ip + b .L20015 +.L20116: + subs r4, r0, #4 + ldr r2, [ip, #0] + ldreq r1, [sp, #100] + beq .L20128 + mov r3, r1, asl #3 + mov r3, r2, lsr r3 + mov r1, #0 +.L20129: + tst r3, #255 + ldrne r5, [sp, #56] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r5, [sp, #100] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp r1, r4 + mov r3, r3, lsr #8 + bne .L20129 + mov r3, r0, asl #1 + ldr r0, [sp, #56] + ldr r1, [sp, #100] + add r2, r0, r3 + sub r2, r2, #8 + add r3, r1, r3 + str r2, [sp, #56] + sub r1, r3, #8 +.L20128: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L20134 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L20134: + ldr r0, [sp, #56] + add r1, r1, #8 + add r0, r0, #8 + add ip, ip, #64 + str r0, [sp, #56] + b .L20115 +.L19756: + cmp ip, #0 + ldr r2, [r4, #0] + ldreq r5, [sp, #100] + beq .L19766 + mov r3, r3, asl #2 + mov r3, r2, lsr r3 + mov r1, #0 +.L19767: + tst r3, #15 + ldrne r0, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r0] + ldrne r0, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r0] @ movhi + cmp ip, r1 + mov r3, r3, lsr #4 + bne .L19767 + ldr r6, [sp, #56] + mov r3, ip, asl #1 + ldr lr, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r5, r3, lr +.L19766: + ldr r0, [sp, #120] + add r4, r4, #32 + rsb r7, ip, r0 + b .L19755 +.L19886: + cmp lr, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #100] + beq .L19896 + mov r3, r4, asl #2 + mov r3, r2, asl r3 + mov ip, #0 +.L19897: + movs r1, r3, lsr #28 + ldrne r4, [sp, #56] + mov r2, ip, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add ip, ip, #1 + strneh r5, [r2, r4] @ movhi + cmp lr, ip + mov r3, r3, asl #4 + bne .L19897 + ldr r6, [sp, #56] + mov r3, lr, asl #1 + ldr ip, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r1, r3, ip +.L19896: + ldr r2, [sp, #120] + sub r0, r0, #32 + rsb r7, lr, r2 + b .L19885 +.L20336: + subs r4, r0, #4 + ldr r1, [ip, #4] + ldreq r1, [sp, #100] + beq .L20348 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L20349: + movs r2, r3, lsr #24 + ldrne r5, [sp, #56] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r5, [sp, #100] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp r1, r4 + mov r3, r3, asl #8 + bne .L20349 + mov r3, r0, asl #1 + ldr r0, [sp, #56] + ldr r1, [sp, #100] + add r2, r0, r3 + sub r2, r2, #8 + add r3, r1, r3 + str r2, [sp, #56] + sub r1, r3, #8 +.L20348: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L20354 + tst r2, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #56] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L20354: + ldr r0, [sp, #56] + add r1, r1, #8 + add r0, r0, #8 + sub ip, ip, #64 + str r0, [sp, #56] + b .L20335 +.L20236: + cmp ip, #3 + bls .L20266 + cmp lr, #0 + ldr r2, [r8, #0] + ldreq r5, [sp, #100] + beq .L20270 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L20271: + movs r2, r3, lsr #24 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp lr, r1 + mov r3, r3, asl #8 + bne .L20271 + ldr r6, [sp, #56] + mov r3, lr, asl #1 + ldr ip, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add r5, ip, r3 +.L20270: + ldr ip, [sp, #120] + sub r8, r8, #64 + rsb r7, lr, ip + b .L20235 +.L20482: + mov r7, #0 + b .L19733 +.L20478: + mov r7, #0 + b .L19698 +.L20046: + subs r0, lr, #4 + ldr r2, [r8, #0] + ldreq r1, [sp, #100] + beq .L20058 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L20059: + tst r1, #255 + ldrne ip, [sp, #56] + mov r3, r2, asl #1 + ldrneh r4, [r3, ip] + ldrne ip, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, ip] @ movhi + cmp r2, r0 + mov r1, r1, lsr #8 + bne .L20059 + ldr r5, [sp, #56] + mov r3, lr, asl #1 + ldr r6, [sp, #100] + add r2, r5, r3 + sub r2, r2, #8 + add r3, r6, r3 + str r2, [sp, #56] + sub r1, r3, #8 +.L20058: + ldr r2, [r8, #4] + cmp r2, #0 + beq .L20064 + tst r2, #255 + ldrne ip, [sp, #56] + mov r3, r2, lsr #8 + ldrneh ip, [ip, #0] + strneh ip, [r1, #0] @ movhi + tst r3, #255 + ldrne r0, [sp, #56] + mov r3, r2, lsr #16 + ldrneh r0, [r0, #2] + strneh r0, [r1, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #6] + strneh r4, [r1, #6] @ movhi +.L20064: + ldr r6, [sp, #56] + add r5, r1, #8 + add r6, r6, #8 + str r6, [sp, #56] + b .L20050 +.L20266: + subs r0, lr, #4 + ldr r2, [r8, #4] + ldreq r1, [sp, #100] + beq .L20278 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L20279: + movs r2, r3, lsr #24 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, asl #8 + bne .L20279 + ldr r6, [sp, #56] + mov r3, lr, asl #1 + ldr ip, [sp, #100] + add r2, r6, r3 + sub r2, r2, #8 + add r3, ip, r3 + str r2, [sp, #56] + sub r1, r3, #8 +.L20278: + ldr r2, [r8, #0] + cmp r2, #0 + beq .L20284 + tst r2, #255 + ldrne r0, [sp, #56] + mov r3, r2, lsr #8 + ldrneh r0, [r0, #6] + strneh r0, [r1, #6] @ movhi + tst r3, #255 + ldrne r3, [sp, #56] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + tst r3, #255 + ldrne r4, [sp, #56] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r5, [sp, #56] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L20284: + ldr r6, [sp, #56] + add r5, r1, #8 + add r6, r6, #8 + str r6, [sp, #56] + b .L20270 +.L20485: + mov r1, fp + b .L20464 +.L20484: + mov lr, r6 + b .L20462 +.L20019: + ldr lr, [sp, #120] + ldr r3, [r8, #0] + add r2, lr, ip + mov r1, ip, asl #3 + cmp r2, #4 + mov r3, r3, lsr r1 + bhi .L20026 + cmp lr, #0 + movne r1, #0 + beq .L19663 +.L20042: + tst r3, #255 + ldrne r5, [sp, #56] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldr ip, [sp, #120] + ldrne r5, [sp, #100] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L20042 + b .L19663 +.L20239: + ldr r4, [sp, #120] + mov r3, ip, asl #3 + ldr r1, [r8, #4] + add r2, r4, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L20246 + cmp r4, #0 + movne r2, #0 + beq .L19663 +.L20262: + movs r6, r1, lsr #24 + ldrne ip, [sp, #56] + mov r3, r2, asl #1 + ldrneh lr, [r3, ip] + ldr r0, [sp, #120] + ldrne ip, [sp, #100] + add r2, r2, #1 + strneh lr, [r3, ip] @ movhi + cmp r0, r2 + mov r1, r1, asl #8 + bne .L20262 + b .L19663 +.L20026: + rsbs r0, ip, #4 + ldreq ip, [sp, #100] + beq .L20031 + mov r1, #0 +.L20032: + tst r3, #255 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L20032 + ldr r6, [sp, #56] + mov r3, r0, asl #1 + ldr lr, [sp, #100] + add r6, r6, r3 + str r6, [sp, #56] + add ip, r3, lr +.L20031: + ldr r1, [sp, #120] + ldr r3, [r8, #4] + subs r0, r1, r0 + beq .L19663 + mov r1, #0 +.L20038: + tst r3, #255 + ldrne r4, [sp, #56] + mov r2, r1, asl #1 + ldrneh r4, [r2, r4] + add r1, r1, #1 + strneh r4, [r2, ip] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L20038 + b .L19663 +.L20246: + rsbs r0, ip, #4 + ldreq r3, [sp, #100] + beq .L20251 + mov r2, #0 +.L20252: + movs r5, r1, lsr #24 + ldrne r6, [sp, #56] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldrne r6, [sp, #100] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp r2, r0 + mov r1, r1, asl #8 + bne .L20252 + ldr lr, [sp, #56] + mov r3, r0, asl #1 + ldr r1, [sp, #100] + add lr, lr, r3 + str lr, [sp, #56] + add r3, r3, r1 +.L20251: + ldr r2, [sp, #120] + subs ip, r2, r0 + ldr r2, [r8, #0] + beq .L19663 + mov r0, #0 +.L20258: + movs r4, r2, lsr #24 + ldrne r5, [sp, #56] + mov r1, r0, asl #1 + ldrneh r5, [r1, r5] + add r0, r0, #1 + strneh r5, [r1, r3] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L20258 + b .L19663 + .size render_scanline_obj_copy_tile_1D, .-render_scanline_obj_copy_tile_1D + .align 2 + .global render_scanline_window_tile + .type render_scanline_window_tile, %function +render_scanline_window_tile: + @ args = 0, pretend = 0, frame = 20 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L21076 + mov r2, r1, lsr #13 + ldrh ip, [lr, #74] + ldr r3, .L21076+4 + and ip, ip, #63 + sub sp, sp, #32 + mov r6, r1 + sub r2, r2, #1 + and r1, r1, #7 + str ip, [sp, #12] + add r9, r3, r1, asl #7 + mov r7, r0 + ldrh ip, [lr, #6] + ldrh sl, [lr, #80] + cmp r2, #6 + ldrls pc, [pc, r2, asl #2] + b .L20990 + .p2align 2 +.L20509: + .word .L20502 + .word .L20503 + .word .L20504 + .word .L20505 + .word .L20506 + .word .L20507 + .word .L20508 +.L20503: + ldrh r3, [lr, #70] + ldr r4, .L21076 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L20531 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + bne .L20539 +.L20994: + cmp r1, #227 + bhi .L20539 +.L20535: + mov r4, #240 + mov r5, r4 +.L20547: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20548: + cmp r5, r4 + beq .L20528 + mov r0, r5 + mov r3, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20528: + cmp r4, #240 + beq .L20990 + ldr r3, [sp, #12] + mov r0, r4 + mov r2, r7 +.L21037: + mov r1, #240 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20990: + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L20502: + ldrh r3, [lr, #68] + ldr r4, .L21076 + and r2, r3, #255 + mov r1, r3, lsr #8 + cmp r1, r2 + ldrh r0, [lr, #72] + bls .L20510 + cmp ip, r1 + movls r3, #0 + movhi r3, #1 + cmp ip, r2 + orrls r3, r3, #1 + cmp r3, #0 + beq .L20992 +.L20518: + cmp r1, #227 + bhi .L20535 + ldrh r3, [r4, #64] + and r8, r0, #63 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + bhi .L21059 +.L20538: + cmp r5, r4 + bls .L20542 + cmp r4, #0 + bne .L21060 +.L20544: + mov r0, r4 + ldr r3, [sp, #12] + mov r2, r7 + mov r1, r5 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + cmp r5, #240 + movne r0, r5 + movne r2, r7 + movne r3, r8 + bne .L21037 + b .L20990 +.L20508: + ldrh r3, [lr, #68] + ldr r2, .L21076 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r4, [lr, #72] + bls .L20774 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21053 +.L20782: + cmp r0, #227 + bls .L21061 +.L20778: + mov r8, #240 + mov fp, r8 +.L20781: + ldrh r3, [lr, #70] + ldr r0, .L21076 + and r1, r3, #255 + mov r2, r3, lsr #8 + cmp r2, r1 + bls .L20785 + cmp ip, r2 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21054 +.L20793: + cmp r2, #227 + bls .L21062 +.L20789: + mov r5, #240 + mov r4, r5 +.L20792: + cmp fp, r8 + bls .L20796 + cmp r8, #0 + bne .L21063 +.L20798: + cmp r4, #240 + beq .L20800 + cmp r4, r5 + bhi .L21064 + cmp r4, #0 + beq .L20840 + cmp r8, #0 + beq .L20842 + cmp r8, r4 + bcs .L20840 +.L20842: + cmp fp, r4 + bcs .L20851 + mov r0, r8 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20853 + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20840: + cmp r4, r5 + beq .L20857 + cmp r8, r4 + bls .L20859 + cmp r8, r5 + bcs .L20857 + cmp fp, r5 + ldrcc r3, [sp, #28] + ldrcs r3, [sp, #28] + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 +.L21026: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20857: + cmp r5, #240 + beq .L20832 + cmp r8, r5 + bls .L20868 + cmp r8, #239 + bhi .L20832 + cmp fp, #239 + bhi .L20871 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20873 + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20836 +.L20507: + ldrh r3, [lr, #70] + ldr r4, .L21076 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L20744 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21019 +.L20752: + cmp r0, #227 + bls .L21065 +.L20748: + mov r4, #240 + mov r5, r4 +.L20763: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20764: + ands r8, r6, #64 + beq .L20765 + mov r0, #4 + mov r1, #0 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20767: + cmp r4, r5 + beq .L20768 +.L21056: + mov r0, r5 + mov r3, fp + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20768: + cmp r4, #240 + beq .L20770 + ldr r3, [sp, #12] + mov r0, r4 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20770: + cmp r8, #0 + movne r1, r4 + beq .L21066 +.L21040: + mov r3, r7 + mov r0, #4 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_tile_1D +.L20506: + ldrh r3, [lr, #68] + ldr r4, .L21076 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L20714 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21017 +.L20722: + cmp r0, #227 + bls .L21067 +.L20718: + mov r4, #240 + mov r5, r4 +.L20733: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20734: + ands r8, r6, #64 + beq .L20735 + mov r0, #4 + mov r1, #0 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20737: + cmp r5, r4 + bne .L21056 + b .L20768 +.L20504: + ldrh r3, [lr, #68] + ldr r2, .L21076 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r4, [lr, #72] + bls .L20552 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21049 +.L20560: + cmp r0, #227 + bls .L21068 +.L20556: + mov r5, #240 + mov fp, r5 +.L20559: + ldrh r3, [lr, #70] + ldr r0, .L21076 + and r1, r3, #255 + mov r2, r3, lsr #8 + cmp r2, r1 + bls .L20563 + cmp ip, r2 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L21050 +.L20571: + cmp r2, #227 + bls .L21069 +.L20567: + mov r8, #240 + mov r4, r8 +.L20570: + cmp fp, r5 + bls .L20574 + cmp r5, #0 + bne .L21070 +.L20576: + cmp r4, #240 + beq .L20578 + cmp r4, r8 + bls .L20580 + cmp r8, #0 + beq .L20582 + cmp r5, #0 + beq .L20584 + cmp r5, r8 + bcs .L20582 + cmp fp, r8 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20582: + cmp r5, r8 + bls .L20591 + cmp r5, r4 + bcs .L20593 + cmp fp, r4 + ldrcc r3, [sp, #12] + ldrcs r3, [sp, #12] + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r4 +.L20999: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20593: + cmp r5, r4 + bls .L20600 + cmp r5, #239 + bhi .L20602 + cmp fp, #239 + movls r0, r5 + bls .L21003 + ldr r3, [sp, #20] + mov r0, r5 + mov r1, #240 +.L21002: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20602: + cmp fp, #240 + beq .L20990 +.L20606: + ldr r3, [sp, #16] + mov r0, fp + mov r2, r7 + b .L21037 +.L20505: + mov r1, #240 + ldr r3, [sp, #12] + mov r0, #0 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_tile + ands r1, r6, #64 + beq .L21038 + mov r3, r7 + mov r0, #4 + mov r1, #0 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_tile_1D +.L20531: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + beq .L20994 +.L20539: + cmp r0, #227 + bhi .L20535 + ldrh r3, [r4, #66] + mov r2, r2, lsr #8 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + and r8, r2, #63 + bls .L20538 +.L21059: + mov r4, #240 + b .L20538 +.L20714: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20722 +.L21017: + cmp r1, #227 + bls .L20718 + b .L20722 +.L20563: + cmp ip, r2 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20571 +.L21050: + cmp r1, #227 + bls .L20567 + b .L20571 +.L20552: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20560 +.L21049: + cmp r1, #227 + bls .L20556 + b .L20560 +.L20785: + cmp ip, r2 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20793 +.L21054: + cmp r1, #227 + bls .L20789 + b .L20793 +.L20744: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20752 +.L21019: + cmp r1, #227 + bls .L20748 + b .L20752 +.L20510: + cmp ip, r1 + movcc r3, #0 + movcs r3, #1 + cmp ip, r2 + movcs r3, #0 + cmp r3, #0 + bne .L20518 +.L20992: + cmp r2, #227 + bls .L20535 + b .L20518 +.L20774: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L20782 +.L21053: + cmp r1, #227 + bls .L20778 + b .L20782 +.L21066: + mov r1, r4 +.L21038: + mov r3, r7 + mov r0, #4 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_tile_2D +.L20796: + cmp r4, #240 + beq .L20886 + cmp r4, r5 + bls .L20888 + cmp r5, #0 + beq .L20890 + cmp fp, r5 + bcs .L20892 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L21029 +.L20890: + cmp fp, r4 + bcs .L20895 + cmp fp, r5 + bhi .L21071 +.L20897: + cmp fp, #239 + bhi .L20903 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L21031 +.L20905: + cmp fp, r8 + beq .L20933 + mov r0, fp + ldr r3, [sp, #24] + mov r1, r8 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20933: + cmp r4, #240 + beq .L20935 + cmp r4, r5 + bls .L20937 + cmp r5, #0 + beq .L20939 + cmp r8, #0 + beq .L20941 + cmp r8, r5 + bcs .L20939 + cmp r5, #240 + movhi r0, r8 + movhi r1, #240 + movls r0, r8 + movls r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20939: + cmp r8, r5 + bls .L20948 + cmp r8, r4 + bcc .L21072 +.L20950: + cmp r8, r4 + bls .L20956 + cmp r8, #239 + bhi .L20990 + ldr r3, [sp, #28] + mov r0, r8 + mov r2, r7 + b .L21037 +.L20574: + cmp r4, #240 + beq .L20638 + cmp r4, r8 + bls .L20640 + cmp r8, #0 + beq .L20642 + cmp fp, r8 + bcs .L20644 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L21005 +.L20642: + cmp fp, r4 + bcs .L20647 + cmp fp, r8 + movhi r0, r8 + movhi r1, fp + bhi .L21006 +.L20649: + cmp fp, #239 + bhi .L20651 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L21009 +.L20653: + cmp fp, r5 + beq .L20670 + mov r0, fp + ldr r3, [sp, #16] + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20670: + cmp r4, #240 + beq .L20672 + cmp r4, r8 + bls .L20674 + cmp r8, #0 + beq .L20676 + cmp r5, #0 + beq .L20678 + cmp r5, r8 + bcs .L20676 + cmp r8, #240 + movhi r0, r5 + movhi r1, #240 + movls r0, r5 + movls r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20676: + cmp r5, r8 + bls .L20685 + cmp r5, r4 + ldrcc r3, [sp, #12] + movcc r0, r5 + bcc .L21013 +.L20687: + cmp r5, r4 + bls .L20689 + cmp r5, #239 + bhi .L20990 + ldr r3, [sp, #20] + mov r0, r5 + mov r2, r7 + b .L21037 +.L20765: + mov r0, #4 + mov r1, r8 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20767 +.L20735: + mov r0, #4 + mov r1, r8 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20737 +.L21067: + ldrh r3, [r4, #64] + and fp, r2, #63 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + movhi r4, #240 + cmp r5, r4 + bhi .L21058 + cmp r5, #0 + bne .L20733 + b .L20734 +.L21069: + ldrh r3, [r0, #66] + mov r2, r4, lsr #8 + and r8, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r4, r3 + movcs r4, #240 + cmp r8, #240 + and r2, r2, #63 + movhi r8, #240 + str r2, [sp, #20] + b .L20570 +.L21062: + ldrh r3, [r0, #66] + mov r2, r4, lsr #8 + and r5, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r4, r3 + movcs r4, #240 + cmp r5, #240 + and r2, r2, #63 + movhi r5, #240 + str r2, [sp, #28] + b .L20792 +.L21061: + ldrh r3, [r2, #64] + and r2, r4, #63 + and r8, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc fp, r3 + movcs fp, #240 + cmp r8, #240 + movhi r8, #240 + str r2, [sp, #24] + b .L20781 +.L21065: + ldrh r3, [r4, #66] + mov r2, r2, lsr #8 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + movhi r4, #240 + cmp r5, r4 + and fp, r2, #63 + bhi .L21058 + cmp r5, #0 + bne .L20763 + b .L20764 +.L21068: + ldrh r3, [r2, #64] + and r2, r4, #63 + and r5, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc fp, r3 + movcs fp, #240 + cmp r5, #240 + movhi r5, #240 + str r2, [sp, #16] + b .L20559 +.L21064: + cmp r5, #0 + beq .L20804 + cmp r8, #0 + beq .L20806 + cmp r8, r5 + bcs .L20804 + cmp fp, r5 + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20804: + cmp r8, r5 + bls .L20813 + cmp r8, r4 + bcs .L20815 + cmp fp, r4 + bcs .L20817 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20819 + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20815: + cmp r8, r4 + bls .L20830 + cmp r8, #239 + bhi .L20832 + cmp fp, #239 + movls r0, r8 + movhi r0, r8 + bhi .L21027 +.L21028: + ldr r3, [sp, #28] + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20836: + ldr r3, [sp, #24] + mov r0, fp + mov r2, r7 + b .L21037 +.L20580: + cmp r4, #0 + beq .L20610 + cmp r5, #0 + beq .L20612 + cmp r5, r4 + bcs .L20610 +.L20612: + cmp fp, r4 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20610: + cmp r4, r8 + beq .L20619 + cmp r5, r4 + bls .L20621 + cmp r5, r8 + bcs .L20619 + cmp fp, r8 + ldrcc r3, [sp, #20] + ldrcs r3, [sp, #20] + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 +.L21001: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20619: + cmp r8, #240 + beq .L20602 + cmp r5, r8 + bls .L20630 + cmp r5, #239 + bhi .L20602 + cmp fp, #239 + movls r0, r5 + ldrls r3, [sp, #12] + bls .L21004 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, #240 + b .L21002 +.L21063: + mov r0, #0 + mov r1, r8 + mov r2, r7 + ldr r3, [sp, #24] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20798 +.L21070: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #16] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20576 +.L20886: + cmp fp, #0 + bne .L21073 +.L20929: + ands r1, r6, #64 + beq .L20931 + mov r0, #4 + mov r1, #0 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20905 +.L20638: + cmp fp, #0 + beq .L20653 + mov r0, #0 + mov r1, fp +.L21010: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20653 +.L21058: + cmp r4, #0 + bne .L21074 +.L20757: + ldr r3, [sp, #12] + mov r0, r4 + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20759 + mov r1, r4 + mov r0, #4 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20761: + cmp r5, #240 + movne r0, r5 + movne r2, r7 + movne r3, fp + bne .L21037 + b .L20990 +.L20542: + cmp r5, #0 + bne .L20547 + b .L20548 +.L20800: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20884 + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D +.L20832: + cmp fp, #240 + bne .L20836 + b .L20990 +.L20759: + mov r1, r4 + mov r0, #4 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20761 +.L21077: + .align 2 +.L21076: + .word io_registers + .word tile_mode_renderers +.L20937: + cmp r4, #0 + beq .L20959 + cmp r8, #0 + beq .L20961 + cmp r8, r4 + bcc .L20961 +.L20959: + cmp r4, r5 + beq .L20968 + cmp r8, r4 + bls .L20970 + cmp r8, r5 + bcs .L20968 + cmp r5, #240 + ldrhi r3, [sp, #28] + movhi r0, r8 + ldrls r3, [sp, #28] + movls r0, r8 + bls .L21035 +.L21036: + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20975: + cmp r8, r5 + bls .L20979 + cmp r8, #239 + bhi .L20990 + mov r1, #240 + ldr r3, [sp, #12] + mov r0, r8 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_tile + tst r6, #64 + moveq r1, r8 + beq .L21038 + mov r1, r8 + b .L21040 +.L20674: + cmp r4, #0 + beq .L20692 + cmp r5, #0 + beq .L20694 + cmp r5, r4 + bcc .L20694 +.L20692: + cmp r4, r8 + beq .L20697 + cmp r5, r4 + bls .L20699 + cmp r5, r8 + bcs .L20697 + cmp r8, #240 + ldrhi r3, [sp, #20] + movhi r0, r5 + ldrls r3, [sp, #20] + movls r0, r5 + bls .L21014 +.L21015: + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20704: + cmp r5, r8 + bls .L20708 + cmp r5, #239 + bhi .L20990 + ldr r3, [sp, #12] + mov r0, r5 + mov r2, r7 + b .L21037 +.L20888: + cmp r4, #0 + beq .L20907 + cmp fp, r4 + bcs .L20909 + cmp fp, #0 + bne .L21075 +.L20907: + cmp r4, r5 + beq .L20916 + cmp fp, r5 + bcs .L20918 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L21030 +.L20916: + cmp r5, #240 + beq .L20905 + cmp fp, #239 + bhi .L20922 + cmp fp, r5 + bls .L20905 + mov r0, r5 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20925 + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20905 +.L20640: + cmp r4, #0 + beq .L20655 + cmp fp, r4 + bcs .L20657 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L21007 +.L20655: + cmp r4, r8 + beq .L20660 + cmp fp, r8 + bcs .L20662 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L21008 +.L20660: + cmp r8, #240 + beq .L20653 + cmp fp, #239 + bhi .L20666 + cmp fp, r8 + movhi r0, r8 + movhi r1, fp + bls .L20653 + b .L21010 +.L20935: + cmp r8, #240 + beq .L20986 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_tile +.L20986: + tst r6, #64 + beq .L20988 + mov r1, r8 + mov r2, r4 + mov r3, r7 + mov r0, #4 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_tile_1D +.L20672: + cmp r5, #240 + beq .L20990 + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20990 +.L20806: + cmp fp, r5 + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20813: + cmp fp, r4 + bcs .L20823 + cmp fp, r5 + bls .L20815 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20826 + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20815 +.L20584: + cmp fp, r8 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20591: + cmp fp, r4 + bcs .L20597 + cmp fp, r8 + bls .L20593 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + b .L20999 +.L20678: + cmp r8, #240 + movhi r0, r5 + movhi r1, #240 + movls r0, r5 + movls r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20685: + ldr r3, [sp, #12] + mov r0, r8 +.L21013: + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20687 +.L20705: + ldr r3, [sp, #20] + mov r0, r4 +.L21014: + mov r1, r8 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20697: + cmp r8, #240 + bne .L20704 + b .L20990 +.L20976: + ldr r3, [sp, #28] + mov r0, r4 +.L21035: + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20968: + cmp r5, #240 + bne .L20975 + b .L20990 +.L21060: + mov r0, #0 + mov r1, r4 + mov r2, r7 + mov r3, r8 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20544 +.L21074: + mov r0, #0 + mov r1, r4 + mov r2, r7 + mov r3, fp + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20757 +.L20941: + cmp r5, #240 + movhi r0, r8 + movhi r1, #240 + movls r0, r8 + movls r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile +.L20948: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20954 + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20950 +.L20830: + cmp fp, #239 + bhi .L20837 + cmp fp, r4 + bls .L20836 + mov r0, r4 + b .L21028 +.L20600: + cmp fp, #239 + bhi .L20607 + cmp fp, r4 + bls .L20606 + mov r0, r4 +.L21003: + ldr r3, [sp, #20] +.L21004: + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20606 +.L20651: + mov r0, r4 + mov r1, #240 +.L21009: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20653 +.L20903: + mov r0, r4 + mov r1, #240 +.L21031: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20905 +.L20647: + mov r0, r8 + mov r1, r4 +.L21006: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20649 +.L20630: + cmp fp, #239 + bhi .L20635 + cmp fp, r8 + movhi r0, r8 + ldrhi r3, [sp, #12] + bls .L20606 + b .L21004 +.L20859: + cmp fp, r5 + bcs .L20864 + cmp fp, r4 + bls .L20857 + ldr r3, [sp, #28] + mov r0, r4 + mov r1, fp + b .L21026 +.L20868: + cmp fp, #239 + bhi .L20877 + cmp fp, r5 + bls .L20836 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20880 + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20836 +.L20621: + cmp fp, r8 + bcs .L20626 + cmp fp, r4 + bls .L20619 + ldr r3, [sp, #20] + mov r0, r4 + mov r1, fp + b .L21001 +.L20578: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + b .L21002 +.L20988: + mov r1, r8 + mov r2, r4 + mov r3, r7 + mov r0, #4 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_tile_2D +.L20931: + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20905 +.L20918: + mov r0, r4 + mov r1, r5 +.L21030: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20916 +.L20662: + mov r0, r4 + mov r1, r8 +.L21008: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20660 +.L20699: + cmp r8, #240 + bls .L20705 + cmp r4, #239 + bhi .L20704 + ldr r3, [sp, #20] + mov r0, r4 + b .L21015 +.L20970: + cmp r5, #240 + bls .L20976 + cmp r4, #239 + bhi .L20975 + ldr r3, [sp, #28] + mov r0, r4 + b .L21036 +.L20837: + mov r0, r4 +.L21027: + ldr r3, [sp, #28] + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20832 +.L20954: + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20950 +.L20895: + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20901 + mov r0, #4 + mov r1, r5 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20897 +.L20956: + ldr r3, [sp, #28] + mov r0, r4 + mov r2, r7 + b .L21037 +.L20689: + ldr r3, [sp, #20] + mov r0, r4 + mov r2, r7 + b .L21037 +.L20708: + ldr r3, [sp, #12] + mov r0, r8 + mov r2, r7 + b .L21037 +.L20979: + mov r1, #240 + ldr r3, [sp, #12] + mov r0, r5 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_tile + tst r6, #64 + movne r1, r5 + moveq r1, r5 + beq .L21038 + b .L21040 +.L20892: + mov r0, #0 + mov r1, r5 +.L21029: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20890 +.L20657: + mov r0, #0 + mov r1, r4 +.L21007: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20655 +.L20644: + mov r0, #0 + mov r1, r8 +.L21005: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20642 +.L20961: + mov r0, r8 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20966 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20959 +.L20694: + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20692 +.L21073: + mov r0, #0 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + b .L20929 +.L20823: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20828 + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20815 +.L20597: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + b .L20999 +.L20851: + mov r0, r8 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20855 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20840 +.L20666: + mov r0, r8 + mov r1, #240 + b .L21010 +.L20884: + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20832 +.L20922: + mov r0, r5 + mov r1, #240 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20927 + mov r0, #4 + mov r1, r5 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20905 +.L21071: + mov r0, r5 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20899 + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20897 +.L20607: + ldr r3, [sp, #20] + mov r0, r4 + mov r1, #240 + b .L21002 +.L20909: + mov r1, r4 + mov r0, #0 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + ands r1, r6, #64 + beq .L20914 + mov r0, #4 + mov r1, #0 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20907 +.L20901: + mov r0, #4 + mov r1, r5 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20897 +.L20966: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20959 +.L20635: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, #240 + b .L21002 +.L20626: + ldr r3, [sp, #20] + mov r0, r4 + mov r1, r8 + b .L21001 +.L20877: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20882 + mov r1, r5 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20832 +.L20864: + ldr r3, [sp, #28] + mov r0, r4 + mov r1, r5 + b .L21026 +.L21072: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20952 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20950 +.L20817: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20821 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20815 +.L20853: + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20840 +.L20828: + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20815 +.L20855: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20840 +.L20927: + mov r0, #4 + mov r1, r5 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20905 +.L20871: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + tst r6, #64 + beq .L20875 + mov r1, r8 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20832 +.L21075: + mov r1, fp + mov r0, #0 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_tile + ands r1, r6, #64 + beq .L20912 + mov r0, #4 + mov r1, #0 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_1D + b .L20907 +.L20899: + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20897 +.L20826: + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20815 +.L20914: + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20907 +.L20925: + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20905 +.L20882: + mov r1, r5 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20832 +.L20875: + mov r1, r8 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20832 +.L20819: + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20815 +.L20952: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20950 +.L20912: + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20907 +.L20821: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20815 +.L20873: + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20836 +.L20880: + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_tile_2D + b .L20836 + .size render_scanline_window_tile, .-render_scanline_window_tile + .align 2 + .global render_scanline_tile + .type render_scanline_tile, %function +render_scanline_tile: + @ args = 0, pretend = 0, frame = 960 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr fp, .L21279 + ldr lr, .L21279+4 + ldr r3, [fp, #0] + mov r5, r0 + cmp r3, #0 + sub sp, sp, #960 + mov r4, r1 + mov sl, lr + ldrh r0, [lr, #80] + beq .L21079 + ldr r3, .L21279+8 + ldrh r2, [lr, #6] + and r1, r1, #7 + ldr ip, [r3, r2, asl #2] + ldr r3, .L21279+12 + cmp ip, #0 + add r9, r3, r1, asl #7 + bne .L21267 + mov r3, r0, lsr #6 + and r3, r3, #3 + cmp r3, #2 + beq .L21157 + cmp r3, #3 + beq .L21158 + cmp r3, #1 + beq .L21268 +.L21155: + ldr r3, .L21279+16 + ldr ip, [r3, #0] + ands r1, ip, #4 + beq .L21221 + ldr r3, .L21279+20 + mov r2, #0 + ldrh r3, [r3, #0] +.L21223: + strh r3, [r2, r5] @ movhi + add r2, r2, #2 + cmp r2, #480 + bne .L21223 + ands r1, r4, #64 + bic r0, ip, #4 + beq .L21225 + mov r1, #0 + sub r2, r2, #240 + mov r3, r5 + bl render_scanline_obj_normal_1D +.L21227: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21241 + ldr r7, .L21279+16 + and r8, r4, #64 + mov r6, #1 + b .L21229 +.L21269: + bl render_scanline_obj_normal_1D +.L21234: + ldr r3, [fp, #0] + add r6, r6, #1 + cmp r3, r6 + add r7, r7, #4 + bls .L21241 +.L21229: + ldr ip, [r7, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, r5 + beq .L21230 + mov r1, #0 + bic ip, ip, #4 + cmp r8, r1 + mov r0, ip + bne .L21269 + mov r3, r5 + mov r0, ip + mov r1, r8 + mov r2, #240 + bl render_scanline_obj_normal_2D + ldr r3, [fp, #0] + add r6, r6, #1 + cmp r3, r6 + add r7, r7, #4 + bhi .L21229 +.L21241: + add sp, sp, #960 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L21079: + mov r3, r0, lsr #6 + and r2, r3, #3 + ldr r3, .L21279+20 + cmp r2, #2 + ldrh ip, [r3, #0] + beq .L21236 + cmp r2, #3 + beq .L21270 +.L21235: + mov r3, ip, asl #16 + mov r3, r3, lsr #16 + mov r2, #0 +.L21240: + strh r3, [r2, r5] @ movhi + add r2, r2, #2 + cmp r2, #480 + bne .L21240 + b .L21241 +.L21267: + mov r3, r0, lsr #6 + and r3, r3, #3 + cmp r3, #2 + beq .L21085 + cmp r3, #3 + beq .L21086 + cmp r3, #1 + beq .L21271 +.L21083: + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21140 + mov r2, #0 + mov r6, sp + mov r1, r2 +.L21142: + str r1, [r2, r6] + add r2, r2, #4 + cmp r2, #960 + bne .L21142 + ands r2, r4, #64 + bic r0, r3, #4 + beq .L21144 + mov r2, #240 + mov r3, sp + bl render_scanline_obj_partial_alpha_1D +.L21146: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21169 + ldr r8, .L21279+16 + and sl, r4, #64 + mov r7, #1 + b .L21149 +.L21272: + bl render_scanline_obj_partial_alpha_1D +.L21154: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bls .L21169 +.L21149: + ldr ip, [r8, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, sp + beq .L21150 + mov r1, #0 + bic ip, ip, #4 + cmp sl, r1 + mov r0, ip + bne .L21272 + mov r3, sp + mov r0, ip + mov r1, sl + mov r2, #240 + bl render_scanline_obj_partial_alpha_2D + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bhi .L21149 +.L21169: + mov r0, sp + mov r1, r5 + mov r2, #0 + mov r3, #240 + bl expand_blend + b .L21241 +.L21236: + tst r0, #32 + beq .L21235 + ldrh r3, [lr, #84] + ldr r1, .L21279+24 + and r3, r3, #31 + cmp r3, #16 + movcs r3, #16 + orr r2, ip, ip, asl #16 + and r1, r2, r1 + rsb r0, r3, #16 + rsb r2, r3, r3, asl #6 + mul ip, r1, r0 + add r3, r3, r2, asl #5 + rsb r3, r3, r3, asl #16 + ldr r1, .L21279+24 + mov r3, r3, lsr #4 + and r1, r3, r1 + ldr r2, .L21279+24 + add r1, r1, ip, lsr #4 + and r2, r1, r2 + orr ip, r2, r2, lsr #16 + b .L21235 +.L21085: + ldrh r3, [lr, #84] + tst r3, #31 + beq .L21083 + tst r0, #63 + beq .L21083 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21108 + mov r2, #0 + mov r6, sp + mov r1, r2 +.L21110: + str r1, [r2, r6] + add r2, r2, #4 + cmp r2, #960 + bne .L21110 + ands r2, r4, #64 + bic r0, r3, #4 + beq .L21112 + mov r2, #240 + mov r3, sp + bl render_scanline_obj_partial_alpha_1D +.L21114: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21115 + ldr r8, .L21279+16 + and sl, r4, #64 + mov r7, #1 + b .L21117 +.L21273: + bl render_scanline_obj_partial_alpha_1D +.L21122: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bls .L21115 +.L21117: + ldr ip, [r8, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, sp + beq .L21118 + mov r1, #0 + bic ip, ip, #4 + cmp sl, r1 + mov r0, ip + bne .L21273 + mov r0, ip + mov r1, sl + mov r2, #240 + mov r3, sp + bl render_scanline_obj_partial_alpha_2D + b .L21122 +.L21157: + ldrh r3, [lr, #84] + tst r3, #31 + beq .L21155 + tst r0, #63 + beq .L21155 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21179 + mov r2, ip +.L21181: + mov r1, #0 @ movhi + strh r1, [r2, r5] @ movhi + add r2, r2, #2 + cmp r2, #480 + bne .L21181 + ands r1, r4, #64 + bic r0, r3, #4 + beq .L21183 + mov r1, #0 + sub r2, r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_1D +.L21185: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21186 + ldr r7, .L21279+16 + and r8, r4, #64 + mov r6, #1 + b .L21188 +.L21274: + bl render_scanline_obj_color16_1D +.L21193: + ldr r3, [fp, #0] + add r6, r6, #1 + cmp r3, r6 + add r7, r7, #4 + bls .L21186 +.L21188: + ldr ip, [r7, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, r5 + beq .L21189 + mov r1, #0 + bic ip, ip, #4 + cmp r8, r1 + mov r0, ip + bne .L21274 + mov r0, ip + mov r1, r8 + mov r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_2D + b .L21193 +.L21230: + mov lr, pc + ldr pc, [r4, #4] + b .L21234 +.L21150: + mov lr, pc + ldr pc, [r4, #28] + b .L21154 +.L21270: + tst r0, #32 + beq .L21235 + ldrh r3, [lr, #84] + ldr r0, .L21279+24 + and r3, r3, #31 + orr r2, ip, ip, asl #16 + rsb r3, r3, #16 + and r0, r2, r0 + cmp r3, #0 + movlt r3, #0 + mul r1, r3, r0 + ldr r2, .L21279+24 + mov r1, r1, lsr #4 + and r2, r1, r2 + orr ip, r2, r2, lsr #16 + b .L21235 +.L21144: + mov r1, r2 + mov r3, sp + mov r2, #240 + bl render_scanline_obj_partial_alpha_2D + b .L21146 +.L21225: + mov r2, #240 + mov r3, r5 + bl render_scanline_obj_normal_2D + b .L21227 +.L21140: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, sp + mov r6, sp + mov lr, pc + ldr pc, [ip, #24] + b .L21146 +.L21221: + mov r0, ip + mov r2, #240 + mov r3, r5 + mov lr, pc + ldr pc, [r9, ip, asl #5] + b .L21227 +.L21086: + ldrh r3, [lr, #84] + tst r3, #31 + beq .L21083 + tst r0, #63 + beq .L21083 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21125 + mov r2, #0 + mov r6, sp + mov r1, r2 +.L21127: + str r1, [r2, r6] + add r2, r2, #4 + cmp r2, #960 + bne .L21127 + ands r2, r4, #64 + bic r0, r3, #4 + beq .L21129 + mov r2, #240 + mov r3, sp + bl render_scanline_obj_partial_alpha_1D +.L21131: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21132 + ldr r8, .L21279+16 + and sl, r4, #64 + mov r7, #1 + b .L21134 +.L21275: + bl render_scanline_obj_partial_alpha_1D +.L21139: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bls .L21132 +.L21134: + ldr ip, [r8, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, sp + beq .L21135 + mov r1, #0 + bic ip, ip, #4 + cmp sl, r1 + mov r0, ip + bne .L21275 + mov r0, ip + mov r1, sl + mov r2, #240 + mov r3, sp + bl render_scanline_obj_partial_alpha_2D + b .L21139 +.L21158: + ldrh r3, [lr, #84] + tst r3, #31 + beq .L21155 + tst r0, #63 + beq .L21155 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21201 + mov r2, #0 +.L21203: + mov r1, #0 @ movhi + strh r1, [r2, r5] @ movhi + add r2, r2, #2 + cmp r2, #480 + bne .L21203 + ands r1, r4, #64 + bic r0, r3, #4 + beq .L21205 + mov r1, #0 + sub r2, r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_1D +.L21207: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21208 + ldr r6, .L21279+16 + and r8, r4, #64 + mov r7, #1 + b .L21210 +.L21276: + bl render_scanline_obj_color16_1D +.L21215: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r6, r6, #4 + bls .L21208 +.L21210: + ldr ip, [r6, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, r5 + beq .L21211 + mov r1, #0 + bic ip, ip, #4 + cmp r8, r1 + mov r0, ip + bne .L21276 + mov r0, ip + mov r1, r8 + mov r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_2D + b .L21215 +.L21118: + mov lr, pc + ldr pc, [r4, #28] + b .L21122 +.L21189: + mov lr, pc + ldr pc, [r4, #20] + b .L21193 +.L21135: + mov lr, pc + ldr pc, [r4, #28] + b .L21139 +.L21211: + mov lr, pc + ldr pc, [r4, #20] + b .L21215 +.L21271: + ldrh r2, [lr, #82] + ldr r3, .L21279+28 + and r3, r2, r3 + cmp r3, #31 + beq .L21083 + tst r0, #63 + beq .L21083 + tst r0, #16128 + beq .L21083 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21090 + mov r2, #0 + mov r6, sp + mov r1, r2 +.L21092: + str r1, [r2, r6] + add r2, r2, #4 + cmp r2, #960 + bne .L21092 + ands r2, r4, #64 + bic r0, r3, #4 + beq .L21094 + mov r2, #240 + mov r3, sp + bl render_scanline_obj_alpha_obj_1D +.L21096: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21169 + ldr r8, .L21279+16 + and sl, r4, #64 + mov r7, #1 + b .L21099 +.L21277: + mov r1, #0 + bic ip, ip, #4 + cmp sl, r1 + mov r0, ip + beq .L21102 + bl render_scanline_obj_alpha_obj_1D +.L21104: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bls .L21169 +.L21099: + ldr ip, [r8, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, sp + bne .L21277 + mov lr, pc + ldr pc, [r4, #12] + b .L21104 +.L21268: + ldrh r2, [lr, #82] + ldr r3, .L21279+28 + and r3, r2, r3 + cmp r3, #31 + beq .L21155 + tst r0, #63 + beq .L21155 + tst r0, #16128 + beq .L21155 + ldr r3, .L21279+16 + ldr r3, [r3, #0] + ands r1, r3, #4 + beq .L21162 + mov r2, ip + mov r6, sp + mov r1, ip +.L21164: + str r1, [r2, r6] + add r2, r2, #4 + cmp r2, #960 + bne .L21164 + ands r2, r4, #64 + bic r0, r3, #4 + beq .L21166 + mov r2, #240 + mov r3, sp + bl render_scanline_obj_alpha_obj_1D +.L21168: + ldr r3, [fp, #0] + cmp r3, #1 + bls .L21169 + ldr r8, .L21279+16 + and sl, r4, #64 + mov r7, #1 + b .L21171 +.L21278: + mov r1, #0 + bic ip, ip, #4 + cmp sl, r1 + mov r0, ip + beq .L21174 + bl render_scanline_obj_alpha_obj_1D +.L21176: + ldr r3, [fp, #0] + add r7, r7, #1 + cmp r3, r7 + add r8, r8, #4 + bls .L21169 +.L21171: + ldr ip, [r8, #4] + mov r2, #240 + ands r1, ip, #4 + mov r0, ip + add r4, r9, ip, asl #5 + mov r3, sp + bne .L21278 + mov lr, pc + ldr pc, [r4, #12] + b .L21176 +.L21174: + mov r0, ip + mov r1, sl + mov r2, #240 + mov r3, sp + bl render_scanline_obj_alpha_obj_2D + b .L21176 +.L21102: + mov r0, ip + mov r1, sl + mov r2, #240 + mov r3, sp + bl render_scanline_obj_alpha_obj_2D + b .L21104 +.L21115: + mov r0, sp + mov r1, r5 + mov r2, #0 + mov r3, #240 + bl expand_brighten_partial_alpha + b .L21241 +.L21186: + ldrh r2, [sl, #84] + ldr r7, .L21279+24 + and r2, r2, #31 + cmp r2, #16 + movcs r2, #16 + rsb r3, r2, r2, asl #6 + add r3, r2, r3, asl #5 + rsb r3, r3, r3, asl #16 + mov r3, r3, lsr #4 + ldr r6, .L21279+20 + and r7, r3, r7 + rsb r4, r2, #16 + mov lr, #0 +.L21194: + ldrh r3, [r5, #0] + ldr ip, .L21279+24 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, r6] + mov r0, ip + orrne r3, r3, r3, asl #16 + andne ip, r3, ip + mulne r2, ip, r4 + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + addne r2, r7, r2, lsr #4 + andne r0, r2, r0 + ldreqh r1, [r1, r6] + orrne r3, r0, r0, lsr #16 + add lr, lr, #1 + strneh r3, [r5, #0] @ movhi + streqh r1, [r5, #0] @ movhi + cmp lr, #240 + add r5, r5, #2 + bne .L21194 + b .L21241 +.L21132: + mov r0, sp + mov r1, r5 + mov r2, #0 + mov r3, #240 + bl expand_darken_partial_alpha + b .L21241 +.L21208: + ldrh r3, [sl, #84] + ldr r6, .L21279+20 + and r3, r3, #31 + rsb r3, r3, #16 + cmp r3, #0 + movge r4, r3 + movlt r4, #0 + mov lr, #0 +.L21216: + ldrh r3, [r5, #0] + ldr ip, .L21279+24 + mov r2, r3, asl #23 + mov r2, r2, lsr #23 + tst r3, #512 + mov r2, r2, asl #1 + mov r1, r3, asl #23 + ldrneh r3, [r2, r6] + mov r0, ip + orrne r3, r3, r3, asl #16 + andne ip, r3, ip + mulne r2, r4, ip + mov r1, r1, lsr #23 + mov r1, r1, asl #1 + movne r2, r2, lsr #4 + andne r0, r2, r0 + ldreqh r1, [r1, r6] + orrne r3, r0, r0, lsr #16 + add lr, lr, #1 + strneh r3, [r5, #0] @ movhi + streqh r1, [r5, #0] @ movhi + cmp lr, #240 + add r5, r5, #2 + bne .L21216 + b .L21241 +.L21183: + mov r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_2D + b .L21185 +.L21179: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, r5 + mov lr, pc + ldr pc, [ip, #16] + b .L21185 +.L21205: + mov r2, #240 + mov r3, r5 + bl render_scanline_obj_color16_2D + b .L21207 +.L21201: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, r5 + mov lr, pc + ldr pc, [ip, #16] + b .L21207 +.L21129: + mov r1, r2 + mov r3, sp + mov r2, #240 + bl render_scanline_obj_partial_alpha_2D + b .L21131 +.L21125: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, sp + mov r6, sp + mov lr, pc + ldr pc, [ip, #24] + b .L21131 +.L21112: + mov r1, r2 + mov r3, sp + mov r2, #240 + bl render_scanline_obj_partial_alpha_2D + b .L21114 +.L21108: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, sp + mov r6, sp + mov lr, pc + ldr pc, [ip, #24] + b .L21114 +.L21166: + mov r1, r2 + mov r3, sp + mov r2, #240 + bl render_scanline_obj_alpha_obj_2D + b .L21168 +.L21094: + mov r1, r2 + mov r3, sp + mov r2, #240 + bl render_scanline_obj_alpha_obj_2D + b .L21096 +.L21162: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, sp + mov r6, sp + mov lr, pc + ldr pc, [ip, #8] + b .L21168 +.L21090: + mov r0, r3 + add ip, r9, r3, asl #5 + mov r2, #240 + mov r3, sp + mov r6, sp + mov lr, pc + ldr pc, [ip, #8] + b .L21096 +.L21280: + .align 2 +.L21279: + .word layer_count + .word io_registers + .word obj_alpha_count + .word tile_mode_renderers + .word layer_order + .word palette_ram_converted + .word 132184095 + .word 7967 + .size render_scanline_tile, .-render_scanline_tile + .align 2 + .global print_string_pad + .type print_string_pad, %function +print_string_pad: + @ args = 8, pretend = 0, frame = 16 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L21320 + sub sp, sp, #16 + ldr ip, .L21320+4 + ldr r5, [lr, #0] + ldr sl, [sp, #52] + ldr r4, [ip, #0] + str r0, [sp, #4] + add ip, sl, #10 + mov r2, r2, asl #16 + mov fp, r3 + ldrh r3, [r5, #16] + ldr r5, [r5, #20] + cmp ip, r4 + mov r4, r2, lsr #16 + ldr r2, [sp, #4] + mov r1, r1, asl #16 + str r5, [sp, #0] + mov r0, r1, lsr #16 + ldrb ip, [r2, #0] @ zero_extendqisi2 + bcs .L21313 + cmp ip, #0 + beq .L21313 + ldr r2, .L21320+8 + mov r9, r3, lsr #1 + ldr r2, [r2, #0] + mla r3, sl, r9, fp + add r1, r9, r9, asl #2 + str r2, [sp, #12] + ldr r2, [sp, #0] + mov r1, r1, asl #2 + str r1, [sp, #8] + add r6, r2, r3, asl #1 + mov r5, r9, asl #1 + mov r1, fp + mov r7, #0 + mov r8, #1 +.L21285: + cmp ip, #10 + beq .L21319 + ldr r3, .L21320+12 + mov lr, #0 + ldr r2, [r3, ip, asl #2] + ldr r3, .L21320+16 + mov ip, r6 + add r2, r3, r2, asl #1 +.L21289: + ldrh r3, [r2, #0] + add lr, lr, #1 + tst r3, #32768 + streqh r4, [ip, #0] @ movhi + strneh r0, [ip, #0] @ movhi + tst r3, #16384 + streqh r4, [ip, #2] @ movhi + strneh r0, [ip, #2] @ movhi + tst r3, #8192 + streqh r4, [ip, #4] @ movhi + strneh r0, [ip, #4] @ movhi + tst r3, #4096 + streqh r4, [ip, #6] @ movhi + strneh r0, [ip, #6] @ movhi + tst r3, #2048 + streqh r4, [ip, #8] @ movhi + strneh r0, [ip, #8] @ movhi + tst r3, #1024 + strneh r0, [ip, #10] @ movhi + streqh r4, [ip, #10] @ movhi + cmp lr, #10 + add ip, ip, r5 + add r2, r2, #2 + bne .L21289 + add r3, r6, r5 + add r2, r5, r5, asl #3 + add r3, r3, r2 + ldr r2, [sp, #8] + add r1, r1, #6 + rsb r3, r2, r3 + add r6, r3, #12 +.L21288: + ldr r3, [sp, #4] + ldr r2, [sp, #56] + ldrb ip, [r3, r8] @ zero_extendqisi2 + add r7, r7, #1 + cmp r2, r7 + movls r3, #0 + movhi r3, #1 + cmp ip, #0 + movne r3, #0 + ldr r2, [sp, #12] + cmp r3, #0 + add r3, r1, #6 + movne ip, #32 + addeq r8, r8, #1 + cmp r3, r2 + bcs .L21313 + cmp ip, #0 + bne .L21285 +.L21313: + add sp, sp, #16 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L21319: + add sl, sl, #10 + mla r3, sl, r9, fp + ldr r2, [sp, #0] + mov r1, fp + add r6, r2, r3, asl #1 + b .L21288 +.L21321: + .align 2 +.L21320: + .word screen + .word resolution_height + .word resolution_width + .word _font_offset + .word _font_bits + .size print_string_pad, .-print_string_pad + .align 2 + .global print_string + .type print_string, %function +print_string: + @ args = 4, pretend = 0, frame = 12 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L21358 + sub sp, sp, #12 + ldr ip, .L21358+4 + ldr r5, [lr, #0] + ldr r8, [sp, #48] + ldr r4, [ip, #0] + mov r9, r3 + ldrh r3, [r5, #16] + ldr r5, [r5, #20] + add ip, r8, #10 + cmp ip, r4 + mov fp, r0 + mov r1, r1, asl #16 + mov r2, r2, asl #16 + str r5, [sp, #0] + mov r0, r1, lsr #16 + mov r4, r2, lsr #16 + ldrb ip, [fp, #0] @ zero_extendqisi2 + bcs .L21352 + cmp ip, #0 + beq .L21352 + ldr r2, .L21358+8 + mov sl, r3, lsr #1 + ldr r2, [r2, #0] + mla r3, r8, sl, r9 + add r1, sl, sl, asl #2 + str r2, [sp, #8] + ldr r2, [sp, #0] + mov r1, r1, asl #2 + cmp ip, #10 + str r1, [sp, #4] + add r6, r2, r3, asl #1 + mov r5, sl, asl #1 + mov r1, r9 + mov r7, #1 + beq .L21357 +.L21327: + ldr r3, .L21358+12 + mov lr, #0 + ldr r2, [r3, ip, asl #2] + ldr r3, .L21358+16 + mov ip, r6 + add r2, r3, r2, asl #1 +.L21330: + ldrh r3, [r2, #0] + add lr, lr, #1 + tst r3, #32768 + streqh r4, [ip, #0] @ movhi + strneh r0, [ip, #0] @ movhi + tst r3, #16384 + streqh r4, [ip, #2] @ movhi + strneh r0, [ip, #2] @ movhi + tst r3, #8192 + streqh r4, [ip, #4] @ movhi + strneh r0, [ip, #4] @ movhi + tst r3, #4096 + streqh r4, [ip, #6] @ movhi + strneh r0, [ip, #6] @ movhi + tst r3, #2048 + streqh r4, [ip, #8] @ movhi + strneh r0, [ip, #8] @ movhi + tst r3, #1024 + strneh r0, [ip, #10] @ movhi + streqh r4, [ip, #10] @ movhi + cmp lr, #10 + add ip, ip, r5 + add r2, r2, #2 + bne .L21330 + add r3, r5, r6 + add r2, r5, r5, asl #3 + add r3, r3, r2 + ldr r2, [sp, #4] + add r1, r1, #6 + rsb r3, r2, r3 + ldr r2, [sp, #8] + add r6, r3, #12 + add r3, r1, #6 + cmp r3, r2 + ldrb ip, [r7, fp] @ zero_extendqisi2 + bcs .L21352 +.L21356: + cmp ip, #0 + beq .L21352 + cmp ip, #10 + add r7, r7, #1 + bne .L21327 +.L21357: + add r8, r8, #10 + mla r3, r8, sl, r9 + ldr r2, [sp, #0] + mov r1, r9 + add r6, r2, r3, asl #1 + ldr r2, [sp, #8] + add r3, r1, #6 + cmp r3, r2 + ldrb ip, [r7, fp] @ zero_extendqisi2 + bcc .L21356 +.L21352: + add sp, sp, #12 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L21359: + .align 2 +.L21358: + .word screen + .word resolution_height + .word resolution_width + .word _font_offset + .word _font_bits + .size print_string, .-print_string + .align 2 + .global render_scanline_obj_copy_bitmap_2D + .type render_scanline_obj_copy_bitmap_2D, %function +render_scanline_obj_copy_bitmap_2D: + @ args = 0, pretend = 0, frame = 596 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L22220 + add r0, r0, r0, asl #2 + ldrh r4, [lr, #6] + ldr ip, .L22220+4 + add r0, r4, r0, asl #5 + ldr ip, [ip, r0, asl #2] + sub sp, sp, #596 + ldrh r6, [lr, #0] + ldrh r5, [lr, #74] + str ip, [sp, #56] + cmp ip, #0 + ldr lr, .L22220+8 + ldr ip, .L22220+12 + str r4, [sp, #52] + and r4, r6, #7 + add r4, ip, r4, asl #2 + add r0, lr, r0, asl #7 + str r4, [sp, #40] + str r0, [sp, #60] + str r1, [sp, #16] + str r2, [sp, #12] + str r3, [sp, #8] + mov r5, r5, lsr #8 + beq .L22165 + and r7, r5, #16 + add ip, r3, r1, asl #1 + rsb lr, r1, r2 + mov r0, #0 + and r6, r6, #64 + and r5, r5, #4 + str r7, [sp, #76] + str r6, [sp, #80] + str r5, [sp, #84] + str ip, [sp, #88] + str lr, [sp, #108] + str r0, [sp, #44] + mov r1, r0 +.L21363: + ldr r2, [sp, #60] + ldr r4, .L22220+16 + ldrb r3, [r1, r2] @ zero_extendqisi2 + ldr ip, .L22220+20 + mov r3, r3, asl #3 + ldrh r8, [r3, r4] + add r3, r3, r4 + ldrh sl, [r3, #2] + mov r6, r8, lsr #12 + and r2, r6, #12 + orr r2, r2, sl, lsr #14 + ldr ip, [ip, r2, asl #2] + ands r7, r8, #512 + mov r1, sl, asl #23 + moveq lr, ip + mov r9, r1, asr #23 + str r7, [sp, #28] + ldr r7, [sp, #12] + addne r1, r9, ip, asl #1 + addeq r1, r9, lr + str r6, [sp, #24] + ldr r6, [sp, #16] + ldrh r3, [r3, #4] + cmp r1, r7 + movcc r7, r1 + ldr r0, [sp, #12] + ldr r1, [sp, #16] + cmp r9, r6 + movcs r6, r9 + str r3, [sp, #20] + cmp r0, r6 + movls r3, #0 + movhi r3, #1 + cmp r1, r7 + movcs r3, #0 + cmp r3, #0 + str r2, [sp, #48] + str ip, [sp, #112] + beq .L21367 + cmp r7, r6 + ldr r3, .L22220+24 + movls r4, r6, asl #1 + ldrh r0, [r3, #0] + strls r4, [sp, #0] + bls .L21369 + mov r2, r6, asl #1 + add r3, sp, #116 + str r2, [sp, #0] + rsb r1, r6, r7 + add r2, r3, r2 + mov r3, #0 +.L21371: + add r3, r3, #1 + cmp r1, r3 + strh r0, [r2], #2 @ movhi + bne .L21371 +.L21369: + ldr fp, .L22220+28 + ldr r3, [fp, #0] + cmp r3, #0 + beq .L21372 + ldr r5, .L22220+32 + mov r4, #0 + b .L21374 +.L22194: + ldr ip, [sp, #76] + cmp ip, #0 + bic ip, r0, #4 + beq .L21377 + ldr lr, [sp, #80] + mov r0, ip + cmp lr, #0 + mov r1, r6 + mov r2, r7 + add r3, sp, #116 + beq .L21379 + bl render_scanline_obj_normal_1D +.L21377: + ldr r3, [fp, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bls .L21372 +.L21374: + ldr r0, [r5, #0] + tst r0, #4 + bne .L22194 + ldr r0, [sp, #84] + mov r1, r7 + cmp r0, #0 + add r2, sp, #116 + mov r0, r6 + beq .L21377 + ldr r3, [sp, #40] + mov lr, pc + ldr pc, [r3, #0] + ldr r3, [fp, #0] + add r4, r4, #1 + cmp r3, r4 + add r5, r5, #4 + bhi .L21374 +.L21372: + and r0, r8, #255 + cmp r0, #160 + ldr r6, [sp, #0] + ldr r3, .L22220+36 + ldr r7, [sp, #48] + add r4, sp, #116 + subgt r0, r0, #256 + tst r8, #256 + add r5, r4, r6 + ldr fp, [r3, r7, asl #2] + beq .L21384 + tst r8, #8192 + beq .L21386 + mov r3, sl, lsr #4 + ldr ip, [sp, #28] + ldr lr, .L22220+16 + ldr r1, [sp, #112] + and r3, r3, #992 + cmp ip, #0 + add r3, r3, lr + add r2, r1, r1, lsr #31 + add r1, fp, fp, lsr #31 + ldrh r4, [r3, #30] + mov lr, r1, asr #1 + ldrne r6, [sp, #112] + ldr r1, [sp, #16] + mov ip, r2, asr #1 + str r4, [sp, #32] + moveq r7, ip + movne r4, r6, asl #1 + ldreq r4, [sp, #112] + moveq r6, lr + movne r7, ip, asl #1 + movne r6, lr, asl #1 + cmp r9, r1 + ldrh sl, [r3, #6] + ldrh r2, [r3, #14] + ldrh r8, [r3, #22] + bge .L21391 + rsb r1, r9, r1 + rsb r4, r1, r4 + cmp r4, #0 + ble .L21367 + ldr r9, [sp, #16] + rsb r7, r1, r7 +.L21391: + ldr r1, [sp, #12] + add r3, r9, r4 + cmp r3, r1 + blt .L21394 + rsb r4, r9, r1 + cmp r4, #0 + ble .L21367 +.L21394: + add r0, r0, r6 + ldr r6, [sp, #32] + mov r2, r2, asl #16 + mov ip, ip, asl #8 + mov r3, sl, asl #16 + mov r1, r6, asl #16 + str ip, [sp, #104] + mov r6, r2, asr #16 + mov ip, lr, asl #8 + ldr r2, [sp, #52] + ldr lr, [sp, #8] + mov r3, r3, asr #16 + cmp r8, #0 + str r3, [sp, #64] + mov r1, r1, asr #16 + add sl, lr, r9, asl #1 + rsb r0, r0, r2 + bne .L21396 + mla r3, r0, r1, ip + mov r1, r3, asr #8 + cmp r1, fp + bcs .L21367 + ldr ip, [sp, #20] + mov r2, r1, lsr #3 + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #2 + ldr r3, .L22220+40 + cmp r4, #0 + add r9, r3, r1, asl #3 + ble .L21367 + ldr r2, [sp, #64] + mul r3, r0, r6 + mul r2, r7, r2 + ldr lr, [sp, #104] + rsb r3, r2, r3 + add r0, lr, r3 + ldr r1, [sp, #112] + mov ip, r0, asr #8 + cmp ip, r1 + movcs lr, r8 + bcs .L21402 + b .L22216 +.L21403: + ldr r2, [sp, #112] + cmp ip, r2 + bcc .L22182 +.L21402: + ldr r3, [sp, #64] + add lr, lr, #1 + add r0, r0, r3 + cmp r4, lr + mov ip, r0, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bne .L21403 +.L21367: + ldr ip, [sp, #44] + ldr lr, [sp, #56] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #44] + beq .L22165 +.L22197: + ldr r1, [sp, #44] + b .L21363 +.L21379: + mov r0, ip + mov r1, r6 + mov r2, r7 + add r3, sp, #116 + bl render_scanline_obj_normal_2D + b .L21377 +.L21384: + ldr r3, [sp, #52] + tst sl, #8192 + rsb r0, r0, r3 + ldr r4, [sp, #24] + rsbne r3, r0, fp + subne r0, r3, #1 + mov r2, sl, asl #19 + and r3, r4, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L21367 + .p2align 2 +.L21464: + .word .L21460 + .word .L21461 + .word .L21462 + .word .L21463 +.L21386: + ldr r6, .L22220+16 + mov r3, sl, lsr #4 + and r3, r3, #992 + add r3, r3, r6 + ldr r7, [sp, #112] + ldr r4, [sp, #28] + ldrh ip, [r3, #30] + add r2, r7, r7, lsr #31 + cmp r4, #0 + add r1, fp, fp, lsr #31 + str ip, [sp, #36] + ldrh sl, [r3, #6] + mov ip, r2, asr #1 + ldrh r8, [r3, #22] + ldrh r2, [r3, #14] + ldr r3, [sp, #16] + mov lr, r1, asr #1 + movne r1, r7 + moveq r4, r7 + moveq r6, lr + moveq r7, ip + movne r4, r1, asl #1 + movne r7, ip, asl #1 + movne r6, lr, asl #1 + cmp r9, r3 + bge .L21423 + rsb r1, r9, r3 + rsb r4, r1, r4 + cmp r4, #0 + ble .L21367 + rsb r7, r1, r7 + mov r9, r3 +.L21423: + ldr r1, [sp, #12] + add r3, r9, r4 + cmp r3, r1 + blt .L21426 + rsb r4, r9, r1 + cmp r4, #0 + ble .L21367 +.L21426: + add r0, r0, r6 + ldr r6, [sp, #36] + mov r2, r2, asl #16 + mov ip, ip, asl #8 + mov r3, sl, asl #16 + mov r1, r6, asl #16 + str ip, [sp, #92] + mov r6, r2, asr #16 + mov ip, lr, asl #8 + ldr r2, [sp, #52] + ldr lr, [sp, #8] + mov r3, r3, asr #16 + cmp r8, #0 + str r3, [sp, #68] + mov r1, r1, asr #16 + add sl, lr, r9, asl #1 + rsb r0, r0, r2 + bne .L21428 + mla r3, r0, r1, ip + mov r1, r3, asr #8 + cmp r1, fp + bcs .L21367 + ldr ip, [sp, #20] + mov r2, r1, lsr #3 + mov r3, ip, asl #22 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r1, #7 + add r1, r1, r3, asl #3 + ldr r3, .L22220+40 + cmp r4, #0 + add r9, r3, r1, asl #2 + ble .L21367 + ldr r2, [sp, #68] + mul r3, r0, r6 + mul r2, r7, r2 + ldr lr, [sp, #92] + rsb r3, r2, r3 + ldr r1, [sp, #112] + add r0, lr, r3 + mov ip, r0, asr #8 + cmp ip, r1 + movcs r1, r8 + bcs .L21434 + b .L22217 +.L21435: + ldr r2, [sp, #112] + cmp ip, r2 + bcc .L22184 +.L21434: + ldr r3, [sp, #68] + add r1, r1, #1 + add r0, r0, r3 + cmp r4, r1 + mov ip, r0, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bne .L21435 + ldr ip, [sp, #44] + ldr lr, [sp, #56] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #44] + bne .L22197 +.L22165: + add sp, sp, #596 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L21437: + ldr r6, [sp, #112] + cmp ip, r6 + bcs .L21367 +.L22184: + mov r3, ip, asr #1 + and r6, r3, #3 + mov r3, ip, asr #3 + mov r3, r3, asl #5 + mov r2, ip, asr #1 + tst ip, #1 + and lr, r2, #3 + add ip, r3, r9 + add r2, r3, r9 + ldreqb r3, [r2, lr] @ zero_extendqisi2 + ldrneb r3, [ip, r6] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + cmp r2, #0 + ldrneh lr, [r5, #0] + ldr r7, [sp, #68] + add r1, r1, #1 + strneh lr, [sl, #0] @ movhi + add r0, r0, r7 + cmp r4, r1 + mov ip, r0, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bgt .L21437 + b .L21367 +.L21428: + ldr r2, [sp, #20] + cmp r4, #0 + mov r3, r2, asl #22 + ldr r2, .L22220+40 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + str r3, [sp, #96] + ble .L21367 + mov r3, r8, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #72] + mul r2, r0, r1 + mul r3, r0, r6 + ldr r1, [sp, #72] + ldr r0, [sp, #68] + mul r1, r7, r1 + mul r0, r7, r0 + ldr r6, [sp, #92] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r7, r6, r3 + ldr r0, [sp, #112] + add r6, ip, r2 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + cmp lr, r0 + cmpcc ip, fp + movcs r3, #0 + movcc r3, #1 + movcs r8, r3 + bcs .L21447 + b .L22218 +.L21448: + ldr r1, [sp, #112] + cmp lr, r1 + cmpcc ip, fp + bcc .L21449 +.L21447: + ldr r2, [sp, #68] + ldr r3, [sp, #72] + add r8, r8, #1 + add r7, r7, r2 + add r6, r6, r3 + cmp r4, r8 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bne .L21448 + b .L21367 +.L21405: + ldr r6, [sp, #112] + cmp ip, r6 + bcs .L21367 +.L22182: + mov r3, ip, asr #3 + and r1, ip, #7 + add r3, r9, r3, asl #6 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r7, [sp, #64] + cmp r2, #0 + ldrneh r1, [r5, #0] + add lr, lr, #1 + strneh r1, [sl, #0] @ movhi + add r0, r0, r7 + cmp r4, lr + mov ip, r0, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bgt .L21405 + b .L21367 +.L21396: + ldr r2, [sp, #20] + cmp r4, #0 + mov r3, r2, asl #22 + ldr r2, .L22220+40 + mov r3, r3, lsr #22 + add r3, r2, r3, asl #5 + str r3, [sp, #100] + ble .L21367 + mov r3, r8, asl #16 + mul r2, r0, r1 + mov r9, r3, asr #16 + mul r3, r0, r6 + ldr r0, [sp, #64] + mul r1, r9, r7 + mul r0, r7, r0 + ldr r6, [sp, #104] + rsb r3, r0, r3 + rsb r2, r1, r2 + add r7, r6, r3 + ldr r0, [sp, #112] + add r6, ip, r2 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + cmp lr, r0 + cmpcc ip, fp + movcs r3, #0 + movcc r3, #1 + movcs r8, r3 + bcs .L21412 + b .L22219 +.L21413: + ldr r1, [sp, #112] + cmp lr, r1 + cmpcc ip, fp + bcc .L21414 +.L21412: + ldr r2, [sp, #64] + add r8, r8, #1 + add r7, r7, r2 + add r6, r6, r9 + cmp r4, r8 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bne .L21413 + b .L21367 +.L21460: + ldr r6, [sp, #20] + mov r2, r0, lsr #3 + mov r3, r6, asl #22 + mov r3, r3, lsr #22 + add r3, r3, r2, asl #5 + and r1, r0, #7 + ldr r7, [sp, #16] + add r1, r1, r3, asl #3 + ldr r3, .L22220+40 + cmp r9, r7 + add r0, r3, r1, asl #2 + bge .L21465 + ldr r1, [sp, #112] + rsb ip, r9, r7 + rsb lr, ip, r1 + cmp lr, #0 + ble .L21367 + ldr r2, [sp, #12] + add r3, r9, r1 + cmp r2, r3 + bhi .L21468 + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + add r6, r0, r1 + bne .L21470 + ldr r8, [sp, #108] + ldr r7, [sp, #88] +.L21472: + movs lr, r8, lsr #3 + beq .L21489 + mov r1, r5 + mov r2, r7 + mov r0, r6 + mov ip, #0 +.L21491: + ldr r3, [r0, #0] + cmp r3, #0 + beq .L21492 + tst r3, #15 + ldrneh r4, [r1, #0] + strneh r4, [r2, #0] @ movhi + tst r3, #240 + ldrneh r4, [r1, #2] + strneh r4, [r2, #2] @ movhi + tst r3, #3840 + ldrneh r4, [r1, #4] + strneh r4, [r2, #4] @ movhi + tst r3, #61440 + ldrneh r4, [r1, #6] + strneh r4, [r2, #6] @ movhi + tst r3, #983040 + ldrneh r4, [r1, #8] + strneh r4, [r2, #8] @ movhi + tst r3, #15728640 + ldrneh r4, [r1, #10] + strneh r4, [r2, #10] @ movhi + tst r3, #251658240 + ldrneh r4, [r1, #12] + strneh r4, [r2, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [r1, #14] + strneh r3, [r2, #14] @ movhi +.L21492: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + bne .L21491 + mov r3, lr, asl #4 + add r7, r7, r3 + add r6, r6, lr, asl #5 + add r5, r5, r3 +.L21489: + ands r0, r8, #7 + beq .L21367 + ldr r3, [r6, #0] + mov r1, #0 +.L21511: + tst r3, #15 + mov r2, r1, asl #1 + ldrneh r4, [r2, r5] + add r1, r1, #1 + strneh r4, [r2, r7] @ movhi + cmp r1, r0 + mov r3, r3, lsr #4 + bne .L21511 + b .L21367 +.L21461: + ldr ip, [sp, #20] + ldr lr, [sp, #112] + mov r3, ip, asl #22 + mov r1, r0, lsr #3 + subs r2, lr, #8 + mov r3, r3, lsr #22 + submi r2, lr, #1 + add r3, r3, r1, asl #5 + add r3, r3, r2, asr #3 + and r1, r0, #7 + ldr r0, [sp, #16] + add r1, r1, r3, asl #3 + ldr r3, .L22220+40 + cmp r9, r0 + add r0, r3, r1, asl #2 + bge .L21595 + ldr r1, [sp, #16] + rsb ip, r9, r1 + rsb r1, ip, lr + cmp r1, #0 + ble .L21367 + ldr r2, [sp, #12] + add r3, r9, lr + cmp r2, r3 + bhi .L21598 + mov r3, ip, lsr #3 + ands r6, ip, #7 + sub r0, r0, r3, asl #5 + bne .L21600 + ldr r8, [sp, #108] + ldr r1, [sp, #88] +.L21602: + movs r3, r8, lsr #3 + beq .L21619 + mov lr, r5 + mov ip, r1 + mov r6, r0 + mov r7, #0 +.L21621: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L21622 + tst r2, #15 + ldrneh r4, [lr, #14] + strneh r4, [ip, #14] @ movhi + tst r2, #240 + ldrneh r4, [lr, #12] + strneh r4, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r4, [lr, #10] + strneh r4, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r4, [lr, #8] + strneh r4, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r4, [lr, #6] + strneh r4, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r4, [lr, #4] + strneh r4, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r4, [lr, #2] + strneh r4, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L21622: + add r7, r7, #1 + cmp r7, r3 + sub r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L21621 + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r1, r1, r3 + add r0, r0, r2, asl #5 + add r5, r5, r3 +.L21619: + ands ip, r8, #7 + beq .L21367 + ldr r0, [r0, #0] + mov r2, #0 +.L21641: + movs r3, r0, lsr #28 + mov r3, r2, asl #1 + ldrneh r4, [r3, r5] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L21641 + b .L21367 +.L21463: + ldr lr, [sp, #112] + ldr r3, [sp, #20] + subs r2, lr, #8 + submi r2, lr, #1 + mov r1, r3, asl #22 + mov r2, r2, asr #3 + mov r3, r0, lsr #3 + add r2, r2, r3, asl #4 + mov r1, r1, lsr #22 + and r3, r0, #7 + add r1, r1, r2, asl #1 + add r3, r3, r1, asl #2 + ldr r4, [sp, #16] + mov r0, r3, asl #3 + ldr r3, .L22220+40 + cmp r9, r4 + add r8, r0, r3 + bge .L21945 + rsb r0, r9, r4 + rsb lr, r0, lr + cmp lr, #0 + ble .L21367 + ldr r6, [sp, #112] + ldr r7, [sp, #12] + add r3, r9, r6 + cmp r7, r3 + bhi .L21948 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub sl, r8, r3, asl #6 + bne .L21950 + ldr r8, [sp, #108] + ldr r7, [sp, #88] +.L21952: + movs r6, r8, lsr #3 + beq .L22010 + mov r0, r5 + mov r1, r7 + mov ip, sl + mov lr, #0 +.L22012: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L22013 + tst r2, #255 + ldrneh r3, [r0, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #4] + mov r3, r2, lsr #16 + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrneh r3, [r0, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r4, [r0, #0] + strneh r4, [r1, #0] @ movhi +.L22013: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L22022 + tst r2, #255 + ldrneh r3, [r0, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #12] + mov r3, r2, lsr #16 + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrneh r3, [r0, #10] + strneh r3, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrneh r4, [r0, #8] + strneh r4, [r1, #8] @ movhi +.L22022: + add lr, lr, #1 + cmp lr, r6 + sub ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L22012 + mov r3, r6, asl #4 + rsb r2, r6, r6, asl #26 + add r7, r7, r3 + add sl, sl, r2, asl #6 + add r5, r5, r3 +.L22010: + ands ip, r8, #7 + beq .L21367 + cmp ip, #3 + ldrls r2, [sl, #4] + bls .L22045 + ldr r2, [sl, #4] + cmp r2, #0 + beq .L22035 + tst r2, #255 + ldrneh r6, [r5, #6] + mov r3, r2, lsr #8 + strneh r6, [r7, #6] @ movhi + tst r3, #255 + ldrneh lr, [r5, #4] + mov r3, r2, lsr #16 + strneh lr, [r7, #4] @ movhi + tst r3, #255 + ldrneh r0, [r5, #2] + strneh r0, [r7, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r1, [r5, #0] + strneh r1, [r7, #0] @ movhi +.L22035: + subs ip, ip, #4 + ldr r2, [sl, #0] + addne r7, r7, #8 + addne r5, r5, #8 + beq .L21367 +.L22045: + mov r1, #0 +.L22046: + movs r3, r2, lsr #24 + mov r0, r1, asl #1 + ldrneh r4, [r0, r5] + add r1, r1, #1 + strneh r4, [r0, r7] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L22046 + b .L21367 +.L21462: + ldr ip, [sp, #20] + mov r1, r0, lsr #3 + mov r2, ip, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r1, asl #5 + and r3, r0, #7 + add r3, r3, r2, asl #2 + ldr lr, [sp, #16] + mov r0, r3, asl #3 + ldr r3, .L22220+40 + cmp r9, lr + add r2, r0, r3 + bge .L21725 + ldr r1, [sp, #112] + rsb r0, r9, lr + rsb lr, r0, r1 + cmp lr, #0 + ble .L21367 + ldr r4, [sp, #12] + add r3, r9, r1 + cmp r4, r3 + bhi .L21728 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add sl, r2, r3, asl #6 + bne .L21730 + ldr r8, [sp, #108] + ldr r7, [sp, #88] +.L21732: + movs r6, r8, lsr #3 + beq .L21790 + mov r0, r5 + mov r1, r7 + mov ip, sl + mov lr, #0 +.L21792: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L21793 + tst r2, #255 + ldrneh r3, [r0, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #2] + mov r3, r2, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r3, [r0, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r4, [r0, #6] + strneh r4, [r1, #6] @ movhi +.L21793: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L21802 + tst r2, #255 + ldrneh r3, [r0, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #10] + mov r3, r2, lsr #16 + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrneh r3, [r0, #12] + strneh r3, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrneh r4, [r0, #14] + strneh r4, [r1, #14] @ movhi +.L21802: + add lr, lr, #1 + cmp lr, r6 + add ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L21792 + mov r3, r6, asl #4 + add r7, r7, r3 + add sl, sl, r6, asl #6 + add r5, r5, r3 +.L21790: + ands r0, r8, #7 + beq .L21367 + cmp r0, #3 + ldrls r3, [sl, #0] + bls .L21825 + ldr r2, [sl, #0] + cmp r2, #0 + beq .L21815 + tst r2, #255 + ldrneh r6, [r5, #0] + mov r3, r2, lsr #8 + strneh r6, [r7, #0] @ movhi + tst r3, #255 + ldrneh ip, [r5, #2] + mov r3, r2, lsr #16 + strneh ip, [r7, #2] @ movhi + tst r3, #255 + ldrneh lr, [r5, #4] + strneh lr, [r7, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r1, [r5, #6] + strneh r1, [r7, #6] @ movhi +.L21815: + subs r0, r0, #4 + ldr r3, [sl, #4] + addne r7, r7, #8 + addne r5, r5, #8 + beq .L21367 +.L21825: + mov r2, #0 +.L21826: + tst r3, #255 + mov r1, r2, asl #1 + ldrneh r4, [r1, r5] + add r2, r2, #1 + strneh r4, [r1, r7] @ movhi + cmp r0, r2 + mov r3, r3, lsr #8 + bhi .L21826 + b .L21367 +.L21725: + ldr ip, [sp, #112] + ldr lr, [sp, #12] + add r3, r9, ip + cmp lr, r3 + bls .L22200 + cmp ip, #0 + add r3, ip, #7 + movge r3, ip + movs r6, r3, asr #3 + beq .L21367 + ldr r7, [sp, #8] + ldr r3, .L22220+48 + add r1, r7, r9, asl #1 + add r0, r0, r3 + mov lr, #0 + b .L21925 +.L22201: + add r2, r2, #64 + add r1, r1, #16 + add r5, r5, #16 +.L21925: + ldr ip, [r2, #0] + cmp ip, #0 + beq .L21926 + tst ip, #255 + ldrneh r3, [r5, #0] + strneh r3, [r1, #0] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #2] + mov r3, ip, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r7, [r5, #4] + strneh r7, [r1, #4] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r5, #6] + strneh ip, [r1, #6] @ movhi +.L21926: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L21935 + tst ip, #255 + ldrneh r3, [r5, #8] + strneh r3, [r1, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #10] + mov r3, ip, lsr #16 + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrneh r7, [r5, #12] + strneh r7, [r1, #12] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r5, #14] + strneh ip, [r1, #14] @ movhi +.L21935: + add lr, lr, #1 + cmp r6, lr + add r0, r0, #64 + bne .L22201 + b .L21367 +.L21595: + ldr ip, [sp, #12] + add r3, r9, lr + cmp ip, r3 + mov r7, lr + bls .L22202 + cmp lr, #0 + add r3, lr, #7 + movge r3, lr + movs r3, r3, asr #3 + mov r6, lr + beq .L21367 + ldr r7, [sp, #8] + mov ip, #0 + add r1, r7, r9, asl #1 + b .L21706 +.L22221: + .align 2 +.L22220: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word bitmap_mode_renderers-12 + .word oam_ram + .word obj_width_table + .word palette_ram_converted + .word layer_count + .word layer_order + .word obj_height_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L22203: + sub r0, r0, #32 + add r1, r1, #16 + add r5, r5, #16 +.L21706: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L21707 + tst r2, #15 + ldrneh lr, [r5, #14] + strneh lr, [r1, #14] @ movhi + tst r2, #240 + ldrneh r4, [r5, #12] + strneh r4, [r1, #12] @ movhi + tst r2, #3840 + ldrneh r6, [r5, #10] + strneh r6, [r1, #10] @ movhi + tst r2, #61440 + ldrneh r7, [r5, #8] + strneh r7, [r1, #8] @ movhi + tst r2, #983040 + ldrneh lr, [r5, #6] + strneh lr, [r1, #6] @ movhi + tst r2, #15728640 + ldrneh r4, [r5, #4] + strneh r4, [r1, #4] @ movhi + tst r2, #251658240 + ldrneh r6, [r5, #2] + strneh r6, [r1, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r7, [r5, #0] + strneh r7, [r1, #0] @ movhi +.L21707: + add ip, ip, #1 + cmp r3, ip + bne .L22203 + b .L21367 +.L21465: + ldr r1, [sp, #112] + ldr r2, [sp, #12] + add r3, r9, r1 + cmp r2, r3 + bls .L22204 + cmp r1, #0 + add r3, r1, #7 + movge r3, r1 + movs r3, r3, asr #3 + mov r6, r1 + beq .L21367 + ldr r7, [sp, #8] + mov r2, #0 + add r1, r7, r9, asl #1 + b .L21576 +.L22205: + add r0, r0, #32 + add r1, r1, #16 + add r5, r5, #16 +.L21576: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L21577 + tst ip, #15 + ldrneh lr, [r5, #0] + strneh lr, [r1, #0] @ movhi + tst ip, #240 + ldrneh r4, [r5, #2] + strneh r4, [r1, #2] @ movhi + tst ip, #3840 + ldrneh r6, [r5, #4] + strneh r6, [r1, #4] @ movhi + tst ip, #61440 + ldrneh r7, [r5, #6] + strneh r7, [r1, #6] @ movhi + tst ip, #983040 + ldrneh lr, [r5, #8] + strneh lr, [r1, #8] @ movhi + tst ip, #15728640 + ldrneh r4, [r5, #10] + strneh r4, [r1, #10] @ movhi + tst ip, #251658240 + ldrneh r6, [r5, #12] + strneh r6, [r1, #12] @ movhi + movs ip, ip, lsr #28 + ldrneh r7, [r5, #14] + strneh r7, [r1, #14] @ movhi +.L21577: + add r2, r2, #1 + cmp r3, r2 + bne .L22205 + b .L21367 +.L21945: + add r3, r9, lr + mov ip, lr + ldr lr, [sp, #12] + cmp lr, r3 + bls .L22206 + cmp ip, #0 + add r3, ip, #7 + movge r3, ip + movs lr, r3, asr #3 + mov r7, ip + beq .L21367 + ldr ip, [sp, #8] + ldr r3, .L22220+44 + add r1, ip, r9, asl #1 + add r0, r0, r3 + mov r2, #0 + b .L22145 +.L22207: + sub r8, r8, #64 + add r1, r1, #16 + add r5, r5, #16 +.L22145: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L22146 + tst ip, #255 + ldrneh r3, [r5, #6] + strneh r3, [r1, #6] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #4] + mov r3, ip, lsr #16 + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrneh r6, [r5, #2] + strneh r6, [r1, #2] @ movhi + movs ip, ip, lsr #24 + ldrneh r7, [r5, #0] + strneh r7, [r1, #0] @ movhi +.L22146: + ldr ip, [r8, #0] + cmp ip, #0 + beq .L22155 + tst ip, #255 + ldrneh r3, [r5, #14] + strneh r3, [r1, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #12] + mov r3, ip, lsr #16 + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrneh r6, [r5, #10] + strneh r6, [r1, #10] @ movhi + movs ip, ip, lsr #24 + ldrneh r7, [r5, #8] + strneh r7, [r1, #8] @ movhi +.L22155: + add r2, r2, #1 + cmp lr, r2 + sub r0, r0, #64 + bne .L22207 + b .L21367 +.L22219: + mov r8, #0 +.L21414: + ldr r0, [sp, #112] + cmp ip, fp + cmpcc lr, r0 + bcc .L22183 + b .L21367 +.L21415: + ldr r3, [sp, #112] + cmp ip, fp + cmpcc lr, r3 + bcs .L21367 +.L22183: + and r3, ip, #7 + mov r2, lr, asr #3 + mov r3, r3, asl #3 + mov r1, ip, asr #3 + add r3, r3, r2, asl #6 + ldr r0, [sp, #64] + add r3, r3, r1, asl #10 + ldr r1, [sp, #100] + add r7, r7, r0 + add r3, r3, r1 + and r0, lr, #7 + ldrb r2, [r3, r0] @ zero_extendqisi2 + add r8, r8, #1 + cmp r2, #0 + ldrneh r2, [r5, #0] + add r6, r6, r9 + strneh r2, [sl, #0] @ movhi + cmp r4, r8 + mov ip, r6, asr #8 + mov lr, r7, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bgt .L21415 + b .L21367 +.L22218: + ldr r1, [sp, #112] + mov r8, #0 +.L21449: + cmp ip, fp + cmpcc lr, r1 + bcc .L22185 + b .L21367 +.L21450: + ldr r0, [sp, #112] + cmp ip, fp + cmpcc lr, r0 + bcs .L21367 +.L22185: + mov r3, lr, asr #1 + ldr r1, [sp, #96] + and r3, r3, #3 + and r0, ip, #7 + str r3, [sp, #4] + ldr r3, [sp, #96] + add r0, r1, r0, asl #2 + and r1, ip, #7 + mov r2, lr, asr #1 + add r1, r3, r1, asl #2 + mov r3, ip, asr #3 + and r9, r2, #3 + mov r3, r3, asl #10 + mov r2, lr, asr #3 + tst lr, #1 + add r3, r3, r2, asl #5 + add r2, r0, r3 + movne ip, r9 + add r0, r1, r3 + ldreqb r3, [r0, r9] @ zero_extendqisi2 + ldrneb r3, [r2, ip] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + cmp r0, #0 + ldrneh r2, [r5, #0] + ldr lr, [sp, #68] + ldr r1, [sp, #72] + add r8, r8, #1 + strneh r2, [sl, #0] @ movhi + add r7, r7, lr + add r6, r6, r1 + cmp r4, r8 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + add sl, sl, #2 + add r5, r5, #2 + bgt .L21450 + b .L21367 +.L22206: + rsb fp, r9, lr + cmp fp, #0 + ble .L21367 + ldr r2, [sp, #8] + movs sl, fp, lsr #3 + add r1, r2, r9, asl #1 + beq .L22104 + ldr r3, .L22220+44 + mov r6, r5 + add r0, r0, r3 + mov lr, r1 + mov r7, r8 + mov r2, #0 +.L22106: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L22107 + tst ip, #255 + ldrneh r3, [r6, #6] + strneh r3, [lr, #6] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #4] + mov r3, ip, lsr #16 + strneh r4, [lr, #4] @ movhi + tst r3, #255 + ldrneh r3, [r6, #2] + strneh r3, [lr, #2] @ movhi + movs ip, ip, lsr #24 + ldrneh r4, [r6, #0] + strneh r4, [lr, #0] @ movhi +.L22107: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L22116 + tst ip, #255 + ldrneh r3, [r6, #14] + strneh r3, [lr, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #12] + mov r3, ip, lsr #16 + strneh r4, [lr, #12] @ movhi + tst r3, #255 + ldrneh r3, [r6, #10] + strneh r3, [lr, #10] @ movhi + movs ip, ip, lsr #24 + ldrneh r4, [r6, #8] + strneh r4, [lr, #8] @ movhi +.L22116: + add r2, r2, #1 + cmp sl, r2 + sub r7, r7, #64 + add lr, lr, #16 + add r6, r6, #16 + sub r0, r0, #64 + bne .L22106 + mov r3, sl, asl #4 + rsb r2, sl, sl, asl #26 + add r1, r1, r3 + add r8, r8, r2, asl #6 + add r5, r5, r3 +.L22104: + ands ip, fp, #7 + beq .L21367 + cmp ip, #3 + ldrls r2, [r8, #4] + bls .L22139 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L22129 + tst r2, #255 + ldrneh r6, [r5, #6] + mov r3, r2, lsr #8 + strneh r6, [r1, #6] @ movhi + tst r3, #255 + ldrneh r7, [r5, #4] + mov r3, r2, lsr #16 + strneh r7, [r1, #4] @ movhi + tst r3, #255 + ldrneh lr, [r5, #2] + strneh lr, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r0, [r5, #0] + strneh r0, [r1, #0] @ movhi +.L22129: + subs ip, ip, #4 + ldr r2, [r8, #0] + addne r1, r1, #8 + addne r5, r5, #8 + beq .L21367 +.L22139: + mov r3, #0 +.L22140: + movs r4, r2, lsr #24 + mov r0, r3, asl #1 + ldrneh r6, [r0, r5] + add r3, r3, #1 + strneh r6, [r0, r1] @ movhi + cmp ip, r3 + mov r2, r2, asl #8 + bhi .L22140 + b .L21367 +.L22202: + rsb r8, r9, ip + cmp r8, #0 + ble .L21367 + ldr lr, [sp, #8] + movs r3, r8, lsr #3 + add r1, lr, r9, asl #1 + beq .L21679 + mov lr, r5 + mov ip, r1 + mov r6, r0 + mov r7, #0 +.L21681: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L21682 + tst r2, #15 + ldrneh r4, [lr, #14] + strneh r4, [ip, #14] @ movhi + tst r2, #240 + ldrneh r4, [lr, #12] + strneh r4, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r4, [lr, #10] + strneh r4, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r4, [lr, #8] + strneh r4, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r4, [lr, #6] + strneh r4, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r4, [lr, #4] + strneh r4, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r4, [lr, #2] + strneh r4, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r2, [lr, #0] + strneh r2, [ip, #0] @ movhi +.L21682: + add r7, r7, #1 + cmp r7, r3 + sub r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L21681 + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r1, r1, r3 + add r0, r0, r2, asl #5 + add r5, r5, r3 +.L21679: + ands ip, r8, #7 + beq .L21367 + ldr r0, [r0, #0] + mov r2, #0 +.L21701: + movs r3, r0, lsr #28 + mov r3, r2, asl #1 + ldrneh r4, [r3, r5] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L21701 + b .L21367 +.L22204: + rsb r8, r9, r2 + cmp r8, #0 + ble .L21367 + ldr r3, [sp, #8] + movs r7, r8, lsr #3 + add r1, r3, r9, asl #1 + beq .L21549 + mov lr, r5 + mov ip, r1 + mov r6, r0 + mov r2, #0 +.L21551: + ldr r3, [r6, #0] + cmp r3, #0 + beq .L21552 + tst r3, #15 + ldrneh r4, [lr, #0] + strneh r4, [ip, #0] @ movhi + tst r3, #240 + ldrneh r4, [lr, #2] + strneh r4, [ip, #2] @ movhi + tst r3, #3840 + ldrneh r4, [lr, #4] + strneh r4, [ip, #4] @ movhi + tst r3, #61440 + ldrneh r4, [lr, #6] + strneh r4, [ip, #6] @ movhi + tst r3, #983040 + ldrneh r4, [lr, #8] + strneh r4, [ip, #8] @ movhi + tst r3, #15728640 + ldrneh r4, [lr, #10] + strneh r4, [ip, #10] @ movhi + tst r3, #251658240 + ldrneh r4, [lr, #12] + strneh r4, [ip, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [lr, #14] + strneh r3, [ip, #14] @ movhi +.L21552: + add r2, r2, #1 + cmp r2, r7 + add r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L21551 + mov r3, r7, asl #4 + add r1, r1, r3 + add r0, r0, r7, asl #5 + add r5, r5, r3 +.L21549: + ands ip, r8, #7 + beq .L21367 + ldr r0, [r0, #0] + mov r2, #0 +.L21571: + tst r0, #15 + mov r3, r2, asl #1 + ldrneh r4, [r3, r5] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, lsr #4 + bne .L21571 + b .L21367 +.L22200: + rsb fp, r9, lr + cmp fp, #0 + ble .L21367 + ldr r3, [sp, #8] + movs sl, fp, lsr #3 + add r1, r3, r9, asl #1 + beq .L21884 + ldr r3, .L22220+48 + mov r6, r5 + add r0, r0, r3 + mov lr, r1 + mov r7, r2 + mov r8, #0 +.L21886: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L21887 + tst ip, #255 + ldrneh r4, [r6, #0] + mov r3, ip, lsr #8 + strneh r4, [lr, #0] @ movhi + tst r3, #255 + ldrneh r3, [r6, #2] + strneh r3, [lr, #2] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrneh r4, [r6, #4] + strneh r4, [lr, #4] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r6, #6] + strneh ip, [lr, #6] @ movhi +.L21887: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L21896 + tst ip, #255 + ldrneh r3, [r6, #8] + strneh r3, [lr, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #10] + mov r3, ip, lsr #16 + strneh r4, [lr, #10] @ movhi + tst r3, #255 + ldrneh r3, [r6, #12] + strneh r3, [lr, #12] @ movhi + movs ip, ip, lsr #24 + ldrneh r4, [r6, #14] + strneh r4, [lr, #14] @ movhi +.L21896: + add r8, r8, #1 + cmp r8, sl + add r7, r7, #64 + add lr, lr, #16 + add r6, r6, #16 + add r0, r0, #64 + bne .L21886 + mov r3, sl, asl #4 + add r1, r1, r3 + add r2, r2, sl, asl #6 + add r5, r5, r3 +.L21884: + ands ip, fp, #7 + beq .L21367 + cmp ip, #3 + ldrls r3, [r2, #0] + bls .L21919 + ldr r0, [r2, #0] + cmp r0, #0 + beq .L21909 + tst r0, #255 + ldrneh r6, [r5, #0] + mov r3, r0, lsr #8 + strneh r6, [r1, #0] @ movhi + tst r3, #255 + ldrneh r7, [r5, #2] + mov r3, r0, lsr #16 + strneh r7, [r1, #2] @ movhi + tst r3, #255 + ldrneh lr, [r5, #4] + strneh lr, [r1, #4] @ movhi + movs r0, r0, lsr #24 + ldrneh r0, [r5, #6] + strneh r0, [r1, #6] @ movhi +.L21909: + subs ip, ip, #4 + ldr r3, [r2, #4] + addne r1, r1, #8 + addne r5, r5, #8 + beq .L21367 +.L21919: + mov r2, #0 +.L21920: + tst r3, #255 + mov r0, r2, asl #1 + ldrneh r4, [r0, r5] + add r2, r2, #1 + strneh r4, [r0, r1] @ movhi + cmp ip, r2 + mov r3, r3, lsr #8 + bhi .L21920 + b .L21367 +.L21468: + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + ldreq r3, [sp, #88] + add ip, r0, r1 + bne .L22208 +.L21517: + movs r0, lr, lsr #3 + beq .L21367 + mov r1, #0 + b .L21527 +.L22209: + add ip, ip, #32 + add r3, r3, #16 + add r5, r5, #16 +.L21527: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L21528 + tst r2, #15 + ldrneh r4, [r5, #0] + strneh r4, [r3, #0] @ movhi + tst r2, #240 + ldrneh r6, [r5, #2] + strneh r6, [r3, #2] @ movhi + tst r2, #3840 + ldrneh r7, [r5, #4] + strneh r7, [r3, #4] @ movhi + tst r2, #61440 + ldrneh lr, [r5, #6] + strneh lr, [r3, #6] @ movhi + tst r2, #983040 + ldrneh r4, [r5, #8] + strneh r4, [r3, #8] @ movhi + tst r2, #15728640 + ldrneh r6, [r5, #10] + strneh r6, [r3, #10] @ movhi + tst r2, #251658240 + ldrneh r7, [r5, #12] + strneh r7, [r3, #12] @ movhi + movs r2, r2, lsr #28 + ldrneh lr, [r5, #14] + strneh lr, [r3, #14] @ movhi +.L21528: + add r1, r1, #1 + cmp r1, r0 + bne .L22209 + b .L21367 +.L21728: + ands r1, r0, #7 + mov r3, r0, lsr #3 + add r0, r2, r3, asl #6 + ldreq r1, [sp, #88] + bne .L22210 +.L21832: + movs lr, lr, lsr #3 + beq .L21367 + mov ip, #0 + b .L21861 +.L22211: + add r0, r0, #64 + add r1, r1, #16 + add r5, r5, #16 +.L21861: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L21862 + tst r2, #255 + ldrneh r3, [r5, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #2] + mov r3, r2, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r6, [r5, #4] + strneh r6, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #6] + strneh r7, [r1, #6] @ movhi +.L21862: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L21871 + tst r2, #255 + ldrneh r3, [r5, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #10] + mov r3, r2, lsr #16 + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrneh r6, [r5, #12] + strneh r6, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #14] + strneh r7, [r1, #14] @ movhi +.L21871: + add ip, ip, #1 + cmp ip, lr + bne .L22211 + b .L21367 +.L21948: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub r0, r8, r3, asl #6 + ldreq r1, [sp, #88] + bne .L22212 +.L22052: + movs lr, lr, lsr #3 + beq .L21367 + mov ip, #0 + b .L22081 +.L22213: + sub r0, r0, #64 + add r1, r1, #16 + add r5, r5, #16 +.L22081: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L22082 + tst r2, #255 + ldrneh r3, [r5, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #4] + mov r3, r2, lsr #16 + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrneh r6, [r5, #2] + strneh r6, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #0] + strneh r7, [r1, #0] @ movhi +.L22082: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22091 + tst r2, #255 + ldrneh r3, [r5, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #12] + mov r3, r2, lsr #16 + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrneh r6, [r5, #10] + strneh r6, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #8] + strneh r7, [r1, #8] @ movhi +.L22091: + add ip, ip, #1 + cmp ip, lr + bne .L22213 + b .L21367 +.L21598: + mov r3, ip, lsr #3 + ands r2, ip, #7 + sub r0, r0, r3, asl #5 + ldreq r3, [sp, #88] + bne .L22214 +.L21647: + movs r1, r1, lsr #3 + beq .L21367 + mov r2, #0 + b .L21657 +.L22215: + sub r0, r0, #32 + add r3, r3, #16 + add r5, r5, #16 +.L21657: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L21658 + tst ip, #15 + ldrneh r7, [r5, #14] + strneh r7, [r3, #14] @ movhi + tst ip, #240 + ldrneh lr, [r5, #12] + strneh lr, [r3, #12] @ movhi + tst ip, #3840 + ldrneh r4, [r5, #10] + strneh r4, [r3, #10] @ movhi + tst ip, #61440 + ldrneh r6, [r5, #8] + strneh r6, [r3, #8] @ movhi + tst ip, #983040 + ldrneh r7, [r5, #6] + strneh r7, [r3, #6] @ movhi + tst ip, #15728640 + ldrneh lr, [r5, #4] + strneh lr, [r3, #4] @ movhi + tst ip, #251658240 + ldrneh r4, [r5, #2] + strneh r4, [r3, #2] @ movhi + movs ip, ip, lsr #28 + ldrneh r6, [r5, #0] + strneh r6, [r3, #0] @ movhi +.L21658: + add r2, r2, #1 + cmp r2, r1 + bne .L22215 + b .L21367 +.L22214: + rsbs r6, r2, #8 + ldr ip, [r0, #0] + ldreq r3, [sp, #88] + beq .L21650 + mov r3, r2, asl #2 + mov r3, ip, asl r3 + mov lr, #0 +.L21651: + movs r7, r3, lsr #28 + mov ip, lr, asl #1 + ldrneh r4, [ip, r5] + ldrne r2, [sp, #88] + add lr, lr, #1 + strneh r4, [ip, r2] @ movhi + cmp lr, r6 + mov r3, r3, asl #4 + bne .L21651 + mov r3, r6, asl #1 + ldr r6, [sp, #88] + add r5, r5, r3 + add r3, r6, r3 +.L21650: + sub r0, r0, #32 + b .L21647 +.L22212: + cmp r2, #3 + rsb ip, r2, #8 + bls .L22053 + cmp ip, #0 + ldr r1, [r0, #0] + ldreq r1, [sp, #88] + beq .L22057 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L22058: + movs r6, r3, lsr #24 + mov r2, r1, asl #1 + ldrneh r4, [r2, r5] + ldrne r7, [sp, #88] + add r1, r1, #1 + strneh r4, [r2, r7] @ movhi + cmp r1, ip + mov r3, r3, asl #8 + bne .L22058 + ldr r6, [sp, #88] + mov r3, ip, asl #1 + add r5, r5, r3 + add r1, r6, r3 +.L22057: + sub r0, r0, #64 + b .L22052 +.L22210: + cmp r1, #3 + rsb ip, r1, #8 + bls .L21833 + cmp ip, #0 + ldr r2, [r0, #4] + ldreq r1, [sp, #88] + beq .L21837 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r3, r2, lsr r3 + mov r1, #0 +.L21838: + tst r3, #255 + mov r2, r1, asl #1 + ldrneh r7, [r2, r5] + ldrne r6, [sp, #88] + add r1, r1, #1 + strneh r7, [r2, r6] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L21838 + mov r3, ip, asl #1 + ldr ip, [sp, #88] + add r5, r5, r3 + add r1, ip, r3 +.L21837: + add r0, r0, #64 + b .L21832 +.L22208: + rsbs r6, r3, #8 + ldr r0, [r0, r1] + ldreq r3, [sp, #88] + beq .L21520 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L21521: + tst r0, #15 + mov r3, r2, asl #1 + ldrneh r1, [r3, r5] + ldrne r7, [sp, #88] + add r2, r2, #1 + strneh r1, [r3, r7] @ movhi + cmp r6, r2 + mov r0, r0, lsr #4 + bne .L21521 + ldr r2, [sp, #88] + mov r3, r6, asl #1 + add r5, r5, r3 + add r3, r2, r3 +.L21520: + add ip, ip, #32 + b .L21517 +.L21950: + ldr lr, [sp, #108] + rsb r0, ip, #8 + cmp lr, r0 + bge .L21953 + cmp lr, #0 + ble .L21367 + cmp ip, #3 + bls .L21956 + ldr r2, [sl, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L21959: + movs r0, r2, lsr #24 + mov r3, r1, asl #1 + ldrneh r6, [r3, r5] + ldrne r4, [sp, #88] + ldr r7, [sp, #108] + add r1, r1, #1 + strneh r6, [r3, r4] @ movhi + cmp r7, r1 + mov r2, r2, asl #8 + bne .L21959 + b .L21367 +.L21730: + ldr r6, [sp, #108] + rsb r0, ip, #8 + cmp r6, r0 + bge .L21733 + cmp r6, #0 + ble .L21367 + cmp ip, #3 + bls .L21736 + ldr r2, [sl, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L21739: + tst r1, #255 + mov r3, r2, asl #1 + ldrneh ip, [r3, r5] + ldrne r7, [sp, #88] + ldr lr, [sp, #108] + add r2, r2, #1 + strneh ip, [r3, r7] @ movhi + cmp lr, r2 + mov r1, r1, lsr #8 + bne .L21739 + b .L21367 +.L21470: + ldr r4, [sp, #108] + rsb ip, r3, #8 + cmp r4, ip + bge .L21473 + cmp r4, #0 + ble .L21367 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L21477: + tst r0, #15 + mov r3, r2, asl #1 + ldrneh r7, [r3, r5] + ldrne r6, [sp, #88] + ldr ip, [sp, #108] + add r2, r2, #1 + strneh r7, [r3, r6] @ movhi + cmp ip, r2 + mov r0, r0, lsr #4 + bne .L21477 + b .L21367 +.L21600: + ldr r3, [sp, #108] + rsb lr, r6, #8 + cmp r3, lr + bge .L21603 + cmp r3, #0 + ble .L21367 + ldr r2, [r0, #0] + mov r3, r6, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L21607: + movs r4, r0, lsr #28 + mov r3, r2, asl #1 + ldrneh r7, [r3, r5] + ldrne r6, [sp, #88] + ldr ip, [sp, #108] + add r2, r2, #1 + strneh r7, [r3, r6] @ movhi + cmp ip, r2 + mov r0, r0, asl #4 + bne .L21607 + b .L21367 +.L22053: + subs r6, ip, #4 + ldr r1, [r0, #4] + ldreq r1, [sp, #88] + beq .L22065 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L22066: + movs r7, r3, lsr #24 + mov r2, r1, asl #1 + ldrneh r7, [r2, r5] + ldrne r4, [sp, #88] + add r1, r1, #1 + strneh r7, [r2, r4] @ movhi + cmp r1, r6 + mov r3, r3, asl #8 + bne .L22066 + mov r3, ip, asl #1 + ldr ip, [sp, #88] + add r2, r5, r3 + add r3, ip, r3 + sub r5, r2, #8 + sub r1, r3, #8 +.L22065: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22071 + tst r2, #255 + ldrneh r3, [r5, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #4] + mov r3, r2, lsr #16 + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrneh r6, [r5, #2] + strneh r6, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #0] + strneh r7, [r1, #0] @ movhi +.L22071: + add r1, r1, #8 + add r5, r5, #8 + sub r0, r0, #64 + b .L22052 +.L21833: + subs r6, ip, #4 + ldr r2, [r0, #0] + ldreq r1, [sp, #88] + beq .L21845 + mov r3, r1, asl #3 + mov r3, r2, lsr r3 + mov r1, #0 +.L21846: + tst r3, #255 + mov r2, r1, asl #1 + ldrneh r7, [r2, r5] + ldrne r4, [sp, #88] + add r1, r1, #1 + strneh r7, [r2, r4] @ movhi + cmp r1, r6 + mov r3, r3, lsr #8 + bne .L21846 + mov r3, ip, asl #1 + ldr ip, [sp, #88] + add r2, r5, r3 + add r3, ip, r3 + sub r5, r2, #8 + sub r1, r3, #8 +.L21845: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L21851 + tst r2, #255 + ldrneh r3, [r5, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #2] + mov r3, r2, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r6, [r5, #4] + strneh r6, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #6] + strneh r7, [r1, #6] @ movhi +.L21851: + add r1, r1, #8 + add r5, r5, #8 + add r0, r0, #64 + b .L21832 +.L21733: + cmp ip, #3 + bls .L21763 + cmp r0, #0 + ldr r2, [sl, #4] + ldreq r7, [sp, #88] + beq .L21767 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L21768: + tst r1, #255 + mov r3, r2, asl #1 + ldrneh r4, [r3, r5] + ldrne lr, [sp, #88] + add r2, r2, #1 + strneh r4, [r3, lr] @ movhi + cmp r0, r2 + mov r1, r1, lsr #8 + bne .L21768 + ldr r6, [sp, #88] + mov r3, r0, asl #1 + add r5, r5, r3 + add r7, r3, r6 +.L21767: + ldr ip, [sp, #108] + add sl, sl, #64 + rsb r8, r0, ip + b .L21732 +.L21473: + cmp ip, #0 + ldr r2, [r6, #0] + ldreq r7, [sp, #88] + beq .L21483 + mov r3, r3, asl #2 + mov r3, r2, lsr r3 + mov r1, #0 +.L21484: + tst r3, #15 + mov r2, r1, asl #1 + ldrneh r0, [r2, r5] + ldrne lr, [sp, #88] + add r1, r1, #1 + strneh r0, [r2, lr] @ movhi + cmp ip, r1 + mov r3, r3, lsr #4 + bne .L21484 + ldr r1, [sp, #88] + mov r3, ip, asl #1 + add r5, r5, r3 + add r7, r3, r1 +.L21483: + ldr r2, [sp, #108] + add r6, r6, #32 + rsb r8, ip, r2 + b .L21472 +.L21603: + cmp lr, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #88] + beq .L21613 + mov r3, r6, asl #2 + mov r3, r2, asl r3 + mov ip, #0 +.L21614: + movs r1, r3, lsr #28 + mov r2, ip, asl #1 + ldrneh r6, [r2, r5] + ldrne r4, [sp, #88] + add ip, ip, #1 + strneh r6, [r2, r4] @ movhi + cmp lr, ip + mov r3, r3, asl #4 + bne .L21614 + ldr r7, [sp, #88] + mov r3, lr, asl #1 + add r5, r5, r3 + add r1, r3, r7 +.L21613: + ldr ip, [sp, #108] + sub r0, r0, #32 + rsb r8, lr, ip + b .L21602 +.L21953: + cmp ip, #3 + bls .L21983 + cmp r0, #0 + ldr r2, [sl, #0] + ldreq r7, [sp, #88] + beq .L21987 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L21988: + movs r2, r3, lsr #24 + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r4, [sp, #88] + add r1, r1, #1 + strneh r6, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, asl #8 + bne .L21988 + ldr ip, [sp, #88] + mov r3, r0, asl #1 + add r5, r5, r3 + add r7, ip, r3 +.L21987: + ldr r6, [sp, #108] + sub sl, sl, #64 + rsb r8, r0, r6 + b .L21952 +.L22217: + mov r1, r8 + b .L22184 +.L22216: + mov lr, r8 + b .L22182 +.L21983: + subs lr, r0, #4 + ldr r2, [sl, #4] + ldreq r1, [sp, #88] + beq .L21995 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L21996: + movs r2, r3, lsr #24 + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r4, [sp, #88] + add r1, r1, #1 + strneh r6, [r2, r4] @ movhi + cmp r1, lr + mov r3, r3, asl #8 + bne .L21996 + ldr r7, [sp, #88] + mov r3, r0, asl #1 + add r2, r5, r3 + add r3, r7, r3 + sub r5, r2, #8 + sub r1, r3, #8 +.L21995: + ldr r2, [sl, #0] + cmp r2, #0 + beq .L22001 + tst r2, #255 + ldrneh ip, [r5, #6] + mov r3, r2, lsr #8 + strneh ip, [r1, #6] @ movhi + tst r3, #255 + ldrneh lr, [r5, #4] + mov r3, r2, lsr #16 + strneh lr, [r1, #4] @ movhi + tst r3, #255 + ldrneh r3, [r5, #2] + strneh r3, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r4, [r5, #0] + strneh r4, [r1, #0] @ movhi +.L22001: + add r7, r1, #8 + add r5, r5, #8 + b .L21987 +.L21763: + subs lr, r0, #4 + ldr r2, [sl, #0] + ldreq r1, [sp, #88] + beq .L21775 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L21776: + tst r1, #255 + mov r3, r2, asl #1 + ldrneh ip, [r3, r5] + ldrne r7, [sp, #88] + add r2, r2, #1 + strneh ip, [r3, r7] @ movhi + cmp r2, lr + mov r1, r1, lsr #8 + bne .L21776 + ldr lr, [sp, #88] + mov r3, r0, asl #1 + add r2, r5, r3 + add r3, lr, r3 + sub r5, r2, #8 + sub r1, r3, #8 +.L21775: + ldr r2, [sl, #4] + cmp r2, #0 + beq .L21781 + tst r2, #255 + ldrneh r3, [r5, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r5, #2] + mov r3, r2, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r6, [r5, #4] + strneh r6, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r7, [r5, #6] + strneh r7, [r1, #6] @ movhi +.L21781: + add r7, r1, #8 + add r5, r5, #8 + b .L21767 +.L21956: + ldr lr, [sp, #108] + mov r3, ip, asl #3 + ldr r1, [sl, #4] + add r2, lr, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L21963 + cmp lr, #0 + movne r2, #0 + beq .L21367 +.L21979: + movs r6, r1, lsr #24 + mov r3, r2, asl #1 + ldrneh ip, [r3, r5] + ldrne r7, [sp, #88] + ldr lr, [sp, #108] + add r2, r2, #1 + strneh ip, [r3, r7] @ movhi + cmp lr, r2 + mov r1, r1, asl #8 + bne .L21979 + b .L21367 +.L21736: + ldr r0, [sp, #108] + ldr r3, [sl, #0] + add r2, r0, ip + mov r1, ip, asl #3 + cmp r2, #4 + mov r3, r3, lsr r1 + bhi .L21743 + cmp r0, #0 + movne r1, #0 + beq .L21367 +.L21759: + tst r3, #255 + mov r2, r1, asl #1 + ldrneh r7, [r2, r5] + ldrne r6, [sp, #88] + ldr ip, [sp, #108] + add r1, r1, #1 + strneh r7, [r2, r6] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L21759 + b .L21367 +.L21963: + rsbs r2, ip, #4 + ldreq r3, [sp, #88] + beq .L21968 + mov r0, #0 +.L21969: + movs r3, r1, lsr #24 + mov r3, r0, asl #1 + ldrneh r6, [r3, r5] + ldrne r4, [sp, #88] + add r0, r0, #1 + strneh r6, [r3, r4] @ movhi + cmp r0, r2 + mov r1, r1, asl #8 + bne .L21969 + ldr r7, [sp, #88] + mov r3, r2, asl #1 + add r5, r5, r3 + add r3, r3, r7 +.L21968: + ldr lr, [sp, #108] + subs ip, lr, r2 + ldr r2, [sl, #0] + beq .L21367 + mov r0, #0 +.L21975: + movs r1, r2, lsr #24 + mov r1, r0, asl #1 + ldrneh r4, [r1, r5] + add r0, r0, #1 + strneh r4, [r1, r3] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L21975 + b .L21367 +.L21743: + rsbs r1, ip, #4 + ldreq ip, [sp, #88] + beq .L21748 + mov r0, #0 +.L21749: + tst r3, #255 + mov r2, r0, asl #1 + ldrneh r6, [r2, r5] + ldrne r4, [sp, #88] + add r0, r0, #1 + strneh r6, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, lsr #8 + bne .L21749 + ldr r7, [sp, #88] + mov r3, r1, asl #1 + add r5, r5, r3 + add ip, r3, r7 +.L21748: + ldr lr, [sp, #108] + ldr r3, [sl, #4] + subs r0, lr, r1 + beq .L21367 + mov r1, #0 +.L21755: + tst r3, #255 + mov r2, r1, asl #1 + ldrneh r4, [r2, r5] + add r1, r1, #1 + strneh r4, [r2, ip] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L21755 + b .L21367 + .size render_scanline_obj_copy_bitmap_2D, .-render_scanline_obj_copy_bitmap_2D + .align 2 + .global render_scanline_obj_copy_bitmap_1D + .type render_scanline_obj_copy_bitmap_1D, %function +render_scanline_obj_copy_bitmap_1D: + @ args = 0, pretend = 0, frame = 604 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L23084 + add r0, r0, r0, asl #2 + ldrh r4, [lr, #6] + ldr ip, .L23084+4 + add r0, r4, r0, asl #5 + ldr ip, [ip, r0, asl #2] + sub sp, sp, #604 + ldrh r6, [lr, #0] + ldrh r5, [lr, #74] + str ip, [sp, #56] + cmp ip, #0 + ldr lr, .L23084+8 + ldr ip, .L23084+12 + str r4, [sp, #52] + and r4, r6, #7 + add r4, ip, r4, asl #2 + add r0, lr, r0, asl #7 + str r4, [sp, #36] + str r0, [sp, #60] + str r1, [sp, #12] + str r2, [sp, #8] + str r3, [sp, #4] + mov r5, r5, lsr #8 + beq .L23027 + rsb r0, r1, r2 + and ip, r5, #16 + add lr, r3, r1, asl #1 + and r6, r6, #64 + mov r1, #0 + and r5, r5, #4 + str ip, [sp, #88] + str r6, [sp, #92] + str r5, [sp, #96] + str lr, [sp, #100] + str r0, [sp, #120] + str r1, [sp, #44] + mov r2, r1 +.L22225: + ldr r4, [sp, #60] + ldr r5, .L23084+16 + ldrb r3, [r2, r4] @ zero_extendqisi2 + ldr lr, .L23084+20 + mov r3, r3, asl #3 + ldrh r8, [r3, r5] + add r3, r3, r5 + ldrh sl, [r3, #2] + mov r6, r8, lsr #12 + and r2, r6, #12 + orr r2, r2, sl, lsr #14 + mov r1, sl, asl #23 + ldr fp, [lr, r2, asl #2] + ands ip, r8, #512 + mov r9, r1, asr #23 + ldr r7, [sp, #8] + addne r1, r9, fp, asl #1 + addeq r1, r9, fp + str r6, [sp, #20] + ldr r6, [sp, #12] + ldrh r3, [r3, #4] + cmp r1, r7 + movcc r7, r1 + ldr r0, [sp, #8] + ldr r1, [sp, #12] + cmp r9, r6 + movcs r6, r9 + str r3, [sp, #16] + cmp r0, r6 + movls r3, #0 + movhi r3, #1 + cmp r1, r7 + movcs r3, #0 + cmp r3, #0 + str r2, [sp, #48] + str ip, [sp, #24] + beq .L22229 + cmp r7, r6 + ldr r3, .L23084+24 + movls r4, r6, asl #1 + ldrh r0, [r3, #0] + strls r4, [sp, #0] + bls .L22231 + mov r2, r6, asl #1 + add r3, sp, #124 + str r2, [sp, #0] + rsb r1, r6, r7 + add r2, r3, r2 + mov r3, #0 +.L22233: + add r3, r3, #1 + cmp r1, r3 + strh r0, [r2], #2 @ movhi + bne .L22233 +.L22231: + ldr r5, .L23084+28 + ldr r3, [r5, #0] + cmp r3, #0 + beq .L22234 + ldr r5, .L23084+32 + mov r4, #0 + b .L22236 +.L23056: + ldr ip, [sp, #88] + cmp ip, #0 + bic ip, r0, #4 + beq .L22239 + ldr lr, [sp, #92] + mov r0, ip + cmp lr, #0 + mov r1, r6 + mov r2, r7 + add r3, sp, #124 + beq .L22241 + bl render_scanline_obj_normal_1D +.L22239: + ldr ip, .L23084+28 + add r4, r4, #1 + ldr r3, [ip, #0] + add r5, r5, #4 + cmp r3, r4 + bls .L22234 +.L22236: + ldr r0, [r5, #0] + tst r0, #4 + bne .L23056 + ldr r0, [sp, #96] + mov r1, r7 + cmp r0, #0 + add r2, sp, #124 + mov r0, r6 + beq .L22239 + ldr r3, [sp, #36] + mov lr, pc + ldr pc, [r3, #0] + ldr ip, .L23084+28 + add r4, r4, #1 + ldr r3, [ip, #0] + add r5, r5, #4 + cmp r3, r4 + bhi .L22236 +.L22234: + and r0, r8, #255 + ldr r1, [sp, #0] + cmp r0, #160 + add lr, sp, #124 + ldr r3, .L23084+36 + ldr r2, [sp, #48] + add lr, lr, r1 + subgt r0, r0, #256 + tst r8, #256 + str lr, [sp, #40] + ldr r4, [r3, r2, asl #2] + beq .L22246 + tst r8, #8192 + beq .L22248 + ldr r6, .L23084+16 + mov r3, sl, lsr #4 + ldr r5, [sp, #24] + add r1, r4, r4, lsr #31 + and r3, r3, #992 + add r3, r3, r6 + mov lr, r1, asr #1 + add r2, fp, fp, lsr #31 + ldr r1, [sp, #12] + cmp r5, #0 + mov ip, r2, asr #1 + ldrh sl, [r3, #30] + ldrh r8, [r3, #6] + ldrh r2, [r3, #14] + ldrh r3, [r3, #22] + moveq r5, fp + moveq r7, ip + moveq r6, lr + movne r5, fp, asl #1 + movne r7, ip, asl #1 + movne r6, lr, asl #1 + cmp r9, r1 + str r3, [sp, #28] + bge .L22253 + rsb r1, r9, r1 + rsb r5, r1, r5 + cmp r5, #0 + ble .L22229 + ldr r9, [sp, #12] + rsb r7, r1, r7 +.L22253: + ldr r1, [sp, #8] + add r3, r9, r5 + cmp r3, r1 + blt .L22256 + rsb r5, r9, r1 + cmp r5, #0 + ble .L22229 +.L22256: + add r0, r0, r6 + ldr r6, [sp, #28] + mov r1, sl, asl #16 + mov ip, ip, asl #8 + mov r3, r8, asl #16 + cmp r6, #0 + str ip, [sp, #116] + mov r6, r1, asr #16 + mov ip, lr, asl #8 + ldr r1, [sp, #52] + ldr lr, [sp, #4] + mov r2, r2, asl #16 + mov r3, r3, asr #16 + add sl, lr, r9, asl #1 + str r3, [sp, #64] + mov r8, r2, asr #16 + rsb lr, r0, r1 + bne .L22258 + mla r3, lr, r6, ip + mov r0, r3, asr #8 + cmp r0, r4 + bcs .L22229 + cmp fp, #0 + ldr r4, [sp, #16] + add r3, fp, #7 + movge r3, fp + mov r3, r3, asr #3 + mov r2, r4, asl #22 + mov r3, r3, asl #1 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L23084+40 + add r0, r0, ip, asl #2 + cmp r5, #0 + add r6, r3, r0, asl #3 + ble .L22229 + ldr r2, [sp, #64] + mul r3, lr, r8 + mul r2, r7, r2 + ldr ip, [sp, #116] + rsb r3, r2, r3 + add r0, ip, r3 + mov ip, r0, asr #8 + cmp ip, fp + ldrcs lr, [sp, #28] + bcs .L22264 + b .L23080 +.L22265: + cmp ip, fp + bcc .L23044 +.L22264: + ldr r2, [sp, #40] + ldr r1, [sp, #64] + add lr, lr, #1 + add r0, r0, r1 + add r2, r2, #2 + cmp r5, lr + mov ip, r0, asr #8 + add sl, sl, #2 + str r2, [sp, #40] + bne .L22265 +.L22229: + ldr ip, [sp, #44] + ldr lr, [sp, #56] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #44] + beq .L23027 +.L23059: + ldr r2, [sp, #44] + b .L22225 +.L22241: + mov r0, ip + mov r1, r6 + mov r2, r7 + add r3, sp, #124 + bl render_scanline_obj_normal_2D + b .L22239 +.L22246: + ldr lr, [sp, #52] + tst sl, #8192 + rsb ip, r0, lr + ldr r0, [sp, #20] + rsbne r3, ip, r4 + subne ip, r3, #1 + mov r2, sl, asl #19 + and r3, r0, #2 + orr r3, r3, r2, lsr #31 + cmp r3, #3 + ldrls pc, [pc, r3, asl #2] + b .L22229 + .p2align 2 +.L22326: + .word .L22322 + .word .L22323 + .word .L22324 + .word .L22325 +.L22248: + ldr r6, .L23084+16 + mov r3, sl, lsr #4 + ldr r5, [sp, #24] + add r1, r4, r4, lsr #31 + and r3, r3, #992 + add r3, r3, r6 + mov lr, r1, asr #1 + add r2, fp, fp, lsr #31 + ldr r1, [sp, #12] + cmp r5, #0 + mov ip, r2, asr #1 + ldrh sl, [r3, #30] + ldrh r8, [r3, #6] + ldrh r2, [r3, #14] + ldrh r3, [r3, #22] + moveq r5, fp + moveq r7, ip + moveq r6, lr + movne r5, fp, asl #1 + movne r7, ip, asl #1 + movne r6, lr, asl #1 + cmp r9, r1 + str r3, [sp, #32] + bge .L22285 + rsb r1, r9, r1 + rsb r5, r1, r5 + cmp r5, #0 + ble .L22229 + ldr r9, [sp, #12] + rsb r7, r1, r7 +.L22285: + ldr r1, [sp, #8] + add r3, r9, r5 + cmp r3, r1 + blt .L22288 + rsb r5, r9, r1 + cmp r5, #0 + ble .L22229 +.L22288: + add r0, r0, r6 + ldr r6, [sp, #32] + mov r1, sl, asl #16 + mov ip, ip, asl #8 + mov r3, r8, asl #16 + mov r2, r2, asl #16 + cmp r6, #0 + str ip, [sp, #104] + mov r6, r1, asr #16 + mov ip, lr, asl #8 + ldr r1, [sp, #52] + ldr lr, [sp, #4] + mov r3, r3, asr #16 + mov r2, r2, asr #16 + add sl, lr, r9, asl #1 + str r3, [sp, #72] + str r2, [sp, #76] + rsb lr, r0, r1 + bne .L22290 + mla r3, lr, r6, ip + mov r0, r3, asr #8 + cmp r0, r4 + bcs .L22229 + ldr r4, [sp, #16] + cmp fp, #0 + add r3, fp, #7 + mov r2, r4, asl #22 + movge r3, fp + mov r3, r3, asr #3 + mov r1, r0, lsr #3 + mov r2, r2, lsr #22 + mla ip, r3, r1, r2 + and r0, r0, #7 + ldr r3, .L23084+40 + add r0, r0, ip, asl #3 + cmp r5, #0 + add r8, r3, r0, asl #2 + ble .L22229 + ldr r3, [sp, #76] + ldr r2, [sp, #72] + mul r3, lr, r3 + mul r2, r7, r2 + ldr r6, [sp, #104] + rsb r3, r2, r3 + add r0, r6, r3 + mov ip, r0, asr #8 + cmp ip, fp + ldrcs r1, [sp, #32] + bcs .L22296 + b .L23081 +.L22297: + cmp ip, fp + bcc .L23046 +.L22296: + ldr ip, [sp, #72] + ldr lr, [sp, #40] + add r1, r1, #1 + add r0, r0, ip + add lr, lr, #2 + cmp r5, r1 + mov ip, r0, asr #8 + add sl, sl, #2 + str lr, [sp, #40] + bne .L22297 + ldr ip, [sp, #44] + ldr lr, [sp, #56] + add ip, ip, #1 + cmp ip, lr + str ip, [sp, #44] + bne .L23059 +.L23027: + add sp, sp, #604 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L22299: + cmp ip, fp + bcs .L22229 +.L23046: + mov r3, ip, asr #1 + and r6, r3, #3 + mov r3, ip, asr #3 + mov r3, r3, asl #5 + mov r2, ip, asr #1 + tst ip, #1 + and lr, r2, #3 + add ip, r3, r8 + add r2, r3, r8 + ldreqb r3, [r2, lr] @ zero_extendqisi2 + ldrneb r3, [ip, r6] @ zero_extendqisi2 + andeq r2, r3, #15 + movne r2, r3, lsr #4 + cmp r2, #0 + ldrne r4, [sp, #40] + ldr r6, [sp, #40] + ldrneh r4, [r4, #0] + ldr r3, [sp, #72] + add r1, r1, #1 + strneh r4, [sl, #0] @ movhi + add r0, r0, r3 + add r6, r6, #2 + cmp r5, r1 + mov ip, r0, asr #8 + add sl, sl, #2 + str r6, [sp, #40] + bgt .L22299 + b .L22229 +.L22290: + ldr r0, [sp, #16] + cmp fp, #0 + add r1, fp, #7 + mov r2, r0, asl #22 + movge r1, fp + ldr r3, .L23084+40 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #5 + cmp r5, #0 + str r2, [sp, #108] + str r1, [sp, #84] + ble .L22229 + ldr r1, [sp, #32] + ldr r0, [sp, #72] + mov r3, r1, asl #16 + mov r3, r3, asr #16 + str r3, [sp, #80] + ldr r1, [sp, #80] + ldr r3, [sp, #76] + mul r2, lr, r6 + mul r3, lr, r3 + mul r1, r7, r1 + mul r0, r7, r0 + ldr r6, [sp, #104] + rsb r2, r1, r2 + rsb r3, r0, r3 + add r7, r6, r3 + add r6, ip, r2 + mov lr, r7, asr #8 + mov r3, r6, asr #8 + cmp lr, fp + cmpcc r3, r4 + movcs r2, #0 + movcc r2, #1 + movcs r8, r2 + bcs .L22309 + b .L23082 +.L22310: + cmp lr, fp + cmpcc r3, r4 + bcc .L22312 +.L22309: + ldr lr, [sp, #80] + ldr r0, [sp, #40] + ldr ip, [sp, #72] + add r8, r8, #1 + add r6, r6, lr + add r7, r7, ip + add r0, r0, #2 + cmp r5, r8 + mov lr, r7, asr #8 + mov r3, r6, asr #8 + add sl, sl, #2 + str r0, [sp, #40] + bne .L22310 + b .L22229 +.L23061: + ldr r1, [sp, #108] + and r0, r3, #7 + ldr r2, [sp, #84] + add r0, r1, r0, asl #2 + and r1, r3, #7 + mov r3, r3, asr #3 + mov ip, lr, asr #1 + mul r2, r3, r2 + and r9, ip, #3 + ldr ip, [sp, #108] + mov r3, lr, asr #1 + add r1, ip, r1, asl #2 + and ip, r3, #3 + mov r3, lr, asr #3 + add r2, r2, r3, asl #5 + add r3, r0, r2 + tst lr, #1 + add r0, r1, r2 + ldreqb r3, [r0, ip] @ zero_extendqisi2 + ldrneb r3, [r3, r9] @ zero_extendqisi2 + andeq r0, r3, #15 + movne r0, r3, lsr #4 + cmp r0, #0 + ldrne r2, [sp, #40] + ldr lr, [sp, #72] + ldrneh r2, [r2, #0] + ldr ip, [sp, #40] + ldr r1, [sp, #80] + add r8, r8, #1 + strneh r2, [sl, #0] @ movhi + add r7, r7, lr + add r6, r6, r1 + add ip, ip, #2 + cmp r5, r8 + mov lr, r7, asr #8 + mov r3, r6, asr #8 + add sl, sl, #2 + str ip, [sp, #40] + ble .L22229 +.L22312: + cmp r3, r4 + cmpcc lr, fp + bcc .L23061 + b .L22229 +.L22267: + cmp ip, fp + bcs .L22229 +.L23044: + ldr r3, [sp, #64] + and r1, ip, #7 + add r0, r0, r3 + mov r3, ip, asr #3 + add r3, r6, r3, asl #6 + ldrb r2, [r3, r1] @ zero_extendqisi2 + ldr r1, [sp, #40] + cmp r2, #0 + ldrne r4, [sp, #40] + add lr, lr, #1 + ldrneh r4, [r4, #0] + add r1, r1, #2 + strneh r4, [sl, #0] @ movhi + cmp r5, lr + mov ip, r0, asr #8 + add sl, sl, #2 + str r1, [sp, #40] + bgt .L22267 + b .L22229 +.L22258: + ldr r3, [sp, #16] + cmp fp, #0 + add r1, fp, #7 + mov r2, r3, asl #22 + movge r1, fp + ldr r3, .L23084+40 + mov r2, r2, lsr #22 + mov r1, r1, asr #3 + add r2, r3, r2, asl #5 + mov r1, r1, asl #6 + cmp r5, #0 + str r2, [sp, #112] + str r1, [sp, #68] + ble .L22229 + ldr r0, [sp, #28] + mul r2, lr, r6 + mov r3, r0, asl #16 + mov r9, r3, asr #16 + ldr r0, [sp, #64] + mul r1, r9, r7 + mul r3, lr, r8 + mul r0, r7, r0 + rsb r2, r1, r2 + ldr r1, [sp, #116] + rsb r3, r0, r3 + add r7, r1, r3 + add r6, ip, r2 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + cmp lr, fp + cmpcc ip, r4 + movcs r3, #0 + movcc r3, #1 + movcs r8, r3 + bcs .L22274 + b .L23083 +.L22275: + cmp lr, fp + cmpcc ip, r4 + bcc .L22277 +.L22274: + ldr r3, [sp, #40] + ldr r2, [sp, #64] + add r8, r8, #1 + add r7, r7, r2 + add r6, r6, r9 + add r3, r3, #2 + cmp r5, r8 + mov lr, r7, asr #8 + mov ip, r6, asr #8 + add sl, sl, #2 + str r3, [sp, #40] + bne .L22275 + b .L22229 +.L23063: + ldr r0, [sp, #64] + and r3, ip, #7 + mov r2, lr, asr #3 + ldr r1, [sp, #112] + mov r3, r3, asl #3 + add r7, r7, r0 + add r3, r3, r2, asl #6 + ldr r0, [sp, #68] + mov r2, ip, asr #3 + add r3, r3, r1 + mla r0, r2, r0, r3 + and r1, lr, #7 + ldrb r3, [r0, r1] @ zero_extendqisi2 + add r8, r8, #1 + cmp r3, #0 + ldrne r2, [sp, #40] + ldr r3, [sp, #40] + ldrneh r2, [r2, #0] + add r6, r6, r9 + strneh r2, [sl, #0] @ movhi + add r3, r3, #2 + cmp r5, r8 + mov ip, r6, asr #8 + mov lr, r7, asr #8 + add sl, sl, #2 + str r3, [sp, #40] + ble .L22229 +.L22277: + cmp ip, r4 + cmpcc lr, fp + bcc .L23063 + b .L22229 +.L22322: + ldr r1, [sp, #16] + cmp fp, #0 + add r3, fp, #7 + mov r2, r1, asl #22 + movge r3, fp + mov lr, r3, asr #3 + mov r2, r2, lsr #22 + mov r3, ip, lsr #3 + mla r0, lr, r3, r2 + ldr r2, [sp, #12] + and r1, ip, #7 + ldr r3, .L23084+40 + add r1, r1, r0, asl #3 + cmp r9, r2 + add r0, r3, r1, asl #2 + bge .L22327 + rsb ip, r9, r2 + rsb lr, ip, fp + cmp lr, #0 + ble .L22229 + ldr r4, [sp, #8] + add r3, r9, fp + cmp r4, r3 + bhi .L22330 + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + add r6, r0, r1 + bne .L22332 + ldr r5, [sp, #120] + ldr r7, [sp, #100] +.L22334: + movs lr, r5, lsr #3 + beq .L22351 + ldr r1, [sp, #40] + mov r2, r7 + mov r0, r6 + mov ip, #0 +.L22353: + ldr r3, [r0, #0] + cmp r3, #0 + beq .L22354 + tst r3, #15 + ldrneh r4, [r1, #0] + strneh r4, [r2, #0] @ movhi + tst r3, #240 + ldrneh r4, [r1, #2] + strneh r4, [r2, #2] @ movhi + tst r3, #3840 + ldrneh r4, [r1, #4] + strneh r4, [r2, #4] @ movhi + tst r3, #61440 + ldrneh r4, [r1, #6] + strneh r4, [r2, #6] @ movhi + tst r3, #983040 + ldrneh r4, [r1, #8] + strneh r4, [r2, #8] @ movhi + tst r3, #15728640 + ldrneh r4, [r1, #10] + strneh r4, [r2, #10] @ movhi + tst r3, #251658240 + ldrneh r4, [r1, #12] + strneh r4, [r2, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r3, [r1, #14] + strneh r3, [r2, #14] @ movhi +.L22354: + add ip, ip, #1 + cmp ip, lr + add r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + bne .L22353 + ldr r4, [sp, #40] + mov r3, lr, asl #4 + add r4, r4, r3 + add r7, r7, r3 + add r6, r6, lr, asl #5 + str r4, [sp, #40] +.L22351: + ands r0, r5, #7 + beq .L22229 + ldr r3, [r6, #0] + mov r1, #0 +.L22373: + tst r3, #15 + ldrne r5, [sp, #40] + mov r2, r1, asl #1 + ldrneh r5, [r2, r5] + add r1, r1, #1 + strneh r5, [r2, r7] @ movhi + cmp r1, r0 + mov r3, r3, lsr #4 + bne .L22373 + b .L22229 +.L22323: + ldr r4, [sp, #16] + cmp fp, #0 + add r3, fp, #7 + mov r2, r4, asl #22 + movge r3, fp + mov lr, r3, asr #3 + mov r2, r2, lsr #22 + mov r1, ip, lsr #3 + mla r0, lr, r1, r2 + subs r3, fp, #8 + submi r3, fp, #1 + ldr r5, [sp, #12] + add r0, r0, r3, asr #3 + and r2, ip, #7 + ldr r3, .L23084+40 + add r2, r2, r0, asl #3 + cmp r9, r5 + add r0, r3, r2, asl #2 + bge .L22457 + rsb ip, r9, r5 + rsb r1, ip, fp + cmp r1, #0 + ble .L22229 + ldr r6, [sp, #8] + add r3, r9, fp + cmp r6, r3 + bhi .L22460 + mov r3, ip, lsr #3 + ands r6, ip, #7 + sub r0, r0, r3, asl #5 + bne .L22462 + ldr r8, [sp, #120] + ldr r1, [sp, #100] +.L22464: + movs r3, r8, lsr #3 + beq .L22481 + ldr lr, [sp, #40] + mov ip, r1 + mov r6, r0 + mov r7, #0 +.L22483: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L22484 + tst r2, #15 + ldrneh r4, [lr, #14] + strneh r4, [ip, #14] @ movhi + tst r2, #240 + ldrneh r5, [lr, #12] + strneh r5, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r4, [lr, #10] + strneh r4, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r5, [lr, #8] + strneh r5, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r4, [lr, #6] + strneh r4, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r5, [lr, #4] + strneh r5, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r4, [lr, #2] + strneh r4, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r5, [lr, #0] + strneh r5, [ip, #0] @ movhi +.L22484: + add r7, r7, #1 + cmp r7, r3 + sub r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L22483 + ldr r6, [sp, #40] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r6, r6, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r6, [sp, #40] +.L22481: + ands ip, r8, #7 + beq .L22229 + ldr r0, [r0, #0] + mov r2, #0 +.L22503: + movs lr, r0, lsr #28 + ldrne r4, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, r4] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L22503 + b .L22229 +.L22325: + cmp fp, #0 + add r2, fp, #7 + movge r2, fp + subs r3, fp, #8 + submi r3, fp, #1 + mov lr, r2, asr #3 + mov r3, r3, asr #3 + mov r1, ip, lsr #3 + mla r0, lr, r1, r3 + ldr r4, [sp, #16] + and r3, ip, #7 + mov r2, r4, asl #22 + mov r2, r2, lsr #22 + add r2, r2, r0, asl #1 + add r3, r3, r2, asl #2 + ldr r5, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L23084+40 + cmp r9, r5 + add r8, r0, r3 + bge .L22807 + rsb r0, r9, r5 + rsb lr, r0, fp + cmp lr, #0 + ble .L22229 + ldr r6, [sp, #8] + add r3, r9, fp + cmp r6, r3 + bhi .L22810 + mov r3, r0, lsr #3 + ands ip, r0, #7 + sub sl, r8, r3, asl #6 + bne .L22812 + ldr r8, [sp, #120] + ldr r7, [sp, #100] +.L22814: + movs r6, r8, lsr #3 + beq .L22872 + ldr r0, [sp, #40] + mov r1, r7 + mov ip, sl + mov lr, #0 +.L22874: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L22875 + tst r2, #255 + ldrneh r3, [r0, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #4] + mov r3, r2, lsr #16 + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrneh r5, [r0, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrneh r2, [r0, #0] + strneh r2, [r1, #0] @ movhi +.L22875: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L22884 + tst r2, #255 + ldrneh r3, [r0, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #12] + mov r3, r2, lsr #16 + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrneh r5, [r0, #10] + strneh r5, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrneh r2, [r0, #8] + strneh r2, [r1, #8] @ movhi +.L22884: + add lr, lr, #1 + cmp lr, r6 + sub ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L22874 + ldr r4, [sp, #40] + mov r3, r6, asl #4 + rsb r2, r6, r6, asl #26 + add r4, r4, r3 + add r7, r7, r3 + add sl, sl, r2, asl #6 + str r4, [sp, #40] +.L22872: + ands ip, r8, #7 + beq .L22229 + cmp ip, #3 + ldrls r2, [sl, #4] + bls .L22907 + ldr r2, [sl, #4] + cmp r2, #0 + beq .L22897 + tst r2, #255 + ldrne r5, [sp, #40] + mov r3, r2, lsr #8 + ldrneh r5, [r5, #6] + strneh r5, [r7, #6] @ movhi + tst r3, #255 + ldrne r6, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r6, [r6, #4] + strneh r6, [r7, #4] @ movhi + tst r3, #255 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #2] + strneh lr, [r7, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r0, [sp, #40] + ldrneh r0, [r0, #0] + strneh r0, [r7, #0] @ movhi +.L22897: + subs ip, ip, #4 + ldr r2, [sl, #0] + beq .L22229 + ldr r1, [sp, #40] + add r7, r7, #8 + add r1, r1, #8 + str r1, [sp, #40] +.L22907: + mov r1, #0 +.L22908: + movs r3, r2, lsr #24 + ldrne r4, [sp, #40] + mov r0, r1, asl #1 + ldrneh r4, [r0, r4] + add r1, r1, #1 + strneh r4, [r0, r7] @ movhi + cmp ip, r1 + mov r2, r2, asl #8 + bhi .L22908 + b .L22229 +.L23085: + .align 2 +.L23084: + .word io_registers + .word obj_priority_count + .word obj_priority_list + .word bitmap_mode_renderers-12 + .word oam_ram + .word obj_width_table + .word palette_ram_converted + .word layer_count + .word layer_order + .word obj_height_table + .word vram+65536 + .word vram+65472 + .word vram+65600 +.L22324: + ldr lr, [sp, #16] + cmp fp, #0 + add r3, fp, #7 + mov r1, lr, asl #22 + movge r3, fp + mov r2, ip, lsr #3 + mov r6, r3, asr #3 + mov r2, r2, asl #1 + mov r1, r1, lsr #22 + mla r0, r2, r6, r1 + and r3, ip, #7 + add r3, r3, r0, asl #2 + ldr r1, [sp, #12] + mov r0, r3, asl #3 + ldr r3, .L23084+40 + cmp r9, r1 + add r2, r0, r3 + bge .L22587 + rsb r0, r9, r1 + rsb lr, r0, fp + cmp lr, #0 + ble .L22229 + ldr r4, [sp, #8] + add r3, r9, fp + cmp r4, r3 + bhi .L22590 + mov r3, r0, lsr #3 + ands ip, r0, #7 + add sl, r2, r3, asl #6 + bne .L22592 + ldr r8, [sp, #120] + ldr r7, [sp, #100] +.L22594: + movs r6, r8, lsr #3 + beq .L22652 + ldr r0, [sp, #40] + mov r1, r7 + mov ip, sl + mov lr, #0 +.L22654: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L22655 + tst r2, #255 + ldrneh r3, [r0, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #2] + mov r3, r2, lsr #16 + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrneh r5, [r0, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrneh r2, [r0, #6] + strneh r2, [r1, #6] @ movhi +.L22655: + ldr r2, [ip, #4] + cmp r2, #0 + beq .L22664 + tst r2, #255 + ldrneh r3, [r0, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrneh r4, [r0, #10] + mov r3, r2, lsr #16 + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrneh r5, [r0, #12] + strneh r5, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrneh r2, [r0, #14] + strneh r2, [r1, #14] @ movhi +.L22664: + add lr, lr, #1 + cmp lr, r6 + add ip, ip, #64 + add r1, r1, #16 + add r0, r0, #16 + bne .L22654 + ldr r4, [sp, #40] + mov r3, r6, asl #4 + add r4, r4, r3 + add r7, r7, r3 + add sl, sl, r6, asl #6 + str r4, [sp, #40] +.L22652: + ands r0, r8, #7 + beq .L22229 + cmp r0, #3 + ldrls r3, [sl, #0] + bls .L22687 + ldr r2, [sl, #0] + cmp r2, #0 + beq .L22677 + tst r2, #255 + ldrne r5, [sp, #40] + mov r3, r2, lsr #8 + ldrneh r5, [r5, #0] + strneh r5, [r7, #0] @ movhi + tst r3, #255 + ldrne r6, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r6, [r6, #2] + strneh r6, [r7, #2] @ movhi + tst r3, #255 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #4] + strneh ip, [r7, #4] @ movhi + movs r2, r2, lsr #24 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #6] + strneh lr, [r7, #6] @ movhi +.L22677: + subs r0, r0, #4 + ldr r3, [sl, #4] + beq .L22229 + ldr r1, [sp, #40] + add r7, r7, #8 + add r1, r1, #8 + str r1, [sp, #40] +.L22687: + mov r2, #0 +.L22688: + tst r3, #255 + ldrne r4, [sp, #40] + mov r1, r2, asl #1 + ldrneh r4, [r1, r4] + add r2, r2, #1 + strneh r4, [r1, r7] @ movhi + cmp r0, r2 + mov r3, r3, lsr #8 + bhi .L22688 + b .L22229 +.L22587: + ldr r4, [sp, #8] + add r3, r9, fp + cmp r4, r3 + bls .L23064 + cmp r6, #0 + beq .L22229 + ldr r5, [sp, #4] + ldr r3, .L23084+48 + add r1, r5, r9, asl #1 + add r0, r0, r3 + mov lr, #0 + b .L22787 +.L23065: + ldr r3, [sp, #40] + add r2, r2, #64 + add r3, r3, #16 + add r1, r1, #16 + str r3, [sp, #40] +.L22787: + ldr ip, [r2, #0] + cmp ip, #0 + beq .L22788 + tst ip, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs ip, ip, lsr #24 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #6] + strneh ip, [r1, #6] @ movhi +.L22788: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L22797 + tst ip, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #8] + strneh r3, [r1, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, ip, lsr #16 + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs ip, ip, lsr #24 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #14] + strneh ip, [r1, #14] @ movhi +.L22797: + add lr, lr, #1 + cmp r6, lr + add r0, r0, #64 + bne .L23065 + b .L22229 +.L22457: + ldr r1, [sp, #8] + add r3, r9, fp + cmp r1, r3 + bls .L23066 + cmp lr, #0 + beq .L22229 + ldr r5, [sp, #4] + mov r3, #0 + add r1, r5, r9, asl #1 + b .L22568 +.L23067: + ldr r6, [sp, #40] + sub r0, r0, #32 + add r6, r6, #16 + add r1, r1, #16 + str r6, [sp, #40] +.L22568: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22569 + tst r2, #15 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi + tst r2, #240 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #12] + strneh ip, [r1, #12] @ movhi + tst r2, #3840 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst r2, #61440 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #8] + strneh r5, [r1, #8] @ movhi + tst r2, #983040 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi + tst r2, #15728640 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #4] + strneh ip, [r1, #4] @ movhi + tst r2, #251658240 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs r2, r2, lsr #28 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L22569: + add r3, r3, #1 + cmp lr, r3 + bne .L23067 + b .L22229 +.L22327: + ldr r1, [sp, #8] + add r3, r9, fp + cmp r1, r3 + bls .L23068 + cmp lr, #0 + beq .L22229 + ldr r2, [sp, #4] + mov r3, #0 + add r1, r2, r9, asl #1 + b .L22438 +.L23069: + ldr r2, [sp, #40] + add r0, r0, #32 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #40] +.L22438: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L22439 + tst ip, #15 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #0] + strneh r4, [r1, #0] @ movhi + tst ip, #240 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + tst ip, #3840 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #4] + strneh r6, [r1, #4] @ movhi + tst ip, #61440 + ldrne r2, [sp, #40] + ldrneh r2, [r2, #6] + strneh r2, [r1, #6] @ movhi + tst ip, #983040 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #8] + strneh r4, [r1, #8] @ movhi + tst ip, #15728640 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + tst ip, #251658240 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #12] + strneh r6, [r1, #12] @ movhi + movs ip, ip, lsr #28 + ldrne ip, [sp, #40] + ldrneh ip, [ip, #14] + strneh ip, [r1, #14] @ movhi +.L22439: + add r3, r3, #1 + cmp lr, r3 + bne .L23069 + b .L22229 +.L22807: + ldr r4, [sp, #8] + add r3, r9, fp + cmp r4, r3 + bls .L23070 + cmp lr, #0 + beq .L22229 + ldr r5, [sp, #4] + ldr r3, .L23084+44 + add r1, r5, r9, asl #1 + add r0, r0, r3 + mov r2, #0 + b .L23007 +.L23071: + ldr r6, [sp, #40] + sub r8, r8, #64 + add r6, r6, #16 + add r1, r1, #16 + str r6, [sp, #40] +.L23007: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L23008 + tst ip, #255 + ldrne r6, [sp, #40] + mov r3, ip, lsr #8 + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi + tst r3, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs ip, ip, lsr #24 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L23008: + ldr ip, [r8, #0] + cmp ip, #0 + beq .L23017 + tst ip, #255 + ldrne r6, [sp, #40] + mov r3, ip, lsr #8 + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi + tst r3, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #12] + strneh r3, [r1, #12] @ movhi + mov r3, ip, lsr #16 + tst r3, #255 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + movs ip, ip, lsr #24 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #8] + strneh r5, [r1, #8] @ movhi +.L23017: + add r2, r2, #1 + cmp lr, r2 + sub r0, r0, #64 + bne .L23071 + b .L22229 +.L23070: + rsb fp, r9, r4 + cmp fp, #0 + ble .L22229 + ldr r5, [sp, #4] + movs sl, fp, lsr #3 + add r1, r5, r9, asl #1 + beq .L22966 + ldr r3, .L23084+44 + ldr r6, [sp, #40] + add r0, r0, r3 + mov lr, r1 + mov r7, r8 + mov r2, #0 +.L22968: + ldr ip, [r0, #68] + cmp ip, #0 + beq .L22969 + tst ip, #255 + ldrneh r3, [r6, #6] + strneh r3, [lr, #6] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #4] + mov r3, ip, lsr #16 + strneh r4, [lr, #4] @ movhi + tst r3, #255 + ldrneh r5, [r6, #2] + strneh r5, [lr, #2] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r6, #0] + strneh ip, [lr, #0] @ movhi +.L22969: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L22978 + tst ip, #255 + ldrneh r3, [r6, #14] + strneh r3, [lr, #14] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #12] + mov r3, ip, lsr #16 + strneh r4, [lr, #12] @ movhi + tst r3, #255 + ldrneh r5, [r6, #10] + strneh r5, [lr, #10] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r6, #8] + strneh ip, [lr, #8] @ movhi +.L22978: + add r2, r2, #1 + cmp sl, r2 + sub r7, r7, #64 + add lr, lr, #16 + add r6, r6, #16 + sub r0, r0, #64 + bne .L22968 + ldr lr, [sp, #40] + mov r3, sl, asl #4 + rsb r2, sl, sl, asl #26 + add lr, lr, r3 + add r1, r1, r3 + add r8, r8, r2, asl #6 + str lr, [sp, #40] +.L22966: + ands ip, fp, #7 + beq .L22229 + cmp ip, #3 + ldrls r2, [r8, #4] + bls .L23001 + ldr r2, [r8, #4] + cmp r2, #0 + beq .L22991 + tst r2, #255 + ldrne r0, [sp, #40] + mov r3, r2, lsr #8 + ldrneh r0, [r0, #6] + strneh r0, [r1, #6] @ movhi + tst r3, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + tst r3, #255 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L22991: + subs ip, ip, #4 + ldr r2, [r8, #0] + beq .L22229 + ldr r6, [sp, #40] + add r1, r1, #8 + add r6, r6, #8 + str r6, [sp, #40] +.L23001: + mov r3, #0 +.L23002: + movs lr, r2, lsr #24 + ldrne r4, [sp, #40] + mov r0, r3, asl #1 + ldrneh r4, [r0, r4] + add r3, r3, #1 + strneh r4, [r0, r1] @ movhi + cmp ip, r3 + mov r2, r2, asl #8 + bhi .L23002 + b .L22229 +.L23066: + rsb r8, r9, r1 + cmp r8, #0 + ble .L22229 + ldr r2, [sp, #4] + movs r3, r8, lsr #3 + add r1, r2, r9, asl #1 + beq .L22541 + ldr lr, [sp, #40] + mov ip, r1 + mov r6, r0 + mov r7, #0 +.L22543: + ldr r2, [r6, #0] + cmp r2, #0 + beq .L22544 + tst r2, #15 + ldrneh r4, [lr, #14] + strneh r4, [ip, #14] @ movhi + tst r2, #240 + ldrneh r5, [lr, #12] + strneh r5, [ip, #12] @ movhi + tst r2, #3840 + ldrneh r4, [lr, #10] + strneh r4, [ip, #10] @ movhi + tst r2, #61440 + ldrneh r5, [lr, #8] + strneh r5, [ip, #8] @ movhi + tst r2, #983040 + ldrneh r4, [lr, #6] + strneh r4, [ip, #6] @ movhi + tst r2, #15728640 + ldrneh r5, [lr, #4] + strneh r5, [ip, #4] @ movhi + tst r2, #251658240 + ldrneh r4, [lr, #2] + strneh r4, [ip, #2] @ movhi + movs r2, r2, lsr #28 + ldrneh r5, [lr, #0] + strneh r5, [ip, #0] @ movhi +.L22544: + add r7, r7, #1 + cmp r7, r3 + sub r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L22543 + ldr r6, [sp, #40] + rsb r2, r3, r3, asl #27 + mov r3, r3, asl #4 + add r6, r6, r3 + add r1, r1, r3 + add r0, r0, r2, asl #5 + str r6, [sp, #40] +.L22541: + ands ip, r8, #7 + beq .L22229 + ldr r0, [r0, #0] + mov r2, #0 +.L22563: + movs lr, r0, lsr #28 + ldrne r4, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, r4] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, asl #4 + bne .L22563 + b .L22229 +.L23068: + rsb r8, r9, r1 + cmp r8, #0 + ble .L22229 + ldr r2, [sp, #4] + movs r7, r8, lsr #3 + add r1, r2, r9, asl #1 + beq .L22411 + ldr lr, [sp, #40] + mov ip, r1 + mov r6, r0 + mov r2, #0 +.L22413: + ldr r3, [r6, #0] + cmp r3, #0 + beq .L22414 + tst r3, #15 + ldrneh r4, [lr, #0] + strneh r4, [ip, #0] @ movhi + tst r3, #240 + ldrneh r5, [lr, #2] + strneh r5, [ip, #2] @ movhi + tst r3, #3840 + ldrneh r4, [lr, #4] + strneh r4, [ip, #4] @ movhi + tst r3, #61440 + ldrneh r5, [lr, #6] + strneh r5, [ip, #6] @ movhi + tst r3, #983040 + ldrneh r4, [lr, #8] + strneh r4, [ip, #8] @ movhi + tst r3, #15728640 + ldrneh r5, [lr, #10] + strneh r5, [ip, #10] @ movhi + tst r3, #251658240 + ldrneh r4, [lr, #12] + strneh r4, [ip, #12] @ movhi + movs r3, r3, lsr #28 + ldrneh r5, [lr, #14] + strneh r5, [ip, #14] @ movhi +.L22414: + add r2, r2, #1 + cmp r2, r7 + add r6, r6, #32 + add ip, ip, #16 + add lr, lr, #16 + bne .L22413 + ldr r6, [sp, #40] + mov r3, r7, asl #4 + add r6, r6, r3 + add r1, r1, r3 + add r0, r0, r7, asl #5 + str r6, [sp, #40] +.L22411: + ands ip, r8, #7 + beq .L22229 + ldr r0, [r0, #0] + mov r2, #0 +.L22433: + tst r0, #15 + ldrne lr, [sp, #40] + mov r3, r2, asl #1 + ldrneh lr, [r3, lr] + add r2, r2, #1 + strneh lr, [r3, r1] @ movhi + cmp r2, ip + mov r0, r0, lsr #4 + bne .L22433 + b .L22229 +.L23064: + rsb fp, r9, r4 + cmp fp, #0 + ble .L22229 + ldr r5, [sp, #4] + movs sl, fp, lsr #3 + add r1, r5, r9, asl #1 + beq .L22746 + ldr r3, .L23084+48 + ldr r6, [sp, #40] + add r0, r0, r3 + mov lr, r1 + mov r7, r2 + mov r8, #0 +.L22748: + ldr ip, [r7, #0] + cmp ip, #0 + beq .L22749 + tst ip, #255 + ldrneh r3, [r6, #0] + strneh r3, [lr, #0] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #2] + mov r3, ip, lsr #16 + strneh r4, [lr, #2] @ movhi + tst r3, #255 + ldrneh r5, [r6, #4] + strneh r5, [lr, #4] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r6, #6] + strneh ip, [lr, #6] @ movhi +.L22749: + ldr ip, [r0, #-60] + cmp ip, #0 + beq .L22758 + tst ip, #255 + ldrneh r3, [r6, #8] + strneh r3, [lr, #8] @ movhi + mov r3, ip, lsr #8 + tst r3, #255 + ldrneh r4, [r6, #10] + mov r3, ip, lsr #16 + strneh r4, [lr, #10] @ movhi + tst r3, #255 + ldrneh r5, [r6, #12] + strneh r5, [lr, #12] @ movhi + movs ip, ip, lsr #24 + ldrneh ip, [r6, #14] + strneh ip, [lr, #14] @ movhi +.L22758: + add r8, r8, #1 + cmp r8, sl + add r7, r7, #64 + add lr, lr, #16 + add r6, r6, #16 + add r0, r0, #64 + bne .L22748 + ldr lr, [sp, #40] + mov r3, sl, asl #4 + add lr, lr, r3 + add r1, r1, r3 + add r2, r2, sl, asl #6 + str lr, [sp, #40] +.L22746: + ands ip, fp, #7 + beq .L22229 + cmp ip, #3 + ldrls r3, [r2, #0] + bls .L22781 + ldr r0, [r2, #0] + cmp r0, #0 + beq .L22771 + tst r0, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r0, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r0, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r0, r0, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L22771: + subs ip, ip, #4 + ldr r3, [r2, #4] + beq .L22229 + ldr lr, [sp, #40] + add r1, r1, #8 + add lr, lr, #8 + str lr, [sp, #40] +.L22781: + mov r2, #0 +.L22782: + tst r3, #255 + ldrne r4, [sp, #40] + mov r0, r2, asl #1 + ldrneh r4, [r0, r4] + add r2, r2, #1 + strneh r4, [r0, r1] @ movhi + cmp ip, r2 + mov r3, r3, lsr #8 + bhi .L22782 + b .L22229 +.L22330: + mov r3, ip, lsr #3 + mov r1, r3, asl #5 + ands r3, ip, #7 + ldreq r3, [sp, #100] + add ip, r0, r1 + bne .L23072 +.L22379: + movs r0, lr, lsr #3 + beq .L22229 + mov r1, #0 + b .L22389 +.L23073: + ldr lr, [sp, #40] + add ip, ip, #32 + add lr, lr, #16 + add r3, r3, #16 + str lr, [sp, #40] +.L22389: + ldr r2, [ip, #0] + cmp r2, #0 + beq .L22390 + tst r2, #15 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #0] + strneh lr, [r3, #0] @ movhi + tst r2, #240 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #2] + strneh r4, [r3, #2] @ movhi + tst r2, #3840 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #4] + strneh r5, [r3, #4] @ movhi + tst r2, #61440 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #6] + strneh r6, [r3, #6] @ movhi + tst r2, #983040 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #8] + strneh lr, [r3, #8] @ movhi + tst r2, #15728640 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #10] + strneh r4, [r3, #10] @ movhi + tst r2, #251658240 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #12] + strneh r5, [r3, #12] @ movhi + movs r2, r2, lsr #28 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #14] + strneh r6, [r3, #14] @ movhi +.L22390: + add r1, r1, #1 + cmp r1, r0 + bne .L23073 + b .L22229 +.L22590: + ands r1, r0, #7 + mov r3, r0, lsr #3 + add r0, r2, r3, asl #6 + ldreq r1, [sp, #100] + bne .L23074 +.L22694: + movs lr, lr, lsr #3 + beq .L22229 + mov ip, #0 + b .L22723 +.L23075: + ldr r2, [sp, #40] + add r0, r0, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #40] +.L22723: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22724 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L22724: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L22733 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #8] + strneh r3, [r1, #8] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #10] + strneh r4, [r1, #10] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #12] + strneh r5, [r1, #12] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #14] + strneh r6, [r1, #14] @ movhi +.L22733: + add ip, ip, #1 + cmp ip, lr + bne .L23075 + b .L22229 +.L22810: + ands r2, r0, #7 + mov r3, r0, lsr #3 + sub r0, r8, r3, asl #6 + ldreq r1, [sp, #100] + bne .L23076 +.L22914: + movs lr, lr, lsr #3 + beq .L22229 + mov ip, #0 + b .L22943 +.L23077: + ldr r2, [sp, #40] + sub r0, r0, #64 + add r2, r2, #16 + add r1, r1, #16 + str r2, [sp, #40] +.L22943: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L22944 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L22944: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22953 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #14] + strneh r3, [r1, #14] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #12] + strneh r4, [r1, #12] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #10] + strneh r5, [r1, #10] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #8] + strneh r6, [r1, #8] @ movhi +.L22953: + add ip, ip, #1 + cmp ip, lr + bne .L23077 + b .L22229 +.L22460: + mov r3, ip, lsr #3 + ands r2, ip, #7 + sub r0, r0, r3, asl #5 + ldreq r3, [sp, #100] + bne .L23078 +.L22509: + movs r1, r1, lsr #3 + beq .L22229 + mov r2, #0 + b .L22519 +.L23079: + ldr ip, [sp, #40] + sub r0, r0, #32 + add ip, ip, #16 + add r3, r3, #16 + str ip, [sp, #40] +.L22519: + ldr ip, [r0, #0] + cmp ip, #0 + beq .L22520 + tst ip, #15 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #14] + strneh lr, [r3, #14] @ movhi + tst ip, #240 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #12] + strneh r4, [r3, #12] @ movhi + tst ip, #3840 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #10] + strneh r5, [r3, #10] @ movhi + tst ip, #61440 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #8] + strneh r6, [r3, #8] @ movhi + tst ip, #983040 + ldrne lr, [sp, #40] + ldrneh lr, [lr, #6] + strneh lr, [r3, #6] @ movhi + tst ip, #15728640 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #4] + strneh r4, [r3, #4] @ movhi + tst ip, #251658240 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #2] + strneh r5, [r3, #2] @ movhi + movs ip, ip, lsr #28 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #0] + strneh r6, [r3, #0] @ movhi +.L22520: + add r2, r2, #1 + cmp r2, r1 + bne .L23079 + b .L22229 +.L23078: + rsbs r6, r2, #8 + ldr ip, [r0, #0] + ldreq r3, [sp, #100] + beq .L22512 + mov r3, r2, asl #2 + mov r3, ip, asl r3 + mov lr, #0 +.L22513: + movs r5, r3, lsr #28 + ldrne r2, [sp, #40] + mov ip, lr, asl #1 + ldrneh r4, [ip, r2] + ldrne r2, [sp, #100] + add lr, lr, #1 + strneh r4, [ip, r2] @ movhi + cmp lr, r6 + mov r3, r3, asl #4 + bne .L22513 + ldr r5, [sp, #40] + mov r3, r6, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r3, r6, r3 +.L22512: + sub r0, r0, #32 + b .L22509 +.L23076: + cmp r2, #3 + rsb ip, r2, #8 + bls .L22915 + cmp ip, #0 + ldr r1, [r0, #0] + ldreq r1, [sp, #100] + beq .L22919 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L22920: + movs r5, r3, lsr #24 + ldrne r6, [sp, #40] + mov r2, r1, asl #1 + ldrneh r4, [r2, r6] + ldrne r6, [sp, #100] + add r1, r1, #1 + strneh r4, [r2, r6] @ movhi + cmp r1, ip + mov r3, r3, asl #8 + bne .L22920 + ldr r5, [sp, #40] + mov r3, ip, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r1, r6, r3 +.L22919: + sub r0, r0, #64 + b .L22914 +.L23074: + cmp r1, #3 + rsb ip, r1, #8 + bls .L22695 + cmp ip, #0 + ldr r2, [r0, #4] + ldreq r1, [sp, #100] + beq .L22699 + mov r3, r1, asl #3 + sub r3, r3, #32 + mov r3, r2, lsr r3 + mov r1, #0 +.L22700: + tst r3, #255 + ldrne r5, [sp, #40] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldrne r5, [sp, #100] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L22700 + mov r3, ip, asl #1 + ldr ip, [sp, #40] + ldr r2, [sp, #100] + add ip, ip, r3 + str ip, [sp, #40] + add r1, r2, r3 +.L22699: + add r0, r0, #64 + b .L22694 +.L23072: + rsbs r6, r3, #8 + ldr r0, [r0, r1] + ldreq r3, [sp, #100] + beq .L22382 + mov r3, r3, asl #2 + mov r0, r0, lsr r3 + mov r2, #0 +.L22383: + tst r0, #15 + ldrne r1, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, r1] + ldrne r1, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r6, r2 + mov r0, r0, lsr #4 + bne .L22383 + ldr r5, [sp, #40] + mov r3, r6, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r3, r6, r3 +.L22382: + add ip, ip, #32 + b .L22379 +.L22812: + ldr lr, [sp, #120] + rsb r0, ip, #8 + cmp lr, r0 + bge .L22815 + cmp lr, #0 + ble .L22229 + cmp ip, #3 + bls .L22818 + ldr r2, [sl, #0] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r2, r2, asl r3 + mov r1, #0 +.L22821: + movs r0, r2, lsr #24 + ldrne r4, [sp, #40] + mov r3, r1, asl #1 + ldrneh r5, [r3, r4] + ldr r6, [sp, #120] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r3, r4] @ movhi + cmp r6, r1 + mov r2, r2, asl #8 + bne .L22821 + b .L22229 +.L22592: + ldr r5, [sp, #120] + rsb r0, ip, #8 + cmp r5, r0 + bge .L22595 + cmp r5, #0 + ble .L22229 + cmp ip, #3 + bls .L22598 + ldr r2, [sl, #4] + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L22601: + tst r1, #255 + ldrne r6, [sp, #40] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #120] + ldrne r6, [sp, #100] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r1, r1, lsr #8 + bne .L22601 + b .L22229 +.L22332: + ldr r5, [sp, #120] + rsb ip, r3, #8 + cmp r5, ip + bge .L22335 + cmp r5, #0 + ble .L22229 + ldr r2, [r0, r1] + mov r3, r3, asl #2 + mov r0, r2, lsr r3 + mov r2, #0 +.L22339: + tst r0, #15 + ldrne r6, [sp, #40] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #120] + ldrne r6, [sp, #100] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r0, r0, lsr #4 + bne .L22339 + b .L22229 +.L22462: + ldr ip, [sp, #120] + rsb lr, r6, #8 + cmp ip, lr + bge .L22465 + cmp ip, #0 + ble .L22229 + ldr r2, [r0, #0] + mov r3, r6, asl #2 + mov r0, r2, asl r3 + mov r2, #0 +.L22469: + movs lr, r0, lsr #28 + ldrne r1, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, r1] + ldr r5, [sp, #120] + ldrne r1, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, r1] @ movhi + cmp r5, r2 + mov r0, r0, asl #4 + bne .L22469 + b .L22229 +.L22915: + subs r6, ip, #4 + ldr r1, [r0, #4] + ldreq r1, [sp, #100] + beq .L22927 + mov r3, r2, asl #3 + sub r3, r3, #32 + mov r3, r1, asl r3 + mov r1, #0 +.L22928: + movs r2, r3, lsr #24 + ldrne r4, [sp, #40] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r6 + mov r3, r3, asl #8 + bne .L22928 + ldr r6, [sp, #40] + mov r3, ip, asl #1 + ldr ip, [sp, #100] + add r2, r6, r3 + sub r2, r2, #8 + add r3, ip, r3 + str r2, [sp, #40] + sub r1, r3, #8 +.L22927: + ldr r2, [r0, #0] + cmp r2, #0 + beq .L22933 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #6] + strneh r3, [r1, #6] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #4] + strneh r4, [r1, #4] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #2] + strneh r5, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #0] + strneh r6, [r1, #0] @ movhi +.L22933: + ldr ip, [sp, #40] + add r1, r1, #8 + add ip, ip, #8 + sub r0, r0, #64 + str ip, [sp, #40] + b .L22914 +.L22695: + subs r6, ip, #4 + ldr r2, [r0, #0] + ldreq r1, [sp, #100] + beq .L22707 + mov r3, r1, asl #3 + mov r3, r2, lsr r3 + mov r1, #0 +.L22708: + tst r3, #255 + ldrne r4, [sp, #40] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, r6 + mov r3, r3, lsr #8 + bne .L22708 + ldr r6, [sp, #40] + mov r3, ip, asl #1 + ldr ip, [sp, #100] + add r2, r6, r3 + sub r2, r2, #8 + add r3, ip, r3 + str r2, [sp, #40] + sub r1, r3, #8 +.L22707: + ldr r2, [r0, #4] + cmp r2, #0 + beq .L22713 + tst r2, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #0] + strneh r3, [r1, #0] @ movhi + mov r3, r2, lsr #8 + tst r3, #255 + ldrne r4, [sp, #40] + mov r3, r2, lsr #16 + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + tst r3, #255 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #4] + strneh r5, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r6, [sp, #40] + ldrneh r6, [r6, #6] + strneh r6, [r1, #6] @ movhi +.L22713: + ldr ip, [sp, #40] + add r1, r1, #8 + add ip, ip, #8 + add r0, r0, #64 + str ip, [sp, #40] + b .L22694 +.L22595: + cmp ip, #3 + bls .L22625 + cmp r0, #0 + ldr r2, [sl, #4] + ldreq r7, [sp, #100] + beq .L22629 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r1, r2, lsr r3 + mov r2, #0 +.L22630: + tst r1, #255 + ldrne lr, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, lr] + ldrne lr, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, lr] @ movhi + cmp r0, r2 + mov r1, r1, lsr #8 + bne .L22630 + ldr r5, [sp, #40] + mov r3, r0, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r7, r3, r6 +.L22629: + ldr r6, [sp, #120] + add sl, sl, #64 + rsb r8, r0, r6 + b .L22594 +.L22335: + cmp ip, #0 + ldr r2, [r6, #0] + ldreq r7, [sp, #100] + beq .L22345 + mov r3, r3, asl #2 + mov r3, r2, lsr r3 + mov r1, #0 +.L22346: + tst r3, #15 + ldrne r0, [sp, #40] + mov r2, r1, asl #1 + ldrneh r4, [r2, r0] + ldrne r0, [sp, #100] + add r1, r1, #1 + strneh r4, [r2, r0] @ movhi + cmp ip, r1 + mov r3, r3, lsr #4 + bne .L22346 + ldr r5, [sp, #40] + mov r3, ip, asl #1 + ldr lr, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r7, r3, lr +.L22345: + ldr r0, [sp, #120] + add r6, r6, #32 + rsb r5, ip, r0 + b .L22334 +.L22465: + cmp lr, #0 + ldr r2, [r0, #0] + ldreq r1, [sp, #100] + beq .L22475 + mov r3, r6, asl #2 + mov r3, r2, asl r3 + mov ip, #0 +.L22476: + movs r6, r3, lsr #28 + ldrne r1, [sp, #40] + mov r2, ip, asl #1 + ldrneh r4, [r2, r1] + ldrne r1, [sp, #100] + add ip, ip, #1 + strneh r4, [r2, r1] @ movhi + cmp lr, ip + mov r3, r3, asl #4 + bne .L22476 + ldr r5, [sp, #40] + mov r3, lr, asl #1 + ldr r6, [sp, #100] + add r5, r5, r3 + str r5, [sp, #40] + add r1, r3, r6 +.L22475: + ldr ip, [sp, #120] + sub r0, r0, #32 + rsb r8, lr, ip + b .L22464 +.L22815: + cmp ip, #3 + bls .L22845 + cmp r0, #0 + ldr r2, [sl, #0] + ldreq r7, [sp, #100] + beq .L22849 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L22850: + movs r2, r3, lsr #24 + ldrne r4, [sp, #40] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, asl #8 + bne .L22850 + ldr r6, [sp, #40] + mov r3, r0, asl #1 + ldr ip, [sp, #100] + add r6, r6, r3 + str r6, [sp, #40] + add r7, ip, r3 +.L22849: + ldr ip, [sp, #120] + sub sl, sl, #64 + rsb r8, r0, ip + b .L22814 +.L23082: + mov r8, #0 + b .L22312 +.L23083: + mov r8, #0 + b .L22277 +.L23081: + ldr r1, [sp, #32] + b .L23046 +.L23080: + ldr lr, [sp, #28] + b .L23044 +.L22845: + subs lr, r0, #4 + ldr r2, [sl, #4] + ldreq r1, [sp, #100] + beq .L22857 + mov r3, ip, asl #3 + sub r3, r3, #32 + mov r3, r2, asl r3 + mov r1, #0 +.L22858: + movs r2, r3, lsr #24 + ldrne r4, [sp, #40] + mov r2, r1, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r1, r1, #1 + strneh r5, [r2, r4] @ movhi + cmp r1, lr + mov r3, r3, asl #8 + bne .L22858 + ldr r6, [sp, #40] + mov r3, r0, asl #1 + ldr ip, [sp, #100] + add r2, r6, r3 + sub r2, r2, #8 + add r3, ip, r3 + str r2, [sp, #40] + sub r1, r3, #8 +.L22857: + ldr r2, [sl, #0] + cmp r2, #0 + beq .L22863 + tst r2, #255 + ldrne lr, [sp, #40] + mov r3, r2, lsr #8 + ldrneh lr, [lr, #6] + strneh lr, [r1, #6] @ movhi + tst r3, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + mov r3, r2, lsr #16 + tst r3, #255 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #2] + strneh r4, [r1, #2] @ movhi + movs r2, r2, lsr #24 + ldrne r5, [sp, #40] + ldrneh r5, [r5, #0] + strneh r5, [r1, #0] @ movhi +.L22863: + ldr r6, [sp, #40] + add r7, r1, #8 + add r6, r6, #8 + str r6, [sp, #40] + b .L22849 +.L22625: + subs lr, r0, #4 + ldr r2, [sl, #0] + ldreq r1, [sp, #100] + beq .L22637 + mov r3, ip, asl #3 + mov r1, r2, lsr r3 + mov r2, #0 +.L22638: + tst r1, #255 + ldrne ip, [sp, #40] + mov r3, r2, asl #1 + ldrneh r4, [r3, ip] + ldrne ip, [sp, #100] + add r2, r2, #1 + strneh r4, [r3, ip] @ movhi + cmp r2, lr + mov r1, r1, lsr #8 + bne .L22638 + ldr r5, [sp, #40] + mov r3, r0, asl #1 + ldr r6, [sp, #100] + add r2, r5, r3 + sub r2, r2, #8 + add r3, r6, r3 + str r2, [sp, #40] + sub r1, r3, #8 +.L22637: + ldr r2, [sl, #4] + cmp r2, #0 + beq .L22643 + tst r2, #255 + ldrne ip, [sp, #40] + mov r3, r2, lsr #8 + ldrneh ip, [ip, #0] + strneh ip, [r1, #0] @ movhi + tst r3, #255 + ldrne lr, [sp, #40] + mov r3, r2, lsr #16 + ldrneh lr, [lr, #2] + strneh lr, [r1, #2] @ movhi + tst r3, #255 + ldrne r3, [sp, #40] + ldrneh r3, [r3, #4] + strneh r3, [r1, #4] @ movhi + movs r2, r2, lsr #24 + ldrne r4, [sp, #40] + ldrneh r4, [r4, #6] + strneh r4, [r1, #6] @ movhi +.L22643: + ldr r5, [sp, #40] + add r7, r1, #8 + add r5, r5, #8 + str r5, [sp, #40] + b .L22629 +.L22818: + ldr lr, [sp, #120] + mov r3, ip, asl #3 + ldr r1, [sl, #4] + add r2, lr, ip + sub r3, r3, #32 + cmp r2, #4 + mov r1, r1, asl r3 + bhi .L22825 + cmp lr, #0 + movne r2, #0 + beq .L22229 +.L22841: + movs r5, r1, lsr #24 + ldrne r6, [sp, #40] + mov r3, r2, asl #1 + ldrneh ip, [r3, r6] + ldr lr, [sp, #120] + ldrne r6, [sp, #100] + add r2, r2, #1 + strneh ip, [r3, r6] @ movhi + cmp lr, r2 + mov r1, r1, asl #8 + bne .L22841 + b .L22229 +.L22598: + ldr r0, [sp, #120] + ldr r3, [sl, #0] + add r2, r0, ip + mov r1, ip, asl #3 + cmp r2, #4 + mov r3, r3, lsr r1 + bhi .L22605 + cmp r0, #0 + movne r1, #0 + beq .L22229 +.L22621: + tst r3, #255 + ldrne r5, [sp, #40] + mov r2, r1, asl #1 + ldrneh r6, [r2, r5] + ldr ip, [sp, #120] + ldrne r5, [sp, #100] + add r1, r1, #1 + strneh r6, [r2, r5] @ movhi + cmp ip, r1 + mov r3, r3, lsr #8 + bne .L22621 + b .L22229 +.L22825: + rsbs r2, ip, #4 + ldreq r3, [sp, #100] + beq .L22830 + mov r0, #0 +.L22831: + movs r3, r1, lsr #24 + ldrne r4, [sp, #40] + mov r3, r0, asl #1 + ldrneh r5, [r3, r4] + ldrne r4, [sp, #100] + add r0, r0, #1 + strneh r5, [r3, r4] @ movhi + cmp r0, r2 + mov r1, r1, asl #8 + bne .L22831 + ldr r6, [sp, #40] + mov r3, r2, asl #1 + ldr ip, [sp, #100] + add r6, r6, r3 + str r6, [sp, #40] + add r3, r3, ip +.L22830: + ldr lr, [sp, #120] + subs ip, lr, r2 + ldr r2, [sl, #0] + beq .L22229 + mov r0, #0 +.L22837: + movs r1, r2, lsr #24 + ldrne r4, [sp, #40] + mov r1, r0, asl #1 + ldrneh r4, [r1, r4] + add r0, r0, #1 + strneh r4, [r1, r3] @ movhi + cmp r0, ip + mov r2, r2, asl #8 + bne .L22837 + b .L22229 +.L22605: + rsbs r1, ip, #4 + ldreq ip, [sp, #100] + beq .L22610 + mov r0, #0 +.L22611: + tst r3, #255 + ldrne r4, [sp, #40] + mov r2, r0, asl #1 + ldrneh r5, [r2, r4] + ldrne r4, [sp, #100] + add r0, r0, #1 + strneh r5, [r2, r4] @ movhi + cmp r0, r1 + mov r3, r3, lsr #8 + bne .L22611 + ldr r6, [sp, #40] + mov r3, r1, asl #1 + ldr lr, [sp, #100] + add r6, r6, r3 + str r6, [sp, #40] + add ip, r3, lr +.L22610: + ldr r2, [sp, #120] + ldr r3, [sl, #4] + subs r0, r2, r1 + beq .L22229 + mov r1, #0 +.L22617: + tst r3, #255 + ldrne r4, [sp, #40] + mov r2, r1, asl #1 + ldrneh r4, [r2, r4] + add r1, r1, #1 + strneh r4, [r2, ip] @ movhi + cmp r1, r0 + mov r3, r3, lsr #8 + bne .L22617 + b .L22229 + .size render_scanline_obj_copy_bitmap_1D, .-render_scanline_obj_copy_bitmap_1D + .align 2 + .global render_scanline_window_bitmap + .type render_scanline_window_bitmap, %function +render_scanline_window_bitmap: + @ args = 0, pretend = 0, frame = 20 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr lr, .L23662 + mov r2, r1, lsr #13 + ldrh ip, [lr, #74] + ldr r3, .L23662+4 + and ip, ip, #63 + sub sp, sp, #32 + mov r6, r1 + sub r2, r2, #1 + and r1, r1, #7 + str ip, [sp, #12] + add r9, r3, r1, asl #2 + mov r7, r0 + ldrh ip, [lr, #6] + ldrh sl, [lr, #80] + cmp r2, #6 + ldrls pc, [pc, r2, asl #2] + b .L23576 + .p2align 2 +.L23095: + .word .L23088 + .word .L23089 + .word .L23090 + .word .L23091 + .word .L23092 + .word .L23093 + .word .L23094 +.L23089: + ldrh r3, [lr, #70] + ldr r4, .L23662 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L23117 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + bne .L23125 +.L23580: + cmp r1, #227 + bhi .L23125 +.L23121: + mov r4, #240 + mov r5, r4 +.L23133: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23134: + cmp r5, r4 + beq .L23114 + mov r0, r5 + mov r3, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23114: + cmp r4, #240 + beq .L23576 + ldr r3, [sp, #12] + mov r0, r4 + mov r2, r7 +.L23623: + mov r1, #240 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23576: + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L23088: + ldrh r3, [lr, #68] + ldr r4, .L23662 + and r2, r3, #255 + mov r1, r3, lsr #8 + cmp r1, r2 + ldrh r0, [lr, #72] + bls .L23096 + cmp ip, r1 + movls r3, #0 + movhi r3, #1 + cmp ip, r2 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23578 +.L23104: + cmp r1, #227 + bhi .L23121 + ldrh r3, [r4, #64] + and r8, r0, #63 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + bhi .L23645 +.L23124: + cmp r5, r4 + bls .L23128 + cmp r4, #0 + bne .L23646 +.L23130: + mov r0, r4 + ldr r3, [sp, #12] + mov r2, r7 + mov r1, r5 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + cmp r5, #240 + movne r0, r5 + movne r2, r7 + movne r3, r8 + bne .L23623 + b .L23576 +.L23094: + ldrh r3, [lr, #68] + ldr r2, .L23662 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r4, [lr, #72] + bls .L23360 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23639 +.L23368: + cmp r0, #227 + bls .L23647 +.L23364: + mov r8, #240 + mov fp, r8 +.L23367: + ldrh r3, [lr, #70] + ldr r0, .L23662 + and r1, r3, #255 + mov r2, r3, lsr #8 + cmp r2, r1 + bls .L23371 + cmp ip, r2 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23640 +.L23379: + cmp r2, #227 + bls .L23648 +.L23375: + mov r5, #240 + mov r4, r5 +.L23378: + cmp fp, r8 + bls .L23382 + cmp r8, #0 + bne .L23649 +.L23384: + cmp r4, #240 + beq .L23386 + cmp r4, r5 + bhi .L23650 + cmp r4, #0 + beq .L23426 + cmp r8, #0 + beq .L23428 + cmp r8, r4 + bcs .L23426 +.L23428: + cmp fp, r4 + bcs .L23437 + mov r0, r8 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23439 + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23426: + cmp r4, r5 + beq .L23443 + cmp r8, r4 + bls .L23445 + cmp r8, r5 + bcs .L23443 + cmp fp, r5 + ldrcc r3, [sp, #28] + ldrcs r3, [sp, #28] + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 +.L23612: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23443: + cmp r5, #240 + beq .L23418 + cmp r8, r5 + bls .L23454 + cmp r8, #239 + bhi .L23418 + cmp fp, #239 + bhi .L23457 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23459 + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23422 +.L23093: + ldrh r3, [lr, #70] + ldr r4, .L23662 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L23330 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23605 +.L23338: + cmp r0, #227 + bls .L23651 +.L23334: + mov r4, #240 + mov r5, r4 +.L23349: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23350: + ands r8, r6, #64 + beq .L23351 + mov r0, #4 + mov r1, #0 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23353: + cmp r4, r5 + beq .L23354 +.L23642: + mov r0, r5 + mov r3, fp + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23354: + cmp r4, #240 + beq .L23356 + ldr r3, [sp, #12] + mov r0, r4 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23356: + cmp r8, #0 + movne r1, r4 + beq .L23652 +.L23626: + mov r3, r7 + mov r0, #4 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_bitmap_1D +.L23092: + ldrh r3, [lr, #68] + ldr r4, .L23662 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r2, [lr, #72] + bls .L23300 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23603 +.L23308: + cmp r0, #227 + bls .L23653 +.L23304: + mov r4, #240 + mov r5, r4 +.L23319: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23320: + ands r8, r6, #64 + beq .L23321 + mov r0, #4 + mov r1, #0 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23323: + cmp r5, r4 + bne .L23642 + b .L23354 +.L23090: + ldrh r3, [lr, #68] + ldr r2, .L23662 + and r1, r3, #255 + mov r0, r3, lsr #8 + cmp r0, r1 + ldrh r4, [lr, #72] + bls .L23138 + cmp ip, r0 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23635 +.L23146: + cmp r0, #227 + bls .L23654 +.L23142: + mov r5, #240 + mov fp, r5 +.L23145: + ldrh r3, [lr, #70] + ldr r0, .L23662 + and r1, r3, #255 + mov r2, r3, lsr #8 + cmp r2, r1 + bls .L23149 + cmp ip, r2 + movls r3, #0 + movhi r3, #1 + cmp ip, r1 + orrls r3, r3, #1 + cmp r3, #0 + beq .L23636 +.L23157: + cmp r2, #227 + bls .L23655 +.L23153: + mov r8, #240 + mov r4, r8 +.L23156: + cmp fp, r5 + bls .L23160 + cmp r5, #0 + bne .L23656 +.L23162: + cmp r4, #240 + beq .L23164 + cmp r4, r8 + bls .L23166 + cmp r8, #0 + beq .L23168 + cmp r5, #0 + beq .L23170 + cmp r5, r8 + bcs .L23168 + cmp fp, r8 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23168: + cmp r5, r8 + bls .L23177 + cmp r5, r4 + bcs .L23179 + cmp fp, r4 + ldrcc r3, [sp, #12] + ldrcs r3, [sp, #12] + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r4 +.L23585: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23179: + cmp r5, r4 + bls .L23186 + cmp r5, #239 + bhi .L23188 + cmp fp, #239 + movls r0, r5 + bls .L23589 + ldr r3, [sp, #20] + mov r0, r5 + mov r1, #240 +.L23588: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23188: + cmp fp, #240 + beq .L23576 +.L23192: + ldr r3, [sp, #16] + mov r0, fp + mov r2, r7 + b .L23623 +.L23091: + mov r1, #240 + ldr r3, [sp, #12] + mov r0, #0 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_bitmap + ands r1, r6, #64 + beq .L23624 + mov r3, r7 + mov r0, #4 + mov r1, #0 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_bitmap_1D +.L23117: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + beq .L23580 +.L23125: + cmp r0, #227 + bhi .L23121 + ldrh r3, [r4, #66] + mov r2, r2, lsr #8 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + and r8, r2, #63 + bls .L23124 +.L23645: + mov r4, #240 + b .L23124 +.L23300: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23308 +.L23603: + cmp r1, #227 + bls .L23304 + b .L23308 +.L23149: + cmp ip, r2 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23157 +.L23636: + cmp r1, #227 + bls .L23153 + b .L23157 +.L23138: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23146 +.L23635: + cmp r1, #227 + bls .L23142 + b .L23146 +.L23371: + cmp ip, r2 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23379 +.L23640: + cmp r1, #227 + bls .L23375 + b .L23379 +.L23330: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23338 +.L23605: + cmp r1, #227 + bls .L23334 + b .L23338 +.L23096: + cmp ip, r1 + movcc r3, #0 + movcs r3, #1 + cmp ip, r2 + movcs r3, #0 + cmp r3, #0 + bne .L23104 +.L23578: + cmp r2, #227 + bls .L23121 + b .L23104 +.L23360: + cmp ip, r0 + movcc r3, #0 + movcs r3, #1 + cmp ip, r1 + movcs r3, #0 + cmp r3, #0 + bne .L23368 +.L23639: + cmp r1, #227 + bls .L23364 + b .L23368 +.L23652: + mov r1, r4 +.L23624: + mov r3, r7 + mov r0, #4 + mov r2, #240 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_bitmap_2D +.L23382: + cmp r4, #240 + beq .L23472 + cmp r4, r5 + bls .L23474 + cmp r5, #0 + beq .L23476 + cmp fp, r5 + bcs .L23478 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L23615 +.L23476: + cmp fp, r4 + bcs .L23481 + cmp fp, r5 + bhi .L23657 +.L23483: + cmp fp, #239 + bhi .L23489 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L23617 +.L23491: + cmp fp, r8 + beq .L23519 + mov r0, fp + ldr r3, [sp, #24] + mov r1, r8 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23519: + cmp r4, #240 + beq .L23521 + cmp r4, r5 + bls .L23523 + cmp r5, #0 + beq .L23525 + cmp r8, #0 + beq .L23527 + cmp r8, r5 + bcs .L23525 + cmp r5, #240 + movhi r0, r8 + movhi r1, #240 + movls r0, r8 + movls r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23525: + cmp r8, r5 + bls .L23534 + cmp r8, r4 + bcc .L23658 +.L23536: + cmp r8, r4 + bls .L23542 + cmp r8, #239 + bhi .L23576 + ldr r3, [sp, #28] + mov r0, r8 + mov r2, r7 + b .L23623 +.L23160: + cmp r4, #240 + beq .L23224 + cmp r4, r8 + bls .L23226 + cmp r8, #0 + beq .L23228 + cmp fp, r8 + bcs .L23230 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L23591 +.L23228: + cmp fp, r4 + bcs .L23233 + cmp fp, r8 + movhi r0, r8 + movhi r1, fp + bhi .L23592 +.L23235: + cmp fp, #239 + bhi .L23237 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L23595 +.L23239: + cmp fp, r5 + beq .L23256 + mov r0, fp + ldr r3, [sp, #16] + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23256: + cmp r4, #240 + beq .L23258 + cmp r4, r8 + bls .L23260 + cmp r8, #0 + beq .L23262 + cmp r5, #0 + beq .L23264 + cmp r5, r8 + bcs .L23262 + cmp r8, #240 + movhi r0, r5 + movhi r1, #240 + movls r0, r5 + movls r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23262: + cmp r5, r8 + bls .L23271 + cmp r5, r4 + ldrcc r3, [sp, #12] + movcc r0, r5 + bcc .L23599 +.L23273: + cmp r5, r4 + bls .L23275 + cmp r5, #239 + bhi .L23576 + ldr r3, [sp, #20] + mov r0, r5 + mov r2, r7 + b .L23623 +.L23351: + mov r0, #4 + mov r1, r8 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23353 +.L23321: + mov r0, #4 + mov r1, r8 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23323 +.L23653: + ldrh r3, [r4, #64] + and fp, r2, #63 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + movhi r4, #240 + cmp r5, r4 + bhi .L23644 + cmp r5, #0 + bne .L23319 + b .L23320 +.L23655: + ldrh r3, [r0, #66] + mov r2, r4, lsr #8 + and r8, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r4, r3 + movcs r4, #240 + cmp r8, #240 + and r2, r2, #63 + movhi r8, #240 + str r2, [sp, #20] + b .L23156 +.L23648: + ldrh r3, [r0, #66] + mov r2, r4, lsr #8 + and r5, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r4, r3 + movcs r4, #240 + cmp r5, #240 + and r2, r2, #63 + movhi r5, #240 + str r2, [sp, #28] + b .L23378 +.L23647: + ldrh r3, [r2, #64] + and r2, r4, #63 + and r8, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc fp, r3 + movcs fp, #240 + cmp r8, #240 + movhi r8, #240 + str r2, [sp, #24] + b .L23367 +.L23651: + ldrh r3, [r4, #66] + mov r2, r2, lsr #8 + and r4, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc r5, r3 + movcs r5, #240 + cmp r4, #240 + movhi r4, #240 + cmp r5, r4 + and fp, r2, #63 + bhi .L23644 + cmp r5, #0 + bne .L23349 + b .L23350 +.L23654: + ldrh r3, [r2, #64] + and r2, r4, #63 + and r5, r3, #255 + mov r3, r3, lsr #8 + cmp r3, #240 + movcc fp, r3 + movcs fp, #240 + cmp r5, #240 + movhi r5, #240 + str r2, [sp, #16] + b .L23145 +.L23650: + cmp r5, #0 + beq .L23390 + cmp r8, #0 + beq .L23392 + cmp r8, r5 + bcs .L23390 + cmp fp, r5 + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23390: + cmp r8, r5 + bls .L23399 + cmp r8, r4 + bcs .L23401 + cmp fp, r4 + bcs .L23403 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23405 + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23401: + cmp r8, r4 + bls .L23416 + cmp r8, #239 + bhi .L23418 + cmp fp, #239 + movls r0, r8 + movhi r0, r8 + bhi .L23613 +.L23614: + ldr r3, [sp, #28] + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23422: + ldr r3, [sp, #24] + mov r0, fp + mov r2, r7 + b .L23623 +.L23166: + cmp r4, #0 + beq .L23196 + cmp r5, #0 + beq .L23198 + cmp r5, r4 + bcs .L23196 +.L23198: + cmp fp, r4 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23196: + cmp r4, r8 + beq .L23205 + cmp r5, r4 + bls .L23207 + cmp r5, r8 + bcs .L23205 + cmp fp, r8 + ldrcc r3, [sp, #20] + ldrcs r3, [sp, #20] + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 +.L23587: + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23205: + cmp r8, #240 + beq .L23188 + cmp r5, r8 + bls .L23216 + cmp r5, #239 + bhi .L23188 + cmp fp, #239 + movls r0, r5 + ldrls r3, [sp, #12] + bls .L23590 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, #240 + b .L23588 +.L23649: + mov r0, #0 + mov r1, r8 + mov r2, r7 + ldr r3, [sp, #24] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23384 +.L23656: + mov r0, #0 + mov r1, r5 + mov r2, r7 + ldr r3, [sp, #16] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23162 +.L23472: + cmp fp, #0 + bne .L23659 +.L23515: + ands r1, r6, #64 + beq .L23517 + mov r0, #4 + mov r1, #0 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23491 +.L23224: + cmp fp, #0 + beq .L23239 + mov r0, #0 + mov r1, fp +.L23596: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23239 +.L23644: + cmp r4, #0 + bne .L23660 +.L23343: + ldr r3, [sp, #12] + mov r0, r4 + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23345 + mov r1, r4 + mov r0, #4 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23347: + cmp r5, #240 + movne r0, r5 + movne r2, r7 + movne r3, fp + bne .L23623 + b .L23576 +.L23128: + cmp r5, #0 + bne .L23133 + b .L23134 +.L23386: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23470 + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D +.L23418: + cmp fp, #240 + bne .L23422 + b .L23576 +.L23345: + mov r1, r4 + mov r0, #4 + mov r2, r5 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23347 +.L23663: + .align 2 +.L23662: + .word io_registers + .word bitmap_mode_renderers-12 +.L23523: + cmp r4, #0 + beq .L23545 + cmp r8, #0 + beq .L23547 + cmp r8, r4 + bcc .L23547 +.L23545: + cmp r4, r5 + beq .L23554 + cmp r8, r4 + bls .L23556 + cmp r8, r5 + bcs .L23554 + cmp r5, #240 + ldrhi r3, [sp, #28] + movhi r0, r8 + ldrls r3, [sp, #28] + movls r0, r8 + bls .L23621 +.L23622: + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23561: + cmp r8, r5 + bls .L23565 + cmp r8, #239 + bhi .L23576 + mov r1, #240 + ldr r3, [sp, #12] + mov r0, r8 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_bitmap + tst r6, #64 + moveq r1, r8 + beq .L23624 + mov r1, r8 + b .L23626 +.L23260: + cmp r4, #0 + beq .L23278 + cmp r5, #0 + beq .L23280 + cmp r5, r4 + bcc .L23280 +.L23278: + cmp r4, r8 + beq .L23283 + cmp r5, r4 + bls .L23285 + cmp r5, r8 + bcs .L23283 + cmp r8, #240 + ldrhi r3, [sp, #20] + movhi r0, r5 + ldrls r3, [sp, #20] + movls r0, r5 + bls .L23600 +.L23601: + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23290: + cmp r5, r8 + bls .L23294 + cmp r5, #239 + bhi .L23576 + ldr r3, [sp, #12] + mov r0, r5 + mov r2, r7 + b .L23623 +.L23474: + cmp r4, #0 + beq .L23493 + cmp fp, r4 + bcs .L23495 + cmp fp, #0 + bne .L23661 +.L23493: + cmp r4, r5 + beq .L23502 + cmp fp, r5 + bcs .L23504 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L23616 +.L23502: + cmp r5, #240 + beq .L23491 + cmp fp, #239 + bhi .L23508 + cmp fp, r5 + bls .L23491 + mov r0, r5 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23511 + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23491 +.L23226: + cmp r4, #0 + beq .L23241 + cmp fp, r4 + bcs .L23243 + cmp fp, #0 + movne r0, #0 + movne r1, fp + bne .L23593 +.L23241: + cmp r4, r8 + beq .L23246 + cmp fp, r8 + bcs .L23248 + cmp fp, r4 + movhi r0, r4 + movhi r1, fp + bhi .L23594 +.L23246: + cmp r8, #240 + beq .L23239 + cmp fp, #239 + bhi .L23252 + cmp fp, r8 + movhi r0, r8 + movhi r1, fp + bls .L23239 + b .L23596 +.L23521: + cmp r8, #240 + beq .L23572 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_bitmap +.L23572: + tst r6, #64 + beq .L23574 + mov r1, r8 + mov r2, r4 + mov r3, r7 + mov r0, #4 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_bitmap_1D +.L23258: + cmp r5, #240 + beq .L23576 + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23576 +.L23392: + cmp fp, r5 + movcc r0, r8 + movcc r1, fp + movcs r0, r8 + movcs r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23399: + cmp fp, r4 + bcs .L23409 + cmp fp, r5 + bls .L23401 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23412 + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23401 +.L23170: + cmp fp, r8 + movcc r0, r5 + movcc r1, fp + movcs r0, r5 + movcs r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23177: + cmp fp, r4 + bcs .L23183 + cmp fp, r8 + bls .L23179 + ldr r3, [sp, #12] + mov r0, r8 + mov r1, fp + b .L23585 +.L23264: + cmp r8, #240 + movhi r0, r5 + movhi r1, #240 + movls r0, r5 + movls r1, r8 + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23271: + ldr r3, [sp, #12] + mov r0, r8 +.L23599: + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23273 +.L23291: + ldr r3, [sp, #20] + mov r0, r4 +.L23600: + mov r1, r8 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23283: + cmp r8, #240 + bne .L23290 + b .L23576 +.L23562: + ldr r3, [sp, #28] + mov r0, r4 +.L23621: + mov r1, r5 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23554: + cmp r5, #240 + bne .L23561 + b .L23576 +.L23646: + mov r0, #0 + mov r1, r4 + mov r2, r7 + mov r3, r8 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23130 +.L23660: + mov r0, #0 + mov r1, r4 + mov r2, r7 + mov r3, fp + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23343 +.L23527: + cmp r5, #240 + movhi r0, r8 + movhi r1, #240 + movls r0, r8 + movls r1, r5 + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap +.L23534: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23540 + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23536 +.L23416: + cmp fp, #239 + bhi .L23423 + cmp fp, r4 + bls .L23422 + mov r0, r4 + b .L23614 +.L23186: + cmp fp, #239 + bhi .L23193 + cmp fp, r4 + bls .L23192 + mov r0, r4 +.L23589: + ldr r3, [sp, #20] +.L23590: + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23192 +.L23237: + mov r0, r4 + mov r1, #240 +.L23595: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23239 +.L23489: + mov r0, r4 + mov r1, #240 +.L23617: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23491 +.L23233: + mov r0, r8 + mov r1, r4 +.L23592: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23235 +.L23216: + cmp fp, #239 + bhi .L23221 + cmp fp, r8 + movhi r0, r8 + ldrhi r3, [sp, #12] + bls .L23192 + b .L23590 +.L23445: + cmp fp, r5 + bcs .L23450 + cmp fp, r4 + bls .L23443 + ldr r3, [sp, #28] + mov r0, r4 + mov r1, fp + b .L23612 +.L23454: + cmp fp, #239 + bhi .L23463 + cmp fp, r5 + bls .L23422 + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23466 + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23422 +.L23207: + cmp fp, r8 + bcs .L23212 + cmp fp, r4 + bls .L23205 + ldr r3, [sp, #20] + mov r0, r4 + mov r1, fp + b .L23587 +.L23164: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, fp + b .L23588 +.L23574: + mov r1, r8 + mov r2, r4 + mov r3, r7 + mov r0, #4 + add sp, sp, #32 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + b render_scanline_obj_copy_bitmap_2D +.L23517: + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23491 +.L23504: + mov r0, r4 + mov r1, r5 +.L23616: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23502 +.L23248: + mov r0, r4 + mov r1, r8 +.L23594: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23246 +.L23285: + cmp r8, #240 + bls .L23291 + cmp r4, #239 + bhi .L23290 + ldr r3, [sp, #20] + mov r0, r4 + b .L23601 +.L23556: + cmp r5, #240 + bls .L23562 + cmp r4, #239 + bhi .L23561 + ldr r3, [sp, #28] + mov r0, r4 + b .L23622 +.L23423: + mov r0, r4 +.L23613: + ldr r3, [sp, #28] + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23418 +.L23540: + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23536 +.L23481: + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23487 + mov r0, #4 + mov r1, r5 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23483 +.L23542: + ldr r3, [sp, #28] + mov r0, r4 + mov r2, r7 + b .L23623 +.L23275: + ldr r3, [sp, #20] + mov r0, r4 + mov r2, r7 + b .L23623 +.L23294: + ldr r3, [sp, #12] + mov r0, r8 + mov r2, r7 + b .L23623 +.L23565: + mov r1, #240 + ldr r3, [sp, #12] + mov r0, r5 + mov r2, r7 + str sl, [sp, #4] + str r9, [sp, #8] + str r6, [sp, #0] + bl render_scanline_conditional_bitmap + tst r6, #64 + movne r1, r5 + moveq r1, r5 + beq .L23624 + b .L23626 +.L23478: + mov r0, #0 + mov r1, r5 +.L23615: + mov r2, r7 + ldr r3, [sp, #28] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23476 +.L23243: + mov r0, #0 + mov r1, r4 +.L23593: + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23241 +.L23230: + mov r0, #0 + mov r1, r8 +.L23591: + mov r2, r7 + ldr r3, [sp, #20] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23228 +.L23547: + mov r0, r8 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23552 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23545 +.L23280: + mov r0, r5 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23278 +.L23659: + mov r0, #0 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + b .L23515 +.L23409: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23414 + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23401 +.L23183: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + b .L23585 +.L23437: + mov r0, r8 + mov r1, r4 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23441 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23426 +.L23252: + mov r0, r8 + mov r1, #240 + b .L23596 +.L23470: + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23418 +.L23508: + mov r0, r5 + mov r1, #240 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23513 + mov r0, #4 + mov r1, r5 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23491 +.L23657: + mov r0, r5 + mov r1, fp + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23485 + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23483 +.L23193: + ldr r3, [sp, #20] + mov r0, r4 + mov r1, #240 + b .L23588 +.L23495: + mov r1, r4 + mov r0, #0 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + ands r1, r6, #64 + beq .L23500 + mov r0, #4 + mov r1, #0 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23493 +.L23487: + mov r0, #4 + mov r1, r5 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23483 +.L23552: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23545 +.L23221: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, #240 + b .L23588 +.L23212: + ldr r3, [sp, #20] + mov r0, r4 + mov r1, r8 + b .L23587 +.L23463: + ldr r3, [sp, #12] + mov r0, r5 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23468 + mov r1, r5 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23418 +.L23450: + ldr r3, [sp, #28] + mov r0, r4 + mov r1, r5 + b .L23612 +.L23658: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23538 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23536 +.L23403: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, r4 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23407 + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23401 +.L23439: + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23426 +.L23414: + mov r1, r5 + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23401 +.L23441: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23426 +.L23513: + mov r0, #4 + mov r1, r5 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23491 +.L23457: + ldr r3, [sp, #12] + mov r0, r8 + mov r1, #240 + mov r2, r7 + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + tst r6, #64 + beq .L23461 + mov r1, r8 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23418 +.L23661: + mov r1, fp + mov r0, #0 + mov r2, r7 + ldr r3, [sp, #12] + stmia sp, {r6, sl} @ phole stm + str r9, [sp, #8] + bl render_scanline_conditional_bitmap + ands r1, r6, #64 + beq .L23498 + mov r0, #4 + mov r1, #0 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_1D + b .L23493 +.L23485: + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23483 +.L23412: + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23401 +.L23500: + mov r0, #4 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23493 +.L23511: + mov r0, #4 + mov r1, r5 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23491 +.L23468: + mov r1, r5 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23418 +.L23461: + mov r1, r8 + mov r0, #4 + mov r2, #240 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23418 +.L23405: + mov r0, #4 + mov r1, r8 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23401 +.L23538: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23536 +.L23498: + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23493 +.L23407: + mov r0, #4 + mov r1, r8 + mov r2, r4 + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23401 +.L23459: + mov r1, r8 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23422 +.L23466: + mov r1, r5 + mov r0, #4 + mov r2, fp + mov r3, r7 + bl render_scanline_obj_copy_bitmap_2D + b .L23422 + .size render_scanline_window_bitmap, .-render_scanline_window_bitmap + .align 2 + .global update_scanline + .type update_scanline, %function +update_scanline: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 0, uses_anonymous_args = 0 + stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ldr r2, .L23760 + ldr r0, .L23760+4 + ldr r9, .L23760+8 + ldr r3, [r0, #0] + ldr r1, [r2, #0] + cmp r3, #0 + ldr r2, [r1, #20] + ldrh fp, [r9, #0] + ldrh r1, [r1, #16] + ldrh r3, [r9, #6] + sub sp, sp, #12 + str r2, [sp, #8] + stmia sp, {r1, r3} @ phole stm + and sl, fp, #7 + movne ip, #0 + bne .L23669 +.L23666: + ldr r2, .L23760+12 + ldr r0, [sp, #4] + ldr r3, [r2, sl, asl #2] + ldr r2, .L23760+16 + and r3, r3, fp, lsr #8 + add lr, r2, r0, asl #2 + ldr r2, .L23760+20 + mov r1, #0 + mov r5, r1 + and r7, r3, #1 + and r0, r3, #16 + mov ip, #3 + and r8, r3, #8 + and r6, r3, #4 + and r4, r3, #2 + str r1, [r2, #0] +.L23696: + cmp r8, #0 + beq .L23725 + ldrh r3, [r9, #14] + and r3, r3, #3 + cmp r3, ip + ldreq r3, .L23760+24 + moveq r2, #3 + streq r2, [r3, r5, asl #2] + addeq r5, r5, #1 +.L23725: + cmp r6, #0 + beq .L23728 + ldrh r3, [r9, #12] + and r3, r3, #3 + cmp r3, ip + ldreq r3, .L23760+24 + moveq r2, #2 + streq r2, [r3, r5, asl #2] + addeq r5, r5, #1 +.L23728: + cmp r4, #0 + beq .L23731 + ldrh r3, [r9, #10] + and r3, r3, #3 + cmp r3, ip + ldreq r3, .L23760+24 + moveq r2, #1 + streq r2, [r3, r5, asl #2] + addeq r5, r5, r2 +.L23731: + cmp r7, #0 + beq .L23698 + ldrh r3, [r9, #8] + and r3, r3, #3 + cmp r3, ip + ldreq r3, .L23760+24 + moveq r2, #0 + streq r2, [r3, r5, asl #2] + addeq r5, r5, #1 +.L23698: + ldr r3, [lr, #1920] + cmp r3, #0 + beq .L23700 + cmp r0, #0 + ldrne r3, .L23760+24 + orrne r2, ip, #4 + strne r2, [r3, r5, asl #2] + addne r5, r5, #1 +.L23700: + sub ip, ip, #1 + cmn ip, #1 + sub lr, lr, #640 + bne .L23696 + ldr r3, .L23760+20 + str r5, [r3, #0] + ldr r3, .L23760+28 + ldr r1, [r3, #0] + cmp r1, #0 + bne .L23734 + ldr r0, [sp, #0] + ldr r4, [sp, #8] + mov r2, r0, lsr #1 + ldr r0, [sp, #4] + tst fp, #128 + mov r3, r0, asl #1 + mla r4, r3, r2, r4 + beq .L23706 + mov r3, r1 +.L23708: + mvn r1, #0 @ movhi + strh r1, [r3, r4] @ movhi + add r3, r3, #2 + cmp r3, #480 + bne .L23708 +.L23709: + ldr lr, .L23760+32 + ldr r4, .L23760+36 + ldr r5, [lr, #0] + ldr r6, [r4, #0] + ldr r3, [lr, #4] + ldr r2, [r4, #4] + ldrsh r7, [r9, #54] + ldrsh r1, [r9, #34] + ldrsh r0, [r9, #38] + ldrsh ip, [r9, #50] + add r5, r5, r1 + add r6, r6, r0 + add r3, r3, ip + add r2, r2, r7 + str r3, [lr, #4] + str r2, [r4, #4] + str r5, [lr, #0] + str r6, [r4, #0] +.L23734: + add sp, sp, #12 + ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} +.L23759: + add ip, ip, #1 + cmp ip, #5 + beq .L23752 +.L23669: + ldr r1, .L23760+16 + add r3, ip, ip, asl #2 + add r2, r1, r3, asl #7 + mov r3, #0 +.L23667: + add r3, r3, #1 + mov r1, #0 + cmp r3, #160 + str r1, [r2], #4 + bne .L23667 + b .L23759 +.L23752: + ldr r3, .L23760+40 + add r2, r3, #640 +.L23671: + str r1, [r3], #4 + cmp r3, r2 + bne .L23671 + ldr r6, .L23760+44 + mov r7, #127 +.L23673: + ldrh r2, [r6, #8] + ldrh r0, [r6, #12] + and r1, r2, #49152 + and r3, r2, #768 + cmp r3, #512 + cmpne r1, #49152 + beq .L23674 + mov r3, r2, lsr #10 + and r4, r3, #3 + cmp r4, #3 + beq .L23674 + cmp sl, #2 + bls .L23677 + mov r3, r0, asl #22 + mov r3, r3, lsr #22 + cmp r3, #512 + bcc .L23674 +.L23677: + ldrh r5, [r6, #10] + and ip, r2, #255 + mov r3, r5, lsr #14 + orr r3, r3, r1, lsr #12 + ldr r1, .L23760+48 + cmp ip, #160 + subgt ip, ip, #256 + ldr r1, [r1, r3, asl #2] + tst r2, #512 + ldr r2, .L23760+52 + movne r1, r1, asl #1 + ldr r2, [r2, r3, asl #2] + add lr, ip, r1 + movne r2, r2, asl #1 + cmp lr, #0 + movle r3, #0 + movgt r3, #1 + cmp ip, #159 + movgt r3, #0 + cmp r3, #0 + beq .L23674 + mov r3, r5, asl #23 + mov r3, r3, asr #23 + add r2, r2, r3 + cmp r2, #0 + movle r1, #0 + movgt r1, #1 + cmp r3, #239 + movgt r1, #0 + cmp r1, #0 + beq .L23674 + cmp ip, #0 + movlt ip, #0 + cmp lr, #160 + movge lr, #160 + mov r3, r0, lsr #10 + cmp r4, #1 + and r3, r3, #3 + beq .L23754 + cmp r4, #2 + moveq r3, #4 + cmp ip, lr + bge .L23674 + add r3, r3, r3, asl #2 + ldr r2, .L23760+56 + ldr r0, .L23760+16 + rsb r1, ip, lr + add r3, ip, r3, asl #5 + mov r4, ip + add r1, ip, r1 + add lr, r2, r3, asl #7 + and r5, r7, #255 + add ip, r0, r3, asl #2 +.L23694: + ldr r2, [ip, #0] + add r4, r4, #1 + add r3, r2, #1 + cmp r4, r1 + strb r5, [lr, r2] + str r3, [ip], #4 + add lr, lr, #128 + bne .L23694 +.L23674: + sub r7, r7, #1 + cmn r7, #1 + sub r6, r6, #8 + bne .L23673 +.L23755: + ldr r1, .L23760+4 + mov r3, #0 + str r3, [r1, #0] + b .L23666 +.L23754: + cmp ip, lr + bge .L23674 + ldr r2, .L23760+56 + add r3, r3, r3, asl #2 + rsb r1, ip, lr + add r3, ip, r3, asl #5 + add r8, ip, r1 + add r4, r2, r3, asl #7 + ldr r1, .L23760+16 + ldr r2, .L23760+40 + mov r5, ip + and r0, r7, #255 + add lr, r1, r3, asl #2 + add ip, r2, ip, asl #2 +.L23690: + ldr r3, [lr, #0] + ldr r2, [ip, #0] + add r5, r5, #1 + add r1, r3, #1 + add r2, r2, #1 + cmp r5, r8 + strb r0, [r4, r3] + str r1, [lr], #4 + str r2, [ip], #4 + add r4, r4, #128 + bne .L23690 + sub r7, r7, #1 + cmn r7, #1 + sub r6, r6, #8 + bne .L23673 + b .L23755 +.L23706: + cmp sl, #2 + bls .L23756 + movs r0, fp, lsr #13 + bne .L23757 + ldr r3, .L23760+60 + ldr r2, .L23760+64 + ldrh r1, [r3, #0] + add r8, r2, sl, asl #2 + mov r3, r0 +.L23716: + strh r1, [r3, r4] @ movhi + add r3, r3, #2 + cmp r3, #480 + bne .L23716 + cmp r5, #0 + beq .L23709 + ldr r6, .L23760+24 + and r7, fp, #64 + mov r5, #0 + b .L23719 +.L23758: + bl render_scanline_obj_normal_1D +.L23724: + ldr r0, .L23760+20 + add r5, r5, #1 + ldr r3, [r0, #0] + add r6, r6, #4 + cmp r3, r5 + bls .L23709 +.L23719: + ldr ip, [r6, #0] + mov r1, #240 + ands r0, ip, #4 + mov r2, r4 + beq .L23720 + sub r1, r1, #240 + bic ip, ip, #4 + cmp r7, r1 + mov r2, #240 + mov r3, r4 + mov r0, ip + bne .L23758 + mov r0, ip + mov r1, r7 + mov r2, #240 + mov r3, r4 + bl render_scanline_obj_normal_2D + b .L23724 +.L23756: + movs r2, fp, lsr #13 + beq .L23712 + mov r0, r4 + mov r1, fp + bl render_scanline_window_tile + b .L23709 +.L23720: + mov lr, pc + ldr pc, [r8, #0] + b .L23724 +.L23712: + mov r0, r4 + mov r1, fp + bl render_scanline_tile + b .L23709 +.L23757: + mov r0, r4 + mov r1, fp + bl render_scanline_window_bitmap + b .L23709 +.L23761: + .align 2 +.L23760: + .word screen + .word oam_update + .word io_registers + .word active_layers + .word obj_priority_count + .word layer_count + .word layer_order + .word skip_next_frame + .word affine_reference_x + .word affine_reference_y + .word obj_alpha_count + .word oam_ram+1008 + .word obj_height_table + .word obj_width_table + .word obj_priority_list + .word palette_ram_converted + .word bitmap_mode_renderers-12 + .size update_scanline, .-update_scanline + .global video_scale + .section .rodata + .align 2 + .type video_scale, %object + .size video_scale, 4 +video_scale: + .word 1 + .global map_widths + .data + .align 2 + .type map_widths, %object + .size map_widths, 16 +map_widths: + .word 256 + .word 512 + .word 256 + .word 512 + .global map_heights + .align 2 + .type map_heights, %object + .size map_heights, 16 +map_heights: + .word 256 + .word 256 + .word 512 + .word 512 + .global tile_mode_renderers + .align 2 + .type tile_mode_renderers, %object + .size tile_mode_renderers, 384 +tile_mode_renderers: + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word render_scanline_text_transparent_alpha + .word render_scanline_text_base_color16 + .word render_scanline_text_transparent_color16 + .word render_scanline_text_base_color32 + .word render_scanline_text_transparent_color32 + .word render_scanline_affine_base_normal + .word render_scanline_affine_transparent_normal + .word render_scanline_affine_base_alpha + .word render_scanline_affine_transparent_alpha + .word render_scanline_affine_base_color16 + .word render_scanline_affine_transparent_color16 + .word render_scanline_affine_base_color32 + .word render_scanline_affine_transparent_color32 + .word render_scanline_text_base_normal + .word render_scanline_text_transparent_normal + .word render_scanline_text_base_alpha + .word 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.short -30720 + .short -26624 + .short 26624 + .short 2048 + .short -30720 + .short 28672 + .align 2 + .type C.627.17651, %object + .size C.627.17651, 8 +C.627.17651: + .short 40 + .short 40 + .short 240 + .short 160 + .align 2 + .type C.626.17650, %object + .size C.626.17650, 8 +C.626.17650: + .short 0 + .short 0 + .short 240 + .short 160 + .global affine_reference_x + .bss + .align 2 + .type affine_reference_x, %object + .size affine_reference_x, 8 +affine_reference_x: + .space 8 + .global affine_reference_y + .align 2 + .type affine_reference_y, %object + .size affine_reference_y, 8 +affine_reference_y: + .space 8 + .global hw_screen + .align 2 + .type hw_screen, %object + .size hw_screen, 4 +hw_screen: + .space 4 + .global screen + .align 2 + .type screen, %object + .size screen, 4 +screen: + .space 4 + .global obj_priority_list + .type obj_priority_list, %object + .size obj_priority_list, 102400 +obj_priority_list: + .space 102400 + .global obj_priority_count + .align 2 + .type obj_priority_count, %object + .size obj_priority_count, 3200 +obj_priority_count: + .space 3200 + .global obj_alpha_count + .align 2 + .type obj_alpha_count, %object + .size obj_alpha_count, 640 +obj_alpha_count: + .space 640 + .global layer_order + .align 2 + .type layer_order, %object + .size layer_order, 64 +layer_order: + .space 64 + .global layer_count + .align 2 + .type layer_count, %object + .size layer_count, 4 +layer_count: + .space 4 + .global resolution_width + .align 2 + .type resolution_width, %object + .size resolution_width, 4 +resolution_width: + .space 4 + .global resolution_height + .align 2 + .type resolution_height, %object + .size resolution_height, 4 +resolution_height: + .space 4 + .global frame_to_render + .align 2 + .type frame_to_render, %object + .size frame_to_render, 4 +frame_to_render: + .space 4 + .ident "GCC: (GNU) 4.1.1" diff --git a/gp2x/video_blend.S b/gp2x/video_blend.S new file mode 100644 index 0000000..63a5480 --- /dev/null +++ b/gp2x/video_blend.S @@ -0,0 +1,181 @@ +.align 2 + +.global expand_blend +.global expand_normal + +@ Input: +@ r0 = screen_src_ptr +@ r1 = screen_dest_ptr +@ r2 = start +@ r3 = end + +6: + .word io_registers + .word palette_ram_converted + .word 0x04000200 @ combine test mask + .word 0x07E0F81F @ clamp mask + .word 0x000003FE @ palette index mask + .word 0x08010020 @ saturation mask + +expand_blend: + stmdb sp!, { r4, r5, r6, r9, r10, r11, r14 } + + add r0, r0, r2, lsl #2 @ screen_src_ptr += start + add r1, r1, r2, lsl #1 @ screen_dest_ptr += start + sub r2, r3, r2 @ r2 = end - start + ldr r3, 6b @ r3 = io_registers + ldr r3, [r3, #0x52] @ r3 = bldalpha + mov r4, r3, lsr #8 @ r4 = bldalpha >> 8 + and r3, r3, #0x1F @ r3 = blend_a + and r4, r4, #0x1F @ r4 = blend_b + cmp r3, #16 @ if(blend_a > 16) + movgt r3, #16 @ blend_a = 16 + cmp r4, #16 @ if(blend_b > 16) + movgt r3, #16 @ blend_b = 16 + + ldr r14, 6b + 4 @ r14 = palette_ram_converted + ldr r12, 6b + 8 @ r12 = 0x04000200 + ldr r11, 6b + 12 @ r11 = 0x07E0F81F + ldr r10, 6b + 16 @ r10 = 0x000003FE + + add r5, r3, r4 @ r5 = blend_a + blend_b + cmp r5, #16 @ if((blend_a + blend_b) > 16) + bgt 3f @ goto loop w/saturation + + + @ loop w/o saturation +1: + ldr r5, [r0], #4 @ r5 = pixel_pair, screen_src_ptr++ + and r6, r5, r12 @ r6 = r5 & 0x04000200 + cmp r6, r12 @ if(r6 != 0x4000200) + bne 2f @ goto no_blend + + and r6, r10, r5, lsl #1 @ r6 = (pixel_pair & 0x1FF) << 1 + ldrh r6, [r14, r6] @ r6 = pixel_top + orr r6, r6, r6, lsl #16 @ r6 = pixel_top | (pixel_top << 16) + and r6, r6, r11 @ r6 = pixel_top_dilated + + and r5, r10, r5, lsr #15 @ r5 = ((pixel_pair >> 16) & 0x1FF) << 1 + ldrh r5, [r14, r5] @ r5 = pixel_bottom + orr r5, r5, r5, lsl #16 @ r5 = pixel_bottom | (pixel_bottom << 16) + and r5, r5, r11 @ r5 = pixel_bottom_dilated + + mul r5, r4, r5 @ r5 = pixel_bottom * blend_b = bottom_mul + mla r5, r3, r6, r5 @ r5 = (pixel_top * blend_a) + bottom_mul + + and r5, r11, r5, lsr #4 @ r5 = (color_dilated >> 4) & 0x07E0F81F + orr r5, r5, r5, lsr #16 @ r5 = color_dilated | (color_dilated >> 16) + + strh r5, [r1], #2 @ *screen_dest_ptr = r5, screen_dest_ptr++ + subs r2, r2, #1 @ counter-- + bne 1b @ go again + + ldmia sp!, { r4, r5, r6, r9, r10, r11, pc } + +2: + and r5, r10, r5, lsl #1 @ r5 = (pixel_pair & 0x1FF) << 1 + ldrh r5, [r14, r5] @ r5 = pixel_top + strh r5, [r1], #2 @ *screen_dest_ptr = r5, screen_dest_ptr++ + + subs r2, r2, #1 @ counter-- + bne 1b @ go again + + ldmia sp!, { r4, r5, r6, r9, r10, r11, pc } + +@ loop w/saturation + +3: + ldr r9, 6b + 20 @ r9 = 0x08010020 + +4: + ldr r5, [r0], #4 @ r5 = pixel_pair, screen_src_ptr++ + and r6, r5, r12 @ r6 = r5 & 0x04000200 + cmp r6, r12 @ if(r6 != 0x4000200) + bne 5f @ goto no_blend + + and r6, r10, r5, lsl #1 @ r6 = (pixel_pair & 0x1FF) << 1 + ldrh r6, [r14, r6] @ r6 = pixel_top + orr r6, r6, r6, lsl #16 @ r6 = pixel_top | (pixel_top << 16) + and r6, r6, r11 @ r6 = pixel_top_dilated + + and r5, r10, r5, lsr #15 @ r5 = ((pixel_pair >> 16) & 0x1FF) << 1 + ldrh r5, [r14, r5] @ r5 = pixel_bottom + orr r5, r5, r5, lsl #16 @ r5 = pixel_bottom | (pixel_bottom << 16) + and r5, r5, r11 @ r5 = pixel_bottom_dilated + + mul r5, r4, r5 @ r5 = pixel_bottom * blend_b = bottom_mul + mla r5, r3, r6, r5 @ r5 = (pixel_top * blend_a) + bottom_mul + + and r6, r9, r5, lsr #4 @ r6 = saturation bits + orr r6, r6, r6, lsr #1 @ propogate saturation down msb + orr r6, r6, r6, lsr #2 @ propogate down next two bits + orr r6, r6, r6, lsr #3 @ propogate down next three bits + orr r5, r6, r5, lsr #4 @ mask over result w/saturation + + and r5, r11, r5 @ r5 = (color_dilated >> 4) & 0x07E0F81F + orr r5, r5, r5, lsr #16 @ r5 = color_dilated | (color_dilated >> 16) + strh r5, [r1], #2 @ *screen_dest_ptr = r5, screen_dest_ptr++ + + subs r2, r2, #1 @ counter-- + bne 4b @ go again + + ldmia sp!, { r4, r5, r6, r9, r10, r11, pc } + +5: + and r5, r10, r5, lsl #1 @ r5 = (pixel_pair & 0x1FF) << 1 + ldrh r5, [r14, r5] @ r5 = pixel_top + strh r5, [r1], #2 @ *screen_dest_ptr = r5, screen_dest_ptr++ + + subs r2, r2, #1 @ counter-- + bne 4b @ go again + + ldmia sp!, { r4, r5, r6, r9, r10, r11, pc } + + + +@ The following function isn't complete (only works on run multiples of 8), +@ but unfortunately I don't see much potential for actually being able to +@ use it.. + +#define expand_pixel_pair(reg, temp) ;\ + and temp, r3, reg, lsr #15 ;\ + ldrh temp, [r2, temp] ;\ + ;\ + and reg, r3, reg, lsl #1 ;\ + ldrh reg, [r2, reg] ;\ + ;\ + orr reg, reg, temp, lsl #16 ;\ + + +@ Input: +@ r0 = screen_ptr +@ r1 = start +@ r2 = end + +1: + .word palette_ram_converted + .word 0x3FE + +expand_normal: + stmdb sp!, { r4, r5, r6, r7, r14 } + + add r0, r0, r1, lsl #1 @ screen_ptr += start + sub r1, r2, r1 @ r1 = end - start + ldr r2, 1b @ r2 = palette_ram_converted + ldr r3, 1b + 4 @ r3 = 0x3FE + +2: + ldmia r0, { r4, r5, r6, r7 } + + expand_pixel_pair(r4, r14) + expand_pixel_pair(r5, r14) + expand_pixel_pair(r6, r14) + expand_pixel_pair(r7, r14) + + stmia r0!, { r4, r5, r6, r7 } + + subs r1, r1, #8 + bne 2b + + ldmia sp!, { r4, r5, r6, r7, pc } + diff --git a/gui.c b/gui.c new file mode 100644 index 0000000..6eb9ddb --- /dev/null +++ b/gui.c @@ -0,0 +1,1605 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licens e as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _WIN32_WCE + +#include +#include +#include +#include + +#endif + +#include "common.h" +#include "font.h" + +#define MAX_PATH 1024 + +// Blatantly stolen and trimmed from MZX (megazeux.sourceforge.net) + +#ifdef GP2X_BUILD + +#define FILE_LIST_ROWS ((int)((SDL_SCREEN_HEIGHT - 40) / FONT_HEIGHT)) +#define FILE_LIST_POSITION 5 +#define DIR_LIST_POSITION 260 + +#else + +#define FILE_LIST_ROWS 25 +#define FILE_LIST_POSITION 5 +#define DIR_LIST_POSITION 360 + +#endif + +#ifdef PSP_BUILD + +#define color16(red, green, blue) \ + (blue << 11) | (green << 5) | red \ + +#else + +#define color16(red, green, blue) \ + (red << 11) | (green << 5) | blue \ + +#endif + +#ifdef GP2X_BUILD + +#define COLOR_BG color16(0, 0, 0) + +#else + +#define COLOR_BG color16(2, 8, 10) + +#endif + +#define COLOR_ROM_INFO color16(22, 36, 26) +#define COLOR_ACTIVE_ITEM color16(31, 63, 31) +#define COLOR_INACTIVE_ITEM color16(13, 40, 18) +#define COLOR_FRAMESKIP_BAR color16(15, 31, 31) +#define COLOR_HELP_TEXT color16(16, 40, 24) + +int sort_function(const void *dest_str_ptr, const void *src_str_ptr) +{ + char *dest_str = *((char **)dest_str_ptr); + char *src_str = *((char **)src_str_ptr); + + if(src_str[0] == '.') + return 1; + + if(dest_str[0] == '.') + return -1; + + return strcasecmp(dest_str, src_str); +} + +s32 load_file(u8 **wildcards, u8 *result) +{ + DIR *current_dir; + struct dirent *current_file; + struct stat file_info; + u8 current_dir_name[MAX_PATH]; + u8 current_dir_short[81]; + u32 current_dir_length; + u32 total_filenames_allocated; + u32 total_dirnames_allocated; + u8 **file_list; + u8 **dir_list; + u32 num_files; + u32 num_dirs; + u8 *file_name; + u32 file_name_length; + u32 ext_pos = -1; + u32 chosen_file, chosen_dir; + u32 dialog_result = 1; + s32 return_value = 1; + u32 current_file_selection; + u32 current_file_scroll_value; + u32 current_dir_selection; + u32 current_dir_scroll_value; + u32 current_file_in_scroll; + u32 current_dir_in_scroll; + u32 current_file_number, current_dir_number; + u32 current_column = 0; + u32 repeat; + u32 i; + gui_action_type gui_action; + + while(return_value == 1) + { + current_file_selection = 0; + current_file_scroll_value = 0; + current_dir_selection = 0; + current_dir_scroll_value = 0; + current_file_in_scroll = 0; + current_dir_in_scroll = 0; + + total_filenames_allocated = 32; + total_dirnames_allocated = 32; + file_list = (u8 **)malloc(sizeof(u8 *) * 32); + dir_list = (u8 **)malloc(sizeof(u8 *) * 32); + memset(file_list, 0, sizeof(u8 *) * 32); + memset(dir_list, 0, sizeof(u8 *) * 32); + + num_files = 0; + num_dirs = 0; + chosen_file = 0; + chosen_dir = 0; + + getcwd(current_dir_name, MAX_PATH); + + current_dir = opendir(current_dir_name); + + do + { + if(current_dir) + current_file = readdir(current_dir); + else + current_file = NULL; + + if(current_file) + { + file_name = current_file->d_name; + file_name_length = strlen(file_name); + + if((stat(file_name, &file_info) >= 0) && + ((file_name[0] != '.') || (file_name[1] == '.'))) + { + if(S_ISDIR(file_info.st_mode)) + { + dir_list[num_dirs] = + (u8 *)malloc(file_name_length + 1); + + sprintf(dir_list[num_dirs], "%s", file_name); + + num_dirs++; + } + else + { + // Must match one of the wildcards, also ignore the . + if(file_name_length >= 4) + { + if(file_name[file_name_length - 4] == '.') + ext_pos = file_name_length - 4; + else + + if(file_name[file_name_length - 3] == '.') + ext_pos = file_name_length - 3; + + else + ext_pos = 0; + + for(i = 0; wildcards[i] != NULL; i++) + { + if(!strcasecmp((file_name + ext_pos), + wildcards[i])) + { + file_list[num_files] = + (u8 *)malloc(file_name_length + 1); + + sprintf(file_list[num_files], "%s", file_name); + + num_files++; + break; + } + } + } + } + } + + if(num_files == total_filenames_allocated) + { + file_list = (u8 **)realloc(file_list, sizeof(u8 *) * + total_filenames_allocated * 2); + memset(file_list + total_filenames_allocated, 0, + sizeof(u8 *) * total_filenames_allocated); + total_filenames_allocated *= 2; + } + + if(num_dirs == total_dirnames_allocated) + { + dir_list = (u8 **)realloc(dir_list, sizeof(u8 *) * + total_dirnames_allocated * 2); + memset(dir_list + total_dirnames_allocated, 0, + sizeof(u8 *) * total_dirnames_allocated); + total_dirnames_allocated *= 2; + } + } + } while(current_file); + + qsort((void *)file_list, num_files, sizeof(u8 *), sort_function); + qsort((void *)dir_list, num_dirs, sizeof(u8 *), sort_function); + + closedir(current_dir); + + current_dir_length = strlen(current_dir_name); + + if(current_dir_length > 80) + { + +#ifdef GP2X_BUILD + snprintf(current_dir_short, 80, + "...%s", current_dir_name + current_dir_length - 77); +#else + memcpy(current_dir_short, "...", 3); + memcpy(current_dir_short + 3, + current_dir_name + current_dir_length - 77, 77); + current_dir_short[80] = 0; +#endif + } + else + { +#ifdef GP2X_BUILD + snprintf(current_dir_short, 80, "%s", current_dir_name); +#else + memcpy(current_dir_short, current_dir_name, + current_dir_length + 1); +#endif + } + + repeat = 1; + + if(num_files == 0) + current_column = 1; + + clear_screen(COLOR_BG); + { + u8 print_buffer[81]; + + while(repeat) + { + flip_screen(); + + print_string(current_dir_short, COLOR_ACTIVE_ITEM, COLOR_BG, 0, 0); +#ifdef GP2X_BUILD + print_string("Press X to return to the main menu.", + COLOR_HELP_TEXT, COLOR_BG, 20, 220); +#else + print_string("Press X to return to the main menu.", + COLOR_HELP_TEXT, COLOR_BG, 20, 260); +#endif + + for(i = 0, current_file_number = i + current_file_scroll_value; + i < FILE_LIST_ROWS; i++, current_file_number++) + { + if(current_file_number < num_files) + { + if((current_file_number == current_file_selection) && + (current_column == 0)) + { + print_string(file_list[current_file_number], COLOR_ACTIVE_ITEM, + COLOR_BG, FILE_LIST_POSITION, ((i + 1) * 10)); + } + else + { + print_string(file_list[current_file_number], COLOR_INACTIVE_ITEM, + COLOR_BG, FILE_LIST_POSITION, ((i + 1) * 10)); + } + } + } + + for(i = 0, current_dir_number = i + current_dir_scroll_value; + i < FILE_LIST_ROWS; i++, current_dir_number++) + { + if(current_dir_number < num_dirs) + { + if((current_dir_number == current_dir_selection) && + (current_column == 1)) + { + print_string(dir_list[current_dir_number], COLOR_ACTIVE_ITEM, + COLOR_BG, DIR_LIST_POSITION, ((i + 1) * 10)); + } + else + { + print_string(dir_list[current_dir_number], COLOR_INACTIVE_ITEM, + COLOR_BG, DIR_LIST_POSITION, ((i + 1) * 10)); + } + } + } + + gui_action = get_gui_input(); + + switch(gui_action) + { + case CURSOR_DOWN: + if(current_column == 0) + { + if(current_file_selection < (num_files - 1)) + { + current_file_selection++; + if(current_file_in_scroll == (FILE_LIST_ROWS - 1)) + { + clear_screen(COLOR_BG); + current_file_scroll_value++; + } + else + { + current_file_in_scroll++; + } + } + } + else + { + if(current_dir_selection < (num_dirs - 1)) + { + current_dir_selection++; + if(current_dir_in_scroll == (FILE_LIST_ROWS - 1)) + { + clear_screen(COLOR_BG); + current_dir_scroll_value++; + } + else + { + current_dir_in_scroll++; + } + } + } + + break; + + case CURSOR_UP: + if(current_column == 0) + { + if(current_file_selection) + { + current_file_selection--; + if(current_file_in_scroll == 0) + { + clear_screen(COLOR_BG); + current_file_scroll_value--; + } + else + { + current_file_in_scroll--; + } + } + } + else + { + if(current_dir_selection) + { + current_dir_selection--; + if(current_dir_in_scroll == 0) + { + clear_screen(COLOR_BG); + current_dir_scroll_value--; + } + else + { + current_dir_in_scroll--; + } + } + } + break; + + case CURSOR_RIGHT: + if(current_column == 0) + { + if(num_dirs != 0) + current_column = 1; + } + break; + + case CURSOR_LEFT: + if(current_column == 1) + { + if(num_files != 0) + current_column = 0; + } + break; + + case CURSOR_SELECT: + if(current_column == 1) + { + repeat = 0; + chdir(dir_list[current_dir_selection]); + } + else + { + if(num_files != 0) + { + repeat = 0; + return_value = 0; + strcpy(result, file_list[current_file_selection]); + } + } + break; + + case CURSOR_BACK: +#ifdef PSP_BUILD + if(!strcmp(current_dir_name, "ms0:/PSP")) + break; +#endif + repeat = 0; + chdir(".."); + break; + + case CURSOR_EXIT: + return_value = -1; + repeat = 0; + break; + } + } + } + + for(i = 0; i < num_files; i++) + { + free(file_list[i]); + } + free(file_list); + + for(i = 0; i < num_dirs; i++) + { + free(dir_list[i]); + } + free(dir_list); + } + + clear_screen(COLOR_BG); + + return return_value; +} + +typedef enum +{ + NUMBER_SELECTION_OPTION = 0x01, + STRING_SELECTION_OPTION = 0x02, + SUBMENU_OPTION = 0x04, + ACTION_OPTION = 0x08 +} menu_option_type_enum; + +struct _menu_type +{ + void (* init_function)(); + void (* passive_function)(); + struct _menu_option_type *options; + u32 num_options; +}; + +struct _menu_option_type +{ + void (* action_function)(); + void (* passive_function)(); + struct _menu_type *sub_menu; + char *display_string; + void *options; + u32 *current_option; + u32 num_options; + char *help_string; + u32 line_number; + menu_option_type_enum option_type; +}; + +typedef struct _menu_option_type menu_option_type; +typedef struct _menu_type menu_type; + +#define make_menu(name, init_function, passive_function) \ + menu_type name##_menu = \ + { \ + init_function, \ + passive_function, \ + name##_options, \ + sizeof(name##_options) / sizeof(menu_option_type) \ + } \ + +#define gamepad_config_option(display_string, number) \ +{ \ + NULL, \ + menu_fix_gamepad_help, \ + NULL, \ + display_string ": %s", \ + gamepad_config_buttons, \ + gamepad_config_map + gamepad_config_line_to_button[number], \ + sizeof(gamepad_config_buttons) / sizeof(gamepad_config_buttons[0]), \ + gamepad_help[gamepad_config_map[ \ + gamepad_config_line_to_button[number]]], \ + number, \ + STRING_SELECTION_OPTION \ +} \ + +#define analog_config_option(display_string, number) \ +{ \ + NULL, \ + menu_fix_gamepad_help, \ + NULL, \ + display_string ": %s", \ + gamepad_config_buttons, \ + gamepad_config_map + number + 12, \ + sizeof(gamepad_config_buttons) / sizeof(gamepad_config_buttons[0]), \ + gamepad_help[gamepad_config_map[number + 12]], \ + number + 2, \ + STRING_SELECTION_OPTION \ +} \ + +#define cheat_option(number) \ +{ \ + NULL, \ + NULL, \ + NULL, \ + cheat_format_str[number], \ + enable_disable_options, \ + &(cheats[number].cheat_active), \ + 2, \ + "Activate/deactivate this cheat code.", \ + number, \ + STRING_SELECTION_OPTION \ +} \ + +#define action_option(action_function, passive_function, display_string, \ + help_string, line_number) \ +{ \ + action_function, \ + passive_function, \ + NULL, \ + display_string, \ + NULL, \ + NULL, \ + 0, \ + help_string, \ + line_number, \ + ACTION_OPTION \ +} \ + +#define submenu_option(sub_menu, display_string, help_string, line_number) \ +{ \ + NULL, \ + NULL, \ + sub_menu, \ + display_string, \ + NULL, \ + NULL, \ + sizeof(sub_menu) / sizeof(menu_option_type), \ + help_string, \ + line_number, \ + SUBMENU_OPTION \ +} \ + +#define selection_option(passive_function, display_string, options, \ + option_ptr, num_options, help_string, line_number, type) \ +{ \ + NULL, \ + passive_function, \ + NULL, \ + display_string, \ + options, \ + option_ptr, \ + num_options, \ + help_string, \ + line_number, \ + type \ +} \ + +#define action_selection_option(action_function, passive_function, \ + display_string, options, option_ptr, num_options, help_string, line_number, \ + type) \ +{ \ + action_function, \ + passive_function, \ + NULL, \ + display_string, \ + options, \ + option_ptr, \ + num_options, \ + help_string, \ + line_number, \ + type | ACTION_OPTION \ +} \ + + +#define string_selection_option(passive_function, display_string, options, \ + option_ptr, num_options, help_string, line_number) \ + selection_option(passive_function, display_string ": %s", options, \ + option_ptr, num_options, help_string, line_number, STRING_SELECTION_OPTION)\ + +#define numeric_selection_option(passive_function, display_string, \ + option_ptr, num_options, help_string, line_number) \ + selection_option(passive_function, display_string ": %d", NULL, option_ptr, \ + num_options, help_string, line_number, NUMBER_SELECTION_OPTION) \ + +#define string_selection_action_option(action_function, passive_function, \ + display_string, options, option_ptr, num_options, help_string, line_number) \ + action_selection_option(action_function, passive_function, \ + display_string ": %s", options, option_ptr, num_options, help_string, \ + line_number, STRING_SELECTION_OPTION) \ + +#define numeric_selection_action_option(action_function, passive_function, \ + display_string, option_ptr, num_options, help_string, line_number) \ + action_selection_option(action_function, passive_function, \ + display_string ": %d", NULL, option_ptr, num_options, help_string, \ + line_number, NUMBER_SELECTION_OPTION) \ + +#define numeric_selection_action_hide_option(action_function, \ + passive_function, display_string, option_ptr, num_options, help_string, \ + line_number) \ + action_selection_option(action_function, passive_function, \ + display_string, NULL, option_ptr, num_options, help_string, \ + line_number, NUMBER_SELECTION_OPTION) \ + + +#define GAMEPAD_MENU_WIDTH 15 + +#ifdef PSP_BUILD + +u32 gamepad_config_line_to_button[] = + { 8, 6, 7, 9, 1, 2, 3, 0, 4, 5, 11, 10 }; + +#endif + +#ifdef GP2X_BUILD + +u32 gamepad_config_line_to_button[] = + { 0, 2, 1, 3, 8, 9, 10, 11, 6, 7, 4, 5 }; + +#endif + + +s32 load_game_config_file() +{ + u8 game_config_filename[512]; + u32 file_loaded = 0; + u32 i; + change_ext(gamepak_filename, game_config_filename, ".cfg"); + + file_open(game_config_file, game_config_filename, read); + + if(file_check_valid(game_config_file)) + { + u32 file_size = file_length(game_config_filename, game_config_file); + + // Sanity check: File size must be the right size + if(file_size == 56) + { + u32 file_options[file_size / 4]; + + file_read_array(game_config_file, file_options); + current_frameskip_type = file_options[0] % 3; + frameskip_value = file_options[1]; + random_skip = file_options[2] % 2; + clock_speed = file_options[3]; + + if(clock_speed > 333) + clock_speed = 333; + + if(clock_speed < 33) + clock_speed = 33; + + if(frameskip_value < 0) + frameskip_value = 0; + + if(frameskip_value > 99) + frameskip_value = 99; + + for(i = 0; i < 10; i++) + { + cheats[i].cheat_active = file_options[3 + i] % 2; + cheats[i].cheat_name[0] = 0; + } + + file_close(game_config_file); + file_loaded = 1; + } + } + + if(file_loaded) + return 0; + + current_frameskip_type = auto_frameskip; + frameskip_value = 4; + random_skip = 0; + clock_speed = 333; + + for(i = 0; i < 10; i++) + { + cheats[i].cheat_active = 0; + cheats[i].cheat_name[0] = 0; + } + + return -1; +} + +s32 load_config_file() +{ + u8 config_path[512]; + + #if (defined(PSP_BUILD) || defined(ARM_ARCH)) && !defined(_WIN32_WCE) + sprintf(config_path, "%s/%s", main_path, GPSP_CONFIG_FILENAME); + #else + sprintf(config_path, "%s\\%s", main_path, GPSP_CONFIG_FILENAME); + #endif + + file_open(config_file, config_path, read); + + if(file_check_valid(config_file)) + { + u32 file_size = file_length(config_path, config_file); + + // Sanity check: File size must be the right size + if(file_size == 92) + { + u32 file_options[file_size / 4]; + u32 i; + s32 menu_button = -1; + file_read_array(config_file, file_options); + + screen_scale = file_options[0] % 3; + screen_filter = file_options[1] % 2; + global_enable_audio = file_options[2] % 2; + +#ifdef PSP_BUILD + audio_buffer_size_number = file_options[3] % 10; +#else + audio_buffer_size_number = file_options[3] % 11; +#endif + + update_backup_flag = file_options[4] % 2; + global_enable_analog = file_options[5] % 2; + analog_sensitivity_level = file_options[6] % 8; + +#ifdef PSP_BUILD + scePowerSetClockFrequency(clock_speed, clock_speed, clock_speed / 2); +#endif + + // Sanity check: Make sure there's a MENU or FRAMESKIP + // key, if not assign to triangle + +#ifndef PC_BUILD + for(i = 0; i < 16; i++) + { + gamepad_config_map[i] = file_options[7 + i] % + (BUTTON_ID_NONE + 1); + + if(gamepad_config_map[i] == BUTTON_ID_MENU) + { + menu_button = i; + } + } + + if(menu_button == -1) + { + gamepad_config_map[0] = BUTTON_ID_MENU; + } +#endif + + file_close(config_file); + } + + return 0; + } + + return -1; +} + +s32 save_game_config_file() +{ + u8 game_config_filename[512]; + u32 i; + + change_ext(gamepak_filename, game_config_filename, ".cfg"); + + file_open(game_config_file, game_config_filename, write); + + if(file_check_valid(game_config_file)) + { + u32 file_options[14]; + + file_options[0] = current_frameskip_type; + file_options[1] = frameskip_value; + file_options[2] = random_skip; + file_options[3] = clock_speed; + + for(i = 0; i < 10; i++) + { + file_options[4 + i] = cheats[i].cheat_active; + } + + file_write_array(game_config_file, file_options); + + file_close(game_config_file); + + return 0; + } + + return -1; +} + +s32 save_config_file() +{ + u8 config_path[512]; + + #if (defined(PSP_BUILD) || defined(ARM_ARCH)) && !defined(_WIN32_WCE) + sprintf(config_path, "%s/%s", main_path, GPSP_CONFIG_FILENAME); + #else + sprintf(config_path, "%s\\%s", main_path, GPSP_CONFIG_FILENAME); + #endif + + file_open(config_file, config_path, write); + + save_game_config_file(); + + if(file_check_valid(config_file)) + { + u32 file_options[23]; + u32 i; + + file_options[0] = screen_scale; + file_options[1] = screen_filter; + file_options[2] = global_enable_audio; + file_options[3] = audio_buffer_size_number; + file_options[4] = update_backup_flag; + file_options[5] = global_enable_analog; + file_options[6] = analog_sensitivity_level; + +#ifndef PC_BUILD + for(i = 0; i < 16; i++) + { + file_options[7 + i] = gamepad_config_map[i]; + } +#endif + + file_write_array(config_file, file_options); + + file_close(config_file); + + return 0; + } + + return -1; +} + +typedef enum +{ + MAIN_MENU, + GAMEPAD_MENU, + SAVESTATE_MENU, + FRAMESKIP_MENU, + CHEAT_MENU +} menu_enum; + +u32 savestate_slot = 0; + +void get_savestate_snapshot(u8 *savestate_filename) +{ + u16 snapshot_buffer[240 * 160]; + u8 savestate_timestamp_string[80]; + + file_open(savestate_file, savestate_filename, read); + + if(file_check_valid(savestate_file)) + { + u8 weekday_strings[7][11] = + { + "Sunday", "Monday", "Tuesday", "Wednesday", + "Thursday", "Friday", "Saturday" + }; + time_t savestate_time_flat; + struct tm *current_time; + file_read_array(savestate_file, snapshot_buffer); + file_read_variable(savestate_file, savestate_time_flat); + + file_close(savestate_file); + + current_time = localtime(&savestate_time_flat); + sprintf(savestate_timestamp_string, + "%s %02d/%02d/%04d %02d:%02d:%02d ", + weekday_strings[current_time->tm_wday], current_time->tm_mon + 1, + current_time->tm_mday, current_time->tm_year + 1900, + current_time->tm_hour, current_time->tm_min, current_time->tm_sec); + + savestate_timestamp_string[40] = 0; + print_string(savestate_timestamp_string, COLOR_HELP_TEXT, COLOR_BG, + 10, 40); + } + else + { + memset(snapshot_buffer, 0, 240 * 160 * 2); + print_string_ext("No savestate exists for this slot.", + 0xFFFF, 0x0000, 15, 75, snapshot_buffer, 240, 0); + print_string("---------- --/--/---- --:--:-- ", COLOR_HELP_TEXT, + COLOR_BG, 10, 40); + } + +#ifndef GP2X_BUILD + blit_to_screen(snapshot_buffer, 240, 160, 230, 40); +#endif +} + +void get_savestate_filename(u32 slot, u8 *name_buffer) +{ + u8 savestate_ext[16]; + + sprintf(savestate_ext, "%d.svs", slot); + change_ext(gamepak_filename, name_buffer, savestate_ext); + + get_savestate_snapshot(name_buffer); +} + +void get_savestate_filename_noshot(u32 slot, u8 *name_buffer) +{ + u8 savestate_ext[16]; + + sprintf(savestate_ext, "%d.svs", slot); + change_ext(gamepak_filename, name_buffer, savestate_ext); +} + +#ifdef PSP_BUILD + void _flush_cache() + { + invalidate_all_cache(); + } +#endif + +u32 menu(u16 *original_screen) +{ + u32 clock_speed_number = (clock_speed / 33) - 1; + u8 print_buffer[81]; + u32 _current_option = 0; + gui_action_type gui_action; + menu_enum _current_menu = MAIN_MENU; + u32 i; + u32 repeat = 1; + u32 return_value = 0; + u32 first_load = 0; + u8 savestate_ext[16]; + u8 current_savestate_filename[512]; + u8 line_buffer[80]; + u8 cheat_format_str[10][41]; + + menu_type *current_menu; + menu_option_type *current_option; + menu_option_type *display_option; + u32 current_option_num; + + auto void choose_menu(); + auto void clear_help(); + + u8 *gamepad_help[] = + { + "Up button on GBA d-pad.", + "Down button on GBA d-pad.", + "Left button on GBA d-pad.", + "Right button on GBA d-pad.", + "A button on GBA.", + "B button on GBA.", + "Left shoulder button on GBA.", + "Right shoulder button on GBA.", + "Start button on GBA.", + "Select button on GBA.", + "Brings up the options menu.", + "Toggles fastforward on/off.", + "Loads the game state from the current slot.", + "Saves the game state to the current slot.", + "Rapidly press/release the A button on GBA.", + "Rapidly press/release the B button on GBA.", + "Rapidly press/release the L shoulder on GBA.", + "Rapidly press/release the R shoulder on GBA.", + "Increases the volume.", + "Decreases the volume.", + "Displays virtual/drawn frames per second.", + "Does nothing." + }; + + void menu_exit() + { + if(!first_load) + repeat = 0; + } + + void menu_quit() + { + clock_speed = (clock_speed_number + 1) * 33; + save_config_file(); + quit(); + } + + void menu_load() + { + u8 *file_ext[] = { ".gba", ".bin", ".zip", NULL }; + u8 load_filename[512]; + save_game_config_file(); + if(load_file(file_ext, load_filename) != -1) + { + if(load_gamepak(load_filename) == -1) + { + quit(); + } + reset_gba(); + return_value = 1; + repeat = 0; + reg[CHANGED_PC_STATUS] = 1; + } + else + { + choose_menu(current_menu); + } + } + + void menu_restart() + { + if(!first_load) + { + reset_gba(); + reg[CHANGED_PC_STATUS] = 1; + return_value = 1; + repeat = 0; + } + } + + void menu_change_state() + { + get_savestate_filename(savestate_slot, current_savestate_filename); + } + + void menu_save_state() + { + if(!first_load) + { + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + save_state(current_savestate_filename, original_screen); + } + menu_change_state(); + } + + void menu_load_state() + { + if(!first_load) + { + load_state(current_savestate_filename); + return_value = 1; + repeat = 0; + } + } + + void menu_load_state_file() + { + u8 *file_ext[] = { ".svs", NULL }; + u8 load_filename[512]; + if(load_file(file_ext, load_filename) != -1) + { + load_state(load_filename); + return_value = 1; + repeat = 0; + } + else + { + choose_menu(current_menu); + } + } + + void menu_fix_gamepad_help() + { +#ifndef PC_BUILD + clear_help(); + current_option->help_string = + gamepad_help[gamepad_config_map[ + gamepad_config_line_to_button[current_option_num]]]; +#endif + } + + void submenu_graphics_sound() + { + + } + + void submenu_cheats_misc() + { + + } + + void submenu_gamepad() + { + + } + + void submenu_analog() + { + + } + + void submenu_savestate() + { + print_string("Savestate options:", COLOR_ACTIVE_ITEM, COLOR_BG, 10, 70); + menu_change_state(); + } + + void submenu_main() + { + strncpy(print_buffer, gamepak_filename, 80); + print_string(print_buffer, COLOR_ROM_INFO, COLOR_BG, 10, 10); + sprintf(print_buffer, "%s %s %s", gamepak_title, + gamepak_code, gamepak_maker); + print_string(print_buffer, COLOR_ROM_INFO, COLOR_BG, 10, 20); + + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + } + + u8 *yes_no_options[] = { "no", "yes" }; + u8 *enable_disable_options[] = { "disabled", "enabled" }; + + u8 *scale_options[] = + { + "unscaled 3:2", "scaled 3:2", "fullscreen 16:9" + }; + + u8 *frameskip_options[] = { "automatic", "manual", "off" }; + u8 *frameskip_variation_options[] = { "uniform", "random" }; + +#ifndef PSP_BUILD + u8 *audio_buffer_options[] = + { + "16 bytes", "32 bytes", "64 bytes", + "128 bytes", "256 bytes", "512 bytes", "1024 bytes", "2048 bytes", + "4096 bytes", "8192 bytes", "16284 bytes" + }; +#else + u8 *audio_buffer_options[] = + { + "3072 bytes", "4096 bytes", "5120 bytes", "6144 bytes", "7168 bytes", + "8192 bytes", "9216 bytes", "10240 bytes", "11264 bytes", "12288 bytes" + }; + +#endif + + u8 *update_backup_options[] = { "Exit only", "Automatic" }; + + u8 *clock_speed_options[] = + { + "33MHz", "66MHz", "100MHz", "133MHz", "166MHz", "200MHz", "233MHz", + "266MHz", "300MHz", "333MHz" + }; + + u8 *gamepad_config_buttons[] = + { + "UP", + "DOWN", + "LEFT", + "RIGHT", + "A", + "B", + "L", + "R", + "START", + "SELECT", + "MENU", + "FASTFORWARD", + "LOAD STATE", + "SAVE STATE", + "RAPIDFIRE A", + "RAPIDFIRE B", + "RAPIDFIRE L", + "RAPIDFIRE R", + "VOLUME UP", + "VOLUME DOWN", + "DISPLAY FPS", + "NOTHING" + }; + + // Marker for help information, don't go past this mark (except \n)------* + menu_option_type graphics_sound_options[] = + { + string_selection_option(NULL, "Display scaling", scale_options, + (u32 *)(&screen_scale), 3, + "Determines how the GBA screen is resized in relation to the entire\n" + "screen. Select unscaled 3:2 for GBA resolution, scaled 3:2 for GBA\n" + "aspect ratio scaled to fill the height of the PSP screen, and\n" + "fullscreen to fill the entire PSP screen.", 2), + string_selection_option(NULL, "Screen filtering", yes_no_options, + (u32 *)(&screen_filter), 2, + "Determines whether or not bilinear filtering should be used when\n" + "scaling the screen. Selecting this will produce a more even and\n" + "smooth image, at the cost of being blurry and having less vibrant\n" + "colors.", 3), + string_selection_option(NULL, "Frameskip type", frameskip_options, + (u32 *)(¤t_frameskip_type), 3, + "Determines what kind of frameskipping should be employed.\n" + "Frameskipping may improve emulation speed of many games.\n" + "Off: Do not skip any frames.\n" + "Auto: Skip up to N frames (see next option) as needed.\n" + "Manual: Always render only 1 out of N + 1 frames.", 5), + numeric_selection_option(NULL, "Frameskip value", &frameskip_value, 100, + "For auto frameskip, determines the maximum number of frames that\n" + "are allowed to be skipped consecutively.\n" + "For manual frameskip, determines the number of frames that will\n" + "always be skipped.", 6), + string_selection_option(NULL, "Framskip variation", + frameskip_variation_options, &random_skip, 2, + "If objects in the game flicker at a regular rate certain manual\n" + "frameskip values may cause them to normally disappear. Change this\n" + "value to 'random' to avoid this. Do not use otherwise, as it tends to\n" + "make the image quality worse, especially in high motion games.", 7), + string_selection_option(NULL, "Audio output", yes_no_options, + &global_enable_audio, 2, + "Select 'no' to turn off all audio output. This will not result in a\n" + "significant change in performance.", 9), +#ifndef PSP_BUILD + string_selection_option(NULL, "Audio buffer", audio_buffer_options, + &audio_buffer_size_number, 11, +#else + string_selection_option(NULL, "Audio buffer", audio_buffer_options, + &audio_buffer_size_number, 10, +#endif + + "Set the size (in bytes) of the audio buffer. Larger values may result\n" + "in slightly better performance at the cost of latency; the lowest\n" + "value will give the most responsive audio.\n" + "This option requires gpSP to be restarted before it will take effect.", + 10), + submenu_option(NULL, "Back", "Return to the main menu.", 12) + }; + + make_menu(graphics_sound, submenu_graphics_sound, NULL); + + menu_option_type cheats_misc_options[] = + { + cheat_option(0), + cheat_option(1), + cheat_option(2), + cheat_option(3), + cheat_option(4), + cheat_option(5), + cheat_option(6), + cheat_option(7), + cheat_option(8), + cheat_option(9), + string_selection_option(NULL, "Clock speed", + clock_speed_options, &clock_speed_number, 10, + "Change the clock speed of the device. Higher clock speed will yield\n" + "better performance, but will use drain battery life further.", 11), + string_selection_option(NULL, "Update backup", + update_backup_options, &update_backup_flag, 2, + "Determines when in-game save files should be written back to\n" + "memstick. If set to 'automatic' writebacks will occur shortly after\n" + "the game's backup is altered. On 'exit only' it will only be written\n" + "back when you exit from this menu (NOT from using the home button).\n" + "Use the latter with extreme care.", 12), + submenu_option(NULL, "Back", "Return to the main menu.", 14) + }; + + make_menu(cheats_misc, submenu_cheats_misc, NULL); + + menu_option_type savestate_options[] = + { + numeric_selection_action_hide_option(menu_load_state, menu_change_state, + "Load savestate from current slot", &savestate_slot, 10, + "Select to load the game state from the current slot for this game.\n" + "Press left + right to change the current slot.", 6), + numeric_selection_action_hide_option(menu_save_state, menu_change_state, + "Save savestate to current slot", &savestate_slot, 10, + "Select to save the game state to the current slot for this game.\n" + "Press left + right to change the current slot.", 7), + numeric_selection_action_hide_option(menu_load_state_file, + menu_change_state, + "Load savestate from file", &savestate_slot, 10, + "Restore gameplay from a savestate file.\n" + "Note: The same file used to save the state must be present.\n", 9), + numeric_selection_option(menu_change_state, + "Current savestate slot", &savestate_slot, 10, + "Change the current savestate slot.\n", 11), + submenu_option(NULL, "Back", "Return to the main menu.", 13) + }; + + make_menu(savestate, submenu_savestate, NULL); + +#ifdef PSP_BUILD + + menu_option_type gamepad_config_options[] = + { + gamepad_config_option("D-pad up ", 0), + gamepad_config_option("D-pad down ", 1), + gamepad_config_option("D-pad left ", 2), + gamepad_config_option("D-pad right ", 3), + gamepad_config_option("Circle ", 4), + gamepad_config_option("Cross ", 5), + gamepad_config_option("Square ", 6), + gamepad_config_option("Triangle ", 7), + gamepad_config_option("Left Trigger ", 8), + gamepad_config_option("Right Trigger", 9), + gamepad_config_option("Start ", 10), + gamepad_config_option("Select ", 11), + submenu_option(NULL, "Back", "Return to the main menu.", 13) + }; + + + menu_option_type analog_config_options[] = + { + analog_config_option("Analog up ", 0), + analog_config_option("Analog down ", 1), + analog_config_option("Analog left ", 2), + analog_config_option("Analog right", 3), + string_selection_option(NULL, "Enable analog", yes_no_options, + &global_enable_analog, 2, + "Select 'no' to block analog input entirely.", 7), + numeric_selection_option(NULL, "Analog sensitivity", + &analog_sensitivity_level, 10, + "Determine sensitivity/responsiveness of the analog input.\n" + "Lower numbers are less sensitive.", 8), + submenu_option(NULL, "Back", "Return to the main menu.", 11) + }; + +#endif + +#ifdef GP2X_BUILD + + menu_option_type gamepad_config_options[] = + { + gamepad_config_option("D-pad up ", 0), + gamepad_config_option("D-pad down ", 1), + gamepad_config_option("D-pad left ", 2), + gamepad_config_option("D-pad right ", 3), + gamepad_config_option("A ", 4), + gamepad_config_option("B ", 5), + gamepad_config_option("X ", 6), + gamepad_config_option("Y ", 7), + gamepad_config_option("Left Trigger ", 8), + gamepad_config_option("Right Trigger", 9), + gamepad_config_option("Start ", 10), + gamepad_config_option("Select ", 11), + submenu_option(NULL, "Back", "Return to the main menu.", 13) + }; + + + menu_option_type analog_config_options[] = + { + submenu_option(NULL, "Back", "Return to the main menu.", 11) + }; + +#endif + +#ifdef PC_BUILD + + menu_option_type gamepad_config_options[] = + { + submenu_option(NULL, "Back", "Return to the main menu.", 13) + }; + + menu_option_type analog_config_options[] = + { + submenu_option(NULL, "Back", "Return to the main menu.", 11) + }; + +#endif + + make_menu(gamepad_config, submenu_gamepad, NULL); + make_menu(analog_config, submenu_analog, NULL); + + menu_option_type main_options[] = + { + submenu_option(&graphics_sound_menu, "Graphics and Sound options", + "Select to set display parameters and frameskip behavior,\n" + "audio on/off, audio buffer size, and audio filtering.", 0), + numeric_selection_action_option(menu_load_state, NULL, + "Load state from slot", &savestate_slot, 10, + "Select to load the game state from the current slot for this game,\n" + "if it exists (see the extended menu for more information)\n" + "Press left + right to change the current slot.", 2), + numeric_selection_action_option(menu_save_state, NULL, + "Save state to slot", &savestate_slot, 10, + "Select to save the game state to the current slot for this game.\n" + "See the extended menu for more information.\n" + "Press left + right to change the current slot.", 3), + submenu_option(&savestate_menu, "Savestate options", + "Select to enter a menu for loading, saving, and viewing the\n" + "currently active savestate for this game (or to load a savestate\n" + "file from another game)", 4), + submenu_option(&gamepad_config_menu, "Configure gamepad input", + "Select to change the in-game behavior of the PSP buttons and d-pad.", + 6), + submenu_option(&analog_config_menu, "Configure analog input", + "Select to change the in-game behavior of the PSP analog nub.", 7), + submenu_option(&cheats_misc_menu, "Cheats and Miscellaneous options", + "Select to manage cheats, set backup behavior, and set device clock\n" + "speed.", 9), + action_option(menu_load, NULL, "Load new game", + "Select to load a new game (will exit a game if currently playing).", + 11), + action_option(menu_restart, NULL, "Restart game", + "Select to reset the GBA with the current game loaded.", 12), + action_option(menu_exit, NULL, "Return to game", + "Select to exit this menu and resume gameplay.", 13), + action_option(menu_quit, NULL, "Exit gpSP", + "Select to exit gpSP and return to the PSP XMB/loader.", 15) + }; + + make_menu(main, submenu_main, NULL); + + void choose_menu(menu_type *new_menu) + { + if(new_menu == NULL) + new_menu = &main_menu; + + clear_screen(COLOR_BG); + +#ifndef GP2X_BUILD + blit_to_screen(original_screen, 240, 160, 230, 40); +#endif + + current_menu = new_menu; + current_option = new_menu->options; + current_option_num = 0; + if(current_menu->init_function) + current_menu->init_function(); + } + + void clear_help() + { + for(i = 0; i < 6; i++) + { + print_string_pad(" ", COLOR_BG, COLOR_BG, 30, 210 + (i * 10), 70); + } + } + + video_resolution_large(); + +#ifndef GP2X_BUILD + SDL_LockMutex(sound_mutex); +#endif + SDL_PauseAudio(1); + +#ifndef GP2X_BUILD + SDL_UnlockMutex(sound_mutex); +#endif + + if(gamepak_filename[0] == 0) + { + first_load = 1; + memset(original_screen, 0x00, 240 * 160 * 2); + print_string_ext("No game loaded yet.", 0xFFFF, 0x0000, + 60, 75,original_screen, 240, 0); + } + + choose_menu(&main_menu); + + for(i = 0; i < 10; i++) + { + if(i >= num_cheats) + { + sprintf(cheat_format_str[i], "cheat %d (none loaded)", i); + } + else + { + sprintf(cheat_format_str[i], "cheat %d (%s): %%s", i, + cheats[i].cheat_name); + } + } + + current_menu->init_function(); + + while(repeat) + { + display_option = current_menu->options; + + for(i = 0; i < current_menu->num_options; i++, display_option++) + { + if(display_option->option_type & NUMBER_SELECTION_OPTION) + { + sprintf(line_buffer, display_option->display_string, + *(display_option->current_option)); + } + else + + if(display_option->option_type & STRING_SELECTION_OPTION) + { + sprintf(line_buffer, display_option->display_string, + ((u32 *)display_option->options)[*(display_option->current_option)]); + } + else + { + strcpy(line_buffer, display_option->display_string); + } + + if(display_option == current_option) + { + print_string_pad(line_buffer, COLOR_ACTIVE_ITEM, COLOR_BG, 10, + (display_option->line_number * 10) + 40, 36); + } + else + { + print_string_pad(line_buffer, COLOR_INACTIVE_ITEM, COLOR_BG, 10, + (display_option->line_number * 10) + 40, 36); + } + } + + print_string(current_option->help_string, COLOR_HELP_TEXT, + COLOR_BG, 30, 210); + + flip_screen(); + + gui_action = get_gui_input(); + + switch(gui_action) + { + case CURSOR_DOWN: + current_option_num = (current_option_num + 1) % + current_menu->num_options; + + current_option = current_menu->options + current_option_num; + clear_help(); + break; + + case CURSOR_UP: + if(current_option_num) + current_option_num--; + else + current_option_num = current_menu->num_options - 1; + + current_option = current_menu->options + current_option_num; + clear_help(); + break; + + case CURSOR_RIGHT: + if(current_option->option_type & (NUMBER_SELECTION_OPTION | + STRING_SELECTION_OPTION)) + { + *(current_option->current_option) = + (*current_option->current_option + 1) % + current_option->num_options; + + if(current_option->passive_function) + current_option->passive_function(); + } + break; + + case CURSOR_LEFT: + if(current_option->option_type & (NUMBER_SELECTION_OPTION | + STRING_SELECTION_OPTION)) + { + u32 current_option_val = *(current_option->current_option); + + if(current_option_val) + current_option_val--; + else + current_option_val = current_option->num_options - 1; + + *(current_option->current_option) = current_option_val; + + if(current_option->passive_function) + current_option->passive_function(); + } + break; + + case CURSOR_EXIT: + if(current_menu == &main_menu) + menu_exit(); + + choose_menu(&main_menu); + break; + + case CURSOR_SELECT: + if(current_option->option_type & ACTION_OPTION) + current_option->action_function(); + + if(current_option->option_type & SUBMENU_OPTION) + choose_menu(current_option->sub_menu); + break; + } + } + + set_gba_resolution(screen_scale); + video_resolution_small(); + + clock_speed = (clock_speed_number + 1) * 33; + + #ifdef PSP_BUILD + scePowerSetClockFrequency(clock_speed, clock_speed, clock_speed / 2); + #endif + + SDL_PauseAudio(0); + + return return_value; +} diff --git a/gui.h b/gui.h new file mode 100644 index 0000000..6019d22 --- /dev/null +++ b/gui.h @@ -0,0 +1,40 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GUI_H +#define GUI_H + +#define GPSP_CONFIG_FILENAME "gpsp.cfg" + +s32 load_file(u8 **wildcards, u8 *result); +u32 adjust_frameskip(u32 button_id); +s32 load_game_config_file(); +s32 load_config_file(); +s32 save_game_config_file(); +s32 save_config_file(); +u32 menu(u16 *original_screen); + +extern u32 savestate_slot; + +void get_savestate_filename_noshot(u32 slot, u8 *name_buffer); +void get_savestate_filename(u32 slot, u8 *name_buffer); +void get_savestate_snapshot(u8 *savestate_filename); + +#endif + diff --git a/input.c b/input.c new file mode 100644 index 0000000..be00c60 --- /dev/null +++ b/input.c @@ -0,0 +1,899 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "common.h" + +// Special thanks to psp298 for the analog->dpad code! + +void trigger_key(u32 key) +{ + u32 p1_cnt = io_registers[REG_P1CNT]; + u32 p1; + + if((p1_cnt >> 14) & 0x01) + { + u32 key_intersection = (p1_cnt & key) & 0x3FF; + + if(p1_cnt >> 15) + { + if(key_intersection == (p1_cnt & 0x3FF)) + raise_interrupt(IRQ_KEYPAD); + } + else + { + if(key_intersection) + raise_interrupt(IRQ_KEYPAD); + } + } +} + +u32 key = 0; + +u32 global_enable_analog = 1; +u32 analog_sensitivity_level = 4; + +typedef enum +{ + BUTTON_NOT_HELD, + BUTTON_HELD_INITIAL, + BUTTON_HELD_REPEAT +} button_repeat_state_type; + + +// These define autorepeat values (in microseconds), tweak as necessary. + +#define BUTTON_REPEAT_START 200000 +#define BUTTON_REPEAT_CONTINUE 50000 + +button_repeat_state_type button_repeat_state = BUTTON_NOT_HELD; +u32 button_repeat = 0; +gui_action_type cursor_repeat = CURSOR_NONE; + + +#ifdef PSP_BUILD + +u32 gamepad_config_map[16] = +{ + BUTTON_ID_MENU, // Triangle + BUTTON_ID_A, // Circle + BUTTON_ID_B, // Cross + BUTTON_ID_START, // Square + BUTTON_ID_L, // Ltrigger + BUTTON_ID_R, // Rtrigger + BUTTON_ID_DOWN, // Down + BUTTON_ID_LEFT, // Left + BUTTON_ID_UP, // Up + BUTTON_ID_RIGHT, // Right + BUTTON_ID_SELECT, // Select + BUTTON_ID_START, // Start + BUTTON_ID_UP, // Analog up + BUTTON_ID_DOWN, // Analog down + BUTTON_ID_LEFT, // Analog left + BUTTON_ID_RIGHT // Analog right +}; + +#define PSP_ALL_BUTTON_MASK 0xFFFF + +gui_action_type get_gui_input() +{ + SceCtrlData ctrl_data; + gui_action_type new_button = CURSOR_NONE; + u32 new_buttons; + + static u32 last_buttons = 0; + static u64 button_repeat_timestamp; + + delay_us(25000); + + sceCtrlPeekBufferPositive(&ctrl_data, 1); + ctrl_data.Buttons &= PSP_ALL_BUTTON_MASK; + new_buttons = (last_buttons ^ ctrl_data.Buttons) & ctrl_data.Buttons; + last_buttons = ctrl_data.Buttons; + + if(new_buttons & PSP_CTRL_LEFT) + new_button = CURSOR_LEFT; + + if(new_buttons & PSP_CTRL_RIGHT) + new_button = CURSOR_RIGHT; + + if(new_buttons & PSP_CTRL_UP) + new_button = CURSOR_UP; + + if(new_buttons & PSP_CTRL_DOWN) + new_button = CURSOR_DOWN; + + if(new_buttons & PSP_CTRL_START) + new_button = CURSOR_SELECT; + + if(new_buttons & PSP_CTRL_CIRCLE) + new_button = CURSOR_SELECT; + + if(new_buttons & PSP_CTRL_CROSS) + new_button = CURSOR_EXIT; + + if(new_buttons & PSP_CTRL_SQUARE) + new_button = CURSOR_BACK; + + if(new_button != CURSOR_NONE) + { + get_ticks_us(&button_repeat_timestamp); + button_repeat_state = BUTTON_HELD_INITIAL; + button_repeat = new_buttons; + cursor_repeat = new_button; + } + else + { + if(ctrl_data.Buttons & button_repeat) + { + u64 new_ticks; + get_ticks_us(&new_ticks); + + if(button_repeat_state == BUTTON_HELD_INITIAL) + { + if((new_ticks - button_repeat_timestamp) > + BUTTON_REPEAT_START) + { + new_button = cursor_repeat; + button_repeat_timestamp = new_ticks; + button_repeat_state = BUTTON_HELD_REPEAT; + } + } + + if(button_repeat_state == BUTTON_HELD_REPEAT) + { + if((new_ticks - button_repeat_timestamp) > + BUTTON_REPEAT_CONTINUE) + { + new_button = cursor_repeat; + button_repeat_timestamp = new_ticks; + } + } + } + } + + return new_button; +} + +#define PSP_CTRL_ANALOG_UP (1 << 28) +#define PSP_CTRL_ANALOG_DOWN (1 << 29) +#define PSP_CTRL_ANALOG_LEFT (1 << 30) +#define PSP_CTRL_ANALOG_RIGHT (1 << 31) + +u32 button_psp_mask_to_config[] = +{ + PSP_CTRL_TRIANGLE, + PSP_CTRL_CIRCLE, + PSP_CTRL_CROSS, + PSP_CTRL_SQUARE, + PSP_CTRL_LTRIGGER, + PSP_CTRL_RTRIGGER, + PSP_CTRL_DOWN, + PSP_CTRL_LEFT, + PSP_CTRL_UP, + PSP_CTRL_RIGHT, + PSP_CTRL_SELECT, + PSP_CTRL_START, + PSP_CTRL_ANALOG_UP, + PSP_CTRL_ANALOG_DOWN, + PSP_CTRL_ANALOG_LEFT, + PSP_CTRL_ANALOG_RIGHT +}; + +u32 button_id_to_gba_mask[] = +{ + BUTTON_UP, + BUTTON_DOWN, + BUTTON_LEFT, + BUTTON_RIGHT, + BUTTON_A, + BUTTON_B, + BUTTON_L, + BUTTON_R, + BUTTON_START, + BUTTON_SELECT, + BUTTON_NONE, + BUTTON_NONE, + BUTTON_NONE, + BUTTON_NONE +}; + +gui_action_type get_gui_input_fs_hold(u32 button_id) +{ + gui_action_type new_button = get_gui_input(); + if((last_buttons & button_psp_mask_to_config[button_id]) == 0) + return CURSOR_BACK; + + return new_button; +} + +u32 rapidfire_flag = 1; + +u32 update_input() +{ + SceCtrlData ctrl_data; + u32 buttons; + u32 non_repeat_buttons; + u32 button_id; + u32 i; + u32 new_key = 0; + u32 analog_sensitivity = 92 - (analog_sensitivity_level * 4); + u32 inv_analog_sensitivity = 256 - analog_sensitivity; + + sceCtrlPeekBufferPositive(&ctrl_data, 1); + + buttons = ctrl_data.Buttons; + + if(global_enable_analog) + { + if(ctrl_data.Lx < analog_sensitivity) + buttons |= PSP_CTRL_ANALOG_LEFT; + + if(ctrl_data.Lx > inv_analog_sensitivity) + buttons |= PSP_CTRL_ANALOG_RIGHT; + + if(ctrl_data.Ly < analog_sensitivity) + buttons |= PSP_CTRL_ANALOG_UP; + + if(ctrl_data.Ly > inv_analog_sensitivity) + buttons |= PSP_CTRL_ANALOG_DOWN; + } + + non_repeat_buttons = (last_buttons ^ buttons) & buttons; + last_buttons = buttons; + + for(i = 0; i < 16; i++) + { + if(non_repeat_buttons & button_psp_mask_to_config[i]) + button_id = gamepad_config_map[i]; + else + button_id = BUTTON_ID_NONE; + + switch(button_id) + { + case BUTTON_ID_MENU: + { + u16 *screen_copy = copy_screen(); + u32 ret_val = menu(screen_copy); + free(screen_copy); + + return ret_val; + } + + case BUTTON_ID_LOADSTATE: + { + u8 current_savestate_filename[512]; + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + load_state(current_savestate_filename); + return 1; + } + + case BUTTON_ID_SAVESTATE: + { + u8 current_savestate_filename[512]; + u16 *current_screen = copy_screen(); + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + save_state(current_savestate_filename, current_screen); + free(current_screen); + return 0; + } + + case BUTTON_ID_FASTFORWARD: + print_string("FASTFORWARD", 0xFFFF, 0x0000, 0, 50); + synchronize_flag ^= 1; + return 0; + } + + if(buttons & button_psp_mask_to_config[i]) + { + button_id = gamepad_config_map[i]; + if(button_id < BUTTON_ID_MENU) + { + new_key |= button_id_to_gba_mask[button_id]; + } + else + + if((button_id >= BUTTON_ID_RAPIDFIRE_A) && + (button_id <= BUTTON_ID_RAPIDFIRE_L)) + { + rapidfire_flag ^= 1; + if(rapidfire_flag) + { + new_key |= button_id_to_gba_mask[button_id - + BUTTON_ID_RAPIDFIRE_A + BUTTON_ID_A]; + } + else + { + new_key &= ~button_id_to_gba_mask[button_id - + BUTTON_ID_RAPIDFIRE_A + BUTTON_ID_A]; + } + } + } + } + + if((new_key | key) != key) + trigger_key(new_key); + + key = new_key; + + io_registers[REG_P1] = (~key) & 0x3FF; + + return 0; +} + +void init_input() +{ + sceCtrlSetSamplingCycle(0); + sceCtrlSetSamplingMode(PSP_CTRL_MODE_ANALOG); +} + +#endif + + +#ifdef GP2X_BUILD + +// GP2X SDL requires a user made input method +#include +#include +#include "gp2x/gp2x.h" + +u32 gamepad_config_map[16] = +{ + BUTTON_ID_UP, // Up + BUTTON_ID_LEFT, // Left + BUTTON_ID_DOWN, // Down + BUTTON_ID_RIGHT, // Right + BUTTON_ID_START, // Start + BUTTON_ID_SELECT, // Select + BUTTON_ID_L, // Ltrigger + BUTTON_ID_R, // Rtrigger + BUTTON_ID_NONE, // A + BUTTON_ID_A, // B + BUTTON_ID_B, // X + BUTTON_ID_NONE, // Y + BUTTON_ID_VOLDOWN, // Vol down + BUTTON_ID_VOLUP, // Vol up + BUTTON_ID_FPS, // Push + BUTTON_ID_MENU // Vol middle +}; + +extern u32 gp2x_fps_debug; + +u32 gpsp_gp2x_joystick_read(void) +{ + u32 value = (gpsp_gp2x_memregs[0x1198 >> 1] & 0x00FF); + + if(value == 0xFD) + value = 0xFA; + if(value == 0xF7) + value = 0xEB; + if(value == 0xDF) + value = 0xAF; + if(value == 0x7F) + value = 0xBE; + + return ~((gpsp_gp2x_memregs[0x1184 >> 1] & 0xFF00) | value | + (gpsp_gp2x_memregs[0x1186 >> 1] << 16)); +} + +gui_action_type get_gui_input() +{ + gui_action_type new_button = CURSOR_NONE; + u32 buttons = gpsp_gp2x_joystick_read(); + u32 new_buttons; + + static u32 last_buttons = 0; + static u64 button_repeat_timestamp; + + delay_us(25000); + + new_buttons = (last_buttons ^ buttons) & buttons; + last_buttons = buttons; + + if(new_buttons & GP2X_A) + new_button = CURSOR_BACK; + + if(new_buttons & GP2X_X) + new_button = CURSOR_EXIT; + + if(new_buttons & GP2X_B) + new_button = CURSOR_SELECT; + + if(new_buttons & GP2X_UP) + new_button = CURSOR_UP; + + if(new_buttons & GP2X_DOWN) + new_button = CURSOR_DOWN; + + if(new_buttons & GP2X_LEFT) + new_button = CURSOR_LEFT; + + if(new_buttons & GP2X_RIGHT) + new_button = CURSOR_RIGHT; + + + if(new_button != CURSOR_NONE) + { + get_ticks_us(&button_repeat_timestamp); + button_repeat_state = BUTTON_HELD_INITIAL; + button_repeat = new_buttons; + cursor_repeat = new_button; + } + else + { + if(buttons & button_repeat) + { + u64 new_ticks; + get_ticks_us(&new_ticks); + + if(button_repeat_state == BUTTON_HELD_INITIAL) + { + if((new_ticks - button_repeat_timestamp) > + BUTTON_REPEAT_START) + { + new_button = cursor_repeat; + button_repeat_timestamp = new_ticks; + button_repeat_state = BUTTON_HELD_REPEAT; + } + } + + if(button_repeat_state == BUTTON_HELD_REPEAT) + { + if((new_ticks - button_repeat_timestamp) > + BUTTON_REPEAT_CONTINUE) + { + new_button = cursor_repeat; + button_repeat_timestamp = new_ticks; + } + } + } + } + + return new_button; +} + +#define GP2X_VOL_MIDDLE (1 << 24) + +u32 button_gp2x_mask_to_config[] = +{ + GP2X_UP, + GP2X_LEFT, + GP2X_DOWN, + GP2X_RIGHT, + GP2X_START, + GP2X_SELECT, + GP2X_L, + GP2X_R, + GP2X_A, + GP2X_B, + GP2X_X, + GP2X_Y, + GP2X_VOL_DOWN, + GP2X_VOL_UP, + GP2X_PUSH, + GP2X_VOL_MIDDLE +}; + +u32 button_id_to_gba_mask[] = +{ + BUTTON_UP, + BUTTON_DOWN, + BUTTON_LEFT, + BUTTON_RIGHT, + BUTTON_A, + BUTTON_B, + BUTTON_L, + BUTTON_R, + BUTTON_START, + BUTTON_SELECT, + BUTTON_NONE, + BUTTON_NONE, + BUTTON_NONE, + BUTTON_NONE +}; + +u32 update_input() +{ + static u32 rapidfire_flag = 1; + static u32 last_buttons; + u32 non_repeat_buttons; + u32 button_id; + u32 new_key = 0; + u32 buttons = gpsp_gp2x_joystick_read(); + u32 i; + + if((buttons & GP2X_VOL_DOWN) && (buttons & GP2X_VOL_UP)) + { + buttons &= ~(GP2X_VOL_DOWN | GP2X_VOL_UP); + buttons |= GP2X_VOL_MIDDLE; + } + + non_repeat_buttons = (last_buttons ^ buttons) & buttons; + last_buttons = buttons; + + for(i = 0; i < 16; i++) + { + if(non_repeat_buttons & button_gp2x_mask_to_config[i]) + button_id = gamepad_config_map[i]; + else + button_id = BUTTON_ID_NONE; + + switch(button_id) + { + case BUTTON_ID_MENU: + { + u16 *screen_copy = copy_screen(); + u32 ret_val = menu(screen_copy); + free(screen_copy); + + return ret_val; + } + + case BUTTON_ID_LOADSTATE: + { + u8 current_savestate_filename[512]; + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + load_state(current_savestate_filename); + return 1; + } + + case BUTTON_ID_SAVESTATE: + { + u8 current_savestate_filename[512]; + u16 *current_screen = copy_screen(); + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + save_state(current_savestate_filename, current_screen); + free(current_screen); + return 0; + } + + case BUTTON_ID_FASTFORWARD: + print_string("FASTFORWARD", 0xFFFF, 0x0000, 0, 50); + synchronize_flag ^= 1; + return 0; + + case BUTTON_ID_VOLUP: + gp2x_sound_volume(1); + break; + + case BUTTON_ID_VOLDOWN: + gp2x_sound_volume(0); + break; + + case BUTTON_ID_FPS: + gp2x_fps_debug ^= 1; + break; + } + + if(buttons & button_gp2x_mask_to_config[i]) + { + button_id = gamepad_config_map[i]; + if(button_id < BUTTON_ID_MENU) + { + new_key |= button_id_to_gba_mask[button_id]; + } + else + + if((button_id >= BUTTON_ID_RAPIDFIRE_A) && + (button_id <= BUTTON_ID_RAPIDFIRE_L)) + { + rapidfire_flag ^= 1; + if(rapidfire_flag) + { + new_key |= button_id_to_gba_mask[button_id - + BUTTON_ID_RAPIDFIRE_A + BUTTON_ID_A]; + } + else + { + new_key &= ~button_id_to_gba_mask[button_id - + BUTTON_ID_RAPIDFIRE_A + BUTTON_ID_A]; + } + } + } + } + + if((new_key | key) != key) + trigger_key(new_key); + + key = new_key; + + io_registers[REG_P1] = (~key) & 0x3FF; + + return 0; +} + +void init_input() +{ + +} + +#endif + + + +#ifdef PC_BUILD + +u32 key_map(SDLKey key_sym) +{ + switch(key_sym) + { + case SDLK_LSHIFT: + return BUTTON_L; + + case SDLK_x: + return BUTTON_R; + + case SDLK_DOWN: + return BUTTON_DOWN; + + case SDLK_UP: + return BUTTON_UP; + + case SDLK_LEFT: + return BUTTON_LEFT; + + case SDLK_RIGHT: + return BUTTON_RIGHT; + + case SDLK_RETURN: + return BUTTON_START; + + case SDLK_RSHIFT: + return BUTTON_SELECT; + + case SDLK_LCTRL: + return BUTTON_B; + + case SDLK_LALT: + return BUTTON_A; + + default: + return BUTTON_NONE; + } +} + +u32 joy_map(u32 button) +{ + switch(button) + { + case 4: + return BUTTON_L; + + case 5: + return BUTTON_R; + + case 9: + return BUTTON_START; + + case 8: + return BUTTON_SELECT; + + case 0: + return BUTTON_B; + + case 1: + return BUTTON_A; + + default: + return BUTTON_NONE; + } +} + +gui_action_type get_gui_input() +{ + SDL_Event event; + gui_action_type gui_action = CURSOR_NONE; + + delay_us(30000); + + while(SDL_PollEvent(&event)) + { + switch(event.type) + { + case SDL_QUIT: + quit(); + + case SDL_KEYDOWN: + { + switch(event.key.keysym.sym) + { + case SDLK_ESCAPE: + gui_action = CURSOR_EXIT; + break; + + case SDLK_DOWN: + gui_action = CURSOR_DOWN; + break; + + case SDLK_UP: + gui_action = CURSOR_UP; + break; + + case SDLK_LEFT: + gui_action = CURSOR_LEFT; + break; + + case SDLK_RIGHT: + gui_action = CURSOR_RIGHT; + break; + + case SDLK_RETURN: + gui_action = CURSOR_SELECT; + break; + + case SDLK_BACKSPACE: + gui_action = CURSOR_BACK; + break; + } + break; + } + } + } + + return gui_action; +} + +u32 update_input() +{ + SDL_Event event; + + while(SDL_PollEvent(&event)) + { + switch(event.type) + { + case SDL_QUIT: + quit(); + + case SDL_KEYDOWN: + { + if(event.key.keysym.sym == SDLK_ESCAPE) + { + quit(); + } + + if(event.key.keysym.sym == SDLK_BACKSPACE) + { + u16 *screen_copy = copy_screen(); + u32 ret_val = menu(screen_copy); + free(screen_copy); + + return ret_val; + } + else + + if(event.key.keysym.sym == SDLK_F1) + { + debug_on(); + } + else + + if(event.key.keysym.sym == SDLK_F2) + { + FILE *fp = fopen("palette_ram.bin", "wb"); + printf("writing palette RAM\n"); + fwrite(palette_ram, 1024, 1, fp); + fclose(fp); + printf("writing palette VRAM\n"); + fp = fopen("vram.bin", "wb"); + fwrite(vram, 1024 * 96, 1, fp); + fclose(fp); + printf("writing palette OAM RAM\n"); + fp = fopen("oam_ram.bin", "wb"); + fwrite(oam_ram, 1024, 1, fp); + fclose(fp); + printf("writing palette I/O registers\n"); + fp = fopen("io_registers.bin", "wb"); + fwrite(io_registers, 1024, 1, fp); + fclose(fp); + } + else + + if(event.key.keysym.sym == SDLK_F3) + { + dump_translation_cache(); + } + else + + if(event.key.keysym.sym == SDLK_F5) + { + u8 current_savestate_filename[512]; + u16 *current_screen = copy_screen(); + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + save_state(current_savestate_filename, current_screen); + free(current_screen); + } + else + + if(event.key.keysym.sym == SDLK_F7) + { + u8 current_savestate_filename[512]; + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + load_state(current_savestate_filename); + debug_on(); + return 1; + } + else + + if(event.key.keysym.sym == SDLK_BACKQUOTE) + { + synchronize_flag ^= 1; + } + else + { + key |= key_map(event.key.keysym.sym); + trigger_key(key); + } + + break; + } + + case SDL_KEYUP: + { + key &= ~(key_map(event.key.keysym.sym)); + break; + } + + case SDL_JOYBUTTONDOWN: + { + key |= joy_map(event.jbutton.button); + trigger_key(key); + break; + } + + case SDL_JOYBUTTONUP: + { + key &= ~(joy_map(event.jbutton.button)); + break; + } + } + } + + io_registers[REG_P1] = (~key) & 0x3FF; + + return 0; +} + +void init_input() +{ + u32 joystick_count = SDL_NumJoysticks(); + + if(joystick_count > 0) + { + SDL_JoystickOpen(0); + SDL_JoystickEventState(SDL_ENABLE); + } +} + +#endif + + +#define input_savestate_builder(type) \ +void input_##type##_savestate(file_tag_type savestate_file) \ +{ \ + file_##type##_variable(savestate_file, key); \ +} \ + +input_savestate_builder(read); +input_savestate_builder(write_mem); + diff --git a/input.h b/input.h new file mode 100644 index 0000000..e4bc519 --- /dev/null +++ b/input.h @@ -0,0 +1,92 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INPUT_H +#define INPUT_H + +typedef enum +{ + BUTTON_L = 0x200, + BUTTON_R = 0x100, + BUTTON_DOWN = 0x80, + BUTTON_UP = 0x40, + BUTTON_LEFT = 0x20, + BUTTON_RIGHT = 0x10, + BUTTON_START = 0x08, + BUTTON_SELECT = 0x04, + BUTTON_B = 0x02, + BUTTON_A = 0x01, + BUTTON_NONE = 0x00 +} input_buttons_type; + +typedef enum +{ + BUTTON_ID_UP, + BUTTON_ID_DOWN, + BUTTON_ID_LEFT, + BUTTON_ID_RIGHT, + BUTTON_ID_A, + BUTTON_ID_B, + BUTTON_ID_L, + BUTTON_ID_R, + BUTTON_ID_START, + BUTTON_ID_SELECT, + BUTTON_ID_MENU, + BUTTON_ID_FASTFORWARD, + BUTTON_ID_LOADSTATE, + BUTTON_ID_SAVESTATE, + BUTTON_ID_RAPIDFIRE_A, + BUTTON_ID_RAPIDFIRE_B, + BUTTON_ID_RAPIDFIRE_L, + BUTTON_ID_RAPIDFIRE_R, + BUTTON_ID_VOLUP, + BUTTON_ID_VOLDOWN, + BUTTON_ID_FPS, + BUTTON_ID_NONE +} input_buttons_id_type; + +typedef enum +{ + CURSOR_UP, + CURSOR_DOWN, + CURSOR_LEFT, + CURSOR_RIGHT, + CURSOR_SELECT, + CURSOR_BACK, + CURSOR_EXIT, + CURSOR_NONE +} gui_action_type; + +void init_input(); +u32 update_input(); +gui_action_type get_gui_input(); +gui_action_type get_gui_input_fs_hold(u32 button_id); +void input_write_mem_savestate(file_tag_type savestate_file); +void input_read_savestate(file_tag_type savestate_file); + +extern u32 gamepad_config_map[16]; +extern u32 global_enable_analog; +extern u32 analog_sensitivity_level; + +#if defined(GP2X_BUILD) +u32 gpsp_gp2x_joystick_read(void); +#endif + +#endif + diff --git a/main.c b/main.c new file mode 100644 index 0000000..1f076c8 --- /dev/null +++ b/main.c @@ -0,0 +1,1053 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "common.h" + +#ifdef PSP_BUILD + +//PSP_MODULE_INFO("gpSP", 0x1000, 0, 6); +//PSP_MAIN_THREAD_ATTR(THREAD_ATTR_USER); + +void vblank_interrupt_handler(u32 sub, u32 *parg); + +#endif + +timer_type timer[4]; + +//debug_state current_debug_state = COUNTDOWN_BREAKPOINT; +//debug_state current_debug_state = PC_BREAKPOINT; +u32 breakpoint_value = 0x7c5000; +debug_state current_debug_state = RUN; +//debug_state current_debug_state = STEP_RUN; + +//u32 breakpoint_value = 0; + +frameskip_type current_frameskip_type = auto_frameskip; +u32 global_cycles_per_instruction = 1; +u32 random_skip = 0; + +#ifdef GP2X_BUILD +u32 frameskip_value = 2; + +u64 frame_count_initial_timestamp = 0; +u64 last_frame_interval_timestamp; +u32 gp2x_fps_debug = 0; + +void gp2x_quit(void); +#else + +u32 frameskip_value = 4; +#endif +u32 skip_next_frame = 0; + +u32 frameskip_counter = 0; + +u32 cpu_ticks = 0; +u32 frame_ticks = 0; + +u32 execute_cycles = 960; +s32 video_count = 960; +u32 ticks; + +u32 arm_frame = 0; +u32 thumb_frame = 0; +u32 last_frame = 0; + +u32 cycle_memory_access = 0; +u32 cycle_pc_relative_access = 0; +u32 cycle_sp_relative_access = 0; +u32 cycle_block_memory_access = 0; +u32 cycle_block_memory_sp_access = 0; +u32 cycle_block_memory_words = 0; +u32 cycle_dma16_words = 0; +u32 cycle_dma32_words = 0; +u32 flush_ram_count = 0; +u32 gbc_update_count = 0; +u32 oam_update_count = 0; + +u32 synchronize_flag = 1; + +u32 update_backup_flag = 1; +u32 clock_speed = 333; +u8 main_path[512]; + +void trigger_ext_event(); + +#define check_count(count_var) \ + if(count_var < execute_cycles) \ + execute_cycles = count_var; \ + +#define check_timer(timer_number) \ + if(timer[timer_number].status == TIMER_PRESCALE) \ + check_count(timer[timer_number].count); \ + +#define update_timer(timer_number) \ + if(timer[timer_number].status != TIMER_INACTIVE) \ + { \ + if(timer[timer_number].status != TIMER_CASCADE) \ + { \ + timer[timer_number].count -= execute_cycles; \ + io_registers[REG_TM##timer_number##D] = \ + -(timer[timer_number].count >> timer[timer_number].prescale); \ + } \ + \ + if(timer[timer_number].count <= 0) \ + { \ + if(timer[timer_number].irq == TIMER_TRIGGER_IRQ) \ + irq_raised |= IRQ_TIMER##timer_number; \ + \ + if((timer_number != 3) && \ + (timer[timer_number + 1].status == TIMER_CASCADE)) \ + { \ + timer[timer_number + 1].count--; \ + io_registers[REG_TM0D + (timer_number + 1) * 2] = \ + -(timer[timer_number + 1].count); \ + } \ + \ + if(timer_number < 2) \ + { \ + if(timer[timer_number].direct_sound_channels & 0x01) \ + sound_timer(timer[timer_number].frequency_step, 0); \ + \ + if(timer[timer_number].direct_sound_channels & 0x02) \ + sound_timer(timer[timer_number].frequency_step, 1); \ + } \ + \ + timer[timer_number].count += \ + (timer[timer_number].reload << timer[timer_number].prescale); \ + } \ + } \ + +u8 *file_ext[] = { ".gba", ".bin", ".zip", NULL }; + +#ifdef ARM_ARCH +void ChangeWorkingDirectory(char *exe) +{ +#ifndef _WIN32_WCE + char *s = strrchr(exe, '/'); + if (s != NULL) { + *s = '\0'; + chdir(exe); + *s = '/'; + } +#endif +} +#endif + +void init_main() +{ + u32 i; + + skip_next_frame = 0; + + for(i = 0; i < 4; i++) + { + dma[i].start_type = DMA_INACTIVE; + dma[i].direct_sound_channel = DMA_NO_DIRECT_SOUND; + timer[i].status = TIMER_INACTIVE; + timer[i].reload = 0x10000; + timer[i].stop_cpu_ticks = 0; + } + + timer[0].direct_sound_channels = TIMER_DS_CHANNEL_BOTH; + timer[1].direct_sound_channels = TIMER_DS_CHANNEL_NONE; + + cpu_ticks = 0; + frame_ticks = 0; + + execute_cycles = 960; + video_count = 960; + + flush_translation_cache_rom(); + flush_translation_cache_ram(); + flush_translation_cache_bios(); +} + +int main(int argc, char *argv[]) +{ + u32 i; + u32 vcount = 0; + u32 ticks; + u32 dispstat; + u8 load_filename[512]; + u8 bios_filename[512]; + +#ifdef GP2X_BUILD + if(gp2x_load_mmuhack() == -1) + delay_us(2500000); +#endif + +#ifdef PSP_BUILD + sceKernelRegisterSubIntrHandler(PSP_VBLANK_INT, 0, + vblank_interrupt_handler, NULL); + sceKernelEnableSubIntr(PSP_VBLANK_INT, 0); +#else + freopen("CON", "wb", stdout); +#endif + + extern char *cpu_mode_names[]; + + init_gamepak_buffer(); + + // Copy the directory path of the executable into main_path + +#ifdef ARM_ARCH + // ChangeWorkingDirectory will null out the filename out of the path + ChangeWorkingDirectory(argv[0]); +#endif + + getcwd(main_path, 512); + load_config_file(); + + gamepak_filename[0] = 0; + +#ifdef PSP_BUILD + delay_us(2500000); +#endif + + init_video(); + +#ifdef GP2X_BUILD + // Overclocking GP2X and MMU patch goes here + gp2x_overclock(); +#endif + +#ifdef GP2X_BUILD + sprintf(bios_filename, "%s/%s", main_path, "gba_bios.bin"); + if(load_bios(bios_filename) == -1) +#else + if(load_bios("gba_bios.bin") == -1) +#endif + { + gui_action_type gui_action = CURSOR_NONE; + + debug_screen_start(); + debug_screen_printl("Sorry, but gpSP requires a Gameboy Advance BIOS "); + debug_screen_printl("image to run correctly. Make sure to get an "); + debug_screen_printl("authentic one, it'll be exactly 16384 bytes large "); + debug_screen_printl("and should have the following md5sum value: "); + debug_screen_printl(" "); + debug_screen_printl("a860e8c0b6d573d191e4ec7db1b1e4f6 "); + debug_screen_printl(" "); + debug_screen_printl("When you do get it name it gba_bios.bin and put it"); + debug_screen_printl("in the same directory as gpSP. "); + debug_screen_printl(" "); + debug_screen_printl("Press any button to exit. "); + + debug_screen_update(); + + while(gui_action == CURSOR_NONE) + { + gui_action = get_gui_input(); + delay_us(15000); + } + + debug_screen_end(); + + quit(); + } + + if(bios_rom[0] != 0x18) + { + gui_action_type gui_action = CURSOR_NONE; + + debug_screen_start(); + debug_screen_printl("You have an incorrect BIOS image. "); + debug_screen_printl("While many games will work fine, some will not. It"); + debug_screen_printl("is strongly recommended that you obtain the "); + debug_screen_printl("correct BIOS file. Do NOT report any bugs if you "); + debug_screen_printl("are seeing this message. "); + debug_screen_printl(" "); + debug_screen_printl("Press any button to resume, at your own risk. "); + + debug_screen_update(); + + while(gui_action == CURSOR_NONE) + { + gui_action = get_gui_input(); + delay_us(15000); + } + + debug_screen_end(); + } + + init_main(); + init_sound(); + + init_input(); + + video_resolution_large(); + + if(argc > 1) + { + if(load_gamepak(argv[1]) == -1) + { +#ifdef PC_BUILD + printf("Failed to load gamepak %s, exiting.\n", load_filename); +#endif + exit(-1); + } + + set_gba_resolution(screen_scale); + video_resolution_small(); + + init_cpu(); + init_memory(); + } + else + { + if(load_file(file_ext, load_filename) == -1) + { + menu(copy_screen()); + } + else + { + if(load_gamepak(load_filename) == -1) + { +#ifdef PC_BUILD + printf("Failed to load gamepak %s, exiting.\n", load_filename); +#endif + exit(-1); + } + + set_gba_resolution(screen_scale); + video_resolution_small(); + + init_cpu(); + init_memory(); + } + } + + last_frame = 0; + + // We'll never actually return from here. + +#ifdef PSP_BUILD + execute_arm_translate(execute_cycles); +#else + +#ifdef GP2X_BUILD + get_ticks_us(&frame_count_initial_timestamp); +#endif + +/* u8 current_savestate_filename[512]; + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + load_state(current_savestate_filename); */ + + debug_on(); + + if(argc > 2) + { + current_debug_state = COUNTDOWN_BREAKPOINT; + breakpoint_value = strtol(argv[2], NULL, 16); + } + + trigger_ext_event(); + + execute_arm_translate(execute_cycles); + execute_arm(execute_cycles); +#endif + return 0; +} + +void print_memory_stats(u32 *counter, u32 *region_stats, char *stats_str) +{ + u32 other_region_counter = region_stats[0x1] + region_stats[0xE] + + region_stats[0xF]; + u32 rom_region_counter = region_stats[0x8] + region_stats[0x9] + + region_stats[0xA] + region_stats[0xB] + region_stats[0xC] + + region_stats[0xD]; + u32 _counter = *counter; + + printf("memory access stats: %s (out of %d)\n", stats_str, _counter); + printf("bios: %f%%\tiwram: %f%%\tewram: %f%%\tvram: %f\n", + region_stats[0x0] * 100.0 / _counter, region_stats[0x3] * 100.0 / + _counter, + region_stats[0x2] * 100.0 / _counter, region_stats[0x6] * 100.0 / + _counter); + + printf("oam: %f%%\tpalette: %f%%\trom: %f%%\tother: %f%%\n", + region_stats[0x7] * 100.0 / _counter, region_stats[0x5] * 100.0 / + _counter, + rom_region_counter * 100.0 / _counter, other_region_counter * 100.0 / + _counter); + + *counter = 0; + memset(region_stats, 0, sizeof(u32) * 16); +} + +u32 event_cycles = 0; +const u32 event_cycles_trigger = 60 * 5; +u32 no_alpha = 0; + +void trigger_ext_event() +{ + static u32 event_number = 0; + static u64 benchmark_ticks[16]; + u64 new_ticks; + u8 current_savestate_filename[512]; + + return; + + if(event_number) + { + get_ticks_us(&new_ticks); + benchmark_ticks[event_number - 1] = + new_ticks - benchmark_ticks[event_number - 1]; + } + + current_frameskip_type = no_frameskip; + no_alpha = 0; + synchronize_flag = 0; + + get_savestate_filename_noshot(savestate_slot, + current_savestate_filename); + load_state(current_savestate_filename); + + switch(event_number) + { + case 0: + // Full benchmark, run normally + break; + + case 1: + // No alpha blending + no_alpha = 1; + break; + + case 2: + // No video benchmark + // Set frameskip really high + manual + current_frameskip_type = manual_frameskip; + frameskip_value = 1000000; + break; + + case 3: + // No CPU benchmark + // Put CPU in halt mode, put it in IRQ mode with interrupts off + reg[CPU_HALT_STATE] = CPU_HALT; + reg[REG_CPSR] = 0xD2; + break; + + case 4: + // No CPU or video benchmark + reg[CPU_HALT_STATE] = CPU_HALT; + reg[REG_CPSR] = 0xD2; + current_frameskip_type = manual_frameskip; + frameskip_value = 1000000; + break; + + case 5: + { + // Done + char *print_strings[] = + { + "Full test ", + "No blending ", + "No video ", + "No CPU ", + "No CPU/video", + "CPU speed ", + "Video speed ", + "Alpha cost " + }; + u32 i; + + benchmark_ticks[6] = benchmark_ticks[0] - benchmark_ticks[2]; + benchmark_ticks[5] = benchmark_ticks[0] - benchmark_ticks[4] - + benchmark_ticks[6]; + benchmark_ticks[7] = benchmark_ticks[0] - benchmark_ticks[1]; + + printf("Benchmark results (%d frames): \n", event_cycles_trigger); + for(i = 0; i < 8; i++) + { + printf(" %s: %d ms (%f ms per frame)\n", + print_strings[i], (u32)benchmark_ticks[i] / 1000, + (float)(benchmark_ticks[i] / (1000.0 * event_cycles_trigger))); + if(i == 4) + printf("\n"); + } + quit(); + } + } + + event_cycles = 0; + + get_ticks_us(benchmark_ticks + event_number); + event_number++; +} + +u32 update_gba() +{ + irq_type irq_raised = IRQ_NONE; + + do + { + cpu_ticks += execute_cycles; + + reg[CHANGED_PC_STATUS] = 0; + + if(gbc_sound_update) + { + gbc_update_count++; + update_gbc_sound(cpu_ticks); + gbc_sound_update = 0; + } + + update_timer(0); + update_timer(1); + update_timer(2); + update_timer(3); + + video_count -= execute_cycles; + + if(video_count <= 0) + { + u32 vcount = io_registers[REG_VCOUNT]; + u32 dispstat = io_registers[REG_DISPSTAT]; + + if((dispstat & 0x02) == 0) + { + // Transition from hrefresh to hblank + video_count += (272); + dispstat |= 0x02; + + if((dispstat & 0x01) == 0) + { + u32 i; + if(oam_update) + oam_update_count++; + + if(no_alpha) + io_registers[REG_BLDCNT] = 0; + update_scanline(); + + // If in visible area also fire HDMA + for(i = 0; i < 4; i++) + { + if(dma[i].start_type == DMA_START_HBLANK) + dma_transfer(dma + i); + } + } + + if(dispstat & 0x10) + irq_raised |= IRQ_HBLANK; + } + else + { + // Transition from hblank to next line + video_count += 960; + dispstat &= ~0x02; + + vcount++; + + if(vcount == 160) + { + // Transition from vrefresh to vblank + u32 i; + + dispstat |= 0x01; + if(dispstat & 0x8) + { + irq_raised |= IRQ_VBLANK; + } + + affine_reference_x[0] = + (s32)(address32(io_registers, 0x28) << 4) >> 4; + affine_reference_y[0] = + (s32)(address32(io_registers, 0x2C) << 4) >> 4; + affine_reference_x[1] = + (s32)(address32(io_registers, 0x38) << 4) >> 4; + affine_reference_y[1] = + (s32)(address32(io_registers, 0x3C) << 4) >> 4; + + for(i = 0; i < 4; i++) + { + if(dma[i].start_type == DMA_START_VBLANK) + dma_transfer(dma + i); + } + } + else + + if(vcount == 228) + { + // Transition from vblank to next screen + dispstat &= ~0x01; + frame_ticks++; + + #ifdef PC_BUILD + printf("frame update (%x), %d instructions total, %d RAM flushes\n", + reg[REG_PC], instruction_count - last_frame, flush_ram_count); + last_frame = instruction_count; + +/* printf("%d gbc audio updates\n", gbc_update_count); + printf("%d oam updates\n", oam_update_count); */ + gbc_update_count = 0; + oam_update_count = 0; + flush_ram_count = 0; + #endif + + if(update_input()) + continue; + + update_gbc_sound(cpu_ticks); + synchronize(); + + update_screen(); + + if(update_backup_flag) + update_backup(); + + process_cheats(); + + event_cycles++; + if(event_cycles == event_cycles_trigger) + { + trigger_ext_event(); + continue; + } + + vcount = 0; + } + + if(vcount == (dispstat >> 8)) + { + // vcount trigger + dispstat |= 0x04; + if(dispstat & 0x20) + { + irq_raised |= IRQ_VCOUNT; + } + } + else + { + dispstat &= ~0x04; + } + + io_registers[REG_VCOUNT] = vcount; + } + io_registers[REG_DISPSTAT] = dispstat; + } + + if(irq_raised) + raise_interrupt(irq_raised); + + execute_cycles = video_count; + + check_timer(0); + check_timer(1); + check_timer(2); + check_timer(3); + } while(reg[CPU_HALT_STATE] != CPU_ACTIVE); + + return execute_cycles; +} + +u64 last_screen_timestamp = 0; +u32 frame_speed = 15000; + + +#ifdef PSP_BUILD + +u32 real_frame_count = 0; +u32 virtual_frame_count = 0; +u32 num_skipped_frames = 0; + +void vblank_interrupt_handler(u32 sub, u32 *parg) +{ + real_frame_count++; +} + +void synchronize() +{ + char char_buffer[64]; + u64 new_ticks, time_delta; + s32 used_frameskip = frameskip_value; + + if(!synchronize_flag) + { + print_string("--FF--", 0xFFFF, 0x000, 0, 0); + used_frameskip = 4; + virtual_frame_count = real_frame_count - 1; + } + + skip_next_frame = 0; + + virtual_frame_count++; + + if(real_frame_count >= virtual_frame_count) + { + if((real_frame_count > virtual_frame_count) && + (current_frameskip_type == auto_frameskip) && + (num_skipped_frames < frameskip_value)) + { + skip_next_frame = 1; + num_skipped_frames++; + } + else + { + virtual_frame_count = real_frame_count; + num_skipped_frames = 0; + } + + // Here so that the home button return will eventually work. + // If it's not running fullspeed anyway this won't really hurt + // it much more. + + delay_us(1); + } + else + { + if(synchronize_flag) + sceDisplayWaitVblankStart(); + } + + if(current_frameskip_type == manual_frameskip) + { + frameskip_counter = (frameskip_counter + 1) % + (used_frameskip + 1); + if(random_skip) + { + if(frameskip_counter != (rand() % (used_frameskip + 1))) + skip_next_frame = 1; + } + else + { + if(frameskip_counter) + skip_next_frame = 1; + } + } + +/* sprintf(char_buffer, "%08d %08d %d %d %d\n", + real_frame_count, virtual_frame_count, num_skipped_frames, + real_frame_count - virtual_frame_count, skip_next_frame); + print_string(char_buffer, 0xFFFF, 0x0000, 0, 10); */ + +/* + sprintf(char_buffer, "%02d %02d %06d %07d", frameskip, (u32)ms_needed, + ram_translation_ptr - ram_translation_cache, rom_translation_ptr - + rom_translation_cache); + print_string(char_buffer, 0xFFFF, 0x0000, 0, 0); +*/ +} + +#endif + +#ifdef GP2X_BUILD + +u32 real_frame_count = 0; +u32 virtual_frame_count = 0; +u32 num_skipped_frames = 0; +u32 interval_skipped_frames; +u32 frames; + +u32 skipped_frames = 0; +u32 ticks_needed_total = 0; +const u32 frame_interval = 60; + +void synchronize() +{ + u64 new_ticks; + u64 time_delta; + static u32 fps = 60; + static u32 frames_drawn = 60; + + if(gp2x_fps_debug) + { + char print_buffer[128]; + sprintf(print_buffer, "%d (%d)", fps, frames_drawn); + print_string(print_buffer, 0xFFFF, 0x000, 0, 0); + } + + get_ticks_us(&new_ticks); + time_delta = new_ticks - last_screen_timestamp; + last_screen_timestamp = new_ticks; + ticks_needed_total += time_delta; + + skip_next_frame = 0; + virtual_frame_count++; + + real_frame_count = ((new_ticks - + frame_count_initial_timestamp) * 3) / 50000; + + if(real_frame_count >= virtual_frame_count) + { + if((real_frame_count > virtual_frame_count) && + (current_frameskip_type == auto_frameskip) && + (num_skipped_frames < frameskip_value)) + { + skip_next_frame = 1; + num_skipped_frames++; + } + else + { + virtual_frame_count = real_frame_count; + num_skipped_frames = 0; + } + } + else + { + if((synchronize_flag) && + ((time_delta < frame_speed) && synchronize_flag)) + { + delay_us(frame_speed - time_delta); + } + } + + frames++; + + if(frames == frame_interval) + { + u32 new_fps; + u32 new_frames_drawn; + + time_delta = new_ticks - last_frame_interval_timestamp; + new_fps = (u64)((u64)1000000 * (u64)frame_interval) / time_delta; + new_frames_drawn = + (frame_interval - interval_skipped_frames) * (60 / frame_interval); + + // Left open for rolling averages + fps = new_fps; + frames_drawn = new_frames_drawn; + + last_frame_interval_timestamp = new_ticks; + interval_skipped_frames = 0; + ticks_needed_total = 0; + frames = 0; + } + + if(current_frameskip_type == manual_frameskip) + { + frameskip_counter = (frameskip_counter + 1) % + (frameskip_value + 1); + if(random_skip) + { + if(frameskip_counter != (rand() % (frameskip_value + 1))) + skip_next_frame = 1; + } + else + { + if(frameskip_counter) + skip_next_frame = 1; + } + } + + interval_skipped_frames += skip_next_frame; + + if(!synchronize_flag) + print_string("--FF--", 0xFFFF, 0x000, 0, 0); +} + +#endif + + +#ifdef PC_BUILD + +u32 ticks_needed_total = 0; +float us_needed = 0.0; +u32 frames = 0; +const u32 frame_interval = 60; + +void synchronize() +{ + u64 new_ticks; + u64 time_delta; + char char_buffer[64]; + + get_ticks_us(&new_ticks); + time_delta = new_ticks - last_screen_timestamp; + last_screen_timestamp = new_ticks; + ticks_needed_total += time_delta; + + skip_next_frame = 0; + + if((time_delta < frame_speed) && synchronize_flag) + { + delay_us(frame_speed - time_delta); + } + + frames++; + + if(frames == frame_interval) + { + us_needed = (float)ticks_needed_total / frame_interval; + ticks_needed_total = 0; + frames = 0; + } + + if(current_frameskip_type == manual_frameskip) + { + frameskip_counter = (frameskip_counter + 1) % + (frameskip_value + 1); + if(random_skip) + { + if(frameskip_counter != (rand() % (frameskip_value + 1))) + skip_next_frame = 1; + } + else + { + if(frameskip_counter) + skip_next_frame = 1; + } + } + + if(synchronize_flag == 0) + print_string("--FF--", 0xFFFF, 0x000, 0, 0); + + sprintf(char_buffer, "gpSP: %.1fms %.1ffps", us_needed / 1000.0, + 1000000.0 / us_needed); + SDL_WM_SetCaption(char_buffer, "gpSP"); + +/* + sprintf(char_buffer, "%02d %02d %06d %07d", frameskip, (u32)ms_needed, + ram_translation_ptr - ram_translation_cache, rom_translation_ptr - + rom_translation_cache); + print_string(char_buffer, 0xFFFF, 0x0000, 0, 0); +*/ +} + +#endif + +void quit() +{ + if(!update_backup_flag) + update_backup_force(); + + sound_exit(); + +#ifdef REGISTER_USAGE_ANALYZE + print_register_usage(); +#endif + +#ifdef PSP_BUILD + sceKernelExitGame(); +#else + SDL_Quit(); + +#ifdef GP2X_BUILD + gp2x_quit(); +#endif + + exit(0); +#endif +} + +void reset_gba() +{ + init_main(); + init_memory(); + init_cpu(); + reset_sound(); +} + +#ifdef PSP_BUILD + +u32 file_length(u8 *filename, s32 dummy) +{ + SceIoStat stats; + sceIoGetstat(filename, &stats); + return stats.st_size; +} + +void delay_us(u32 us_count) +{ + sceKernelDelayThread(us_count); +} + +void get_ticks_us(u64 *tick_return) +{ + u64 ticks; + sceRtcGetCurrentTick(&ticks); + + *tick_return = (ticks * 1000000) / sceRtcGetTickResolution(); +} + +#else + +u32 file_length(u8 *dummy, FILE *fp) +{ + u32 length; + + fseek(fp, 0, SEEK_END); + length = ftell(fp); + fseek(fp, 0, SEEK_SET); + + return length; +} + +#ifdef PC_BUILD + +void delay_us(u32 us_count) +{ + SDL_Delay(us_count / 1000); +} + +void get_ticks_us(u64 *ticks_return) +{ + *ticks_return = (SDL_GetTicks() * 1000); +} + +#else + +void delay_us(u32 us_count) +{ + usleep(us_count); +} + +void get_ticks_us(u64 *ticks_return) +{ + struct timeval current_time; + gettimeofday(¤t_time, NULL); + + *ticks_return = + (u64)current_time.tv_sec * 1000000 + current_time.tv_usec; +} + +#endif + +#endif + +void change_ext(u8 *src, u8 *buffer, u8 *extension) +{ + u8 *dot_position; + strcpy(buffer, src); + dot_position = strrchr(buffer, '.'); + + if(dot_position) + strcpy(dot_position, extension); +} + +#define main_savestate_builder(type) \ +void main_##type##_savestate(file_tag_type savestate_file) \ +{ \ + file_##type##_variable(savestate_file, cpu_ticks); \ + file_##type##_variable(savestate_file, execute_cycles); \ + file_##type##_variable(savestate_file, video_count); \ + file_##type##_array(savestate_file, timer); \ +} \ + +main_savestate_builder(read); +main_savestate_builder(write_mem); + + +void printout(void *str, u32 val) +{ + printf(str, val); +} diff --git a/main.h b/main.h new file mode 100644 index 0000000..397541d --- /dev/null +++ b/main.h @@ -0,0 +1,202 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAIN_H +#define MAIN_H + +typedef enum +{ + TIMER_INACTIVE, + TIMER_PRESCALE, + TIMER_CASCADE +} timer_status_type; + +typedef enum +{ + TIMER_NO_IRQ, + TIMER_TRIGGER_IRQ +} timer_irq_type; + + +typedef enum +{ + TIMER_DS_CHANNEL_NONE, + TIMER_DS_CHANNEL_A, + TIMER_DS_CHANNEL_B, + TIMER_DS_CHANNEL_BOTH +} timer_ds_channel_type; + +typedef struct +{ + s32 count; + u32 reload; + u32 prescale; + u32 stop_cpu_ticks; + fixed16_16 frequency_step; + timer_ds_channel_type direct_sound_channels; + timer_irq_type irq; + timer_status_type status; +} timer_type; + +typedef enum +{ + auto_frameskip, + manual_frameskip, + no_frameskip +} frameskip_type; + +extern u32 cpu_ticks; +extern u32 frame_ticks; +extern u32 execute_cycles; +extern frameskip_type current_frameskip_type; +extern u32 frameskip_value; +extern u32 random_skip; +extern u32 global_cycles_per_instruction; +extern u32 synchronize_flag; +extern u32 skip_next_frame; + +extern timer_type timer[4]; +static u32 prescale_table[] = { 0, 6, 8, 10 }; + +extern u32 cycle_memory_access; +extern u32 cycle_pc_relative_access; +extern u32 cycle_sp_relative_access; +extern u32 cycle_block_memory_access; +extern u32 cycle_block_memory_sp_access; +extern u32 cycle_block_memory_words; +extern u32 cycle_dma16_words; +extern u32 cycle_dma32_words; +extern u32 flush_ram_count; + +extern u64 base_timestamp; + +extern u8 main_path[512]; + +extern u32 update_backup_flag; +extern u32 clock_speed; + +u32 update_gba(); +void reset_gba(); +void synchronize(); +void quit(); +void delay_us(u32 us_count); +void get_ticks_us(u64 *tick_return); +void game_name_ext(u8 *src, u8 *buffer, u8 *extension); +void main_write_mem_savestate(file_tag_type savestate_file); +void main_read_savestate(file_tag_type savestate_file); + + +#ifdef PSP_BUILD + +u32 file_length(u8 *filename, s32 dummy); + +extern u32 real_frame_count; +extern u32 virtual_frame_count; +extern u32 max_frameskip; +extern u32 num_skipped_frames; + +#endif + + +#ifdef GP2X_BUILD + +extern u64 frame_count_initial_timestamp; +extern u32 real_frame_count; +extern u32 virtual_frame_count; +extern u32 max_frameskip; +extern u32 num_skipped_frames; + +#endif + + +#ifdef PC_BUILD + +u32 file_length(u8 *dummy, FILE *fp); + +#endif + +#define count_timer(timer_number) \ + timer[timer_number].reload = 0x10000 - value; \ + if(timer_number < 2) \ + { \ + u32 timer_reload = \ + timer[timer_number].reload << timer[timer_number].prescale; \ + sound_update_frequency_step(timer_number); \ + } \ + +#define adjust_sound_buffer(timer_number, channel) \ + if(timer[timer_number].direct_sound_channels & (0x01 << channel)) \ + { \ + direct_sound_channel[channel].buffer_index = \ + (direct_sound_channel[channel].buffer_index + buffer_adjust) % \ + BUFFER_SIZE; \ + } \ + +#define trigger_timer(timer_number) \ + if(value & 0x80) \ + { \ + if(timer[timer_number].status == TIMER_INACTIVE) \ + { \ + u32 prescale = prescale_table[value & 0x03]; \ + u32 timer_reload = timer[timer_number].reload; \ + \ + if((value >> 2) & 0x01) \ + timer[timer_number].status = TIMER_CASCADE; \ + else \ + timer[timer_number].status = TIMER_PRESCALE; \ + \ + timer[timer_number].prescale = prescale; \ + timer[timer_number].irq = (value >> 6) & 0x01; \ + \ + address16(io_registers, 0x100 + (timer_number * 4)) = \ + -timer_reload; \ + \ + timer_reload <<= prescale; \ + timer[timer_number].count = timer_reload; \ + \ + if(timer_reload < execute_cycles) \ + execute_cycles = timer_reload; \ + \ + if(timer_number < 2) \ + { \ + u32 buffer_adjust = \ + (u32)(((float)(cpu_ticks - timer[timer_number].stop_cpu_ticks) * \ + sound_frequency) / 16777216.0) * 2; \ + \ + sound_update_frequency_step(timer_number); \ + adjust_sound_buffer(timer_number, 0); \ + adjust_sound_buffer(timer_number, 1); \ + } \ + } \ + } \ + else \ + { \ + if(timer[timer_number].status != TIMER_INACTIVE) \ + { \ + timer[timer_number].status = TIMER_INACTIVE; \ + timer[timer_number].stop_cpu_ticks = cpu_ticks; \ + } \ + } \ + address16(io_registers, 0x102 + (timer_number * 4)) = value; \ + +void change_ext(u8 *src, u8 *buffer, u8 *extension); + +#endif + + diff --git a/memory.c b/memory.c new file mode 100644 index 0000000..e902af3 --- /dev/null +++ b/memory.c @@ -0,0 +1,3271 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "common.h" + +u32 load_file_zip(u8 *filename); + +// This table is configured for sequential access on system defaults + +u32 waitstate_cycles_sequential[16][3] = +{ + { 1, 1, 1 }, // BIOS + { 1, 1, 1 }, // Invalid + { 3, 3, 6 }, // EWRAM (default settings) + { 1, 1, 1 }, // IWRAM + { 1, 1, 1 }, // IO Registers + { 1, 1, 2 }, // Palette RAM + { 1, 1, 2 }, // VRAM + { 1, 1, 2 }, // OAM + { 3, 3, 6 }, // Gamepak (wait 0) + { 3, 3, 6 }, // Gamepak (wait 0) + { 5, 5, 9 }, // Gamepak (wait 1) + { 5, 5, 9 }, // Gamepak (wait 1) + { 9, 9, 17 }, // Gamepak (wait 2) + { 9, 9, 17 }, // Gamepak (wait 2) +}; + +// Different settings for gamepak ws0-2 sequential (2nd) access + +u32 gamepak_waitstate_sequential[2][3][3] = +{ + { + { 3, 3, 6 }, + { 5, 5, 9 }, + { 9, 9, 17 } + }, + { + { 2, 2, 3 }, + { 2, 2, 3 }, + { 2, 2, 3 } + } +}; + +u16 palette_ram[512]; +u16 oam_ram[512]; +u16 palette_ram_converted[512]; +u16 io_registers[1024 * 16]; +u8 ewram[1024 * 256 * 2]; +u8 iwram[1024 * 32 * 2]; +u8 vram[1024 * 96 * 2]; + +u8 bios_rom[1024 * 32]; +u32 bios_read_protect; + +// Up to 128kb, store SRAM, flash ROM, or EEPROM here. +u8 gamepak_backup[1024 * 128]; + +// Keeps us knowing how much we have left. +u8 *gamepak_rom; +u32 gamepak_size; + +dma_transfer_type dma[4]; + +u8 *memory_regions[16]; +u32 memory_limits[16]; + +typedef struct +{ + u32 page_timestamp; + u32 physical_index; +} gamepak_swap_entry_type; + +u32 gamepak_ram_buffer_size; +u32 gamepak_ram_pages; + +// Enough to map the gamepak RAM space. +gamepak_swap_entry_type *gamepak_memory_map; + +// This is global so that it can be kept open for large ROMs to swap +// pages from, so there's no slowdown with opening and closing the file +// a lot. +#ifdef PSP_BUILD + +file_tag_type gamepak_file_large = -1; + +#else + +file_tag_type gamepak_file_large = NULL; + +#endif + +u32 direct_map_vram = 0; + +// Writes to these respective locations should trigger an update +// so the related subsystem may react to it. + +// If OAM is written to: +u32 oam_update = 1; + +// If GBC audio is written to: +u32 gbc_sound_update = 0; + +// If the GBC audio waveform is modified: +u32 gbc_sound_wave_update = 0; + +// If the backup space is written (only update once this hits 0) +u32 backup_update = 0; + +// Write out backup file this many cycles after the most recent +// backup write. +const u32 write_backup_delay = 10; + + +typedef enum +{ + BACKUP_SRAM, + BACKUP_FLASH, + BACKUP_EEPROM, + BACKUP_NONE +} backup_type_type; + +typedef enum +{ + SRAM_SIZE_32KB, + SRAM_SIZE_64KB +} sram_size_type; + +// Keep it 32KB until the upper 64KB is accessed, then make it 64KB. + +backup_type_type backup_type = BACKUP_NONE; +sram_size_type sram_size = SRAM_SIZE_32KB; + +typedef enum +{ + FLASH_BASE_MODE, + FLASH_ERASE_MODE, + FLASH_ID_MODE, + FLASH_WRITE_MODE, + FLASH_BANKSWITCH_MODE +} flash_mode_type; + +typedef enum +{ + FLASH_SIZE_64KB, + FLASH_SIZE_128KB +} flash_size_type; + +flash_mode_type flash_mode = FLASH_BASE_MODE; +u32 flash_command_position = 0; +u8 *flash_bank_ptr = gamepak_backup; + +flash_device_id_type flash_device_id = FLASH_DEVICE_MACRONIX_64KB; +flash_manufacturer_id_type flash_manufacturer_id = + FLASH_MANUFACTURER_MACRONIX; +flash_size_type flash_size = FLASH_SIZE_64KB; + +u8 read_backup(u32 address) +{ + u8 value; + + if(backup_type == BACKUP_NONE) + backup_type = BACKUP_SRAM; + + if(backup_type == BACKUP_SRAM) + { + value = gamepak_backup[address]; + } + else + + if(flash_mode == FLASH_ID_MODE) + { + /* ID manufacturer type */ + if(address == 0x0000) + value = flash_manufacturer_id; + else + + /* ID device type */ + if(address == 0x0001) + value = flash_device_id; + } + else + { + value = flash_bank_ptr[address]; + } + + return value; +} + +#define read_backup8() \ + value = read_backup(address & 0xFFFF) \ + +#define read_backup16() \ + value = 0 \ + +#define read_backup32() \ + value = 0 \ + + +// EEPROM is 512 bytes by default; it is autodetecte as 8KB if +// 14bit address DMAs are made (this is done in the DMA handler). + +typedef enum +{ + EEPROM_512_BYTE, + EEPROM_8_KBYTE +} eeprom_size_type; + +typedef enum +{ + EEPROM_BASE_MODE, + EEPROM_READ_MODE, + EEPROM_READ_HEADER_MODE, + EEPROM_ADDRESS_MODE, + EEPROM_WRITE_MODE, + EEPROM_WRITE_ADDRESS_MODE, + EEPROM_ADDRESS_FOOTER_MODE, + EEPROM_WRITE_FOOTER_MODE +} eeprom_mode_type; + + +eeprom_size_type eeprom_size = EEPROM_512_BYTE; +eeprom_mode_type eeprom_mode = EEPROM_BASE_MODE; +u32 eeprom_address_length; +u32 eeprom_address = 0; +s32 eeprom_counter = 0; +u8 eeprom_buffer[8]; + + +void function_cc write_eeprom(u32 address, u32 value) +{ + switch(eeprom_mode) + { + case EEPROM_BASE_MODE: + backup_type = BACKUP_EEPROM; + eeprom_buffer[0] |= (value & 0x01) << (1 - eeprom_counter); + eeprom_counter++; + if(eeprom_counter == 2) + { + if(eeprom_size == EEPROM_512_BYTE) + eeprom_address_length = 6; + else + eeprom_address_length = 14; + + eeprom_counter = 0; + + switch(eeprom_buffer[0] & 0x03) + { + case 0x02: + eeprom_mode = EEPROM_WRITE_ADDRESS_MODE; + break; + + case 0x03: + eeprom_mode = EEPROM_ADDRESS_MODE; + break; + } + address16(eeprom_buffer, 0) = 0; + } + break; + + case EEPROM_ADDRESS_MODE: + case EEPROM_WRITE_ADDRESS_MODE: + eeprom_buffer[eeprom_counter / 8] + |= (value & 0x01) << (7 - (eeprom_counter % 8)); + eeprom_counter++; + if(eeprom_counter == eeprom_address_length) + { + if(eeprom_size == EEPROM_512_BYTE) + { + eeprom_address = + (address16(eeprom_buffer, 0) >> 2) * 8; + } + else + { + eeprom_address = (((u32)eeprom_buffer[1] >> 2) | + ((u32)eeprom_buffer[0] << 6)) * 8; + } + + address16(eeprom_buffer, 0) = 0; + eeprom_counter = 0; + + if(eeprom_mode == EEPROM_ADDRESS_MODE) + { + eeprom_mode = EEPROM_ADDRESS_FOOTER_MODE; + } + else + { + eeprom_mode = EEPROM_WRITE_MODE; + memset(gamepak_backup + eeprom_address, 0, 8); + } + } + break; + + case EEPROM_WRITE_MODE: + gamepak_backup[eeprom_address + (eeprom_counter / 8)] |= + (value & 0x01) << (7 - (eeprom_counter % 8)); + eeprom_counter++; + if(eeprom_counter == 64) + { + backup_update = write_backup_delay; + eeprom_counter = 0; + eeprom_mode = EEPROM_WRITE_FOOTER_MODE; + } + break; + + case EEPROM_ADDRESS_FOOTER_MODE: + case EEPROM_WRITE_FOOTER_MODE: + eeprom_counter = 0; + if(eeprom_mode == EEPROM_ADDRESS_FOOTER_MODE) + { + eeprom_mode = EEPROM_READ_HEADER_MODE; + } + else + { + eeprom_mode = EEPROM_BASE_MODE; + } + break; + } +} + +#define read_memory_gamepak(type) \ + u32 gamepak_index = address >> 15; \ + u8 *map = memory_map_read[gamepak_index]; \ + \ + if(map == NULL) \ + map = load_gamepak_page(gamepak_index & 0x3FF); \ + \ + value = address##type(map, address & 0x7FFF) \ + +#define read_open8() \ + if(!(reg[REG_CPSR] & 0x20)) \ + value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \ + else \ + value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \ + +#define read_open16() \ + if(!(reg[REG_CPSR] & 0x20)) \ + value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \ + else \ + value = read_memory16(reg[REG_PC] + 2) \ + +#define read_open32() \ + if(!(reg[REG_CPSR] & 0x20)) \ + { \ + value = read_memory32(reg[REG_PC] + 4); \ + } \ + else \ + { \ + u32 current_instruction = read_memory16(reg[REG_PC] + 2); \ + value = current_instruction | (current_instruction << 16); \ + } \ + +u32 function_cc read_eeprom() +{ + u32 value; + + switch(eeprom_mode) + { + case EEPROM_BASE_MODE: + value = 1; + break; + + case EEPROM_READ_MODE: + value = (gamepak_backup[eeprom_address + (eeprom_counter / 8)] >> + (7 - (eeprom_counter % 8))) & 0x01; + eeprom_counter++; + if(eeprom_counter == 64) + { + eeprom_counter = 0; + eeprom_mode = EEPROM_BASE_MODE; + } + break; + + case EEPROM_READ_HEADER_MODE: + value = 0; + eeprom_counter++; + if(eeprom_counter == 4) + { + eeprom_mode = EEPROM_READ_MODE; + eeprom_counter = 0; + } + break; + + default: + value = 0; + break; + } + + return value; +} + + +#define read_memory(type) \ + switch(address >> 24) \ + { \ + case 0x00: \ + /* BIOS */ \ + if(reg[REG_PC] >= 0x4000) \ + value = address##type(&bios_read_protect, address & 0x03); \ + else \ + value = address##type(bios_rom, address & 0x3FFF); \ + break; \ + \ + case 0x02: \ + /* external work RAM */ \ + address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \ + value = address##type(ewram, address); \ + break; \ + \ + case 0x03: \ + /* internal work RAM */ \ + value = address##type(iwram, (address & 0x7FFF) + 0x8000); \ + break; \ + \ + case 0x04: \ + /* I/O registers */ \ + value = address##type(io_registers, address & 0x3FF); \ + break; \ + \ + case 0x05: \ + /* palette RAM */ \ + value = address##type(palette_ram, address & 0x3FF); \ + break; \ + \ + case 0x06: \ + /* VRAM */ \ + address &= 0x1FFFF; \ + if(address > 0x18000) \ + address -= 0x8000; \ + \ + value = address##type(vram, address); \ + break; \ + \ + case 0x07: \ + /* OAM RAM */ \ + value = address##type(oam_ram, address & 0x3FF); \ + break; \ + \ + case 0x08: \ + case 0x09: \ + case 0x0A: \ + case 0x0B: \ + case 0x0C: \ + /* gamepak ROM */ \ + if((address & 0x1FFFFFF) >= gamepak_size) \ + { \ + value = 0; \ + } \ + else \ + { \ + read_memory_gamepak(type); \ + } \ + break; \ + \ + case 0x0D: \ + if((address & 0x1FFFFFF) < gamepak_size) \ + { \ + read_memory_gamepak(type); \ + } \ + else \ + { \ + value = read_eeprom(); \ + } \ + \ + break; \ + \ + case 0x0E: \ + case 0x0F: \ + read_backup##type(); \ + break; \ + \ + default: \ + read_open##type(); \ + break; \ + } \ + +#define trigger_dma(dma_number) \ + if(value & 0x8000) \ + { \ + if(dma[dma_number].start_type == DMA_INACTIVE) \ + { \ + u32 start_type = (value >> 12) & 0x03; \ + u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) & \ + 0xFFFFFFF; \ + \ + dma[dma_number].dma_channel = dma_number; \ + dma[dma_number].source_address = \ + address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF; \ + dma[dma_number].dest_address = dest_address; \ + dma[dma_number].source_direction = (value >> 7) & 0x03; \ + dma[dma_number].repeat_type = (value >> 9) & 0x01; \ + dma[dma_number].start_type = start_type; \ + dma[dma_number].irq = (value >> 14) & 0x01; \ + \ + /* If it is sound FIFO DMA make sure the settings are a certain way */ \ + if((dma_number >= 1) && (dma_number <= 2) && \ + (start_type == DMA_START_SPECIAL)) \ + { \ + dma[dma_number].length_type = DMA_32BIT; \ + dma[dma_number].length = 4; \ + dma[dma_number].dest_direction = DMA_FIXED; \ + if(dest_address == 0x40000A4) \ + dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_B; \ + else \ + dma[dma_number].direct_sound_channel = DMA_DIRECT_SOUND_A; \ + } \ + else \ + { \ + u32 length = \ + address16(io_registers, (dma_number * 12) + 0xB8); \ + \ + if((dma_number == 3) && ((dest_address >> 24) == 0x0D) && \ + ((length & 0x1F) == 17)) \ + { \ + eeprom_size = EEPROM_8_KBYTE; \ + } \ + \ + if(dma_number < 3) \ + length &= 0x3FFF; \ + \ + if(length == 0) \ + { \ + if(dma_number == 3) \ + length = 0x10000; \ + else \ + length = 0x04000; \ + } \ + \ + dma[dma_number].length = length; \ + dma[dma_number].length_type = (value >> 10) & 0x01; \ + dma[dma_number].dest_direction = (value >> 5) & 0x03; \ + } \ + \ + address16(io_registers, (dma_number * 12) + 0xBA) = value; \ + if(start_type == DMA_START_IMMEDIATELY) \ + return dma_transfer(dma + dma_number); \ + } \ + } \ + else \ + { \ + dma[dma_number].start_type = DMA_INACTIVE; \ + dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND; \ + address16(io_registers, (dma_number * 12) + 0xBA) = value; \ + } \ + + +#define access_register8_high(address) \ + value = (value << 8) | (address8(io_registers, address)) \ + +#define access_register8_low(address) \ + value = ((address8(io_registers, address + 1)) << 8) | value \ + +#define access_register16_high(address) \ + value = (value << 16) | (address16(io_registers, address)) \ + +#define access_register16_low(address) \ + value = ((address16(io_registers, address + 2)) << 16) | value \ + +cpu_alert_type function_cc write_io_register8(u32 address, u32 value) +{ + switch(address) + { + case 0x00: + { + u32 dispcnt = io_registers[REG_DISPCNT]; + + if((value & 0x07) != (dispcnt & 0x07)) + oam_update = 1; + + address8(io_registers, 0x00) = value; + break; + } + + // DISPSTAT (lower byte) + case 0x04: + address8(io_registers, 0x04) = + (address8(io_registers, 0x04) & 0x07) | (value & ~0x07); + break; + + // VCOUNT + case 0x06: + case 0x07: + break; + + // BG2 reference X + case 0x28: + access_register8_low(0x28); + access_register16_low(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + case 0x29: + access_register8_high(0x28); + access_register16_low(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + case 0x2A: + access_register8_low(0x2A); + access_register16_high(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + case 0x2B: + access_register8_high(0x2A); + access_register16_high(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + // BG2 reference Y + case 0x2C: + access_register8_low(0x2C); + access_register16_low(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + case 0x2D: + access_register8_high(0x2C); + access_register16_low(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + case 0x2E: + access_register8_low(0x2E); + access_register16_high(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + case 0x2F: + access_register8_high(0x2E); + access_register16_high(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + // BG3 reference X + case 0x38: + access_register8_low(0x38); + access_register16_low(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + case 0x39: + access_register8_high(0x38); + access_register16_low(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + case 0x3A: + access_register8_low(0x3A); + access_register16_high(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + case 0x3B: + access_register8_high(0x3A); + access_register16_high(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + // BG3 reference Y + case 0x3C: + access_register8_low(0x3C); + access_register16_low(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + case 0x3D: + access_register8_high(0x3C); + access_register16_low(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + case 0x3E: + access_register8_low(0x3E); + access_register16_high(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + case 0x3F: + access_register8_high(0x3E); + access_register16_high(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + // Sound 1 control sweep + case 0x60: + access_register8_low(0x60); + gbc_sound_tone_control_sweep(); + break; + + case 0x61: + access_register8_low(0x60); + gbc_sound_tone_control_sweep(); + break; + + // Sound 1 control duty/length/envelope + case 0x62: + access_register8_low(0x62); + gbc_sound_tone_control_low(0, 0x62); + break; + + case 0x63: + access_register8_high(0x62); + gbc_sound_tone_control_low(0, 0x62); + break; + + // Sound 1 control frequency + case 0x64: + access_register8_low(0x64); + gbc_sound_tone_control_high(0, 0x64); + break; + + case 0x65: + access_register8_high(0x64); + gbc_sound_tone_control_high(0, 0x64); + break; + + // Sound 2 control duty/length/envelope + case 0x68: + access_register8_low(0x68); + gbc_sound_tone_control_low(1, 0x68); + break; + + case 0x69: + access_register8_high(0x68); + gbc_sound_tone_control_low(1, 0x68); + break; + + // Sound 2 control frequency + case 0x6C: + access_register8_low(0x6C); + gbc_sound_tone_control_high(1, 0x6C); + break; + + case 0x6D: + access_register8_high(0x6C); + gbc_sound_tone_control_high(1, 0x6C); + break; + + // Sound 3 control wave + case 0x70: + access_register8_low(0x70); + gbc_sound_wave_control(); + break; + + case 0x71: + access_register8_high(0x70); + gbc_sound_wave_control(); + break; + + // Sound 3 control length/volume + case 0x72: + access_register8_low(0x72); + gbc_sound_tone_control_low_wave(); + break; + + case 0x73: + access_register8_high(0x72); + gbc_sound_tone_control_low_wave(); + break; + + // Sound 3 control frequency + case 0x74: + access_register8_low(0x74); + gbc_sound_tone_control_high_wave(); + break; + + case 0x75: + access_register8_high(0x74); + gbc_sound_tone_control_high_wave(); + break; + + // Sound 4 control length/envelope + case 0x78: + access_register8_low(0x78); + gbc_sound_tone_control_low(3, 0x78); + break; + + case 0x79: + access_register8_high(0x78); + gbc_sound_tone_control_low(3, 0x78); + break; + + // Sound 4 control frequency + case 0x7C: + access_register8_low(0x7C); + gbc_sound_noise_control(); + break; + + case 0x7D: + access_register8_high(0x7C); + gbc_sound_noise_control(); + break; + + // Sound control L + case 0x80: + access_register8_low(0x80); + gbc_trigger_sound(); + break; + + case 0x81: + access_register8_high(0x80); + gbc_trigger_sound(); + break; + + // Sound control H + case 0x82: + access_register8_low(0x82); + trigger_sound(); + break; + + case 0x83: + access_register8_high(0x82); + trigger_sound(); + break; + + // Sound control X + case 0x84: + sound_on(); + break; + + // Sound wave RAM + case 0x90 ... 0x9F: + gbc_sound_wave_update = 1; + address8(io_registers, address) = value; + break; + + // Sound FIFO A + case 0xA0: + sound_timer_queue8(0, value); + break; + + // Sound FIFO B + case 0xA4: + sound_timer_queue8(1, value); + break; + + // DMA control (trigger byte) + case 0xBB: + access_register8_low(0xBA); + trigger_dma(0); + break; + + case 0xC7: + access_register8_low(0xC6); + trigger_dma(1); + break; + + case 0xD3: + access_register8_low(0xD2); + trigger_dma(2); + break; + + case 0xDF: + access_register8_low(0xDE); + trigger_dma(3); + break; + + // Timer counts + case 0x100: + access_register8_low(0x100); + count_timer(0); + break; + + case 0x101: + access_register8_high(0x100); + count_timer(0); + break; + + case 0x104: + access_register8_low(0x104); + count_timer(1); + break; + + case 0x105: + access_register8_high(0x104); + count_timer(1); + break; + + case 0x108: + access_register8_low(0x108); + count_timer(2); + break; + + case 0x109: + access_register8_high(0x108); + count_timer(2); + break; + + case 0x10C: + access_register8_low(0x10C); + count_timer(3); + break; + + case 0x10D: + access_register8_high(0x10C); + count_timer(3); + break; + + // Timer control (trigger byte) + case 0x103: + access_register8_low(0x102); + trigger_timer(0); + break; + + case 0x107: + access_register8_low(0x106); + trigger_timer(1); + break; + + case 0x10B: + access_register8_low(0x10A); + trigger_timer(2); + break; + + case 0x10F: + access_register8_low(0x10E); + trigger_timer(3); + break; + + // IF + case 0x202: + address8(io_registers, 0x202) &= ~value; + break; + + case 0x203: + address8(io_registers, 0x203) &= ~value; + break; + + // Halt + case 0x301: + if((value & 0x01) == 0) + reg[CPU_HALT_STATE] = CPU_HALT; + else + reg[CPU_HALT_STATE] = CPU_STOP; + + return CPU_ALERT_HALT; + break; + + default: + address8(io_registers, address) = value; + break; + } + + return CPU_ALERT_NONE; +} + +cpu_alert_type function_cc write_io_register16(u32 address, u32 value) +{ + switch(address) + { + case 0x00: + { + u32 dispcnt = io_registers[REG_DISPCNT]; + if((value & 0x07) != (dispcnt & 0x07)) + oam_update = 1; + + address16(io_registers, 0x00) = value; + break; + } + + // DISPSTAT + case 0x04: + address16(io_registers, 0x04) = + (address16(io_registers, 0x04) & 0x07) | (value & ~0x07); + break; + + // VCOUNT + case 0x06: + break; + + // BG2 reference X + case 0x28: + access_register16_low(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + case 0x2A: + access_register16_high(0x28); + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + // BG2 reference Y + case 0x2C: + access_register16_low(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + case 0x2E: + access_register16_high(0x2C); + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + // BG3 reference X + + case 0x38: + access_register16_low(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + case 0x3A: + access_register16_high(0x38); + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + // BG3 reference Y + case 0x3C: + access_register16_low(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + case 0x3E: + access_register16_high(0x3C); + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + // Sound 1 control sweep + case 0x60: + gbc_sound_tone_control_sweep(); + break; + + // Sound 1 control duty/length/envelope + case 0x62: + gbc_sound_tone_control_low(0, 0x62); + break; + + // Sound 1 control frequency + case 0x64: + gbc_sound_tone_control_high(0, 0x64); + break; + + // Sound 2 control duty/length/envelope + case 0x68: + gbc_sound_tone_control_low(1, 0x68); + break; + + // Sound 2 control frequency + case 0x6C: + gbc_sound_tone_control_high(1, 0x6C); + break; + + // Sound 3 control wave + case 0x70: + gbc_sound_wave_control(); + break; + + // Sound 3 control length/volume + case 0x72: + gbc_sound_tone_control_low_wave(); + break; + + // Sound 3 control frequency + case 0x74: + gbc_sound_tone_control_high_wave(); + break; + + // Sound 4 control length/envelope + case 0x78: + gbc_sound_tone_control_low(3, 0x78); + break; + + // Sound 4 control frequency + case 0x7C: + gbc_sound_noise_control(); + break; + + // Sound control L + case 0x80: + gbc_trigger_sound(); + break; + + // Sound control H + case 0x82: + trigger_sound(); + break; + + // Sound control X + case 0x84: + sound_on(); + break; + + // Sound wave RAM + case 0x90 ... 0x9E: + gbc_sound_wave_update = 1; + address16(io_registers, address) = value; + break; + + // Sound FIFO A + case 0xA0: + sound_timer_queue16(0, value); + break; + + // Sound FIFO B + case 0xA4: + sound_timer_queue16(1, value); + break; + + // DMA control + case 0xBA: + trigger_dma(0); + break; + + case 0xC6: + trigger_dma(1); + break; + + case 0xD2: + trigger_dma(2); + break; + + case 0xDE: + trigger_dma(3); + break; + + // Timer counts + case 0x100: + count_timer(0); + break; + + case 0x104: + count_timer(1); + break; + + case 0x108: + count_timer(2); + break; + + case 0x10C: + count_timer(3); + break; + + // Timer control + case 0x102: + trigger_timer(0); + break; + + case 0x106: + trigger_timer(1); + break; + + case 0x10A: + trigger_timer(2); + break; + + case 0x10E: + trigger_timer(3); + break; + + // P1 + case 0x130: + break; + + // Interrupt flag + case 0x202: + address16(io_registers, 0x202) &= ~value; + break; + + // WAITCNT + case 0x204: + break; + + // Halt + case 0x300: + if(((value >> 8) & 0x01) == 0) + reg[CPU_HALT_STATE] = CPU_HALT; + else + reg[CPU_HALT_STATE] = CPU_STOP; + + return CPU_ALERT_HALT; + + default: + address16(io_registers, address) = value; + break; + } + + return CPU_ALERT_NONE; +} + + +cpu_alert_type function_cc write_io_register32(u32 address, u32 value) +{ + switch(address) + { + // BG2 reference X + case 0x28: + affine_reference_x[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x28) = value; + break; + + // BG2 reference Y + case 0x2C: + affine_reference_y[0] = (s32)(value << 4) >> 4; + address32(io_registers, 0x2C) = value; + break; + + // BG3 reference X + case 0x38: + affine_reference_x[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x38) = value; + break; + + // BG3 reference Y + case 0x3C: + affine_reference_y[1] = (s32)(value << 4) >> 4; + address32(io_registers, 0x3C) = value; + break; + + // Sound FIFO A + case 0xA0: + sound_timer_queue32(0, value); + break; + + // Sound FIFO B + case 0xA4: + sound_timer_queue32(1, value); + break; + + default: + { + cpu_alert_type alert_low = + write_io_register16(address, value & 0xFFFF); + + cpu_alert_type alert_high = + write_io_register16(address + 2, value >> 16); + + if(alert_high) + return alert_high; + + return alert_low; + } + } + + return CPU_ALERT_NONE; +} + +#define write_palette8(address, value) \ + +#define write_palette16(address, value) \ +{ \ + u32 palette_address = address; \ + address16(palette_ram, palette_address) = value; \ + convert_palette(value); \ + address16(palette_ram_converted, palette_address) = value; \ +} \ + +#define write_palette32(address, value) \ +{ \ + u32 palette_address = address; \ + u32 value_high = value >> 16; \ + u32 value_low = value & 0xFFFF; \ + address32(palette_ram, palette_address) = value; \ + convert_palette(value_high); \ + convert_palette(value_low); \ + value = (value_high << 16) | value_low; \ + address32(palette_ram_converted, palette_address) = value; \ +} \ + + +void function_cc write_backup(u32 address, u32 value) +{ + value &= 0xFF; + + if(backup_type == BACKUP_NONE) + backup_type = BACKUP_SRAM; + + + // gamepak SRAM or Flash ROM + if((address == 0x5555) && (flash_mode != FLASH_WRITE_MODE)) + { + if((flash_command_position == 0) && (value == 0xAA)) + { + backup_type = BACKUP_FLASH; + flash_command_position = 1; + } + + if(flash_command_position == 2) + { + switch(value) + { + case 0x90: + // Enter ID mode, this also tells the emulator that we're using + // flash, not SRAM + + if(flash_mode == FLASH_BASE_MODE) + flash_mode = FLASH_ID_MODE; + + break; + + case 0x80: + // Enter erase mode + if(flash_mode == FLASH_BASE_MODE) + flash_mode = FLASH_ERASE_MODE; + break; + + case 0xF0: + // Terminate ID mode + if(flash_mode == FLASH_ID_MODE) + flash_mode = FLASH_BASE_MODE; + break; + + case 0xA0: + // Write mode + if(flash_mode == FLASH_BASE_MODE) + flash_mode = FLASH_WRITE_MODE; + break; + + case 0xB0: + // Bank switch + // Here the chip is now officially 128KB. + flash_size = FLASH_SIZE_128KB; + if(flash_mode == FLASH_BASE_MODE) + flash_mode = FLASH_BANKSWITCH_MODE; + break; + + case 0x10: + // Erase chip + if(flash_mode == FLASH_ERASE_MODE) + { + if(flash_size == FLASH_SIZE_64KB) + memset(gamepak_backup, 0xFF, 1024 * 64); + else + memset(gamepak_backup, 0xFF, 1024 * 128); + backup_update = write_backup_delay; + flash_mode = FLASH_BASE_MODE; + } + break; + + default: + break; + } + flash_command_position = 0; + } + if(backup_type == BACKUP_SRAM) + gamepak_backup[0x5555] = value; + } + else + + if((address == 0x2AAA) && (value == 0x55) && + (flash_command_position == 1)) + { + flash_command_position = 2; + } + else + { + if((flash_command_position == 2) && + (flash_mode == FLASH_ERASE_MODE) && (value == 0x30)) + { + // Erase sector + memset(flash_bank_ptr + (address & 0xF000), 0xFF, 1024 * 4); + backup_update = write_backup_delay; + flash_mode = FLASH_BASE_MODE; + flash_command_position = 0; + } + else + + if((flash_command_position == 0) && + (flash_mode == FLASH_BANKSWITCH_MODE) && (address == 0x0000) && + (flash_size == FLASH_SIZE_128KB)) + { + flash_bank_ptr = gamepak_backup + ((value & 0x01) * (1024 * 64)); + flash_mode = FLASH_BASE_MODE; + } + else + + if((flash_command_position == 0) && (flash_mode == FLASH_WRITE_MODE)) + { + // Write value to flash ROM + backup_update = write_backup_delay; + flash_bank_ptr[address] = value; + flash_mode = FLASH_BASE_MODE; + } + else + + if(backup_type == BACKUP_SRAM) + { + // Write value to SRAM + backup_update = write_backup_delay; + // Hit 64KB territory? + if(address >= 0x8000) + sram_size = SRAM_SIZE_64KB; + gamepak_backup[address] = value; + } + } +} + +#define write_backup8() \ + write_backup(address & 0xFFFF, value) \ + +#define write_backup16() \ + +#define write_backup32() \ + +#define write_vram8() \ + address &= ~0x01; \ + address16(vram, address) = ((value << 8) | value) \ + +#define write_vram16() \ + address16(vram, address) = value \ + +#define write_vram32() \ + address32(vram, address) = value \ + +// RTC code derived from VBA's (due to lack of any real publically available +// documentation...) + +typedef enum +{ + RTC_DISABLED, + RTC_IDLE, + RTC_COMMAND, + RTC_OUTPUT_DATA, + RTC_INPUT_DATA +} rtc_state_type; + +typedef enum +{ + RTC_COMMAND_RESET = 0x60, + RTC_COMMAND_WRITE_STATUS = 0x62, + RTC_COMMAND_READ_STATUS = 0x63, + RTC_COMMAND_OUTPUT_TIME_FULL = 0x65, + RTC_COMMAND_OUTPUT_TIME = 0x67 +} rtc_command_type; + +typedef enum +{ + RTC_WRITE_TIME, + RTC_WRITE_TIME_FULL, + RTC_WRITE_STATUS +} rtc_write_mode_type; + +rtc_state_type rtc_state = RTC_DISABLED; +rtc_write_mode_type rtc_write_mode; +u8 rtc_registers[3]; +u32 rtc_command; +u32 rtc_data[12]; +u32 rtc_status = 0x40; +u32 rtc_data_bytes; +s32 rtc_bit_count; + +u32 encode_bcd(u8 value) +{ + return ((value / 10) << 4) | (value % 10); +} + +#define write_rtc_register(index, _value) \ + update_address = 0x80000C4 + (index * 2); \ + rtc_registers[index] = _value; \ + rtc_page_index = update_address >> 15; \ + map = memory_map_read[rtc_page_index]; \ + \ + if(map == NULL) \ + map = load_gamepak_page(rtc_page_index & 0x3FF); \ + \ + address16(map, update_address & 0x7FFF) = _value \ + +void function_cc write_rtc(u32 address, u32 value) +{ + u32 rtc_page_index; + u32 update_address; + u8 *map; + + value &= 0xFFFF; + + switch(address) + { + // RTC command + // Bit 0: SCHK, perform action + // Bit 1: IO, input/output command data + // Bit 2: CS, select input/output? If high make I/O write only + case 0xC4: + if(rtc_state == RTC_DISABLED) + rtc_state = RTC_IDLE; + if(!(rtc_registers[0] & 0x04)) + value = (rtc_registers[0] & 0x02) | (value & ~0x02); + if(rtc_registers[2] & 0x01) + { + // To begin writing a command 1, 5 must be written to the command + // registers. + if((rtc_state == RTC_IDLE) && (rtc_registers[0] == 0x01) && + (value == 0x05)) + { + // We're now ready to begin receiving a command. + write_rtc_register(0, value); + rtc_state = RTC_COMMAND; + rtc_command = 0; + rtc_bit_count = 7; + } + else + { + write_rtc_register(0, value); + switch(rtc_state) + { + // Accumulate RTC command by receiving the next bit, and if we + // have accumulated enough bits to form a complete command + // execute it. + case RTC_COMMAND: + if(rtc_registers[0] & 0x01) + { + rtc_command |= ((value & 0x02) >> 1) << rtc_bit_count; + rtc_bit_count--; + } + + // Have we received a full RTC command? If so execute it. + if(rtc_bit_count < 0) + { + switch(rtc_command) + { + // Resets RTC + case RTC_COMMAND_RESET: + rtc_state = RTC_IDLE; + memset(rtc_registers, 0, sizeof(rtc_registers)); + break; + + // Sets status of RTC + case RTC_COMMAND_WRITE_STATUS: + rtc_state = RTC_INPUT_DATA; + rtc_data_bytes = 1; + rtc_write_mode = RTC_WRITE_STATUS; + break; + + // Outputs current status of RTC + case RTC_COMMAND_READ_STATUS: + rtc_state = RTC_OUTPUT_DATA; + rtc_data_bytes = 1; + rtc_data[0] = rtc_status; + break; + + // Actually outputs the time, all of it + case RTC_COMMAND_OUTPUT_TIME_FULL: + { + struct tm *current_time; + time_t current_time_flat; + u32 day_of_week; + + time(¤t_time_flat); + current_time = localtime(¤t_time_flat); + + day_of_week = current_time->tm_wday; + if(day_of_week == 0) + day_of_week = 6; + else + day_of_week--; + + rtc_state = RTC_OUTPUT_DATA; + rtc_data_bytes = 7; + rtc_data[0] = encode_bcd(current_time->tm_year % 100); + rtc_data[1] = encode_bcd(current_time->tm_mon + 1); + rtc_data[2] = encode_bcd(current_time->tm_mday); + rtc_data[3] = encode_bcd(day_of_week); + rtc_data[4] = encode_bcd(current_time->tm_hour); + rtc_data[5] = encode_bcd(current_time->tm_min); + rtc_data[6] = encode_bcd(current_time->tm_sec); + + break; + } + + // Only outputs the current time of day. + case RTC_COMMAND_OUTPUT_TIME: + { + struct tm *current_time; + time_t current_time_flat; + + time(¤t_time_flat); + current_time = localtime(¤t_time_flat); + + rtc_state = RTC_OUTPUT_DATA; + rtc_data_bytes = 3; + rtc_data[0] = encode_bcd(current_time->tm_hour); + rtc_data[1] = encode_bcd(current_time->tm_min); + rtc_data[2] = encode_bcd(current_time->tm_sec); + break; + } + } + rtc_bit_count = 0; + } + break; + + // Receive parameters from the game as input to the RTC + // for a given command. Read one bit at a time. + case RTC_INPUT_DATA: + // Bit 1 of parameter A must be high for input + if(rtc_registers[1] & 0x02) + { + // Read next bit for input + if(!(value & 0x01)) + { + rtc_data[rtc_bit_count >> 3] |= + ((value & 0x01) << (7 - (rtc_bit_count & 0x07))); + } + else + { + rtc_bit_count++; + + if(rtc_bit_count == (rtc_data_bytes * 8)) + { + rtc_state = RTC_IDLE; + switch(rtc_write_mode) + { + case RTC_WRITE_STATUS: + rtc_status = rtc_data[0]; + break; + } + } + } + } + break; + + case RTC_OUTPUT_DATA: + // Bit 1 of parameter A must be low for output + if(!(rtc_registers[1] & 0x02)) + { + // Write next bit to output, on bit 1 of parameter B + if(!(value & 0x01)) + { + u8 current_output_byte = rtc_registers[2]; + + current_output_byte = + (current_output_byte & ~0x02) | + (((rtc_data[rtc_bit_count >> 3] >> + (rtc_bit_count & 0x07)) & 0x01) << 1); + + write_rtc_register(0, current_output_byte); + + } + else + { + rtc_bit_count++; + + if(rtc_bit_count == (rtc_data_bytes * 8)) + { + rtc_state = RTC_IDLE; + memset(rtc_registers, 0, sizeof(rtc_registers)); + } + } + } + break; + } + } + } + else + { + write_rtc_register(2, value); + } + break; + + // Write parameter A + case 0xC6: + write_rtc_register(1, value); + break; + + // Write parameter B + case 0xC8: + write_rtc_register(2, value); + break; + } +} + +#define write_rtc8() \ + +#define write_rtc16() \ + write_rtc(address & 0xFF, value) \ + +#define write_rtc32() \ + +#define write_memory(type) \ + switch(address >> 24) \ + { \ + case 0x02: \ + /* external work RAM */ \ + address = (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000; \ + address##type(ewram, address) = value; \ + break; \ + \ + case 0x03: \ + /* internal work RAM */ \ + address##type(iwram, (address & 0x7FFF) + 0x8000) = value; \ + break; \ + \ + case 0x04: \ + /* I/O registers */ \ + return write_io_register##type(address & 0x3FF, value); \ + \ + case 0x05: \ + /* palette RAM */ \ + write_palette##type(address & 0x3FF, value); \ + break; \ + \ + case 0x06: \ + /* VRAM */ \ + address &= 0x1FFFF; \ + if(address >= 0x18000) \ + address -= 0x8000; \ + \ + write_vram##type(); \ + break; \ + \ + case 0x07: \ + /* OAM RAM */ \ + oam_update = 1; \ + address##type(oam_ram, address & 0x3FF) = value; \ + break; \ + \ + case 0x08: \ + /* gamepak ROM or RTC */ \ + write_rtc##type(); \ + break; \ + \ + case 0x09 ... 0x0C: \ + /* gamepak ROM space */ \ + break; \ + \ + case 0x0D: \ + write_eeprom(address, value); \ + break; \ + \ + case 0x0E: \ + write_backup##type(); \ + break; \ + } \ + +u8 function_cc read_memory8(u32 address) +{ + u8 value; + read_memory(8); + return value; +} + +u16 function_cc read_memory16_signed(u32 address) +{ + u16 value; + + if(address & 0x01) + { + return (s8)read_memory8(address); + } + else + { + read_memory(16); + } + + return value; +} + +// unaligned reads are actually 32bit + +u32 function_cc read_memory16(u32 address) +{ + u32 value; + + if(address & 0x01) + { + address &= ~0x01; + read_memory(16); + ror(value, value, 8); + } + else + { + read_memory(16); + } + + return value; +} + + +u32 function_cc read_memory32(u32 address) +{ + u32 value; + if(address & 0x03) + { + u32 rotate = (address & 0x03) * 8; + address &= ~0x03; + read_memory(32); + ror(value, value, rotate); + } + else + { + read_memory(32); + } + + return value; +} + +cpu_alert_type function_cc write_memory8(u32 address, u8 value) +{ + write_memory(8); + return CPU_ALERT_NONE; +} + +cpu_alert_type function_cc write_memory16(u32 address, u16 value) +{ + write_memory(16); + return CPU_ALERT_NONE; +} + +cpu_alert_type function_cc write_memory32(u32 address, u32 value) +{ + write_memory(32); + return CPU_ALERT_NONE; +} + +char backup_filename[512]; + +u32 load_backup(char *name) +{ + file_open(backup_file, name, read); + + if(file_check_valid(backup_file)) + { + u32 backup_size = file_length(name, backup_file); + + file_read(backup_file, gamepak_backup, backup_size); + + file_close(backup_file); + + // The size might give away what kind of backup it is. + switch(backup_size) + { + case 0x200: + backup_type = BACKUP_EEPROM; + eeprom_size = EEPROM_512_BYTE; + break; + + case 0x2000: + backup_type = BACKUP_EEPROM; + eeprom_size = EEPROM_8_KBYTE; + break; + + case 0x8000: + backup_type = BACKUP_SRAM; + sram_size = SRAM_SIZE_32KB; + break; + + // Could be either flash or SRAM, go with flash + case 0x10000: + backup_type = BACKUP_FLASH; + sram_size = FLASH_SIZE_64KB; + break; + + case 0x20000: + backup_type = BACKUP_FLASH; + flash_size = FLASH_SIZE_128KB; + break; + } + return 1; + } + else + { + backup_type = BACKUP_NONE; + memset(gamepak_backup, 0xFF, 1024 * 128); + } + + return 0; +} + +u32 save_backup(char *name) +{ + if(backup_type != BACKUP_NONE) + { + file_open(backup_file, name, write); + + if(file_check_valid(backup_file)) + { + u32 backup_size; + + switch(backup_type) + { + case BACKUP_SRAM: + if(sram_size == SRAM_SIZE_32KB) + backup_size = 0x8000; + else + backup_size = 0x10000; + break; + + case BACKUP_FLASH: + if(flash_size == FLASH_SIZE_64KB) + backup_size = 0x10000; + else + backup_size = 0x20000; + break; + + case BACKUP_EEPROM: + if(eeprom_size == EEPROM_512_BYTE) + backup_size = 0x200; + else + backup_size = 0x2000; + break; + } + + file_write(backup_file, gamepak_backup, backup_size); + + file_close(backup_file); + return 1; + } + } + + return 0; +} + +void update_backup() +{ + if(backup_update != (write_backup_delay + 1)) + backup_update--; + + if(backup_update == 0) + { + save_backup(backup_filename); + backup_update = write_backup_delay + 1; + } +} + +void update_backup_force() +{ + save_backup(backup_filename); +} + +#define CONFIG_FILENAME "game_config.txt" + +u8 *skip_spaces(u8 *line_ptr) +{ + while(*line_ptr == ' ') + line_ptr++; + + return line_ptr; +} + +s32 parse_config_line(u8 *current_line, u8 *current_variable, u8 *current_value) +{ + u8 *line_ptr = current_line; + u8 *line_ptr_new; + + if((current_line[0] == 0) || (current_line[0] == '#')) + return -1; + + line_ptr_new = strchr(line_ptr, ' '); + if(line_ptr_new == NULL) + return -1; + + *line_ptr_new = 0; + strcpy(current_variable, line_ptr); + line_ptr_new = skip_spaces(line_ptr_new + 1); + + if(*line_ptr_new != '=') + return -1; + + line_ptr_new = skip_spaces(line_ptr_new + 1); + strcpy(current_value, line_ptr_new); + line_ptr_new = current_value + strlen(current_value) - 1; + if(*line_ptr_new == '\n') + { + line_ptr_new--; + *line_ptr_new = 0; + } + + if(*line_ptr_new == '\r') + *line_ptr_new = 0; + + return 0; +} + +s32 load_game_config(u8 *gamepak_title, u8 *gamepak_code, u8 *gamepak_maker) +{ + u8 current_line[256]; + u8 current_variable[256]; + u8 current_value[256]; + u8 config_path[512]; + u8 *line_ptr; + u32 fgets_value; + FILE *config_file; + + idle_loop_target_pc = 0xFFFFFFFF; + iwram_stack_optimize = 1; + bios_rom[0x39] = 0x00; + bios_rom[0x2C] = 0x00; + translation_gate_targets = 0; + flash_device_id = FLASH_DEVICE_MACRONIX_64KB; + +#if (defined(PSP_BUILD) || defined(ARM_ARCH)) && !defined(_WIN32_WCE) + sprintf(config_path, "%s/%s", main_path, CONFIG_FILENAME); +#else + sprintf(config_path, "%s\\%s", main_path, CONFIG_FILENAME); +#endif + + config_file = fopen(config_path, "rb"); + + if(config_file) + { + while(fgets(current_line, 256, config_file)) + { + if(parse_config_line(current_line, current_variable, current_value) + != -1) + { + if(strcmp(current_variable, "game_name") || + strcmp(current_value, gamepak_title)) + continue; + + if(!fgets(current_line, 256, config_file) || + (parse_config_line(current_line, current_variable, + current_value) == -1) || + strcmp(current_variable, "game_code") || + strcmp(current_value, gamepak_code)) + continue; + + if(!fgets(current_line, 256, config_file) || + (parse_config_line(current_line, current_variable, + current_value) == -1) || + strcmp(current_variable, "vender_code") || + strcmp(current_value, gamepak_maker)) + continue; + + while(fgets(current_line, 256, config_file)) + { + if(parse_config_line(current_line, current_variable, current_value) + != -1) + { + if(!strcmp(current_variable, "game_name")) + { + fclose(config_file); + return 0; + } + + if(!strcmp(current_variable, "idle_loop_eliminate_target")) + idle_loop_target_pc = strtol(current_value, NULL, 16); + + if(!strcmp(current_variable, "translation_gate_target")) + { + if(translation_gate_targets < MAX_TRANSLATION_GATES) + { + translation_gate_target_pc[translation_gate_targets] = + strtol(current_value, NULL, 16); + translation_gate_targets++; + } + } + + if(!strcmp(current_variable, "iwram_stack_optimize") && + !strcmp(current_value, "no")) + { + iwram_stack_optimize = 0; + } + + if(!strcmp(current_variable, "flash_rom_type") && + !strcmp(current_value, "128KB")) + { + flash_device_id = FLASH_DEVICE_MACRONIX_128KB; + } + + if(!strcmp(current_variable, "bios_rom_hack_39") && + !strcmp(current_value, "yes")) + { + bios_rom[0x39] = 0xC0; + } + + if(!strcmp(current_variable, "bios_rom_hack_2C") && + !strcmp(current_value, "yes")) + { + bios_rom[0x2C] = 0x02; + } + } + } + + fclose(config_file); + return 0; + } + } + + fclose(config_file); + } + + return -1; +} + +s32 load_gamepak_raw(char *name) +{ + file_open(gamepak_file, name, read); + + if(file_check_valid(gamepak_file)) + { + u32 file_size = file_length(name, gamepak_file); + + // First, close the last one if it was open, we won't + // be needing it anymore. + if(file_check_valid(gamepak_file_large)) + file_close(gamepak_file_large); + + // If it's a big file size keep it, don't close it, we'll + // probably want to load from it more later. + if(file_size <= gamepak_ram_buffer_size) + { + file_read(gamepak_file, gamepak_rom, file_size); + + file_close(gamepak_file); + +#ifdef PSP_BUILD + gamepak_file_large = -1; +#else + gamepak_file_large = NULL; +#endif + } + else + { + // Read in just enough for the header + file_read(gamepak_file, gamepak_rom, 0x100); + gamepak_file_large = gamepak_file; + } + + return file_size; + } + + return -1; +} + +u8 gamepak_title[13]; +u8 gamepak_code[5]; +u8 gamepak_maker[3]; +u8 gamepak_filename[512]; + +u32 load_gamepak(char *name) +{ + char *dot_position = strrchr(name, '.'); + s32 file_size; + u8 cheats_filename[256]; + + if(!strcmp(dot_position, ".zip")) + file_size = load_file_zip(name); + else + file_size = load_gamepak_raw(name); + + // A dumb April fool's joke was here once :o + + if(file_size != -1) + { + gamepak_size = (file_size + 0x7FFF) & ~0x7FFF; + + strcpy(backup_filename, name); + strncpy(gamepak_filename, name, 512); + change_ext(gamepak_filename, backup_filename, ".sav"); + + load_backup(backup_filename); + + memcpy(gamepak_title, gamepak_rom + 0xA0, 12); + memcpy(gamepak_code, gamepak_rom + 0xAC, 4); + memcpy(gamepak_maker, gamepak_rom + 0xB0, 2); + gamepak_title[12] = 0; + gamepak_code[4] = 0; + gamepak_maker[2] = 0; + + load_game_config(gamepak_title, gamepak_code, gamepak_maker); + load_game_config_file(); + + change_ext(gamepak_filename, cheats_filename, ".cht"); + add_cheats(cheats_filename); + + return 0; + } + + return -1; +} + +s32 load_bios(char *name) +{ + file_open(bios_file, name, read); + + if(file_check_valid(bios_file)) + { + file_read(bios_file, bios_rom, 0x4000); + + // This is a hack to get Zelda working, because emulating + // the proper memory read behavior here is much too expensive. + file_close(bios_file); + return 0; + } + + return -1; +} + +// DMA memory regions can be one of the following: +// IWRAM - 32kb offset from the contiguous iwram region. +// EWRAM - like segmented but with self modifying code check. +// VRAM - 96kb offset from the contiguous vram region, should take care +// Palette RAM - Converts palette entries when written to. +// OAM RAM - Sets OAM modified flag to true. +// I/O registers - Uses the I/O register function. +// of mirroring properly. +// Segmented RAM/ROM - a region >= 32kb, the translated address has to +// be reloaded if it wraps around the limit (cartride ROM) +// Ext - should be handled by the memory read/write function. + +// The following map determines the region of each (assumes DMA access +// is not done out of bounds) + +typedef enum +{ + DMA_REGION_IWRAM, + DMA_REGION_EWRAM, + DMA_REGION_VRAM, + DMA_REGION_PALETTE_RAM, + DMA_REGION_OAM_RAM, + DMA_REGION_IO, + DMA_REGION_GAMEPAK, + DMA_REGION_EXT, + DMA_REGION_BIOS, + DMA_REGION_NULL +} dma_region_type; + +dma_region_type dma_region_map[16] = +{ + DMA_REGION_BIOS, // 0x00 - BIOS + DMA_REGION_NULL, // 0x01 - Nothing + DMA_REGION_EWRAM, // 0x02 - EWRAM + DMA_REGION_IWRAM, // 0x03 - IWRAM + DMA_REGION_IO, // 0x04 - I/O registers + DMA_REGION_PALETTE_RAM, // 0x05 - palette RAM + DMA_REGION_VRAM, // 0x06 - VRAM + DMA_REGION_OAM_RAM, // 0x07 - OAM RAM + DMA_REGION_GAMEPAK, // 0x08 - gamepak ROM + DMA_REGION_GAMEPAK, // 0x09 - gamepak ROM + DMA_REGION_GAMEPAK, // 0x0A - gamepak ROM + DMA_REGION_GAMEPAK, // 0x0B - gamepak ROM + DMA_REGION_GAMEPAK, // 0x0C - gamepak ROM + DMA_REGION_EXT, // 0x0D - EEPROM + DMA_REGION_EXT, // 0x0E - gamepak SRAM/flash ROM + DMA_REGION_EXT // 0x0F - gamepak SRAM/flash ROM +}; + +#define dma_adjust_ptr_inc(ptr, size) \ + ptr += (size / 8) \ + +#define dma_adjust_ptr_dec(ptr, size) \ + ptr -= (size / 8) \ + +#define dma_adjust_ptr_fix(ptr, size) \ + +#define dma_adjust_ptr_writeback() \ + dma->dest_address = dest_ptr \ + +#define dma_adjust_ptr_reload() \ + +#define dma_print(src_op, dest_op, transfer_size, wb) \ + printf("dma from %x (%s) to %x (%s) for %x (%s) (%s) (%d) (pc %x)\n", \ + src_ptr, #src_op, dest_ptr, #dest_op, length, #transfer_size, #wb, \ + dma->irq, reg[15]); \ + +#define dma_smc_vars_src() \ + +#define dma_smc_vars_dest() \ + u32 smc_trigger = 0 \ + +#define dma_vars_iwram(type) \ + dma_smc_vars_##type() \ + +#define dma_vars_vram(type) \ + +#define dma_vars_palette_ram(type) \ + +#define dma_oam_ram_src() \ + +#define dma_oam_ram_dest() \ + oam_update = 1 \ + +#define dma_vars_oam_ram(type) \ + dma_oam_ram_##type() \ + +#define dma_vars_io(type) \ + +#define dma_segmented_load_src() \ + memory_map_read[src_current_region] \ + +#define dma_segmented_load_dest() \ + memory_map_write[dest_current_region] \ + +#define dma_vars_gamepak(type) \ + u32 type##_new_region; \ + u32 type##_current_region = type##_ptr >> 15; \ + u8 *type##_address_block = dma_segmented_load_##type(); \ + if(type##_address_block == NULL) \ + { \ + if((type##_ptr & 0x1FFFFFF) >= gamepak_size) \ + break; \ + type##_address_block = load_gamepak_page(type##_current_region & 0x3FF); \ + } \ + +#define dma_vars_ewram(type) \ + dma_smc_vars_##type(); \ + u32 type##_new_region; \ + u32 type##_current_region = type##_ptr >> 15; \ + u8 *type##_address_block = dma_segmented_load_##type() \ + +#define dma_vars_bios(type) \ + +#define dma_vars_ext(type) \ + +#define dma_ewram_check_region(type) \ + type##_new_region = (type##_ptr >> 15); \ + if(type##_new_region != type##_current_region) \ + { \ + type##_current_region = type##_new_region; \ + type##_address_block = dma_segmented_load_##type(); \ + } \ + +#define dma_gamepak_check_region(type) \ + type##_new_region = (type##_ptr >> 15); \ + if(type##_new_region != type##_current_region) \ + { \ + type##_current_region = type##_new_region; \ + type##_address_block = dma_segmented_load_##type(); \ + if(type##_address_block == NULL) \ + { \ + type##_address_block = \ + load_gamepak_page(type##_current_region & 0x3FF); \ + } \ + } \ + +#define dma_read_iwram(type, transfer_size) \ + read_value = address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) \ + +#define dma_read_vram(type, transfer_size) \ + read_value = address##transfer_size(vram, type##_ptr & 0x1FFFF) \ + +#define dma_read_io(type, transfer_size) \ + read_value = address##transfer_size(io_registers, type##_ptr & 0x7FFF) \ + +#define dma_read_oam_ram(type, transfer_size) \ + read_value = address##transfer_size(oam_ram, type##_ptr & 0x3FF) \ + +#define dma_read_palette_ram(type, transfer_size) \ + read_value = address##transfer_size(palette_ram, type##_ptr & 0x3FF) \ + +#define dma_read_ewram(type, transfer_size) \ + dma_ewram_check_region(type); \ + read_value = address##transfer_size(type##_address_block, \ + type##_ptr & 0x7FFF) \ + +#define dma_read_gamepak(type, transfer_size) \ + dma_gamepak_check_region(type); \ + read_value = address##transfer_size(type##_address_block, \ + type##_ptr & 0x7FFF) \ + +// DMAing from the BIOS is funny, just returns 0.. + +#define dma_read_bios(type, transfer_size) \ + read_value = 0 \ + +#define dma_read_ext(type, transfer_size) \ + read_value = read_memory##transfer_size(type##_ptr) \ + +#define dma_write_iwram(type, transfer_size) \ + address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = read_value; \ + smc_trigger |= address##transfer_size(iwram, type##_ptr & 0x7FFF) \ + +#define dma_write_vram(type, transfer_size) \ + address##transfer_size(vram, type##_ptr & 0x1FFFF) = read_value \ + +#define dma_write_io(type, transfer_size) \ + write_io_register##transfer_size(type##_ptr & 0x3FF, read_value) \ + +#define dma_write_oam_ram(type, transfer_size) \ + address##transfer_size(oam_ram, type##_ptr & 0x3FF) = read_value \ + +#define dma_write_palette_ram(type, transfer_size) \ + write_palette##transfer_size(type##_ptr & 0x3FF, read_value) \ + +#define dma_write_ext(type, transfer_size) \ + write_memory##transfer_size(type##_ptr, read_value) \ + +#define dma_write_ewram(type, transfer_size) \ + dma_ewram_check_region(type); \ + \ + address##transfer_size(type##_address_block, type##_ptr & 0x7FFF) = \ + read_value; \ + smc_trigger |= address##transfer_size(type##_address_block, \ + (type##_ptr & 0x7FFF) - 0x8000) \ + +#define dma_epilogue_iwram() \ + if(smc_trigger) \ + { \ + /* Special return code indicating to retranslate to the CPU code */ \ + return_value = CPU_ALERT_SMC; \ + } \ + +#define dma_epilogue_ewram() \ + if(smc_trigger) \ + { \ + /* Special return code indicating to retranslate to the CPU code */ \ + return_value = CPU_ALERT_SMC; \ + } \ + +#define dma_epilogue_vram() \ + +#define dma_epilogue_io() \ + +#define dma_epilogue_oam_ram() \ + +#define dma_epilogue_palette_ram() \ + +#define dma_epilogue_GAMEPAK() \ + +#define dma_epilogue_ext() \ + +#define print_line() \ + dma_print(src_op, dest_op, transfer_size, wb); \ + +#define dma_transfer_loop_region(src_region_type, dest_region_type, src_op, \ + dest_op, transfer_size, wb) \ +{ \ + dma_vars_##src_region_type(src); \ + dma_vars_##dest_region_type(dest); \ + \ + for(i = 0; i < length; i++) \ + { \ + dma_read_##src_region_type(src, transfer_size); \ + dma_write_##dest_region_type(dest, transfer_size); \ + dma_adjust_ptr_##src_op(src_ptr, transfer_size); \ + dma_adjust_ptr_##dest_op(dest_ptr, transfer_size); \ + } \ + dma->source_address = src_ptr; \ + dma_adjust_ptr_##wb(); \ + dma_epilogue_##dest_region_type(); \ + break; \ +} \ + +#define dma_transfer_loop(src_op, dest_op, transfer_size, wb); \ +{ \ + u32 src_region = src_ptr >> 24; \ + u32 dest_region = dest_ptr >> 24; \ + dma_region_type src_region_type = dma_region_map[src_region]; \ + dma_region_type dest_region_type = dma_region_map[dest_region]; \ + \ + switch(src_region_type | (dest_region_type << 4)) \ + { \ + case (DMA_REGION_BIOS | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(bios, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(iwram, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(ewram, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(vram, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(palette_ram, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(oam_ram, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(io, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(gamepak, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_IWRAM << 4)): \ + dma_transfer_loop_region(ext, iwram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(bios, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(iwram, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(ewram, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(vram, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(palette_ram, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(oam_ram, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(io, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(gamepak, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_EWRAM << 4)): \ + dma_transfer_loop_region(ext, ewram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(bios, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(iwram, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(ewram, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(vram, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(palette_ram, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(oam_ram, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(io, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(gamepak, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_VRAM << 4)): \ + dma_transfer_loop_region(ext, vram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(bios, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(iwram, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(ewram, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(vram, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(palette_ram, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(oam_ram, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(io, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(gamepak, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_PALETTE_RAM << 4)): \ + dma_transfer_loop_region(ext, palette_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(bios, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(iwram, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(ewram, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(vram, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(palette_ram, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(oam_ram, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(io, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(gamepak, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_OAM_RAM << 4)): \ + dma_transfer_loop_region(ext, oam_ram, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(bios, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(iwram, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(ewram, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(vram, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(palette_ram, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(oam_ram, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(io, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(gamepak, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_IO << 4)): \ + dma_transfer_loop_region(ext, io, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_BIOS | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(bios, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IWRAM | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(iwram, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EWRAM | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(ewram, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_VRAM | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(vram, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_PALETTE_RAM | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(palette_ram, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_OAM_RAM | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(oam_ram, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_IO | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(io, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_GAMEPAK | (DMA_REGION_EXT << 4)): \ + dma_transfer_loop_region(gamepak, ext, src_op, dest_op, \ + transfer_size, wb); \ + \ + case (DMA_REGION_EXT | (DMA_REGION_EXT << 3)): \ + dma_transfer_loop_region(ext, ext, src_op, dest_op, \ + transfer_size, wb); \ + } \ + break; \ +} \ + +#define dma_transfer_expand(transfer_size) \ + switch((dma->dest_direction << 2) | dma->source_direction) \ + { \ + case 0x00: \ + dma_transfer_loop(inc, inc, transfer_size, writeback); \ + \ + case 0x01: \ + dma_transfer_loop(dec, inc, transfer_size, writeback); \ + \ + case 0x02: \ + dma_transfer_loop(fix, inc, transfer_size, writeback); \ + \ + case 0x03: \ + break; \ + \ + case 0x04: \ + dma_transfer_loop(inc, dec, transfer_size, writeback); \ + \ + case 0x05: \ + dma_transfer_loop(dec, dec, transfer_size, writeback); \ + \ + case 0x06: \ + dma_transfer_loop(fix, dec, transfer_size, writeback); \ + \ + case 0x07: \ + break; \ + \ + case 0x08: \ + dma_transfer_loop(inc, fix, transfer_size, writeback); \ + \ + case 0x09: \ + dma_transfer_loop(dec, fix, transfer_size, writeback); \ + \ + case 0x0A: \ + dma_transfer_loop(fix, fix, transfer_size, writeback); \ + \ + case 0x0B: \ + break; \ + \ + case 0x0C: \ + dma_transfer_loop(inc, inc, transfer_size, reload); \ + \ + case 0x0D: \ + dma_transfer_loop(dec, inc, transfer_size, reload); \ + \ + case 0x0E: \ + dma_transfer_loop(fix, inc, transfer_size, reload); \ + \ + case 0x0F: \ + break; \ + } \ + +cpu_alert_type dma_transfer(dma_transfer_type *dma) +{ + u32 i; + u32 length = dma->length; + u32 read_value; + u32 src_ptr = dma->source_address; + u32 dest_ptr = dma->dest_address; + cpu_alert_type return_value = CPU_ALERT_NONE; + + // Technically this should be done for source and destination, but + // chances are this is only ever used (probably mistakingly!) for dest. + // The only game I know of that requires this is Lucky Luke. + if((dest_ptr >> 24) != ((dest_ptr + length - 1) >> 24)) + { + u32 first_length = ((dest_ptr & 0xFF000000) + 0x1000000) - dest_ptr; + u32 second_length = length - first_length; + dma->length = first_length; + + dma_transfer(dma); + + dma->length = length; + + length = second_length; + dest_ptr += first_length; + src_ptr += first_length; + } + + if(dma->length_type == DMA_16BIT) + { + src_ptr &= ~0x01; + dest_ptr &= ~0x01; + cycle_dma16_words += length; + dma_transfer_expand(16); + } + else + { + src_ptr &= ~0x03; + dest_ptr &= ~0x03; + cycle_dma32_words += length; + dma_transfer_expand(32); + } + + if((dma->repeat_type == DMA_NO_REPEAT) || + (dma->start_type == DMA_START_IMMEDIATELY)) + { + dma->start_type = DMA_INACTIVE; + address16(io_registers, (dma->dma_channel * 12) + 0xBA) &= + (~0x8000); + } + + if(dma->irq) + { + raise_interrupt(IRQ_DMA0 << dma->dma_channel); + return_value = CPU_ALERT_IRQ; + } + + return return_value; +} + +// Be sure to do this after loading ROMs. + +#define map_region(type, start, end, mirror_blocks, region) \ + for(map_offset = (start) / 0x8000; map_offset < \ + ((end) / 0x8000); map_offset++) \ + { \ + memory_map_##type[map_offset] = \ + ((u8 *)region) + ((map_offset % mirror_blocks) * 0x8000); \ + } \ + +#define map_null(type, start, end) \ + for(map_offset = start / 0x8000; map_offset < (end / 0x8000); \ + map_offset++) \ + { \ + memory_map_##type[map_offset] = NULL; \ + } \ + +#define map_ram_region(type, start, end, mirror_blocks, region) \ + for(map_offset = (start) / 0x8000; map_offset < \ + ((end) / 0x8000); map_offset++) \ + { \ + memory_map_##type[map_offset] = \ + ((u8 *)region) + ((map_offset % mirror_blocks) * 0x10000) + 0x8000; \ + } \ + +#define map_vram(type) \ + for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \ + map_offset += 4) \ + { \ + memory_map_##type[map_offset] = vram; \ + memory_map_##type[map_offset + 1] = vram + 0x8000; \ + memory_map_##type[map_offset + 2] = vram + (0x8000 * 2); \ + memory_map_##type[map_offset + 3] = vram + (0x8000 * 2); \ + } \ + +#define map_vram_firstpage(type) \ + for(map_offset = 0x6000000 / 0x8000; map_offset < (0x7000000 / 0x8000); \ + map_offset += 4) \ + { \ + memory_map_##type[map_offset] = vram; \ + memory_map_##type[map_offset + 1] = NULL; \ + memory_map_##type[map_offset + 2] = NULL; \ + memory_map_##type[map_offset + 3] = NULL; \ + } \ + + +// Picks a page to evict +u32 page_time = 0; + +u32 evict_gamepak_page() +{ + // Find the one with the smallest frame timestamp + u32 page_index = 0; + u32 physical_index; + u32 smallest = gamepak_memory_map[0].page_timestamp; + u32 i; + + for(i = 1; i < gamepak_ram_pages; i++) + { + if(gamepak_memory_map[i].page_timestamp <= smallest) + { + smallest = gamepak_memory_map[i].page_timestamp; + page_index = i; + } + } + + physical_index = gamepak_memory_map[page_index].physical_index; + + memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = NULL; + memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = NULL; + memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = NULL; + + return page_index; +} + +u8 *load_gamepak_page(u32 physical_index) +{ + if(physical_index >= (gamepak_size >> 15)) + return gamepak_rom; + + u32 page_index = evict_gamepak_page(); + u32 page_offset = page_index * (32 * 1024); + u8 *swap_location = gamepak_rom + page_offset; + + gamepak_memory_map[page_index].page_timestamp = page_time; + gamepak_memory_map[page_index].physical_index = physical_index; + page_time++; + + file_seek(gamepak_file_large, physical_index * (32 * 1024), SEEK_SET); + file_read(gamepak_file_large, swap_location, (32 * 1024)); + memory_map_read[(0x8000000 / (32 * 1024)) + physical_index] = swap_location; + memory_map_read[(0xA000000 / (32 * 1024)) + physical_index] = swap_location; + memory_map_read[(0xC000000 / (32 * 1024)) + physical_index] = swap_location; + + // If RTC is active page the RTC register bytes so they can be read + if((rtc_state != RTC_DISABLED) && (physical_index == 0)) + { + memcpy(swap_location + 0xC4, rtc_registers, sizeof(rtc_registers)); + } + + return swap_location; +} + +void init_memory_gamepak() +{ + u32 map_offset = 0; + + if(gamepak_size > gamepak_ram_buffer_size) + { + // Large ROMs get special treatment because they + // can't fit into the 16MB ROM buffer. + u32 i; + for(i = 0; i < gamepak_ram_pages; i++) + { + gamepak_memory_map[i].page_timestamp = 0; + gamepak_memory_map[i].physical_index = 0; + } + + map_null(read, 0x8000000, 0xD000000); + } + else + { + map_region(read, 0x8000000, 0x8000000 + gamepak_size, 1024, gamepak_rom); + map_null(read, 0x8000000 + gamepak_size, 0xA000000); + map_region(read, 0xA000000, 0xA000000 + gamepak_size, 1024, gamepak_rom); + map_null(read, 0xA000000 + gamepak_size, 0xC000000); + map_region(read, 0xC000000, 0xC000000 + gamepak_size, 1024, gamepak_rom); + map_null(read, 0xC000000 + gamepak_size, 0xE000000); + } +} + +void init_gamepak_buffer() +{ + // Try to initialize 32MB (this is mainly for non-PSP platforms) + gamepak_rom = NULL; + + gamepak_ram_buffer_size = 32 * 1024 * 1024; + gamepak_rom = malloc(gamepak_ram_buffer_size); + + if(gamepak_rom == NULL) + { + // Try 16MB, for PSP, then lower in 2MB increments + gamepak_ram_buffer_size = 16 * 1024 * 1024; + gamepak_rom = malloc(gamepak_ram_buffer_size); + + while(gamepak_rom == NULL) + { + gamepak_ram_buffer_size -= (2 * 1024 * 1024); + gamepak_rom = malloc(gamepak_ram_buffer_size); + } + } + + // Here's assuming we'll have enough memory left over for this, + // and that the above succeeded (if not we're in trouble all around) + gamepak_ram_pages = gamepak_ram_buffer_size / (32 * 1024); + gamepak_memory_map = malloc(sizeof(gamepak_swap_entry_type) * + gamepak_ram_pages); +} + +void init_memory() +{ + u32 i; + u32 map_offset = 0; + + memory_regions[0x00] = (u8 *)bios_rom; + memory_regions[0x01] = (u8 *)bios_rom; + memory_regions[0x02] = (u8 *)ewram; + memory_regions[0x03] = (u8 *)iwram + 0x8000; + memory_regions[0x04] = (u8 *)io_registers; + memory_regions[0x05] = (u8 *)palette_ram; + memory_regions[0x06] = (u8 *)vram; + memory_regions[0x07] = (u8 *)oam_ram; + memory_regions[0x08] = (u8 *)gamepak_rom; + memory_regions[0x09] = (u8 *)(gamepak_rom + 0xFFFFFF); + memory_regions[0x0A] = (u8 *)gamepak_rom; + memory_regions[0x0B] = (u8 *)(gamepak_rom + 0xFFFFFF); + memory_regions[0x0C] = (u8 *)gamepak_rom; + memory_regions[0x0D] = (u8 *)(gamepak_rom + 0xFFFFFF); + memory_regions[0x0E] = (u8 *)gamepak_backup; + + memory_limits[0x00] = 0x3FFF; + memory_limits[0x01] = 0x3FFF; + memory_limits[0x02] = 0x3FFFF; + memory_limits[0x03] = 0x7FFF; + memory_limits[0x04] = 0x7FFF; + memory_limits[0x05] = 0x3FF; + memory_limits[0x06] = 0x17FFF; + memory_limits[0x07] = 0x3FF; + memory_limits[0x08] = 0x1FFFFFF; + memory_limits[0x09] = 0x1FFFFFF; + memory_limits[0x0A] = 0x1FFFFFF; + memory_limits[0x0B] = 0x1FFFFFF; + memory_limits[0x0C] = 0x1FFFFFF; + memory_limits[0x0D] = 0x1FFFFFF; + memory_limits[0x0E] = 0xFFFF; + + // Fill memory map regions, areas marked as NULL must be checked directly + map_region(read, 0x0000000, 0x1000000, 1, bios_rom); + map_null(read, 0x1000000, 0x2000000); + map_ram_region(read, 0x2000000, 0x3000000, 8, ewram); + map_ram_region(read, 0x3000000, 0x4000000, 1, iwram); + map_region(read, 0x4000000, 0x5000000, 1, io_registers); + map_null(read, 0x5000000, 0x6000000); + map_null(read, 0x6000000, 0x7000000); + map_vram(read); + map_null(read, 0x7000000, 0x8000000); + init_memory_gamepak(); + map_null(read, 0xE000000, 0x10000000); + + // Fill memory map regions, areas marked as NULL must be checked directly + map_null(write, 0x0000000, 0x2000000); + map_ram_region(write, 0x2000000, 0x3000000, 8, ewram); + map_ram_region(write, 0x3000000, 0x4000000, 1, iwram); + map_null(write, 0x4000000, 0x5000000); + map_null(write, 0x5000000, 0x6000000); + + // The problem here is that the current method of handling self-modifying code + // requires writeable memory to be proceeded by 32KB SMC data areas or be + // indirectly writeable. It's possible to get around this if you turn off the SMC + // check altogether, but this will make a good number of ROMs crash (perhaps most + // of the ones that actually need it? This has yet to be determined). + + // This is because VRAM cannot be efficiently made incontiguous, and still allow + // the renderer to work as efficiently. It would, at the very least, require a + // lot of hacking of the renderer which I'm not prepared to do. + + // However, it IS possible to directly map the first page no matter what because + // there's 32kb of blank stuff sitting beneath it. + if(direct_map_vram) + { + map_vram(write); + } + else + { + map_null(write, 0x6000000, 0x7000000); + } + + map_null(write, 0x7000000, 0x8000000); + map_null(write, 0x8000000, 0xE000000); + map_null(write, 0xE000000, 0x10000000); + + memset(io_registers, 0, 0x8000); + memset(oam_ram, 0, 0x400); + memset(palette_ram, 0, 0x400); + memset(iwram, 0, 0x10000); + memset(ewram, 0, 0x80000); + memset(vram, 0, 0x18000); + + io_registers[REG_DISPCNT] = 0x80; + io_registers[REG_P1] = 0x3FF; + io_registers[REG_BG2PA] = 0x100; + io_registers[REG_BG2PD] = 0x100; + io_registers[REG_BG3PA] = 0x100; + io_registers[REG_BG3PD] = 0x100; + io_registers[REG_RCNT] = 0x8000; + + backup_type = BACKUP_NONE; + + sram_size = SRAM_SIZE_32KB; + flash_size = FLASH_SIZE_64KB; + + flash_bank_ptr = gamepak_backup; + flash_command_position = 0; + eeprom_size = EEPROM_512_BYTE; + eeprom_mode = EEPROM_BASE_MODE; + eeprom_address = 0; + eeprom_counter = 0; + + flash_mode = FLASH_BASE_MODE; + + rtc_state = RTC_DISABLED; + memset(rtc_registers, 0, sizeof(rtc_registers)); + bios_read_protect = 0xe129f000; +} + +void bios_region_read_allow() +{ + memory_map_read[0] = bios_rom; +} + +void bios_region_read_protect() +{ +#ifdef GP2X_BUILD + memory_map_read[0] = NULL; +#endif +} + + +#define savestate_block(type) \ + cpu_##type##_savestate(savestate_file); \ + input_##type##_savestate(savestate_file); \ + main_##type##_savestate(savestate_file); \ + memory_##type##_savestate(savestate_file); \ + sound_##type##_savestate(savestate_file); \ + video_##type##_savestate(savestate_file) \ + +void load_state(char *savestate_filename) +{ + file_open(savestate_file, savestate_filename, read); + if(file_check_valid(savestate_file)) + { + char current_gamepak_filename[512]; + char savestate_gamepak_filename[512]; + u32 i; + u32 current_color; + + file_seek(savestate_file, (240 * 160 * 2) + sizeof(time_t), SEEK_SET); + + strcpy(current_gamepak_filename, gamepak_filename); + + savestate_block(read); + + file_close(savestate_file); + + flush_translation_cache_ram(); + flush_translation_cache_rom(); + flush_translation_cache_bios(); + + oam_update = 1; + gbc_sound_update = 1; + if(strcmp(current_gamepak_filename, gamepak_filename)) + { + u32 dot_position = strcspn(current_gamepak_filename, "."); + + // We'll let it slide if the filenames of the savestate and + // the gamepak are similar enough. + strcpy(gamepak_filename, current_gamepak_filename); + if(strncmp(savestate_filename, current_gamepak_filename, dot_position)) + { + if(load_gamepak(gamepak_filename) != -1) + { + reset_gba(); + // Okay, so this takes a while, but for now it works. + load_state(savestate_filename); + } + else + { + quit(); + } + + return; + } + } + + for(i = 0; i < 512; i++) + { + current_color = palette_ram[i]; + palette_ram_converted[i] = + convert_palette(current_color); + } + + // Oops, these contain raw pointers + for(i = 0; i < 4; i++) + { + gbc_sound_channel[i].sample_data = square_pattern_duty[2]; + } + current_debug_state = STEP; + instruction_count = 0; + + reg[CHANGED_PC_STATUS] = 1; + } +} + +u8 savestate_write_buffer[506947]; +u8 *write_mem_ptr; + +void save_state(char *savestate_filename, u16 *screen_capture) +{ + write_mem_ptr = savestate_write_buffer; + file_open(savestate_file, savestate_filename, write); + if(file_check_valid(savestate_file)) + { + time_t current_time; + file_write_mem(savestate_file, screen_capture, 240 * 160 * 2); + + time(¤t_time); + file_write_mem_variable(savestate_file, current_time); + + savestate_block(write_mem); + file_write(savestate_file, savestate_write_buffer, + sizeof(savestate_write_buffer)); + + file_close(savestate_file); + } +} + + +#define memory_savestate_builder(type) \ +void memory_##type##_savestate(file_tag_type savestate_file) \ +{ \ + u32 i; \ + \ + file_##type##_variable(savestate_file, backup_type); \ + file_##type##_variable(savestate_file, sram_size); \ + file_##type##_variable(savestate_file, flash_mode); \ + file_##type##_variable(savestate_file, flash_command_position); \ + file_##type##_variable(savestate_file, flash_bank_ptr); \ + file_##type##_variable(savestate_file, flash_device_id); \ + file_##type##_variable(savestate_file, flash_manufacturer_id); \ + file_##type##_variable(savestate_file, flash_size); \ + file_##type##_variable(savestate_file, eeprom_size); \ + file_##type##_variable(savestate_file, eeprom_mode); \ + file_##type##_variable(savestate_file, eeprom_address_length); \ + file_##type##_variable(savestate_file, eeprom_address); \ + file_##type##_variable(savestate_file, eeprom_counter); \ + file_##type##_variable(savestate_file, rtc_state); \ + file_##type##_variable(savestate_file, rtc_write_mode); \ + file_##type##_array(savestate_file, rtc_registers); \ + file_##type##_variable(savestate_file, rtc_command); \ + file_##type##_array(savestate_file, rtc_data); \ + file_##type##_variable(savestate_file, rtc_status); \ + file_##type##_variable(savestate_file, rtc_data_bytes); \ + file_##type##_variable(savestate_file, rtc_bit_count); \ + file_##type##_array(savestate_file, eeprom_buffer); \ + file_##type##_array(savestate_file, gamepak_filename); \ + file_##type##_array(savestate_file, dma); \ + \ + file_##type(savestate_file, iwram + 0x8000, 0x8000); \ + for(i = 0; i < 8; i++) \ + { \ + file_##type(savestate_file, ewram + (i * 0x10000) + 0x8000, 0x8000); \ + } \ + file_##type(savestate_file, vram, 0x18000); \ + file_##type(savestate_file, oam_ram, 0x400); \ + file_##type(savestate_file, palette_ram, 0x400); \ + file_##type(savestate_file, io_registers, 0x8000); \ + \ + /* This is a hack, for now. */ \ + if((flash_bank_ptr < gamepak_backup) || \ + (flash_bank_ptr > (gamepak_backup + (1024 * 64)))) \ + { \ + flash_bank_ptr = gamepak_backup; \ + } \ +} \ + +memory_savestate_builder(read); +memory_savestate_builder(write_mem); + diff --git a/memory.h b/memory.h new file mode 100644 index 0000000..ca2ecd6 --- /dev/null +++ b/memory.h @@ -0,0 +1,219 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MEMORY_H +#define MEMORY_H + +typedef enum +{ + DMA_START_IMMEDIATELY, + DMA_START_VBLANK, + DMA_START_HBLANK, + DMA_START_SPECIAL, + DMA_INACTIVE +} dma_start_type; + +typedef enum +{ + DMA_16BIT, + DMA_32BIT +} dma_length_type; + +typedef enum +{ + DMA_NO_REPEAT, + DMA_REPEAT +} dma_repeat_type; + +typedef enum +{ + DMA_INCREMENT, + DMA_DECREMENT, + DMA_FIXED, + DMA_RELOAD +} dma_increment_type; + +typedef enum +{ + DMA_NO_IRQ, + DMA_TRIGGER_IRQ +} dma_irq_type; + +typedef enum +{ + DMA_DIRECT_SOUND_A, + DMA_DIRECT_SOUND_B, + DMA_NO_DIRECT_SOUND +} dma_ds_type; + +typedef struct +{ + u32 dma_channel; + u32 source_address; + u32 dest_address; + u32 length; + dma_repeat_type repeat_type; + dma_ds_type direct_sound_channel; + dma_increment_type source_direction; + dma_increment_type dest_direction; + dma_length_type length_type; + dma_start_type start_type; + dma_irq_type irq; +} dma_transfer_type; + +typedef enum +{ + REG_DISPCNT = 0x000, + REG_DISPSTAT = 0x002, + REG_VCOUNT = 0x003, + REG_BG0CNT = 0x004, + REG_BG1CNT = 0x005, + REG_BG2CNT = 0x006, + REG_BG3CNT = 0x007, + REG_BG0HOFS = 0x08, + REG_BG0VOFS = 0x09, + REG_BG1HOFS = 0x0A, + REG_BG1VOFS = 0x0B, + REG_BG2HOFS = 0x0C, + REG_BG2VOFS = 0x0D, + REG_BG3HOFS = 0x0E, + REG_BG3VOFS = 0x0F, + REG_BG2PA = 0x10, + REG_BG2PB = 0x11, + REG_BG2PC = 0x12, + REG_BG2PD = 0x13, + REG_BG2X_L = 0x14, + REG_BG2X_H = 0x15, + REG_BG2Y_L = 0x16, + REG_BG2Y_H = 0x17, + REG_BG3PA = 0x18, + REG_BG3PB = 0x19, + REG_BG3PC = 0x1A, + REG_BG3PD = 0x1B, + REG_BG3X_L = 0x1C, + REG_BG3X_H = 0x1D, + REG_BG3Y_L = 0x1E, + REG_BG3Y_H = 0x1F, + REG_WIN0H = 0x20, + REG_WIN1H = 0x21, + REG_WIN0V = 0x22, + REG_WIN1V = 0x23, + REG_WININ = 0x24, + REG_WINOUT = 0x25, + REG_BLDCNT = 0x28, + REG_BLDALPHA = 0x29, + REG_BLDY = 0x2A, + REG_TM0D = 0x80, + REG_TM0CNT = 0x81, + REG_TM1D = 0x82, + REG_TM1CNT = 0x83, + REG_TM2D = 0x84, + REG_TM2CNT = 0x85, + REG_TM3D = 0x86, + REG_TM3CNT = 0x87, + REG_P1 = 0x098, + REG_P1CNT = 0x099, + REG_RCNT = 0x9A, + REG_IE = 0x100, + REG_IF = 0x101, + REG_IME = 0x104, + REG_HALTCNT = 0x180 +} hardware_register; + +typedef enum +{ + FLASH_DEVICE_MACRONIX_64KB = 0x1C, + FLASH_DEVICE_AMTEL_64KB = 0x3D, + FLASH_DEVICE_SST_64K = 0xD4, + FLASH_DEVICE_PANASONIC_64KB = 0x1B, + FLASH_DEVICE_MACRONIX_128KB = 0x09 +} flash_device_id_type; + +typedef enum +{ + FLASH_MANUFACTURER_MACRONIX = 0xC2, + FLASH_MANUFACTURER_AMTEL = 0x1F, + FLASH_MANUFACTURER_PANASONIC = 0x32, + FLASH_MANUFACTURER_SST = 0xBF +} flash_manufacturer_id_type; + +u8 function_cc read_memory8(u32 address); +u32 function_cc read_memory16(u32 address); +u16 function_cc read_memory16_signed(u32 address); +u32 function_cc read_memory32(u32 address); +cpu_alert_type function_cc write_memory8(u32 address, u8 value); +cpu_alert_type function_cc write_memory16(u32 address, u16 value); +cpu_alert_type function_cc write_memory32(u32 address, u32 value); + +extern u8 *memory_regions[16]; +extern u32 memory_limits[16]; + +/* EDIT: Shouldn't this be extern ?! */ +extern u32 waitstate_cycles_sequential[16][3]; + +extern u32 gamepak_size; +extern u8 gamepak_title[13]; +extern u8 gamepak_code[5]; +extern u8 gamepak_maker[3]; +extern u8 gamepak_filename[512]; + +cpu_alert_type dma_transfer(dma_transfer_type *dma); +u8 *memory_region(u32 address, u32 *memory_limit); +u32 load_gamepak(char *name); +u32 load_backup(char *name); +s32 load_bios(char *name); +void update_backup(); +void update_backup_force(); +void init_memory(); +void init_gamepak_buffer(); +void bios_region_read_allow(); +void bios_region_read_protect(); +u8 *load_gamepak_page(u32 physical_index); +void memory_write_mem_savestate(file_tag_type savestate_file); +void memory_read_savestate(file_tag_type savestate_file); +void load_state(char *savestate_filename); +void save_state(char *savestate_filename, u16 *screen_capture); + +extern u8 *gamepak_rom; +extern u32 gamepak_ram_buffer_size; +extern u32 oam_update; +extern u32 gbc_sound_update; +extern u32 gbc_sound_wave_update; +extern dma_transfer_type dma[4]; + +extern u8 *write_mem_ptr; + +extern u16 palette_ram[512]; +extern u16 oam_ram[512]; +extern u16 palette_ram_converted[512]; +extern u16 io_registers[1024 * 16]; +extern u8 ewram[1024 * 256 * 2]; +extern u8 iwram[1024 * 32 * 2]; +extern u8 vram[1024 * 96 * 2]; + +extern u8 bios_rom[1024 * 32]; +extern u32 bios_read_protect; + +extern u8 *memory_map_read[8 * 1024]; +extern u32 *reg; +extern u8 *memory_map_write[8 * 1024]; + +extern flash_device_id_type flash_device_id; + +#endif diff --git a/psp/Makefile b/psp/Makefile new file mode 100644 index 0000000..9906e6f --- /dev/null +++ b/psp/Makefile @@ -0,0 +1,26 @@ +# -x assembler-with-cpp +# gpSP makefile +# Gilead Kutnick - Exophase + +# Global definitions + +PSPSDK = ${shell psp-config --pspsdk-path} +PREFIX = ${shell psp-config --psp-prefix} + +OBJS = main.o cpu.o video.o memory.o sound.o input.o \ + cpu_threaded.o gui.o zip.o cheats.o mips_stub.o + +TARGET = gpSP + +VPATH += .. +CFLAGS += -O3 -DPSP_BUILD -G0 -funsigned-char +CFLAGS += ${shell ${PREFIX}/bin/sdl-config --cflags} +ASFLAGS = ${CFLAGS} +PSP_EBOOT_TITLE = gpSP +EXTRA_TARGETS = EBOOT.PBP + +LIBS += ${shell ${PREFIX}/bin/sdl-config --libs} -lpsppower \ + -lz + +include ${PSPSDK}/lib/build.mak + diff --git a/psp/mips_emit.h b/psp/mips_emit.h new file mode 100644 index 0000000..8fc95e8 --- /dev/null +++ b/psp/mips_emit.h @@ -0,0 +1,2531 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MIPS_EMIT_H +#define MIPS_EMIT_H + +u32 mips_update_gba(u32 pc); + +// Although these are defined as a function, don't call them as +// such (jump to it instead) +void mips_indirect_branch_arm(u32 address); +void mips_indirect_branch_thumb(u32 address); +void mips_indirect_branch_dual(u32 address); + +u32 execute_read_cpsr(); +u32 execute_read_spsr(); +void execute_swi(u32 pc); + +u32 execute_spsr_restore(u32 address); +void execute_store_cpsr(u32 new_cpsr, u32 store_mask); +void execute_store_spsr(u32 new_spsr, u32 store_mask); + +u32 execute_spsr_restore_body(u32 address); +u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address); + +u32 execute_lsl_flags_reg(u32 value, u32 shift); +u32 execute_lsr_flags_reg(u32 value, u32 shift); +u32 execute_asr_flags_reg(u32 value, u32 shift); +u32 execute_ror_flags_reg(u32 value, u32 shift); + +void execute_aligned_store32(u32 address, u32 value); +u32 execute_aligned_load32(u32 address); + +void step_debug_mips(u32 pc); + +void reg_check(); + +typedef enum +{ + mips_reg_zero, + mips_reg_at, + mips_reg_v0, + mips_reg_v1, + mips_reg_a0, + mips_reg_a1, + mips_reg_a2, + mips_reg_a3, + mips_reg_t0, + mips_reg_t1, + mips_reg_t2, + mips_reg_t3, + mips_reg_t4, + mips_reg_t5, + mips_reg_t6, + mips_reg_t7, + mips_reg_s0, + mips_reg_s1, + mips_reg_s2, + mips_reg_s3, + mips_reg_s4, + mips_reg_s5, + mips_reg_s6, + mips_reg_s7, + mips_reg_t8, + mips_reg_t9, + mips_reg_k0, + mips_reg_k1, + mips_reg_gp, + mips_reg_sp, + mips_reg_fp, + mips_reg_ra +} mips_reg_number; + +typedef enum +{ + mips_special_sll = 0x00, + mips_special_srl = 0x02, + mips_special_sra = 0x03, + mips_special_sllv = 0x04, + mips_special_srlv = 0x06, + mips_special_srav = 0x07, + mips_special_jr = 0x08, + mips_special_jalr = 0x09, + mips_special_movz = 0x0A, + mips_special_movn = 0x0B, + mips_special_mfhi = 0x10, + mips_special_mthi = 0x11, + mips_special_mflo = 0x12, + mips_special_mtlo = 0x13, + mips_special_mult = 0x18, + mips_special_multu = 0x19, + mips_special_div = 0x1A, + mips_special_divu = 0x1B, + mips_special_madd = 0x1C, + mips_special_maddu = 0x1D, + mips_special_add = 0x20, + mips_special_addu = 0x21, + mips_special_sub = 0x22, + mips_special_subu = 0x23, + mips_special_and = 0x24, + mips_special_or = 0x25, + mips_special_xor = 0x26, + mips_special_nor = 0x27, + mips_special_slt = 0x2A, + mips_special_sltu = 0x2B +} mips_function_special; + +typedef enum +{ + mips_special3_ext = 0x00, + mips_special3_ins = 0x04, + mips_special3_bshfl = 0x20 +} mips_function_special3; + +typedef enum +{ + mips_regimm_bltz = 0x00, + mips_regimm_bltzal = 0x10 +} mips_function_regimm; + +typedef enum +{ + mips_opcode_special = 0x00, + mips_opcode_regimm = 0x01, + mips_opcode_j = 0x02, + mips_opcode_jal = 0x03, + mips_opcode_beq = 0x04, + mips_opcode_bne = 0x05, + mips_opcode_blez = 0x06, + mips_opcode_bgtz = 0x07, + mips_opcode_addi = 0x08, + mips_opcode_addiu = 0x09, + mips_opcode_slti = 0x0A, + mips_opcode_sltiu = 0x0B, + mips_opcode_andi = 0x0C, + mips_opcode_ori = 0x0D, + mips_opcode_xori = 0x0E, + mips_opcode_lui = 0x0F, + mips_opcode_llo = 0x18, + mips_opcode_lhi = 0x19, + mips_opcode_trap = 0x1A, + mips_opcode_special2 = 0x1C, + mips_opcode_special3 = 0x1F, + mips_opcode_lb = 0x20, + mips_opcode_lh = 0x21, + mips_opcode_lw = 0x23, + mips_opcode_lbu = 0x24, + mips_opcode_lhu = 0x25, + mips_opcode_sb = 0x28, + mips_opcode_sh = 0x29, + mips_opcode_sw = 0x2B, +} mips_opcode; + +#define mips_emit_reg(opcode, rs, rt, rd, shift, function) \ + *((u32 *)translation_ptr) = (mips_opcode_##opcode << 26) | \ + (rs << 21) | (rt << 16) | (rd << 11) | (shift << 6) | function; \ + translation_ptr += 4 \ + +#define mips_emit_special(function, rs, rt, rd, shift) \ + *((u32 *)translation_ptr) = (mips_opcode_special << 26) | \ + (rs << 21) | (rt << 16) | (rd << 11) | (shift << 6) | \ + mips_special_##function; \ + translation_ptr += 4 \ + +#define mips_emit_special3(function, rs, rt, imm_a, imm_b) \ + *((u32 *)translation_ptr) = (mips_opcode_special3 << 26) | \ + (rs << 21) | (rt << 16) | (imm_a << 11) | (imm_b << 6) | \ + mips_special3_##function; \ + translation_ptr += 4 \ + +#define mips_emit_imm(opcode, rs, rt, immediate) \ + *((u32 *)translation_ptr) = (mips_opcode_##opcode << 26) | \ + (rs << 21) | (rt << 16) | (immediate & 0xFFFF); \ + translation_ptr += 4 \ + +#define mips_emit_regimm(function, rs, immediate) \ + *((u32 *)translation_ptr) = (mips_opcode_regimm << 26) | \ + (rs << 21) | (mips_regimm_##function << 16) | (immediate & 0xFFFF); \ + translation_ptr += 4 \ + +#define mips_emit_jump(opcode, offset) \ + *((u32 *)translation_ptr) = (mips_opcode_##opcode << 26) | \ + (offset & 0x3FFFFFF); \ + translation_ptr += 4 \ + +#define mips_relative_offset(source, offset) \ + (((u32)offset - ((u32)source + 4)) / 4) \ + +#define mips_absolute_offset(offset) \ + ((u32)offset / 4) \ + +#define mips_emit_addu(rd, rs, rt) \ + mips_emit_special(addu, rs, rt, rd, 0) \ + +#define mips_emit_subu(rd, rs, rt) \ + mips_emit_special(subu, rs, rt, rd, 0) \ + +#define mips_emit_xor(rd, rs, rt) \ + mips_emit_special(xor, rs, rt, rd, 0) \ + +#define mips_emit_add(rd, rs, rt) \ + mips_emit_special(and, rs, rt, rd, 0) \ + +#define mips_emit_sub(rd, rs, rt) \ + mips_emit_special(sub, rs, rt, rd, 0) \ + +#define mips_emit_and(rd, rs, rt) \ + mips_emit_special(and, rs, rt, rd, 0) \ + +#define mips_emit_or(rd, rs, rt) \ + mips_emit_special(or, rs, rt, rd, 0) \ + +#define mips_emit_nor(rd, rs, rt) \ + mips_emit_special(nor, rs, rt, rd, 0) \ + +#define mips_emit_slt(rd, rs, rt) \ + mips_emit_special(slt, rs, rt, rd, 0) \ + +#define mips_emit_sltu(rd, rs, rt) \ + mips_emit_special(sltu, rs, rt, rd, 0) \ + +#define mips_emit_sllv(rd, rt, rs) \ + mips_emit_special(sllv, rs, rt, rd, 0) \ + +#define mips_emit_srlv(rd, rt, rs) \ + mips_emit_special(srlv, rs, rt, rd, 0) \ + +#define mips_emit_srav(rd, rt, rs) \ + mips_emit_special(srav, rs, rt, rd, 0) \ + +#define mips_emit_rotrv(rd, rt, rs) \ + mips_emit_special(srlv, rs, rt, rd, 1) \ + +#define mips_emit_sll(rd, rt, shift) \ + mips_emit_special(sll, 0, rt, rd, shift) \ + +#define mips_emit_srl(rd, rt, shift) \ + mips_emit_special(srl, 0, rt, rd, shift) \ + +#define mips_emit_sra(rd, rt, shift) \ + mips_emit_special(sra, 0, rt, rd, shift) \ + +#define mips_emit_rotr(rd, rt, shift) \ + mips_emit_special(srl, 1, rt, rd, shift) \ + +#define mips_emit_mfhi(rd) \ + mips_emit_special(mfhi, 0, 0, rd, 0) \ + +#define mips_emit_mflo(rd) \ + mips_emit_special(mflo, 0, 0, rd, 0) \ + +#define mips_emit_mthi(rs) \ + mips_emit_special(mthi, rs, 0, 0, 0) \ + +#define mips_emit_mtlo(rs) \ + mips_emit_special(mtlo, rs, 0, 0, 0) \ + +#define mips_emit_mult(rs, rt) \ + mips_emit_special(mult, rs, rt, 0, 0) \ + +#define mips_emit_multu(rs, rt) \ + mips_emit_special(multu, rs, rt, 0, 0) \ + +#define mips_emit_div(rs, rt) \ + mips_emit_special(div, rs, rt, 0, 0) \ + +#define mips_emit_divu(rs, rt) \ + mips_emit_special(divu, rs, rt, 0, 0) \ + +#define mips_emit_madd(rs, rt) \ + mips_emit_special(madd, rs, rt, 0, 0) \ + +#define mips_emit_maddu(rs, rt) \ + mips_emit_special(maddu, rs, rt, 0, 0) \ + +#define mips_emit_movn(rd, rs, rt) \ + mips_emit_special(movn, rs, rt, rd, 0) \ + +#define mips_emit_movz(rd, rs, rt) \ + mips_emit_special(movz, rs, rt, rd, 0) \ + +#define mips_emit_lb(rt, rs, offset) \ + mips_emit_imm(lb, rs, rt, offset) \ + +#define mips_emit_lbu(rt, rs, offset) \ + mips_emit_imm(lbu, rs, rt, offset) \ + +#define mips_emit_lh(rt, rs, offset) \ + mips_emit_imm(lh, rs, rt, offset) \ + +#define mips_emit_lhu(rt, rs, offset) \ + mips_emit_imm(lhu, rs, rt, offset) \ + +#define mips_emit_lw(rt, rs, offset) \ + mips_emit_imm(lw, rs, rt, offset) \ + +#define mips_emit_sb(rt, rs, offset) \ + mips_emit_imm(sb, rs, rt, offset) \ + +#define mips_emit_sh(rt, rs, offset) \ + mips_emit_imm(sh, rs, rt, offset) \ + +#define mips_emit_sw(rt, rs, offset) \ + mips_emit_imm(sw, rs, rt, offset) \ + +#define mips_emit_lui(rt, imm) \ + mips_emit_imm(lui, 0, rt, imm) \ + +#define mips_emit_addiu(rt, rs, imm) \ + mips_emit_imm(addiu, rs, rt, imm) \ + +#define mips_emit_xori(rt, rs, imm) \ + mips_emit_imm(xori, rs, rt, imm) \ + +#define mips_emit_ori(rt, rs, imm) \ + mips_emit_imm(ori, rs, rt, imm) \ + +#define mips_emit_andi(rt, rs, imm) \ + mips_emit_imm(andi, rs, rt, imm) \ + +#define mips_emit_slti(rt, rs, imm) \ + mips_emit_imm(slti, rs, rt, imm) \ + +#define mips_emit_sltiu(rt, rs, imm) \ + mips_emit_imm(sltiu, rs, rt, imm) \ + +#define mips_emit_ext(rt, rs, pos, size) \ + mips_emit_special3(ext, rs, rt, (size - 1), pos) \ + +#define mips_emit_ins(rt, rs, pos, size) \ + mips_emit_special3(ins, rs, rt, (pos + size - 1), pos) \ + +// Breaks down if the backpatch offset is greater than 16bits, take care +// when using (should be okay if limited to conditional instructions) + +#define mips_emit_b_filler(type, rs, rt, writeback_location) \ + (writeback_location) = translation_ptr; \ + mips_emit_imm(type, rs, rt, 0) \ + +// The backpatch code for this has to be handled differently than the above + +#define mips_emit_j_filler(writeback_location) \ + (writeback_location) = translation_ptr; \ + mips_emit_jump(j, 0) \ + +#define mips_emit_b(type, rs, rt, offset) \ + mips_emit_imm(type, rs, rt, offset) \ + +#define mips_emit_j(offset) \ + mips_emit_jump(j, offset) \ + +#define mips_emit_jal(offset) \ + mips_emit_jump(jal, offset) \ + +#define mips_emit_jr(rs) \ + mips_emit_special(jr, rs, 0, 0, 0) \ + +#define mips_emit_bltzal(rs, offset) \ + mips_emit_regimm(bltzal, rs, offset) \ + +#define mips_emit_nop() \ + mips_emit_sll(reg_zero, reg_zero, 0) \ + +#define reg_base mips_reg_s0 +#define reg_cycles mips_reg_s1 +#define reg_a0 mips_reg_a0 +#define reg_a1 mips_reg_a1 +#define reg_a2 mips_reg_a2 +#define reg_rv mips_reg_v0 +#define reg_pc mips_reg_s3 +#define reg_temp mips_reg_at +#define reg_zero mips_reg_zero + +#define reg_n_cache mips_reg_s4 +#define reg_z_cache mips_reg_s5 +#define reg_c_cache mips_reg_s6 +#define reg_v_cache mips_reg_s7 + +#define reg_r0 mips_reg_v1 +#define reg_r1 mips_reg_a3 +#define reg_r2 mips_reg_t0 +#define reg_r3 mips_reg_t1 +#define reg_r4 mips_reg_t2 +#define reg_r5 mips_reg_t3 +#define reg_r6 mips_reg_t4 +#define reg_r7 mips_reg_t5 +#define reg_r8 mips_reg_t6 +#define reg_r9 mips_reg_t7 +#define reg_r10 mips_reg_s2 +#define reg_r11 mips_reg_t8 +#define reg_r12 mips_reg_t9 +#define reg_r13 mips_reg_gp +#define reg_r14 mips_reg_fp + +// Writing to r15 goes straight to a0, to be chained with other ops + +u32 arm_to_mips_reg[] = +{ + reg_r0, + reg_r1, + reg_r2, + reg_r3, + reg_r4, + reg_r5, + reg_r6, + reg_r7, + reg_r8, + reg_r9, + reg_r10, + reg_r11, + reg_r12, + reg_r13, + reg_r14, + reg_a0, + reg_a1, + reg_a2, + reg_temp +}; + +#define arm_reg_a0 15 +#define arm_reg_a1 16 +#define arm_reg_a2 17 +#define arm_reg_temp 18 + +#define generate_load_reg(ireg, reg_index) \ + mips_emit_addu(ireg, arm_to_mips_reg[reg_index], reg_zero) \ + +#define generate_load_imm(ireg, imm) \ + if(((s32)imm >= -32768) && ((s32)imm <= 32767)) \ + { \ + mips_emit_addiu(ireg, reg_zero, imm); \ + } \ + else \ + { \ + if(((u32)imm >> 16) == 0x0000) \ + { \ + mips_emit_ori(ireg, reg_zero, imm); \ + } \ + else \ + { \ + mips_emit_lui(ireg, imm >> 16); \ + \ + if(((u32)imm & 0x0000FFFF) != 0x00000000) \ + { \ + mips_emit_ori(ireg, ireg, imm & 0xFFFF); \ + } \ + } \ + } \ + +#define generate_load_pc(ireg, new_pc) \ +{ \ + s32 pc_delta = new_pc - stored_pc; \ + if((pc_delta >= -32768) && (pc_delta <= 32767)) \ + { \ + mips_emit_addiu(ireg, reg_pc, pc_delta); \ + } \ + else \ + { \ + generate_load_imm(ireg, new_pc); \ + } \ +} \ + +#define generate_store_reg(ireg, reg_index) \ + mips_emit_addu(arm_to_mips_reg[reg_index], ireg, reg_zero) \ + +#define generate_shift_left(ireg, imm) \ + mips_emit_sll(ireg, ireg, imm) \ + +#define generate_shift_right(ireg, imm) \ + mips_emit_srl(ireg, ireg, imm) \ + +#define generate_shift_right_arithmetic(ireg, imm) \ + mips_emit_sra(ireg, ireg, imm) \ + +#define generate_rotate_right(ireg, imm) \ + mips_emit_rotr(ireg, ireg, imm) \ + +#define generate_add(ireg_dest, ireg_src) \ + mips_emit_addu(ireg_dest, ireg_dest, ireg_src) \ + +#define generate_sub(ireg_dest, ireg_src) \ + mips_emit_subu(ireg_dest, ireg_dest, ireg_src) \ + +#define generate_or(ireg_dest, ireg_src) \ + mips_emit_or(ireg_dest, ireg_dest, ireg_src) \ + +#define generate_xor(ireg_dest, ireg_src) \ + mips_emit_xor(ireg_dest, ireg_dest, ireg_src) \ + +#define generate_alu_imm(imm_type, reg_type, ireg_dest, ireg_src, imm) \ + if(((s32)imm >= -32768) && ((s32)imm <= 32767)) \ + { \ + mips_emit_##imm_type(ireg_dest, ireg_src, imm); \ + } \ + else \ + { \ + generate_load_imm(reg_temp, imm); \ + mips_emit_##reg_type(ireg_dest, ireg_src, reg_temp); \ + } \ + +#define generate_alu_immu(imm_type, reg_type, ireg_dest, ireg_src, imm) \ + if(((u32)imm >= 0) && ((u32)imm <= 65535)) \ + { \ + mips_emit_##imm_type(ireg_dest, ireg_src, imm); \ + } \ + else \ + { \ + generate_load_imm(reg_temp, imm); \ + mips_emit_##reg_type(ireg_dest, ireg_src, reg_temp); \ + } \ + +#define generate_add_imm(ireg, imm) \ + generate_alu_imm(addiu, add, ireg, ireg, imm) \ + +#define generate_sub_imm(ireg, imm) \ + generate_alu_imm(addiu, add, ireg, ireg, -imm) \ + +#define generate_xor_imm(ireg, imm) \ + generate_alu_immu(xori, xor, ireg, ireg, imm) \ + +#define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm) \ + generate_alu_imm(addiu, add, ireg_dest, ireg_src, imm) \ + +#define generate_and_imm(ireg, imm) \ + generate_alu_immu(andi, and, ireg, ireg, imm) \ + +#define generate_mov(ireg_dest, ireg_src) \ + mips_emit_addu(ireg_dest, ireg_src, reg_zero) \ + +#define generate_multiply_s64() \ + mips_emit_mult(arm_to_mips_reg[rm], arm_to_mips_reg[rs]) \ + +#define generate_multiply_u64() \ + mips_emit_multu(arm_to_mips_reg[rm], arm_to_mips_reg[rs]) \ + +#define generate_multiply_s64_add() \ + mips_emit_madd(arm_to_mips_reg[rm], arm_to_mips_reg[rs]) \ + +#define generate_multiply_u64_add() \ + mips_emit_maddu(arm_to_mips_reg[rm], arm_to_mips_reg[rs]) \ + +#define generate_function_call(function_location) \ + mips_emit_jal(mips_absolute_offset(function_location)); \ + mips_emit_nop() \ + +#define generate_function_call_swap_delay(function_location) \ +{ \ + u32 delay_instruction = address32(translation_ptr, -4); \ + translation_ptr -= 4; \ + mips_emit_jal(mips_absolute_offset(function_location)); \ + address32(translation_ptr, 0) = delay_instruction; \ + translation_ptr += 4; \ +} \ + +#define generate_swap_delay() \ +{ \ + u32 delay_instruction = address32(translation_ptr, -8); \ + u32 branch_instruction = address32(translation_ptr, -4); \ + branch_instruction = (branch_instruction & 0xFFFF0000) | \ + (((branch_instruction & 0x0000FFFF) + 1) & 0x0000FFFF); \ + address32(translation_ptr, -8) = branch_instruction; \ + address32(translation_ptr, -4) = delay_instruction; \ +} \ + +#define generate_cycle_update() \ + if(cycle_count != 0) \ + { \ + mips_emit_addiu(reg_cycles, reg_cycles, -cycle_count); \ + cycle_count = 0; \ + } \ + +#define generate_cycle_update_force() \ + mips_emit_addiu(reg_cycles, reg_cycles, -cycle_count); \ + cycle_count = 0 \ + +#define generate_branch_patch_conditional(dest, offset) \ + *((u16 *)(dest)) = mips_relative_offset(dest, offset) \ + +#define generate_branch_patch_unconditional(dest, offset) \ + *((u32 *)(dest)) = (mips_opcode_j << 26) | \ + ((mips_absolute_offset(offset)) & 0x3FFFFFF) \ + +#define generate_branch_no_cycle_update(writeback_location, new_pc) \ + if(pc == idle_loop_target_pc) \ + { \ + generate_load_pc(reg_a0, new_pc); \ + generate_function_call_swap_delay(mips_update_gba); \ + mips_emit_j_filler(writeback_location); \ + mips_emit_nop(); \ + } \ + else \ + { \ + generate_load_pc(reg_a0, new_pc); \ + mips_emit_bltzal(reg_cycles, \ + mips_relative_offset(translation_ptr, update_trampoline)); \ + generate_swap_delay(); \ + mips_emit_j_filler(writeback_location); \ + mips_emit_nop(); \ + } \ + +#define generate_branch_cycle_update(writeback_location, new_pc) \ + generate_cycle_update(); \ + generate_branch_no_cycle_update(writeback_location, new_pc) \ + +#define generate_conditional_branch(ireg_a, ireg_b, type, writeback_location) \ + generate_branch_filler_##type(ireg_a, ireg_b, writeback_location) \ + +// a0 holds the destination + +#define generate_indirect_branch_cycle_update(type) \ + mips_emit_j(mips_absolute_offset(mips_indirect_branch_##type)); \ + generate_cycle_update_force() \ + +#define generate_indirect_branch_no_cycle_update(type) \ + mips_emit_j(mips_absolute_offset(mips_indirect_branch_##type)); \ + mips_emit_nop() \ + +#define generate_block_prologue() \ + update_trampoline = translation_ptr; \ + __asm__ \ + ( \ + "cache 8, 0(%0)\n" \ + "cache 8, 0(%0)" : : "r"(translation_ptr) \ + ); \ + \ + mips_emit_j(mips_absolute_offset(mips_update_gba)); \ + mips_emit_nop(); \ + generate_load_imm(reg_pc, stored_pc) \ + +#define translate_invalidate_dcache() \ + sceKernelDcacheWritebackAll() \ + +#define block_prologue_size 8 + +#define check_generate_n_flag \ + (flag_status & 0x08) \ + +#define check_generate_z_flag \ + (flag_status & 0x04) \ + +#define check_generate_c_flag \ + (flag_status & 0x02) \ + +#define check_generate_v_flag \ + (flag_status & 0x01) \ + +#define generate_load_reg_pc(ireg, reg_index, pc_offset) \ + if(reg_index == REG_PC) \ + { \ + generate_load_pc(ireg, (pc + pc_offset)); \ + } \ + else \ + { \ + generate_load_reg(ireg, reg_index); \ + } \ + +#define check_load_reg_pc(arm_reg, reg_index, pc_offset) \ + if(reg_index == REG_PC) \ + { \ + reg_index = arm_reg; \ + generate_load_pc(arm_to_mips_reg[arm_reg], (pc + pc_offset)); \ + } \ + +#define check_store_reg_pc_no_flags(reg_index) \ + if(reg_index == REG_PC) \ + { \ + generate_indirect_branch_arm(); \ + } \ + +#define check_store_reg_pc_flags(reg_index) \ + if(reg_index == REG_PC) \ + { \ + generate_function_call(execute_spsr_restore); \ + generate_indirect_branch_dual(); \ + } \ + +#define generate_shift_imm_lsl_no_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_sll(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + _rm = arm_reg; \ + } \ + +#define generate_shift_imm_lsr_no_flags(arm_reg, _rm, _shift) \ + if(_shift != 0) \ + { \ + check_load_reg_pc(arm_reg, _rm, 8); \ + mips_emit_srl(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_addu(arm_to_mips_reg[arm_reg], reg_zero, reg_zero); \ + } \ + _rm = arm_reg \ + +#define generate_shift_imm_asr_no_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_sra(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_sra(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], 31); \ + } \ + _rm = arm_reg \ + +#define generate_shift_imm_ror_no_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_rotr(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_srl(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], 1); \ + mips_emit_ins(arm_to_mips_reg[arm_reg], reg_c_cache, 31, 1); \ + } \ + _rm = arm_reg \ + +#define generate_shift_imm_lsl_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_ext(reg_c_cache, arm_to_mips_reg[_rm], (32 - _shift), 1); \ + mips_emit_sll(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + _rm = arm_reg; \ + } \ + +#define generate_shift_imm_lsr_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_ext(reg_c_cache, arm_to_mips_reg[_rm], (_shift - 1), 1); \ + mips_emit_srl(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_srl(reg_c_cache, arm_to_mips_reg[_rm], 31); \ + mips_emit_addu(arm_to_mips_reg[arm_reg], reg_zero, reg_zero); \ + } \ + _rm = arm_reg \ + +#define generate_shift_imm_asr_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_ext(reg_c_cache, arm_to_mips_reg[_rm], (_shift - 1), 1); \ + mips_emit_sra(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_sra(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], 31); \ + mips_emit_andi(reg_c_cache, arm_to_mips_reg[arm_reg], 1); \ + } \ + _rm = arm_reg \ + +#define generate_shift_imm_ror_flags(arm_reg, _rm, _shift) \ + check_load_reg_pc(arm_reg, _rm, 8); \ + if(_shift != 0) \ + { \ + mips_emit_ext(reg_c_cache, arm_to_mips_reg[_rm], (_shift - 1), 1); \ + mips_emit_rotr(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], _shift); \ + } \ + else \ + { \ + mips_emit_andi(reg_temp, arm_to_mips_reg[_rm], 1); \ + mips_emit_srl(arm_to_mips_reg[arm_reg], arm_to_mips_reg[_rm], 1); \ + mips_emit_ins(arm_to_mips_reg[arm_reg], reg_c_cache, 31, 1); \ + mips_emit_addu(reg_c_cache, reg_temp, reg_zero); \ + } \ + _rm = arm_reg \ + +#define generate_shift_reg_lsl_no_flags(_rm, _rs) \ + mips_emit_sltiu(reg_temp, arm_to_mips_reg[_rs], 32); \ + mips_emit_sllv(reg_a0, arm_to_mips_reg[_rm], arm_to_mips_reg[_rs]); \ + mips_emit_movz(reg_a0, reg_zero, reg_temp) \ + +#define generate_shift_reg_lsr_no_flags(_rm, _rs) \ + mips_emit_sltiu(reg_temp, arm_to_mips_reg[_rs], 32); \ + mips_emit_srlv(reg_a0, arm_to_mips_reg[_rm], arm_to_mips_reg[_rs]); \ + mips_emit_movz(reg_a0, reg_zero, reg_temp) \ + +#define generate_shift_reg_asr_no_flags(_rm, _rs) \ + mips_emit_sltiu(reg_temp, arm_to_mips_reg[_rs], 32); \ + mips_emit_b(bne, reg_temp, reg_zero, 2); \ + mips_emit_srav(reg_a0, arm_to_mips_reg[_rm], arm_to_mips_reg[_rs]); \ + mips_emit_sra(reg_a0, reg_a0, 31) \ + +#define generate_shift_reg_ror_no_flags(_rm, _rs) \ + mips_emit_rotrv(reg_a0, arm_to_mips_reg[_rm], arm_to_mips_reg[_rs]) \ + +#define generate_shift_reg_lsl_flags(_rm, _rs) \ + generate_load_reg_pc(reg_a0, _rm, 12); \ + generate_load_reg_pc(reg_a1, _rs, 8); \ + generate_function_call_swap_delay(execute_lsl_flags_reg) \ + +#define generate_shift_reg_lsr_flags(_rm, _rs) \ + generate_load_reg_pc(reg_a0, _rm, 12); \ + generate_load_reg_pc(reg_a1, _rs, 8) \ + generate_function_call_swap_delay(execute_lsr_flags_reg) \ + +#define generate_shift_reg_asr_flags(_rm, _rs) \ + generate_load_reg_pc(reg_a0, _rm, 12); \ + generate_load_reg_pc(reg_a1, _rs, 8) \ + generate_function_call_swap_delay(execute_asr_flags_reg) \ + +#define generate_shift_reg_ror_flags(_rm, _rs) \ + mips_emit_b(beq, arm_to_mips_reg[_rs], reg_zero, 3); \ + mips_emit_addiu(reg_temp, arm_to_mips_reg[_rs], -1); \ + mips_emit_srlv(reg_temp, arm_to_mips_reg[_rm], reg_temp); \ + mips_emit_andi(reg_c_cache, reg_temp, 1); \ + mips_emit_rotrv(reg_a0, arm_to_mips_reg[_rm], arm_to_mips_reg[_rs]) \ + +#define generate_shift_imm(arm_reg, name, flags_op) \ + u32 shift = (opcode >> 7) & 0x1F; \ + generate_shift_imm_##name##_##flags_op(arm_reg, rm, shift) \ + +#define generate_shift_reg(arm_reg, name, flags_op) \ + u32 rs = ((opcode >> 8) & 0x0F); \ + generate_shift_reg_##name##_##flags_op(rm, rs); \ + rm = arm_reg \ + +// Made functions due to the macro expansion getting too large. +// Returns a new rm if it redirects it (which will happen on most of these +// cases) + +#define generate_load_rm_sh_builder(flags_op) \ +u32 generate_load_rm_sh_##flags_op(u32 rm) \ +{ \ + switch((opcode >> 4) & 0x07) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + generate_shift_imm(arm_reg_a0, lsl, flags_op); \ + break; \ + } \ + \ + /* LSL reg */ \ + case 0x1: \ + { \ + generate_shift_reg(arm_reg_a0, lsl, flags_op); \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x2: \ + { \ + generate_shift_imm(arm_reg_a0, lsr, flags_op); \ + break; \ + } \ + \ + /* LSR reg */ \ + case 0x3: \ + { \ + generate_shift_reg(arm_reg_a0, lsr, flags_op); \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x4: \ + { \ + generate_shift_imm(arm_reg_a0, asr, flags_op); \ + break; \ + } \ + \ + /* ASR reg */ \ + case 0x5: \ + { \ + generate_shift_reg(arm_reg_a0, asr, flags_op); \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x6: \ + { \ + generate_shift_imm(arm_reg_a0, ror, flags_op); \ + break; \ + } \ + \ + /* ROR reg */ \ + case 0x7: \ + { \ + generate_shift_reg(arm_reg_a0, ror, flags_op); \ + break; \ + } \ + } \ + \ + return rm; \ +} \ + +#define read_memory_constant_u8(address) \ + read_memory8(address) \ + +#define read_memory_constant_u16(address) \ + read_memory16(address) \ + +#define read_memory_constant_u32(address) \ + read_memory32(address) \ + +#define read_memory_constant_s8(address) \ + (s8)read_memory8(address) \ + +#define read_memory_constant_s16(address) \ + (s16)read_memory16_signed(address) \ + +#define generate_load_memory_u8(ireg, offset) \ + mips_emit_lbu(ireg, ireg, offset) \ + +#define generate_load_memory_u16(ireg, offset) \ + mips_emit_lhu(ireg, ireg, offset) \ + +#define generate_load_memory_u32(ireg, offset) \ + mips_emit_lw(ireg, ireg, offset) \ + +#define generate_load_memory_s8(ireg, offset) \ + mips_emit_lb(ireg, ireg, offset) \ + +#define generate_load_memory_s16(ireg, offset) \ + mips_emit_lh(ireg, ireg, offset) \ + +#define generate_load_memory(type, ireg, address) \ +{ \ + u32 _address = (u32)(address); \ + u32 _address_hi = (_address + 0x8000) >> 16; \ + generate_load_imm(ireg, address); \ + mips_emit_lui(ireg, _address_hi >> 16) \ + generate_load_memory_##type(ireg, _address - (_address_hi << 16)); \ +} \ + +#define generate_known_address_load_builder(type) \ + u32 generate_known_address_load_##type(u32 rd, u32 address) \ + { \ + switch(address >> 24) \ + { \ + /* Read from the BIOS ROM, can be converted to an immediate load. \ + Only really possible to do this from the BIOS but should be okay \ + to allow it everywhere */ \ + case 0x00: \ + u32 imm = read_memory_constant_##type(address); \ + generate_load_imm(arm_to_mips_reg[rd], imm); \ + return 1; \ + \ + /* Read from RAM, can be converted to a load */ \ + case 0x02: \ + generate_load_memory(type, arm_to_mips_reg[rd], (u8 *)ewram + \ + (address & 0x7FFF) + ((address & 0x38000) * 2) + 0x8000); \ + return 1; \ + \ + case 0x03: \ + generate_load_memory(type, arm_to_mips_reg[rd], (u8 *)iwram + \ + (address & 0x7FFF) + 0x8000); \ + return 1; \ + \ + /* Read from gamepak ROM, this has to be an immediate load because \ + it might not actually be in memory anymore when we get to it. */ \ + case 0x08: \ + u32 imm = read_memory_constant_##type(address); \ + generate_load_imm(arm_to_mips_reg[rd], imm); \ + return 1; \ + \ + default: \ + return 0; \ + } \ + } \ + +#define generate_block_extra_vars() \ + u32 stored_pc = pc; \ + u8 *update_trampoline \ + +#define generate_block_extra_vars_arm() \ + generate_block_extra_vars(); \ + generate_load_rm_sh_builder(flags); \ + generate_load_rm_sh_builder(no_flags); \ + \ +/* generate_known_address_load_builder(u8); \ + generate_known_address_load_builder(u16); \ + generate_known_address_load_builder(u32); \ + generate_known_address_load_builder(s8); \ + generate_known_address_load_builder(s16); */ \ + \ + u32 generate_load_offset_sh(u32 rm) \ + { \ + switch((opcode >> 5) & 0x03) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + generate_shift_imm(arm_reg_a1, lsl, no_flags); \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x1: \ + { \ + generate_shift_imm(arm_reg_a1, lsr, no_flags); \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x2: \ + { \ + generate_shift_imm(arm_reg_a1, asr, no_flags); \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x3: \ + { \ + generate_shift_imm(arm_reg_a1, ror, no_flags); \ + break; \ + } \ + } \ + \ + return rm; \ + } \ + \ + void generate_indirect_branch_arm() \ + { \ + if(condition == 0x0E) \ + { \ + generate_indirect_branch_cycle_update(arm); \ + } \ + else \ + { \ + generate_indirect_branch_no_cycle_update(arm); \ + } \ + } \ + \ + void generate_indirect_branch_dual() \ + { \ + if(condition == 0x0E) \ + { \ + generate_indirect_branch_cycle_update(dual); \ + } \ + else \ + { \ + generate_indirect_branch_no_cycle_update(dual); \ + } \ + } \ + +#define generate_block_extra_vars_thumb() \ + generate_block_extra_vars() \ + +// It should be okay to still generate result flags, spsr will overwrite them. +// This is pretty infrequent (returning from interrupt handlers, et al) so +// probably not worth optimizing for. + +u32 execute_spsr_restore_body(u32 address) +{ + set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); + if((io_registers[REG_IE] & io_registers[REG_IF]) && + io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) + { + reg_mode[MODE_IRQ][6] = address + 4; + spsr[MODE_IRQ] = reg[REG_CPSR]; + reg[REG_CPSR] = 0xD2; + address = 0x00000018; + set_cpu_mode(MODE_IRQ); + } + + if(reg[REG_CPSR] & 0x20) + address |= 0x01; + + return address; +} + +typedef enum +{ + CONDITION_TRUE, + CONDITION_FALSE, + CONDITION_EQUAL, + CONDITION_NOT_EQUAL +} condition_check_type; + + +#define generate_condition_eq() \ + mips_emit_b_filler(beq, reg_z_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_ne() \ + mips_emit_b_filler(bne, reg_z_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_cs() \ + mips_emit_b_filler(beq, reg_c_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_cc() \ + mips_emit_b_filler(bne, reg_c_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_mi() \ + mips_emit_b_filler(beq, reg_n_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_pl() \ + mips_emit_b_filler(bne, reg_n_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_vs() \ + mips_emit_b_filler(beq, reg_v_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_vc() \ + mips_emit_b_filler(bne, reg_v_cache, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_hi() \ + mips_emit_xori(reg_temp, reg_c_cache, 1); \ + mips_emit_or(reg_temp, reg_temp, reg_z_cache); \ + mips_emit_b_filler(bne, reg_temp, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_ls() \ + mips_emit_xori(reg_temp, reg_c_cache, 1); \ + mips_emit_or(reg_temp, reg_temp, reg_z_cache); \ + mips_emit_b_filler(beq, reg_temp, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_ge() \ + mips_emit_b_filler(bne, reg_n_cache, reg_v_cache, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_lt() \ + mips_emit_b_filler(beq, reg_n_cache, reg_v_cache, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_gt() \ + mips_emit_xor(reg_temp, reg_n_cache, reg_v_cache); \ + mips_emit_or(reg_temp, reg_temp, reg_z_cache); \ + mips_emit_b_filler(bne, reg_temp, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition_le() \ + mips_emit_xor(reg_temp, reg_n_cache, reg_v_cache); \ + mips_emit_or(reg_temp, reg_temp, reg_z_cache); \ + mips_emit_b_filler(beq, reg_temp, reg_zero, backpatch_address); \ + generate_cycle_update_force() \ + +#define generate_condition() \ + switch(condition) \ + { \ + case 0x0: \ + generate_condition_eq(); \ + break; \ + \ + case 0x1: \ + generate_condition_ne(); \ + break; \ + \ + case 0x2: \ + generate_condition_cs(); \ + break; \ + \ + case 0x3: \ + generate_condition_cc(); \ + break; \ + \ + case 0x4: \ + generate_condition_mi(); \ + break; \ + \ + case 0x5: \ + generate_condition_pl(); \ + break; \ + \ + case 0x6: \ + generate_condition_vs(); \ + break; \ + \ + case 0x7: \ + generate_condition_vc(); \ + break; \ + \ + case 0x8: \ + generate_condition_hi(); \ + break; \ + \ + case 0x9: \ + generate_condition_ls(); \ + break; \ + \ + case 0xA: \ + generate_condition_ge(); \ + break; \ + \ + case 0xB: \ + generate_condition_lt(); \ + break; \ + \ + case 0xC: \ + generate_condition_gt(); \ + break; \ + \ + case 0xD: \ + generate_condition_le(); \ + break; \ + \ + case 0xE: \ + break; \ + \ + case 0xF: \ + break; \ + } \ + +#define generate_branch() \ +{ \ + if(condition == 0x0E) \ + { \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + } \ + else \ + { \ + generate_branch_no_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + } \ + block_exit_position++; \ +} \ + +#define generate_op_and_reg(_rd, _rn, _rm) \ + mips_emit_and(_rd, _rn, _rm) \ + +#define generate_op_orr_reg(_rd, _rn, _rm) \ + mips_emit_or(_rd, _rn, _rm) \ + +#define generate_op_eor_reg(_rd, _rn, _rm) \ + mips_emit_xor(_rd, _rn, _rm) \ + +#define generate_op_bic_reg(_rd, _rn, _rm) \ + mips_emit_nor(reg_temp, _rm, reg_zero); \ + mips_emit_and(_rd, _rn, reg_temp) \ + +#define generate_op_sub_reg(_rd, _rn, _rm) \ + mips_emit_subu(_rd, _rn, _rm) \ + +#define generate_op_rsb_reg(_rd, _rn, _rm) \ + mips_emit_subu(_rd, _rm, _rn) \ + +#define generate_op_sbc_reg(_rd, _rn, _rm) \ + mips_emit_subu(_rd, _rn, _rm); \ + mips_emit_xori(reg_temp, reg_c_cache, 1); \ + mips_emit_subu(_rd, _rd, reg_temp) \ + +#define generate_op_rsc_reg(_rd, _rn, _rm) \ + mips_emit_addu(reg_temp, _rm, reg_c_cache); \ + mips_emit_addiu(reg_temp, reg_temp, -1); \ + mips_emit_subu(_rd, reg_temp, _rn) \ + +#define generate_op_add_reg(_rd, _rn, _rm) \ + mips_emit_addu(_rd, _rn, _rm) \ + +#define generate_op_adc_reg(_rd, _rn, _rm) \ + mips_emit_addu(reg_temp, _rm, reg_c_cache); \ + mips_emit_addu(_rd, _rn, reg_temp) \ + +#define generate_op_mov_reg(_rd, _rn, _rm) \ + mips_emit_addu(_rd, _rm, reg_zero) \ + +#define generate_op_mvn_reg(_rd, _rn, _rm) \ + mips_emit_nor(_rd, _rm, reg_zero) \ + +#define generate_op_imm_wrapper(name, _rd, _rn) \ + if(imm != 0) \ + { \ + generate_load_imm(reg_a0, imm); \ + generate_op_##name##_reg(_rd, _rn, reg_a0); \ + } \ + else \ + { \ + generate_op_##name##_reg(_rd, _rn, reg_zero); \ + } \ + +#define generate_op_and_imm(_rd, _rn) \ + generate_alu_immu(andi, and, _rd, _rn, imm) \ + +#define generate_op_orr_imm(_rd, _rn) \ + generate_alu_immu(ori, or, _rd, _rn, imm) \ + +#define generate_op_eor_imm(_rd, _rn) \ + generate_alu_immu(xori, xor, _rd, _rn, imm) \ + +#define generate_op_bic_imm(_rd, _rn) \ + generate_alu_immu(andi, and, _rd, _rn, (~imm)) \ + +#define generate_op_sub_imm(_rd, _rn) \ + generate_alu_imm(addiu, addu, _rd, _rn, (-imm)) \ + +#define generate_op_rsb_imm(_rd, _rn) \ + if(imm != 0) \ + { \ + generate_load_imm(reg_temp, imm); \ + mips_emit_subu(_rd, reg_temp, _rn); \ + } \ + else \ + { \ + mips_emit_subu(_rd, reg_zero, _rn); \ + } \ + +#define generate_op_sbc_imm(_rd, _rn) \ + generate_op_imm_wrapper(sbc, _rd, _rn) \ + +#define generate_op_rsc_imm(_rd, _rn) \ + generate_op_imm_wrapper(rsc, _rd, _rn) \ + +#define generate_op_add_imm(_rd, _rn) \ + generate_alu_imm(addiu, addu, _rd, _rn, imm) \ + +#define generate_op_adc_imm(_rd, _rn) \ + generate_op_imm_wrapper(adc, _rd, _rn) \ + +#define generate_op_mov_imm(_rd, _rn) \ + generate_load_imm(_rd, imm) \ + +#define generate_op_mvn_imm(_rd, _rn) \ + generate_load_imm(_rd, (~imm)) \ + +#define generate_op_logic_flags(_rd) \ + if(check_generate_n_flag) \ + { \ + mips_emit_srl(reg_n_cache, _rd, 31); \ + } \ + if(check_generate_z_flag) \ + { \ + mips_emit_sltiu(reg_z_cache, _rd, 1); \ + } \ + +#define generate_op_sub_flags_prologue(_rn, _rm) \ + if(check_generate_c_flag) \ + { \ + mips_emit_sltu(reg_c_cache, _rn, _rm); \ + mips_emit_xori(reg_c_cache, reg_c_cache, 1); \ + } \ + if(check_generate_v_flag) \ + { \ + mips_emit_slt(reg_v_cache, _rn, _rm); \ + } \ + +#define generate_op_sub_flags_epilogue(_rd) \ + generate_op_logic_flags(_rd); \ + if(check_generate_v_flag) \ + { \ + if(!check_generate_n_flag) \ + { \ + mips_emit_srl(reg_n_cache, _rd, 31); \ + } \ + mips_emit_xor(reg_v_cache, reg_v_cache, reg_n_cache); \ + } \ + +#define generate_add_flags_prologue(_rn, _rm) \ + if(check_generate_c_flag | check_generate_v_flag) \ + { \ + mips_emit_addu(reg_c_cache, _rn, reg_zero); \ + } \ + if(check_generate_v_flag) \ + { \ + mips_emit_slt(reg_v_cache, _rm, reg_zero); \ + } \ + +#define generate_add_flags_epilogue(_rd) \ + if(check_generate_v_flag) \ + { \ + mips_emit_slt(reg_a0, _rd, reg_c_cache); \ + mips_emit_xor(reg_v_cache, reg_v_cache, reg_a0); \ + } \ + if(check_generate_c_flag) \ + { \ + mips_emit_sltu(reg_c_cache, _rd, reg_c_cache); \ + } \ + generate_op_logic_flags(_rd) \ + +#define generate_op_ands_reg(_rd, _rn, _rm) \ + mips_emit_and(_rd, _rn, _rm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_orrs_reg(_rd, _rn, _rm) \ + mips_emit_or(_rd, _rn, _rm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_eors_reg(_rd, _rn, _rm) \ + mips_emit_xor(_rd, _rn, _rm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_bics_reg(_rd, _rn, _rm) \ + mips_emit_nor(reg_temp, _rm, reg_zero); \ + mips_emit_and(_rd, _rn, reg_temp); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_subs_reg(_rd, _rn, _rm) \ + generate_op_sub_flags_prologue(_rn, _rm); \ + mips_emit_subu(_rd, _rn, _rm); \ + generate_op_sub_flags_epilogue(_rd) \ + +#define generate_op_rsbs_reg(_rd, _rn, _rm) \ + generate_op_sub_flags_prologue(_rm, _rn); \ + mips_emit_subu(_rd, _rm, _rn); \ + generate_op_sub_flags_epilogue(_rd) \ + +#define generate_op_sbcs_reg(_rd, _rn, _rm) \ + mips_emit_subu(_rd, _rn, _rm); \ + mips_emit_xori(reg_temp, reg_c_cache, 1); \ + generate_op_sub_flags_prologue(_rd, reg_temp); \ + mips_emit_subu(_rd, _rd, reg_temp); \ + generate_op_sub_flags_epilogue(_rd) \ + +#define generate_op_rscs_reg(_rd, _rn, _rm) \ + mips_emit_addu(reg_temp, _rm, reg_c_cache); \ + mips_emit_addiu(reg_temp, reg_temp, -1); \ + generate_op_sub_flags_prologue(reg_temp, _rn); \ + mips_emit_subu(_rd, reg_temp, _rn); \ + generate_op_sub_flags_epilogue(_rd) \ + +#define generate_op_adds_reg(_rd, _rn, _rm) \ + generate_add_flags_prologue(_rn, _rm); \ + mips_emit_addu(_rd, _rn, _rm); \ + generate_add_flags_epilogue(_rd) \ + +#define generate_op_adcs_reg(_rd, _rn, _rm) \ + mips_emit_addu(reg_temp, _rm, reg_c_cache); \ + generate_add_flags_prologue(_rn, _rm); \ + mips_emit_addu(_rd, _rn, reg_temp); \ + generate_add_flags_epilogue(_rd) \ + +#define generate_op_movs_reg(_rd, _rn, _rm) \ + mips_emit_addu(_rd, _rm, reg_zero); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_mvns_reg(_rd, _rn, _rm) \ + mips_emit_nor(_rd, _rm, reg_zero); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_neg_reg(_rd, _rn, _rm) \ + generate_op_subs_reg(_rd, reg_zero, _rm) \ + +#define generate_op_muls_reg(_rd, _rn, _rm) \ + mips_emit_multu(_rn, _rm); \ + mips_emit_mflo(_rd); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_cmp_reg(_rd, _rn, _rm) \ + generate_op_subs_reg(reg_temp, _rn, _rm) \ + +#define generate_op_cmn_reg(_rd, _rn, _rm) \ + generate_op_adds_reg(reg_temp, _rn, _rm) \ + +#define generate_op_tst_reg(_rd, _rn, _rm) \ + generate_op_ands_reg(reg_temp, _rn, _rm) \ + +#define generate_op_teq_reg(_rd, _rn, _rm) \ + generate_op_eors_reg(reg_temp, _rn, _rm) \ + +#define generate_op_ands_imm(_rd, _rn) \ + generate_alu_immu(andi, and, _rd, _rn, imm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_orrs_imm(_rd, _rn) \ + generate_alu_immu(ori, or, _rd, _rn, imm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_eors_imm(_rd, _rn) \ + generate_alu_immu(xori, xor, _rd, _rn, imm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_bics_imm(_rd, _rn) \ + generate_alu_immu(andi, and, _rd, _rn, (~imm)); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_subs_imm(_rd, _rn) \ + generate_op_imm_wrapper(subs, _rd, _rn) \ + +#define generate_op_rsbs_imm(_rd, _rn) \ + generate_op_imm_wrapper(rsbs, _rd, _rn) \ + +#define generate_op_sbcs_imm(_rd, _rn) \ + generate_op_imm_wrapper(sbcs, _rd, _rn) \ + +#define generate_op_rscs_imm(_rd, _rn) \ + generate_op_imm_wrapper(rscs, _rd, _rn) \ + +#define generate_op_adds_imm(_rd, _rn) \ + generate_op_imm_wrapper(adds, _rd, _rn) \ + +#define generate_op_adcs_imm(_rd, _rn) \ + generate_op_imm_wrapper(adcs, _rd, _rn) \ + +#define generate_op_movs_imm(_rd, _rn) \ + generate_load_imm(_rd, imm); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_mvns_imm(_rd, _rn) \ + generate_load_imm(_rd, (~imm)); \ + generate_op_logic_flags(_rd) \ + +#define generate_op_cmp_imm(_rd, _rn) \ + generate_op_imm_wrapper(cmp, _rd, _rn) \ + +#define generate_op_cmn_imm(_rd, _rn) \ + generate_op_imm_wrapper(cmn, _rd, _rn) \ + +#define generate_op_tst_imm(_rd, _rn) \ + generate_op_ands_imm(reg_temp, _rn) \ + +#define generate_op_teq_imm(_rd, _rn) \ + generate_op_eors_imm(reg_temp, _rn) \ + +#define arm_generate_op_load_yes() \ + generate_load_reg_pc(reg_a1, rn, 8) \ + +#define arm_generate_op_load_no() \ + +#define arm_op_check_yes() \ + check_load_reg_pc(arm_reg_a1, rn, 8) \ + +#define arm_op_check_no() \ + +#define arm_generate_op_reg_flags(name, load_op) \ + arm_decode_data_proc_reg(); \ + if(check_generate_c_flag) \ + { \ + rm = generate_load_rm_sh_flags(rm); \ + } \ + else \ + { \ + rm = generate_load_rm_sh_no_flags(rm); \ + } \ + \ + arm_op_check_##load_op(); \ + generate_op_##name##_reg(arm_to_mips_reg[rd], arm_to_mips_reg[rn], \ + arm_to_mips_reg[rm]) \ + +#define arm_generate_op_reg(name, load_op) \ + arm_decode_data_proc_reg(); \ + rm = generate_load_rm_sh_no_flags(rm); \ + arm_op_check_##load_op(); \ + generate_op_##name##_reg(arm_to_mips_reg[rd], arm_to_mips_reg[rn], \ + arm_to_mips_reg[rm]) \ + +#define arm_generate_op_imm(name, load_op) \ + arm_decode_data_proc_imm(); \ + arm_op_check_##load_op(); \ + generate_op_##name##_imm(arm_to_mips_reg[rd], arm_to_mips_reg[rn]) \ + +#define arm_data_proc(name, type, flags_op) \ +{ \ + arm_generate_op_##type(name, yes); \ + check_store_reg_pc_##flags_op(rd); \ +} \ + +#define arm_data_proc_test(name, type) \ +{ \ + arm_generate_op_##type(name, yes); \ +} \ + +#define arm_data_proc_unary(name, type, flags_op) \ +{ \ + arm_generate_op_##type(name, no); \ + check_store_reg_pc_##flags_op(rd); \ +} \ + +#define arm_multiply_flags_yes(_rd) \ + generate_op_logic_flags(_rd) \ + +#define arm_multiply_flags_no(_rd) \ + +#define arm_multiply_add_no() \ + mips_emit_mflo(arm_to_mips_reg[rd]) \ + +#define arm_multiply_add_yes() \ + mips_emit_mflo(reg_temp); \ + mips_emit_addu(arm_to_mips_reg[rd], reg_temp, arm_to_mips_reg[rn]) \ + +#define arm_multiply(add_op, flags) \ +{ \ + arm_decode_multiply(); \ + mips_emit_multu(arm_to_mips_reg[rm], arm_to_mips_reg[rs]); \ + arm_multiply_add_##add_op(); \ + arm_multiply_flags_##flags(arm_to_mips_reg[rd]); \ +} \ + +#define arm_multiply_long_flags_yes(_rdlo, _rdhi) \ + mips_emit_sltiu(reg_z_cache, _rdlo, 1); \ + mips_emit_sltiu(reg_a0, _rdhi, 1); \ + mips_emit_and(reg_z_cache, reg_z_cache, reg_a0); \ + mips_emit_srl(reg_n_cache, _rdhi, 31); \ + +#define arm_multiply_long_flags_no(_rdlo, _rdhi) \ + +#define arm_multiply_long_add_yes(name) \ + mips_emit_mtlo(arm_to_mips_reg[rdlo]); \ + mips_emit_mthi(arm_to_mips_reg[rdhi]); \ + generate_multiply_##name() \ + +#define arm_multiply_long_add_no(name) \ + generate_multiply_##name() \ + +#define arm_multiply_long(name, add_op, flags) \ +{ \ + arm_decode_multiply_long(); \ + arm_multiply_long_add_##add_op(name); \ + mips_emit_mflo(arm_to_mips_reg[rdlo]); \ + mips_emit_mfhi(arm_to_mips_reg[rdhi]); \ + arm_multiply_long_flags_##flags(arm_to_mips_reg[rdlo], \ + arm_to_mips_reg[rdhi]); \ +} \ + +#define arm_psr_read(op_type, psr_reg) \ + generate_function_call(execute_read_##psr_reg); \ + generate_store_reg(reg_rv, rd) \ + +u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) +{ + reg[REG_CPSR] = _cpsr; + if(store_mask & 0xFF) + { + set_cpu_mode(cpu_modes[_cpsr & 0x1F]); + if((io_registers[REG_IE] & io_registers[REG_IF]) && + io_registers[REG_IME] && ((_cpsr & 0x80) == 0)) + { + reg_mode[MODE_IRQ][6] = address + 4; + spsr[MODE_IRQ] = _cpsr; + reg[REG_CPSR] = 0xD2; + set_cpu_mode(MODE_IRQ); + return 0x00000018; + } + } + + return 0; +} + +#define arm_psr_load_new_reg() \ + generate_load_reg(reg_a0, rm) \ + +#define arm_psr_load_new_imm() \ + generate_load_imm(reg_a0, imm) \ + +#define arm_psr_store(op_type, psr_reg) \ + arm_psr_load_new_##op_type(); \ + generate_load_imm(reg_a1, psr_masks[psr_field]); \ + generate_load_pc(reg_a2, (pc + 4)); \ + generate_function_call_swap_delay(execute_store_##psr_reg) \ + +#define arm_psr(op_type, transfer_type, psr_reg) \ +{ \ + arm_decode_psr_##op_type(); \ + arm_psr_##transfer_type(op_type, psr_reg); \ +} \ + +#define arm_access_memory_load(mem_type) \ + cycle_count += 2; \ + mips_emit_jal(mips_absolute_offset(execute_load_##mem_type)); \ + generate_load_pc(reg_a1, (pc + 8)); \ + generate_store_reg(reg_rv, rd); \ + check_store_reg_pc_no_flags(rd) \ + +#define arm_access_memory_store(mem_type) \ + cycle_count++; \ + generate_load_pc(reg_a2, (pc + 4)); \ + generate_load_reg_pc(reg_a1, rd, 12); \ + generate_function_call_swap_delay(execute_store_##mem_type) \ + +#define arm_access_memory_reg_pre_up() \ + mips_emit_addu(reg_a0, arm_to_mips_reg[rn], arm_to_mips_reg[rm]) \ + +#define arm_access_memory_reg_pre_down() \ + mips_emit_subu(reg_a0, arm_to_mips_reg[rn], arm_to_mips_reg[rm]) \ + +#define arm_access_memory_reg_pre(adjust_dir) \ + check_load_reg_pc(arm_reg_a0, rn, 8); \ + arm_access_memory_reg_pre_##adjust_dir() \ + +#define arm_access_memory_reg_pre_wb(adjust_dir) \ + arm_access_memory_reg_pre(adjust_dir); \ + generate_store_reg(reg_a0, rn) \ + +#define arm_access_memory_reg_post_up() \ + mips_emit_addu(arm_to_mips_reg[rn], arm_to_mips_reg[rn], \ + arm_to_mips_reg[rm]) \ + +#define arm_access_memory_reg_post_down() \ + mips_emit_subu(arm_to_mips_reg[rn], arm_to_mips_reg[rn], \ + arm_to_mips_reg[rm]) \ + +#define arm_access_memory_reg_post(adjust_dir) \ + generate_load_reg(reg_a0, rn); \ + arm_access_memory_reg_post_##adjust_dir() \ + +#define arm_access_memory_imm_pre_up() \ + mips_emit_addiu(reg_a0, arm_to_mips_reg[rn], offset) \ + +#define arm_access_memory_imm_pre_down() \ + mips_emit_addiu(reg_a0, arm_to_mips_reg[rn], -offset) \ + +#define arm_access_memory_imm_pre(adjust_dir) \ + check_load_reg_pc(arm_reg_a0, rn, 8); \ + arm_access_memory_imm_pre_##adjust_dir() \ + +#define arm_access_memory_imm_pre_wb(adjust_dir) \ + arm_access_memory_imm_pre(adjust_dir); \ + generate_store_reg(reg_a0, rn) \ + +#define arm_access_memory_imm_post_up() \ + mips_emit_addiu(arm_to_mips_reg[rn], arm_to_mips_reg[rn], offset) \ + +#define arm_access_memory_imm_post_down() \ + mips_emit_addiu(arm_to_mips_reg[rn], arm_to_mips_reg[rn], -offset) \ + +#define arm_access_memory_imm_post(adjust_dir) \ + generate_load_reg(reg_a0, rn); \ + arm_access_memory_imm_post_##adjust_dir() \ + +#define arm_data_trans_reg(adjust_op, adjust_dir) \ + arm_decode_data_trans_reg(); \ + rm = generate_load_offset_sh(rm); \ + arm_access_memory_reg_##adjust_op(adjust_dir) \ + +#define arm_data_trans_imm(adjust_op, adjust_dir) \ + arm_decode_data_trans_imm(); \ + arm_access_memory_imm_##adjust_op(adjust_dir) \ + +#define arm_data_trans_half_reg(adjust_op, adjust_dir) \ + arm_decode_half_trans_r(); \ + arm_access_memory_reg_##adjust_op(adjust_dir) \ + +#define arm_data_trans_half_imm(adjust_op, adjust_dir) \ + arm_decode_half_trans_of(); \ + arm_access_memory_imm_##adjust_op(adjust_dir) \ + +#define arm_access_memory(access_type, direction, adjust_op, mem_type, \ + offset_type) \ +{ \ + arm_data_trans_##offset_type(adjust_op, direction); \ + arm_access_memory_##access_type(mem_type); \ +} \ + +#define word_bit_count(word) \ + (bit_count[word >> 8] + bit_count[word & 0xFF]) \ + +#define sprint_no(access_type, pre_op, post_op, wb) \ + +#define sprint_yes(access_type, pre_op, post_op, wb) \ + printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \ + +#define arm_block_memory_load() \ + generate_function_call_swap_delay(execute_aligned_load32); \ + generate_store_reg(reg_rv, i) \ + +#define arm_block_memory_store() \ + generate_load_reg_pc(reg_a1, i, 8); \ + generate_function_call_swap_delay(execute_aligned_store32) \ + +#define arm_block_memory_final_load() \ + arm_block_memory_load() \ + +#define arm_block_memory_final_store() \ + generate_load_pc(reg_a2, (pc + 4)); \ + mips_emit_jal(mips_absolute_offset(execute_store_u32)); \ + generate_load_reg(reg_a1, i) \ + +#define arm_block_memory_adjust_pc_store() \ + +#define arm_block_memory_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_mov(reg_a0, reg_rv); \ + generate_indirect_branch_arm(); \ + } \ + +#define arm_block_memory_sp_load() \ + mips_emit_lw(arm_to_mips_reg[i], reg_a1, offset); \ + +#define arm_block_memory_sp_store() \ +{ \ + u32 store_reg = i; \ + check_load_reg_pc(arm_reg_a0, store_reg, 8); \ + mips_emit_sw(arm_to_mips_reg[store_reg], reg_a1, offset); \ +} \ + +#define arm_block_memory_sp_adjust_pc_store() \ + +#define arm_block_memory_sp_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_indirect_branch_arm(); \ + } \ + +#define arm_block_memory_offset_down_a() \ + mips_emit_addiu(reg_a2, base_reg, (-((word_bit_count(reg_list) * 4) - 4))) \ + +#define arm_block_memory_offset_down_b() \ + mips_emit_addiu(reg_a2, base_reg, (word_bit_count(reg_list) * -4)) \ + +#define arm_block_memory_offset_no() \ + mips_emit_addu(reg_a2, base_reg, reg_zero) \ + +#define arm_block_memory_offset_up() \ + mips_emit_addiu(reg_a2, base_reg, 4) \ + +#define arm_block_memory_writeback_down() \ + mips_emit_addiu(base_reg, base_reg, (-(word_bit_count(reg_list) * 4))) \ + +#define arm_block_memory_writeback_up() \ + mips_emit_addiu(base_reg, base_reg, (word_bit_count(reg_list) * 4)) \ + +#define arm_block_memory_writeback_no() + +// Only emit writeback if the register is not in the list + +#define arm_block_memory_writeback_load(writeback_type) \ + if(!((reg_list >> rn) & 0x01)) \ + { \ + arm_block_memory_writeback_##writeback_type(); \ + } \ + +#define arm_block_memory_writeback_store(writeback_type) \ + arm_block_memory_writeback_##writeback_type() \ + +#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \ +{ \ + arm_decode_block_trans(); \ + u32 i; \ + u32 offset = 0; \ + u32 base_reg = arm_to_mips_reg[rn]; \ + \ + arm_block_memory_offset_##offset_type(); \ + arm_block_memory_writeback_##access_type(writeback_type); \ + \ + if((rn == REG_SP) && iwram_stack_optimize) \ + { \ + mips_emit_andi(reg_a1, reg_a2, 0x7FFC); \ + generate_load_imm(reg_a0, ((u32)(iwram + 0x8000))); \ + mips_emit_addu(reg_a1, reg_a1, reg_a0); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + arm_block_memory_sp_##access_type(); \ + offset += 4; \ + } \ + } \ + \ + arm_block_memory_sp_adjust_pc_##access_type(); \ + } \ + else \ + { \ + mips_emit_ins(reg_a2, reg_zero, 0, 2); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + mips_emit_addiu(reg_a0, reg_a2, offset); \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + arm_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + arm_block_memory_final_##access_type(); \ + break; \ + } \ + } \ + } \ + \ + arm_block_memory_adjust_pc_##access_type(); \ + } \ +} \ + +#define arm_block_writeback_no() + +#define arm_block_writeback_yes() \ + mips_emit_addu(arm_to_mips_reg[rn], reg_a2, reg_zero) \ + +#define arm_block_address_preadjust_up_full(wb) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \ + ((word_bit_count(reg_list)) * 4)); \ + arm_block_writeback_##wb() \ + +#define arm_block_address_preadjust_up(wb) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], 4); \ + arm_block_writeback_##wb() \ + +#define arm_block_address_preadjust_down_full(wb) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \ + -((word_bit_count(reg_list)) * 4)); \ + arm_block_writeback_##wb() \ + +#define arm_block_address_preadjust_down(wb) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \ + -(((word_bit_count(reg_list)) * 4) - 4)); \ + arm_block_writeback_##wb() + +#define arm_block_address_preadjust_no(wb) \ + mips_emit_addu(reg_a2, arm_to_mips_reg[rn], reg_zero) \ + +#define arm_block_address_postadjust_no() \ + +#define arm_block_address_postadjust_up() \ + mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \ + ((word_bit_count(reg_list)) * 4)) \ + +#define arm_block_address_postadjust_down() \ + mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \ + -((word_bit_count(reg_list)) * 4)) \ + +#define sprint_no(access_type, pre_op, post_op, wb) \ + +#define sprint_yes(access_type, pre_op, post_op, wb) \ + printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \ + +#define arm_block_memory_load() \ + generate_function_call_swap_delay(execute_aligned_load32); \ + generate_store_reg(reg_rv, i) \ + +#define arm_block_memory_store() \ + generate_load_reg_pc(reg_a1, i, 8); \ + generate_function_call_swap_delay(execute_aligned_store32) \ + +#define arm_block_memory_final_load() \ + arm_block_memory_load() \ + +#define arm_block_memory_final_store() \ + generate_load_pc(reg_a2, (pc + 4)); \ + mips_emit_jal(mips_absolute_offset(execute_store_u32)); \ + generate_load_reg(reg_a1, i) \ + +#define arm_block_memory_adjust_pc_store() \ + +#define arm_block_memory_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_mov(reg_a0, reg_rv); \ + generate_indirect_branch_arm(); \ + } \ + +#define arm_block_memory_sp_load() \ + mips_emit_lw(arm_to_mips_reg[i], reg_a1, offset); \ + +#define arm_block_memory_sp_store() \ +{ \ + u32 store_reg = i; \ + check_load_reg_pc(arm_reg_a0, store_reg, 8); \ + mips_emit_sw(arm_to_mips_reg[store_reg], reg_a1, offset); \ +} \ + +#define arm_block_memory_sp_adjust_pc_store() \ + +#define arm_block_memory_sp_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_indirect_branch_arm(); \ + } \ + +#define old_arm_block_memory(access_type, pre_op, post_op, wb, s_bit) \ +{ \ + arm_decode_block_trans(); \ + u32 i; \ + u32 offset = 0; \ + u32 base_reg = arm_to_mips_reg[rn]; \ + \ + arm_block_address_preadjust_##pre_op(wb); \ + arm_block_address_postadjust_##post_op(); \ + \ + sprint_##s_bit(access_type, pre_op, post_op, wb); \ + \ + if((rn == REG_SP) && iwram_stack_optimize) \ + { \ + mips_emit_andi(reg_a1, reg_a2, 0x7FFC); \ + generate_load_imm(reg_a0, ((u32)(iwram + 0x8000))); \ + mips_emit_addu(reg_a1, reg_a1, reg_a0); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + arm_block_memory_sp_##access_type(); \ + offset += 4; \ + } \ + } \ + \ + arm_block_memory_sp_adjust_pc_##access_type(); \ + } \ + else \ + { \ + mips_emit_ins(reg_a2, reg_zero, 0, 2); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + mips_emit_addiu(reg_a0, reg_a2, offset); \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + arm_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + arm_block_memory_final_##access_type(); \ + break; \ + } \ + } \ + } \ + \ + arm_block_memory_adjust_pc_##access_type(); \ + } \ +} + + + +// This isn't really a correct implementation, may have to fix later. + +#define arm_swap(type) \ +{ \ + arm_decode_swap(); \ + cycle_count += 3; \ + mips_emit_jal(mips_absolute_offset(execute_load_##type)); \ + generate_load_reg(reg_a0, rn); \ + generate_mov(reg_a2, reg_rv); \ + generate_load_reg(reg_a0, rn); \ + mips_emit_jal(mips_absolute_offset(execute_store_##type)); \ + generate_load_reg(reg_a1, rm); \ + generate_store_reg(reg_a2, rd); \ +} \ + +#define thumb_generate_op_load_yes(_rs) \ + generate_load_reg(reg_a1, _rs) \ + +#define thumb_generate_op_load_no(_rs) \ + +#define thumb_generate_op_reg(name, _rd, _rs, _rn) \ + generate_op_##name##_reg(arm_to_mips_reg[_rd], \ + arm_to_mips_reg[_rs], arm_to_mips_reg[_rn]) \ + +#define thumb_generate_op_imm(name, _rd, _rs, _rn) \ + generate_op_##name##_imm(arm_to_mips_reg[_rd], arm_to_mips_reg[_rs]) \ + +// Types: add_sub, add_sub_imm, alu_op, imm +// Affects N/Z/C/V flags + +#define thumb_data_proc(type, name, rn_type, _rd, _rs, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_generate_op_##rn_type(name, _rd, _rs, _rn); \ +} \ + +#define thumb_data_proc_test(type, name, rn_type, _rs, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_generate_op_##rn_type(name, 0, _rs, _rn); \ +} \ + +#define thumb_data_proc_unary(type, name, rn_type, _rd, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_generate_op_##rn_type(name, _rd, 0, _rn); \ +} \ + +#define check_store_reg_pc_thumb(_rd) \ + if(_rd == REG_PC) \ + { \ + generate_indirect_branch_cycle_update(thumb); \ + } \ + +#define thumb_data_proc_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + u32 dest_rd = rd; \ + check_load_reg_pc(arm_reg_a0, rs, 4); \ + check_load_reg_pc(arm_reg_a1, rd, 4); \ + generate_op_##name##_reg(arm_to_mips_reg[dest_rd], arm_to_mips_reg[rd], \ + arm_to_mips_reg[rs]); \ + check_store_reg_pc_thumb(dest_rd); \ +} \ + +/* + +#define thumb_data_proc_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + check_load_reg_pc(arm_reg_a0, rs, 4); \ + check_load_reg_pc(arm_reg_a1, rd, 4); \ + generate_op_##name##_reg(arm_to_mips_reg[rd], arm_to_mips_reg[rd], \ + arm_to_mips_reg[rs]); \ + check_store_reg_pc_thumb(rd); \ +} \ + +*/ + +#define thumb_data_proc_test_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + check_load_reg_pc(arm_reg_a0, rs, 4); \ + check_load_reg_pc(arm_reg_a1, rd, 4); \ + generate_op_##name##_reg(reg_temp, arm_to_mips_reg[rd], \ + arm_to_mips_reg[rs]); \ +} \ + +#define thumb_data_proc_mov_hi() \ +{ \ + thumb_decode_hireg_op(); \ + check_load_reg_pc(arm_reg_a0, rs, 4); \ + mips_emit_addu(arm_to_mips_reg[rd], arm_to_mips_reg[rs], reg_zero); \ + check_store_reg_pc_thumb(rd); \ +} \ + +#define thumb_load_pc(_rd) \ +{ \ + thumb_decode_imm(); \ + generate_load_pc(arm_to_mips_reg[_rd], (((pc & ~2) + 4) + (imm * 4))); \ +} \ + +#define thumb_load_sp(_rd) \ +{ \ + thumb_decode_imm(); \ + mips_emit_addiu(arm_to_mips_reg[_rd], reg_r13, (imm * 4)); \ +} \ + +#define thumb_adjust_sp(value) \ +{ \ + thumb_decode_add_sp(); \ + mips_emit_addiu(reg_r13, reg_r13, (value)); \ +} \ + +// Decode types: shift, alu_op +// Operation types: lsl, lsr, asr, ror +// Affects N/Z/C flags + +#define thumb_generate_shift_imm(name) \ + if(check_generate_c_flag) \ + { \ + generate_shift_imm_##name##_flags(rd, rs, imm); \ + } \ + else \ + { \ + generate_shift_imm_##name##_no_flags(rd, rs, imm); \ + } \ + if(rs != rd) \ + { \ + mips_emit_addu(arm_to_mips_reg[rd], arm_to_mips_reg[rs], reg_zero); \ + } \ + +#define thumb_generate_shift_reg(name) \ +{ \ + u32 original_rd = rd; \ + if(check_generate_c_flag) \ + { \ + generate_shift_reg_##name##_flags(rd, rs); \ + } \ + else \ + { \ + generate_shift_reg_##name##_no_flags(rd, rs); \ + } \ + mips_emit_addu(arm_to_mips_reg[original_rd], reg_a0, reg_zero); \ +} \ + +#define thumb_shift(decode_type, op_type, value_type) \ +{ \ + thumb_decode_##decode_type(); \ + thumb_generate_shift_##value_type(op_type); \ + generate_op_logic_flags(arm_to_mips_reg[rd]); \ +} \ + +// Operation types: imm, mem_reg, mem_imm + +#define thumb_access_memory_load(mem_type, reg_rd) \ + cycle_count += 2; \ + mips_emit_jal(mips_absolute_offset(execute_load_##mem_type)); \ + generate_load_pc(reg_a1, (pc + 4)); \ + generate_store_reg(reg_rv, reg_rd) \ + +#define thumb_access_memory_store(mem_type, reg_rd) \ + cycle_count++; \ + generate_load_pc(reg_a2, (pc + 2)); \ + mips_emit_jal(mips_absolute_offset(execute_store_##mem_type)); \ + generate_load_reg(reg_a1, reg_rd) \ + +#define thumb_access_memory_generate_address_pc_relative(offset, reg_rb, \ + reg_ro) \ + generate_load_pc(reg_a0, (offset)) \ + +#define thumb_access_memory_generate_address_reg_imm(offset, reg_rb, reg_ro) \ + mips_emit_addiu(reg_a0, arm_to_mips_reg[reg_rb], (offset)) \ + +#define thumb_access_memory_generate_address_reg_reg(offset, reg_rb, reg_ro) \ + mips_emit_addu(reg_a0, arm_to_mips_reg[reg_rb], arm_to_mips_reg[reg_ro]) \ + +#define thumb_access_memory(access_type, op_type, reg_rd, reg_rb, reg_ro, \ + address_type, offset, mem_type) \ +{ \ + thumb_decode_##op_type(); \ + thumb_access_memory_generate_address_##address_type(offset, reg_rb, \ + reg_ro); \ + thumb_access_memory_##access_type(mem_type, reg_rd); \ +} \ + + +#define thumb_block_address_preadjust_no(base_reg) \ + mips_emit_addu(reg_a2, arm_to_mips_reg[base_reg], reg_zero) \ + +#define thumb_block_address_preadjust_up(base_reg) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[base_reg], \ + (bit_count[reg_list] * 4)); \ + mips_emit_addu(arm_to_mips_reg[base_reg], reg_a2, reg_zero) \ + +#define thumb_block_address_preadjust_down(base_reg) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[base_reg], \ + -(bit_count[reg_list] * 4)); \ + mips_emit_addu(arm_to_mips_reg[base_reg], reg_a2, reg_zero) \ + +#define thumb_block_address_preadjust_push_lr(base_reg) \ + mips_emit_addiu(reg_a2, arm_to_mips_reg[base_reg], \ + -((bit_count[reg_list] + 1) * 4)); \ + mips_emit_addu(arm_to_mips_reg[base_reg], reg_a2, reg_zero) \ + +#define thumb_block_address_postadjust_no(base_reg) \ + +#define thumb_block_address_postadjust_up(base_reg) \ + mips_emit_addiu(arm_to_mips_reg[base_reg], reg_a2, \ + (bit_count[reg_list] * 4)) \ + +#define thumb_block_address_postadjust_down(base_reg) \ + mips_emit_addiu(arm_to_mips_reg[base_reg], reg_a2, \ + -(bit_count[reg_list] * 4)) \ + +#define thumb_block_address_postadjust_pop_pc(base_reg) \ + mips_emit_addiu(arm_to_mips_reg[base_reg], reg_a2, \ + ((bit_count[reg_list] * 4) + 4)) \ + +#define thumb_block_address_postadjust_push_lr(base_reg) \ + +#define thumb_block_memory_load() \ + generate_function_call_swap_delay(execute_aligned_load32); \ + generate_store_reg(reg_rv, i) \ + +#define thumb_block_memory_store() \ + mips_emit_jal(mips_absolute_offset(execute_aligned_store32)); \ + generate_load_reg(reg_a1, i) \ + +#define thumb_block_memory_final_load() \ + thumb_block_memory_load() \ + +#define thumb_block_memory_final_store() \ + generate_load_pc(reg_a2, (pc + 2)); \ + mips_emit_jal(mips_absolute_offset(execute_store_u32)); \ + generate_load_reg(reg_a1, i) \ + +#define thumb_block_memory_final_no(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_up(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_down(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_push_lr(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory_final_pop_pc(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory_extra_no() \ + +#define thumb_block_memory_extra_up() \ + +#define thumb_block_memory_extra_down() \ + +#define thumb_block_memory_extra_push_lr() \ + mips_emit_addiu(reg_a0, reg_a2, (bit_count[reg_list] * 4)); \ + mips_emit_jal(mips_absolute_offset(execute_aligned_store32)); \ + generate_load_reg(reg_a1, REG_LR) \ + +#define thumb_block_memory_extra_pop_pc() \ + mips_emit_jal(mips_absolute_offset(execute_aligned_load32)); \ + mips_emit_addiu(reg_a0, reg_a2, (bit_count[reg_list] * 4)); \ + generate_mov(reg_a0, reg_rv); \ + generate_indirect_branch_cycle_update(thumb) \ + +#define thumb_block_memory_sp_load() \ + mips_emit_lw(arm_to_mips_reg[i], reg_a1, offset) \ + +#define thumb_block_memory_sp_store() \ + mips_emit_sw(arm_to_mips_reg[i], reg_a1, offset) \ + +#define thumb_block_memory_sp_extra_no() \ + +#define thumb_block_memory_sp_extra_up() \ + +#define thumb_block_memory_sp_extra_down() \ + +#define thumb_block_memory_sp_extra_pop_pc() \ + mips_emit_lw(reg_a0, reg_a1, (bit_count[reg_list] * 4)); \ + generate_indirect_branch_cycle_update(thumb) \ + +#define thumb_block_memory_sp_extra_push_lr() \ + mips_emit_sw(reg_r14, reg_a1, (bit_count[reg_list] * 4)) \ + +#define thumb_block_memory(access_type, pre_op, post_op, base_reg) \ +{ \ + thumb_decode_rlist(); \ + u32 i; \ + u32 offset = 0; \ + \ + thumb_block_address_preadjust_##pre_op(base_reg); \ + thumb_block_address_postadjust_##post_op(base_reg); \ + \ + if((base_reg == REG_SP) && iwram_stack_optimize) \ + { \ + mips_emit_andi(reg_a1, reg_a2, 0x7FFC); \ + generate_load_imm(reg_a0, ((u32)(iwram + 0x8000))); \ + generate_add(reg_a1, reg_a0); \ + \ + for(i = 0; i < 8; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + thumb_block_memory_sp_##access_type(); \ + offset += 4; \ + } \ + } \ + \ + thumb_block_memory_sp_extra_##post_op(); \ + } \ + else \ + { \ + mips_emit_ins(reg_a2, reg_zero, 0, 2); \ + \ + for(i = 0; i < 8; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + mips_emit_addiu(reg_a0, reg_a2, offset); \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + thumb_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + thumb_block_memory_final_##post_op(access_type); \ + break; \ + } \ + } \ + } \ + \ + thumb_block_memory_extra_##post_op(); \ + } \ +} + + + +#define thumb_conditional_branch(condition) \ +{ \ + condition_check_type condition_check; \ + generate_condition_##condition(); \ + generate_branch_no_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + generate_branch_patch_conditional(backpatch_address, translation_ptr); \ + block_exit_position++; \ +} \ + +#define arm_conditional_block_header() \ + generate_condition(); \ + +#define arm_b() \ + generate_branch() \ + +#define arm_bl() \ + generate_load_pc(reg_r14, (pc + 4)); \ + generate_branch() \ + +#define arm_bx() \ + arm_decode_branchx(); \ + generate_load_reg(reg_a0, rn); \ + /*generate_load_pc(reg_a2, pc);*/ \ + generate_indirect_branch_dual() \ + +#define arm_swi() \ + generate_swi_hle_handler((opcode >> 16) & 0xFF); \ + generate_load_pc(reg_a0, (pc + 4)); \ + generate_function_call_swap_delay(execute_swi); \ + generate_branch() \ + +#define thumb_b() \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +#define thumb_bl() \ + generate_load_pc(reg_r14, ((pc + 2) | 0x01)); \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +#define thumb_blh() \ +{ \ + thumb_decode_branch(); \ + generate_alu_imm(addiu, addu, reg_a0, reg_r14, (offset * 2)); \ + generate_load_pc(reg_r14, ((pc + 2) | 0x01)); \ + generate_indirect_branch_cycle_update(dual); \ + break; \ +} \ + +#define thumb_bx() \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(reg_a0, rs, 4); \ + /*generate_load_pc(reg_a2, pc);*/ \ + generate_indirect_branch_cycle_update(dual); \ +} \ + +#define thumb_swi() \ + generate_swi_hle_handler(opcode & 0xFF); \ + generate_load_pc(reg_a0, (pc + 2)); \ + generate_function_call_swap_delay(execute_swi); \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +u8 swi_hle_handle[256] = +{ + 0x0, // SWI 0: SoftReset + 0x0, // SWI 1: RegisterRAMReset + 0x0, // SWI 2: Halt + 0x0, // SWI 3: Stop/Sleep + 0x0, // SWI 4: IntrWait + 0x0, // SWI 5: VBlankIntrWait + 0x1, // SWI 6: Div + 0x0, // SWI 7: DivArm + 0x0, // SWI 8: Sqrt + 0x0, // SWI 9: ArcTan + 0x0, // SWI A: ArcTan2 + 0x0, // SWI B: CpuSet + 0x0, // SWI C: CpuFastSet + 0x0, // SWI D: GetBIOSCheckSum + 0x0, // SWI E: BgAffineSet + 0x0, // SWI F: ObjAffineSet + 0x0, // SWI 10: BitUnpack + 0x0, // SWI 11: LZ77UnCompWram + 0x0, // SWI 12: LZ77UnCompVram + 0x0, // SWI 13: HuffUnComp + 0x0, // SWI 14: RLUnCompWram + 0x0, // SWI 15: RLUnCompVram + 0x0, // SWI 16: Diff8bitUnFilterWram + 0x0, // SWI 17: Diff8bitUnFilterVram + 0x0, // SWI 18: Diff16bitUnFilter + 0x0, // SWI 19: SoundBias + 0x0, // SWI 1A: SoundDriverInit + 0x0, // SWI 1B: SoundDriverMode + 0x0, // SWI 1C: SoundDriverMain + 0x0, // SWI 1D: SoundDriverVSync + 0x0, // SWI 1E: SoundChannelClear + 0x0, // SWI 1F: MidiKey2Freq + 0x0, // SWI 20: SoundWhatever0 + 0x0, // SWI 21: SoundWhatever1 + 0x0, // SWI 22: SoundWhatever2 + 0x0, // SWI 23: SoundWhatever3 + 0x0, // SWI 24: SoundWhatever4 + 0x0, // SWI 25: MultiBoot + 0x0, // SWI 26: HardReset + 0x0, // SWI 27: CustomHalt + 0x0, // SWI 28: SoundDriverVSyncOff + 0x0, // SWI 29: SoundDriverVSyncOn + 0x0 // SWI 2A: SoundGetJumpList +}; + +#define generate_swi_hle_handler(_swi_number) \ +{ \ + u32 swi_number = _swi_number; \ + if(swi_hle_handle[swi_number]) \ + { \ + /* Div */ \ + if(swi_number == 0x06) \ + { \ + mips_emit_div(reg_r0, reg_r1); \ + mips_emit_mflo(reg_r0); \ + mips_emit_mfhi(reg_r1); \ + mips_emit_sra(reg_a0, reg_r0, 31); \ + mips_emit_xor(reg_r3, reg_r0, reg_a0); \ + mips_emit_subu(reg_r3, reg_r3, reg_a0); \ + } \ + break; \ + } \ +} \ + +#define generate_translation_gate(type) \ + generate_load_pc(reg_a0, pc); \ + generate_indirect_branch_no_cycle_update(type) \ + +#define generate_step_debug() \ + generate_load_imm(reg_a0, pc); \ + generate_function_call(step_debug_mips) \ + +#define generate_update_pc_reg() \ + generate_load_pc(reg_a0, pc); \ + mips_emit_sw(reg_a0, reg_base, (REG_PC * 4)) \ + +#endif diff --git a/psp/mips_stub.S b/psp/mips_stub.S new file mode 100644 index 0000000..65d5e9d --- /dev/null +++ b/psp/mips_stub.S @@ -0,0 +1,3427 @@ +# gameplaySP +# +# Copyright (C) 2006 Exophase +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +.align 4 + +.global mips_update_gba +.global mips_indirect_branch_arm +.global mips_indirect_branch_thumb +.global mips_indirect_branch_dual +.global execute_load_u8 +.global execute_load_u16 +.global execute_load_u32 +.global execute_load_s8 +.global execute_load_s16 +.global execute_store_u8 +.global execute_store_u16 +.global execute_store_u32 +.global execute_aligned_load32 +.global execute_aligned_store32 +.global execute_read_cpsr +.global execute_read_spsr +.global execute_swi +.global execute_spsr_restore +.global execute_store_cpsr +.global execute_store_spsr +.global execute_lsl_flags_reg +.global execute_lsr_flags_reg +.global execute_asr_flags_reg +.global execute_ror_flags_reg +.global execute_arm_translate +.global invalidate_icache_region +.global invalidate_all_cache +.global step_debug_mips +.global reg_check + +.global memory_map_read +.global memory_map_write +.global reg + +.extern reg +.extern spsr + +# MIPS register layout: + +# $0 - constant zero +# $1 - temporary +# $2 - temporary / return value +# $3 - ARM r0 (not saved) +# $4 - temporary / function argument 0 +# $5 - temporary / function argument 1 +# $6 - temporary / function argument 2 +# $7 - ARM r1 (not saved) +# $8 - ARM r2 (not saved) +# $9 - ARM r3 (not saved) +# $10 - ARM r4 (not saved) +# $11 - ARM r5 (not saved) +# $12 - ARM r6 (not saved) +# $13 - ARM r7 (not saved) +# $14 - ARM r8 (not saved) +# $15 - ARM r9 (not saved) +# $16 - ARM machine state pointer (saved) +# $17 - cycle counter (saved) +# $18 - ARM r10 (saved) +# $19 - block start address (roughly r15) (saved) +# $20 - ARM negative register (saved) +# $21 - ARM zero register (saved) +# $22 - ARM carry register (saved) +# $23 - ARM overflow register (saved) +# $24 - ARM r11 (not saved) +# $25 - ARM r12 (not saved) +# $26 - kernel temporary 0 +# $27 - kernel temporary 1 +# $28 - ARM r13 (saved) +# $29 - stack pointer +# $30 - ARM r14 (saved) +# $31 - return address + +.equ REG_R0, (0 * 4) +.equ REG_R1, (1 * 4) +.equ REG_R2, (2 * 4) +.equ REG_R3, (3 * 4) +.equ REG_R4, (4 * 4) +.equ REG_R5, (5 * 4) +.equ REG_R6, (6 * 4) +.equ REG_R7, (7 * 4) +.equ REG_R8, (8 * 4) +.equ REG_R9, (9 * 4) +.equ REG_R10, (10 * 4) +.equ REG_R11, (11 * 4) +.equ REG_R12, (12 * 4) +.equ REG_R13, (13 * 4) +.equ REG_R14, (14 * 4) +.equ REG_LR, (14 * 4) +.equ REG_PC, (15 * 4) +.equ REG_N_FLAG, (16 * 4) +.equ REG_Z_FLAG, (17 * 4) +.equ REG_C_FLAG, (18 * 4) +.equ REG_V_FLAG, (19 * 4) +.equ REG_CPSR, (20 * 4) +.equ REG_SAVE, (21 * 4) +.equ REG_SAVE2, (22 * 4) +.equ REG_SAVE3, (23 * 4) +.equ CPU_MODE, (29 * 4) +.equ CPU_HALT_STATE, (30 * 4) +.equ CHANGED_PC_STATUS, (31 * 4) +.equ GP_SAVE, (32 * 4) + +.equ SUPERVISOR_LR, (reg_mode + (3 * (7 * 4)) + (6 * 4)) +.equ SUPERVISOR_SPSR, (spsr + (3 * 4)) + +.set noat +.set noreorder + +# make sure $16 has the register base for these macros + +.macro collapse_flag flag_reg, shift + ins $2, $\flag_reg, \shift, 1 # insert flag into CPSR +.endm + +.macro collapse_flags + lw $2, REG_CPSR($16) # load CPSR + andi $2, $2, 0xFF # isolate lower 8bits + collapse_flag 20, 31 # store flags + collapse_flag 21, 30 + collapse_flag 22, 29 + collapse_flag 23, 28 + sw $2, REG_CPSR($16) # store CPSR +.endm + +.macro extract_flag shift, flag_reg + ext $\flag_reg, $1, \shift, 1 # extract flag from CPSR +.endm + +.macro extract_flags_body # extract flags from $1 + extract_flag 31, 20 # load flags + extract_flag 30, 21 + extract_flag 29, 22 + extract_flag 28, 23 +.endm + +.macro extract_flags + lw $1, REG_CPSR($16) # load CPSR + extract_flags_body +.endm + +.macro save_registers + sw $3, REG_R0($16) + sw $7, REG_R1($16) + sw $8, REG_R2($16) + sw $9, REG_R3($16) + sw $10, REG_R4($16) + sw $11, REG_R5($16) + sw $12, REG_R6($16) + sw $13, REG_R7($16) + sw $14, REG_R8($16) + sw $15, REG_R9($16) + sw $24, REG_R11($16) + sw $25, REG_R12($16) + + sw $18, REG_R10($16) + sw $28, REG_R13($16) + sw $30, REG_R14($16) + + lw $28, GP_SAVE($16) +.endm + +.macro restore_registers + lw $3, REG_R0($16) + lw $7, REG_R1($16) + lw $8, REG_R2($16) + lw $9, REG_R3($16) + lw $10, REG_R4($16) + lw $11, REG_R5($16) + lw $12, REG_R6($16) + lw $13, REG_R7($16) + lw $14, REG_R8($16) + lw $15, REG_R9($16) + lw $24, REG_R11($16) + lw $25, REG_R12($16) + + lw $18, REG_R10($16) + lw $28, REG_R13($16) + lw $30, REG_R14($16) +.endm + +# Process a hardware event. Since an interrupt might be +# raised we have to check if the PC has changed. + +# $4: next address +# $16: register base +# $17: cycle counter + +.balign 64 + +mips_update_gba: + sw $4, REG_PC($16) # current PC = $4 + + addiu $sp, $sp, -4 # make room on the stack + sw $ra,($sp) # save return address + collapse_flags # update cpsr + save_registers # save registers + jal update_gba # process the next event + sw $0, CHANGED_PC_STATUS($16) + + lw $ra, ($sp) # restore return address + addiu $sp, $sp, 4 # fix stack + + lw $1, CHANGED_PC_STATUS($16) + bne $1, $0, lookup_pc + addu $17, $2, $0 # $17 = new cycle count (delay slot) + + restore_registers + + jr $ra # if not, go back to caller + nop + +# Perform an indirect branch. + +# $4: GBA address to branch to + +mips_indirect_branch_arm: + save_registers + jal block_lookup_address_arm # $2 = MIPS address to jump to + nop + restore_registers + jr $2 # jump to it + nop + +mips_indirect_branch_thumb: + save_registers + jal block_lookup_address_thumb # $2 = MIPS address to jump to + nop + restore_registers + jr $2 # jump to it + nop + +mips_indirect_branch_dual: + save_registers + jal block_lookup_address_dual # $2 = MIPS address to jump to + nop + restore_registers + jr $2 # jump to it + nop + + +# $4: address to write to +# $5: current PC + +# Will patch the return address with a call to the correct handler as +# listed in the given table. + +# Value will be set to force_open if it's open + +.macro patch_handler ftable, force_open + srl $1, $4, 24 # $1 = address region + sltu $2, $1, 0x0F # check if the value is open + bne $2, $0, 1f + sll $1, $1, 2 # make address word indexed (delay) + + addiu $1, $0, (\force_open * 4) + +1: + lui $2, %hi(\ftable) + addu $2, $2, $1 + lw $2, %lo(\ftable)($2) # new function handler is in $2 + srl $2, $2, 2 # remove lower two bits + + lui $1, %hi(3 << 26) # $1 = 3 (JAL opcode) + ins $1, $2, 0, 26 # insert offset into jal + + addiu $ra, $ra, -8 # rewind return address to function call + sw $1, ($ra) # modify to call new handler + + cache 0x1a, ($ra) # hit writeback dcache line + cache 0x08, ($ra) # hit invalidate icache line + + jr $ra # return + nop # wary of putting cache here +.endm + + +# Like the above, but will use the table of the proper alignment, +# The tables should be ordered by alignment + +.macro patch_handler_align ftable, alignment + srl $1, $4, 24 # $1 = address region + sltu $2, $1, 0x0F # check if the value is open + bne $2, $0, 1f + sll $1, $1, 2 # make address word indexed (delay) + + addiu $1, $0, 4 # force address to 0x1 (open) + +1: + ins $1, $4, 6, \alignment # place alignment bits into offset + lui $2, %hi(\ftable) + + addu $2, $2, $1 + lw $2, %lo(\ftable)($2) # new function handler is in $2 + + srl $2, $2, 2 # remove lower two bits + + lui $1, %hi(3 << 26) # $1 = 3 (JAL opcode) + ins $1, $2, 0, 26 # insert offset into jal + + addiu $ra, $ra, -8 # rewind return address to function call + sw $1, ($ra) # modify to call new handler + + cache 0x1a, ($ra) # hit writeback dcache line + cache 0x08, ($ra) # hit invalidate icache line + + jr $ra # return + nop # wary of putting cache here +.endm + + +.macro region_check region, patch_handler + srl $1, $4, 24 # check upper 8bits of address + xor $1, $1, \region # see if it is the given region + bne $1, $0, \patch_handler # if not repatch/try again +.endm + +.macro region_check_open patch_handler + srl $1, $4, 24 # check upper 8bits of address + sltiu $2, $1, 0x0F # true if it is a low address + addiu $1, $1, -1 # non-zero if it is not a low open + sltu $1, $0, $1 # true if lower bits != 1 + and $1, $1, $2 # true if low address and not open + bne $1, $0, \patch_handler # if above is true, patch +.endm + + +.macro region_check_align region, align_bits, alignment, patch_handler + srl $1, $4, 24 # check upper 8bits of address + ins $1, $4, 8, \align_bits # look at lower bits of address too + # See if it is the given region and alignment + xori $1, $1, (\region | (\alignment << 8)) + bne $1, $0, \patch_handler # if not repatch/try again +.endm + +.macro region_check_open_align align_bits, alignment, patch_handler + srl $1, $4, 24 # check upper 8bits of address + sltiu $2, $1, 0x0F # true if it is a low address + addiu $1, $1, -1 # non-zero if it is not a low open + sltu $1, $0, $1 # true if $1 != 0 + and $1, $1, $2 # true if low address and not open + ext $2, $4, 0, \align_bits # $2 = low bits of 4 + xori $2, $2, \alignment # true if alignment doesn't match + or $1, $1, $2 # align failure will trigger too + bne $1, $0, \patch_handler # if above is true, patch +.endm + + +.macro ignore_region region, patch_handler + region_check \region, \patch_handler + nop + jr $ra + nop +.endm + +.macro ignore_high patch_handler + srl $1, $4, 24 # check upper 8bits of address + sltiu $1, $1, 0x0F # see if it is not high + bne $1, $0, \patch_handler # if not repatch/try again + nop + jr $ra + nop +.endm + + +.macro translate_region_core base, size + lui $2, %hi(\base) # generate upper address + andi $4, $4, \size # generate offset + addu $2, $2, $4 # add ptr upper and offset +.endm + +.macro translate_region region, patch_handler, base, size + region_check \region, \patch_handler + translate_region_core \base, \size +.endm + +# I refuse to have > 80 char lines, and GAS has a problem with the param +# list spilling over (grumble) + +.macro translate_region_align region, a_b, alignment, p_h, base, size + region_check_align \region, \a_b, \alignment, \p_h + translate_region_core \base, \size +.endm + + +.macro translate_region_ewram_core mask + lui $2, %hi(ewram + 0x8000) # generate upper address (delay) + andi $1, $4, \mask # generate 15bit offset + ext $4, $4, 15, 3 # isolate top 3 bits of offset + ins $1, $4, 16, 3 # reinsert into top 4 bits + addu $2, $2, $1 +.endm + +.macro translate_region_ewram patch_handler + region_check 2, \patch_handler + translate_region_ewram_core 0x7FFF +.endm + +.macro translate_region_ewram_load_align align_bits, alignment, patch_handler + region_check_align 2, \align_bits, \alignment, \patch_handler + translate_region_ewram_core 0x7FFF +.endm + +.macro translate_region_ewram_load_align16 align_bits, alignment, patch_handler + region_check_align 2, \align_bits, \alignment, \patch_handler + translate_region_ewram_core 0x7FFE +.endm + +.macro translate_region_ewram_load_align32 align_bits, alignment, patch_handler + region_check_align 2, \align_bits, \alignment, \patch_handler + translate_region_ewram_core 0x7FFC +.endm + +.macro translate_region_ewram_store_align16 patch_handler + region_check 2, \patch_handler + translate_region_ewram_core 0x7FFE +.endm + +.macro translate_region_ewram_store_align32 patch_handler + region_check 2, \patch_handler + translate_region_ewram_core 0x7FFC +.endm + + +.macro translate_region_vram_core + addiu $2, $2, -3 # see if it's 3 + ext $4, $4, 0, 17 # generate 17bit offset + bne $2, $0, 1f + lui $1, %hi(vram) # start loading vram address (delay) + + addiu $4, $4, -0x8000 # move address into VRAM region + +1: + addu $2, $1, $4 # $2 = (hi)vram + address +.endm + +.macro translate_region_vram patch_handler + region_check 6, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + translate_region_vram_core +.endm + +.macro translate_region_vram_load_align align_bits, alignment, patch_handler + region_check_align 6, \align_bits, \alignment, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + translate_region_vram_core +.endm + +.macro translate_region_vram_load_align16 align_bits, alignment, patch_handler + region_check_align 6, \align_bits, \alignment, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + ins $4, $0, 0, 1 # mask out lower bit of address + translate_region_vram_core +.endm + +.macro translate_region_vram_load_align32 align_bits, alignment, patch_handler + region_check_align 6, \align_bits, \alignment, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + ins $4, $0, 0, 2 # mask out lower two bits of address + translate_region_vram_core +.endm + +.macro translate_region_vram_store_align16 patch_handler + region_check 6, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + ins $4, $0, 0, 1 # mask out lower bit of address + translate_region_vram_core +.endm + +.macro translate_region_vram_store_align32 patch_handler + region_check 6, \patch_handler + ext $2, $4, 15, 2 # $2 = bits 15 and 16 of address (delay) + ins $4, $0, 0, 2 # mask out lower two bits of address + translate_region_vram_core +.endm + + + +.macro translate_region_gamepak_core mask + srl $2, $4, 15 # $2 = page number of address (delay) + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $2 = memory_map_read[address >> 15] + lw $2, -32768($2) + bne $2, $0, 1f # if it's non-NULL continue + andi $1, $4, \mask # $1 = low 15bits of address (delay slot) + + sw $ra, REG_SAVE2($16) # save return address + + save_registers # save the registers + ext $4, $4, 15, 10 # $4 = (address >> 15) & 0x3FF + + jal load_gamepak_page # get page in $2 + sw $1, REG_SAVE($16) # save offset (delay) + lw $1, REG_SAVE($16) # restore offset (delay) + + restore_registers # restore the other registers + + lw $ra, REG_SAVE2($16) # restore return address + +1: + addu $2, $2, $1 # add the memory map offset +.endm + +.macro translate_region_gamepak region, patch_handler + region_check \region, \patch_handler + translate_region_gamepak_core 0x7FFF +.endm + +.macro translate_region_gamepak_align region, a_b, alignment, patch_handler + region_check_align \region, \a_b, \alignment, \patch_handler + translate_region_gamepak_core 0x7FFF +.endm + +.macro translate_region_gamepak_align16 region, a_b, alignment, patch_handler + region_check_align \region, \a_b, \alignment, \patch_handler + translate_region_gamepak_core 0x7FFE +.endm + +.macro translate_region_gamepak_align32 region, a_b, alignment, patch_handler + region_check_align \region, \a_b, \alignment, \patch_handler + translate_region_gamepak_core 0x7FFC +.endm + + +.macro translate_region_gamepak_a region, patch_handler + region_check \region, \patch_handler + srl $2, $4, 15 # $2 = page number of address (delay) + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $2 = memory_map_read[address >> 15] + lw $2, -32768($2) + bne $2, $0, 1f # if it's non-NULL continue + andi $1, $4, 0x7FFF # $1 = low 15bits of address (delay slot) + + sw $ra, REG_SAVE2($16) # save return address + sw $6, REG_SAVE3($16) # save a2 + + save_registers # save the registers + ext $4, $4, 15, 10 # $4 = (address >> 15) & 0x3FF + + jal load_gamepak_page # get page in $2 + sw $1, REG_SAVE($16) # save offset (delay) + lw $1, REG_SAVE($16) # restore offset (delay) + + restore_registers # restore the other registers + + lw $ra, REG_SAVE2($16) # restore return address + lw $6, REG_SAVE3($16) # restore a2 + +1: + addu $2, $2, $1 # add the memory map offset +.endm + + +.macro eeprom_load_a patch_handler + region_check 0xD, \patch_handler + + sw $ra, REG_SAVE($16) # save the return address (delay) + sw $6, REG_SAVE2($16) # save a2 + + save_registers # save the registers + + jal read_eeprom # get eeprom value in $2 + nop + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + lw $6, REG_SAVE2($16) # restore a2 +.endm + + +.macro eeprom_load_core + sw $ra, REG_SAVE($16) # save the return address (delay) + + save_registers # save the registers + + jal read_eeprom # get eeprom value in $2 + nop + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + nop +.endm + +.macro eeprom_load patch_handler + region_check 0xD, \patch_handler + eeprom_load_core +.endm + +.macro eeprom_load_align align_bits, alignment, patch_handler + region_check_align 0xD, \align_bits, \alignment, \patch_handler + eeprom_load_core +.endm + +.macro eeprom_load_align16 align_bits, alignment, patch_handler + eeprom_load_align \align_bits, \alignment, \patch_handler +.endm + +.macro eeprom_load_align32 align_bits, alignment, patch_handler + eeprom_load_align \align_bits, \alignment, \patch_handler +.endm + + +.macro backup_load_core + save_registers # save the registers + + jal read_backup # get backup value in $2 + ext $4, $4, 0, 16 # address &= 0xFFFF + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return +.endm + +.macro backup_load_a patch_handler + region_check 0xE, \patch_handler + sw $ra, REG_SAVE($16) # save return address (delay) + sw $6, REG_SAVE2($16) # save a2 + + save_registers # save the registers + + jal read_backup # get backup value in $2 + ext $4, $4, 0, 16 # address &= 0xFFFF + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + lw $6, REG_SAVE2($16) # restore a2 +.endm + + +.macro backup_load patch_handler + region_check 0xE, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + backup_load_core +.endm + +.macro backup_load_align align_bits, alignment, patch_handler + region_check_align 0xE, \align_bits, \alignment, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + backup_load_core +.endm + +.macro backup_load_align16 align_bits, alignment, patch_handler + region_check_align 0xE, \align_bits, \alignment, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + ins $4, $0, 0, 1 # mask out lower bit + backup_load_core +.endm + +.macro backup_load_align32 align_bits, alignment, patch_handler + region_check_align 0xE, \align_bits, \alignment, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + ins $4, $0, 0, 2 # mask out lower two bits + backup_load_core +.endm + + +.macro open_load8_core + lw $2, REG_CPSR($16) # $2 = CPSR (delay) + andi $2, $2, 0x20 # test T bit + beq $2, $0, 1f # branch if ARM mode + andi $4, $4, 0x03 # isolate lower 3bits from address (delay) + + andi $4, $4, 0x01 # in Thumb mode, isolate one more bit + +1: + sw $ra, REG_SAVE($16) # save the return address (delay) + save_registers # save the registers + + jal read_memory8 # get instruction at PC + addu $4, $5, $4 # a0 = PC + low bits of address + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return +.endm + +.macro open_load8 patch_handler + region_check_open \patch_handler + open_load8_core +.endm + + + +.macro open_load16_core + lw $2, REG_CPSR($16) # $2 = CPSR (delay) + andi $2, $2, 0x20 # test T bit + beq $2, $0, 1f # branch if ARM mode + andi $4, $4, 0x02 # isolate bit 1 from address (delay) + + addu $4, $0, $0 # zero out address bit + +1: + sw $ra, REG_SAVE($16) # save the return address (delay) + save_registers # save the registers + + jal read_memory16 # get instruction at PC + addu $4, $5, $4 # a0 = PC + low bits of address + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return +.endm + +.macro open_load16_align align_bits, alignment, patch_handler + region_check_open_align \align_bits, \alignment, \patch_handler + open_load16_core +.endm + +.macro open_load16_align16 align_bits, alignment, patch_handler + open_load16_align \align_bits, \alignment, \patch_handler +.endm + + + +.macro open_load32_core + lw $2, REG_CPSR($16) # $2 = CPSR (delay) + andi $2, $2, 0x20 # test T bit + + save_registers # save the registers + + beq $2, $0, 1f # branch if ARM mode + sw $ra, REG_SAVE($16) # save the return address (delay) + + jal read_memory16 # get instruction at PC + addu $4, $5, $0 # a0 = PC + + j 2f + ins $2, $2, 16, 16 # result = (result << 16) | result (delay) + +1: + jal read_memory32 # get instruction at PC + addu $4, $5, $4 # a0 = PC + +2: # join point + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return +.endm + +.macro open_load32_a patch_handler + region_check_open \patch_handler + + lw $2, REG_CPSR($16) # $2 = CPSR (delay) + andi $2, $2, 0x20 # test T bit + + save_registers # save the registers + sw $6, REG_SAVE2($16) # save a2 + + beq $2, $0, 1f # branch if ARM mode + sw $ra, REG_SAVE($16) # save the return address (delay) + + jal read_memory16 # get instruction at PC + addu $4, $5, $0 # a0 = PC + + j 2f + ins $2, $2, 16, 16 # result = (result << 16) | result (delay) + +1: + jal read_memory32 # get instruction at PC + addu $4, $5, $4 # a0 = PC + +2: + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + lw $6, REG_SAVE2($16) # restore a2 (delay) +.endm + +.macro open_load32_align align_bits, alignment, patch_handler + region_check_open_align \align_bits, \alignment, \patch_handler + open_load32_core +.endm + +.macro open_load32_align32 align_bits, alignment, patch_handler + open_load32_align \align_bits, \alignment, \patch_handler +.endm + + +.macro store_function function, region, patch_handler, mask + region_check \region, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + + save_registers # save the registers + + jal \function # store value out + andi $4, $4, \mask # mask address + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + nop +.endm + + +.macro store_function_a function, region, patch_handler, mask + region_check \region, \patch_handler + sw $ra, REG_SAVE($16) # save the return address (delay) + + save_registers # save the registers + + jal \function # store value out + andi $4, $4, \mask # mask address + + restore_registers # restore the other registers + + lw $ra, REG_SAVE($16) # restore return address + jr $ra # return + nop +.endm + + + +.macro load_u8 base + jr $ra # return + lbu $2, %lo(\base)($2) # return base[offset] +.endm + +.macro load_s8 base + jr $ra # return + lb $2, %lo(\base)($2) # return base[offset] +.endm + +.macro load_u16 base + jr $ra # return + lhu $2, %lo(\base)($2) # return base[offset] +.endm + +.macro load_s16 base + jr $ra # return + lh $2, %lo(\base)($2) # return base[offset] +.endm + +.macro load_u32 base + jr $ra # return + lw $2, %lo(\base)($2) # return base[offset] +.endm + + +# 16bit unaligned load will always have a 1 in the LSB; +# should have already been taken care of in indexing. + +.macro load_u16_unaligned base + lhu $2, %lo(\base)($2) # load base[offset] + jr $ra # return + ror $2, $2, 8 # rotate value by 8bits +.endm + +# This is technically the same as load_s8, but kept to +# avoid confusion. + +.macro load_s16_unaligned base + jr $ra # return + lb $2, %lo(\base)($2) # return base[offset] +.endm + +# Unalignment must be known statically (use the tables to +# patch correctly) + +.macro load_u32_unaligned base, alignment + lw $2, %lo(\base)($2) # load base[offset] + jr $ra # return + ror $2, $2, (\alignment * 8) # rotate value by 8bits +.endm + + +.macro store_u8 base + jr $ra # return + sb $5, %lo(\base)($2) # store value at base[offset] +.endm + +.macro store_u16 base + jr $ra # return + sh $5, %lo(\base)($2) # store value at base[offset] +.endm + +.macro store_u32 base + jr $ra # return + sw $5, %lo(\base)($2) # store value at base[offset] +.endm + + +# Store the value double mirrored (u16) + +.macro store_u8_double base + ins $5, $5, 8, 8 # value = (value << 8) | value + jr $ra # return + sh $5, %lo(\base)($2) # store value at base[offset] +.endm + + +# Store the values and check if it overwrote code there + +.macro store_u8_smc base + addiu $2, $2, %lo(\base) # offset the address + lb $1, -32768($2) # load the SMC status + bne $1, $0, smc_write # is there code there? + sb $5, ($2) # store value at base[offset] (delay) + jr $ra # return + nop +.endm + +.macro store_u16_smc base + addiu $2, $2, %lo(\base) # offset the address + lh $1, -32768($2) # load the SMC status + bne $1, $0, smc_write # is there code there? + sh $5, ($2) # store value at base[offset] (delay) + jr $ra # return + nop +.endm + +.macro store_u32_smc base + addiu $2, $2, %lo(\base) # offset the address + lw $1, -32768($2) # load the SMC status + bne $1, $0, smc_write # is there code there? + sw $5, ($2) # store value at base[offset] (delay) + jr $ra # return + nop +.endm + + + +# Unsigned 8bit load handlers + +execute_load_bios_u8: + region_check 0, patch_load_u8 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_u8 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ins $2, $4, 0, 2 # lower 2 bits address contributes + load_u8 bios_read_protect + +2: + open_load8_core + nop + + +execute_load_ewram_u8: + translate_region_ewram patch_load_u8 + load_u8 (ewram + 0x8000) + +# Put the generic address over the handler you want to be default +# IWRAM is typically the most frequently read and written to. + +execute_load_u8: +execute_load_iwram_u8: + translate_region 3, patch_load_u8, (iwram + 0x8000), 0x7FFF + load_u8 (iwram + 0x8000) + +execute_load_io_u8: + translate_region 4, patch_load_u8, io_registers, 0x3FF + load_u8 io_registers + +execute_load_palette_u8: + translate_region 5, patch_load_u8, palette_ram, 0x3FF + load_u8 palette_ram + +execute_load_vram_u8: + translate_region_vram patch_load_u8 + load_u8 vram + +execute_load_oam_u8: + translate_region 7, patch_load_u8, oam_ram, 0x3FF + load_u8 oam_ram + +execute_load_gamepak8_u8: + translate_region_gamepak 8, patch_load_u8 + load_u8 0 + +execute_load_gamepak9_u8: + translate_region_gamepak 9, patch_load_u8 + load_u8 0 + +execute_load_gamepakA_u8: + translate_region_gamepak 10, patch_load_u8 + load_u8 0 + +execute_load_gamepakB_u8: + translate_region_gamepak 11, patch_load_u8 + load_u8 0 + +execute_load_gamepakC_u8: + translate_region_gamepak 12, patch_load_u8 + load_u8 0 + +execute_load_eeprom_u8: + eeprom_load patch_load_u8 + +execute_load_backup_u8: + backup_load patch_load_u8 + nop + +execute_load_open_u8: + open_load8 patch_load_u8 + nop + +load_u8_ftable: + .long execute_load_bios_u8 # 0x00 BIOS + .long execute_load_open_u8 # 0x01 open address + .long execute_load_ewram_u8 # 0x02 EWRAM + .long execute_load_iwram_u8 # 0x03 IWRAM + .long execute_load_io_u8 # 0x04 I/O registers + .long execute_load_palette_u8 # 0x05 Palette RAM + .long execute_load_vram_u8 # 0x06 VRAM + .long execute_load_oam_u8 # 0x07 OAM RAM + .long execute_load_gamepak8_u8 # 0x08 gamepak + .long execute_load_gamepak9_u8 # 0x09 gamepak + .long execute_load_gamepakA_u8 # 0x0A gamepak + .long execute_load_gamepakB_u8 # 0x0B gamepak + .long execute_load_gamepakC_u8 # 0x0C gamepak + .long execute_load_eeprom_u8 # 0x0D gamepak/eeprom + .long execute_load_backup_u8 # 0x0E Flash ROM/SRAM + .long execute_load_open_u8 # 0x0F open address + +patch_load_u8: + patch_handler load_u8_ftable, 0x01 + + + +# Signed 8bit load handlers + +execute_load_bios_s8: + region_check 0, patch_load_s8 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_s8 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ins $2, $4, 0, 2 # lower 2 bits contribute + load_s8 bios_read_protect + +2: + open_load8_core + seb $2, $2 + + +execute_load_ewram_s8: + translate_region_ewram patch_load_s8 + load_s8 (ewram + 0x8000) + +execute_load_s8: +execute_load_iwram_s8: + translate_region 3, patch_load_s8, (iwram + 0x8000), 0x7FFF + load_s8 (iwram + 0x8000) + +execute_load_io_s8: + translate_region 4, patch_load_s8, io_registers, 0x3FF + load_s8 io_registers + +execute_load_palette_s8: + translate_region 5, patch_load_s8, palette_ram, 0x3FF + load_s8 palette_ram + +execute_load_vram_s8: + translate_region_vram patch_load_s8 + load_s8 vram + +execute_load_oam_s8: + translate_region 7, patch_load_s8, oam_ram, 0x3FF + load_s8 oam_ram + +execute_load_gamepak8_s8: + translate_region_gamepak 8, patch_load_s8 + load_s8 0 + +execute_load_gamepak9_s8: + translate_region_gamepak 9, patch_load_s8 + load_s8 0 + +execute_load_gamepakA_s8: + translate_region_gamepak 10, patch_load_s8 + load_s8 0 + +execute_load_gamepakB_s8: + translate_region_gamepak 11, patch_load_s8 + load_s8 0 + +execute_load_gamepakC_s8: + translate_region_gamepak 12, patch_load_s8 + load_s8 0 + +execute_load_eeprom_s8: + eeprom_load patch_load_s8 + +execute_load_backup_s8: + backup_load patch_load_s8 + seb $2, $2 # sign extend result (delay) + +execute_load_open_s8: + open_load8 patch_load_s8 + seb $2, $2 # sign extend result (delay) + +load_s8_ftable: + .long execute_load_bios_s8 # 0x00 BIOS + .long execute_load_open_s8 # 0x01 open address + .long execute_load_ewram_s8 # 0x02 EWRAM + .long execute_load_iwram_s8 # 0x03 IWRAM + .long execute_load_io_s8 # 0x04 I/O registers + .long execute_load_palette_s8 # 0x05 Palette RAM + .long execute_load_vram_s8 # 0x06 VRAM + .long execute_load_oam_s8 # 0x07 OAM RAM + .long execute_load_gamepak8_s8 # 0x08 gamepak + .long execute_load_gamepak9_s8 # 0x09 gamepak + .long execute_load_gamepakA_s8 # 0x0A gamepak + .long execute_load_gamepakB_s8 # 0x0B gamepak + .long execute_load_gamepakC_s8 # 0x0C gamepak + .long execute_load_eeprom_s8 # 0x0D gamepak/eeprom + .long execute_load_backup_s8 # 0x0E Flash ROM/SRAM + .long execute_load_open_s8 # 0x0F open address + +patch_load_s8: + patch_handler load_s8_ftable, 1 + + + +# Unsigned aligned 16bit load handlers + +execute_load_bios_u16: + region_check_align 0, 1, 0, patch_load_u16 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_u16 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ins $2, $4, 0, 2 # bit 1 contributes + load_u16 bios_read_protect + +2: + open_load16_core + nop + +execute_load_ewram_u16: + translate_region_ewram_load_align 1, 0, patch_load_u16 + load_u16 (ewram + 0x8000) + +execute_load_u16: +execute_load_iwram_u16: + translate_region_align 3, 1, 0, patch_load_u16, (iwram + 0x8000), 0x7FFF + load_u16 (iwram + 0x8000) + +execute_load_io_u16: + translate_region_align 4, 1, 0, patch_load_u16, io_registers, 0x3FF + load_u16 io_registers + +execute_load_palette_u16: + translate_region_align 5, 1, 0, patch_load_u16, palette_ram, 0x3FF + load_u16 palette_ram + +execute_load_vram_u16: + translate_region_vram_load_align 1, 0, patch_load_u16 + load_u16 vram + +execute_load_oam_u16: + translate_region_align 7, 1, 0, patch_load_u16, oam_ram, 0x3FF + load_u16 oam_ram + +execute_load_gamepak8_u16: + translate_region_gamepak_align 8, 1, 0, patch_load_u16 + load_u16 0 + +execute_load_gamepak9_u16: + translate_region_gamepak_align 9, 1, 0, patch_load_u16 + load_u16 0 + +execute_load_gamepakA_u16: + translate_region_gamepak_align 10, 1, 0, patch_load_u16 + load_u16 0 + +execute_load_gamepakB_u16: + translate_region_gamepak_align 11, 1, 0, patch_load_u16 + load_u16 0 + +execute_load_gamepakC_u16: + translate_region_gamepak_align 12, 1, 0, patch_load_u16 + load_u16 0 + +execute_load_eeprom_u16: + eeprom_load_align 1, 0, patch_load_u16 + +execute_load_backup_u16: + backup_load_align 1, 0, patch_load_u16 + nop + +execute_load_open_u16: + open_load16_align 1, 0, patch_load_u16 + nop + + +# Unsigned unaligned 16bit load handlers + +execute_load_bios_u16u: + region_check_align 0, 1, 1, patch_load_u16 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFE # generate offset + addu $2, $2, $4 + load_u16_unaligned bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ext $1, $4, 1, 1 + ins $2, $1, 1, 1 # bit 1 contributes + load_u16_unaligned bios_read_protect + +2: + open_load16_core + ror $2, $2, 8 + + +execute_load_ewram_u16u: + translate_region_ewram_load_align16 1, 1, patch_load_u16 + load_u16_unaligned (ewram + 0x8000) + +execute_load_iwram_u16u: + translate_region_align 3, 1, 1, patch_load_u16, (iwram + 0x8000), 0x7FFE + load_u16_unaligned (iwram + 0x8000) + +execute_load_io_u16u: + translate_region_align 4, 1, 1, patch_load_u16, io_registers, 0x3FE + load_u16_unaligned io_registers + +execute_load_palette_u16u: + translate_region_align 5, 1, 1, patch_load_u16, palette_ram, 0x3FE + load_u16_unaligned palette_ram + +execute_load_vram_u16u: + translate_region_vram_load_align16 1, 1, patch_load_u16 + load_u16_unaligned vram + +execute_load_oam_u16u: + translate_region_align 7, 1, 1, patch_load_u16, oam_ram, 0x3FE + load_u16_unaligned oam_ram + +execute_load_gamepak8_u16u: + translate_region_gamepak_align16 8, 1, 1, patch_load_u16 + load_u16_unaligned 0 + +execute_load_gamepak9_u16u: + translate_region_gamepak_align16 9, 1, 1, patch_load_u16 + load_u16_unaligned 0 + +execute_load_gamepakA_u16u: + translate_region_gamepak_align16 10, 1, 1, patch_load_u16 + load_u16_unaligned 0 + +execute_load_gamepakB_u16u: + translate_region_gamepak_align16 11, 1, 1, patch_load_u16 + load_u16_unaligned 0 + +execute_load_gamepakC_u16u: + translate_region_gamepak_align16 12, 1, 1, patch_load_u16 + load_u16_unaligned 0 + +execute_load_eeprom_u16u: + eeprom_load_align16 1, 1, patch_load_u16 + +execute_load_backup_u16u: + backup_load_align16 1, 1, patch_load_u16 + ror $2, $2, 8 # rotate value by 8bits + +execute_load_open_u16u: + open_load16_align16 1, 1, patch_load_u16 + ror $2, $2, 8 # rotate value by 8bits + +load_u16_ftable: +# .long execute_load_full_u16 + .long execute_load_bios_u16 # 0x00 BIOS + .long execute_load_open_u16 # 0x01 open address + .long execute_load_ewram_u16 # 0x02 EWRAM + .long execute_load_iwram_u16 # 0x03 IWRAM + .long execute_load_io_u16 # 0x04 I/O registers + .long execute_load_palette_u16 # 0x05 Palette RAM + .long execute_load_vram_u16 # 0x06 VRAM + .long execute_load_oam_u16 # 0x07 OAM RAM + .long execute_load_gamepak8_u16 # 0x08 gamepak + .long execute_load_gamepak9_u16 # 0x09 gamepak + .long execute_load_gamepakA_u16 # 0x0A gamepak + .long execute_load_gamepakB_u16 # 0x0B gamepak + .long execute_load_gamepakC_u16 # 0x0C gamepak + + .long execute_load_eeprom_u16 # 0x0D gamepak/eeprom + .long execute_load_backup_u16 # 0x0E Flash ROM/SRAM + .long execute_load_open_u16 # 0x0F open + + .long execute_load_bios_u16u # 0x00 BIOS unaligned + .long execute_load_open_u16u # 0x01 open address unaligned + .long execute_load_ewram_u16u # 0x02 EWRAM unaligned + .long execute_load_iwram_u16u # 0x03 IWRAM unaligned + .long execute_load_io_u16u # 0x04 I/O registers unaligned + .long execute_load_palette_u16u # 0x05 Palette RAM unaligned + .long execute_load_vram_u16u # 0x06 VRAM unaligned + .long execute_load_oam_u16u # 0x07 OAM RAM unaligned + .long execute_load_gamepak8_u16u# 0x08 gamepak unaligned + .long execute_load_gamepak9_u16u# 0x09 gamepak unaligned + .long execute_load_gamepakA_u16u# 0x0A gamepak unaligned + .long execute_load_gamepakB_u16u# 0x0B gamepak unaligned + .long execute_load_gamepakC_u16u# 0x0C gamepak unaligned + .long execute_load_eeprom_u16u # 0x0D gamepak/eeprom unaligned + .long execute_load_backup_u16u # 0x0E Flash ROM/SRAM unaligned + .long execute_load_open_u16u # 0x0F open unaligned + + + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + .long execute_load_full_u16 + + + +patch_load_u16: + patch_handler_align load_u16_ftable, 1 + +# Signed aligned 16bit load handlers + +execute_load_bios_s16: + region_check_align 0, 1, 0, patch_load_s16 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_s16 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ins $2, $4, 0, 2 # bit 1 contributes + load_s16 bios_read_protect + +2: + open_load16_core + seh $2, $2 + + +execute_load_ewram_s16: + translate_region_ewram_load_align 1, 0, patch_load_s16 + load_s16 (ewram + 0x8000) + +execute_load_s16: +execute_load_iwram_s16: + translate_region_align 3, 1, 0, patch_load_s16, (iwram + 0x8000), 0x7FFF + load_s16 (iwram + 0x8000) + +execute_load_io_s16: + translate_region_align 4, 1, 0, patch_load_s16, io_registers, 0x3FF + load_s16 io_registers + +execute_load_palette_s16: + translate_region_align 5, 1, 0, patch_load_s16, palette_ram, 0x3FF + load_s16 palette_ram + +execute_load_vram_s16: + translate_region_vram_load_align 1, 0, patch_load_s16 + load_s16 vram + +execute_load_oam_s16: + translate_region_align 7, 1, 0, patch_load_s16, oam_ram, 0x3FF + load_s16 oam_ram + +execute_load_gamepak8_s16: + translate_region_gamepak_align 8, 1, 0, patch_load_s16 + load_s16 0 + +execute_load_gamepak9_s16: + translate_region_gamepak_align 9, 1, 0, patch_load_s16 + load_s16 0 + +execute_load_gamepakA_s16: + translate_region_gamepak_align 10, 1, 0, patch_load_s16 + load_s16 0 + +execute_load_gamepakB_s16: + translate_region_gamepak_align 11, 1, 0, patch_load_s16 + load_s16 0 + +execute_load_gamepakC_s16: + translate_region_gamepak_align 12, 1, 0, patch_load_s16 + load_s16 0 + +execute_load_eeprom_s16: + eeprom_load_align 1, 0, patch_load_s16 + +execute_load_backup_s16: + backup_load_align 1, 0, patch_load_s16 + nop + +execute_load_open_s16: + open_load16_align 1, 0, patch_load_s16 + nop + + +# Signed unaligned 16bit load handlers + +execute_load_bios_s16u: + region_check_align 0, 1, 1, patch_load_s16 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFE # generate offset + addu $2, $1, $4 + load_s16_unaligned bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + ext $1, $4, 1, 1 + ins $2, $1, 1, 1 # bit 1 contributes + load_s16_unaligned bios_read_protect + +2: + open_load16_core + seb $2, $2 + +execute_load_ewram_s16u: + translate_region_ewram_load_align16 1, 1, patch_load_s16 + load_s16_unaligned (ewram + 0x8000) + +execute_load_iwram_s16u: + translate_region_align 3, 1, 1, patch_load_s16, (iwram + 0x8000), 0x7FFE + load_s16_unaligned (iwram + 0x8000) + +execute_load_io_s16u: + translate_region_align 4, 1, 1, patch_load_s16, io_registers, 0x3FE + load_s16_unaligned io_registers + +execute_load_palette_s16u: + translate_region_align 5, 1, 1, patch_load_s16, palette_ram, 0x3FE + load_s16_unaligned palette_ram + +execute_load_vram_s16u: + translate_region_vram_load_align16 1, 1, patch_load_s16 + load_s16_unaligned vram + +execute_load_oam_s16u: + translate_region_align 7, 1, 1, patch_load_s16, oam_ram, 0x3FE + load_s16_unaligned oam_ram + +execute_load_gamepak8_s16u: + translate_region_gamepak_align16 8, 1, 1, patch_load_s16 + load_s16_unaligned 0 + +execute_load_gamepak9_s16u: + translate_region_gamepak_align16 9, 1, 1, patch_load_s16 + load_s16_unaligned 0 + +execute_load_gamepakA_s16u: + translate_region_gamepak_align16 10, 1, 1, patch_load_s16 + load_s16_unaligned 0 + +execute_load_gamepakB_s16u: + translate_region_gamepak_align16 11, 1, 1, patch_load_s16 + load_s16_unaligned 0 + +execute_load_gamepakC_s16u: + translate_region_gamepak_align16 12, 1, 1, patch_load_s16 + load_s16_unaligned 0 + +execute_load_eeprom_s16u: + eeprom_load_align 1, 1, patch_load_s16 + +execute_load_backup_s16u: + backup_load_align 1, 1, patch_load_s16 + seb $2, $2 # sign extend result from 8bits + +execute_load_open_s16u: + open_load16_align 1, 1, patch_load_s16 + seb $2, $2 # sign extend result from 8bits + +load_s16_ftable: + .long execute_load_bios_s16 # 0x00 BIOS + .long execute_load_open_s16 # 0x01 open address + .long execute_load_ewram_s16 # 0x02 EWRAM + .long execute_load_iwram_s16 # 0x03 IWRAM + .long execute_load_io_s16 # 0x04 I/O registers + .long execute_load_palette_s16 # 0x05 Palette RAM + .long execute_load_vram_s16 # 0x06 VRAM + .long execute_load_oam_s16 # 0x07 OAM RAM + .long execute_load_gamepak8_s16 # 0x08 gamepak + .long execute_load_gamepak9_s16 # 0x09 gamepak + .long execute_load_gamepakA_s16 # 0x0A gamepak + .long execute_load_gamepakB_s16 # 0x0B gamepak + .long execute_load_gamepakC_s16 # 0x0C gamepak + .long execute_load_eeprom_s16 # 0x0D gamepak/eeprom + .long execute_load_backup_s16 # 0x0E Flash ROM/SRAM + .long execute_load_open_s16 # 0x0F open unaligned + + .long execute_load_bios_s16u # 0x00 BIOS unaligned + .long execute_load_open_s16u # 0x01 open address unaligned + .long execute_load_ewram_s16u # 0x02 EWRAM unaligned + .long execute_load_iwram_s16u # 0x03 IWRAM unaligned + .long execute_load_io_s16u # 0x04 I/O registers unaligned + .long execute_load_palette_s16u # 0x05 Palette RAM unaligned + .long execute_load_vram_s16u # 0x06 VRAM unaligned + .long execute_load_oam_s16u # 0x07 OAM RAM unaligned + .long execute_load_gamepak8_s16u# 0x08 gamepak unaligned + .long execute_load_gamepak9_s16u# 0x09 gamepak unaligned + .long execute_load_gamepakA_s16u# 0x0A gamepak unaligned + .long execute_load_gamepakB_s16u# 0x0B gamepak unaligned + .long execute_load_gamepakC_s16u# 0x0C gamepak unaligned + .long execute_load_eeprom_s16u # 0x0D gamepak/eeprom unaligned + .long execute_load_backup_s16u # 0x0E Flash ROM/SRAM unaligned + .long execute_load_open_s16u # 0x0F open unaligned + +patch_load_s16: + patch_handler_align load_s16_ftable, 1 + + + +# Unsigned aligned 32bit load handlers + +execute_load_bios_u32: + region_check_align 0, 2, 0, patch_load_u32 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_u32 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + load_u32 bios_read_protect + +2: + open_load32_core + nop + + +execute_load_ewram_u32: + translate_region_ewram_load_align 2, 0, patch_load_u32 + load_u32 (ewram + 0x8000) + +execute_load_u32: +execute_load_iwram_u32: + translate_region_align 3, 2, 0, patch_load_u32, (iwram + 0x8000), 0x7FFF + load_u32 (iwram + 0x8000) + +execute_load_io_u32: + translate_region_align 4, 2, 0, patch_load_u32, io_registers, 0x3FF + load_u32 io_registers + +execute_load_palette_u32: + translate_region_align 5, 2, 0, patch_load_u32, palette_ram, 0x3FF + load_u32 palette_ram + +execute_load_vram_u32: + translate_region_vram_load_align 2, 0, patch_load_u32 + load_u32 vram + +execute_load_oam_u32: + translate_region_align 7, 2, 0, patch_load_u32, oam_ram, 0x3FF + load_u32 oam_ram + +execute_load_gamepak8_u32: + translate_region_gamepak_align 8, 2, 0, patch_load_u32 + load_u32 0 + +execute_load_gamepak9_u32: + translate_region_gamepak_align 9, 2, 0, patch_load_u32 + load_u32 0 + +execute_load_gamepakA_u32: + translate_region_gamepak_align 10, 2, 0, patch_load_u32 + load_u32 0 + +execute_load_gamepakB_u32: + translate_region_gamepak_align 11, 2, 0, patch_load_u32 + load_u32 0 + +execute_load_gamepakC_u32: + translate_region_gamepak_align 12, 2, 0, patch_load_u32 + load_u32 0 + +execute_load_eeprom_u32: + eeprom_load_align 2, 0, patch_load_u32 + +execute_load_backup_u32: + backup_load_align 2, 0, patch_load_u32 + nop + +execute_load_open_u32: + open_load32_align 2, 0, patch_load_u32 + nop + + +# Unsigned unaligned (by 1) 32bit load handlers + +execute_load_bios_u32u1: + region_check_align 0, 2, 1, patch_load_u32 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFC # generate offset + addu $2, $2, $4 + load_u32_unaligned bios_rom, 1 + +1: + lui $2, %hi(bios_read_protect) # generate upper address + load_u32_unaligned bios_read_protect, 1 + +2: + open_load32_core + ror $2, $2, 8 + +execute_load_ewram_u32u1: + translate_region_ewram_load_align32 2, 1, patch_load_u32 + load_u32_unaligned (ewram + 0x8000), 1 + +execute_load_iwram_u32u1: + translate_region_align 3, 2, 1, patch_load_u32, (iwram + 0x8000), 0x7FFC + load_u32_unaligned (iwram + 0x8000), 1 + +execute_load_io_u32u1: + translate_region_align 4, 2, 1, patch_load_u32, io_registers, 0x3FC + load_u32_unaligned io_registers, 1 + +execute_load_palette_u32u1: + translate_region_align 5, 2, 1, patch_load_u32, palette_ram, 0x3FC + load_u32_unaligned palette_ram, 1 + +execute_load_vram_u32u1: + translate_region_vram_load_align32 2, 1, patch_load_u32 + load_u32_unaligned vram, 1 + +execute_load_oam_u32u1: + translate_region_align 7, 2, 1, patch_load_u32, oam_ram, 0x3FC + load_u32_unaligned oam_ram, 1 + +execute_load_gamepak8_u32u1: + translate_region_gamepak_align32 8, 2, 1, patch_load_u32 + load_u32_unaligned 0, 1 + +execute_load_gamepak9_u32u1: + translate_region_gamepak_align32 9, 2, 1, patch_load_u32 + load_u32_unaligned 0, 1 + +execute_load_gamepakA_u32u1: + translate_region_gamepak_align32 10, 2, 1, patch_load_u32 + load_u32_unaligned 0, 1 + +execute_load_gamepakB_u32u1: + translate_region_gamepak_align32 11, 2, 1, patch_load_u32 + load_u32_unaligned 0, 1 + +execute_load_gamepakC_u32u1: + translate_region_gamepak_align32 12, 2, 1, patch_load_u32 + load_u32_unaligned 0, 1 + +execute_load_eeprom_u32u1: + eeprom_load_align32 2, 1, patch_load_u32 + +execute_load_backup_u32u1: + backup_load_align32 2, 1, patch_load_u32 + ror $2, $2, 8 # rotate value by 8bits + +execute_load_open_u32u1: + open_load32_align32 2, 1, patch_load_u32 + ror $2, $2, 8 # rotate value by 8bits + + +# Unsigned unaligned (by 2) 32bit load handlers + +execute_load_bios_u32u2: + region_check_align 0, 2, 2, patch_load_u32 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFC # generate offset + addu $2, $2, $4 + load_u32_unaligned bios_rom, 2 + +1: + lui $2, %hi(bios_read_protect) # generate upper address + load_u32_unaligned bios_read_protect, 2 + +2: + open_load32_core + ror $2, $2, 16 + +execute_load_ewram_u32u2: + translate_region_ewram_load_align32 2, 2, patch_load_u32 + load_u32_unaligned (ewram + 0x8000), 2 + +execute_load_iwram_u32u2: + translate_region_align 3, 2, 2, patch_load_u32, (iwram + 0x8000), 0x7FFC + load_u32_unaligned (iwram + 0x8000), 2 + +execute_load_io_u32u2: + translate_region_align 4, 2, 2, patch_load_u32, io_registers, 0x3FC + load_u32_unaligned io_registers, 2 + +execute_load_palette_u32u2: + translate_region_align 5, 2, 2, patch_load_u32, palette_ram, 0x3FC + load_u32_unaligned palette_ram, 2 + +execute_load_vram_u32u2: + translate_region_vram_load_align32 2, 2, patch_load_u32 + load_u32_unaligned vram, 2 + +execute_load_oam_u32u2: + translate_region_align 7, 2, 2, patch_load_u32, oam_ram, 0x3FC + load_u32_unaligned oam_ram, 2 + +execute_load_gamepak8_u32u2: + translate_region_gamepak_align32 8, 2, 2, patch_load_u32 + load_u32_unaligned 0, 2 + +execute_load_gamepak9_u32u2: + translate_region_gamepak_align32 9, 2, 2, patch_load_u32 + load_u32_unaligned 0, 2 + +execute_load_gamepakA_u32u2: + translate_region_gamepak_align32 10, 2, 2, patch_load_u32 + load_u32_unaligned 0, 2 + +execute_load_gamepakB_u32u2: + translate_region_gamepak_align32 11, 2, 2, patch_load_u32 + load_u32_unaligned 0, 2 + +execute_load_gamepakC_u32u2: + translate_region_gamepak_align32 12, 2, 2, patch_load_u32 + load_u32_unaligned 0, 2 + +execute_load_eeprom_u32u2: + eeprom_load_align32 2, 2, patch_load_u32 + +execute_load_backup_u32u2: + backup_load_align32 2, 2, patch_load_u32 + ror $2, $2, 16 # rotate value by 16bits + +execute_load_open_u32u2: + open_load32_align32 2, 2, patch_load_u32 + ror $2, $2, 16 # rotate value by 16bits + +# Unsigned unaligned (by 1) 32bit load handlers + +execute_load_bios_u32u3: + region_check_align 0, 2, 3, patch_load_u32 + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFC # generate offset + addu $2, $2, $4 + load_u32_unaligned bios_rom, 3 + +1: + lui $2, %hi(bios_read_protect) # generate upper address + load_u32_unaligned bios_read_protect, 3 + +2: + open_load32_core + ror $2, $2, 24 + +execute_load_ewram_u32u3: + translate_region_ewram_load_align32 2, 3, patch_load_u32 + load_u32_unaligned (ewram + 0x8000), 3 + +execute_load_iwram_u32u3: + translate_region_align 3, 2, 3, patch_load_u32, (iwram + 0x8000), 0x7FFC + load_u32_unaligned (iwram + 0x8000), 3 + +execute_load_io_u32u3: + translate_region_align 4, 2, 3, patch_load_u32, io_registers, 0x3FC + load_u32_unaligned io_registers, 3 + +execute_load_palette_u32u3: + translate_region_align 5, 2, 3, patch_load_u32, palette_ram, 0x3FC + load_u32_unaligned palette_ram, 3 + +execute_load_vram_u32u3: + translate_region_vram_load_align32 2, 3, patch_load_u32 + load_u32_unaligned vram, 3 + +execute_load_oam_u32u3: + translate_region_align 7, 2, 3, patch_load_u32, oam_ram, 0x3FC + load_u32_unaligned oam_ram, 3 + +execute_load_gamepak8_u32u3: + translate_region_gamepak_align32 8, 2, 3, patch_load_u32 + load_u32_unaligned 0, 3 + +execute_load_gamepak9_u32u3: + translate_region_gamepak_align32 9, 2, 3, patch_load_u32 + load_u32_unaligned 0, 3 + +execute_load_gamepakA_u32u3: + translate_region_gamepak_align32 10, 2, 3, patch_load_u32 + load_u32_unaligned 0, 3 + +execute_load_gamepakB_u32u3: + translate_region_gamepak_align32 11, 2, 3, patch_load_u32 + load_u32_unaligned 0, 3 + +execute_load_gamepakC_u32u3: + translate_region_gamepak_align32 12, 2, 3, patch_load_u32 + load_u32_unaligned 0, 3 + +execute_load_eeprom_u32u3: + eeprom_load_align32 2, 3, patch_load_u32 + +execute_load_backup_u32u3: + backup_load_align32 2, 3, patch_load_u32 + ror $2, $2, 24 # rotate value by 24bits + +execute_load_open_u32u3: + open_load32_align32 2, 3, patch_load_u32 + ror $2, $2, 24 # rotate value by 24bits + + +load_u32_ftable: + .long execute_load_bios_u32 # 0x00 BIOS + .long execute_load_open_u32 # 0x01 open address + .long execute_load_ewram_u32 # 0x02 EWRAM + .long execute_load_iwram_u32 # 0x03 IWRAM + .long execute_load_io_u32 # 0x04 I/O registers + .long execute_load_palette_u32 # 0x05 Palette RAM + .long execute_load_vram_u32 # 0x06 VRAM + .long execute_load_oam_u32 # 0x07 OAM RAM + .long execute_load_gamepak8_u32 # 0x08 gamepak + .long execute_load_gamepak9_u32 # 0x09 gamepak + .long execute_load_gamepakA_u32 # 0x0A gamepak + .long execute_load_gamepakB_u32 # 0x0B gamepak + .long execute_load_gamepakC_u32 # 0x0C gamepak + + .long execute_load_eeprom_u32 # 0x0D gamepak/eeprom + .long execute_load_backup_u32 # 0x0E Flash ROM/SRAM + .long execute_load_open_u32 # 0x0F open + + .long execute_load_bios_u32u1 # 0x00 BIOS unaligned (1b) + .long execute_load_open_u32u1 # 0x01 open address unaligned (1b) + .long execute_load_ewram_u32u1 # 0x02 EWRAM unaligned (1b) + .long execute_load_iwram_u32u1 # 0x03 IWRAM unaligned (1b) + .long execute_load_io_u32u1 # 0x04 I/O registers unaligned (1b) + .long execute_load_palette_u32u1 # 0x05 Palette RAM unaligned (1b) + .long execute_load_vram_u32u1 # 0x06 VRAM unaligned (1b) + .long execute_load_oam_u32u1 # 0x07 OAM RAM unaligned (1b) + .long execute_load_gamepak8_u32u1 # 0x08 gamepak unaligned (1b) + .long execute_load_gamepak9_u32u1 # 0x09 gamepak unaligned (1b) + .long execute_load_gamepakA_u32u1 # 0x0A gamepak unaligned (1b) + .long execute_load_gamepakB_u32u1 # 0x0B gamepak unaligned (1b) + .long execute_load_gamepakC_u32u1 # 0x0C gamepak unaligned (1b) + .long execute_load_eeprom_u32u1 # 0x0D gamepak/eeprom unaligned (1b) + .long execute_load_backup_u32u1 # 0x0E Flash ROM/SRAM unaligned (1b) + .long execute_load_open_u32u1 # 0x0F open unaligned (1b) + + .long execute_load_bios_u32u2 # 0x00 BIOS unaligned (2b) + .long execute_load_open_u32u2 # 0x01 open address unaligned (2b) + .long execute_load_ewram_u32u2 # 0x02 EWRAM unaligned (2b) + .long execute_load_iwram_u32u2 # 0x03 IWRAM unaligned (2b) + .long execute_load_io_u32u2 # 0x04 I/O registers unaligned (2b) + .long execute_load_palette_u32u2 # 0x05 Palette RAM unaligned (2b) + .long execute_load_vram_u32u2 # 0x06 VRAM unaligned (2b) + .long execute_load_oam_u32u2 # 0x07 OAM RAM unaligned (2b) + .long execute_load_gamepak8_u32u2 # 0x08 gamepak unaligned (2b) + .long execute_load_gamepak9_u32u2 # 0x09 gamepak unaligned (2b) + .long execute_load_gamepakA_u32u2 # 0x0A gamepak unaligned (2b) + .long execute_load_gamepakB_u32u2 # 0x0B gamepak unaligned (2b) + .long execute_load_gamepakC_u32u2 # 0x0C gamepak unaligned (2b) + .long execute_load_eeprom_u32u2 # 0x0D gamepak/eeprom unaligned (2b) + .long execute_load_backup_u32u2 # 0x0E Flash ROM/SRAM unaligned (2b) + .long execute_load_open_u32u2 # 0x0F open unaligned (2b) + + .long execute_load_bios_u32u3 # 0x00 BIOS unaligned (3b) + .long execute_load_open_u32u3 # 0x01 open address unaligned (3b) + .long execute_load_ewram_u32u3 # 0x02 EWRAM unaligned (3b) + .long execute_load_iwram_u32u3 # 0x03 IWRAM unaligned (3b) + .long execute_load_io_u32u3 # 0x04 I/O registers unaligned (3b) + .long execute_load_palette_u32u3 # 0x05 Palette RAM unaligned (3b) + .long execute_load_vram_u32u3 # 0x06 VRAM unaligned (3b) + .long execute_load_oam_u32u3 # 0x07 OAM RAM unaligned (3b) + .long execute_load_gamepak8_u32u3 # 0x08 gamepak unaligned (3b) + .long execute_load_gamepak9_u32u3 # 0x09 gamepak unaligned (3b) + .long execute_load_gamepakA_u32u3 # 0x0A gamepak unaligned (3b) + .long execute_load_gamepakB_u32u3 # 0x0B gamepak unaligned (3b) + .long execute_load_gamepakC_u32u3 # 0x0C gamepak unaligned (3b) + .long execute_load_eeprom_u32u3 # 0x0D gamepak/eeprom unaligned (3b) + .long execute_load_backup_u32u3 # 0x0E Flash ROM/SRAM unaligned (3b) + .long execute_load_open_u32u3 # 0x0F open unaligned (3b) + +patch_load_u32: + patch_handler_align load_u32_ftable, 2 + + + +# Unsigned always aligned 32bit load handlers + +execute_load_bios_u32a: + region_check 0, patch_load_u32a + srl $2, $4, 14 # check if address is in BIOS region + bne $2, $0, 2f # if not, perform open read + srl $1, $5, 14 # check if PC is in BIOS region + bne $1, $0, 1f # if not, perform BIOS protected read + lui $2, %hi(bios_rom) # generate upper address (delay) + + andi $4, $4, 0x3FFF # generate offset + addu $2, $2, $4 + load_u32 bios_rom + +1: + lui $2, %hi(bios_read_protect) # generate upper address + load_u32 bios_read_protect + +2: + open_load32_a + nop + +execute_load_ewram_u32a: + translate_region_ewram patch_load_u32a + load_u32 (ewram + 0x8000) + +execute_aligned_load32: +execute_load_iwram_u32a: + translate_region 3, patch_load_u32a, (iwram + 0x8000), 0x7FFF + load_u32 (iwram + 0x8000) + +execute_load_io_u32a: + translate_region 4, patch_load_u32a, io_registers, 0x3FF + load_u32 io_registers + +execute_load_palette_u32a: + translate_region 5, patch_load_u32a, palette_ram, 0x3FF + load_u32 palette_ram + +execute_load_vram_u32a: + translate_region_vram patch_load_u32a + load_u32 vram + +execute_load_oam_u32a: + translate_region 7, patch_load_u32a, oam_ram, 0x3FF + load_u32 oam_ram + +execute_load_gamepak8_u32a: + translate_region_gamepak_a 8, patch_load_u32a + load_u32 0 + +execute_load_gamepak9_u32a: + translate_region_gamepak_a 9, patch_load_u32a + load_u32 0 + +execute_load_gamepakA_u32a: + translate_region_gamepak_a 10, patch_load_u32a + load_u32 0 + +execute_load_gamepakB_u32a: + translate_region_gamepak_a 11, patch_load_u32a + load_u32 0 + +execute_load_gamepakC_u32a: + translate_region_gamepak_a 12, patch_load_u32a + load_u32 0 + +execute_load_eeprom_u32a: + eeprom_load_a patch_load_u32a + +execute_load_backup_u32a: + backup_load_a patch_load_u32a + nop + +execute_load_open_u32a: + open_load32_a patch_load_u32a + +load_u32a_ftable: + .long execute_load_bios_u32a # 0x00 BIOS unaligned (3b) + .long execute_load_open_u32a # 0x01 open address unaligned (3b) + .long execute_load_ewram_u32a # 0x02 EWRAM unaligned (3b) + .long execute_load_iwram_u32a # 0x03 IWRAM unaligned (3b) + .long execute_load_io_u32a # 0x04 I/O registers unaligned (3b) + .long execute_load_palette_u32a # 0x05 Palette RAM unaligned (3b) + .long execute_load_vram_u32a # 0x06 VRAM unaligned (3b) + .long execute_load_oam_u32a # 0x07 OAM RAM unaligned (3b) + .long execute_load_gamepak8_u32a # 0x08 gamepak unaligned (3b) + .long execute_load_gamepak9_u32a # 0x09 gamepak unaligned (3b) + .long execute_load_gamepakA_u32a # 0x0A gamepak unaligned (3b) + .long execute_load_gamepakB_u32a # 0x0B gamepak unaligned (3b) + .long execute_load_gamepakC_u32a # 0x0C gamepak unaligned (3b) + .long execute_load_eeprom_u32a # 0x0D gamepak/eeprom unaligned (3b) + .long execute_load_backup_u32a # 0x0E Flash ROM/SRAM unaligned (3b) + .long execute_load_open_u32a # 0x0F open unaligned (3b) + +patch_load_u32a: + patch_handler load_u32a_ftable, 1 + + +# Unsigned 8bit store handlers + +execute_store_ignore0_u8: + ignore_region 0, patch_store_u8 + +execute_store_ignore1_u8: + ignore_region 1, patch_store_u8 + +execute_store_ewram_u8: + translate_region_ewram patch_store_u8 + store_u8_smc (ewram + 0x8000) + +execute_store_u8: +execute_store_iwram_u8: + translate_region 3, patch_store_u8, (iwram + 0x8000), 0x7FFF + store_u8_smc (iwram + 0x8000) + +execute_store_io_u8: + region_check 4, patch_store_u8 + andi $5, $5, 0xFF # make value 8bit + andi $4, $4, 0x3FF # wrap around address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + + save_registers + jal write_io_register8 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +execute_store_palette_u8: + region_check 5, patch_store_u8 + lui $2, %hi(palette_ram) # start loading palette_ram address (delay) + ins $5, $5, 8, 8 # double value + andi $4, $4, 0x3FE # align palette address + addu $2, $2, $4 + sh $5, %lo(palette_ram)($2) # palette_ram[address] = value + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + lui $2, %hi(palette_ram_converted) + addu $2, $2, $4 + jr $ra # return + sh $1, %lo(palette_ram_converted)($2) + +execute_store_vram_u8: + translate_region_vram_store_align16 patch_store_u8 + store_u8_double vram + +execute_store_oam_u8: + translate_region 7, patch_store_u8, oam_ram, 0x3FE + lui $1, %hi(oam_update) # write non-zero to oam_update + sw $1, %lo(oam_update)($1) # cheap, but this is non-zero + store_u8_double oam_ram + +execute_store_ignore8_u8: + ignore_region 8, patch_store_u8 + +execute_store_ignore9_u8: + ignore_region 9, patch_store_u8 + +execute_store_ignoreA_u8: + ignore_region 10, patch_store_u8 + +execute_store_ignoreB_u8: + ignore_region 11, patch_store_u8 + +execute_store_ignoreC_u8: + ignore_region 12, patch_store_u8 + +execute_store_eeprom_u8: + store_function write_eeprom, 13, patch_store_u8, 0x3FF + +execute_store_backup_u8: + store_function write_backup, 14, patch_store_u8, 0xFFFF + +execute_store_ignoreF_u8: + ignore_high patch_store_u8 + +store_u8_ftable: + .long execute_store_ignore0_u8 # 0x00 BIOS + .long execute_store_ignore1_u8 # 0x01 open address + .long execute_store_ewram_u8 # 0x02 EWRAM + .long execute_store_iwram_u8 # 0x03 IWRAM + .long execute_store_io_u8 # 0x04 I/O registers + .long execute_store_palette_u8 # 0x05 Palette RAM + .long execute_store_vram_u8 # 0x06 VRAM + .long execute_store_oam_u8 # 0x07 OAM RAM + .long execute_store_ignore8_u8 # 0x08 gamepak + .long execute_store_ignore9_u8 # 0x09 gamepak + .long execute_store_ignoreA_u8 # 0x0A gamepak + .long execute_store_ignoreB_u8 # 0x0B gamepak + .long execute_store_ignoreC_u8 # 0x0C gamepak + .long execute_store_eeprom_u8 # 0x0D gamepak/eeprom + .long execute_store_backup_u8 # 0x0E Flash ROM/SRAM + .long execute_store_ignoreF_u8 # 0x0F open address + +patch_store_u8: + patch_handler store_u8_ftable, 0x0F + + +# Unsigned 16bit store handlers + +execute_store_ignore0_u16: + ignore_region 0, patch_store_u16 + +execute_store_ignore1_u16: + ignore_region 1, patch_store_u16 + +execute_store_ewram_u16: + translate_region_ewram_store_align16 patch_store_u16 + store_u16_smc (ewram + 0x8000) + +execute_store_u16: +execute_store_iwram_u16: + translate_region 3, patch_store_u16, (iwram + 0x8000), 0x7FFE + store_u16_smc (iwram + 0x8000) + +execute_store_io_u16: + region_check 4, patch_store_u16 + andi $5, $5, 0xFFFF # make value 16bit + andi $4, $4, 0x3FE # wrap around/align address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + + save_registers + jal write_io_register16 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +execute_store_palette_u16: + region_check 5, patch_store_u16 + lui $2, %hi(palette_ram) # start loading palette_ram address (delay) + andi $4, $4, 0x3FE # wrap/align palette address + addu $2, $2, $4 + sh $5, %lo(palette_ram)($2) # palette_ram[address] = value + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + lui $2, %hi(palette_ram_converted) + addu $2, $2, $4 + jr $ra # return + sh $1, %lo(palette_ram_converted)($2) + +execute_store_vram_u16: + translate_region_vram_store_align16 patch_store_u16 + store_u16 vram + +execute_store_oam_u16: + translate_region 7, patch_store_u16, oam_ram, 0x3FE + lui $1, %hi(oam_update) # write non-zero to oam_update + sw $1, %lo(oam_update)($1) # cheap, but this is non-zero + store_u16 oam_ram + +execute_store_rtc_u16: + store_function write_rtc, 8, patch_store_u16, 0xFE + +execute_store_ignore9_u16: + ignore_region 9, patch_store_u16 + +execute_store_ignoreA_u16: + ignore_region 10, patch_store_u16 + +execute_store_ignoreB_u16: + ignore_region 11, patch_store_u16 + +execute_store_ignoreC_u16: + ignore_region 12, patch_store_u16 + +execute_store_eeprom_u16: + store_function write_eeprom, 13, patch_store_u16, 0x3FE + +execute_store_ignoreE_u16: + ignore_region 14, patch_store_u16 + +execute_store_ignoreF_u16: + ignore_high patch_store_u16 + +store_u16_ftable: + .long execute_store_ignore0_u16 # 0x00 BIOS + .long execute_store_ignore1_u16 # 0x01 open address + .long execute_store_ewram_u16 # 0x02 EWRAM + .long execute_store_iwram_u16 # 0x03 IWRAM + .long execute_store_io_u16 # 0x04 I/O registers + .long execute_store_palette_u16 # 0x05 Palette RAM + .long execute_store_vram_u16 # 0x06 VRAM + .long execute_store_oam_u16 # 0x07 OAM RAM + .long execute_store_rtc_u16 # 0x08 gamepak + .long execute_store_ignore9_u16 # 0x09 gamepak + .long execute_store_ignoreA_u16 # 0x0A gamepak + .long execute_store_ignoreB_u16 # 0x0B gamepak + .long execute_store_ignoreC_u16 # 0x0C gamepak + .long execute_store_eeprom_u16 # 0x0D gamepak/eeprom + .long execute_store_ignoreE_u16 # 0x0E Flash ROM/SRAM + .long execute_store_ignoreF_u16 # 0x0F open address + + +patch_store_u16: + patch_handler store_u16_ftable, 0x0F + + + + +# Unsigned 32bit store handlers + +execute_store_ignore0_u32: + ignore_region 0, patch_store_u32 + +execute_store_ignore1_u32: + ignore_region 1, patch_store_u32 + +execute_store_ewram_u32: + translate_region_ewram_store_align32 patch_store_u32 + store_u32_smc (ewram + 0x8000) + +execute_store_u32: +execute_store_iwram_u32: + translate_region 3, patch_store_u32, (iwram + 0x8000), 0x7FFC + store_u32_smc (iwram + 0x8000) + +execute_store_io_u32: + region_check 4, patch_store_u32 + nop + andi $4, $4, 0x3FC # wrap around/align address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + + save_registers + jal write_io_register32 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +execute_store_palette_u32: + region_check 5, patch_store_u32 + lui $2, %hi(palette_ram) # start loading palette_ram address (delay) + andi $4, $4, 0x3FC # wrap/align palette address + addu $2, $2, $4 + sw $5, %lo(palette_ram)($2) # palette_ram[address] = value + + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + lui $2, %hi(palette_ram_converted) + addu $2, $2, $4 + addiu $2, $2, %lo(palette_ram_converted) + sh $1, ($2) + + srl $5, $5, 16 # shift down to next palette value + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + + jr $ra # return + sh $1, 2($2) + +execute_store_vram_u32: + translate_region_vram_store_align32 patch_store_u32 + store_u32 vram + +execute_store_oam_u32: + translate_region 7, patch_store_u32, oam_ram, 0x3FC + lui $1, %hi(oam_update) # write non-zero to oam_update + sw $1, %lo(oam_update)($1) # cheap, but this is non-zero + store_u32 oam_ram + +execute_store_ignore8_u32: + ignore_region 8, patch_store_u32 + +execute_store_ignore9_u32: + ignore_region 9, patch_store_u32 + +execute_store_ignoreA_u32: + ignore_region 10, patch_store_u32 + +execute_store_ignoreB_u32: + ignore_region 11, patch_store_u32 + +execute_store_ignoreC_u32: + ignore_region 12, patch_store_u32 + +execute_store_eeprom_u32: + store_function write_eeprom, 13, patch_store_u32, 0x3FC + +execute_store_ignoreE_u32: + ignore_region 14, patch_store_u32 + +execute_store_ignoreF_u32: + ignore_high patch_store_u32 + +store_u32_ftable: + .long execute_store_ignore0_u32 # 0x00 BIOS + .long execute_store_ignore1_u32 # 0x01 open address + .long execute_store_ewram_u32 # 0x02 EWRAM + .long execute_store_iwram_u32 # 0x03 IWRAM + .long execute_store_io_u32 # 0x04 I/O registers + .long execute_store_palette_u32 # 0x05 Palette RAM + .long execute_store_vram_u32 # 0x06 VRAM + .long execute_store_oam_u32 # 0x07 OAM RAM + .long execute_store_ignore8_u32 # 0x08 gamepak + .long execute_store_ignore9_u32 # 0x09 gamepak + .long execute_store_ignoreA_u32 # 0x0A gamepak + .long execute_store_ignoreB_u32 # 0x0B gamepak + .long execute_store_ignoreC_u32 # 0x0C gamepak + .long execute_store_eeprom_u32 # 0x0D gamepak/eeprom + .long execute_store_ignoreE_u32 # 0x0E Flash ROM/SRAM + .long execute_store_ignoreF_u32 # 0x0F open address + + +patch_store_u32: + patch_handler store_u32_ftable, 0x0F + + + +# Unsigned always aligned, a2 safe 32bit store handlers + +execute_store_ignore0_u32a: + ignore_region 0, patch_store_u32a + +execute_store_ignore1_u32a: + ignore_region 1, patch_store_u32a + +execute_store_ewram_u32a: + translate_region_ewram_store_align32 patch_store_u32a + store_u32 (ewram + 0x8000) + +execute_aligned_store32: +execute_store_iwram_u32a: + translate_region 3, patch_store_u32a, (iwram + 0x8000), 0x7FFC + store_u32 (iwram + 0x8000) + +execute_store_io_u32a: + region_check 4, patch_store_u32a + nop + sw $6, REG_SAVE($16) # save a2 + sw $ra, REG_SAVE2($16) # save ra + + andi $4, $4, 0x3FC # wrap around/align address + + save_registers + jal write_io_register32 # write the value out + nop + + restore_registers + + lw $ra, REG_SAVE2($16) # restore ra + jr $ra + lw $6, REG_SAVE($16) # restore a2 + +execute_store_palette_u32a: + region_check 5, patch_store_u32a + lui $2, %hi(palette_ram) # start loading palette_ram address (delay) + andi $4, $4, 0x3FC # wrap/align palette address + addu $2, $2, $4 + sw $5, %lo(palette_ram)($2) # palette_ram[address] = value + + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + lui $2, %hi(palette_ram_converted) + addu $2, $2, $4 + addiu $2, $2, %lo(palette_ram_converted) + sh $1, ($2) + + srl $5, $5, 16 # shift down to next palette value + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + + jr $ra # return + sh $1, 2($2) + +execute_store_vram_u32a: + translate_region_vram_store_align32 patch_store_u32a + store_u32 vram + +execute_store_oam_u32a: + translate_region 7, patch_store_u32a, oam_ram, 0x3FC + lui $1, %hi(oam_update) # write non-zero to oam_update + sw $1, %lo(oam_update)($1) # cheap, but this is non-zero + store_u32 oam_ram + +execute_store_ignore8_u32a: + ignore_region 8, patch_store_u32a + +execute_store_ignore9_u32a: + ignore_region 9, patch_store_u32a + +execute_store_ignoreA_u32a: + ignore_region 10, patch_store_u32a + +execute_store_ignoreB_u32a: + ignore_region 11, patch_store_u32a + +execute_store_ignoreC_u32a: + ignore_region 12, patch_store_u32a + +execute_store_eeprom_u32a: + store_function_a write_eeprom, 13, patch_store_u32a, 0x3FC + +execute_store_ignoreE_u32a: + ignore_region 14, patch_store_u32a + +execute_store_ignoreF_u32a: + ignore_high patch_store_u32a + +store_u32a_ftable: + .long execute_store_ignore0_u32a# 0x00 BIOS + .long execute_store_ignore1_u32a# 0x01 open address + .long execute_store_ewram_u32a # 0x02 EWRAM + .long execute_store_iwram_u32a # 0x03 IWRAM + .long execute_store_io_u32a # 0x04 I/O registers + .long execute_store_palette_u32a# 0x05 Palette RAM + .long execute_store_vram_u32a # 0x06 VRAM + .long execute_store_oam_u32a # 0x07 OAM RAM + .long execute_store_ignore8_u32a# 0x08 gamepak + .long execute_store_ignore9_u32a# 0x09 gamepak + .long execute_store_ignoreA_u32a# 0x0A gamepak + .long execute_store_ignoreB_u32a# 0x0B gamepak + .long execute_store_ignoreC_u32a# 0x0C gamepak + .long execute_store_eeprom_u32a # 0x0D gamepak/eeprom + .long execute_store_ignoreE_u32a# 0x0E Flash ROM/SRAM + .long execute_store_ignoreF_u32a# 0x0F open address + +patch_store_u32a: + patch_handler store_u32a_ftable, 0x0F + + + +#execute_load_u8: +execute_load_full_u8: + srl $1, $4, 28 # check if the address is out of range + bne $1, $0, ext_load_u8 # if it is, perform an extended read + srl $2, $4, 15 # $1 = page number of address + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($2) + beq $1, $0, ext_load_u8 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lbu $2, ($1) # read the value + +ext_load_u8: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) # store return address + save_registers + jal read_memory8 # read the value + nop + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 4 # fix stack (delay slot) + +#execute_load_s8: +execute_load_full_s8: + srl $1, $4, 28 # check if the address is out of range + bne $1, $0, ext_load_s8 # if it is, perform an extended read + srl $2, $4, 15 # $1 = page number of address + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($2) + beq $1, $0, ext_load_s8 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lb $2, ($1) # read the value + +ext_load_s8: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) # store return address + save_registers + jal read_memory8 # read the value + nop + restore_registers + seb $2, $2 # sign extend the read value + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 4 # fix stack (delay slot) + +#execute_load_u16: +execute_load_full_u16: + srl $1, $4, 28 # check if the address is out of range + ins $1, $4, 4, 1 # or unaligned (bottom bit) + bne $1, $0, ext_load_u16 # if it is, perform an extended read + srl $2, $4, 15 # $1 = page number of address + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($2) + beq $1, $0, ext_load_u16 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lhu $2, ($1) # read the value + +ext_load_u16: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) # store return address + save_registers + jal read_memory16 # read the value + nop + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 4 # fix stack (delay slot) + +#execute_load_s16: +execute_load_full_s16: + srl $1, $4, 28 # check if the address is out of range + ins $1, $4, 4, 1 # or unaligned (bottom bit) + bne $1, $0, ext_load_s16 # if it is, perform an extended read + srl $2, $4, 15 # $1 = page number of address + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($2) + beq $1, $0, ext_load_s16 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lh $2, ($1) # read the value + +ext_load_s16: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) # store return address + save_registers + jal read_memory16_signed # read the value + nop + restore_registers + seh $2, $2 # sign extend the return value + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 4 # fix stack (delay slot) + +#execute_load_u32: +execute_load_full_u32: + srl $1, $4, 28 # check if the address is out of range + ins $1, $4, 4, 2 # or unaligned (bottom two bits) + bne $1, $0, ext_load_u32 # if it is, perform an extended read + srl $2, $4, 15 # $1 = page number of address + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($2) + beq $1, $0, ext_load_u32 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lw $2, ($1) # read the value + +ext_load_u32: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) # store return address + save_registers + jal read_memory32 # read the value + nop + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 4 # fix stack (delay slot) + +#execute_aligned_load32: + srl $2, $4, 28 # check if the address is out of range + bne $2, $0, ext_aligned_load32 # if it is, perform an extended load + srl $1, $4, 15 # $1 = page number of address + sll $1, $1, 2 # adjust to word index + addu $1, $1, $16 # $1 = memory_map_read[address >> 15] + lw $1, -32768($1) + beq $1, $0, ext_aligned_load32 # if it's NULL perform an extended read + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + lw $2, ($1) # read the value + +ext_aligned_load32: + addiu $sp, $sp, -8 # make room on the stack for $ra + sw $6, 4($sp) + sw $ra, ($sp) # store return address + save_registers + jal read_memory32 # read the value + nop + restore_registers + lw $6, 4($sp) + lw $ra, ($sp) # restore return address + jr $ra # return + addiu $sp, $sp, 8 # fix stack (delay slot) + +# General ext memory routines + +ext_store_ignore: + jr $ra # ignore these writes + nop + +write_io_epilogue: + beq $2, $0, no_alert # 0 means nothing happened + addiu $4, $2, -2 # see if return value is 2 (delay slot) + beq $4, $0, smc_dma # is it an SMC alert? (return value = 2) + nop + addiu $4, $2, -3 # see if return value is 3 + beq $4, $0, irq_alert # is it an IRQ alert? (return value = 3) + nop + collapse_flags # make sure flags are good for update_gba + +alert_loop: + jal update_gba # process the next event + nop + lw $1, CPU_HALT_STATE($16) # check if CPU is sleeping + bne $1, $0, alert_loop # see if it hasn't changed + nop + + addu $17, $2, $0 # $17 = new cycle counter + lw $4, REG_PC($16) # $4 = new PC + + j lookup_pc + addiu $sp, $sp, 4 # fix the stack (delay slot) + +irq_alert: + restore_registers + j lookup_pc # PC has changed, get a new one + addiu $sp, $sp, 4 # fix the stack + +no_alert: + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # we can return + addiu $sp, $sp, 4 # fix the stack + +smc_dma: + addiu $sp, $sp, 4 # fix the stack + jal flush_translation_cache_ram # flush translation cache + nop + j lookup_pc + nop + + +ext_store_eeprom: + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_eeprom # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # we can return + addiu $sp, $sp, 4 # fix the stack + + +# 8bit ext memory routines + +ext_store_io8: + andi $5, $5, 0xFF # make value 8bit + andi $4, $4, 0x3FF # wrap around address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_io_register8 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +ext_store_palette8: + j ext_store_palette16b # perform 16bit palette write + andi $4, $4, 0x3FE # wrap + align (delay) + +ext_store_vram8: + ins $5, $5, 8, 8 # value = (value << 8) | value + ext $4, $4, 0, 17 # address = adress & 0x1FFFF + ins $4, $0, 0, 1 # align out bottom bit + lui $1, %hi(0x18000) # $1 = 0x18000 + sltu $1, $4, $1 # see if address < 0x18000 + bne $1, $0, ext_store_vram8b + lui $2, %hi(vram) # start loading vram address (delay) + + addiu $4, $4, -0x8000 # move address into VRAM region + +ext_store_vram8b: + addu $2, $2, $4 # $2 = (hi)vram + address + jr $ra # return + sh $5, %lo(vram)($2) # vram[address] = value (delay) + +ext_store_oam8: + lui $1, %hi(oam_update) # $1 = oam_update + addiu $1, %lo(oam_update) + li $2, 1 # $2 = 1 + sw $2, ($1) # *oam_update = 1 + andi $4, $4, 0x3FE # wrap around address and align to 16bits + ins $5, $5, 8, 8 # value = (value << 8) | value + lui $1, %hi(oam_ram) # $1 = (hi)oam_ram + addu $1, $1, $4 # $1 = (hi)oam_ram + address + jr $ra # return + sh $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay) + +ext_store_backup: + andi $5, $5, 0xFF # make value 8bit + andi $4, $4, 0xFFFF # mask value + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_backup # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # we can return + addiu $sp, $sp, 4 # fix the stack + +ext_store_u8_jtable: + .long ext_store_ignore # 0x00 BIOS + .long ext_store_ignore # 0x01 invalid + .long ext_store_ignore # 0x02 EWRAM + .long ext_store_ignore # 0x03 IWRAM + .long ext_store_io8 # 0x04 I/O registers + .long ext_store_palette8 # 0x05 Palette RAM + .long ext_store_vram8 # 0x06 VRAM + .long ext_store_oam8 # 0x07 OAM RAM + .long ext_store_ignore # 0x08 gamepak (no RTC accepted in 8bit) + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_backup # 0x0E Flash ROM/SRAM + .long ext_store_ignore # 0x0F invalid + + + +ext_store_u8: + srl $1, $4, 24 # $1 = address >> 24 + sltu $2, $1, 16 # check if the value is out of range + beq $2, $0, ext_store_ignore + sll $1, $1, 2 # make address word indexed (delay) + lui $2, %hi(ext_store_u8_jtable) + addu $2, $2, $1 + # $2 = ext_store_u8_jtable[address >> 24] + lw $2, %lo(ext_store_u8_jtable)($2) + jr $2 # jump to table location + nop + +# $4: address to write to +# $5: value to write +# $6: current PC + +#execute_store_u8: + srl $1, $4, 28 # check if the address is out of range + bne $1, $0, ext_store_u8 # if it is, perform an extended write + srl $2, $4, 15 # $1 = page number of address (delay slot) + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 + lw $1, 256($2) # $1 = memory_map_write[address >> 15] + beq $1, $0, ext_store_u8 # if it's NULL perform an extended write + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + lb $2, -32768($1) # load the SMC status + bne $2, $0, smc_write # is there code there? + sb $5, ($1) # store the value (delay slot) + jr $ra # return + nop + +# 16bit ext memory routines + +ext_store_io16: + andi $4, $4, 0x3FF # wrap around address + andi $5, $5, 0xFFFF # make value 16bit + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_io_register16 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +ext_store_palette16: + andi $4, 0x3FF # wrap address + +ext_store_palette16b: + lui $2, %hi(palette_ram) + addu $2, $2, $4 + sh $5, %lo(palette_ram)($2) # palette_ram[address] = value + sll $1, $5, 1 # make green 6bits + ins $1, $0, 0, 6 # make bottom bit 0 + ins $1, $5, 0, 5 # insert red channel into $1 + lui $2, %hi(palette_ram_converted) + addu $2, $2, $4 + jr $ra # return + sh $1, %lo(palette_ram_converted)($2) + +ext_store_vram16: + ext $4, $4, 0, 17 # address = adress & 0x1FFFF + lui $1, %hi(0x18000) # $1 = 0x18000 + sltu $1, $4, $1 # see if address < 0x18000 + bne $1, $0, ext_store_vram16b + lui $2, %hi(vram) # start loading vram address (delay) + + addiu $4, $4, -0x8000 # move address into VRAM region + +ext_store_vram16b: + addu $2, $2, $4 # $2 = (hi)vram + address + jr $ra # return + sh $5, %lo(vram)($2) # vram[address] = value (delay) + +ext_store_oam16: + lui $1, %hi(oam_update) # $1 = oam_update + addiu $1, %lo(oam_update) + li $2, 1 # $2 = 1 + sw $2, ($1) # *oam_update = 1 + andi $4, $4, 0x3FF # wrap around address + lui $1, %hi(oam_ram) # $1 = (hi)oam_ram + addu $1, $1, $4 # $1 = (hi)oam_ram + address + jr $ra # return + sh $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay) + +ext_store_rtc: + andi $5, $5, 0xFFFF # make value 16bit + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_rtc # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + restore_registers + lw $ra, ($sp) # restore return address + jr $ra # we can return + addiu $sp, $sp, 4 # fix the stack + +ext_store_u16_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io16 # 0x04 I/O registers + .long ext_store_palette16 # 0x05 Palette RAM + .long ext_store_vram16 # 0x06 VRAM + .long ext_store_oam16 # 0x07 OAM RAM + .long ext_store_rtc # 0x08 gamepak, RTC + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_ignore # 0x0E Flash ROM/SRAM + +ext_store_u16: + srl $1, $4, 24 # $1 = address >> 24 + sltu $2, $1, 16 # check if the value is out of range + beq $2, $0, ext_store_ignore + sll $1, $1, 2 # make address word indexed (delay) + lui $2, %hi(ext_store_u16_jtable) + addu $2, $2, $1 + # $2 = ext_store_u16_jtable[address >> 24] + lw $2, %lo(ext_store_u16_jtable)($2) + jr $2 # jump to table location + nop + + +#execute_store_u16: + srl $1, $4, 28 # check if the address is out of range + bne $1, $0, ext_store_u16 # if it is, perform an extended write + srl $2, $4, 15 # $1 = page number of address (delay slot) + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 + lw $1, 256($2) # $1 = memory_map_write[address >> 15] + beq $1, $0, ext_store_u16 # if it's NULL perform an extended write + andi $2, $4, 0x7FFE # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + lh $2, -32768($1) # load the SMC status + bne $2, $0, smc_write # is there code there? + sh $5, ($1) # store the value (delay slot) + jr $ra # return + nop + + + + + + + + +# 32bit ext memory routines + +ext_store_io32: + andi $4, $4, 0x3FF # wrap around address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_io_register32 # write the value out + sw $6, REG_PC($16) # save the PC (delay slot) + j write_io_epilogue # handle any state changes + nop + +ext_store_palette32: + addu $6, $ra, $0 # save return address in $6 + jal ext_store_palette16b # write out palette entry + andi $4, 0x3FF # wrap address (delay) + addiu $4, $4, 2 # go to next location + srl $5, $5, 16 # shift to next 16bit value + j ext_store_palette16b # write out next palette entry + addu $ra, $6, $0 # restore return address (delay) + +ext_store_vram32: + ext $4, $4, 0, 17 # address = adress & 0x1FFFF + lui $1, %hi(0x18000) # $1 = 0x18000 + sltu $1, $4, $1 # see if address < 0x18000 + bne $1, $0, ext_store_vram32b + lui $2, %hi(vram) # start loading vram address (delay) + + addiu $4, $4, -0x8000 # move address into VRAM region + +ext_store_vram32b: + addu $2, $2, $4 # $2 = (hi)vram + address + jr $ra # return + sw $5, %lo(vram)($2) # vram[address] = value (delay) + +ext_store_oam32: + lui $1, %hi(oam_update) # $1 = oam_update + addiu $1, %lo(oam_update) + li $2, 1 # $2 = 1 + sw $2, ($1) # *oam_update = 1 + andi $4, $4, 0x3FF # wrap around address + lui $1, %hi(oam_ram) # $1 = (hi)oam_ram + addu $1, $1, $4 # $1 = (hi)oam_ram + address + jr $ra # return + sw $5, %lo(oam_ram)($1) # oam_ram[address] = value (delay) + +ext_store_u32_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io32 # 0x04 I/O registers + .long ext_store_palette32 # 0x05 Palette RAM + .long ext_store_vram32 # 0x06 VRAM + .long ext_store_oam32 # 0x07 OAM RAM + .long ext_store_ignore # 0x08 gamepak, ignore + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_ignore # 0x0E Flash ROM/SRAM + +ext_store_u32: + srl $1, $4, 24 # $1 = address >> 24 + sltu $2, $1, 16 # check if the value is out of range + beq $2, $0, ext_store_ignore + sll $1, $1, 2 # make address word indexed (delay) + lui $2, %hi(ext_store_u32_jtable) + addu $2, $2, $1 + # $2 = ext_store_u32_jtable[address >> 24] + lw $2, %lo(ext_store_u32_jtable)($2) + jr $2 # jump to table location + nop + +#execute_store_u32: +execute_store_full_u32: + srl $1, $4, 28 # check if the address is out of range + bne $1, $0, ext_store_u32 # if it is, perform an extended write + srl $2, $4, 15 # $1 = page number of address (delay slot) + sll $2, $2, 2 # adjust to word index + addu $2, $2, $16 + lw $1, 256($2) # $1 = memory_map_write[address >> 15] + beq $1, $0, ext_store_u32 # if it's NULL perform an extended write + andi $2, $4, 0x7FFC # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + lw $2, -32768($1) # load the SMC status + bne $2, $0, smc_write # is there code there? + sw $5, ($1) # store the value (delay slot) + jr $ra # return + nop + + +# 32bit ext aligned, non a2 destroying routines + +ext_store_io32a: + andi $4, $4, 0x3FF # wrap around address + addiu $sp, $sp, -4 # make room on the stack for $ra + sw $ra, ($sp) + save_registers + jal write_io_register32 # write the value out + sw $6, REG_SAVE($16) # save a2 + lw $6, REG_SAVE($16) # restore a2 + j write_io_epilogue # handle any state changes + nop + +ext_store_palette32a: + sw $ra, REG_SAVE($16) # save return address + jal ext_store_palette16b # write out palette entry + andi $4, 0x3FF # wrap address (delay) + addiu $4, $4, 2 # go to next location + srl $5, $5, 16 # shift to next 16bit value + j ext_store_palette16b # write out next palette entry + lw $ra, REG_SAVE($16) # restore return address (delay) + +ext_store_u32a_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io32a # 0x04 I/O registers + .long ext_store_palette32a # 0x05 Palette RAM + .long ext_store_vram32 # 0x06 VRAM + .long ext_store_oam32 # 0x07 OAM RAM + .long ext_store_ignore # 0x08 gamepak, ignore + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_ignore # 0x0D EEPROM (nothing will write this) + .long ext_store_ignore # 0x0E Flash ROM/SRAM + +ext_aligned_store32: + srl $1, $4, 24 # $1 = address >> 24 + sltu $2, $1, 16 # check if the value is out of range + beq $2, $0, ext_store_ignore + sll $1, $1, 2 # make address word indexed (delay) + lui $2, %hi(ext_store_u32a_jtable) + addu $2, $2, $1 + # $2 = ext_store_u32a_jtable[address >> 24] + lw $2, %lo(ext_store_u32a_jtable)($2) + jr $2 # jump to table location + nop + +#execute_aligned_store32: + srl $2, $4, 28 # check if the address is out of range + bne $2, $0, ext_aligned_store32 # if it is, perform an extended load + srl $1, $4, 15 # $1 = page number of address + sll $1, $1, 2 # adjust to word index + addu $1, $1, $16 # $1 = memory_map_write[address >> 15] + lw $1, 256($1) + beq $1, $0, ext_aligned_store32 # if it's NULL perform an extended write + andi $2, $4, 0x7FFF # $2 = low 15bits of address (delay slot) + addu $1, $1, $2 # add the memory map offset + jr $ra # return + sw $5, ($1) # write the value + +smc_write: + save_registers + jal flush_translation_cache_ram # flush translation cache + sw $6, REG_PC($16) # save PC (delay slot) + +lookup_pc: + lw $2, REG_CPSR($16) # $2 = cpsr + andi $2, $2, 0x20 # isolate mode bit + beq $2, $0, lookup_pc_arm # if T bit is zero use arm handler + nop + +lookup_pc_thumb: + jal block_lookup_address_thumb # get Thumb address + lw $4, REG_PC($16) # load PC as arg 0 (delay slot) + restore_registers + jr $2 # jump to result + nop + +lookup_pc_arm: + jal block_lookup_address_arm # get ARM address + lw $4, REG_PC($16) # load PC as arg 0 (delay slot) + restore_registers + jr $2 # jump to result + nop + +# Return the current cpsr + +execute_read_cpsr: + collapse_flags # fold flags into cpsr, put cpsr into $2 + jr $ra # return + nop + +# Return the current spsr + +execute_read_spsr: + lw $1, CPU_MODE($16) # $1 = cpu_mode + lui $2, %hi(spsr) + sll $1, $1, 2 # adjust to word offset size + addu $2, $2, $1 + jr $ra # return + lw $2, %lo(spsr)($2) # $2 = spsr[cpu_mode] (delay slot) + +# Switch into SWI, has to collapse flags +# $4: Current pc + +execute_swi: + add $sp, $sp, -4 # push $ra + sw $ra, ($sp) + lui $1, %hi(SUPERVISOR_LR) + sw $4, %lo(SUPERVISOR_LR)($1) # store next PC in the supervisor's LR + collapse_flags # get cpsr in $2 + lui $5, %hi(SUPERVISOR_SPSR) + sw $2, %lo(SUPERVISOR_SPSR)($5) # save cpsr in SUPERVISOR_CPSR + ins $2, $0, 0, 6 # zero out bottom 6 bits of CPSR + ori $2, 0x13 # set mode to supervisor + sw $2, REG_CPSR($16) # write back CPSR + save_registers + jal set_cpu_mode # set the CPU mode to supervisor + li $4, 3 # 3 is supervisor mode (delay slot) + restore_registers + lw $ra, ($sp) # pop $ra + jr $ra # return + add $sp, $sp, 4 # fix stack (delay slot) + +# $4: pc to restore to +# returns in $4 + +execute_spsr_restore: + lw $1, CPU_MODE($16) # $1 = cpu_mode + + beq $1, $0, no_spsr_restore # only restore if the cpu isn't usermode + lui $2, %hi(spsr) # start loading SPSR (delay) + + sll $1, $1, 2 # adjust to word offset size + addu $2, $2, $1 + lw $1, %lo(spsr)($2) # $1 = spsr[cpu_mode] + sw $1, REG_CPSR($16) # cpsr = spsr[cpu_mode] + extract_flags_body # extract flags from $1 + addiu $sp, $sp, -4 + sw $ra, ($sp) + save_registers + jal execute_spsr_restore_body # do the dirty work in this C function + nop + restore_registers + addu $4, $2, $0 # move return value to $4 + lw $ra, ($sp) + jr $ra + addiu $sp, $sp, 4 + +no_spsr_restore: + jr $ra + nop + +# $4: new cpsr +# $5: store mask +# $6: current PC + +execute_store_cpsr: + and $1, $4, $5 # $1 = new_cpsr & store_mask + lw $2, REG_CPSR($16) # $2 = current cpsr + nor $4, $5, $0 # $4 = ~store_mask + and $2, $2, $4 # $2 = (cpsr & (~store_mask)) + or $1, $1, $2 # $1 = new cpsr combined with old + extract_flags_body # extract flags from $1 + addiu $sp, $sp, -4 + sw $ra, ($sp) + save_registers + jal execute_store_cpsr_body # do the dirty work in this C function + addu $4, $1, $0 # load the new CPSR (delay slot) + + bne $2, $0, changed_pc_cpsr # this could have changed the pc + nop + + restore_registers + + lw $ra, ($sp) + jr $ra + addiu $sp, $sp, 4 + +changed_pc_cpsr: + jal block_lookup_address_arm # GBA address is in $4 + addu $4, $2, $0 # load new address in $4 (delay slot) + restore_registers # restore registers + jr $2 # jump to the new address + addiu $sp, $sp, 4 # get rid of the old ra (delay slot) + + +# $4: new spsr +# $5: store mask + +execute_store_spsr: + lw $1, CPU_MODE($16) # $1 = cpu_mode + lui $2, %hi(spsr) + sll $1, $1, 2 # adjust to word offset size + addu $1, $2, $1 + lw $2, %lo(spsr)($1) # $2 = spsr[cpu_mode] + and $4, $4, $5 # $4 = new_spsr & store_mask + nor $5, $5, $0 # $5 = ~store_mask + and $2, $2, $5 # $2 = (spsr & (~store_mask)) + or $4, $4, $2 # $4 = new spsr combined with old + jr $ra # return + sw $4, %lo(spsr)($1) # spsr[cpu_mode] = $4 (delay slot) + +# $4: value +# $5: shift + +execute_lsl_flags_reg: + beq $5, $0, lsl_shift_zero # is the shift zero? + sltiu $1, $5, 32 # $1 = (shift < 32) (delay) + beq $1, $0, lsl_shift_high # is the shift >= 32? + li $2, 32 + + subu $2, $2, $5 # $2 = (32 - shift) + srlv $2, $4, $2 # $2 = (value >> (32 - shift)) + andi $22, $2, 1 # c flag = (value >> (32 - shift)) & 0x01 + +lsl_shift_zero: + jr $ra # return + sllv $4, $4, $5 # return (value << shift) (delay) + +lsl_shift_high: + sltiu $1, $5, 33 # $1 = (shift < 33) (delay) + bne $1, $0, lsl_shift_done # jump if shift == 32 + andi $22, $4, 1 # c flag = value & 0x01 (delay) + + add $22, $0, $0 # c flag = 0 otherwise + +lsl_shift_done: + jr $ra # return + add $4, $0, $0 # value = 0 no matter what + + +execute_lsr_flags_reg: + beq $5, $0, lsr_shift_zero # is the shift zero? + sltiu $1, $5, 32 # $1 = (shift < 32) (delay) + beq $1, $0, lsr_shift_high # is the shift >= 32? + addiu $2, $5, -1 # $2 = shift - 1 (delay) + + srlv $2, $4, $2 # $2 = (value >> (shift - 1)) + andi $22, $2, 1 # c flag = (value >> (32 - shift)) & 0x01 + +lsr_shift_zero: + jr $ra # return + srlv $4, $4, $5 # return (value >> shift) (delay) + +lsr_shift_high: + sltiu $1, $5, 33 # $1 = (shift < 33) (delay) + bne $1, $0, lsr_shift_done # jump if shift == 32 + srl $22, $4, 31 # c flag = value >> 31 (delay) + + add $22, $0, $0 # c flag = 0 otherwise + +lsr_shift_done: + jr $ra # return + add $4, $0, $0 # value = 0 no matter what + + +execute_asr_flags_reg: + beq $5, $0, asr_shift_zero # is the shift zero? + sltiu $1, $5, 32 # $1 = (shift < 32) (delay) + beq $1, $0, asr_shift_high # is the shift >= 32? + addiu $2, $5, -1 # $2 = shift - 1 (delay) + + srlv $2, $4, $2 # $2 = (value >> (shift - 1)) + andi $22, $2, 1 # c flag = (value >> (32 - shift)) & 0x01 + +asr_shift_zero: + jr $ra # return + srav $4, $4, $5 # return (value >> shift) (delay) + +asr_shift_high: + sra $4, $4, 31 # value >>= 31 + jr $ra # return + andi $22, $4, 1 # c flag = value & 0x01 + + +execute_ror_flags_reg: + beq $5, $0, ror_zero_shift # is the shift zero? + addiu $1, $5, -1 # $1 = (shift - 1) (delay) + + srav $1, $4, $1 # $1 = (value >> (shift - 1)) + andi $22, $1, 1 # c flag = $1 & 1 + +ror_zero_shift: + jr $ra # return + rotrv $4, $4, $5 # return (value ror shift) delay + +# $4: cycle counter argument + +execute_arm_translate: + addu $17, $4, $0 # load cycle counter register + lui $16, %hi(reg) # load base register + addiu $16, %lo(reg) + extract_flags # load flag variables + + and $1, $1, 0x20 # see if Thumb bit is set in flags + + bne $1, $0, 1f + lw $4, REG_PC($16) # load PC into $4 (delay) + + jal block_lookup_address_arm # lookup initial jump address + nop + restore_registers # load initial register values + jr $2 # jump to return + nop + +1: + jal block_lookup_address_thumb # lookup initial jump address + nop + restore_registers # load initial register values + jr $2 # jump to return + nop + +# sceKernelInvalidateIcacheRange gives me problems, trying this instead +# Invalidates an n byte region starting at the start address +# $4: start location +# $5: length + +invalidate_icache_region: + ins $4, $0, 0, 6 # align to 64 bytes + addiu $2, $5, 63 # align up to 64 bytes + srl $2, $2, 6 # divide by 64 + beq $2, $0, done # exit early on 0 + nop + +iir_loop: + cache 0x08, ($4) # hit invalidate icache line + addiu $2, $2, -1 # next loop iteration + bne $2, $0, iir_loop # loop + addiu $4, $4, 64 # go to next cache line (delay slot) + +done: + jr $ra # return + nop + +# Writes back dcache and invalidates icache. + +invalidate_all_cache: + addu $4, $0, $0 # $4 = 0 + addiu $5, $0, 0x4000 # $5 = 0x4000 + +iac_loop: + cache 0x14, 0($4) # index invalidate/writeback dcache index + addiu $4, $4, 0x40 # goto next cache line + bne $4, $5, iac_loop # next iteration + cache 0x04, -0x40($4) # index invalidate icache index.. maybe? + + jr $ra # return + nop + + +step_debug_mips: + addiu $sp, $sp, -4 + sw $ra, ($sp) + collapse_flags + save_registers + jal step_debug + addiu $5, $17, 0 + restore_registers + lw $ra, ($sp) + jr $ra + addiu $sp, $sp, 4 + +memory_map_read: + .space 0x8000 + +reg: + .space 0x100 + +memory_map_write: + .space 0x8000 + diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..15bf6fd --- /dev/null +++ b/readme.txt @@ -0,0 +1,880 @@ +-- gameplaySP Gameboy Advance emulator for Playstation Portable -- + + +-- Release log -- + +v0.91 (minor cleanup release) + +NOTE: I don't usually do minor releases but I rewrote a ton of +things in gpSP 0.9, much of it during the last few days, and although +I spent a lot of time debugging a few bugs inevitably crept in. + +# Fixed some issues in the new memory handlers that crept up, hopefully + should fix the problems between 0.8 and 0.9. +# Fixed a bug introduced in 0.9 that could cause crashes when selecting + things in the menu (I hope, at least). +# Fixed a bug with a certain invalid opcode causing a jump to be scanned + when there isn't one (fixes Sabre Wulf). +# Removed 2048 option for audio buffer. + +v0.9 (yes, it's still beta) + +NOTE: As some of you may be aware I'm pretty much tired of these +unofficial releases by people (okay, mostly single person) who +don't wish to follow my wishes. I'm in the process of asking this +person to stop, in his own language. However, I want to make +something clear. Look at the last six new features in this +changelog. I added these TODAY. I could have done them at any +time. But I didn't, because I spent many (dozens, quite possibly +hundreds) hours debugging games that people want to play. I have +always believed that this is far more important than spending time +on new features. Frankly, I'm tired of my emulator being hacked on +by other people, and if it doesn't stop I'm going to make this +project closed source. + +Since I know this information is most visible when updated on the +major sites, note that it is the news posters I am especially +talking to. Next time you upload unofficial releases of my +emulator (without even knowing what's changed) bear in mind that +you're only encouraging me to stop working on this. If you want +to pick sides between me and unofficial devs, be my guest. I'll +let you decide by the contents of this release who's doing more +for my emulator. + +Oh, and if you downloaded a version of gpSP that has more than +"gpSP" in its name then you're using one of their versions. Shame +on them for not even removing this threatening message, and shame +on you. Unless you're using a port I endorse (GP2X, Dreamcast, etc), +in which case everything's good. + + +# Fixed stereo output being reversed. +# Fixed a bug causing misaligned errors on 8bit writes to the gbc + audio channel 3 wave data (fixes various Super Robot Wars games) +# Fixed DMA with garbage in their upper 4 bits (fixes a crash in + Zelda: Minish Cap) +# Added double buffering to the rendering, removes line artifacts. + Big thanks to Brunni for the idea. +# Fixed a bug preventing some SRAM based games from saving (fixes + MMBN4-6) +# Fixed a bug causing part of EWRAM to potentially get corrupted if + code segments loaded in EWRAM cross 32KB boundaries (fixes + Phantasy Star 2) +# Fixed a bug causing games using movs pc in user mode (very bad + behavior) to crash. Fixes Colin McRae Rally 2.0. +# Improved timing a bit more. Fixes GTA Advance. +# Fixed a sprite clipping bug (fixes crash in third boss of Zelda: + Minish cap) +# Increased translation buffer size significantly (fixes Donkey Kong: + King of Swing) +# Fixed a dynarec bug causing add pc, reg to not work in Thumb code + (fixes crash in DBZ:LoZ, seems to fix crashes in battle in Golden + Sun, probably fixes other games) +# Made sprites using tiles < 512 not display in modes 3-5 (fixes + a couple minor graphical bugs) +# Removed abort on instruction 0x00000000 hack, was breaking a + certain bugged up game (Scurge) +# Fixed bug in flags generating variable logical shifts (fixes + SD Gundam Force) +# Fixed unaligned 16bit reads (fixes DBZ:LoZ in game) +# Redid contiguous block flag modification checking AGAIN and + hopefully got it right this time (fixes Mario vs. Donkey Kong) +# Redid ldm/stm instructions, fixing some cases (along with the + timing improvements fixes Mario & Luigi) +# Fixed 14bit EEPROM addressing (hopefully fixes saving in a lot + of games) +# Completely redid memory handlers, accurately emulates open and + BIOS reads now. Fixes Zelda: Minish Cap (roll bug, last dungeon), + Rayman, MMBN 1 (last dungeon), probably others. +# Fixed a minor graphical glitch on the edges of the screen + (thanks Brunni and hlide for the help!) +# Fixed crash on loading savestates from files of games not currently + loaded, but be sure you have the exact file you loaded it from or + gpSP will exit. +@ New memory handlers should provide performance boost for games + that access VRAM significantly (ie 3D games) +@ Added dead flag elimination checking for logical shifts, probably + doesn't make a noticeable difference but should have been there + anyway. ++ Added rapidfire to the button mappings. ++ Added auto frameskip. Removed fractional frameskip (don't think + it's very useful with auto anyway). Select auto in the graphics/ + sound menu to activate it; frameskip value will act as the + maximum (auto is by default on). Thanks again to Brunni for some + help with this. Frameskip options are game specific. ++ Added vsync to the rendering. Only occurs when frames aren't + skipped. Seems to reduce tearing at least some of the time. ++ Added non-filtered video option. ++ Cheat support (Gameshark/Pro Action Replay v1-v3 only), still + in early stages, doesn't support everything; codes may cause + the game to crash, haven't determined yet if the codes are bad + or the implementation is. See cheat section for more information. ++ Added ability to change audio buffer size. Does not take affect + until you restart the game. ++ Added analog config options. ++ Added ability to set analog sensitivity and turn off analog. ++ Added ability to change the clock speed. This is a game specific + option. Try lower speeds w/auto frameskip to save battery life. ++ Fixed savestate speed on crappy Sony sticks. + +(legend: # bug fix, + feature addition, @ optimization) + +v0.8 - ("unlocked" beta) + +NOTE 1: It has come to my attention that there are actually BIOSes +out there that are being used that cause some games to not work. +The BIOS md5sum listed here is for the BIOS actually in GBAs and +is as accurate as you'll get, (if you have a GBA and a flashcart +you can dump it yourself, see http://wiki.pocketheaven.com/GBA_BIOS) + +NOTE 2: Since I know this is as far as a lot of people here I have a +little request. Please, please, (I'd italicize this if I could) +please stop constantly asking me when the next release will be, +what it'll have, etc. And while you're at it, please stop asking me +to implement wi-fi multiplayer, cheat support, or fix all of your +games. Some things will happen in due time, other things might not +ever happen. I devote about as much time as I can to this emulator +and I carefully include as much as I can in releases to try to +minimize the number of people who will nag me next time (erm, I +mean, to make the most people happy), so I don't release every other +day or anything like that. Sorry that I can't release once a week, +but I'm a lot busier now than I was when I was first developing this +emulator. Good thing I got the first version out before that, wasn't +it? + +Congratulations, you made it this far! Now read the rest of the this +thing. *_* + + +# Fixed bug in dead flag elimination, "alt" version no longer needed. +# Fixed EEPROM saves being saved as 32kb instead of 512bytes/8kb ++ 32MB ROM support has been added. ROMS are "demand loaded" as + necessary and page swapped out; there might be a small loading lag, + but I have yet to ever really notice anything. + NOTE: 32MB ROM support only works for unzipped ROMs. ++ Save states have been added. See the save state menu for save/load + options. ++ Support for the real-time clock (RTC) chip in Pokemon cartridegs + and other games. The implementation is based off of VBA's, whatever + notes on gbadev I could find, and some of my own reverse engineering + of what the games do... it might not be totally correct. Also, + setting the time does not work. ++ Per-game configuration. Currently this only saves frameskip and + frameskip variation options. ++ Removed the flash type option from the menu and instead added it + to game_config.txt. Hopefully got everything - let me know if you + find something that isn't there. It's pretty easy to add them if you + have to. ++ Added a display in the upper left-hand corner to indicate when + fast-forward is on. ++ Added button bindings for save/load state. +@ Found a fix of StrmnNrmn proportion: far too much unnecessary mutex + synchronization was going on. Removing the two offending lines of + code gave a massive speed boost for free. Enjoy. + +v0.7 - (beta than ever) + +# Fixed a dynarec bug involving flags generating functions in + contiguous conditional blocks. Fixes music in Super Mario + Advance 2-4. +# Fixed a dynarec bug where Thumb mov imm instructions wouldn't + set flags. Fixes Zelda: Minish Cap, Megaman Battle Network, + probably others. Comes at a slight speed cost. +# Fixed a MIPS dynarec bug where some delay slots might not + get filled rarely, causing chaos. Don't know if it improves + any games. +# Improved self-modifying code detection. Makes Golden Sun, + Golden Sun 2, and Madden 2007 sorta work but excrutiatingly + slowly. Looking for a game-specific workaround for this - if you + want to play these games you'll have to wait for now :( +# Fixed a bug causing the interrupt disable flag to go down + when SWIs are entered, causing crashes/resets. Fixes + Super Mario Advance 2-4. +# Fixed menu crashing when strings with certain characters are + printed (for instance going to the menu after loading the + BIOS) +# Accidentally forgot to render win0 + win1 + objwin when all + active at the same time, many weeks ago. Added that, should fix + some parts in games that had frozen screens. +# Fixed some issues with gpsp.cfg needing to be present and + corrupting, hopefully. At the very least sanity checks are + performed on the config file. +# Made it so assigning the frameskip button to something besides + triangle actually worked as expected. +# Fixed ability to restart current game if nothing is loaded + (ie, crash) +# Added interrupt on cpsr modification support to the dynarec + (fixes backgrounds in Castlevania: Harmony of Dissonance) +# Added open addressing for ldm/stm instructions (fixes + Super Mario Advance 3) +# Improved cycle accuracy a little. Don't know of anything this + fixes, but games with idle loops will run a little better w/o + idle loop elimination (but should still be added when possible) +# Fixed some bugs causing sound to play sometimes when it shouldn't. +@ Added dead flag elimination for Thumb code. May possibly have + noticeable performance increases (Thumb emited coded size can + have a reduction of 20% or more) +@ Added code generation for divide SWI. May have a small speed + increase in some games. ++ Added analog nub support (special thanks to psp298 for the + code) ++ Added fractional frameskip. Go below 0 to get them. A frameskip + of 1/2 for instance means render 2 out of every 3 frames, 2/3 + means render 3 out of every 4 frames, etc. Possibly useful for + games that are not quite fast enough at fs0 but fullspeed at + fs1... + +v0.6 - (still beta quality, look out for new bugs) + +NOTE: Please include gpsp.cfg with EBOOT.PBP, this shouldn't be + necessary but I think it is right now. + +# Fixed a nasty bug that shouldn't have made it into the initial + release; a lot of games that TECM.. erm.. crash won't anymore. + NOTE: This doesn't mean that no game will ever crash, freeze, + otherwise not work. +# Fixed some crashes in the GUI and the ability to "go up" past + ms0:/PSP. Made the "go up" button square like it was supposed to + be (instead of cross). ++ There's now a menu that you can access, by default press right + while holding down triangle for the frameskip bar. ++ Menu option: resize screen aspect ratio, the default is now + "scaled 3:2" which makes it look more like a normal GBA. You + can use "fullscreen" (what it was like before) or "unscaled 3:2" + (tiny but pixel for pixel like a GBA) ++ Menu option: You can now load new games while the current one + is running. ++ Menu option: You can now restart the currently running game. ++ Menu option: Frameskip variation - this defaults to "uniform" + whereas it defaulted to "random" last release. Basically, turn + it on random if you find that frameskip causes flickering + animations to make things disappear. Other than that it will + generally look better on uniform. ++ GUI and file loading now have "auto repeat" on the buttons so + they're not such a pain to navigate. ++ Menu option: Added support for 128KB flash ROM, some games + require it (Pokemon Firered/Leaf Green, Super Mario Advance 4), + turn it on before running the game to make sure it works. + NOTE: There are some versions of these ROMs that have been + hacked to get around their 128KB flash, and may not even work + properly at all. Look out for them, these games should save + 128KB save files after you set the setting to it, IF they use + 128KB flash. ++ Menu option: Added ability to make the .sav files only update + when you exit the emulator, use with extreme caution (in other + words, it's not a good idea to use something like this in beta + quality software if you care about your saves). Does NOT update + if you exit through the home button, don't use the home button + if you can help it. ++ Zip support thanks to SiberianSTAR. It will load the first file + with the extension .gba or .bin that it finds. ++ Menu options are saved to gpsp.cfg. Note that it does not save + frameskip options or flash ROM options because these are very + per game particular. ++ The emulator will now try to save backup files to something + more matching the backup size than a fixed 64KB. +@ Loading ROMs and the auto save of the .sav files is MUCH faster + now. Thanks for the heads up on how to improve this from pollux! +@ While coding for the screen resize code I found that SDL just + wasn't cutting it and had to code for the GU myself. Turns out + the new code is faster (but because it is render code any + improvement will be diminished to nothing as frameskip is + increased). Special thanks to Zx-81 for the tips on this one + and for his GU code in the PSPVBA source as an example. +@ Added some games to game_config.txt. Note that not all versions + of these ROMs will work with these options, try to use the USA + version if possible. + +8-19-2006 v0.5 - Initial release (public beta quality) + + +-- About -- + +gameplaySP (gpSP for short) is a GBA emulator written completely from +scratch. It is still pretty young (only having started a 3 months prior +to the first release) and thus rather immature, but it does a decent +job of playing a number of games, and is being improved upon somewhat +regularly. It is currently somewhat minimalistic, in the sourcecode, +presentation, and features. Its number one focus is to deliver a GBA +gaming experience in the most playable way that PSP can manage, with +frills being secondary (although still a consideration, at least for +some of them). + +Having said that, optimization was the important way in achieving this +goal, with overall compatability being a near second. Because of this +some games may not run at the favor of running more games significantly +better. Of course, the compatability will improve with time. The +compatability in the current version (0.8) is perhaps around 80% +(assuming the correct BIOS image is used). + +Many games will run at their best out of the box, but some games will +run very slowly unless idle loops are taken care of. There is a supplied +ROM database, game_config.txt, that gives idle loop targets and other +settings that may help a game to run better (or at all) on a per-game +basis. Currently (as of version 0.8) a few dozen games are on this list, +mostly only USA versions. This list will continue to be updated; there's +no real telling exactly how many of the ~2500 GBA games will need to +appear here. + +gpSP currently requires an authentic GBA BIOS image file to run. It will +make no effort to run without one present; this file is 16kb and should +be called gba_bios.bin and present in the same location as the EBOOT.PBP +file. Please do not ask me where to obtain this, you'll have to look +online or grab it from a GBA. Note that it is not legal to have this file +unless you own a GBA, and even then it's rather gray area. + + + +-- Features -- + +gpSP mostly emulates the core Gameboy Advance system. As of right now it +does not emulate any special hardware present on various GBA cartridges. + + +What it emulates: + +GBA CPU: All ARM7TDMI ARM and Thumb mode opcodes except block memory w/ + s-bit (probably aren't used in GBA games) +Video: Modes 0, 1, 2 almost completely, basic 3-5 support, sprites, + windows/OBJ windows +Interrupts: HBlank, VBlank, all timers, all DMA channels, keypad +DMA: Immediate, HBlank, VBlank, sound timer triggered +Sound: Both DirectSound channels and all 4 GBC audio channels +Input: Basic GBA input delivered through PSP controls +Cartridges: Currently supports ROMs up to 32MB in size (the maximum for +GBA) with the technique of ROM page swapping to fit within PSP's RAM. +Backup: 32/64kb SRAM, 64/128kb flash, 512bit/8kb EEPROM +RTC: The real-time clock present in cartridges such as most of the + Pokemon games and some others. + + +What it lacks: + +Video: No mosaic, bitmap modes lack color effects (alpha, fades), + there might be some minor inaccuracies in blending... +Cycle accuracy: Very cycle innacurate; CPU is effectively somewhat + overclocked, meaning games with rampant idle loops will probably run + rather poorly. DMA transfers effectively happen for free (0 cycle). + Please do NOT use gpSP as a first source for developing GBA homebrew, + try No$GBA instead. + + +Additional features it has: +- The ability to attempt to run games at faster than GBA speed (sometimes + they can end up a lot faster, other times not so much) +- Savestates: the ability to save a game's state to a file and resume + playing where you left off later. +- Mild cheat support + + +Features that it doesn't have (please don't ask me to implement these!) +- Wi-fi multiplayer + + +-- Controls -- + +The default control scheme is very simple. If you don't like it you can +change it in the configuration menu. + +At the ROM selection screen: + +Up/down: navigate current selection window. +Left/right: switch between file window and directory window. +Circle/start: select current entry. +Square: go one directory up. + +In game: + +Up/down/left/right: GBA d-pad +Circle: GBA A button +Cross: GBA B button +Square/start: GBA start button +Select: GBA select button +Left trigger: GBA left trigger +Right trigger: GBA right trigger +Triangle: Adjust frameksip + +In frameskip adjustment: + +Hold down triangle to keep up, press up/down to increase/decrease +frameskip, respectively. Press down at 0 to change to auto, and up +at auto to change to 0. + +In the menu: + +Up/down: navigate current menu. +Left/right: change value in current menu selection (if a value is present) +Circle/start: select current entry (see help for entry to see what this means) +Square: exit the current menu. + + +-- Frameskip -- + +The purpose behind frameskip is to cause the emulator to not render every +frame of graphics to make the emulation closer to fullspeed. Many games will +run fullspeed without skipping any frames, however, some (particularly more +graphically demanding ones) will require this. + +Frameskip can be set to two forms, either auto or manual. Auto will attempt +to skip only as many frames as necessary to make the game full speed, and +will not skip more than 4 in a row no matter what speed the game runs at +(at this point the benefits of frameskip yield diminishing returns). + +It is recommended that you keep frameskip on auto, but manual is maintained +as an option if you want it and works as follows: + +Manual frameskip will only render one out of every (n + 1) frames, where n +is the current frameskip value (so 0 will render everything). Increasing +the frameskip can improve speed, especially with very graphically +intensive games. + + +-- Cheats -- + +Currently, gpSP supports some functionality of Gameshark/Pro Action Replay +cheat codes. To use these, you must first make a file with the same name +as the ROM you want the cheat code to apply to, but with the extension .cht. +Put this file in the same directory as the ROM. To make it use a normal +text editor like notepad or wordpad if you're on Windows. + +To write a code, write the type of model it is, gameshark_v1, gameshark_v3, +PAR_v1, or PAR_v3. gameshark_v1/PAR_v1 and gameshark_v3/PAR_v3 respectively +are interchangeable, but v1 and v3 are not! So if you don't know which +version it is, try both to see if it'll work. + +Then, after that, put a space and put the name you'd like to give the cheat. + +On the next several lines, put each cheat code pair, which should look like +this: + +AAAAAAAA BBBBBBBB + +Then put a blank line when you're done with that code, and start a new code +immediately after it. Here's an example of what a cheat file should look +like: + + +gameshark_v3 MarioInfHP +995fa0d9 0c6720d2 + +gameshark_v3 MarioMaxHP +21d58888 c5d0e432 + +gameshark_v3 InfHlthBat +6f4feadb 0581b00e +79af5dc6 5ce0d2b1 +dbbd5995 44b801c9 +65f8924d 2fbcd3c4 + +gameshark_v3 StopTimer +2b399ca4 ec81f071 + + +After you have written the .cht file, you have to enable the cheats +individually in the game menu. Go to the Cheats/Misc menu, and you will +see the cheats; turn them on here. You may turn them on and off as you +please, but note that some cheats may still hold after you turn them off, +due to the nature of the system. Restart to completely get rid of them. + +IMPORTANT NOTES: + +This is still very work in progress! I basically added this in only 1.5 +or so hours, and I don't have a lot of time right now to work on it +before releasing. So I'll probably improve it later. + +Not all of gameshark's features are supported, especially for v3. Only +basic cheats will work, more or less. + +Cheats may be unstable and may crash your game. If you're having problems +turn the cheats off. + +Really, there's no guarantee that ANY cheats will work; I tried a few and +some seem to work, others are questionable. Try for yourself, but don't +expect anything to actually work right now. Do expect this feature to +improve in future versions. + + + +-- Frequently Asked Questions -- + +Q) How do I run this on my PSP? + +A) Provided is an EBOOT.PBP which will run as is on a 1.0 firmware + PSP or custom firmware that can run unsigned EBOOTs. On 1.5 firmwares + you must use a kxploit tool to run it (try SeiPSPtool). On 2.0 + firmwares and higher further exploits must be used - see + http://pspupdates.qj.net/ for more information. Note that I have NOT + tested this emulator on any firmware version besides 1.5, and it's + very possible that it doesn't run well, or at all on higher versions. + Therefore I strongly recommend you downgrade if possible, and use + Devhook to run games that require > 1.5 version firmwares. + + Be sure to include in the same directory as the EBOOT.PBP file the + game_config.txt file included and the gba_bios.bin file which you + must provide yourself. + + gpSP does not run on PSPs with version 2.71 or higher firmware yet, + nor does any other homebrew executable. + + +Q) What is a BIOS image file? Why do I need it to run gpSP? Other GBA + emulators don't require this... + +A) The GBA BIOS image file is a copy of a ROM on the GBA system that + has code for starting up the GBA (it shows the logo), verifying the + game, and most importantly, providing utility functions for the games + to use. It is the latter that gpSP needs the BIOS present for. It's + possible to replace all of these functions with equivilent code, but + this will take time - in the future gpSP may not require a BIOS image. + + +Q) I can't find this BIOS image.. please send it to me. + +A) Sorry, but you're on your own. I won't send you a BIOS or tell you + where to get one (unless you want to rip it from a GBA yourself, in + which case I'll just give you the same link at the top). I can't do + this because it's not legal to send it around and I don't want to + get a reputation for illegally distributing BIOS images. + + +Q) How do I know I have the right BIOS? + +A) If you have md5sum you can check if it has this hash: + a860e8c0b6d573d191e4ec7db1b1e4f6 + That BIOS should work fine. I think that some others work fine too, + although I haven't confirmed this with absolute certainty. It's also + theoretically possible to use custom (and free) BIOS replacements, + but I don't know of any publically availablone ones. + + As far as I'm aware there are two BIOSes floating around, I doubt + you'll get one that isn't one of those two. There's a very easy way + to determine which one you have - just look at the very first byte in + a hex editor. The correct BIOS begins with 0x18, the buggy BIOS begins + with 0x14. + + +Q) My favorite game won't run. + +A) There probably isn't anything you can do about this, although a + change to game_config.txt might help. gpSP is still an emulator in + its infancy so the compatability is not superb. I don't have time + to test too many games so I'm releasing it as a public beta to get + a feel for some things that don't work. The next version could + perhaps fix it, or it might never run. There are always other + emulators of course, please try one. + + However, before nagging me there is one thing I recommend you try, + and that is to add the option "iwram_stack_optimize = no" for the + game in game_config.txt. See the file itself for more information + on how to do this. If this fixes your game (and it's not already + in the game_config.txt) please tell me about it. + + +Q) My favorite game is very slow. + +A) Emulating GBA takes a number of resources and getting it done well + on PSP is no simple task by any means. Some games are just going to + overwhelm the emulator completely. Of course, there is one special + case of game (a lot of early generation games fall under this + category) that can be made much faster by a simple addition to the + game_config.txt file. Wait for a new version of this file or the + next version of the emulator and the game may be improved. + + That aside, there are still numerous optimizations that can be done, + and I sure you future versions will be faster (I just can't tell you + how much) + + Also, a lot of games will be sped up considerably by adding an + idle_loop_eliminate_target line for it in game_config.txt. There + are some more obscurer options there that can improve speed too. If + the game is VERY slow there might be something wrong with its + emulation that can be improved. For instance, if you can't get a game + to run fullspeed on any frameskip you should e-mail me about it. + + +Q) Some games run fullspeed but the sound is messed up. Why? + +A) At least 9 out of 10 times it means the game isn't really running + full speed, but just that you can't notice the difference. Increasing + frameskip will almost always improve sound quality in these + situations, to a certain point (after around frameskip 3 you + probably won't be seeing many more returns if it isn't already + fullspeed). The rest of the time it means there's a bug somewhere else + in the emulator, probably in the CPU core. Chances are that all you + can do is wait for it to be fixed in a later release. + + +Q) The emulator crashed! + +A) Most games that don't run will probably take the emulator down with + it, or it could be an emulator bug completely unrelated to the game + (but unlikely). Press home and wait for the next version. + + There is some information that comes up when the game crashes. This + information may be slightly useful to me, but chances are it + usually won't be all that interesting. + + These days games are more likely to exit with a "bad crash" error. + This number is possibly useful to me, but to debug a game I'll have + to reproduce the crash anyway. When this happens it's probably due to + a bug in the CPU core that hasn't been fixed yet. + + +Q) Why won't my game save? + +A) The game might need 128KB flash turned on and might not be listed in + game_config.txt. See game_config.txt for more information regarding + this. Be sure to include game_config.txt with the EBOOT.PBP file. + + Other games might simply have bugs in the save support. For now, use + savestates as an alternative if you can't save. + + +Q) How do I change sound quality? + +A) Right now, you can't. For those wondering, sound is locked at 44.1KHz + (sounds a bit high? It is, but it's currently necessary to play + everything correctly). I don't have any plans to allow changing this + right now, because I don't think there's really much reason to be + able to (it'd be a tiny speed boost at best and I don't think SDL even + allows for anything besides this sampling rate on PSP) + + +Q) What is this emulator's name? + +A) Um.. what? It's gameplaySP, isn't it? You call it gpSP for short. + Somehow the name can't have the acronyms gbSP, gbapSP, or really + just about anything else you feel like giving it. Oh, and if you + really want to make me happy get the capitalization right too. + That's gpSP, not gPSP, GPsp.. you get the idea. + + +Q) Does gpSP run Gameboy/Gameboy Color games? Will it later? + +A) No. Even though GBA can run these games it uses separate hardware + that proper GBA games have no access to (save for the audio chip), + and thus there's no point including it in a GBA emulator (it + doesn't help run GBA games). I recommend using a GB/GBC emulator + like Rin for playing these games. It'll probably give you a lot + more options anyway. gpSP will never actually emulate GB/GBC + games. You'd may as well be waiting for it to emulate PS2 games... + (that was an analogy. gpSP won't ever emulate PS2 games. >_>) + + +Q) Other emulators use the PSP's graphical hardware to accelerate the + video emulation. Is this possible for gpSP? + +A) I'm honestly not too sure at this point. It's definitely a rather + complicated procedure, and I don't think it'll be possible to + accurately accelerate alpha blending. On the other hand, affine + transformations could perhaps receive a speed boost this way. Any + solution would have to be hybrid hardware/software, which might be + possible due to the nature of the PSP's VRAM. Maybe someone will + be willing to help me think of possibilities here? + + But don't bother of you're just going to tell me to render a list + of quads... + + +Q) Other emulators use the PSP's second CPU to offload the sound + emulation. Is this possible for gpSP? + +A) Yes, but it wouldn't improve it nearly as much as say, SNES9x TYL. + This is because most of the processing that goes into sound on a GBA + game is done in the CPU, not in dedicated audio hardware. It could + help a little, but probably not a lot. Maybe enough to be worthwhile. + It might also be possible to split the video rendering to the main + CPU and the main emulation to the secondary one, but there are a lot + of coherency issues involved. + + +Q) I heard gpSP can only load games 16MB or smaller in size. Is this + true? What about zipped games? + +A) As of version 0.8 gpSP can play 32MB ROMs. However, they must be + unzipped. The reason for this is that parts of the ROM are constantly + loaded to memory as needed, and for this to be as fast as possible the + ROM has to be present on the memory stick in raw format. + + You might be wondering, why not just have gpSP unzip the ROM to a file + then delete the file when it is done? The reason why is because this + would impose a "hidden" requirement of 32MB on the user that very + likely may not be there. Furthermore, there are only a few 32MB games + that anyone actually wants to play. If you only have one 32MB game on + your memstick then it'd actually require signifnicantly more free space + to hold both the ROM and the 32MB raw file. With 2 32MB ROMs you only + gain a around 10-25MB of free space, depending on how effective the + compression is. + + +Q) Savestates? From other emulators?? + +A) See the savestates option in main menu. gpSP will probably never + support savestates from other emulators, there's just too much in the + way of emulator specific data in them. + + Savestates are currently 506,943 bytes. They would be a little smaller + without the snapshot, but I find that very useful and it wouldn't help + size immensely. Compression would help, but I wanted the size to be + constant so you knew exactly how much you could hold and to improve + save/load speed. + + +Q) What's with the zip support? + +A) I hear stories that some games work unzipped and not zipped, so you + might want to try unzipping them if it gives you problems. You also + might want to try making fresh zips with WinRAR - users have + reported some higher success rates doing this. + + +Q) What's with the config file? Should I make it read only? + +A) There was a bug in version 0.6 that caused the config file to not + get updated or get corrupted sometimes. Hopefully this is fixed now, + but if it DOES get corrupted making it read only can prevent this + from happening in the future. + + +Q) So when WILL the next version be released? + +A) Sorry, but I almost never announce release dates. Furthermore, I'll + probably be pretty hush hush on internal development, just to keep + people from nagging me about it and building too much suspense. + + +Q) I don't like this emulator. Are there other alternatives? + +A) Yes. Try PSPVBA by Zx-81 (http://zx81.dcemu.co.uk/). Overall I doubt + the compatability is significantly higher than gpSP's anymore, but + I'm sure there are some games it runs that gpSP doesn't. + + +Q) I heard there was a version of gpSP for PCs. Is that true? + +A) I developed this emulator internally on PC. It might have a speed + advantage over other PC GBA emulators, although the PSP version has + more sophisticated optimizations. Most people have fast enough + computers to run better GBA emulators for PC and gpSP lacks some + important features (screen resizing) that the PSP version kinda + hides. Even though gpSP spent a majority of its development + gestation as a PC app it was always developed with the PSP in mind, + so the PC version will probably not see the light of the day unless + I get overwhelming demand for it. It is, however, possible to + build it from the source. But I request that you don't distribute + such builds. If you happen to find one, bear in mind that I don't + offer any support for it, and as far as I'm concerned it won't + exist. + + +Q) I hear there's a version of gpSP for other platforms too, like + Dreamcast. And I hear they're slow! What gives? + + These are ports, done by other people (or maybe myself?). This is + possible because gpSP is open source and its base version is fairly + portable, but to run fast enough on anything but platforms quite a + bit faster than PSP it at least needs a CPU specific dynarec backend. + + I don't (necessarily) maintain all builds of gpSP, so you'll have to + contact the authors of these ports for more information. That + notwithstanding, I try to get as involved in other ports of gpSP as + I can. + + +Q) I want to modify gpSP. How can I do this, and am I at liberty to do + so? + +A) Yes, you are, under the terms of the GPL (see the included + COPYING.DOC). You can download the sourcecode from whereever you + downloaded this; if you can't find it please e-mail me and I'll give + you a link to it. I would vastly appreciate it if you contacted me first + before forking my project, especially if you're just looking to gain + recognition without adding much to it. It's better to keep all changes + tidy in one branch of development. + + I would like to stress this a little more seriously (hopefully those + interested are reading this). Although you are legally entitled to + release your own forks of gpSP it would be much more benficial to me, + to you, and to the users of this program if you instead tried working + with me to get your changes incorporated into the next version. I + really don't feel like competing with other builds of my source + anymore, so please do me a big favor and send me an e-mail if you want + to work with gpSP. + + +Q) How do I build gpSP? + +A) make will build it. You need to have SDL for PSP installed, as well + as the standard PSP toolchain/PSPSDK and zlib. gpSP isn't much of a + "build it yourself" program so please don't bother me much about how to + build it unless you have a good reason for wanting to do so. + + +Q) What is with the version numbers? + +A) Anything less than 1.0 means beta. Beta means that I still have major + plans for working on it, and that I don't fully back it as being + stable or reliable software. Of course, if it does hit 1.0, that doesn't + mean it'll be perfect. It just means I'll have spent a lot of cumulative + time working things out. The closer it gets to 0.9, the happier I am with + it overall. + + +Q) Donations? + +A) Very appreciated. exophase@gmail.com on PayPal. <3 + + +Q) How can I contact you? + +A) exophase@gmail.com, Exophase on AIM, exophase@adelphia.net on MSN. I + welcome IMs, but if you nag me a lot you'll make me sad inside. And + don't ask me for ROMs or the GBA BIOS. I figured this was common sense + but apparently not. + + +-- Credits -- + +Exophase: main developer +siberianSTAR: zip support +psp298: analog nub code + +Beta testers for 0.7: +theohsoawesome1 +thisnamesucks837 +blackdragonwave9 +dagreatpeewee +xsgenji + +Beta testers for 0.8: +Runaway_prisoner +theohsoawesome1 +tanyareimyoko +spynghotoh2020 + +Beta testers for 0.9: +RunawayPrisoner (my right hand man) +Veskgar (my left hand man) +qasim + +-- Special thanks -- + +Quasar84: He's helped me in so many ways with this. We both kinda learned +GBA together, he did little demos for me and I got them emulated. It was +great trying out your more advanced code for your own projects once you +got to them, it was equally rewarding to see your work and to be able to +run it at the same time. Least of all I wouldn't have been able to do any +of this without your constant support and presence. I really owe this +release to you. + +gladius: You are an amazing GBA coder. I wouldn't have been able to get +through some tough parts without your help. Its been good talking about +ideas with you.. I'm sure you're glad to see that there's finally a GBA +emulator with dynarec ;) + + +Many, many others of course, probably too many to name, and I don't want +to make anyone feel bad by putting others above them (well, except those +two, heh) so if you think you should be on here, you probably should be! +Just pretend you are for now, and maybe I'll put you here next time. + diff --git a/sound.c b/sound.c new file mode 100644 index 0000000..55985fc --- /dev/null +++ b/sound.c @@ -0,0 +1,812 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include "common.h" +#include +u32 global_enable_audio = 1; + +direct_sound_struct direct_sound_channel[2]; +gbc_sound_struct gbc_sound_channel[4]; + +#if defined(GP2X_BUILD) || defined(TAVI_BUILD) +u32 sound_frequency = 44100; +#else +u32 sound_frequency = 44100; +#endif + +SDL_AudioSpec sound_settings; +SDL_mutex *sound_mutex; +SDL_cond *sound_cv; + +#ifndef PSP_BUILD +u32 audio_buffer_size_number = 7; +#else +u32 audio_buffer_size_number = 1; +#endif + +u32 audio_buffer_size; +u32 sound_on = 0; +s16 sound_buffer[BUFFER_SIZE]; +u32 sound_buffer_base = 0; + +u32 sound_last_cpu_ticks = 0; +fixed16_16 gbc_sound_tick_step; + +// Queue 1, 2, or 4 samples to the top of the DS FIFO, wrap around circularly + +#define sound_timer_queue(size, value) \ + *((s##size *)(ds->fifo + ds->fifo_top)) = value; \ + ds->fifo_top = (ds->fifo_top + 1) % 32; \ + +void sound_timer_queue8(u32 channel, u8 value) +{ + direct_sound_struct *ds = direct_sound_channel + channel; + sound_timer_queue(8, value); +} + +void sound_timer_queue16(u32 channel, u16 value) +{ + direct_sound_struct *ds = direct_sound_channel + channel; + sound_timer_queue(8, value & 0xFF); + sound_timer_queue(8, value >> 8); +} + +void sound_timer_queue32(u32 channel, u32 value) +{ + direct_sound_struct *ds = direct_sound_channel + channel; + + sound_timer_queue(8, value & 0xFF); + sound_timer_queue(8, (value >> 8) & 0xFF); + sound_timer_queue(8, (value >> 16) & 0xFF); + sound_timer_queue(8, value >> 24); +} + +// Unqueue 1 sample from the base of the DS FIFO and place it on the audio +// buffer for as many samples as necessary. If the DS FIFO is 16 bytes or +// smaller and if DMA is enabled for the sound channel initiate a DMA transfer +// to the DS FIFO. + +#define render_sample_null() \ + +#define render_sample_left() \ + sound_buffer[buffer_index] += current_sample + \ + fp16_16_to_u32((next_sample - current_sample) * fifo_fractional) \ + +#define render_sample_right() \ + sound_buffer[buffer_index + 1] += current_sample + \ + fp16_16_to_u32((next_sample - current_sample) * fifo_fractional) \ + +#define render_sample_both() \ + dest_sample = current_sample + \ + fp16_16_to_u32((next_sample - current_sample) * fifo_fractional); \ + sound_buffer[buffer_index] += dest_sample; \ + sound_buffer[buffer_index + 1] += dest_sample \ + +#define render_samples(type) \ + while(fifo_fractional <= 0xFFFF) \ + { \ + render_sample_##type(); \ + fifo_fractional += frequency_step; \ + buffer_index = (buffer_index + 2) % BUFFER_SIZE; \ + } \ + +void sound_timer(fixed16_16 frequency_step, u32 channel) +{ + direct_sound_struct *ds = direct_sound_channel + channel; + + fixed16_16 fifo_fractional = ds->fifo_fractional; + u32 buffer_index = ds->buffer_index; + s16 current_sample, next_sample, dest_sample; + + current_sample = ds->fifo[ds->fifo_base] << 4; + ds->fifo_base = (ds->fifo_base + 1) % 32; + next_sample = ds->fifo[ds->fifo_base] << 4; + + if(sound_on == 1) + { + if(ds->volume == DIRECT_SOUND_VOLUME_50) + { + current_sample >>= 1; + next_sample >>= 1; + } + + switch(ds->status) + { + case DIRECT_SOUND_INACTIVE: + render_samples(null); + break; + + case DIRECT_SOUND_RIGHT: + render_samples(right); + break; + + case DIRECT_SOUND_LEFT: + render_samples(left); + break; + + case DIRECT_SOUND_LEFTRIGHT: + render_samples(both); + break; + } + } + else + { + render_samples(null); + } + + ds->buffer_index = buffer_index; + ds->fifo_fractional = fp16_16_fractional_part(fifo_fractional); + + if(((ds->fifo_top - ds->fifo_base) % 32) <= 16) + { + if(dma[1].direct_sound_channel == channel) + dma_transfer(dma + 1); + + if(dma[2].direct_sound_channel == channel) + dma_transfer(dma + 2); + } +} + +void sound_reset_fifo(u32 channel) +{ + direct_sound_struct *ds = direct_sound_channel; + + memset(ds->fifo, 0, 32); +} + +// Initial pattern data = 4bits (signed) +// Channel volume = 12bits +// Envelope volume = 14bits +// Master volume = 2bits + +// Recalculate left and right volume as volume changes. +// To calculate the current sample, use (sample * volume) >> 16 + +// Square waves range from -8 (low) to 7 (high) + +s8 square_pattern_duty[4][8] = +{ + { 0xF8, 0xF8, 0xF8, 0xF8, 0x07, 0xF8, 0xF8, 0xF8 }, + { 0xF8, 0xF8, 0xF8, 0xF8, 0x07, 0x07, 0xF8, 0xF8 }, + { 0xF8, 0xF8, 0x07, 0x07, 0x07, 0x07, 0xF8, 0xF8 }, + { 0x07, 0x07, 0x07, 0x07, 0xF8, 0xF8, 0x07, 0x07 }, +}; + +s8 wave_samples[64]; + +u32 noise_table15[1024]; +u32 noise_table7[4]; + +u32 gbc_sound_master_volume_table[4] = { 1, 2, 4, 0 }; + +u32 gbc_sound_channel_volume_table[8] = +{ + fixed_div(0, 7, 12), + fixed_div(1, 7, 12), + fixed_div(2, 7, 12), + fixed_div(3, 7, 12), + fixed_div(4, 7, 12), + fixed_div(5, 7, 12), + fixed_div(6, 7, 12), + fixed_div(7, 7, 12) +}; + +u32 gbc_sound_envelope_volume_table[16] = +{ + fixed_div(0, 15, 14), + fixed_div(1, 15, 14), + fixed_div(2, 15, 14), + fixed_div(3, 15, 14), + fixed_div(4, 15, 14), + fixed_div(5, 15, 14), + fixed_div(6, 15, 14), + fixed_div(7, 15, 14), + fixed_div(8, 15, 14), + fixed_div(9, 15, 14), + fixed_div(10, 15, 14), + fixed_div(11, 15, 14), + fixed_div(12, 15, 14), + fixed_div(13, 15, 14), + fixed_div(14, 15, 14), + fixed_div(15, 15, 14) +}; + +u32 gbc_sound_buffer_index = 0; +u32 gbc_sound_last_cpu_ticks = 0; +u32 gbc_sound_partial_ticks = 0; + +u32 gbc_sound_master_volume_left; +u32 gbc_sound_master_volume_right; +u32 gbc_sound_master_volume; + +#define update_volume_channel_envelope(channel) \ + volume_##channel = gbc_sound_envelope_volume_table[envelope_volume] * \ + gbc_sound_channel_volume_table[gbc_sound_master_volume_##channel] * \ + gbc_sound_master_volume_table[gbc_sound_master_volume] \ + +#define update_volume_channel_noenvelope(channel) \ + volume_##channel = gs->wave_volume * \ + gbc_sound_channel_volume_table[gbc_sound_master_volume_##channel] * \ + gbc_sound_master_volume_table[gbc_sound_master_volume] \ + +#define update_volume(type) \ + update_volume_channel_##type(left); \ + update_volume_channel_##type(right) \ + +#define update_tone_sweep() \ + if(gs->sweep_status) \ + { \ + u32 sweep_ticks = gs->sweep_ticks - 1; \ + \ + if(sweep_ticks == 0) \ + { \ + u32 rate = gs->rate; \ + \ + if(gs->sweep_direction) \ + rate = rate - (rate >> gs->sweep_shift); \ + else \ + rate = rate + (rate >> gs->sweep_shift); \ + \ + if(rate > 2048) \ + rate = 2048; \ + \ + frequency_step = float_to_fp16_16(((131072.0 / (2048 - rate)) * 8.0) / \ + sound_frequency); \ + \ + gs->frequency_step = frequency_step; \ + gs->rate = rate; \ + \ + sweep_ticks = gs->sweep_initial_ticks; \ + } \ + gs->sweep_ticks = sweep_ticks; \ + } \ + +#define update_tone_nosweep() \ + +#define update_tone_envelope() \ + if(gs->envelope_status) \ + { \ + u32 envelope_ticks = gs->envelope_ticks - 1; \ + envelope_volume = gs->envelope_volume; \ + \ + if(envelope_ticks == 0) \ + { \ + if(gs->envelope_direction) \ + { \ + if(envelope_volume != 15) \ + envelope_volume = gs->envelope_volume + 1; \ + } \ + else \ + { \ + if(envelope_volume != 0) \ + envelope_volume = gs->envelope_volume - 1; \ + } \ + \ + update_volume(envelope); \ + \ + gs->envelope_volume = envelope_volume; \ + gs->envelope_ticks = gs->envelope_initial_ticks; \ + } \ + else \ + { \ + gs->envelope_ticks = envelope_ticks; \ + } \ + } \ + +#define update_tone_noenvelope() \ + +#define gbc_sound_synchronize() \ + while(((gbc_sound_buffer_index - sound_buffer_base) % BUFFER_SIZE) > \ + (audio_buffer_size * 2)) \ + { \ + SDL_CondWait(sound_cv, sound_mutex); \ + } \ + +#define update_tone_counters(envelope_op, sweep_op) \ + tick_counter += gbc_sound_tick_step; \ + if(tick_counter > 0xFFFF) \ + { \ + if(gs->length_status) \ + { \ + u32 length_ticks = gs->length_ticks - 1; \ + gs->length_ticks = length_ticks; \ + \ + if(length_ticks == 0) \ + { \ + gs->active_flag = 0; \ + break; \ + } \ + } \ + \ + update_tone_##envelope_op(); \ + update_tone_##sweep_op(); \ + \ + tick_counter &= 0xFFFF; \ + } \ + +#define gbc_sound_render_sample_right() \ + sound_buffer[buffer_index + 1] += (current_sample * volume_right) >> 22 \ + +#define gbc_sound_render_sample_left() \ + sound_buffer[buffer_index] += (current_sample * volume_left) >> 22 \ + +#define gbc_sound_render_sample_both() \ + gbc_sound_render_sample_right(); \ + gbc_sound_render_sample_left() \ + +#define gbc_sound_render_samples(type, sample_length, envelope_op, sweep_op) \ + for(i = 0; i < buffer_ticks; i++) \ + { \ + current_sample = \ + sample_data[fp16_16_to_u32(sample_index) % sample_length]; \ + gbc_sound_render_sample_##type(); \ + \ + sample_index += frequency_step; \ + buffer_index = (buffer_index + 2) % BUFFER_SIZE; \ + \ + update_tone_counters(envelope_op, sweep_op); \ + } \ + +#define gbc_noise_wrap_full 32767 + +#define gbc_noise_wrap_half 126 + +#define get_noise_sample_full() \ + current_sample = \ + ((s32)(noise_table15[fp16_16_to_u32(sample_index) >> 5] << \ + (fp16_16_to_u32(sample_index) & 0x1F)) >> 31) & 0x0F \ + +#define get_noise_sample_half() \ + current_sample = \ + ((s32)(noise_table7[fp16_16_to_u32(sample_index) >> 5] << \ + (fp16_16_to_u32(sample_index) & 0x1F)) >> 31) & 0x0F \ + +#define gbc_sound_render_noise(type, noise_type, envelope_op, sweep_op) \ + for(i = 0; i < buffer_ticks; i++) \ + { \ + get_noise_sample_##noise_type(); \ + gbc_sound_render_sample_##type(); \ + \ + sample_index += frequency_step; \ + \ + if(sample_index >= u32_to_fp16_16(gbc_noise_wrap_##noise_type)) \ + sample_index -= u32_to_fp16_16(gbc_noise_wrap_##noise_type); \ + \ + buffer_index = (buffer_index + 2) % BUFFER_SIZE; \ + update_tone_counters(envelope_op, sweep_op); \ + } \ + +#define gbc_sound_render_channel(type, sample_length, envelope_op, sweep_op) \ + buffer_index = gbc_sound_buffer_index; \ + sample_index = gs->sample_index; \ + frequency_step = gs->frequency_step; \ + tick_counter = gs->tick_counter; \ + \ + update_volume(envelope_op); \ + \ + switch(gs->status) \ + { \ + case GBC_SOUND_INACTIVE: \ + break; \ + \ + case GBC_SOUND_LEFT: \ + gbc_sound_render_##type(left, sample_length, envelope_op, sweep_op); \ + break; \ + \ + case GBC_SOUND_RIGHT: \ + gbc_sound_render_##type(right, sample_length, envelope_op, sweep_op); \ + break; \ + \ + case GBC_SOUND_LEFTRIGHT: \ + gbc_sound_render_##type(both, sample_length, envelope_op, sweep_op); \ + break; \ + } \ + \ + gs->sample_index = sample_index; \ + gs->tick_counter = tick_counter; \ + +#define gbc_sound_load_wave_ram(bank) \ + wave_bank = wave_samples + (bank * 32); \ + for(i = 0, i2 = 0; i < 16; i++, i2 += 2) \ + { \ + current_sample = wave_ram[i]; \ + wave_bank[i2] = (((current_sample >> 4) & 0x0F) - 8); \ + wave_bank[i2 + 1] = ((current_sample & 0x0F) - 8); \ + } \ + +void synchronize_sound() +{ + SDL_LockMutex(sound_mutex); + + gbc_sound_synchronize(); + + SDL_UnlockMutex(sound_mutex); +} + +void update_gbc_sound(u32 cpu_ticks) +{ + fixed16_16 buffer_ticks = float_to_fp16_16(((float)(cpu_ticks - + gbc_sound_last_cpu_ticks) * sound_frequency) / 16777216.0); + u32 i, i2; + gbc_sound_struct *gs = gbc_sound_channel; + fixed16_16 sample_index, frequency_step; + fixed16_16 tick_counter; + u32 buffer_index; + s32 volume_left, volume_right; + u32 envelope_volume; + s32 current_sample; + u32 sound_status = address16(io_registers, 0x84) & 0xFFF0; + s8 *sample_data; + s8 *wave_bank; + u8 *wave_ram = ((u8 *)io_registers) + 0x90; + + gbc_sound_partial_ticks += fp16_16_fractional_part(buffer_ticks); + buffer_ticks = fp16_16_to_u32(buffer_ticks); + + if(gbc_sound_partial_ticks > 0xFFFF) + { + buffer_ticks += 1; + gbc_sound_partial_ticks &= 0xFFFF; + } + + SDL_LockMutex(sound_mutex); + if(synchronize_flag) + { + if(((gbc_sound_buffer_index - sound_buffer_base) % BUFFER_SIZE) > + (audio_buffer_size * 3 / 2)) + { + while(((gbc_sound_buffer_index - sound_buffer_base) % BUFFER_SIZE) > + (audio_buffer_size * 3 / 2)) + { + SDL_CondWait(sound_cv, sound_mutex); + } + +#ifdef PSP_BUILD + if(current_frameskip_type == auto_frameskip) + { + sceDisplayWaitVblankStart(); + real_frame_count = 0; + virtual_frame_count = 0; + } +#endif + +/* + +#ifdef GP2X_BUILD + if(current_frameskip_type == auto_frameskip) + { + u64 current_ticks; + u64 next_ticks; + get_ticks_us(¤t_ticks); + + next_ticks = ((current_ticks + 16666) / 16667) * 16667; + delay_us(next_ticks - current_ticks); + + get_ticks_us(&frame_count_initial_timestamp); + real_frame_count = 0; + virtual_frame_count = 0; + } +#endif + +*/ + } + } + if(sound_on == 1) + { + gs = gbc_sound_channel + 0; + if(gs->active_flag) + { + sound_status |= 0x01; + sample_data = gs->sample_data; + envelope_volume = gs->envelope_volume; + gbc_sound_render_channel(samples, 8, envelope, sweep); + } + + gs = gbc_sound_channel + 1; + if(gs->active_flag) + { + sound_status |= 0x02; + sample_data = gs->sample_data; + envelope_volume = gs->envelope_volume; + gbc_sound_render_channel(samples, 8, envelope, nosweep); + } + + gs = gbc_sound_channel + 2; + if(gbc_sound_wave_update) + { + if(gs->wave_bank == 1) + { + gbc_sound_load_wave_ram(1); + } + else + { + gbc_sound_load_wave_ram(0); + } + + gbc_sound_wave_update = 0; + } + + if((gs->active_flag) && (gs->master_enable)) + { + sound_status |= 0x04; + sample_data = wave_samples; + if(gs->wave_type == 0) + { + if(gs->wave_bank == 1) + sample_data += 32; + + gbc_sound_render_channel(samples, 32, noenvelope, nosweep); + } + else + { + gbc_sound_render_channel(samples, 64, noenvelope, nosweep); + } + } + + gs = gbc_sound_channel + 3; + if(gs->active_flag) + { + sound_status |= 0x08; + envelope_volume = gs->envelope_volume; + + if(gs->noise_type == 1) + { + gbc_sound_render_channel(noise, half, envelope, nosweep); + } + else + { + gbc_sound_render_channel(noise, full, envelope, nosweep); + } + } + } + + address16(io_registers, 0x84) = sound_status; + + SDL_CondSignal(sound_cv); + + SDL_UnlockMutex(sound_mutex); + + gbc_sound_last_cpu_ticks = cpu_ticks; + gbc_sound_buffer_index = + (gbc_sound_buffer_index + (buffer_ticks * 2)) % BUFFER_SIZE; +} + +#define sound_copy_normal() \ + current_sample = source[i] \ + +#define sound_copy(source_offset, length, render_type) \ + _length = (length) / 2; \ + source = (s16 *)(sound_buffer + source_offset); \ + for(i = 0; i < _length; i++) \ + { \ + sound_copy_##render_type(); \ + if(current_sample > 2047) \ + current_sample = 2047; \ + if(current_sample < -2048) \ + current_sample = -2048; \ + \ + stream_base[i] = current_sample << 4; \ + source[i] = 0; \ + } \ + +#define sound_copy_null(source_offset, length) \ + _length = (length) / 2; \ + source = (s16 *)(sound_buffer + source_offset); \ + for(i = 0; i < _length; i++) \ + { \ + stream_base[i] = 0; \ + source[i] = 0; \ + } \ + + +void sound_callback(void *userdata, Uint8 *stream, int length) +{ + u32 sample_length = length / 2; + u32 _length; + u32 i; + s16 *stream_base = (s16 *)stream; + s16 *source; + s32 current_sample; + + SDL_LockMutex(sound_mutex); + + while(((gbc_sound_buffer_index - sound_buffer_base) % BUFFER_SIZE) < + length) + { + SDL_CondWait(sound_cv, sound_mutex); + } + + if(global_enable_audio) + { + if((sound_buffer_base + sample_length) >= BUFFER_SIZE) + { + u32 partial_length = (BUFFER_SIZE - sound_buffer_base) * 2; + sound_copy(sound_buffer_base, partial_length, normal); + source = (s16 *)sound_buffer; + sound_copy(0, length - partial_length, normal); + sound_buffer_base = (length - partial_length) / 2; + } + else + { + sound_copy(sound_buffer_base, length, normal); + sound_buffer_base += sample_length; + } + } + else + { + if((sound_buffer_base + sample_length) >= BUFFER_SIZE) + { + u32 partial_length = (BUFFER_SIZE - sound_buffer_base) * 2; + sound_copy_null(sound_buffer_base, partial_length); + source = (s16 *)sound_buffer; + sound_copy(0, length - partial_length, normal); + sound_buffer_base = (length - partial_length) / 2; + } + else + { + sound_copy_null(sound_buffer_base, length); + sound_buffer_base += sample_length; + } + } + + SDL_CondSignal(sound_cv); + + SDL_UnlockMutex(sound_mutex); +} + +// Special thanks to blarrg for the LSFR frequency used in Meridian, as posted +// on the forum at http://meridian.overclocked.org: +// http://meridian.overclocked.org/cgi-bin/wwwthreads/showpost.pl?Board=merid +// angeneraldiscussion&Number=2069&page=0&view=expanded&mode=threaded&sb=4 +// Hope you don't mind me borrowing it ^_- + +void init_noise_table(u32 *table, u32 period, u32 bit_length) +{ + u32 shift_register = 0xFF; + u32 mask = ~(1 << bit_length); + s32 table_pos, bit_pos; + u32 current_entry; + u32 table_period = (period + 31) / 32; + + // Bits are stored in reverse order so they can be more easily moved to + // bit 31, for sign extended shift down. + + for(table_pos = 0; table_pos < table_period; table_pos++) + { + current_entry = 0; + for(bit_pos = 31; bit_pos >= 0; bit_pos--) + { + current_entry |= (shift_register & 0x01) << bit_pos; + + shift_register = + ((1 & (shift_register ^ (shift_register >> 1))) << bit_length) | + ((shift_register >> 1) & mask); + } + + table[table_pos] = current_entry; + } +} + +void reset_sound() +{ + direct_sound_struct *ds = direct_sound_channel; + gbc_sound_struct *gs = gbc_sound_channel; + u32 i; + + sound_on = 0; + sound_buffer_base = 0; + sound_last_cpu_ticks = 0; + memset(sound_buffer, 0, audio_buffer_size); + + for(i = 0; i < 2; i++, ds++) + { + ds->buffer_index = 0; + ds->status = DIRECT_SOUND_INACTIVE; + ds->fifo_top = 0; + ds->fifo_base = 0; + ds->fifo_fractional = 0; + ds->last_cpu_ticks = 0; + memset(ds->fifo, 0, 32); + } + + gbc_sound_buffer_index = 0; + gbc_sound_last_cpu_ticks = 0; + gbc_sound_partial_ticks = 0; + + gbc_sound_master_volume_left = 0; + gbc_sound_master_volume_right = 0; + gbc_sound_master_volume = 0; + memset(wave_samples, 0, 64); + + for(i = 0; i < 4; i++, gs++) + { + gs->status = GBC_SOUND_INACTIVE; + gs->sample_data = square_pattern_duty[2]; + gs->active_flag = 0; + } +} + +void sound_exit() +{ + gbc_sound_buffer_index = + (sound_buffer_base + audio_buffer_size) % BUFFER_SIZE; + SDL_PauseAudio(1); + SDL_CondSignal(sound_cv); +} + +void init_sound() +{ +#ifdef PSP_BUILD + audio_buffer_size = (audio_buffer_size_number * 1024) + 3072; +#elif defined(TAVI_BUILD) || defined(ARM_ARCH) + audio_buffer_size = 16 << audio_buffer_size_number; +// audio_buffer_size = 16384; +#else + audio_buffer_size = 16384; +#endif + + SDL_AudioSpec desired_spec = + { + sound_frequency, + AUDIO_S16, + 2, + 0, + audio_buffer_size / 4, + 0, + 0, + sound_callback, + NULL + }; + + gbc_sound_tick_step = + float_to_fp16_16(256.0 / sound_frequency); + + init_noise_table(noise_table15, 32767, 14); + init_noise_table(noise_table7, 127, 6); + + reset_sound(); + + SDL_OpenAudio(&desired_spec, &sound_settings); + sound_frequency = sound_settings.freq; + sound_mutex = SDL_CreateMutex(); + sound_cv = SDL_CreateCond(); + SDL_PauseAudio(0); +} + +#define sound_savestate_builder(type) \ +void sound_##type##_savestate(file_tag_type savestate_file) \ +{ \ + file_##type##_variable(savestate_file, sound_on); \ + file_##type##_variable(savestate_file, sound_buffer_base); \ + file_##type##_variable(savestate_file, sound_last_cpu_ticks); \ + file_##type##_variable(savestate_file, gbc_sound_buffer_index); \ + file_##type##_variable(savestate_file, gbc_sound_last_cpu_ticks); \ + file_##type##_variable(savestate_file, gbc_sound_partial_ticks); \ + file_##type##_variable(savestate_file, gbc_sound_master_volume_left); \ + file_##type##_variable(savestate_file, gbc_sound_master_volume_right); \ + file_##type##_variable(savestate_file, gbc_sound_master_volume); \ + file_##type##_array(savestate_file, wave_samples); \ + file_##type##_array(savestate_file, direct_sound_channel); \ + file_##type##_array(savestate_file, gbc_sound_channel); \ +} \ + +sound_savestate_builder(read); +sound_savestate_builder(write_mem); + diff --git a/sound.h b/sound.h new file mode 100644 index 0000000..303cf83 --- /dev/null +++ b/sound.h @@ -0,0 +1,328 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUND_H +#define SOUND_H + +#define BUFFER_SIZE 65536 + +// A lot of sound cards on PC can't handle such small buffers but this +// seems to work well on PSP. + +#ifdef PSP_BUILD + +#define SOUND_BUFFER_SIZE 4096 + +#else + +#define SOUND_BUFFER_SIZE 16384 + +#endif + +typedef enum +{ + DIRECT_SOUND_INACTIVE, + DIRECT_SOUND_RIGHT, + DIRECT_SOUND_LEFT, + DIRECT_SOUND_LEFTRIGHT +} direct_sound_status_type; + +typedef enum +{ + DIRECT_SOUND_VOLUME_50, + DIRECT_SOUND_VOLUME_100 +} direct_sound_volume_type; + +typedef struct +{ + s8 fifo[32]; + u32 fifo_base; + u32 fifo_top; + fixed16_16 fifo_fractional; + // The + 1 is to give some extra room for linear interpolation + // when wrapping around. + u32 buffer_index; + direct_sound_status_type status; + direct_sound_volume_type volume; + u32 last_cpu_ticks; +} direct_sound_struct; + +typedef enum +{ + GBC_SOUND_INACTIVE, + GBC_SOUND_RIGHT, + GBC_SOUND_LEFT, + GBC_SOUND_LEFTRIGHT +} gbc_sound_status_type; + + +typedef struct +{ + u32 rate; + fixed16_16 frequency_step; + fixed16_16 sample_index; + fixed16_16 tick_counter; + u32 total_volume; + u32 envelope_initial_volume; + u32 envelope_volume; + u32 envelope_direction; + u32 envelope_status; + u32 envelope_step; + u32 envelope_ticks; + u32 envelope_initial_ticks; + u32 sweep_status; + u32 sweep_direction; + u32 sweep_ticks; + u32 sweep_initial_ticks; + u32 sweep_shift; + u32 length_status; + u32 length_ticks; + u32 noise_type; + u32 wave_type; + u32 wave_bank; + u32 wave_volume; + gbc_sound_status_type status; + u32 active_flag; + u32 master_enable; + s8 *sample_data; +} gbc_sound_struct; + +extern direct_sound_struct direct_sound_channel[2]; +extern gbc_sound_struct gbc_sound_channel[4]; +extern s8 square_pattern_duty[4][8]; +extern u32 gbc_sound_master_volume_left; +extern u32 gbc_sound_master_volume_right; +extern u32 gbc_sound_master_volume; + +extern u32 sound_frequency; +extern u32 sound_on; + +extern u32 global_enable_audio; +extern u32 enable_low_pass_filter; +extern u32 audio_buffer_size_number; + +extern SDL_mutex *sound_mutex; +extern SDL_cond *sound_cv; + +void sound_timer_queue8(u32 channel, u8 value); +void sound_timer_queue16(u32 channel, u16 value); +void sound_timer_queue32(u32 channel, u32 value); +void sound_timer(fixed16_16 frequency_step, u32 channel); +void sound_reset_fifo(u32 channel); +void update_gbc_sound(u32 cpu_ticks); +void init_sound(); +void sound_write_mem_savestate(file_tag_type savestate_file); +void sound_read_savestate(file_tag_type savestate_file); + +#define gbc_sound_tone_control_low(channel, address) \ +{ \ + u32 initial_volume = (value >> 12) & 0x0F; \ + u32 envelope_ticks = ((value >> 8) & 0x07) * 4; \ + gbc_sound_channel[channel].length_ticks = 64 - (value & 0x3F); \ + gbc_sound_channel[channel].sample_data = \ + square_pattern_duty[(value >> 6) & 0x03]; \ + gbc_sound_channel[channel].envelope_direction = (value >> 11) & 0x01; \ + gbc_sound_channel[channel].envelope_initial_volume = initial_volume; \ + gbc_sound_channel[channel].envelope_volume = initial_volume; \ + gbc_sound_channel[channel].envelope_initial_ticks = envelope_ticks; \ + gbc_sound_channel[channel].envelope_ticks = envelope_ticks; \ + gbc_sound_channel[channel].envelope_status = (envelope_ticks != 0); \ + gbc_sound_channel[channel].envelope_volume = initial_volume; \ + gbc_sound_update = 1; \ + address16(io_registers, address) = value; \ +} \ + +#define gbc_sound_tone_control_high(channel, address) \ +{ \ + u32 rate = value & 0x7FF; \ + gbc_sound_channel[channel].rate = rate; \ + gbc_sound_channel[channel].frequency_step = \ + float_to_fp16_16(((131072.0 / (2048 - rate)) * 8.0) / sound_frequency); \ + gbc_sound_channel[channel].length_status = (value >> 14) & 0x01; \ + if(value & 0x8000) \ + { \ + gbc_sound_channel[channel].active_flag = 1; \ + gbc_sound_channel[channel].sample_index -= float_to_fp16_16(1.0 / 12.0); \ + gbc_sound_channel[channel].envelope_ticks = \ + gbc_sound_channel[channel].envelope_initial_ticks; \ + gbc_sound_channel[channel].envelope_volume = \ + gbc_sound_channel[channel].envelope_initial_volume; \ + } \ + \ + gbc_sound_update = 1; \ + address16(io_registers, address) = value; \ +} \ + +#define gbc_sound_tone_control_sweep() \ +{ \ + u32 sweep_ticks = ((value >> 4) & 0x07) * 2; \ + gbc_sound_channel[0].sweep_shift = value & 0x07; \ + gbc_sound_channel[0].sweep_direction = (value >> 3) & 0x01; \ + gbc_sound_channel[0].sweep_status = (value != 8); \ + gbc_sound_channel[0].sweep_ticks = sweep_ticks; \ + gbc_sound_channel[0].sweep_initial_ticks = sweep_ticks; \ + gbc_sound_update = 1; \ + address16(io_registers, 0x60) = value; \ +} \ + +#define gbc_sound_wave_control() \ +{ \ + gbc_sound_channel[2].wave_type = (value >> 5) & 0x01; \ + gbc_sound_channel[2].wave_bank = (value >> 6) & 0x01; \ + if(value & 0x80) \ + { \ + gbc_sound_channel[2].master_enable = 1; \ + } \ + else \ + { \ + gbc_sound_channel[2].master_enable = 0; \ + } \ + \ + gbc_sound_update = 1; \ + address16(io_registers, 0x70) = value; \ +} \ + +static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 }; + +#define gbc_sound_tone_control_low_wave() \ +{ \ + gbc_sound_channel[2].length_ticks = 256 - (value & 0xFF); \ + if((value >> 15) & 0x01) \ + { \ + gbc_sound_channel[2].wave_volume = 12288; \ + } \ + else \ + { \ + gbc_sound_channel[2].wave_volume = \ + gbc_sound_wave_volume[(value >> 13) & 0x03]; \ + } \ + gbc_sound_update = 1; \ + address16(io_registers, 0x72) = value; \ +} \ + +#define gbc_sound_tone_control_high_wave() \ +{ \ + u32 rate = value & 0x7FF; \ + gbc_sound_channel[2].rate = rate; \ + gbc_sound_channel[2].frequency_step = \ + float_to_fp16_16((2097152.0 / (2048 - rate)) / sound_frequency); \ + gbc_sound_channel[2].length_status = (value >> 14) & 0x01; \ + if(value & 0x8000) \ + { \ + gbc_sound_channel[2].sample_index = 0; \ + gbc_sound_channel[2].active_flag = 1; \ + } \ + gbc_sound_update = 1; \ + address16(io_registers, 0x74) = value; \ +} \ + +#define gbc_sound_noise_control() \ +{ \ + u32 dividing_ratio = value & 0x07; \ + u32 frequency_shift = (value >> 4) & 0x0F; \ + if(dividing_ratio == 0) \ + { \ + gbc_sound_channel[3].frequency_step = \ + float_to_fp16_16(1048576.0 / (1 << (frequency_shift + 1)) / \ + sound_frequency); \ + } \ + else \ + { \ + gbc_sound_channel[3].frequency_step = \ + float_to_fp16_16(524288.0 / (dividing_ratio * \ + (1 << (frequency_shift + 1))) / sound_frequency); \ + } \ + gbc_sound_channel[3].noise_type = (value >> 3) & 0x01; \ + gbc_sound_channel[3].length_status = (value >> 14) & 0x01; \ + if(value & 0x8000) \ + { \ + gbc_sound_channel[3].sample_index = 0; \ + gbc_sound_channel[3].active_flag = 1; \ + gbc_sound_channel[3].envelope_ticks = \ + gbc_sound_channel[3].envelope_initial_ticks; \ + gbc_sound_channel[3].envelope_volume = \ + gbc_sound_channel[3].envelope_initial_volume; \ + } \ + gbc_sound_update = 1; \ + address16(io_registers, 0x7C) = value; \ +} \ + +#define gbc_trigger_sound_channel(channel) \ + gbc_sound_master_volume_right = value & 0x07; \ + gbc_sound_master_volume_left = (value >> 4) & 0x07; \ + gbc_sound_channel[channel].status = ((value >> (channel + 8)) & 0x01) | \ + ((value >> (channel + 11)) & 0x03) \ + +#define gbc_trigger_sound() \ +{ \ + gbc_trigger_sound_channel(0); \ + gbc_trigger_sound_channel(1); \ + gbc_trigger_sound_channel(2); \ + gbc_trigger_sound_channel(3); \ + address16(io_registers, 0x80) = value; \ +} \ + +#define trigger_sound() \ +{ \ + timer[0].direct_sound_channels = (((value >> 10) & 0x01) == 0) | \ + ((((value >> 14) & 0x01) == 0) << 1); \ + timer[1].direct_sound_channels = (((value >> 10) & 0x01) == 1) | \ + ((((value >> 14) & 0x01) == 1) << 1); \ + direct_sound_channel[0].volume = (value >> 2) & 0x01; \ + direct_sound_channel[0].status = (value >> 8) & 0x03; \ + direct_sound_channel[1].volume = (value >> 3) & 0x01; \ + direct_sound_channel[1].status = (value >> 12) & 0x03; \ + gbc_sound_master_volume = value & 0x03; \ + \ + if((value >> 11) & 0x01) \ + sound_reset_fifo(0); \ + if((value >> 15) & 0x01) \ + sound_reset_fifo(1); \ + address16(io_registers, 0x82) = value; \ +} \ + +#define sound_on() \ + if(value & 0x80) \ + { \ + if(sound_on != 1) \ + { \ + sound_on = 1; \ + } \ + } \ + else \ + { \ + u32 i; \ + for(i = 0; i < 4; i++) \ + { \ + gbc_sound_channel[i].active_flag = 0; \ + } \ + sound_on = 0; \ + } \ + address16(io_registers, 0x84) = \ + (address16(io_registers, 0x84) & 0x000F) | (value & 0xFFF0); \ + +#define sound_update_frequency_step(timer_number) \ + timer[timer_number].frequency_step = \ + float_to_fp16_16(16777216.0 / (timer_reload * sound_frequency)) \ + + +void reset_sound(); +void sound_exit(); + +#endif diff --git a/video.c b/video.c new file mode 100644 index 0000000..e1f749e --- /dev/null +++ b/video.c @@ -0,0 +1,3937 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "common.h" +#include "font.h" + +#ifdef PSP_BUILD + +#include + +#include +#include +#include + +#include +#include +#include + +static float *screen_vertex = (float *)0x441FC100; +static u32 *ge_cmd = (u32 *)0x441FC000; +static u16 *psp_gu_vram_base = (u16 *)(0x44000000); +static u32 *ge_cmd_ptr = (u32 *)0x441FC000; +static u32 gecbid; +static u32 video_direct = 0; + +static u32 __attribute__((aligned(16))) display_list[32]; + +#define GBA_SCREEN_WIDTH 240 +#define GBA_SCREEN_HEIGHT 160 + +#define PSP_SCREEN_WIDTH 480 +#define PSP_SCREEN_HEIGHT 272 +#define PSP_LINE_SIZE 512 + +#define PSP_ALL_BUTTON_MASK 0xFFFF + +#define GE_CMD_FBP 0x9C +#define GE_CMD_FBW 0x9D +#define GE_CMD_TBP0 0xA0 +#define GE_CMD_TBW0 0xA8 +#define GE_CMD_TSIZE0 0xB8 +#define GE_CMD_TFLUSH 0xCB +#define GE_CMD_CLEAR 0xD3 +#define GE_CMD_VTYPE 0x12 +#define GE_CMD_BASE 0x10 +#define GE_CMD_VADDR 0x01 +#define GE_CMD_IADDR 0x02 +#define GE_CMD_PRIM 0x04 +#define GE_CMD_FINISH 0x0F +#define GE_CMD_SIGNAL 0x0C +#define GE_CMD_NOP 0x00 + +#define GE_CMD(cmd, operand) \ + *ge_cmd_ptr = (((GE_CMD_##cmd) << 24) | (operand)); \ + ge_cmd_ptr++ \ + +static u16 *screen_texture = (u16 *)(0x4000000 + (512 * 272 * 2)); +static u16 *current_screen_texture = (u16 *)(0x4000000 + (512 * 272 * 2)); +static u16 *screen_pixels = (u16 *)(0x4000000 + (512 * 272 * 2)); +static u32 screen_pitch = 240; + +static void Ge_Finish_Callback(int id, void *arg) +{ +} + +#define get_screen_pixels() \ + screen_pixels \ + +#define get_screen_pitch() \ + screen_pitch \ + +#else + +#ifdef GP2X_BUILD +#include "SDL_gp2x.h" +SDL_Surface *hw_screen; +#endif +SDL_Surface *screen; +const u32 video_scale = 1; + +#define get_screen_pixels() \ + ((u16 *)screen->pixels) \ + +#define get_screen_pitch() \ + (screen->pitch / 2) \ + +#endif + +void render_scanline_conditional_tile(u32 start, u32 end, u16 *scanline, + u32 enable_flags, u32 dispcnt, u32 bldcnt, tile_layer_render_struct + *layer_renderers); +void render_scanline_conditional_bitmap(u32 start, u32 end, u16 *scanline, + u32 enable_flags, u32 dispcnt, u32 bldcnt, bitmap_layer_render_struct + *layer_renderers); + +#define no_op \ + +// This old version is not necessary if the palette is either being converted +// transparently or the ABGR 1555 format is being used natively. The direct +// version (without conversion) is much faster. + +#define tile_lookup_palette_full(palette, source) \ + current_pixel = palette[source]; \ + convert_palette(current_pixel) \ + +#define tile_lookup_palette(palette, source) \ + current_pixel = palette[source]; \ + + +#ifdef RENDER_COLOR16_NORMAL + +#define tile_expand_base_normal(index) \ + tile_expand_base_color16(index) \ + +#else + +#define tile_expand_base_normal(index) \ + tile_lookup_palette(palette, current_pixel); \ + dest_ptr[index] = current_pixel \ + +#endif + +#define tile_expand_transparent_normal(index) \ + tile_expand_base_normal(index) \ + +#define tile_expand_copy(index) \ + dest_ptr[index] = copy_ptr[index] \ + + +#define advance_dest_ptr_base(delta) \ + dest_ptr += delta \ + +#define advance_dest_ptr_transparent(delta) \ + advance_dest_ptr_base(delta) \ + +#define advance_dest_ptr_copy(delta) \ + advance_dest_ptr_base(delta); \ + copy_ptr += delta \ + + +#define color_combine_mask_a(layer) \ + ((io_registers[REG_BLDCNT] >> layer) & 0x01) \ + +// For color blending operations, will create a mask that has in bit +// 10 if the layer is target B, and bit 9 if the layer is target A. + +#define color_combine_mask(layer) \ + (color_combine_mask_a(layer) | \ + ((io_registers[REG_BLDCNT] >> (layer + 7)) & 0x02)) << 9 \ + +// For alpha blending renderers, draw the palette index (9bpp) and +// layer bits rather than the raw RGB. For the base this should write to +// the 32bit location directly. + +#define tile_expand_base_alpha(index) \ + dest_ptr[index] = current_pixel | pixel_combine \ + +#define tile_expand_base_bg(index) \ + dest_ptr[index] = bg_combine \ + + +// For layered (transparent) writes this should shift the "stack" and write +// to the bottom. This will preserve the topmost pixel and the most recent +// one. + +#define tile_expand_transparent_alpha(index) \ + dest_ptr[index] = (dest_ptr[index] << 16) | current_pixel | pixel_combine \ + + +// OBJ should only shift if the top isn't already OBJ +#define tile_expand_transparent_alpha_obj(index) \ + dest = dest_ptr[index]; \ + if(dest & 0x00000100) \ + { \ + dest_ptr[index] = (dest & 0xFFFF0000) | current_pixel | pixel_combine; \ + } \ + else \ + { \ + dest_ptr[index] = (dest << 16) | current_pixel | pixel_combine; \ + } \ + + +// For color effects that don't need to preserve the previous layer. +// The color32 version should be used with 32bit wide dest_ptr so as to be +// compatible with alpha combine on top of it. + +#define tile_expand_base_color16(index) \ + dest_ptr[index] = current_pixel | pixel_combine \ + +#define tile_expand_transparent_color16(index) \ + tile_expand_base_color16(index) \ + +#define tile_expand_base_color32(index) \ + tile_expand_base_color16(index) \ + +#define tile_expand_transparent_color32(index) \ + tile_expand_base_color16(index) \ + + +// Operations for isolation 8bpp pixels within 32bpp pixel blocks. + +#define tile_8bpp_pixel_op_mask(op_param) \ + current_pixel = current_pixels & 0xFF \ + +#define tile_8bpp_pixel_op_shift_mask(shift) \ + current_pixel = (current_pixels >> shift) & 0xFF \ + +#define tile_8bpp_pixel_op_shift(shift) \ + current_pixel = current_pixels >> shift \ + +#define tile_8bpp_pixel_op_none(shift) \ + +// Base should always draw raw in 8bpp mode; color 0 will be drawn where +// color 0 is. + +#define tile_8bpp_draw_base_normal(index) \ + tile_expand_base_normal(index) \ + +#define tile_8bpp_draw_base_alpha(index) \ + if(current_pixel) \ + { \ + tile_expand_base_alpha(index); \ + } \ + else \ + { \ + tile_expand_base_bg(index); \ + } \ + + +#define tile_8bpp_draw_base_color16(index) \ + tile_8bpp_draw_base_alpha(index) \ + +#define tile_8bpp_draw_base_color32(index) \ + tile_8bpp_draw_base_alpha(index) \ + + +#define tile_8bpp_draw_base(index, op, op_param, alpha_op) \ + tile_8bpp_pixel_op_##op(op_param); \ + tile_8bpp_draw_base_##alpha_op(index) \ + +// Transparent (layered) writes should only replace what is there if the +// pixel is not transparent (zero) + +#define tile_8bpp_draw_transparent(index, op, op_param, alpha_op) \ + tile_8bpp_pixel_op_##op(op_param); \ + if(current_pixel) \ + { \ + tile_expand_transparent_##alpha_op(index); \ + } \ + +#define tile_8bpp_draw_copy(index, op, op_param, alpha_op) \ + tile_8bpp_pixel_op_##op(op_param); \ + if(current_pixel) \ + { \ + tile_expand_copy(index); \ + } \ + +// Get the current tile from the map in 8bpp mode + +#define get_tile_8bpp() \ + current_tile = *map_ptr; \ + tile_ptr = tile_base + ((current_tile & 0x3FF) * 64) \ + + +// Draw half of a tile in 8bpp mode, for base renderer + +#define tile_8bpp_draw_four_noflip(index, combine_op, alpha_op) \ + tile_8bpp_draw_##combine_op(index + 0, mask, 0, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 1, shift_mask, 8, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 2, shift_mask, 16, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 3, shift, 24, alpha_op) \ + + +// Like the above, but draws the half-tile horizontally flipped + +#define tile_8bpp_draw_four_flip(index, combine_op, alpha_op) \ + tile_8bpp_draw_##combine_op(index + 3, mask, 0, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 2, shift_mask, 8, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 1, shift_mask, 16, alpha_op); \ + tile_8bpp_draw_##combine_op(index + 0, shift, 24, alpha_op) \ + +#define tile_8bpp_draw_four_base(index, alpha_op, flip_op) \ + tile_8bpp_draw_four_##flip_op(index, base, alpha_op) \ + + +// Draw half of a tile in 8bpp mode, for transparent renderer; as an +// optimization the entire thing is checked against zero (in transparent +// capable renders it is more likely for the pixels to be transparent than +// opaque) + +#define tile_8bpp_draw_four_transparent(index, alpha_op, flip_op) \ + if(current_pixels != 0) \ + { \ + tile_8bpp_draw_four_##flip_op(index, transparent, alpha_op); \ + } \ + +#define tile_8bpp_draw_four_copy(index, alpha_op, flip_op) \ + if(current_pixels != 0) \ + { \ + tile_8bpp_draw_four_##flip_op(index, copy, alpha_op); \ + } \ + +// Helper macro for drawing 8bpp tiles clipped against the edge of the screen + +#define partial_tile_8bpp(combine_op, alpha_op) \ + for(i = 0; i < partial_tile_run; i++) \ + { \ + tile_8bpp_draw_##combine_op(0, mask, 0, alpha_op); \ + current_pixels >>= 8; \ + advance_dest_ptr_##combine_op(1); \ + } \ + + +// Draws 8bpp tiles clipped against the left side of the screen, +// partial_tile_offset indicates how much clipped in it is, partial_tile_run +// indicates how much it should draw. + +#define partial_tile_right_noflip_8bpp(combine_op, alpha_op) \ + if(partial_tile_offset >= 4) \ + { \ + current_pixels = *((u32 *)(tile_ptr + 4)) >> \ + ((partial_tile_offset - 4) * 8); \ + partial_tile_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + partial_tile_run -= 4; \ + current_pixels = *((u32 *)tile_ptr) >> (partial_tile_offset * 8); \ + partial_tile_8bpp(combine_op, alpha_op); \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, noflip); \ + advance_dest_ptr_##combine_op(4); \ + } \ + + +// Draws 8bpp tiles clipped against both the left and right side of the +// screen, IE, runs of less than 8 - partial_tile_offset. + +#define partial_tile_mid_noflip_8bpp(combine_op, alpha_op) \ + if(partial_tile_offset >= 4) \ + { \ + current_pixels = *((u32 *)(tile_ptr + 4)) >> \ + ((partial_tile_offset - 4) * 8); \ + partial_tile_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + current_pixels = *((u32 *)tile_ptr) >> (partial_tile_offset * 8); \ + if((partial_tile_offset + partial_tile_run) > 4) \ + { \ + u32 old_run = partial_tile_run; \ + partial_tile_run = 4 - partial_tile_offset; \ + partial_tile_8bpp(combine_op, alpha_op); \ + partial_tile_run = old_run - partial_tile_run; \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + partial_tile_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + partial_tile_8bpp(combine_op, alpha_op); \ + } \ + } \ + + +// Draws 8bpp tiles clipped against the right side of the screen, +// partial_tile_run indicates how much there is to draw. + +#define partial_tile_left_noflip_8bpp(combine_op, alpha_op) \ + if(partial_tile_run >= 4) \ + { \ + current_pixels = *((u32 *)tile_ptr); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, noflip); \ + advance_dest_ptr_##combine_op(4); \ + tile_ptr += 4; \ + partial_tile_run -= 4; \ + } \ + \ + current_pixels = *((u32 *)(tile_ptr)); \ + partial_tile_8bpp(combine_op, alpha_op) \ + + +// Draws a non-clipped (complete) 8bpp tile. + +#define tile_noflip_8bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, noflip); \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + tile_8bpp_draw_four_##combine_op(4, alpha_op, noflip) \ + + +// Like the above versions but draws flipped tiles. + +#define partial_tile_flip_8bpp(combine_op, alpha_op) \ + for(i = 0; i < partial_tile_run; i++) \ + { \ + tile_8bpp_draw_##combine_op(0, shift, 24, alpha_op); \ + current_pixels <<= 8; \ + advance_dest_ptr_##combine_op(1); \ + } \ + +#define partial_tile_right_flip_8bpp(combine_op, alpha_op) \ + if(partial_tile_offset >= 4) \ + { \ + current_pixels = *((u32 *)tile_ptr) << ((partial_tile_offset - 4) * 8); \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + partial_tile_run -= 4; \ + current_pixels = *((u32 *)(tile_ptr + 4)) << \ + ((partial_tile_offset - 4) * 8); \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + current_pixels = *((u32 *)tile_ptr); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, flip); \ + advance_dest_ptr_##combine_op(4); \ + } \ + +#define partial_tile_mid_flip_8bpp(combine_op, alpha_op) \ + if(partial_tile_offset >= 4) \ + { \ + current_pixels = *((u32 *)tile_ptr) << ((partial_tile_offset - 4) * 8); \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + current_pixels = *((u32 *)(tile_ptr + 4)) << \ + ((partial_tile_offset - 4) * 8); \ + \ + if((partial_tile_offset + partial_tile_run) > 4) \ + { \ + u32 old_run = partial_tile_run; \ + partial_tile_run = 4 - partial_tile_offset; \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + partial_tile_run = old_run - partial_tile_run; \ + current_pixels = *((u32 *)(tile_ptr)); \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + } \ + else \ + { \ + partial_tile_flip_8bpp(combine_op, alpha_op); \ + } \ + } \ + +#define partial_tile_left_flip_8bpp(combine_op, alpha_op) \ + if(partial_tile_run >= 4) \ + { \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, flip); \ + advance_dest_ptr_##combine_op(4); \ + tile_ptr -= 4; \ + partial_tile_run -= 4; \ + } \ + \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + partial_tile_flip_8bpp(combine_op, alpha_op) \ + +#define tile_flip_8bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)(tile_ptr + 4)); \ + tile_8bpp_draw_four_##combine_op(0, alpha_op, flip); \ + current_pixels = *((u32 *)tile_ptr); \ + tile_8bpp_draw_four_##combine_op(4, alpha_op, flip) \ + + +// Operations for isolating 4bpp tiles in a 32bit block + +#define tile_4bpp_pixel_op_mask(op_param) \ + current_pixel = current_pixels & 0x0F \ + +#define tile_4bpp_pixel_op_shift_mask(shift) \ + current_pixel = (current_pixels >> shift) & 0x0F \ + +#define tile_4bpp_pixel_op_shift(shift) \ + current_pixel = current_pixels >> shift \ + +#define tile_4bpp_pixel_op_none(op_param) \ + +// Draws a single 4bpp pixel as base, normal renderer; checks to see if the +// pixel is zero because if so the current palette should not be applied. +// These ifs can be replaced with a lookup table, may or may not be superior +// this way, should be benchmarked. The lookup table would be from 0-255 +// identity map except for multiples of 16, which would map to 0. + +#define tile_4bpp_draw_base_normal(index) \ + if(current_pixel) \ + { \ + current_pixel |= current_palette; \ + tile_expand_base_normal(index); \ + } \ + else \ + { \ + tile_expand_base_normal(index); \ + } \ + + +#define tile_4bpp_draw_base_alpha(index) \ + if(current_pixel) \ + { \ + current_pixel |= current_palette; \ + tile_expand_base_alpha(index); \ + } \ + else \ + { \ + tile_expand_base_bg(index); \ + } \ + +#define tile_4bpp_draw_base_color16(index) \ + tile_4bpp_draw_base_alpha(index) \ + +#define tile_4bpp_draw_base_color32(index) \ + tile_4bpp_draw_base_alpha(index) \ + + +#define tile_4bpp_draw_base(index, op, op_param, alpha_op) \ + tile_4bpp_pixel_op_##op(op_param); \ + tile_4bpp_draw_base_##alpha_op(index) \ + + +// Draws a single 4bpp pixel as layered, if not transparent. + +#define tile_4bpp_draw_transparent(index, op, op_param, alpha_op) \ + tile_4bpp_pixel_op_##op(op_param); \ + if(current_pixel) \ + { \ + current_pixel |= current_palette; \ + tile_expand_transparent_##alpha_op(index); \ + } \ + +#define tile_4bpp_draw_copy(index, op, op_param, alpha_op) \ + tile_4bpp_pixel_op_##op(op_param); \ + if(current_pixel) \ + { \ + current_pixel |= current_palette; \ + tile_expand_copy(index); \ + } \ + + +// Draws eight background pixels in transparent mode, for alpha or normal +// renderers. + +#define tile_4bpp_draw_eight_base_zero(value) \ + dest_ptr[0] = value; \ + dest_ptr[1] = value; \ + dest_ptr[2] = value; \ + dest_ptr[3] = value; \ + dest_ptr[4] = value; \ + dest_ptr[5] = value; \ + dest_ptr[6] = value; \ + dest_ptr[7] = value \ + + +// Draws eight background pixels for the alpha renderer, basically color zero +// with the background flag high. + +#define tile_4bpp_draw_eight_base_zero_alpha() \ + tile_4bpp_draw_eight_base_zero(bg_combine) \ + +#define tile_4bpp_draw_eight_base_zero_color16() \ + tile_4bpp_draw_eight_base_zero_alpha() \ + +#define tile_4bpp_draw_eight_base_zero_color32() \ + tile_4bpp_draw_eight_base_zero_alpha() \ + + +// Draws eight background pixels for the normal renderer, just a bunch of +// zeros. + +#ifdef RENDER_COLOR16_NORMAL + +#define tile_4bpp_draw_eight_base_zero_normal() \ + current_pixel = 0; \ + tile_4bpp_draw_eight_base_zero(current_pixel) \ + +#else + +#define tile_4bpp_draw_eight_base_zero_normal() \ + current_pixel = palette[0]; \ + tile_4bpp_draw_eight_base_zero(current_pixel) \ + +#endif + + +// Draws eight 4bpp pixels. + +#define tile_4bpp_draw_eight_noflip(combine_op, alpha_op) \ + tile_4bpp_draw_##combine_op(0, mask, 0, alpha_op); \ + tile_4bpp_draw_##combine_op(1, shift_mask, 4, alpha_op); \ + tile_4bpp_draw_##combine_op(2, shift_mask, 8, alpha_op); \ + tile_4bpp_draw_##combine_op(3, shift_mask, 12, alpha_op); \ + tile_4bpp_draw_##combine_op(4, shift_mask, 16, alpha_op); \ + tile_4bpp_draw_##combine_op(5, shift_mask, 20, alpha_op); \ + tile_4bpp_draw_##combine_op(6, shift_mask, 24, alpha_op); \ + tile_4bpp_draw_##combine_op(7, shift, 28, alpha_op) \ + + +// Draws eight 4bpp pixels in reverse order (for hflip). + +#define tile_4bpp_draw_eight_flip(combine_op, alpha_op) \ + tile_4bpp_draw_##combine_op(7, mask, 0, alpha_op); \ + tile_4bpp_draw_##combine_op(6, shift_mask, 4, alpha_op); \ + tile_4bpp_draw_##combine_op(5, shift_mask, 8, alpha_op); \ + tile_4bpp_draw_##combine_op(4, shift_mask, 12, alpha_op); \ + tile_4bpp_draw_##combine_op(3, shift_mask, 16, alpha_op); \ + tile_4bpp_draw_##combine_op(2, shift_mask, 20, alpha_op); \ + tile_4bpp_draw_##combine_op(1, shift_mask, 24, alpha_op); \ + tile_4bpp_draw_##combine_op(0, shift, 28, alpha_op) \ + + +// Draws eight 4bpp pixels in base mode, checks if all are zero, if so draws +// the appropriate background pixels. + +#define tile_4bpp_draw_eight_base(alpha_op, flip_op) \ + if(current_pixels != 0) \ + { \ + tile_4bpp_draw_eight_##flip_op(base, alpha_op); \ + } \ + else \ + { \ + tile_4bpp_draw_eight_base_zero_##alpha_op(); \ + } \ + + +// Draws eight 4bpp pixels in transparent (layered) mode, checks if all are +// zero and if so draws nothing. + +#define tile_4bpp_draw_eight_transparent(alpha_op, flip_op) \ + if(current_pixels != 0) \ + { \ + tile_4bpp_draw_eight_##flip_op(transparent, alpha_op); \ + } \ + + +#define tile_4bpp_draw_eight_copy(alpha_op, flip_op) \ + if(current_pixels != 0) \ + { \ + tile_4bpp_draw_eight_##flip_op(copy, alpha_op); \ + } \ + +// Gets the current tile in 4bpp mode, also getting the current palette and +// the pixel block. + +#define get_tile_4bpp() \ + current_tile = *map_ptr; \ + current_palette = (current_tile >> 12) << 4; \ + tile_ptr = tile_base + ((current_tile & 0x3FF) * 32); \ + + +// Helper macro for drawing clipped 4bpp tiles. + +#define partial_tile_4bpp(combine_op, alpha_op) \ + for(i = 0; i < partial_tile_run; i++) \ + { \ + tile_4bpp_draw_##combine_op(0, mask, 0, alpha_op); \ + current_pixels >>= 4; \ + advance_dest_ptr_##combine_op(1); \ + } \ + + +// Draws a 4bpp tile clipped against the left edge of the screen. +// partial_tile_offset is how far in it's clipped, partial_tile_run is +// how many to draw. + +#define partial_tile_right_noflip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr) >> (partial_tile_offset * 4); \ + partial_tile_4bpp(combine_op, alpha_op) \ + + +// Draws a 4bpp tile clipped against both edges of the screen, same as right. + +#define partial_tile_mid_noflip_4bpp(combine_op, alpha_op) \ + partial_tile_right_noflip_4bpp(combine_op, alpha_op) \ + + +// Draws a 4bpp tile clipped against the right edge of the screen. +// partial_tile_offset is how many to draw. + +#define partial_tile_left_noflip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr); \ + partial_tile_4bpp(combine_op, alpha_op) \ + + +// Draws a complete 4bpp tile row (not clipped) +#define tile_noflip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr); \ + tile_4bpp_draw_eight_##combine_op(alpha_op, noflip) \ + + +// Like the above, but draws flipped tiles. + +#define partial_tile_flip_4bpp(combine_op, alpha_op) \ + for(i = 0; i < partial_tile_run; i++) \ + { \ + tile_4bpp_draw_##combine_op(0, shift, 28, alpha_op); \ + current_pixels <<= 4; \ + advance_dest_ptr_##combine_op(1); \ + } \ + +#define partial_tile_right_flip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr) << (partial_tile_offset * 4); \ + partial_tile_flip_4bpp(combine_op, alpha_op) \ + +#define partial_tile_mid_flip_4bpp(combine_op, alpha_op) \ + partial_tile_right_flip_4bpp(combine_op, alpha_op) \ + +#define partial_tile_left_flip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr); \ + partial_tile_flip_4bpp(combine_op, alpha_op) \ + +#define tile_flip_4bpp(combine_op, alpha_op) \ + current_pixels = *((u32 *)tile_ptr); \ + tile_4bpp_draw_eight_##combine_op(alpha_op, flip) \ + + +// Draws a single (partial or complete) tile from the tilemap, flipping +// as necessary. + +#define single_tile_map(tile_type, combine_op, color_depth, alpha_op) \ + get_tile_##color_depth(); \ + if(current_tile & 0x800) \ + tile_ptr += vertical_pixel_flip; \ + \ + if(current_tile & 0x400) \ + { \ + tile_type##_flip_##color_depth(combine_op, alpha_op); \ + } \ + else \ + { \ + tile_type##_noflip_##color_depth(combine_op, alpha_op); \ + } \ + + +// Draws multiple sequential tiles from the tilemap, hflips and vflips as +// necessary. + +#define multiple_tile_map(combine_op, color_depth, alpha_op) \ + for(i = 0; i < tile_run; i++) \ + { \ + single_tile_map(tile, combine_op, color_depth, alpha_op); \ + advance_dest_ptr_##combine_op(8); \ + map_ptr++; \ + } \ + +// Draws a partial tile from a tilemap clipped against the left edge of the +// screen. + +#define partial_tile_right_map(combine_op, color_depth, alpha_op) \ + single_tile_map(partial_tile_right, combine_op, color_depth, alpha_op); \ + map_ptr++ \ + +// Draws a partial tile from a tilemap clipped against both edges of the +// screen. + +#define partial_tile_mid_map(combine_op, color_depth, alpha_op) \ + single_tile_map(partial_tile_mid, combine_op, color_depth, alpha_op) \ + +// Draws a partial tile from a tilemap clipped against the right edge of the +// screen. + +#define partial_tile_left_map(combine_op, color_depth, alpha_op) \ + single_tile_map(partial_tile_left, combine_op, color_depth, alpha_op) \ + + +// Advances a non-flipped 4bpp obj to the next tile. + +#define obj_advance_noflip_4bpp() \ + tile_ptr += 32 \ + + +// Advances a non-flipped 8bpp obj to the next tile. + +#define obj_advance_noflip_8bpp() \ + tile_ptr += 64 \ + + +// Advances a flipped 4bpp obj to the next tile. + +#define obj_advance_flip_4bpp() \ + tile_ptr -= 32 \ + + +// Advances a flipped 8bpp obj to the next tile. + +#define obj_advance_flip_8bpp() \ + tile_ptr -= 64 \ + + + +// Draws multiple sequential tiles from an obj, flip_op determines if it should +// be flipped or not (set to flip or noflip) + +#define multiple_tile_obj(combine_op, color_depth, alpha_op, flip_op) \ + for(i = 0; i < tile_run; i++) \ + { \ + tile_##flip_op##_##color_depth(combine_op, alpha_op); \ + obj_advance_##flip_op##_##color_depth(); \ + advance_dest_ptr_##combine_op(8); \ + } \ + + +// Draws an obj's tile clipped against the left side of the screen + +#define partial_tile_right_obj(combine_op, color_depth, alpha_op, flip_op) \ + partial_tile_right_##flip_op##_##color_depth(combine_op, alpha_op); \ + obj_advance_##flip_op##_##color_depth() \ + +// Draws an obj's tile clipped against both sides of the screen + +#define partial_tile_mid_obj(combine_op, color_depth, alpha_op, flip_op) \ + partial_tile_mid_##flip_op##_##color_depth(combine_op, alpha_op) \ + +// Draws an obj's tile clipped against the right side of the screen + +#define partial_tile_left_obj(combine_op, color_depth, alpha_op, flip_op) \ + partial_tile_left_##flip_op##_##color_depth(combine_op, alpha_op) \ + + +// Extra variables specific for 8bpp/4bpp tile renderers. + +#define tile_extra_variables_8bpp() \ + +#define tile_extra_variables_4bpp() \ + u32 current_palette \ + + +// Byte lengths of complete tiles and tile rows in 4bpp and 8bpp. + +#define tile_width_4bpp 4 +#define tile_size_4bpp 32 +#define tile_width_8bpp 8 +#define tile_size_8bpp 64 + + +// Render a single scanline of text tiles + +#define tile_render(color_depth, combine_op, alpha_op) \ +{ \ + u32 vertical_pixel_offset = (vertical_offset % 8) * \ + tile_width_##color_depth; \ + u32 vertical_pixel_flip = \ + ((tile_size_##color_depth - tile_width_##color_depth) - \ + vertical_pixel_offset) - vertical_pixel_offset; \ + tile_extra_variables_##color_depth(); \ + u8 *tile_base = vram + (((bg_control >> 2) & 0x03) * (1024 * 16)) + \ + vertical_pixel_offset; \ + u32 pixel_run = 256 - (horizontal_offset % 256); \ + u32 current_tile; \ + \ + map_base += ((vertical_offset % 256) / 8) * 32; \ + partial_tile_offset = (horizontal_offset % 8); \ + \ + if(pixel_run >= end) \ + { \ + if(partial_tile_offset) \ + { \ + partial_tile_run = 8 - partial_tile_offset; \ + if(end < partial_tile_run) \ + { \ + partial_tile_run = end; \ + partial_tile_mid_map(combine_op, color_depth, alpha_op); \ + return; \ + } \ + else \ + { \ + end -= partial_tile_run; \ + partial_tile_right_map(combine_op, color_depth, alpha_op); \ + } \ + } \ + \ + tile_run = end / 8; \ + multiple_tile_map(combine_op, color_depth, alpha_op); \ + \ + partial_tile_run = end % 8; \ + \ + if(partial_tile_run) \ + { \ + partial_tile_left_map(combine_op, color_depth, alpha_op); \ + } \ + } \ + else \ + { \ + if(partial_tile_offset) \ + { \ + partial_tile_run = 8 - partial_tile_offset; \ + partial_tile_right_map(combine_op, color_depth, alpha_op); \ + } \ + \ + tile_run = (pixel_run - partial_tile_run) / 8; \ + multiple_tile_map(combine_op, color_depth, alpha_op); \ + map_ptr = second_ptr; \ + end -= pixel_run; \ + tile_run = end / 8; \ + multiple_tile_map(combine_op, color_depth, alpha_op); \ + \ + partial_tile_run = end % 8; \ + if(partial_tile_run) \ + { \ + partial_tile_left_map(combine_op, color_depth, alpha_op); \ + } \ + } \ +} \ + +#define render_scanline_dest_normal u16 +#define render_scanline_dest_alpha u32 +#define render_scanline_dest_alpha_obj u32 +#define render_scanline_dest_color16 u16 +#define render_scanline_dest_color32 u32 +#define render_scanline_dest_partial_alpha u32 +#define render_scanline_dest_copy_tile u16 +#define render_scanline_dest_copy_bitmap u16 + + +// If rendering a scanline that is not a target A then there's no point in +// keeping what's underneath it because it can't blend with it. + +#define render_scanline_skip_alpha(bg_type, combine_op) \ + if((pixel_combine & 0x00000200) == 0) \ + { \ + render_scanline_##bg_type##_##combine_op##_color32(layer, \ + start, end, scanline); \ + return; \ + } \ + + +#ifdef RENDER_COLOR16_NORMAL + +#define render_scanline_extra_variables_base_normal(bg_type) \ + const u32 pixel_combine = 0 \ + +#else + +#define render_scanline_extra_variables_base_normal(bg_type) \ + u16 *palette = palette_ram_converted \ + +#endif + + +#define render_scanline_extra_variables_base_alpha(bg_type) \ + u32 bg_combine = color_combine_mask(5); \ + u32 pixel_combine = color_combine_mask(layer) | (bg_combine << 16); \ + render_scanline_skip_alpha(bg_type, base) \ + +#define render_scanline_extra_variables_base_color() \ + u32 bg_combine = color_combine_mask(5); \ + u32 pixel_combine = color_combine_mask(layer) \ + +#define render_scanline_extra_variables_base_color16(bg_type) \ + render_scanline_extra_variables_base_color() \ + +#define render_scanline_extra_variables_base_color32(bg_type) \ + render_scanline_extra_variables_base_color() \ + + +#define render_scanline_extra_variables_transparent_normal(bg_type) \ + render_scanline_extra_variables_base_normal(bg_type) \ + +#define render_scanline_extra_variables_transparent_alpha(bg_type) \ + u32 pixel_combine = color_combine_mask(layer); \ + render_scanline_skip_alpha(bg_type, transparent) \ + +#define render_scanline_extra_variables_transparent_color() \ + u32 pixel_combine = color_combine_mask(layer) \ + +#define render_scanline_extra_variables_transparent_color16(bg_type) \ + render_scanline_extra_variables_transparent_color() \ + +#define render_scanline_extra_variables_transparent_color32(bg_type) \ + render_scanline_extra_variables_transparent_color() \ + + + + + +// Map widths and heights + +u32 map_widths[] = { 256, 512, 256, 512 }; +u32 map_heights[] = { 256, 256, 512, 512 }; + +// Build text scanline rendering functions. + +#define render_scanline_text_builder(combine_op, alpha_op) \ +void render_scanline_text_##combine_op##_##alpha_op(u32 layer, \ + u32 start, u32 end, void *scanline) \ +{ \ + render_scanline_extra_variables_##combine_op##_##alpha_op(text); \ + u32 bg_control = io_registers[REG_BG0CNT + layer]; \ + u32 map_size = (bg_control >> 14) & 0x03; \ + u32 map_width = map_widths[map_size]; \ + u32 map_height = map_heights[map_size]; \ + u32 horizontal_offset = \ + (io_registers[REG_BG0HOFS + (layer * 2)] + start) % 512; \ + u32 vertical_offset = (io_registers[REG_VCOUNT] + \ + io_registers[REG_BG0VOFS + (layer * 2)]) % 512; \ + u32 current_pixel; \ + u32 current_pixels; \ + u32 partial_tile_run = 0; \ + u32 partial_tile_offset; \ + u32 tile_run; \ + u32 i; \ + render_scanline_dest_##alpha_op *dest_ptr = \ + ((render_scanline_dest_##alpha_op *)scanline) + start; \ + \ + u16 *map_base = (u16 *)(vram + ((bg_control >> 8) & 0x1F) * (1024 * 2)); \ + u16 *map_ptr, *second_ptr; \ + u8 *tile_ptr; \ + \ + end -= start; \ + \ + if((map_size & 0x02) && (vertical_offset >= 256)) \ + { \ + map_base += ((map_width / 8) * 32) + \ + (((vertical_offset - 256) / 8) * 32); \ + } \ + else \ + { \ + map_base += (((vertical_offset % 256) / 8) * 32); \ + } \ + \ + if(map_size & 0x01) \ + { \ + if(horizontal_offset >= 256) \ + { \ + horizontal_offset -= 256; \ + map_ptr = map_base + (32 * 32) + (horizontal_offset / 8); \ + second_ptr = map_base; \ + } \ + else \ + { \ + map_ptr = map_base + (horizontal_offset / 8); \ + second_ptr = map_base + (32 * 32); \ + } \ + } \ + else \ + { \ + horizontal_offset %= 256; \ + map_ptr = map_base + (horizontal_offset / 8); \ + second_ptr = map_base; \ + } \ + \ + if(bg_control & 0x80) \ + { \ + tile_render(8bpp, combine_op, alpha_op); \ + } \ + else \ + { \ + tile_render(4bpp, combine_op, alpha_op); \ + } \ +} \ + +render_scanline_text_builder(base, normal); +render_scanline_text_builder(transparent, normal); +render_scanline_text_builder(base, color16); +render_scanline_text_builder(transparent, color16); +render_scanline_text_builder(base, color32); +render_scanline_text_builder(transparent, color32); +render_scanline_text_builder(base, alpha); +render_scanline_text_builder(transparent, alpha); + + +s32 affine_reference_x[2]; +s32 affine_reference_y[2]; + +#define affine_render_bg_pixel_normal() \ + current_pixel = palette_ram_converted[0] \ + +#define affine_render_bg_pixel_alpha() \ + current_pixel = bg_combine \ + +#define affine_render_bg_pixel_color16() \ + affine_render_bg_pixel_alpha() \ + +#define affine_render_bg_pixel_color32() \ + affine_render_bg_pixel_alpha() \ + +#define affine_render_bg_pixel_base(alpha_op) \ + affine_render_bg_pixel_##alpha_op() \ + +#define affine_render_bg_pixel_transparent(alpha_op) \ + +#define affine_render_bg_pixel_copy(alpha_op) \ + +#define affine_render_bg_base(alpha_op) \ + dest_ptr[0] = current_pixel + +#define affine_render_bg_transparent(alpha_op) \ + +#define affine_render_bg_copy(alpha_op) \ + +#define affine_render_bg_remainder_base(alpha_op) \ + affine_render_bg_pixel_##alpha_op(); \ + for(; i < end; i++) \ + { \ + affine_render_bg_base(alpha_op); \ + advance_dest_ptr_base(1); \ + } \ + +#define affine_render_bg_remainder_transparent(alpha_op) \ + +#define affine_render_bg_remainder_copy(alpha_op) \ + +#define affine_render_next(combine_op) \ + source_x += dx; \ + source_y += dy; \ + advance_dest_ptr_##combine_op(1) \ + +#define affine_render_scale_offset() \ + tile_base += ((pixel_y % 8) * 8); \ + map_base += (pixel_y / 8) << map_pitch \ + +#define affine_render_scale_pixel(combine_op, alpha_op) \ + map_offset = (pixel_x / 8); \ + if(map_offset != last_map_offset) \ + { \ + tile_ptr = tile_base + (map_base[map_offset] * 64); \ + last_map_offset = map_offset; \ + } \ + tile_ptr = tile_base + (map_base[(pixel_x / 8)] * 64); \ + current_pixel = tile_ptr[(pixel_x % 8)]; \ + tile_8bpp_draw_##combine_op(0, none, 0, alpha_op); \ + affine_render_next(combine_op) \ + +#define affine_render_scale(combine_op, alpha_op) \ +{ \ + pixel_y = source_y >> 8; \ + u32 i = 0; \ + affine_render_bg_pixel_##combine_op(alpha_op); \ + if((u32)pixel_y < (u32)width_height) \ + { \ + affine_render_scale_offset(); \ + for(; i < end; i++) \ + { \ + pixel_x = source_x >> 8; \ + \ + if((u32)pixel_x < (u32)width_height) \ + { \ + break; \ + } \ + \ + affine_render_bg_##combine_op(alpha_op); \ + affine_render_next(combine_op); \ + } \ + \ + for(; i < end; i++) \ + { \ + pixel_x = source_x >> 8; \ + \ + if((u32)pixel_x >= (u32)width_height) \ + break; \ + \ + affine_render_scale_pixel(combine_op, alpha_op); \ + } \ + } \ + affine_render_bg_remainder_##combine_op(alpha_op); \ +} \ + +#define affine_render_scale_wrap(combine_op, alpha_op) \ +{ \ + u32 wrap_mask = width_height - 1; \ + pixel_y = (source_y >> 8) & wrap_mask; \ + if((u32)pixel_y < (u32)width_height) \ + { \ + affine_render_scale_offset(); \ + for(i = 0; i < end; i++) \ + { \ + pixel_x = (source_x >> 8) & wrap_mask; \ + affine_render_scale_pixel(combine_op, alpha_op); \ + } \ + } \ +} \ + + +#define affine_render_rotate_pixel(combine_op, alpha_op) \ + map_offset = (pixel_x / 8) + ((pixel_y / 8) << map_pitch); \ + if(map_offset != last_map_offset) \ + { \ + tile_ptr = tile_base + (map_base[map_offset] * 64); \ + last_map_offset = map_offset; \ + } \ + \ + current_pixel = tile_ptr[(pixel_x % 8) + ((pixel_y % 8) * 8)]; \ + tile_8bpp_draw_##combine_op(0, none, 0, alpha_op); \ + affine_render_next(combine_op) \ + +#define affine_render_rotate(combine_op, alpha_op) \ +{ \ + affine_render_bg_pixel_##combine_op(alpha_op); \ + for(i = 0; i < end; i++) \ + { \ + pixel_x = source_x >> 8; \ + pixel_y = source_y >> 8; \ + \ + if(((u32)pixel_x < (u32)width_height) && \ + ((u32)pixel_y < (u32)width_height)) \ + { \ + break; \ + } \ + affine_render_bg_##combine_op(alpha_op); \ + affine_render_next(combine_op); \ + } \ + \ + for(; i < end; i++) \ + { \ + pixel_x = source_x >> 8; \ + pixel_y = source_y >> 8; \ + \ + if(((u32)pixel_x >= (u32)width_height) || \ + ((u32)pixel_y >= (u32)width_height)) \ + { \ + affine_render_bg_remainder_##combine_op(alpha_op); \ + break; \ + } \ + \ + affine_render_rotate_pixel(combine_op, alpha_op); \ + } \ +} \ + +#define affine_render_rotate_wrap(combine_op, alpha_op) \ +{ \ + u32 wrap_mask = width_height - 1; \ + for(i = 0; i < end; i++) \ + { \ + pixel_x = (source_x >> 8) & wrap_mask; \ + pixel_y = (source_y >> 8) & wrap_mask; \ + \ + affine_render_rotate_pixel(combine_op, alpha_op); \ + } \ +} \ + + +// Build affine background renderers. + +#define render_scanline_affine_builder(combine_op, alpha_op) \ +void render_scanline_affine_##combine_op##_##alpha_op(u32 layer, \ + u32 start, u32 end, void *scanline) \ +{ \ + render_scanline_extra_variables_##combine_op##_##alpha_op(affine); \ + u32 bg_control = io_registers[REG_BG0CNT + layer]; \ + u32 current_pixel; \ + s32 source_x, source_y; \ + u32 vcount = io_registers[REG_VCOUNT]; \ + u32 pixel_x, pixel_y; \ + u32 layer_offset = (layer - 2) * 8; \ + s32 dx, dy; \ + u32 map_size = (bg_control >> 14) & 0x03; \ + u32 width_height = 1 << (7 + map_size); \ + u32 map_pitch = map_size + 4; \ + u8 *map_base = vram + (((bg_control >> 8) & 0x1F) * (1024 * 2)); \ + u8 *tile_base = vram + (((bg_control >> 2) & 0x03) * (1024 * 16)); \ + u8 *tile_ptr; \ + u32 map_offset, last_map_offset = (u32)-1; \ + u32 i; \ + render_scanline_dest_##alpha_op *dest_ptr = \ + ((render_scanline_dest_##alpha_op *)scanline) + start; \ + \ + dx = (s16)io_registers[REG_BG2PA + layer_offset]; \ + dy = (s16)io_registers[REG_BG2PC + layer_offset]; \ + source_x = affine_reference_x[layer - 2] + (start * dx); \ + source_y = affine_reference_y[layer - 2] + (start * dy); \ + \ + end -= start; \ + \ + switch(((bg_control >> 12) & 0x02) | (dy != 0)) \ + { \ + case 0x00: \ + affine_render_scale(combine_op, alpha_op); \ + break; \ + \ + case 0x01: \ + affine_render_rotate(combine_op, alpha_op); \ + break; \ + \ + case 0x02: \ + affine_render_scale_wrap(combine_op, alpha_op); \ + break; \ + \ + case 0x03: \ + affine_render_rotate_wrap(combine_op, alpha_op); \ + break; \ + } \ +} \ + +render_scanline_affine_builder(base, normal); +render_scanline_affine_builder(transparent, normal); +render_scanline_affine_builder(base, color16); +render_scanline_affine_builder(transparent, color16); +render_scanline_affine_builder(base, color32); +render_scanline_affine_builder(transparent, color32); +render_scanline_affine_builder(base, alpha); +render_scanline_affine_builder(transparent, alpha); + + +#define bitmap_render_pixel_mode3(alpha_op) \ + convert_palette(current_pixel); \ + *dest_ptr = current_pixel \ + +#define bitmap_render_pixel_mode4(alpha_op) \ + tile_expand_base_##alpha_op(0) \ + +#define bitmap_render_pixel_mode5(alpha_op) \ + bitmap_render_pixel_mode3(alpha_op) \ + + +#define bitmap_render_scale(type, alpha_op, width, height) \ + pixel_y = (source_y >> 8); \ + if((u32)pixel_y < (u32)height) \ + { \ + pixel_x = (source_x >> 8); \ + src_ptr += (pixel_y * width); \ + if(dx == 0x100) \ + { \ + if(pixel_x < 0) \ + { \ + end += pixel_x; \ + dest_ptr -= pixel_x; \ + pixel_x = 0; \ + } \ + else \ + \ + if(pixel_x > 0) \ + { \ + src_ptr += pixel_x; \ + } \ + \ + if((pixel_x + end) >= width) \ + end = (width - pixel_x); \ + \ + for(i = 0; (s32)i < (s32)end; i++) \ + { \ + current_pixel = *src_ptr; \ + bitmap_render_pixel_##type(alpha_op); \ + src_ptr++; \ + dest_ptr++; \ + } \ + } \ + else \ + { \ + if((u32)(source_y >> 8) < (u32)height) \ + { \ + for(i = 0; i < end; i++) \ + { \ + pixel_x = (source_x >> 8); \ + \ + if((u32)pixel_x < (u32)width) \ + break; \ + \ + source_x += dx; \ + dest_ptr++; \ + } \ + \ + for(; i < end; i++) \ + { \ + pixel_x = (source_x >> 8); \ + \ + if((u32)pixel_x >= (u32)width) \ + break; \ + \ + current_pixel = src_ptr[pixel_x]; \ + bitmap_render_pixel_##type(alpha_op); \ + \ + source_x += dx; \ + dest_ptr++; \ + } \ + } \ + } \ + } \ + +#define bitmap_render_rotate(type, alpha_op, width, height) \ + for(i = 0; i < end; i++) \ + { \ + pixel_x = source_x >> 8; \ + pixel_y = source_y >> 8; \ + \ + if(((u32)pixel_x < (u32)width) && ((u32)pixel_y < (u32)height)) \ + break; \ + \ + source_x += dx; \ + source_y += dy; \ + dest_ptr++; \ + } \ + \ + for(; i < end; i++) \ + { \ + pixel_x = (source_x >> 8); \ + pixel_y = (source_y >> 8); \ + \ + if(((u32)pixel_x >= (u32)width) || ((u32)pixel_y >= (u32)height)) \ + break; \ + \ + current_pixel = src_ptr[pixel_x + (pixel_y * width)]; \ + bitmap_render_pixel_##type(alpha_op); \ + \ + source_x += dx; \ + source_y += dy; \ + dest_ptr++; \ + } \ + + +#define render_scanline_vram_setup_mode3() \ + u16 *src_ptr = (u16 *)vram \ + +#define render_scanline_vram_setup_mode5() \ + u16 *src_ptr; \ + if(io_registers[REG_DISPCNT] & 0x10) \ + src_ptr = (u16 *)(vram + 0xA000); \ + else \ + src_ptr = (u16 *)vram \ + + +#ifdef RENDER_COLOR16_NORMAL + +#define render_scanline_vram_setup_mode4() \ + const u32 pixel_combine = 0; \ + u8 *src_ptr; \ + if(io_registers[REG_DISPCNT] & 0x10) \ + src_ptr = vram + 0xA000; \ + else \ + src_ptr = vram \ + + +#else + +#define render_scanline_vram_setup_mode4() \ + u16 *palette = palette_ram_converted; \ + u8 *src_ptr; \ + if(io_registers[REG_DISPCNT] & 0x10) \ + src_ptr = vram + 0xA000; \ + else \ + src_ptr = vram \ + +#endif + + + +// Build bitmap scanline rendering functions. + +#define render_scanline_bitmap_builder(type, alpha_op, width, height) \ +void render_scanline_bitmap_##type##_##alpha_op(u32 start, u32 end, \ + void *scanline) \ +{ \ + u32 bg_control = io_registers[REG_BG2CNT]; \ + u32 current_pixel; \ + s32 source_x, source_y; \ + u32 vcount = io_registers[REG_VCOUNT]; \ + s32 pixel_x, pixel_y; \ + \ + s32 dx = (s16)io_registers[REG_BG2PA]; \ + s32 dy = (s16)io_registers[REG_BG2PC]; \ + \ + u32 i; \ + \ + render_scanline_dest_##alpha_op *dest_ptr = \ + ((render_scanline_dest_##alpha_op *)scanline) + start; \ + render_scanline_vram_setup_##type(); \ + \ + end -= start; \ + \ + source_x = affine_reference_x[0] + (start * dx); \ + source_y = affine_reference_y[0] + (start * dy); \ + \ + if(dy == 0) \ + { \ + bitmap_render_scale(type, alpha_op, width, height); \ + } \ + else \ + { \ + bitmap_render_rotate(type, alpha_op, width, height); \ + } \ +} \ + +render_scanline_bitmap_builder(mode3, normal, 240, 160); +render_scanline_bitmap_builder(mode4, normal, 240, 160); +render_scanline_bitmap_builder(mode5, normal, 160, 128); + + +// Fill in the renderers for a layer based on the mode type, + +#define tile_layer_render_functions(type) \ +{ \ + render_scanline_##type##_base_normal, \ + render_scanline_##type##_transparent_normal, \ + render_scanline_##type##_base_alpha, \ + render_scanline_##type##_transparent_alpha, \ + render_scanline_##type##_base_color16, \ + render_scanline_##type##_transparent_color16, \ + render_scanline_##type##_base_color32, \ + render_scanline_##type##_transparent_color32 \ +} \ + + +// Use if a layer is unsupported for that mode. + +#define tile_layer_render_null() \ +{ \ + NULL, NULL, NULL, NULL \ +} \ + +#define bitmap_layer_render_functions(type) \ +{ \ + render_scanline_bitmap_##type##_normal \ +} \ + +// Structs containing functions to render the layers for each mode, for +// each render type. +tile_layer_render_struct tile_mode_renderers[3][4] = +{ + { + tile_layer_render_functions(text), tile_layer_render_functions(text), + tile_layer_render_functions(text), tile_layer_render_functions(text) + }, + { + tile_layer_render_functions(text), tile_layer_render_functions(text), + tile_layer_render_functions(affine), tile_layer_render_functions(text) + }, + { + tile_layer_render_functions(text), tile_layer_render_functions(text), + tile_layer_render_functions(affine), tile_layer_render_functions(affine) + } +}; + +bitmap_layer_render_struct bitmap_mode_renderers[3] = +{ + bitmap_layer_render_functions(mode3), + bitmap_layer_render_functions(mode4), + bitmap_layer_render_functions(mode5) +}; + + +#define render_scanline_layer_functions_tile() \ + tile_layer_render_struct *layer_renderers = \ + tile_mode_renderers[dispcnt & 0x07] \ + +#define render_scanline_layer_functions_bitmap() \ + bitmap_layer_render_struct *layer_renderers = \ + bitmap_mode_renderers + ((dispcnt & 0x07) - 3) \ + + +// Adjust a flipped obj's starting position + +#define obj_tile_offset_noflip(color_depth) \ + +#define obj_tile_offset_flip(color_depth) \ + + (tile_size_##color_depth * ((obj_width - 8) / 8)) \ + + +// Adjust the obj's starting point if it goes too far off the left edge of \ +// the screen. \ + +#define obj_tile_right_offset_noflip(color_depth) \ + tile_ptr += (partial_tile_offset / 8) * tile_size_##color_depth \ + +#define obj_tile_right_offset_flip(color_depth) \ + tile_ptr -= (partial_tile_offset / 8) * tile_size_##color_depth \ + +// Get the current row offset into an obj in 1D map space + +#define obj_tile_offset_1D(color_depth, flip_op) \ + tile_ptr = tile_base + ((obj_attribute_2 & 0x3FF) * 32) \ + + ((vertical_offset / 8) * (obj_width / 8) * tile_size_##color_depth) \ + + ((vertical_offset % 8) * tile_width_##color_depth) \ + obj_tile_offset_##flip_op(color_depth) \ + +// Get the current row offset into an obj in 2D map space + +#define obj_tile_offset_2D(color_depth, flip_op) \ + tile_ptr = tile_base + ((obj_attribute_2 & 0x3FF) * 32) \ + + ((vertical_offset / 8) * 1024) \ + + ((vertical_offset % 8) * tile_width_##color_depth) \ + obj_tile_offset_##flip_op(color_depth) \ + + +// Get the palette for 4bpp obj. + +#define obj_get_palette_4bpp() \ + current_palette = (obj_attribute_2 >> 8) & 0xF0 \ + +#define obj_get_palette_8bpp() \ + + +// Render the current row of an obj. + +#define obj_render(combine_op, color_depth, alpha_op, map_space, flip_op) \ +{ \ + obj_get_palette_##color_depth(); \ + obj_tile_offset_##map_space(color_depth, flip_op); \ + \ + if(obj_x < (s32)start) \ + { \ + dest_ptr = scanline + start; \ + pixel_run = obj_width - (start - obj_x); \ + if((s32)pixel_run > 0) \ + { \ + if((obj_x + obj_width) >= end) \ + { \ + pixel_run = end - start; \ + partial_tile_offset = start - obj_x; \ + obj_tile_right_offset_##flip_op(color_depth); \ + partial_tile_offset %= 8; \ + \ + if(partial_tile_offset) \ + { \ + partial_tile_run = 8 - partial_tile_offset; \ + if((s32)pixel_run < (s32)partial_tile_run) \ + { \ + if((s32)pixel_run > 0) \ + { \ + partial_tile_run = pixel_run; \ + partial_tile_mid_obj(combine_op, color_depth, alpha_op, \ + flip_op); \ + } \ + continue; \ + } \ + else \ + { \ + pixel_run -= partial_tile_run; \ + partial_tile_right_obj(combine_op, color_depth, alpha_op, \ + flip_op); \ + } \ + } \ + tile_run = pixel_run / 8; \ + multiple_tile_obj(combine_op, color_depth, alpha_op, flip_op); \ + partial_tile_run = pixel_run % 8; \ + if(partial_tile_run) \ + { \ + partial_tile_left_obj(combine_op, color_depth, alpha_op, \ + flip_op); \ + } \ + } \ + else \ + { \ + partial_tile_offset = start - obj_x; \ + obj_tile_right_offset_##flip_op(color_depth); \ + partial_tile_offset %= 8; \ + if(partial_tile_offset) \ + { \ + partial_tile_run = 8 - partial_tile_offset; \ + partial_tile_right_obj(combine_op, color_depth, alpha_op, \ + flip_op); \ + } \ + tile_run = pixel_run / 8; \ + multiple_tile_obj(combine_op, color_depth, alpha_op, flip_op); \ + } \ + } \ + } \ + else \ + \ + if((obj_x + obj_width) >= end) \ + { \ + pixel_run = end - obj_x; \ + if((s32)pixel_run > 0) \ + { \ + dest_ptr = scanline + obj_x; \ + tile_run = pixel_run / 8; \ + multiple_tile_obj(combine_op, color_depth, alpha_op, flip_op); \ + partial_tile_run = pixel_run % 8; \ + if(partial_tile_run) \ + { \ + partial_tile_left_obj(combine_op, color_depth, alpha_op, flip_op); \ + } \ + } \ + } \ + else \ + { \ + dest_ptr = scanline + obj_x; \ + tile_run = obj_width / 8; \ + multiple_tile_obj(combine_op, color_depth, alpha_op, flip_op); \ + } \ +} \ + +#define obj_scale_offset_1D(color_depth) \ + tile_ptr = tile_base + ((obj_attribute_2 & 0x3FF) * 32) \ + + ((vertical_offset / 8) * (max_x / 8) * tile_size_##color_depth) \ + + ((vertical_offset % 8) * tile_width_##color_depth) \ + +// Get the current row offset into an obj in 2D map space + +#define obj_scale_offset_2D(color_depth) \ + tile_ptr = tile_base + ((obj_attribute_2 & 0x3FF) * 32) \ + + ((vertical_offset / 8) * 1024) \ + + ((vertical_offset % 8) * tile_width_##color_depth) \ + +#define obj_render_scale_pixel_4bpp(combine_op, alpha_op) \ + if(tile_x & 0x01) \ + { \ + current_pixel = tile_ptr[tile_map_offset + ((tile_x >> 1) & 0x03)] >> 4; \ + } \ + else \ + { \ + current_pixel = \ + tile_ptr[tile_map_offset + ((tile_x >> 1) & 0x03)] & 0x0F; \ + } \ + \ + tile_4bpp_draw_##combine_op(0, none, 0, alpha_op) \ + + +#define obj_render_scale_pixel_8bpp(combine_op, alpha_op) \ + current_pixel = tile_ptr[tile_map_offset + (tile_x & 0x07)]; \ + tile_8bpp_draw_##combine_op(0, none, 0, alpha_op); \ + +#define obj_render_scale(combine_op, color_depth, alpha_op, map_space) \ +{ \ + u32 vertical_offset; \ + source_y += (y_delta * dmy); \ + vertical_offset = (source_y >> 8); \ + if((u32)vertical_offset < (u32)max_y) \ + { \ + obj_scale_offset_##map_space(color_depth); \ + source_x += (y_delta * dmx) - (middle_x * dx); \ + \ + for(i = 0; i < obj_width; i++) \ + { \ + tile_x = (source_x >> 8); \ + \ + if((u32)tile_x < (u32)max_x) \ + break; \ + \ + source_x += dx; \ + advance_dest_ptr_##combine_op(1); \ + } \ + \ + for(; i < obj_width; i++) \ + { \ + tile_x = (source_x >> 8); \ + \ + if((u32)tile_x >= (u32)max_x) \ + break; \ + \ + tile_map_offset = (tile_x >> 3) * tile_size_##color_depth; \ + obj_render_scale_pixel_##color_depth(combine_op, alpha_op); \ + \ + source_x += dx; \ + advance_dest_ptr_##combine_op(1); \ + } \ + } \ +} \ + + +#define obj_rotate_offset_1D(color_depth) \ + obj_tile_pitch = (max_x / 8) * tile_size_##color_depth \ + +#define obj_rotate_offset_2D(color_depth) \ + obj_tile_pitch = 1024 \ + +#define obj_render_rotate_pixel_4bpp(combine_op, alpha_op) \ + if(tile_x & 0x01) \ + { \ + current_pixel = tile_ptr[tile_map_offset + \ + ((tile_x >> 1) & 0x03) + ((tile_y & 0x07) * obj_pitch)] >> 4; \ + } \ + else \ + { \ + current_pixel = tile_ptr[tile_map_offset + \ + ((tile_x >> 1) & 0x03) + ((tile_y & 0x07) * obj_pitch)] & 0x0F; \ + } \ + \ + tile_4bpp_draw_##combine_op(0, none, 0, alpha_op) \ + +#define obj_render_rotate_pixel_8bpp(combine_op, alpha_op) \ + current_pixel = tile_ptr[tile_map_offset + \ + (tile_x & 0x07) + ((tile_y & 0x07) * obj_pitch)]; \ + \ + tile_8bpp_draw_##combine_op(0, none, 0, alpha_op) \ + +#define obj_render_rotate(combine_op, color_depth, alpha_op, map_space) \ +{ \ + tile_ptr = tile_base + ((obj_attribute_2 & 0x3FF) * 32); \ + obj_rotate_offset_##map_space(color_depth); \ + \ + source_x += (y_delta * dmx) - (middle_x * dx); \ + source_y += (y_delta * dmy) - (middle_x * dy); \ + \ + for(i = 0; i < obj_width; i++) \ + { \ + tile_x = (source_x >> 8); \ + tile_y = (source_y >> 8); \ + \ + if(((u32)tile_x < (u32)max_x) && ((u32)tile_y < (u32)max_y)) \ + break; \ + \ + source_x += dx; \ + source_y += dy; \ + advance_dest_ptr_##combine_op(1); \ + } \ + \ + for(; i < obj_width; i++) \ + { \ + tile_x = (source_x >> 8); \ + tile_y = (source_y >> 8); \ + \ + if(((u32)tile_x >= (u32)max_x) || ((u32)tile_y >= (u32)max_y)) \ + break; \ + \ + tile_map_offset = ((tile_x >> 3) * tile_size_##color_depth) + \ + ((tile_y >> 3) * obj_tile_pitch); \ + obj_render_rotate_pixel_##color_depth(combine_op, alpha_op); \ + \ + source_x += dx; \ + source_y += dy; \ + advance_dest_ptr_##combine_op(1); \ + } \ +} \ + +// Render the current row of an affine transformed OBJ. + +#define obj_render_affine(combine_op, color_depth, alpha_op, map_space) \ +{ \ + s16 *params = oam_ram + (((obj_attribute_1 >> 9) & 0x1F) * 16); \ + s32 dx = params[3]; \ + s32 dmx = params[7]; \ + s32 dy = params[11]; \ + s32 dmy = params[15]; \ + s32 source_x, source_y; \ + s32 tile_x, tile_y; \ + u32 tile_offset; \ + u32 tile_map_offset; \ + s32 middle_x; \ + s32 middle_y; \ + s32 max_x = obj_width; \ + s32 max_y = obj_height; \ + s32 y_delta; \ + u32 obj_pitch = tile_width_##color_depth; \ + u32 obj_tile_pitch; \ + \ + middle_x = (obj_width / 2); \ + middle_y = (obj_height / 2); \ + \ + source_x = (middle_x << 8); \ + source_y = (middle_y << 8); \ + \ + \ + if(obj_attribute_0 & 0x200) \ + { \ + obj_width *= 2; \ + obj_height *= 2; \ + middle_x *= 2; \ + middle_y *= 2; \ + } \ + \ + if((s32)obj_x < (s32)start) \ + { \ + u32 x_delta = start - obj_x; \ + middle_x -= x_delta; \ + obj_width -= x_delta; \ + obj_x = start; \ + \ + if((s32)obj_width <= 0) \ + continue; \ + } \ + \ + if((s32)(obj_x + obj_width) >= (s32)end) \ + { \ + obj_width = end - obj_x; \ + \ + if((s32)obj_width <= 0) \ + continue; \ + } \ + dest_ptr = scanline + obj_x; \ + \ + y_delta = vcount - (obj_y + middle_y); \ + \ + obj_get_palette_##color_depth(); \ + \ + if(dy == 0) \ + { \ + obj_render_scale(combine_op, color_depth, alpha_op, map_space); \ + } \ + else \ + { \ + obj_render_rotate(combine_op, color_depth, alpha_op, map_space); \ + } \ +} \ + +u32 obj_width_table[] = { 8, 16, 32, 64, 16, 32, 32, 64, 8, 8, 16, 32 }; +u32 obj_height_table[] = { 8, 16, 32, 64, 8, 8, 16, 32, 16, 32, 32, 64 }; + +u8 obj_priority_list[5][160][128]; +u32 obj_priority_count[5][160]; +u32 obj_alpha_count[160]; + + +// Build obj rendering functions + +#ifdef RENDER_COLOR16_NORMAL + +#define render_scanline_obj_extra_variables_normal(bg_type) \ + const u32 pixel_combine = (1 << 8) \ + +#else + +#define render_scanline_obj_extra_variables_normal(bg_type) \ + u16 *palette = palette_ram_converted + 256 \ + +#endif + + +#define render_scanline_obj_extra_variables_color() \ + u32 dest; \ + u32 pixel_combine = color_combine_mask(4) | (1 << 8) \ + +#define render_scanline_obj_extra_variables_alpha_obj(map_space) \ + render_scanline_obj_extra_variables_color(); \ + if((pixel_combine & 0x00000200) == 0) \ + { \ + render_scanline_obj_color32_##map_space(priority, start, end, scanline); \ + return; \ + } \ + +#define render_scanline_obj_extra_variables_color16(map_space) \ + render_scanline_obj_extra_variables_color() \ + +#define render_scanline_obj_extra_variables_color32(map_space) \ + render_scanline_obj_extra_variables_color() \ + +#define render_scanline_obj_extra_variables_partial_alpha(map_space) \ + render_scanline_obj_extra_variables_color(); \ + u32 base_pixel_combine = pixel_combine \ + +#define render_scanline_obj_extra_variables_copy(type) \ + u32 bldcnt = io_registers[REG_BLDCNT]; \ + u32 dispcnt = io_registers[REG_DISPCNT]; \ + u32 obj_enable = io_registers[REG_WINOUT] >> 8; \ + render_scanline_layer_functions_##type(); \ + u32 copy_start, copy_end; \ + u16 copy_buffer[240]; \ + u16 *copy_ptr \ + +#define render_scanline_obj_extra_variables_copy_tile(map_space) \ + render_scanline_obj_extra_variables_copy(tile) \ + +#define render_scanline_obj_extra_variables_copy_bitmap(map_space) \ + render_scanline_obj_extra_variables_copy(bitmap) \ + + +#define render_scanline_obj_main(combine_op, alpha_op, map_space) \ + if(obj_attribute_0 & 0x100) \ + { \ + if((obj_attribute_0 >> 13) & 0x01) \ + { \ + obj_render_affine(combine_op, 8bpp, alpha_op, map_space); \ + } \ + else \ + { \ + obj_render_affine(combine_op, 4bpp, alpha_op, map_space); \ + } \ + } \ + else \ + { \ + vertical_offset = vcount - obj_y; \ + \ + if((obj_attribute_1 >> 13) & 0x01) \ + vertical_offset = obj_height - vertical_offset - 1; \ + \ + switch(((obj_attribute_0 >> 12) & 0x02) | \ + ((obj_attribute_1 >> 12) & 0x01)) \ + { \ + case 0x0: \ + obj_render(combine_op, 4bpp, alpha_op, map_space, noflip); \ + break; \ + \ + case 0x1: \ + obj_render(combine_op, 4bpp, alpha_op, map_space, flip); \ + break; \ + \ + case 0x2: \ + obj_render(combine_op, 8bpp, alpha_op, map_space, noflip); \ + break; \ + \ + case 0x3: \ + obj_render(combine_op, 8bpp, alpha_op, map_space, flip); \ + break; \ + } \ + } \ + +#define render_scanline_obj_no_partial_alpha(combine_op, alpha_op, map_space) \ + render_scanline_obj_main(combine_op, alpha_op, map_space) \ + +#define render_scanline_obj_partial_alpha(combine_op, alpha_op, map_space) \ + if((obj_attribute_0 >> 10) & 0x03) \ + { \ + pixel_combine = 0x00000300; \ + render_scanline_obj_main(combine_op, alpha_obj, map_space); \ + } \ + else \ + { \ + pixel_combine = base_pixel_combine; \ + render_scanline_obj_main(combine_op, color32, map_space); \ + } \ + +#define render_scanline_obj_prologue_transparent(alpha_op) \ + +#define render_scanline_obj_prologue_copy_body(type) \ + copy_start = obj_x; \ + if(obj_attribute_0 & 0x200) \ + copy_end = obj_x + (obj_width * 2); \ + else \ + copy_end = obj_x + obj_width; \ + \ + if(copy_start < start) \ + copy_start = start; \ + if(copy_end > end) \ + copy_end = end; \ + \ + if((copy_start < end) && (copy_end > start)) \ + { \ + render_scanline_conditional_##type(copy_start, copy_end, copy_buffer, \ + obj_enable, dispcnt, bldcnt, layer_renderers); \ + copy_ptr = copy_buffer + copy_start; \ + } \ + else \ + { \ + continue; \ + } \ + +#define render_scanline_obj_prologue_copy_tile() \ + render_scanline_obj_prologue_copy_body(tile) \ + +#define render_scanline_obj_prologue_copy_bitmap() \ + render_scanline_obj_prologue_copy_body(bitmap) \ + +#define render_scanline_obj_prologue_copy(alpha_op) \ + render_scanline_obj_prologue_##alpha_op() \ + + +#define render_scanline_obj_builder(combine_op, alpha_op, map_space, \ + partial_alpha_op) \ +void render_scanline_obj_##alpha_op##_##map_space(u32 priority, \ + u32 start, u32 end, render_scanline_dest_##alpha_op *scanline) \ +{ \ + render_scanline_obj_extra_variables_##alpha_op(map_space); \ + s32 obj_num, i; \ + s32 obj_x, obj_y; \ + s32 obj_size; \ + s32 obj_width, obj_height; \ + u32 obj_attribute_0, obj_attribute_1, obj_attribute_2; \ + s32 vcount = io_registers[REG_VCOUNT]; \ + u32 tile_run; \ + u32 current_pixels; \ + u32 current_pixel; \ + u32 current_palette; \ + u32 vertical_offset; \ + u32 partial_tile_run, partial_tile_offset; \ + u32 pixel_run; \ + u16 *oam_ptr; \ + render_scanline_dest_##alpha_op *dest_ptr; \ + u8 *tile_base = vram + 0x10000; \ + u8 *tile_ptr; \ + u32 obj_count = obj_priority_count[priority][vcount]; \ + u8 *obj_list = obj_priority_list[priority][vcount]; \ + \ + for(obj_num = 0; obj_num < obj_count; obj_num++) \ + { \ + oam_ptr = oam_ram + (obj_list[obj_num] * 4); \ + obj_attribute_0 = oam_ptr[0]; \ + obj_attribute_1 = oam_ptr[1]; \ + obj_attribute_2 = oam_ptr[2]; \ + obj_size = ((obj_attribute_0 >> 12) & 0x0C) | (obj_attribute_1 >> 14); \ + \ + obj_x = (s32)(obj_attribute_1 << 23) >> 23; \ + obj_width = obj_width_table[obj_size]; \ + \ + render_scanline_obj_prologue_##combine_op(alpha_op); \ + \ + obj_y = obj_attribute_0 & 0xFF; \ + \ + if(obj_y > 160) \ + obj_y -= 256; \ + \ + obj_height = obj_height_table[obj_size]; \ + render_scanline_obj_##partial_alpha_op(combine_op, alpha_op, map_space); \ + } \ +} \ + +render_scanline_obj_builder(transparent, normal, 1D, no_partial_alpha); +render_scanline_obj_builder(transparent, normal, 2D, no_partial_alpha); +render_scanline_obj_builder(transparent, color16, 1D, no_partial_alpha); +render_scanline_obj_builder(transparent, color16, 2D, no_partial_alpha); +render_scanline_obj_builder(transparent, color32, 1D, no_partial_alpha); +render_scanline_obj_builder(transparent, color32, 2D, no_partial_alpha); +render_scanline_obj_builder(transparent, alpha_obj, 1D, no_partial_alpha); +render_scanline_obj_builder(transparent, alpha_obj, 2D, no_partial_alpha); +render_scanline_obj_builder(transparent, partial_alpha, 1D, partial_alpha); +render_scanline_obj_builder(transparent, partial_alpha, 2D, partial_alpha); +render_scanline_obj_builder(copy, copy_tile, 1D, no_partial_alpha); +render_scanline_obj_builder(copy, copy_tile, 2D, no_partial_alpha); +render_scanline_obj_builder(copy, copy_bitmap, 1D, no_partial_alpha); +render_scanline_obj_builder(copy, copy_bitmap, 2D, no_partial_alpha); + + + +void order_obj(u32 video_mode) +{ + s32 obj_num, priority, row; + s32 obj_x, obj_y; + s32 obj_size, obj_mode; + s32 obj_width, obj_height; + u32 obj_priority; + u32 obj_attribute_0, obj_attribute_1, obj_attribute_2; + s32 vcount = io_registers[REG_VCOUNT]; + u32 partial_tile_run, partial_tile_offset; + u32 pixel_run; + u32 current_count; + u16 *oam_ptr = oam_ram + 508; + u16 *dest_ptr; + u8 *tile_base = vram + 0x10000; + u8 *tile_ptr; + + for(priority = 0; priority < 5; priority++) + { + for(row = 0; row < 160; row++) + { + obj_priority_count[priority][row] = 0; + } + } + + for(row = 0; row < 160; row++) + { + obj_alpha_count[row] = 0; + } + + for(obj_num = 127; obj_num >= 0; obj_num--, oam_ptr -= 4) + { + obj_attribute_0 = oam_ptr[0]; + obj_attribute_2 = oam_ptr[2]; + obj_size = obj_attribute_0 & 0xC000; + obj_priority = (obj_attribute_2 >> 10) & 0x03; + obj_mode = (obj_attribute_0 >> 10) & 0x03; + + if(((obj_attribute_0 & 0x0300) != 0x0200) && (obj_size != 0xC000) && + (obj_mode != 3) && ((video_mode < 3) || + ((obj_attribute_2 & 0x3FF) >= 512))) + { + obj_y = obj_attribute_0 & 0xFF; + if(obj_y > 160) + obj_y -= 256; + + obj_attribute_1 = oam_ptr[1]; + obj_size = ((obj_size >> 12) & 0x0C) | (obj_attribute_1 >> 14); + obj_height = obj_height_table[obj_size]; + obj_width = obj_width_table[obj_size]; + + if(obj_attribute_0 & 0x200) + { + obj_height *= 2; + obj_width *= 2; + } + + if(((obj_y + obj_height) > 0) && (obj_y < 160)) + { + obj_x = (s32)(obj_attribute_1 << 23) >> 23; + + if(((obj_x + obj_width) > 0) && (obj_x < 240)) + { + if(obj_y < 0) + { + obj_height += obj_y; + obj_y = 0; + } + + if((obj_y + obj_height) >= 160) + { + obj_height = 160 - obj_y; + } + + if(obj_mode == 1) + { + for(row = obj_y; row < obj_y + obj_height; row++) + { + current_count = obj_priority_count[obj_priority][row]; + obj_priority_list[obj_priority][row][current_count] = obj_num; + obj_priority_count[obj_priority][row] = current_count + 1; + obj_alpha_count[row]++; + } + } + else + { + if(obj_mode == 2) + { + obj_priority = 4; + } + + for(row = obj_y; row < obj_y + obj_height; row++) + { + current_count = obj_priority_count[obj_priority][row]; + obj_priority_list[obj_priority][row][current_count] = obj_num; + obj_priority_count[obj_priority][row] = current_count + 1; + } + } + } + } + } + } +} + +u32 layer_order[16]; +u32 layer_count; + +u32 order_layers(u32 layer_flags) +{ + s32 priority, layer_number; + layer_count = 0; + + for(priority = 3; priority >= 0; priority--) + { + for(layer_number = 3; layer_number >= 0; layer_number--) + { + if(((layer_flags >> layer_number) & 1) && + ((io_registers[REG_BG0CNT + layer_number] & 0x03) == priority)) + { + layer_order[layer_count] = layer_number; + layer_count++; + } + } + + if((obj_priority_count[priority][io_registers[REG_VCOUNT]] > 0) + && (layer_flags & 0x10)) + { + layer_order[layer_count] = priority | 0x04; + layer_count++; + } + } +} + +#define fill_line(_start, _end) \ + u32 i; \ + \ + for(i = _start; i < _end; i++) \ + { \ + dest_ptr[i] = color; \ + } \ + + +#define fill_line_color_normal() \ + color = palette_ram_converted[color] \ + +#define fill_line_color_alpha() \ + +#define fill_line_color_color16() \ + +#define fill_line_color_color32() \ + +#define fill_line_builder(type) \ +void fill_line_##type(u16 color, render_scanline_dest_##type *dest_ptr, \ + u32 start, u32 end) \ +{ \ + fill_line_color_##type(); \ + fill_line(start, end); \ +} \ + +fill_line_builder(normal); +fill_line_builder(alpha); +fill_line_builder(color16); +fill_line_builder(color32); + + +// Alpha blend two pixels (pixel_top and pixel_bottom). + +#define blend_pixel() \ + pixel_bottom = palette_ram_converted[(pixel_pair >> 16) & 0x1FF]; \ + pixel_bottom = (pixel_bottom | (pixel_bottom << 16)) & 0x07E0F81F; \ + pixel_top = ((pixel_top * blend_a) + (pixel_bottom * blend_b)) >> 4 \ + + +// Alpha blend two pixels, allowing for saturation (individual channels > 31). +// The operation is optimized towards saturation not occuring. + +#define blend_saturate_pixel() \ + pixel_bottom = palette_ram_converted[(pixel_pair >> 16) & 0x1FF]; \ + pixel_bottom = (pixel_bottom | (pixel_bottom << 16)) & 0x07E0F81F; \ + pixel_top = ((pixel_top * blend_a) + (pixel_bottom * blend_b)) >> 4; \ + if(pixel_top & 0x08010020) \ + { \ + if(pixel_top & 0x08000000) \ + pixel_top |= 0x07E00000; \ + \ + if(pixel_top & 0x00010000) \ + pixel_top |= 0x0000F800; \ + \ + if(pixel_top & 0x00000020) \ + pixel_top |= 0x0000001F; \ + } \ + +#define brighten_pixel() \ + pixel_top = upper + ((pixel_top * blend) >> 4); \ + +#define darken_pixel() \ + pixel_top = (pixel_top * blend) >> 4; \ + +#define effect_condition_alpha \ + ((pixel_pair & 0x04000200) == 0x04000200) \ + +#define effect_condition_fade(pixel_source) \ + ((pixel_source & 0x00000200) == 0x00000200) \ + +#define expand_pixel_no_dest(expand_type, pixel_source) \ + pixel_top = (pixel_top | (pixel_top << 16)) & 0x07E0F81F; \ + expand_type##_pixel(); \ + pixel_top &= 0x07E0F81F; \ + pixel_top = (pixel_top >> 16) | pixel_top \ + +#define expand_pixel(expand_type, pixel_source) \ + pixel_top = palette_ram_converted[pixel_source & 0x1FF]; \ + expand_pixel_no_dest(expand_type, pixel_source); \ + *screen_dest_ptr = pixel_top \ + +#define expand_loop(expand_type, effect_condition, pixel_source) \ + screen_src_ptr += start; \ + screen_dest_ptr += start; \ + \ + end -= start; \ + \ + for(i = 0; i < end; i++) \ + { \ + pixel_source = *screen_src_ptr; \ + if(effect_condition) \ + { \ + expand_pixel(expand_type, pixel_source); \ + } \ + else \ + { \ + *screen_dest_ptr = \ + palette_ram_converted[pixel_source & 0x1FF]; \ + } \ + \ + screen_src_ptr++; \ + screen_dest_ptr++; \ + } \ + + +#define expand_loop_partial_alpha(alpha_expand, expand_type) \ + screen_src_ptr += start; \ + screen_dest_ptr += start; \ + \ + end -= start; \ + \ + for(i = 0; i < end; i++) \ + { \ + pixel_pair = *screen_src_ptr; \ + if(effect_condition_fade(pixel_pair)) \ + { \ + if(effect_condition_alpha) \ + { \ + expand_pixel(alpha_expand, pixel_pair); \ + } \ + else \ + { \ + expand_pixel(expand_type, pixel_pair); \ + } \ + } \ + else \ + { \ + *screen_dest_ptr = \ + palette_ram_converted[pixel_pair & 0x1FF]; \ + } \ + \ + screen_src_ptr++; \ + screen_dest_ptr++; \ + } \ + + +#define expand_partial_alpha(expand_type) \ + if((blend_a + blend_b) > 16) \ + { \ + expand_loop_partial_alpha(blend_saturate, expand_type); \ + } \ + else \ + { \ + expand_loop_partial_alpha(blend, expand_type); \ + } \ + + + +// Blend top two pixels of scanline with each other. + +#ifdef RENDER_COLOR16_NORMAL + +#ifndef GP2X_BUILD + +void expand_normal(u16 *screen_ptr, u32 start, u32 end) +{ + u32 i, pixel_source; + screen_ptr += start; + + return; + + end -= start; + + for(i = 0; i < end; i++) + { + pixel_source = *screen_ptr; + *screen_ptr = palette_ram_converted[pixel_source]; + + screen_ptr++; + } +} + +#endif + +#else + +#define expand_normal(screen_ptr, start, end) + +#endif + + +#ifndef GP2X_BUILD + +void expand_blend(u32 *screen_src_ptr, u16 *screen_dest_ptr, + u32 start, u32 end) +{ + u32 pixel_pair; + u32 pixel_top, pixel_bottom; + u32 bldalpha = io_registers[REG_BLDALPHA]; + u32 blend_a = bldalpha & 0x1F; + u32 blend_b = (bldalpha >> 8) & 0x1F; + u32 i; + + if(blend_a > 16) + blend_a = 16; + + if(blend_b > 16) + blend_b = 16; + + // The individual colors can saturate over 31, this should be taken + // care of in an alternate pass as it incurs a huge additional speedhit. + if((blend_a + blend_b) > 16) + { + expand_loop(blend_saturate, effect_condition_alpha, pixel_pair); + } + else + { + expand_loop(blend, effect_condition_alpha, pixel_pair); + } +} + +#endif + +// Blend scanline with white. + +void expand_darken(u16 *screen_src_ptr, u16 *screen_dest_ptr, + u32 start, u32 end) +{ + u32 pixel_top; + s32 blend = 16 - (io_registers[REG_BLDY] & 0x1F); + u32 i; + + if(blend < 0) + blend = 0; + + expand_loop(darken, effect_condition_fade(pixel_top), pixel_top); +} + + +// Blend scanline with black. + +void expand_brighten(u16 *screen_src_ptr, u16 *screen_dest_ptr, + u32 start, u32 end) +{ + u32 pixel_top; + u32 blend = io_registers[REG_BLDY] & 0x1F; + u32 upper; + u32 i; + + if(blend > 16) + blend = 16; + + upper = ((0x07E0F81F * blend) >> 4) & 0x07E0F81F; + blend = 16 - blend; + + expand_loop(brighten, effect_condition_fade(pixel_top), pixel_top); + +} + + +// Expand scanline such that if both top and bottom pass it's alpha, +// if only top passes it's as specified, and if neither pass it's normal. + +void expand_darken_partial_alpha(u32 *screen_src_ptr, u16 *screen_dest_ptr, + u32 start, u32 end) +{ + s32 blend = 16 - (io_registers[REG_BLDY] & 0x1F); + u32 pixel_pair; + u32 pixel_top, pixel_bottom; + u32 bldalpha = io_registers[REG_BLDALPHA]; + u32 blend_a = bldalpha & 0x1F; + u32 blend_b = (bldalpha >> 8) & 0x1F; + u32 i; + + if(blend < 0) + blend = 0; + + if(blend_a > 16) + blend_a = 16; + + if(blend_b > 16) + blend_b = 16; + + expand_partial_alpha(darken); +} + + +void expand_brighten_partial_alpha(u32 *screen_src_ptr, u16 *screen_dest_ptr, + u32 start, u32 end) +{ + s32 blend = io_registers[REG_BLDY] & 0x1F; + u32 pixel_pair; + u32 pixel_top, pixel_bottom; + u32 bldalpha = io_registers[REG_BLDALPHA]; + u32 blend_a = bldalpha & 0x1F; + u32 blend_b = (bldalpha >> 8) & 0x1F; + u32 upper; + u32 i; + + if(blend > 16) + blend = 16; + + upper = ((0x07E0F81F * blend) >> 4) & 0x07E0F81F; + blend = 16 - blend; + + if(blend_a > 16) + blend_a = 16; + + if(blend_b > 16) + blend_b = 16; + + expand_partial_alpha(brighten); +} + + +// Render an OBJ layer from start to end, depending on the type (1D or 2D) +// stored in dispcnt. + +#define render_obj_layer(type, dest, _start, _end) \ + current_layer &= ~0x04; \ + if(dispcnt & 0x40) \ + render_scanline_obj_##type##_1D(current_layer, _start, _end, dest); \ + else \ + render_scanline_obj_##type##_2D(current_layer, _start, _end, dest) \ + + +// Render a target all the way with the background color as taken from the +// palette. + +#define fill_line_bg(type, dest, _start, _end) \ + fill_line_##type(0, dest, _start, _end) \ + + +// Render all layers as they appear in the layer order. + +#define render_layers(tile_alpha, obj_alpha, dest) \ +{ \ + current_layer = layer_order[0]; \ + if(current_layer & 0x04) \ + { \ + /* If the first one is OBJ render the background then render it. */ \ + fill_line_bg(tile_alpha, dest, 0, 240); \ + render_obj_layer(obj_alpha, dest, 0, 240); \ + } \ + else \ + { \ + /* Otherwise render a base layer. */ \ + layer_renderers[current_layer].tile_alpha##_render_base(current_layer, \ + 0, 240, dest); \ + } \ + \ + /* Render the rest of the layers. */ \ + for(layer_order_pos = 1; layer_order_pos < layer_count; layer_order_pos++) \ + { \ + current_layer = layer_order[layer_order_pos]; \ + if(current_layer & 0x04) \ + { \ + render_obj_layer(obj_alpha, dest, 0, 240); \ + } \ + else \ + { \ + layer_renderers[current_layer]. \ + tile_alpha##_render_transparent(current_layer, 0, 240, dest); \ + } \ + } \ +} \ + +#define render_condition_alpha \ + (((io_registers[REG_BLDALPHA] & 0x1F1F) != 0x001F) && \ + ((io_registers[REG_BLDCNT] & 0x3F) != 0) && \ + ((io_registers[REG_BLDCNT] & 0x3F00) != 0)) \ + +#define render_condition_fade \ + (((io_registers[REG_BLDY] & 0x1F) != 0) && \ + ((io_registers[REG_BLDCNT] & 0x3F) != 0)) \ + +#define render_layers_color_effect(renderer, layer_condition, \ + alpha_condition, fade_condition, _start, _end) \ +{ \ + if(layer_condition) \ + { \ + if(obj_alpha_count[io_registers[REG_VCOUNT]] > 0) \ + { \ + /* Render based on special effects mode. */ \ + u32 screen_buffer[240]; \ + switch((bldcnt >> 6) & 0x03) \ + { \ + /* Alpha blend */ \ + case 0x01: \ + { \ + if(alpha_condition) \ + { \ + renderer(alpha, alpha_obj, screen_buffer); \ + expand_blend(screen_buffer, scanline, _start, _end); \ + return; \ + } \ + break; \ + } \ + \ + /* Fade to white */ \ + case 0x02: \ + { \ + if(fade_condition) \ + { \ + renderer(color32, partial_alpha, screen_buffer); \ + expand_brighten_partial_alpha(screen_buffer, scanline, \ + _start, _end); \ + return; \ + } \ + break; \ + } \ + \ + /* Fade to black */ \ + case 0x03: \ + { \ + if(fade_condition) \ + { \ + renderer(color32, partial_alpha, screen_buffer); \ + expand_darken_partial_alpha(screen_buffer, scanline, \ + _start, _end); \ + return; \ + } \ + break; \ + } \ + } \ + \ + renderer(color32, partial_alpha, screen_buffer); \ + expand_blend(screen_buffer, scanline, _start, _end); \ + } \ + else \ + { \ + /* Render based on special effects mode. */ \ + switch((bldcnt >> 6) & 0x03) \ + { \ + /* Alpha blend */ \ + case 0x01: \ + { \ + if(alpha_condition) \ + { \ + u32 screen_buffer[240]; \ + renderer(alpha, alpha_obj, screen_buffer); \ + expand_blend(screen_buffer, scanline, _start, _end); \ + return; \ + } \ + break; \ + } \ + \ + /* Fade to white */ \ + case 0x02: \ + { \ + if(fade_condition) \ + { \ + renderer(color16, color16, scanline); \ + expand_brighten(scanline, scanline, _start, _end); \ + return; \ + } \ + break; \ + } \ + \ + /* Fade to black */ \ + case 0x03: \ + { \ + if(fade_condition) \ + { \ + renderer(color16, color16, scanline); \ + expand_darken(scanline, scanline, _start, _end); \ + return; \ + } \ + break; \ + } \ + } \ + \ + renderer(normal, normal, scanline); \ + expand_normal(scanline, _start, _end); \ + } \ + } \ + else \ + { \ + u32 pixel_top = palette_ram_converted[0]; \ + switch((bldcnt >> 6) & 0x03) \ + { \ + /* Fade to white */ \ + case 0x02: \ + { \ + if(color_combine_mask_a(5)) \ + { \ + u32 blend = io_registers[REG_BLDY] & 0x1F; \ + u32 upper; \ + \ + if(blend > 16) \ + blend = 16; \ + \ + upper = ((0x07E0F81F * blend) >> 4) & 0x07E0F81F; \ + blend = 16 - blend; \ + \ + expand_pixel_no_dest(brighten, pixel_top); \ + } \ + break; \ + } \ + \ + /* Fade to black */ \ + case 0x03: \ + { \ + if(color_combine_mask_a(5)) \ + { \ + s32 blend = 16 - (io_registers[REG_BLDY] & 0x1F); \ + \ + if(blend < 0) \ + blend = 0; \ + \ + expand_pixel_no_dest(darken, pixel_top); \ + } \ + break; \ + } \ + } \ + fill_line_color16(pixel_top, scanline, _start, _end); \ + } \ +} \ + + +// Renders an entire scanline from 0 to 240, based on current color mode. + +void render_scanline_tile(u16 *scanline, u32 dispcnt) +{ + u32 current_layer; + u32 layer_order_pos; + u32 bldcnt = io_registers[REG_BLDCNT]; + render_scanline_layer_functions_tile(); + + render_layers_color_effect(render_layers, layer_count, + render_condition_alpha, render_condition_fade, 0, 240); +} + +void render_scanline_bitmap(u16 *scanline, u32 dispcnt) +{ + u32 bldcnt = io_registers[REG_BLDCNT]; + render_scanline_layer_functions_bitmap(); + u32 current_layer; + u32 layer_order_pos; + + fill_line_bg(normal, scanline, 0, 240); + + for(layer_order_pos = 0; layer_order_pos < layer_count; layer_order_pos++) + { + current_layer = layer_order[layer_order_pos]; + if(current_layer & 0x04) + { + render_obj_layer(normal, scanline, 0, 240); + } + else + { + layer_renderers->normal_render(0, 240, scanline); + } + } +} + +// Render layers from start to end based on if they're allowed in the +// enable flags. + +#define render_layers_conditional(tile_alpha, obj_alpha, dest) \ +{ \ + __label__ skip; \ + current_layer = layer_order[layer_order_pos]; \ + /* If OBJ aren't enabled skip to the first non-OBJ layer */ \ + if(!(enable_flags & 0x10)) \ + { \ + while((current_layer & 0x04) || !((1 << current_layer) & enable_flags)) \ + { \ + layer_order_pos++; \ + current_layer = layer_order[layer_order_pos]; \ + \ + /* Oops, ran out of layers, render the background. */ \ + if(layer_order_pos == layer_count) \ + { \ + fill_line_bg(tile_alpha, dest, start, end); \ + goto skip; \ + } \ + } \ + \ + /* Render the first valid layer */ \ + layer_renderers[current_layer].tile_alpha##_render_base(current_layer, \ + start, end, dest); \ + \ + layer_order_pos++; \ + \ + /* Render the rest of the layers if active, skipping OBJ ones. */ \ + for(; layer_order_pos < layer_count; layer_order_pos++) \ + { \ + current_layer = layer_order[layer_order_pos]; \ + if(!(current_layer & 0x04) && ((1 << current_layer) & enable_flags)) \ + { \ + layer_renderers[current_layer]. \ + tile_alpha##_render_transparent(current_layer, start, end, dest); \ + } \ + } \ + } \ + else \ + { \ + /* Find the first active layer, skip all of the inactive ones */ \ + while(!((current_layer & 0x04) || ((1 << current_layer) & enable_flags))) \ + { \ + layer_order_pos++; \ + current_layer = layer_order[layer_order_pos]; \ + \ + /* Oops, ran out of layers, render the background. */ \ + if(layer_order_pos == layer_count) \ + { \ + fill_line_bg(tile_alpha, dest, start, end); \ + goto skip; \ + } \ + } \ + \ + if(current_layer & 0x04) \ + { \ + /* If the first one is OBJ render the background then render it. */ \ + fill_line_bg(tile_alpha, dest, start, end); \ + render_obj_layer(obj_alpha, dest, start, end); \ + } \ + else \ + { \ + /* Otherwise render a base layer. */ \ + layer_renderers[current_layer]. \ + tile_alpha##_render_base(current_layer, start, end, dest); \ + } \ + \ + layer_order_pos++; \ + \ + /* Render the rest of the layers. */ \ + for(; layer_order_pos < layer_count; layer_order_pos++) \ + { \ + current_layer = layer_order[layer_order_pos]; \ + if(current_layer & 0x04) \ + { \ + render_obj_layer(obj_alpha, dest, start, end); \ + } \ + else \ + { \ + if(enable_flags & (1 << current_layer)) \ + { \ + layer_renderers[current_layer]. \ + tile_alpha##_render_transparent(current_layer, start, end, dest); \ + } \ + } \ + } \ + } \ + \ + skip: \ + ; \ +} \ + + +// Render all of the BG and OBJ in a tiled scanline from start to end ONLY if +// enable_flag allows that layer/OBJ. Also conditionally render color effects. + +void render_scanline_conditional_tile(u32 start, u32 end, u16 *scanline, + u32 enable_flags, u32 dispcnt, u32 bldcnt, tile_layer_render_struct + *layer_renderers) +{ + u32 current_layer; + u32 layer_order_pos = 0; + + render_layers_color_effect(render_layers_conditional, + (layer_count && (enable_flags & 0x1F)), + ((enable_flags & 0x20) && render_condition_alpha), + ((enable_flags & 0x20) && render_condition_fade), start, end); +} + + +// Render the BG and OBJ in a bitmap scanline from start to end ONLY if +// enable_flag allows that layer/OBJ. Also conditionally render color effects. + +void render_scanline_conditional_bitmap(u32 start, u32 end, u16 *scanline, + u32 enable_flags, u32 dispcnt, u32 bldcnt, bitmap_layer_render_struct + *layer_renderers) +{ + u32 current_layer; + u32 layer_order_pos; + + fill_line_bg(normal, scanline, start, end); + + for(layer_order_pos = 0; layer_order_pos < layer_count; layer_order_pos++) + { + current_layer = layer_order[layer_order_pos]; + if(current_layer & 0x04) + { + if(enable_flags & 0x10) + { + render_obj_layer(normal, scanline, start, end); + } + } + else + { + if(enable_flags & 0x04) + layer_renderers->normal_render(start, end, scanline); + } + } +} + + +#define window_x_coords(window_number) \ + window_##window_number##_x1 = \ + io_registers[REG_WIN##window_number##H] >> 8; \ + window_##window_number##_x2 = \ + io_registers[REG_WIN##window_number##H] & 0xFF; \ + window_##window_number##_enable = \ + (winin >> (window_number * 8)) & 0x3F; \ + \ + if(window_##window_number##_x1 > 240) \ + window_##window_number##_x1 = 240; \ + \ + if(window_##window_number##_x2 > 240) \ + window_##window_number##_x2 = 240 \ + +#define window_coords(window_number) \ + u32 window_##window_number##_x1, window_##window_number##_x2; \ + u32 window_##window_number##_y1, window_##window_number##_y2; \ + u32 window_##window_number##_enable; \ + window_##window_number##_y1 = \ + io_registers[REG_WIN##window_number##V] >> 8; \ + window_##window_number##_y2 = \ + io_registers[REG_WIN##window_number##V] & 0xFF; \ + \ + if(window_##window_number##_y1 > window_##window_number##_y2) \ + { \ + if((((vcount <= window_##window_number##_y2) || \ + (vcount > window_##window_number##_y1)) || \ + (window_##window_number##_y2 > 227)) && \ + (window_##window_number##_y1 <= 227)) \ + { \ + window_x_coords(window_number); \ + } \ + else \ + { \ + window_##window_number##_x1 = 240; \ + window_##window_number##_x2 = 240; \ + } \ + } \ + else \ + { \ + if((((vcount >= window_##window_number##_y1) && \ + (vcount < window_##window_number##_y2)) || \ + (window_##window_number##_y2 > 227)) && \ + (window_##window_number##_y1 <= 227)) \ + { \ + window_x_coords(window_number); \ + } \ + else \ + { \ + window_##window_number##_x1 = 240; \ + window_##window_number##_x2 = 240; \ + } \ + } \ + +#define render_window_segment(type, start, end, window_type) \ + if(start != end) \ + { \ + render_scanline_conditional_##type(start, end, scanline, \ + window_##window_type##_enable, dispcnt, bldcnt, layer_renderers); \ + } \ + +#define render_window_segment_unequal(type, start, end, window_type) \ + render_scanline_conditional_##type(start, end, scanline, \ + window_##window_type##_enable, dispcnt, bldcnt, layer_renderers) \ + +#define render_window_segment_clip(type, clip_start, clip_end, start, end, \ + window_type) \ +{ \ + if(start != end) \ + { \ + if(start < clip_start) \ + { \ + if(end > clip_start) \ + { \ + if(end > clip_end) \ + { \ + render_window_segment_unequal(type, clip_start, clip_end, \ + window_type); \ + } \ + else \ + { \ + render_window_segment_unequal(type, clip_start, end, window_type); \ + } \ + } \ + } \ + else \ + \ + if(end > clip_end) \ + { \ + if(start < clip_end) \ + render_window_segment_unequal(type, start, clip_end, window_type); \ + } \ + else \ + { \ + render_window_segment_unequal(type, start, end, window_type); \ + } \ + } \ +} \ + +#define render_window_clip_1(type, start, end) \ + if(window_1_x1 != 240) \ + { \ + if(window_1_x1 > window_1_x2) \ + { \ + render_window_segment_clip(type, start, end, 0, window_1_x2, 1); \ + render_window_segment_clip(type, start, end, window_1_x2, window_1_x1, \ + out); \ + render_window_segment_clip(type, start, end, window_1_x1, 240, 1); \ + } \ + else \ + { \ + render_window_segment_clip(type, start, end, 0, window_1_x1, out); \ + render_window_segment_clip(type, start, end, window_1_x1, window_1_x2, \ + 1); \ + render_window_segment_clip(type, start, end, window_1_x2, 240, out); \ + } \ + } \ + else \ + { \ + render_window_segment(type, start, end, out); \ + } \ + +#define render_window_clip_obj(type, start, end); \ + render_window_segment(type, start, end, out); \ + if(dispcnt & 0x40) \ + render_scanline_obj_copy_##type##_1D(4, start, end, scanline); \ + else \ + render_scanline_obj_copy_##type##_2D(4, start, end, scanline) \ + + +#define render_window_segment_clip_obj(type, clip_start, clip_end, start, \ + end) \ +{ \ + if(start != end) \ + { \ + if(start < clip_start) \ + { \ + if(end > clip_start) \ + { \ + if(end > clip_end) \ + { \ + render_window_clip_obj(type, clip_start, clip_end); \ + } \ + else \ + { \ + render_window_clip_obj(type, clip_start, end); \ + } \ + } \ + } \ + else \ + \ + if(end > clip_end) \ + { \ + if(start < clip_end) \ + { \ + render_window_clip_obj(type, start, clip_end); \ + } \ + } \ + else \ + { \ + render_window_clip_obj(type, start, end); \ + } \ + } \ +} \ + + +#define render_window_clip_1_obj(type, start, end) \ + if(window_1_x1 != 240) \ + { \ + if(window_1_x1 > window_1_x2) \ + { \ + render_window_segment_clip(type, start, end, 0, window_1_x2, 1); \ + render_window_segment_clip_obj(type, start, end, window_1_x2, \ + window_1_x1); \ + render_window_segment_clip(type, start, end, window_1_x1, 240, 1); \ + } \ + else \ + { \ + render_window_segment_clip_obj(type, start, end, 0, window_1_x1); \ + render_window_segment_clip(type, start, end, window_1_x1, window_1_x2, \ + 1); \ + render_window_segment_clip_obj(type, start, end, window_1_x2, 240); \ + } \ + } \ + else \ + { \ + render_window_clip_obj(type, start, end); \ + } \ + + + +#define render_window_single(type, window_number) \ + u32 winin = io_registers[REG_WININ]; \ + window_coords(window_number); \ + if(window_##window_number##_x1 > window_##window_number##_x2) \ + { \ + render_window_segment(type, 0, window_##window_number##_x2, \ + window_number); \ + render_window_segment(type, window_##window_number##_x2, \ + window_##window_number##_x1, out); \ + render_window_segment(type, window_##window_number##_x1, 240, \ + window_number); \ + } \ + else \ + { \ + render_window_segment(type, 0, window_##window_number##_x1, out); \ + render_window_segment(type, window_##window_number##_x1, \ + window_##window_number##_x2, window_number); \ + render_window_segment(type, window_##window_number##_x2, 240, out); \ + } \ + +#define render_window_multi(type, front, back) \ + if(window_##front##_x1 > window_##front##_x2) \ + { \ + render_window_segment(type, 0, window_##front##_x2, front); \ + render_window_clip_##back(type, window_##front##_x2, \ + window_##front##_x1); \ + render_window_segment(type, window_##front##_x1, 240, front); \ + } \ + else \ + { \ + render_window_clip_##back(type, 0, window_##front##_x1); \ + render_window_segment(type, window_##front##_x1, window_##front##_x2, \ + front); \ + render_window_clip_##back(type, window_##front##_x2, 240); \ + } \ + +#define render_scanline_window_builder(type) \ +void render_scanline_window_##type(u16 *scanline, u32 dispcnt) \ +{ \ + u32 vcount = io_registers[REG_VCOUNT]; \ + u32 winout = io_registers[REG_WINOUT]; \ + u32 bldcnt = io_registers[REG_BLDCNT]; \ + u32 window_out_enable = winout & 0x3F; \ + \ + render_scanline_layer_functions_##type(); \ + \ + switch(dispcnt >> 13) \ + { \ + /* Just window 0 */ \ + case 0x01: \ + { \ + render_window_single(type, 0); \ + break; \ + } \ + \ + /* Just window 1 */ \ + case 0x02: \ + { \ + render_window_single(type, 1); \ + break; \ + } \ + \ + /* Windows 1 and 2 */ \ + case 0x03: \ + { \ + u32 winin = io_registers[REG_WININ]; \ + window_coords(0); \ + window_coords(1); \ + render_window_multi(type, 0, 1); \ + break; \ + } \ + \ + /* Just OBJ windows */ \ + case 0x04: \ + { \ + u32 window_obj_enable = winout >> 8; \ + render_window_clip_obj(type, 0, 240); \ + break; \ + } \ + \ + /* Window 0 and OBJ window */ \ + case 0x05: \ + { \ + u32 window_obj_enable = winout >> 8; \ + u32 winin = io_registers[REG_WININ]; \ + window_coords(0); \ + render_window_multi(type, 0, obj); \ + break; \ + } \ + \ + /* Window 1 and OBJ window */ \ + case 0x06: \ + { \ + u32 window_obj_enable = winout >> 8; \ + u32 winin = io_registers[REG_WININ]; \ + window_coords(1); \ + render_window_multi(type, 1, obj); \ + break; \ + } \ + \ + /* Window 0, 1, and OBJ window */ \ + case 0x07: \ + { \ + u32 window_obj_enable = winout >> 8; \ + u32 winin = io_registers[REG_WININ]; \ + window_coords(0); \ + window_coords(1); \ + render_window_multi(type, 0, 1_obj); \ + break; \ + } \ + } \ +} \ + +render_scanline_window_builder(tile); +render_scanline_window_builder(bitmap); + +u32 active_layers[6] = { 0x1F, 0x17, 0x1C, 0x14, 0x14, 0x14 }; + +u32 small_resolution_width = 240; +u32 small_resolution_height = 160; +u32 resolution_width, resolution_height; + +void update_scanline() +{ + u32 pitch = get_screen_pitch(); + u32 dispcnt = io_registers[REG_DISPCNT]; + u32 display_flags = (dispcnt >> 8) & 0x1F; + u32 vcount = io_registers[REG_VCOUNT]; + u16 *screen_offset = get_screen_pixels() + (vcount * pitch); + u32 video_mode = dispcnt & 0x07; + u32 current_layer; + + // If OAM has been modified since the last scanline has been updated then + // reorder and reprofile the OBJ lists. + if(oam_update) + { + order_obj(video_mode); + oam_update = 0; + } + + order_layers((dispcnt >> 8) & active_layers[video_mode]); + + if(skip_next_frame) + return; + + // If the screen is in in forced blank draw pure white. + if(dispcnt & 0x80) + { + fill_line_color16(0xFFFF, screen_offset, 0, 240); + } + else + { + if(video_mode < 3) + { + if(dispcnt >> 13) + { + render_scanline_window_tile(screen_offset, dispcnt); + } + else + { + render_scanline_tile(screen_offset, dispcnt); + } + } + else + { + if(dispcnt >> 13) + render_scanline_window_bitmap(screen_offset, dispcnt); + else + render_scanline_bitmap(screen_offset, dispcnt); + } + } + + affine_reference_x[0] += (s16)io_registers[REG_BG2PB]; + affine_reference_y[0] += (s16)io_registers[REG_BG2PD]; + affine_reference_x[1] += (s16)io_registers[REG_BG3PB]; + affine_reference_y[1] += (s16)io_registers[REG_BG3PD]; +} + +#ifdef PSP_BUILD + +u32 screen_flip = 0; + +void flip_screen() +{ + if(video_direct == 0) + { + u32 *old_ge_cmd_ptr = ge_cmd_ptr; + sceKernelDcacheWritebackAll(); + + // Render the current screen + ge_cmd_ptr = ge_cmd + 2; + GE_CMD(TBP0, ((u32)screen_pixels & 0x00FFFFFF)); + GE_CMD(TBW0, (((u32)screen_pixels & 0xFF000000) >> 8) | + GBA_SCREEN_WIDTH); + ge_cmd_ptr = old_ge_cmd_ptr; + + sceGeListEnQueue(ge_cmd, ge_cmd_ptr, gecbid, NULL); + + // Flip to the next screen + screen_flip ^= 1; + + if(screen_flip) + screen_pixels = screen_texture + (240 * 160 * 2); + else + screen_pixels = screen_texture; + } +} + +#else + +#define integer_scale_copy_2() \ + current_scanline_ptr[x2] = current_pixel; \ + current_scanline_ptr[x2 - 1] = current_pixel; \ + x2 -= 2 \ + +#define integer_scale_copy_3() \ + current_scanline_ptr[x2] = current_pixel; \ + current_scanline_ptr[x2 - 1] = current_pixel; \ + current_scanline_ptr[x2 - 2] = current_pixel; \ + x2 -= 3 \ + +#define integer_scale_copy_4() \ + current_scanline_ptr[x2] = current_pixel; \ + current_scanline_ptr[x2 - 1] = current_pixel; \ + current_scanline_ptr[x2 - 2] = current_pixel; \ + current_scanline_ptr[x2 - 3] = current_pixel; \ + x2 -= 4 \ + +#define integer_scale_horizontal(scale_factor) \ + for(y = 0; y < 160; y++) \ + { \ + for(x = 239, x2 = (240 * video_scale) - 1; x >= 0; x--) \ + { \ + current_pixel = current_scanline_ptr[x]; \ + integer_scale_copy_##scale_factor(); \ + current_scanline_ptr[x2] = current_scanline_ptr[x]; \ + current_scanline_ptr[x2 - 1] = current_scanline_ptr[x]; \ + current_scanline_ptr[x2 - 2] = current_scanline_ptr[x]; \ + } \ + current_scanline_ptr += pitch; \ + } \ + +void flip_screen() +{ + if((video_scale != 1) && (current_scale != unscaled)) + { + s32 x, y; + s32 x2, y2; + u16 *screen_ptr = get_screen_pixels(); + u16 *current_scanline_ptr = screen_ptr; + u32 pitch = get_screen_pitch(); + u16 current_pixel; + u32 i; + + switch(video_scale) + { + case 2: + integer_scale_horizontal(2); + break; + + case 3: + integer_scale_horizontal(3); + break; + + default: + case 4: + integer_scale_horizontal(4); + break; + + } + + for(y = 159, y2 = (160 * video_scale) - 1; y >= 0; y--) + { + for(i = 0; i < video_scale; i++) + { + memcpy(screen_ptr + (y2 * pitch), + screen_ptr + (y * pitch), 480 * video_scale); + y2--; + } + } + } +#ifdef GP2X_BUILD + { + if((screen_scale == unscaled) && + (resolution_width == small_resolution_width) && + (resolution_height == small_resolution_height)) + { + SDL_Rect srect = {0, 0, 240, 160}; + SDL_Rect drect = {40, 40, 240, 160}; + SDL_BlitSurface(screen, &srect, hw_screen, &drect); + } + else + { + SDL_BlitSurface(screen, NULL, hw_screen, NULL); + } + } +#else + SDL_Flip(screen); +#endif +} + +#endif + +u32 frame_to_render; + +void update_screen() +{ + if(!skip_next_frame) + flip_screen(); +} + +#ifdef PSP_BUILD + +void init_video() +{ + sceDisplaySetMode(0, PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT); + + sceDisplayWaitVblankStart(); + sceDisplaySetFrameBuf((void*)psp_gu_vram_base, PSP_LINE_SIZE, + PSP_DISPLAY_PIXEL_FORMAT_565, PSP_DISPLAY_SETBUF_NEXTFRAME); + + sceGuInit(); + + sceGuStart(GU_DIRECT, display_list); + sceGuDrawBuffer(GU_PSM_5650, (void*)0, PSP_LINE_SIZE); + sceGuDispBuffer(PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT, + (void*)0, PSP_LINE_SIZE); + sceGuClear(GU_COLOR_BUFFER_BIT); + + sceGuOffset(2048 - (PSP_SCREEN_WIDTH / 2), 2048 - (PSP_SCREEN_HEIGHT / 2)); + sceGuViewport(2048, 2048, PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT); + + sceGuScissor(0, 0, PSP_SCREEN_WIDTH + 1, PSP_SCREEN_HEIGHT + 1); + sceGuEnable(GU_SCISSOR_TEST); + sceGuTexMode(GU_PSM_5650, 0, 0, GU_FALSE); + sceGuTexFunc(GU_TFX_REPLACE, GU_TCC_RGBA); + sceGuTexFilter(GU_LINEAR, GU_LINEAR); + sceGuEnable(GU_TEXTURE_2D); + + sceGuFrontFace(GU_CW); + sceGuDisable(GU_BLEND); + + sceGuFinish(); + sceGuSync(0, 0); + + sceDisplayWaitVblankStart(); + sceGuDisplay(GU_TRUE); + + PspGeCallbackData gecb; + gecb.signal_func = NULL; + gecb.signal_arg = NULL; + gecb.finish_func = Ge_Finish_Callback; + gecb.finish_arg = NULL; + gecbid = sceGeSetCallback(&gecb); + + screen_vertex[0] = 0 + 0.5; + screen_vertex[1] = 0 + 0.5; + screen_vertex[2] = 0 + 0.5; + screen_vertex[3] = 0 + 0.5; + screen_vertex[4] = 0; + screen_vertex[5] = GBA_SCREEN_WIDTH - 0.5; + screen_vertex[6] = GBA_SCREEN_HEIGHT - 0.5; + screen_vertex[7] = PSP_SCREEN_WIDTH - 0.5; + screen_vertex[8] = PSP_SCREEN_HEIGHT - 0.5; + screen_vertex[9] = 0; + + // Set framebuffer to PSP VRAM + GE_CMD(FBP, ((u32)psp_gu_vram_base & 0x00FFFFFF)); + GE_CMD(FBW, (((u32)psp_gu_vram_base & 0xFF000000) >> 8) | PSP_LINE_SIZE); + // Set texture 0 to the screen texture + GE_CMD(TBP0, ((u32)screen_texture & 0x00FFFFFF)); + GE_CMD(TBW0, (((u32)screen_texture & 0xFF000000) >> 8) | GBA_SCREEN_WIDTH); + // Set the texture size to 256 by 256 (2^8 by 2^8) + GE_CMD(TSIZE0, (8 << 8) | 8); + // Flush the texture cache + GE_CMD(TFLUSH, 0); + // Use 2D coordinates, no indeces, no weights, 32bit float positions, + // 32bit float texture coordinates + GE_CMD(VTYPE, (1 << 23) | (0 << 11) | (0 << 9) | + (3 << 7) | (0 << 5) | (0 << 2) | 3); + // Set the base of the index list pointer to 0 + GE_CMD(BASE, 0); + // Set the rest of index list pointer to 0 (not being used) + GE_CMD(IADDR, 0); + // Set the base of the screen vertex list pointer + GE_CMD(BASE, ((u32)screen_vertex & 0xFF000000) >> 8); + // Set the rest of the screen vertex list pointer + GE_CMD(VADDR, ((u32)screen_vertex & 0x00FFFFFF)); + // Primitive kick: render sprite (primitive 6), 2 vertices + GE_CMD(PRIM, (6 << 16) | 2); + // Done with commands + GE_CMD(FINISH, 0); + // Raise signal interrupt + GE_CMD(SIGNAL, 0); + GE_CMD(NOP, 0); + GE_CMD(NOP, 0); +} + +#else + +void init_video() +{ + SDL_Init(SDL_INIT_VIDEO | SDL_INIT_JOYSTICK | SDL_INIT_NOPARACHUTE); + +#ifdef GP2X_BUILD + SDL_GP2X_AllowGfxMemory(NULL, 0); + + hw_screen = SDL_SetVideoMode(320 * video_scale, 240 * video_scale, + 16, SDL_HWSURFACE); + + screen = SDL_CreateRGBSurface(SDL_HWSURFACE, 240 * video_scale, + 160 * video_scale, 16, 0xFFFF, 0xFFFF, 0xFFFF, 0); + + gp2x_load_mmuhack(); +#else + screen = SDL_SetVideoMode(240 * video_scale, 160 * video_scale, 16, 0); +#endif + SDL_ShowCursor(0); +} + +#endif + +video_scale_type screen_scale = scaled_aspect; +video_scale_type current_scale = scaled_aspect; +video_filter_type screen_filter = filter_bilinear; + + +#ifdef PSP_BUILD + +void video_resolution_large() +{ + if(video_direct != 1) + { + video_direct = 1; + screen_pixels = psp_gu_vram_base; + screen_pitch = 512; + sceGuStart(GU_DIRECT, display_list); + sceGuDispBuffer(PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT, + (void*)0, PSP_LINE_SIZE); + sceGuFinish(); + } +} + +void set_gba_resolution(video_scale_type scale) +{ + u32 filter_linear = 0; + screen_scale = scale; + switch(scale) + { + case unscaled: + screen_vertex[2] = 120 + 0.5; + screen_vertex[3] = 56 + 0.5; + screen_vertex[7] = GBA_SCREEN_WIDTH + 120 - 0.5; + screen_vertex[8] = GBA_SCREEN_HEIGHT + 56 - 0.5; + break; + + case scaled_aspect: + screen_vertex[2] = 36 + 0.5; + screen_vertex[3] = 0 + 0.5; + screen_vertex[7] = 408 + 36 - 0.5; + screen_vertex[8] = PSP_SCREEN_HEIGHT - 0.5; + break; + + case fullscreen: + screen_vertex[2] = 0; + screen_vertex[3] = 0; + screen_vertex[7] = PSP_SCREEN_WIDTH; + screen_vertex[8] = PSP_SCREEN_HEIGHT; + break; + } + + sceGuStart(GU_DIRECT, display_list); + if(screen_filter == filter_bilinear) + sceGuTexFilter(GU_LINEAR, GU_LINEAR); + else + sceGuTexFilter(GU_NEAREST, GU_NEAREST); + + sceGuFinish(); + sceGuSync(0, 0); + + clear_screen(0x0000); +} + +void video_resolution_small() +{ + if(video_direct != 0) + { + set_gba_resolution(screen_scale); + video_direct = 0; + screen_pixels = screen_texture; + screen_flip = 0; + screen_pitch = 240; + sceGuStart(GU_DIRECT, display_list); + sceGuDispBuffer(PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT, + (void*)0, PSP_LINE_SIZE); + sceGuFinish(); + } +} + +void clear_screen(u16 color) +{ + u32 i; + u16 *src_ptr = get_screen_pixels(); + + sceGuSync(0, 0); + + for(i = 0; i < (512 * 272); i++, src_ptr++) + { + *src_ptr = color; + } + + // I don't know why this doesn't work. +/* color = (((color & 0x1F) * 255 / 31) << 0) | + ((((color >> 5) & 0x3F) * 255 / 63) << 8) | + ((((color >> 11) & 0x1F) * 255 / 31) << 16) | (0xFF << 24); + + sceGuStart(GU_DIRECT, display_list); + sceGuDrawBuffer(GU_PSM_5650, (void*)0, PSP_LINE_SIZE); + //sceGuDispBuffer(PSP_SCREEN_WIDTH, PSP_SCREEN_HEIGHT, + // (void*)0, PSP_LINE_SIZE); + sceGuClearColor(color); + sceGuClear(GU_COLOR_BUFFER_BIT); + sceGuFinish(); + sceGuSync(0, 0); */ +} + +#else + +void video_resolution_large() +{ + current_scale = unscaled; + +#ifdef GP2X_BUILD + SDL_FreeSurface(screen); + SDL_GP2X_AllowGfxMemory(NULL, 0); + hw_screen = SDL_SetVideoMode(320, 240, 16, SDL_HWSURFACE); + screen = SDL_CreateRGBSurface(SDL_HWSURFACE, 320, 240, 16, 0xFFFF, + 0xFFFF, 0xFFFF, 0); + resolution_width = 320; + resolution_height = 240; + SDL_ShowCursor(0); + + gp2x_load_mmuhack(); +#else + screen = SDL_SetVideoMode(480, 272, 16, 0); + resolution_width = 480; + resolution_height = 272; +#endif +} + +void video_resolution_small() +{ + current_scale = screen_scale; + +#ifdef GP2X_BUILD + SDL_FreeSurface(screen); + SDL_GP2X_AllowGfxMemory(NULL, 0); + hw_screen = SDL_SetVideoMode((screen_scale == unscaled ? 320 : + small_resolution_width * video_scale), (screen_scale == unscaled ? 320 : + small_resolution_height * video_scale), 16, SDL_HWSURFACE); + + screen = SDL_CreateRGBSurface(SDL_HWSURFACE, + small_resolution_width * video_scale, small_resolution_height * + video_scale, 16, 0xFFFF, 0xFFFF, 0xFFFF, 0); + + SDL_ShowCursor(0); + + gp2x_load_mmuhack(); +#else + screen = SDL_SetVideoMode(small_resolution_width * video_scale, + small_resolution_height * video_scale, 16, 0); +#endif + resolution_width = small_resolution_width; + resolution_height = small_resolution_height; +} + +void set_gba_resolution(video_scale_type scale) +{ + if(screen_scale != scale) + { + screen_scale = scale; + switch(scale) + { + case unscaled: + case scaled_aspect: + case fullscreen: + small_resolution_width = 240 * video_scale; + small_resolution_height = 160 * video_scale; + break; + } + } +} + +void clear_screen(u16 color) +{ + u16 *dest_ptr = get_screen_pixels(); + u32 line_skip = get_screen_pitch() - screen->w; + u32 x, y; + + for(y = 0; y < screen->h; y++) + { + for(x = 0; x < screen->w; x++, dest_ptr++) + { + *dest_ptr = color; + } + dest_ptr += line_skip; + } +} + +#endif + +u16 *copy_screen() +{ + u16 *copy = malloc(240 * 160 * 2); + memcpy(copy, get_screen_pixels(), 240 * 160 * 2); + return copy; +} + +void blit_to_screen(u16 *src, u32 w, u32 h, u32 dest_x, u32 dest_y) +{ + u32 pitch = get_screen_pitch(); + u16 *dest_ptr = get_screen_pixels() + dest_x + (dest_y * pitch); + + u16 *src_ptr = src; + u32 line_skip = pitch - w; + u32 x, y; + + for(y = 0; y < h; y++) + { + for(x = 0; x < w; x++, src_ptr++, dest_ptr++) + { + *dest_ptr = *src_ptr; + } + dest_ptr += line_skip; + } +} + +void print_string_ext(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y, void *_dest_ptr, u32 pitch, u32 pad) +{ + u16 *dest_ptr = (u16 *)_dest_ptr + (y * pitch) + x; + u8 current_char = str[0]; + u32 current_row; + u32 glyph_offset; + u32 i = 0, i2, i3; + u32 str_index = 1; + u32 current_x = x; + + + /* EDIT */ + if(y + FONT_HEIGHT >= resolution_height) + return; + + while(current_char) + { + if(current_char == '\n') + { + y += FONT_HEIGHT; + current_x = x; + dest_ptr = get_screen_pixels() + (y * pitch) + x; + } + else + { + glyph_offset = _font_offset[current_char]; + current_x += FONT_WIDTH; + for(i2 = 0; i2 < FONT_HEIGHT; i2++, glyph_offset++) + { + current_row = _font_bits[glyph_offset]; + for(i3 = 0; i3 < FONT_WIDTH; i3++) + { + if((current_row >> (15 - i3)) & 0x01) + *dest_ptr = fg_color; + else + *dest_ptr = bg_color; + dest_ptr++; + } + dest_ptr += (pitch - FONT_WIDTH); + } + dest_ptr = dest_ptr - (pitch * FONT_HEIGHT) + FONT_WIDTH; + } + + i++; + + current_char = str[str_index]; + + if((i < pad) && (current_char == 0)) + { + current_char = ' '; + } + else + { + str_index++; + } + + if(current_x + FONT_WIDTH >= resolution_width /* EDIT */) + break; + } +} + +void print_string(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y) +{ + print_string_ext(str, fg_color, bg_color, x, y, get_screen_pixels(), + get_screen_pitch(), 0); +} + +void print_string_pad(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y, u32 pad) +{ + print_string_ext(str, fg_color, bg_color, x, y, get_screen_pixels(), + get_screen_pitch(), pad); +} + +u32 debug_cursor_x = 0; +u32 debug_cursor_y = 0; + +#ifdef STDIO_DEBUG + +void debug_screen_clear() +{ +} + +void debug_screen_start() +{ +} + +void debug_screen_end() +{ +} + +void debug_screen_update() +{ +} + +void debug_screen_printf(const char *format, ...) +{ + va_list ap; + + va_start(ap, format); + vprintf(format, ap); + va_end(ap); +} + +void debug_screen_newline(u32 count) +{ + printf("\n"); +} + + +#else + +void debug_screen_clear() +{ + debug_cursor_x = 0; + debug_cursor_y = 0; + clear_screen(0x0000); +} + +void debug_screen_start() +{ + video_resolution_large(); + debug_screen_clear(); +} + +void debug_screen_end() +{ + video_resolution_small(); +} + +void debug_screen_update() +{ + flip_screen(); +} + +void debug_screen_printf(const char *format, ...) +{ + char str_buffer[512]; + u32 str_buffer_length; + va_list ap; + + va_start(ap, format); + str_buffer_length = vsnprintf(str_buffer, 512, format, ap); + va_end(ap); + + printf("printing debug string %s at %d %d\n", str_buffer, + debug_cursor_x, debug_cursor_y); + + print_string(str_buffer, 0xFFFF, 0x0000, debug_cursor_x, debug_cursor_y); + debug_cursor_x += FONT_WIDTH * str_buffer_length; +} + +void debug_screen_newline(u32 count) +{ + debug_cursor_x = 0; + debug_cursor_y += FONT_HEIGHT * count; +} + +#endif + +void debug_screen_printl(const char *format, ...) +{ + va_list ap; + + va_start(ap, format); + debug_screen_printf(format, ap); + debug_screen_printf("\n"); + va_end(ap); +} + + +#define video_savestate_builder(type) \ +void video_##type##_savestate(file_tag_type savestate_file) \ +{ \ + file_##type##_array(savestate_file, affine_reference_x); \ + file_##type##_array(savestate_file, affine_reference_y); \ +} \ + +video_savestate_builder(read); +video_savestate_builder(write_mem); + + diff --git a/video.h b/video.h new file mode 100644 index 0000000..6be6b9c --- /dev/null +++ b/video.h @@ -0,0 +1,94 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef VIDEO_H +#define VIDEO_H + +void update_scanline(); +void update_screen(); +void init_video(); +void video_resolution_large(); +void video_resolution_small(); +void print_string(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y); +void print_string_pad(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y, u32 pad); +void print_string_ext(const char *str, u16 fg_color, u16 bg_color, + u32 x, u32 y, void *_dest_ptr, u32 pitch, u32 pad); +void clear_screen(u16 color); +void blit_to_screen(u16 *src, u32 w, u32 h, u32 x, u32 y); +u16 *copy_screen(); +void flip_screen(); +void video_write_mem_savestate(file_tag_type savestate_file); +void video_read_savestate(file_tag_type savestate_file); + +void debug_screen_clear(); +void debug_screen_start(); +void debug_screen_end(); +void debug_screen_printf(const char *format, ...); +void debug_screen_printl(const char *format, ...); +void debug_screen_newline(u32 count); +void debug_screen_update(); + +extern u32 frame_speed; + +extern s32 affine_reference_x[2]; +extern s32 affine_reference_y[2]; + +typedef void (* tile_render_function)(u32 layer_number, u32 start, u32 end, + void *dest_ptr); +typedef void (* bitmap_render_function)(u32 start, u32 end, void *dest_ptr); + +typedef struct +{ + tile_render_function normal_render_base; + tile_render_function normal_render_transparent; + tile_render_function alpha_render_base; + tile_render_function alpha_render_transparent; + tile_render_function color16_render_base; + tile_render_function color16_render_transparent; + tile_render_function color32_render_base; + tile_render_function color32_render_transparent; +} tile_layer_render_struct; + +typedef struct +{ + bitmap_render_function normal_render; +} bitmap_layer_render_struct; + +typedef enum +{ + unscaled, + scaled_aspect, + fullscreen, +} video_scale_type; + +typedef enum +{ + filter_nearest, + filter_bilinear +} video_filter_type; + +extern video_scale_type screen_scale; +extern video_scale_type current_scale; +extern video_filter_type screen_filter; + +void set_gba_resolution(video_scale_type scale); + +#endif diff --git a/x86/Makefile b/x86/Makefile new file mode 100644 index 0000000..e0a5767 --- /dev/null +++ b/x86/Makefile @@ -0,0 +1,38 @@ +# gpSP makefile +# Gilead Kutnick - Exophase + +# Global definitions + +CC = gcc +STRIP = strip +AS = as + +PREFIX = /usr +OBJS = main.o cpu.o memory.o video.o input.o sound.o \ + cpu_threaded.o gui.o x86_stub.o cheats.o zip.o +BIN ?= gpsp.exe + +# Platform specific definitions + +VPATH += .. +CFLAGS += -DPC_BUILD +INCLUDES = -I${PREFIX}/include `sdl-config --cflags` +LIBS = -L${PREFIX}/lib `sdl-config --libs` -mconsole -lz + +# Compilation: + +.SUFFIXES: .c .S + +%.o: %.c + ${CC} ${CFLAGS} ${INCLUDES} -c -o $@ $< + +%.o: %.S + ${AS} -o $@ $< + +all: ${OBJS} + ${CC} ${OBJS} ${LIBS} -o ${BIN} + ${STRIP} ${BIN} + +clean: + rm -f *.o ${BIN} + diff --git a/x86/x86_emit.h b/x86/x86_emit.h new file mode 100644 index 0000000..6f02d07 --- /dev/null +++ b/x86/x86_emit.h @@ -0,0 +1,2327 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X86_EMIT_H +#define X86_EMIT_H + +u32 x86_update_gba(u32 pc); + +// Although these are defined as a function, don't call them as +// such (jump to it instead) +void x86_indirect_branch_arm(u32 address); +void x86_indirect_branch_thumb(u32 address); +void x86_indirect_branch_dual(u32 address); + +void function_cc execute_store_cpsr(u32 new_cpsr, u32 store_mask); + +void step_debug_x86(u32 pc); + +typedef enum +{ + x86_reg_number_eax, + x86_reg_number_ecx, + x86_reg_number_edx, + x86_reg_number_ebx, + x86_reg_number_esp, + x86_reg_number_ebp, + x86_reg_number_esi, + x86_reg_number_edi +} x86_reg_number; + +#define x86_emit_byte(value) \ + *translation_ptr = value; \ + translation_ptr++ \ + +#define x86_emit_dword(value) \ + *((u32 *)translation_ptr) = value; \ + translation_ptr += 4 \ + +typedef enum +{ + x86_mod_mem = 0, + x86_mod_mem_disp8 = 1, + x86_mod_mem_disp32 = 2, + x86_mod_reg = 3 +} x86_mod; + +#define x86_emit_mod_rm(mod, rm, spare) \ + x86_emit_byte((mod << 6) | (spare << 3) | rm) \ + +#define x86_emit_mem_op(dest, base, offset) \ + if(offset == 0) \ + { \ + x86_emit_mod_rm(x86_mod_mem, base, dest); \ + } \ + else \ + \ + if(((s32)offset < 127) && ((s32)offset > -128)) \ + { \ + x86_emit_mod_rm(x86_mod_mem_disp8, base, dest); \ + x86_emit_byte((s8)offset); \ + } \ + else \ + { \ + x86_emit_mod_rm(x86_mod_mem_disp32, base, dest); \ + x86_emit_dword(offset); \ + } \ + +#define x86_emit_reg_op(dest, source) \ + x86_emit_mod_rm(x86_mod_reg, source, dest) \ + + +typedef enum +{ + x86_opcode_mov_rm_reg = 0x89, + x86_opcode_mov_reg_rm = 0x8B, + x86_opcode_mov_reg_imm = 0xB8, + x86_opcode_mov_rm_imm = 0x00C7, + x86_opcode_ror_reg_imm = 0x01C1, + x86_opcode_shl_reg_imm = 0x04C1, + x86_opcode_shr_reg_imm = 0x05C1, + x86_opcode_sar_reg_imm = 0x07C1, + x86_opcode_push_reg = 0x50, + x86_opcode_push_rm = 0xFF, + x86_opcode_push_imm = 0x0668, + x86_opcode_call_offset = 0xE8, + x86_opcode_ret = 0xC3, + x86_opcode_test_rm_imm = 0x00F7, + x86_opcode_test_reg_rm = 0x85, + x86_opcode_mul_eax_rm = 0x04F7, + x86_opcode_imul_eax_rm = 0x05F7, + x86_opcode_idiv_eax_rm = 0x07F7, + x86_opcode_add_rm_imm = 0x0081, + x86_opcode_and_rm_imm = 0x0481, + x86_opcode_sub_rm_imm = 0x0581, + x86_opcode_xor_rm_imm = 0x0681, + x86_opcode_add_reg_rm = 0x03, + x86_opcode_adc_reg_rm = 0x13, + x86_opcode_or_reg_rm = 0x0B, + x86_opcode_sub_reg_rm = 0x2B, + x86_opcode_xor_reg_rm = 0x33, + x86_opcode_cmp_reg_rm = 0x39, + x86_opcode_cmp_rm_imm = 0x053B, + x86_opcode_lea_reg_rm = 0x8D, + x86_opcode_j = 0x80, + x86_opcode_jmp = 0xE9, + x86_opcode_jmp_reg = 0x04FF, + x86_opcode_ext = 0x0F +} x86_opcodes; + +typedef enum +{ + x86_condition_code_o = 0x00, + x86_condition_code_no = 0x01, + x86_condition_code_c = 0x02, + x86_condition_code_nc = 0x03, + x86_condition_code_z = 0x04, + x86_condition_code_nz = 0x05, + x86_condition_code_na = 0x06, + x86_condition_code_a = 0x07, + x86_condition_code_s = 0x08, + x86_condition_code_ns = 0x09, + x86_condition_code_p = 0x0A, + x86_condition_code_np = 0x0B, + x86_condition_code_l = 0x0C, + x86_condition_code_nl = 0x0D, + x86_condition_code_ng = 0x0E, + x86_condition_code_g = 0x0F +} x86_condition_codes; + +#define x86_relative_offset(source, offset, next) \ + ((u32)offset - ((u32)source + next)) \ + +#define x86_unequal_operands(op_a, op_b) \ + (x86_reg_number_##op_a != x86_reg_number_##op_b) \ + +#define x86_emit_opcode_1b_reg(opcode, dest, source) \ +{ \ + x86_emit_byte(x86_opcode_##opcode); \ + x86_emit_reg_op(x86_reg_number_##dest, x86_reg_number_##source); \ +} \ + +#define x86_emit_opcode_1b_mem(opcode, dest, base, offset) \ +{ \ + x86_emit_byte(x86_opcode_##opcode); \ + x86_emit_mem_op(x86_reg_number_##dest, x86_reg_number_##base, offset); \ +} \ + +#define x86_emit_opcode_1b(opcode, reg) \ + x86_emit_byte(x86_opcode_##opcode | x86_reg_number_##reg) \ + +#define x86_emit_opcode_1b_ext_reg(opcode, dest) \ + x86_emit_byte(x86_opcode_##opcode & 0xFF); \ + x86_emit_reg_op(x86_opcode_##opcode >> 8, x86_reg_number_##dest) \ + +#define x86_emit_opcode_1b_ext_mem(opcode, base, offset) \ + x86_emit_byte(x86_opcode_##opcode & 0xFF); \ + x86_emit_mem_op(x86_opcode_##opcode >> 8, x86_reg_number_##base, offset) \ + +#define x86_emit_mov_reg_mem(dest, base, offset) \ + x86_emit_opcode_1b_mem(mov_reg_rm, dest, base, offset) \ + +#define x86_emit_mov_mem_reg(source, base, offset) \ + x86_emit_opcode_1b_mem(mov_rm_reg, source, base, offset) \ + +#define x86_emit_mov_reg_reg(dest, source) \ + if(x86_unequal_operands(dest, source)) \ + { \ + x86_emit_opcode_1b_reg(mov_reg_rm, dest, source) \ + } \ + +#define x86_emit_mov_reg_imm(dest, imm) \ + x86_emit_opcode_1b(mov_reg_imm, dest); \ + x86_emit_dword(imm) \ + +#define x86_emit_mov_mem_imm(imm, base, offset) \ + x86_emit_opcode_1b_ext_mem(mov_rm_imm, base, offset); \ + x86_emit_dword(imm) \ + +#define x86_emit_shl_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(shl_reg_imm, dest); \ + x86_emit_byte(imm) \ + +#define x86_emit_shr_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(shr_reg_imm, dest); \ + x86_emit_byte(imm) \ + +#define x86_emit_sar_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(sar_reg_imm, dest); \ + x86_emit_byte(imm) \ + +#define x86_emit_ror_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(ror_reg_imm, dest); \ + x86_emit_byte(imm) \ + +#define x86_emit_add_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(add_reg_rm, dest, source) \ + +#define x86_emit_adc_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(adc_reg_rm, dest, source) \ + +#define x86_emit_sub_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(sub_reg_rm, dest, source) \ + +#define x86_emit_or_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(or_reg_rm, dest, source) \ + +#define x86_emit_xor_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(xor_reg_rm, dest, source) \ + +#define x86_emit_add_reg_imm(dest, imm) \ + if(imm != 0) \ + { \ + x86_emit_opcode_1b_ext_reg(add_rm_imm, dest); \ + x86_emit_dword(imm); \ + } \ + +#define x86_emit_sub_reg_imm(dest, imm) \ + if(imm != 0) \ + { \ + x86_emit_opcode_1b_ext_reg(sub_rm_imm, dest); \ + x86_emit_dword(imm); \ + } \ + +#define x86_emit_and_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(and_rm_imm, dest); \ + x86_emit_dword(imm) \ + +#define x86_emit_xor_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(xor_rm_imm, dest); \ + x86_emit_dword(imm) \ + +#define x86_emit_test_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(test_rm_imm, dest); \ + x86_emit_dword(imm) \ + +#define x86_emit_cmp_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(cmp_reg_rm, dest, source) \ + +#define x86_emit_test_reg_reg(dest, source) \ + x86_emit_opcode_1b_reg(test_reg_rm, dest, source) \ + +#define x86_emit_cmp_reg_imm(dest, imm) \ + x86_emit_opcode_1b_ext_reg(cmp_rm_imm, dest); \ + x86_emit_dword(imm) \ + +#define x86_emit_mul_eax_reg(source) \ + x86_emit_opcode_1b_ext_reg(mul_eax_rm, source) \ + +#define x86_emit_imul_eax_reg(source) \ + x86_emit_opcode_1b_ext_reg(imul_eax_rm, source) \ + +#define x86_emit_idiv_eax_reg(source) \ + x86_emit_opcode_1b_ext_reg(idiv_eax_rm, source) \ + +#define x86_emit_push_mem(base, offset) \ + x86_emit_opcode_1b_mem(push_rm, 0x06, base, offset) \ + +#define x86_emit_push_imm(imm) \ + x86_emit_byte(x86_opcode_push_imm); \ + x86_emit_dword(imm) \ + +#define x86_emit_call_offset(relative_offset) \ + x86_emit_byte(x86_opcode_call_offset); \ + x86_emit_dword(relative_offset) \ + +#define x86_emit_ret() \ + x86_emit_byte(x86_opcode_ret) \ + +#define x86_emit_lea_reg_mem(dest, base, offset) \ + x86_emit_opcode_1b_mem(lea_reg_rm, dest, base, offset) \ + +#define x86_emit_j_filler(condition_code, writeback_location) \ + x86_emit_byte(x86_opcode_ext); \ + x86_emit_byte(x86_opcode_j | condition_code); \ + (writeback_location) = translation_ptr; \ + translation_ptr += 4 \ + +#define x86_emit_j_offset(condition_code, offset) \ + x86_emit_byte(x86_opcode_ext); \ + x86_emit_byte(x86_opcode_j | condition_code); \ + x86_emit_dword(offset) \ + +#define x86_emit_jmp_filler(writeback_location) \ + x86_emit_byte(x86_opcode_jmp); \ + (writeback_location) = translation_ptr; \ + translation_ptr += 4 \ + +#define x86_emit_jmp_offset(offset) \ + x86_emit_byte(x86_opcode_jmp); \ + x86_emit_dword(offset) \ + +#define x86_emit_jmp_reg(source) \ + x86_emit_opcode_1b_ext_reg(jmp_reg, source) \ + +#define reg_base ebx +#define reg_cycles edi +#define reg_a0 eax +#define reg_a1 edx +#define reg_a2 ecx +#define reg_rv eax +#define reg_s0 esi + +#define generate_load_reg(ireg, reg_index) \ + x86_emit_mov_reg_mem(reg_##ireg, reg_base, reg_index * 4); \ + +#define generate_load_pc(ireg, new_pc) \ + x86_emit_mov_reg_imm(reg_##ireg, new_pc) \ + +#define generate_load_imm(ireg, imm) \ + x86_emit_mov_reg_imm(reg_##ireg, imm) \ + +#define generate_store_reg(ireg, reg_index) \ + x86_emit_mov_mem_reg(reg_##ireg, reg_base, reg_index * 4) \ + +#define generate_shift_left(ireg, imm) \ + x86_emit_shl_reg_imm(reg_##ireg, imm) \ + +#define generate_shift_right(ireg, imm) \ + x86_emit_shr_reg_imm(reg_##ireg, imm) \ + +#define generate_shift_right_arithmetic(ireg, imm) \ + x86_emit_sar_reg_imm(reg_##ireg, imm) \ + +#define generate_rotate_right(ireg, imm) \ + x86_emit_ror_reg_imm(reg_##ireg, imm) \ + +#define generate_add(ireg_dest, ireg_src) \ + x86_emit_add_reg_reg(reg_##ireg_dest, reg_##ireg_src) \ + +#define generate_sub(ireg_dest, ireg_src) \ + x86_emit_sub_reg_reg(reg_##ireg_dest, reg_##ireg_src) \ + +#define generate_or(ireg_dest, ireg_src) \ + x86_emit_or_reg_reg(reg_##ireg_dest, reg_##ireg_src) \ + +#define generate_xor(ireg_dest, ireg_src) \ + x86_emit_xor_reg_reg(reg_##ireg_dest, reg_##ireg_src) \ + +#define generate_add_imm(ireg, imm) \ + x86_emit_add_reg_imm(reg_##ireg, imm) \ + +#define generate_sub_imm(ireg, imm) \ + x86_emit_sub_reg_imm(reg_##ireg, imm) \ + +#define generate_xor_imm(ireg, imm) \ + x86_emit_xor_reg_imm(reg_##ireg, imm) \ + +#define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm) \ + x86_emit_lea_reg_mem(reg_##ireg_dest, reg_##ireg_src, imm) \ + +#define generate_and_imm(ireg, imm) \ + x86_emit_and_reg_imm(reg_##ireg, imm) \ + +#define generate_mov(ireg_dest, ireg_src) \ + x86_emit_mov_reg_reg(reg_##ireg_dest, reg_##ireg_src) \ + +#define generate_multiply(ireg) \ + x86_emit_imul_eax_reg(reg_##ireg) \ + +#define generate_multiply_s64(ireg) \ + x86_emit_imul_eax_reg(reg_##ireg) \ + +#define generate_multiply_u64(ireg) \ + x86_emit_mul_eax_reg(reg_##ireg) \ + +#define generate_multiply_s64_add(ireg_src, ireg_lo, ireg_hi) \ + x86_emit_imul_eax_reg(reg_##ireg_src); \ + x86_emit_add_reg_reg(reg_a0, reg_##ireg_lo); \ + x86_emit_adc_reg_reg(reg_a1, reg_##ireg_hi) \ + +#define generate_multiply_u64_add(ireg_src, ireg_lo, ireg_hi) \ + x86_emit_mul_eax_reg(reg_##ireg_src); \ + x86_emit_add_reg_reg(reg_a0, reg_##ireg_lo); \ + x86_emit_adc_reg_reg(reg_a1, reg_##ireg_hi) \ + + +#define generate_function_call(function_location) \ + x86_emit_call_offset(x86_relative_offset(translation_ptr, \ + function_location, 4)); \ + +#define generate_exit_block() \ + x86_emit_ret(); \ + +#define generate_branch_filler_true(ireg_dest, ireg_src, writeback_location) \ + x86_emit_test_reg_imm(reg_##ireg_dest, 1); \ + x86_emit_j_filler(x86_condition_code_z, writeback_location) \ + +#define generate_branch_filler_false(ireg_dest, ireg_src, writeback_location) \ + x86_emit_test_reg_imm(reg_##ireg_dest, 1); \ + x86_emit_j_filler(x86_condition_code_nz, writeback_location) \ + +#define generate_branch_filler_equal(ireg_dest, ireg_src, writeback_location) \ + x86_emit_cmp_reg_reg(reg_##ireg_dest, reg_##ireg_src); \ + x86_emit_j_filler(x86_condition_code_nz, writeback_location) \ + +#define generate_branch_filler_not_equal(ireg_dest, ireg_src, \ + writeback_location) \ + x86_emit_cmp_reg_reg(reg_##ireg_dest, reg_##ireg_src); \ + x86_emit_j_filler(x86_condition_code_z, writeback_location) \ + +#define generate_update_pc(new_pc) \ + x86_emit_mov_reg_imm(eax, new_pc) \ + +#define generate_update_pc_reg() \ + generate_update_pc(pc); \ + generate_store_reg(a0, REG_PC) \ + +#define generate_cycle_update() \ + x86_emit_sub_reg_imm(reg_cycles, cycle_count); \ + cycle_count = 0 \ + +#define generate_branch_patch_conditional(dest, offset) \ + *((u32 *)(dest)) = x86_relative_offset(dest, offset, 4) \ + +#define generate_branch_patch_unconditional(dest, offset) \ + *((u32 *)(dest)) = x86_relative_offset(dest, offset, 4) \ + +#define generate_branch_no_cycle_update(writeback_location, new_pc) \ + if(pc == idle_loop_target_pc) \ + { \ + x86_emit_mov_reg_imm(eax, new_pc); \ + generate_function_call(x86_update_gba); \ + x86_emit_jmp_filler(writeback_location); \ + } \ + else \ + { \ + x86_emit_test_reg_reg(reg_cycles, reg_cycles); \ + x86_emit_j_offset(x86_condition_code_ns, 10); \ + x86_emit_mov_reg_imm(eax, new_pc); \ + generate_function_call(x86_update_gba); \ + x86_emit_jmp_filler(writeback_location); \ + } \ + +#define generate_branch_cycle_update(writeback_location, new_pc) \ + generate_cycle_update(); \ + generate_branch_no_cycle_update(writeback_location, new_pc) \ + +#define generate_conditional_branch(ireg_a, ireg_b, type, writeback_location) \ + generate_branch_filler_##type(ireg_a, ireg_b, writeback_location) \ + +// a0 holds the destination + +#define generate_indirect_branch_cycle_update(type) \ + generate_cycle_update(); \ + x86_emit_jmp_offset(x86_relative_offset(translation_ptr, \ + x86_indirect_branch_##type, 4)) \ + +#define generate_indirect_branch_no_cycle_update(type) \ + x86_emit_jmp_offset(x86_relative_offset(translation_ptr, \ + x86_indirect_branch_##type, 4)) \ + +#define generate_block_prologue() \ + +#define generate_block_extra_vars_arm() \ + void generate_indirect_branch_arm() \ + { \ + if(condition == 0x0E) \ + { \ + generate_indirect_branch_cycle_update(arm); \ + } \ + else \ + { \ + generate_indirect_branch_no_cycle_update(arm); \ + } \ + } \ + \ + void generate_indirect_branch_dual() \ + { \ + if(condition == 0x0E) \ + { \ + generate_indirect_branch_cycle_update(dual); \ + } \ + else \ + { \ + generate_indirect_branch_no_cycle_update(dual); \ + } \ + } \ + +#define generate_block_extra_vars_thumb() \ + + +#define translate_invalidate_dcache() \ + +#define block_prologue_size 0 + +#define calculate_z_flag(dest) \ + reg[REG_Z_FLAG] = (dest == 0) \ + +#define calculate_n_flag(dest) \ + reg[REG_N_FLAG] = ((signed)dest < 0) \ + +#define calculate_c_flag_sub(dest, src_a, src_b) \ + reg[REG_C_FLAG] = ((unsigned)src_b <= (unsigned)src_a) \ + +#define calculate_v_flag_sub(dest, src_a, src_b) \ + reg[REG_V_FLAG] = ((signed)src_b > (signed)src_a) != ((signed)dest < 0) \ + +#define calculate_c_flag_add(dest, src_a, src_b) \ + reg[REG_C_FLAG] = ((unsigned)dest < (unsigned)src_a) \ + +#define calculate_v_flag_add(dest, src_a, src_b) \ + reg[REG_V_FLAG] = ((signed)dest < (signed)src_a) != ((signed)src_b < 0) \ + + + +#define get_shift_imm() \ + u32 shift = (opcode >> 7) & 0x1F \ + +#define generate_shift_reg(ireg, name, flags_op) \ + generate_load_reg_pc(ireg, rm, 12); \ + generate_load_reg(a1, ((opcode >> 8) & 0x0F)); \ + generate_function_call(execute_##name##_##flags_op##_reg); \ + generate_mov(ireg, rv) \ + +u32 function_cc execute_lsl_no_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + value = 0; + else + value <<= shift; + } + return value; +} + +u32 function_cc execute_lsr_no_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + value = 0; + else + value >>= shift; + } + return value; +} + +u32 function_cc execute_asr_no_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + value = (s32)value >> 31; + else + value = (s32)value >> shift; + } + return value; +} + +u32 function_cc execute_ror_no_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + ror(value, value, shift); + } + + return value; +} + + +u32 function_cc execute_lsl_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + reg[REG_C_FLAG] = value & 0x01; + + if(shift != 32) + reg[REG_C_FLAG] = 0; + + value = 0; + } + else + { + reg[REG_C_FLAG] = (value >> (32 - shift)) & 0x01; + value <<= shift; + } + } + return value; +} + +u32 function_cc execute_lsr_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + reg[REG_C_FLAG] = value >> 31; + + if(shift != 32) + reg[REG_C_FLAG] = 0; + + value = 0; + } + else + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value >>= shift; + } + } + return value; +} + +u32 function_cc execute_asr_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + value = (s32)value >> 31; + reg[REG_C_FLAG] = value & 0x01; + } + else + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value = (s32)value >> shift; + } + } + return value; +} + +u32 function_cc execute_ror_flags_reg(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + ror(value, value, shift); + } + + return value; +} + +u32 function_cc execute_rrx_flags(u32 value) +{ + u32 c_flag = reg[REG_C_FLAG]; + reg[REG_C_FLAG] = value & 0x01; + return (value >> 1) | (c_flag << 31); +} + +u32 function_cc execute_rrx(u32 value) +{ + return (value >> 1) | (reg[REG_C_FLAG] << 31); +} + +#define generate_shift_imm_lsl_no_flags(ireg) \ + generate_load_reg_pc(ireg, rm, 8); \ + if(shift != 0) \ + { \ + generate_shift_left(ireg, shift); \ + } \ + +#define generate_shift_imm_lsr_no_flags(ireg) \ + if(shift != 0) \ + { \ + generate_load_reg_pc(ireg, rm, 8); \ + generate_shift_right(ireg, shift); \ + } \ + else \ + { \ + generate_load_imm(ireg, 0); \ + } \ + +#define generate_shift_imm_asr_no_flags(ireg) \ + generate_load_reg_pc(ireg, rm, 8); \ + if(shift != 0) \ + { \ + generate_shift_right_arithmetic(ireg, shift); \ + } \ + else \ + { \ + generate_shift_right_arithmetic(ireg, 31); \ + } \ + +#define generate_shift_imm_ror_no_flags(ireg) \ + if(shift != 0) \ + { \ + generate_load_reg_pc(ireg, rm, 8); \ + generate_rotate_right(ireg, shift); \ + } \ + else \ + { \ + generate_load_reg_pc(a0, rm, 8); \ + generate_function_call(execute_rrx); \ + generate_mov(ireg, rv); \ + } \ + +#define generate_shift_imm_lsl_flags(ireg) \ + generate_load_reg_pc(ireg, rm, 8); \ + if(shift != 0) \ + { \ + generate_mov(a1, ireg); \ + generate_shift_right(a1, (32 - shift)); \ + generate_and_imm(a1, 1); \ + generate_store_reg(a1, REG_C_FLAG); \ + generate_shift_left(ireg, shift); \ + } \ + +#define generate_shift_imm_lsr_flags(ireg) \ + if(shift != 0) \ + { \ + generate_load_reg_pc(ireg, rm, 8); \ + generate_mov(a1, ireg); \ + generate_shift_right(a1, shift - 1); \ + generate_and_imm(a1, 1); \ + generate_store_reg(a1, REG_C_FLAG); \ + generate_shift_right(ireg, shift); \ + } \ + else \ + { \ + generate_load_reg_pc(a1, rm, 8); \ + generate_shift_right(a1, 31); \ + generate_store_reg(a1, REG_C_FLAG); \ + generate_load_imm(ireg, 0); \ + } \ + +#define generate_shift_imm_asr_flags(ireg) \ + if(shift != 0) \ + { \ + generate_load_reg_pc(ireg, rm, 8); \ + generate_mov(a1, ireg); \ + generate_shift_right_arithmetic(a1, shift - 1); \ + generate_and_imm(a1, 1); \ + generate_store_reg(a1, REG_C_FLAG); \ + generate_shift_right_arithmetic(ireg, shift); \ + } \ + else \ + { \ + generate_load_reg_pc(a0, rm, 8); \ + generate_shift_right_arithmetic(ireg, 31); \ + generate_mov(a1, ireg); \ + generate_and_imm(a1, 1); \ + generate_store_reg(a1, REG_C_FLAG); \ + } \ + +#define generate_shift_imm_ror_flags(ireg) \ + generate_load_reg_pc(ireg, rm, 8); \ + if(shift != 0) \ + { \ + generate_mov(a1, ireg); \ + generate_shift_right(a1, shift - 1); \ + generate_and_imm(a1, 1); \ + generate_store_reg(a1, REG_C_FLAG); \ + generate_rotate_right(ireg, shift); \ + } \ + else \ + { \ + generate_function_call(execute_rrx_flags); \ + generate_mov(ireg, rv); \ + } \ + +#define generate_shift_imm(ireg, name, flags_op) \ + get_shift_imm(); \ + generate_shift_imm_##name##_##flags_op(ireg) \ + +#define generate_load_rm_sh(flags_op) \ + switch((opcode >> 4) & 0x07) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + generate_shift_imm(a0, lsl, flags_op); \ + break; \ + } \ + \ + /* LSL reg */ \ + case 0x1: \ + { \ + generate_shift_reg(a0, lsl, flags_op); \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x2: \ + { \ + generate_shift_imm(a0, lsr, flags_op); \ + break; \ + } \ + \ + /* LSR reg */ \ + case 0x3: \ + { \ + generate_shift_reg(a0, lsr, flags_op); \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x4: \ + { \ + generate_shift_imm(a0, asr, flags_op); \ + break; \ + } \ + \ + /* ASR reg */ \ + case 0x5: \ + { \ + generate_shift_reg(a0, asr, flags_op); \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x6: \ + { \ + generate_shift_imm(a0, ror, flags_op); \ + break; \ + } \ + \ + /* ROR reg */ \ + case 0x7: \ + { \ + generate_shift_reg(a0, ror, flags_op); \ + break; \ + } \ + } \ + +#define generate_load_offset_sh() \ + switch((opcode >> 5) & 0x03) \ + { \ + /* LSL imm */ \ + case 0x0: \ + { \ + generate_shift_imm(a1, lsl, no_flags); \ + break; \ + } \ + \ + /* LSR imm */ \ + case 0x1: \ + { \ + generate_shift_imm(a1, lsr, no_flags); \ + break; \ + } \ + \ + /* ASR imm */ \ + case 0x2: \ + { \ + generate_shift_imm(a1, asr, no_flags); \ + break; \ + } \ + \ + /* ROR imm */ \ + case 0x3: \ + { \ + generate_shift_imm(a1, ror, no_flags); \ + break; \ + } \ + } \ + +#define calculate_flags_add(dest, src_a, src_b) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + calculate_c_flag_add(dest, src_a, src_b); \ + calculate_v_flag_add(dest, src_a, src_b) \ + +#define calculate_flags_sub(dest, src_a, src_b) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + calculate_c_flag_sub(dest, src_a, src_b); \ + calculate_v_flag_sub(dest, src_a, src_b) \ + +#define calculate_flags_logic(dest) \ + calculate_z_flag(dest); \ + calculate_n_flag(dest) \ + +#define extract_flags() \ + reg[REG_N_FLAG] = reg[REG_CPSR] >> 31; \ + reg[REG_Z_FLAG] = (reg[REG_CPSR] >> 30) & 0x01; \ + reg[REG_C_FLAG] = (reg[REG_CPSR] >> 29) & 0x01; \ + reg[REG_V_FLAG] = (reg[REG_CPSR] >> 28) & 0x01; \ + +#define collapse_flags() \ + reg[REG_CPSR] = (reg[REG_N_FLAG] << 31) | (reg[REG_Z_FLAG] << 30) | \ + (reg[REG_C_FLAG] << 29) | (reg[REG_V_FLAG] << 28) | \ + reg[REG_CPSR] & 0xFF \ + +// It should be okay to still generate result flags, spsr will overwrite them. +// This is pretty infrequent (returning from interrupt handlers, et al) so +// probably not worth optimizing for. + +#define check_for_interrupts() \ + if((io_registers[REG_IE] & io_registers[REG_IF]) && \ + io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \ + { \ + reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4; \ + spsr[MODE_IRQ] = reg[REG_CPSR]; \ + reg[REG_CPSR] = 0xD2; \ + address = 0x00000018; \ + set_cpu_mode(MODE_IRQ); \ + } \ + +#define generate_load_reg_pc(ireg, reg_index, pc_offset) \ + if(reg_index == 15) \ + { \ + generate_load_pc(ireg, pc + pc_offset); \ + } \ + else \ + { \ + generate_load_reg(ireg, reg_index); \ + } \ + +#define generate_store_reg_pc_no_flags(ireg, reg_index) \ + generate_store_reg(ireg, reg_index); \ + if(reg_index == 15) \ + { \ + generate_mov(a0, ireg); \ + generate_indirect_branch_arm(); \ + } \ + +u32 function_cc execute_spsr_restore(u32 address) +{ + if(reg[CPU_MODE] != MODE_USER) + { + reg[REG_CPSR] = spsr[reg[CPU_MODE]]; + extract_flags(); + set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); + check_for_interrupts(); + + if(reg[REG_CPSR] & 0x20) + address |= 0x01; + } + + return address; +} + +#define generate_store_reg_pc_flags(ireg, reg_index) \ + generate_store_reg(ireg, reg_index); \ + if(reg_index == 15) \ + { \ + generate_mov(a0, ireg); \ + generate_function_call(execute_spsr_restore); \ + generate_mov(a0, rv); \ + generate_indirect_branch_dual(); \ + } \ + +typedef enum +{ + CONDITION_TRUE, + CONDITION_FALSE, + CONDITION_EQUAL, + CONDITION_NOT_EQUAL +} condition_check_type; + + +#define generate_condition_eq(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_Z_FLAG); \ + condition_check = CONDITION_TRUE \ + +#define generate_condition_ne(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_Z_FLAG); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_cs(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_C_FLAG); \ + condition_check = CONDITION_TRUE \ + +#define generate_condition_cc(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_C_FLAG); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_mi(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + condition_check = CONDITION_TRUE \ + +#define generate_condition_pl(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_vs(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_V_FLAG); \ + condition_check = CONDITION_TRUE \ + +#define generate_condition_vc(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_V_FLAG); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_hi(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_C_FLAG); \ + generate_xor_imm(ireg_a, 1); \ + generate_load_reg(ireg_b, REG_Z_FLAG); \ + generate_or(ireg_a, ireg_b); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_ls(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_C_FLAG); \ + generate_xor_imm(ireg_a, 1); \ + generate_load_reg(ireg_b, REG_Z_FLAG); \ + generate_or(ireg_a, ireg_b); \ + condition_check = CONDITION_TRUE \ + +#define generate_condition_ge(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + generate_load_reg(ireg_b, REG_V_FLAG); \ + condition_check = CONDITION_EQUAL \ + +#define generate_condition_lt(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + generate_load_reg(ireg_b, REG_V_FLAG); \ + condition_check = CONDITION_NOT_EQUAL \ + +#define generate_condition_gt(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + generate_load_reg(ireg_b, REG_V_FLAG); \ + generate_xor(ireg_b, ireg_a); \ + generate_load_reg(a0, REG_Z_FLAG); \ + generate_or(ireg_a, ireg_b); \ + condition_check = CONDITION_FALSE \ + +#define generate_condition_le(ireg_a, ireg_b) \ + generate_load_reg(ireg_a, REG_N_FLAG); \ + generate_load_reg(ireg_b, REG_V_FLAG); \ + generate_xor(ireg_b, ireg_a); \ + generate_load_reg(a0, REG_Z_FLAG); \ + generate_or(ireg_a, ireg_b); \ + condition_check = CONDITION_TRUE \ + + +#define generate_condition(ireg_a, ireg_b) \ + switch(condition) \ + { \ + case 0x0: \ + generate_condition_eq(ireg_a, ireg_b); \ + break; \ + \ + case 0x1: \ + generate_condition_ne(ireg_a, ireg_b); \ + break; \ + \ + case 0x2: \ + generate_condition_cs(ireg_a, ireg_b); \ + break; \ + \ + case 0x3: \ + generate_condition_cc(ireg_a, ireg_b); \ + break; \ + \ + case 0x4: \ + generate_condition_mi(ireg_a, ireg_b); \ + break; \ + \ + case 0x5: \ + generate_condition_pl(ireg_a, ireg_b); \ + break; \ + \ + case 0x6: \ + generate_condition_vs(ireg_a, ireg_b); \ + break; \ + \ + case 0x7: \ + generate_condition_vc(ireg_a, ireg_b); \ + break; \ + \ + case 0x8: \ + generate_condition_hi(ireg_a, ireg_b); \ + break; \ + \ + case 0x9: \ + generate_condition_ls(ireg_a, ireg_b); \ + break; \ + \ + case 0xA: \ + generate_condition_ge(ireg_a, ireg_b); \ + break; \ + \ + case 0xB: \ + generate_condition_lt(ireg_a, ireg_b); \ + break; \ + \ + case 0xC: \ + generate_condition_gt(ireg_a, ireg_b); \ + break; \ + \ + case 0xD: \ + generate_condition_le(ireg_a, ireg_b); \ + break; \ + \ + case 0xE: \ + /* AL */ \ + break; \ + \ + case 0xF: \ + /* Reserved */ \ + break; \ + } \ + generate_cycle_update() \ + +#define generate_conditional_branch_type(ireg_a, ireg_b) \ + switch(condition_check) \ + { \ + case CONDITION_TRUE: \ + generate_conditional_branch(ireg_a, ireg_b, true, backpatch_address); \ + break; \ + \ + case CONDITION_FALSE: \ + generate_conditional_branch(ireg_a, ireg_b, false, backpatch_address); \ + break; \ + \ + case CONDITION_EQUAL: \ + generate_conditional_branch(ireg_a, ireg_b, equal, backpatch_address); \ + break; \ + \ + case CONDITION_NOT_EQUAL: \ + generate_conditional_branch(ireg_a, ireg_b, not_equal, \ + backpatch_address); \ + break; \ + } \ + +#define generate_branch() \ +{ \ + if(condition == 0x0E) \ + { \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + } \ + else \ + { \ + generate_branch_no_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + } \ + block_exit_position++; \ +} \ + +#define rm_op_reg rm +#define rm_op_imm imm + +#define arm_data_proc_reg_flags() \ + arm_decode_data_proc_reg(); \ + if(flag_status & 0x02) \ + { \ + generate_load_rm_sh(flags) \ + } \ + else \ + { \ + generate_load_rm_sh(no_flags); \ + } \ + +#define arm_data_proc_reg() \ + arm_decode_data_proc_reg(); \ + generate_load_rm_sh(no_flags) \ + +#define arm_data_proc_imm() \ + arm_decode_data_proc_imm(); \ + ror(imm, imm, imm_ror); \ + generate_load_imm(a0, imm) \ + +#define arm_data_proc_imm_flags() \ + arm_decode_data_proc_imm(); \ + if((flag_status & 0x02) && (imm_ror != 0)) \ + { \ + /* Generate carry flag from integer rotation */ \ + generate_load_imm(a0, ((imm >> (imm_ror - 1)) & 0x01)); \ + generate_store_reg(a0, REG_C_FLAG); \ + } \ + ror(imm, imm, imm_ror); \ + generate_load_imm(a0, imm) \ + + +#define arm_data_proc(name, type, flags_op) \ +{ \ + arm_data_proc_##type(); \ + generate_load_reg_pc(a1, rn, 8); \ + generate_function_call(execute_##name); \ + generate_store_reg_pc_##flags_op(rv, rd); \ +} \ + +#define arm_data_proc_test(name, type) \ +{ \ + arm_data_proc_##type(); \ + generate_load_reg_pc(a1, rn, 8); \ + generate_function_call(execute_##name); \ +} \ + +#define arm_data_proc_unary(name, type, flags_op) \ +{ \ + arm_data_proc_##type(); \ + generate_function_call(execute_##name); \ + generate_store_reg_pc_##flags_op(rv, rd); \ +} \ + +#define arm_data_proc_mov(type) \ +{ \ + arm_data_proc_##type(); \ + generate_store_reg_pc_no_flags(a0, rd); \ +} \ + +u32 function_cc execute_mul_flags(u32 dest) +{ + calculate_z_flag(dest); + calculate_n_flag(dest); +} + +#define arm_multiply_flags_yes() \ + generate_function_call(execute_mul_flags) \ + +#define arm_multiply_flags_no(_dest) \ + +#define arm_multiply_add_no() \ + +#define arm_multiply_add_yes() \ + generate_load_reg(a1, rn); \ + generate_add(a0, a1) \ + +#define arm_multiply(add_op, flags) \ +{ \ + arm_decode_multiply(); \ + generate_load_reg(a0, rm); \ + generate_load_reg(a1, rs); \ + generate_multiply(a1); \ + arm_multiply_add_##add_op(); \ + generate_store_reg(a0, rd); \ + arm_multiply_flags_##flags(); \ +} \ + +u32 function_cc execute_mul_long_flags(u32 dest_lo, u32 dest_hi) +{ + reg[REG_Z_FLAG] = (dest_lo == 0) & (dest_hi == 0); + calculate_n_flag(dest_hi); +} + +#define arm_multiply_long_flags_yes() \ + generate_function_call(execute_mul_long_flags) \ + +#define arm_multiply_long_flags_no(_dest) \ + +#define arm_multiply_long_add_yes(name) \ + generate_load_reg(a2, rdlo); \ + generate_load_reg(s0, rdhi); \ + generate_multiply_##name(a1, a2, s0) \ + +#define arm_multiply_long_add_no(name) \ + generate_multiply_##name(a1) \ + +#define arm_multiply_long(name, add_op, flags) \ +{ \ + arm_decode_multiply_long(); \ + generate_load_reg(a0, rm); \ + generate_load_reg(a1, rs); \ + arm_multiply_long_add_##add_op(name); \ + generate_store_reg(a0, rdlo); \ + generate_store_reg(a1, rdhi); \ + arm_multiply_long_flags_##flags(); \ +} \ + +u32 function_cc execute_read_cpsr() +{ + collapse_flags(); + return reg[REG_CPSR]; +} + +u32 function_cc execute_read_spsr() +{ + collapse_flags(); + return spsr[reg[CPU_MODE]]; +} + +#define arm_psr_read(op_type, psr_reg) \ + generate_function_call(execute_read_##psr_reg); \ + generate_store_reg(rv, rd) \ + +// store_mask and address are stored in the SAVE slots, since there's no real +// register space to nicely pass them. + +u32 function_cc execute_store_cpsr_body(u32 _cpsr) +{ + reg[REG_CPSR] = _cpsr; + if(reg[REG_SAVE] & 0xFF) + { + set_cpu_mode(cpu_modes[_cpsr & 0x1F]); + if((io_registers[REG_IE] & io_registers[REG_IF]) && + io_registers[REG_IME] && ((_cpsr & 0x80) == 0)) + { + reg_mode[MODE_IRQ][6] = reg[REG_SAVE2] + 4; + spsr[MODE_IRQ] = _cpsr; + reg[REG_CPSR] = (_cpsr & 0xFFFFFF00) | 0xD2; + set_cpu_mode(MODE_IRQ); + return 0x00000018; + } + } + + return 0; +} + + +void function_cc execute_store_spsr(u32 new_spsr, u32 store_mask) +{ + u32 _spsr = spsr[reg[CPU_MODE]]; + spsr[reg[CPU_MODE]] = (new_spsr & store_mask) | (_spsr & (~store_mask)); +} + +#define arm_psr_load_new_reg() \ + generate_load_reg(a0, rm) \ + +#define arm_psr_load_new_imm() \ + ror(imm, imm, imm_ror); \ + generate_load_imm(a0, imm) \ + +#define arm_psr_store(op_type, psr_reg) \ + arm_psr_load_new_##op_type(); \ + generate_load_imm(a1, psr_masks[psr_field]); \ + generate_load_pc(a2, (pc + 4)); \ + generate_function_call(execute_store_##psr_reg) \ + +#define arm_psr(op_type, transfer_type, psr_reg) \ +{ \ + arm_decode_psr_##op_type(); \ + arm_psr_##transfer_type(op_type, psr_reg); \ +} \ + +#define aligned_address_mask8 0xF0000000 +#define aligned_address_mask16 0xF0000001 +#define aligned_address_mask32 0xF0000003 + +#define read_memory(size, type, address, dest) \ +{ \ + u8 *map; \ + \ + if(((address >> 24) == 0) && (reg[REG_PC] >= 0x4000)) \ + { \ + dest = *((type *)((u8 *)&bios_read_protect + (address & 0x03))); \ + } \ + else \ + \ + if(((address & aligned_address_mask##size) == 0) && \ + (map = memory_map_read[address >> 15])) \ + { \ + dest = *((type *)((u8 *)map + (address & 0x7FFF))); \ + } \ + else \ + { \ + dest = (type)read_memory##size(address); \ + } \ +} \ + +#define read_memory_s16(address, dest) \ +{ \ + u8 *map; \ + \ + if(((address >> 24) == 0) && (reg[REG_PC] >= 0x4000)) \ + { \ + dest = *((s16 *)((u8 *)&bios_read_protect + (address & 0x03))); \ + } \ + else \ + \ + if(((address & aligned_address_mask16) == 0) && \ + (map = memory_map_read[address >> 15])) \ + { \ + dest = *((s16 *)((u8 *)map + (address & 0x7FFF))); \ + } \ + else \ + { \ + dest = (s16)read_memory16_signed(address); \ + } \ +} \ + +#define access_memory_generate_read_function(mem_size, mem_type) \ +u32 function_cc execute_load_##mem_type(u32 address) \ +{ \ + u32 dest; \ + read_memory(mem_size, mem_type, address, dest); \ + return dest; \ +} \ + +access_memory_generate_read_function(8, u8); +access_memory_generate_read_function(8, s8); +access_memory_generate_read_function(16, u16); +access_memory_generate_read_function(32, u32); + +u32 function_cc execute_load_s16(u32 address) +{ + u32 dest; + read_memory_s16(address, dest); + return dest; +} + +#define access_memory_generate_write_function(mem_size, mem_type) \ +void function_cc execute_store_##mem_type(u32 address, u32 source) \ +{ \ + u8 *map; \ + \ + if(((address & aligned_address_mask##mem_size) == 0) && \ + (map = memory_map_write[address >> 15])) \ + { \ + *((mem_type *)((u8 *)map + (address & 0x7FFF))) = source; \ + } \ + else \ + { \ + write_memory##mem_size(address, source); \ + } \ +} \ + +#define arm_access_memory_load(mem_type) \ + cycle_count += 2; \ + generate_function_call(execute_load_##mem_type); \ + generate_store_reg_pc_no_flags(rv, rd) \ + +#define arm_access_memory_store(mem_type) \ + cycle_count++; \ + generate_load_reg_pc(a1, rd, 12); \ + generate_load_pc(a2, (pc + 4)); \ + generate_function_call(execute_store_##mem_type) \ + +#define no_op \ + +#define arm_access_memory_writeback_yes(off_op) \ + reg[rn] = address off_op \ + +#define arm_access_memory_writeback_no(off_op) \ + +#define load_reg_op reg[rd] \ + +#define store_reg_op reg_op \ + +#define arm_access_memory_adjust_op_up add +#define arm_access_memory_adjust_op_down sub +#define arm_access_memory_reverse_op_up sub +#define arm_access_memory_reverse_op_down add + +#define arm_access_memory_reg_pre(adjust_dir_op, reverse_dir_op) \ + generate_load_reg_pc(a0, rn, 8); \ + generate_##adjust_dir_op(a0, a1) \ + +#define arm_access_memory_reg_pre_wb(adjust_dir_op, reverse_dir_op) \ + arm_access_memory_reg_pre(adjust_dir_op, reverse_dir_op); \ + generate_store_reg(a0, rn) \ + +#define arm_access_memory_reg_post(adjust_dir_op, reverse_dir_op) \ + generate_load_reg(a0, rn); \ + generate_##adjust_dir_op(a0, a1); \ + generate_store_reg(a0, rn); \ + generate_##reverse_dir_op(a0, a1) \ + +#define arm_access_memory_imm_pre(adjust_dir_op, reverse_dir_op) \ + generate_load_reg_pc(a0, rn, 8); \ + generate_##adjust_dir_op##_imm(a0, offset) \ + +#define arm_access_memory_imm_pre_wb(adjust_dir_op, reverse_dir_op) \ + arm_access_memory_imm_pre(adjust_dir_op, reverse_dir_op); \ + generate_store_reg(a0, rn) \ + +#define arm_access_memory_imm_post(adjust_dir_op, reverse_dir_op) \ + generate_load_reg(a0, rn); \ + generate_##adjust_dir_op##_imm(a0, offset); \ + generate_store_reg(a0, rn); \ + generate_##reverse_dir_op##_imm(a0, offset) \ + + +#define arm_data_trans_reg(adjust_op, adjust_dir_op, reverse_dir_op) \ + arm_decode_data_trans_reg(); \ + generate_load_offset_sh(); \ + arm_access_memory_reg_##adjust_op(adjust_dir_op, reverse_dir_op) \ + +#define arm_data_trans_imm(adjust_op, adjust_dir_op, reverse_dir_op) \ + arm_decode_data_trans_imm(); \ + arm_access_memory_imm_##adjust_op(adjust_dir_op, reverse_dir_op) \ + +#define arm_data_trans_half_reg(adjust_op, adjust_dir_op, reverse_dir_op) \ + arm_decode_half_trans_r(); \ + generate_load_reg(a1, rm); \ + arm_access_memory_reg_##adjust_op(adjust_dir_op, reverse_dir_op) \ + +#define arm_data_trans_half_imm(adjust_op, adjust_dir_op, reverse_dir_op) \ + arm_decode_half_trans_of(); \ + arm_access_memory_imm_##adjust_op(adjust_dir_op, reverse_dir_op) \ + +#define arm_access_memory(access_type, direction, adjust_op, mem_type, \ + offset_type) \ +{ \ + arm_data_trans_##offset_type(adjust_op, \ + arm_access_memory_adjust_op_##direction, \ + arm_access_memory_reverse_op_##direction); \ + \ + arm_access_memory_##access_type(mem_type); \ +} \ + +#define word_bit_count(word) \ + (bit_count[word >> 8] + bit_count[word & 0xFF]) \ + +#define sprint_no(access_type, pre_op, post_op, wb) \ + +#define sprint_yes(access_type, pre_op, post_op, wb) \ + printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \ + +u32 function_cc execute_aligned_load32(u32 address) +{ + u8 *map; + if(!(address & 0xF0000000) && (map = memory_map_read[address >> 15])) + return address32(map, address & 0x7FFF); + else + return read_memory32(address); +} + +void function_cc execute_aligned_store32(u32 address, u32 source) +{ + u8 *map; + + if(!(address & 0xF0000000) && (map = memory_map_write[address >> 15])) + address32(map, address & 0x7FFF) = source; + else + write_memory32(address, source); +} + +#define arm_block_memory_load() \ + generate_function_call(execute_aligned_load32); \ + generate_store_reg(rv, i) \ + +#define arm_block_memory_store() \ + generate_load_reg_pc(a1, i, 8); \ + generate_function_call(execute_aligned_store32) \ + +#define arm_block_memory_final_load() \ + arm_block_memory_load() \ + +#define arm_block_memory_final_store() \ + generate_load_reg_pc(a1, i, 12); \ + generate_load_pc(a2, (pc + 4)); \ + generate_function_call(execute_store_u32) \ + +#define arm_block_memory_adjust_pc_store() \ + +#define arm_block_memory_adjust_pc_load() \ + if(reg_list & 0x8000) \ + { \ + generate_mov(a0, rv); \ + generate_indirect_branch_arm(); \ + } \ + +#define arm_block_memory_offset_down_a() \ + generate_add_imm(s0, -((word_bit_count(reg_list) * 4) - 4)) \ + +#define arm_block_memory_offset_down_b() \ + generate_add_imm(s0, -(word_bit_count(reg_list) * 4)) \ + +#define arm_block_memory_offset_no() \ + +#define arm_block_memory_offset_up() \ + generate_add_imm(s0, 4) \ + +#define arm_block_memory_writeback_down() \ + generate_load_reg(a0, rn) \ + generate_add_imm(a0, -(word_bit_count(reg_list) * 4)); \ + generate_store_reg(a0, rn) \ + +#define arm_block_memory_writeback_up() \ + generate_load_reg(a0, rn); \ + generate_add_imm(a0, (word_bit_count(reg_list) * 4)); \ + generate_store_reg(a0, rn) \ + +#define arm_block_memory_writeback_no() + +// Only emit writeback if the register is not in the list + +#define arm_block_memory_writeback_load(writeback_type) \ + if(!((reg_list >> rn) & 0x01)) \ + { \ + arm_block_memory_writeback_##writeback_type(); \ + } \ + +#define arm_block_memory_writeback_store(writeback_type) \ + arm_block_memory_writeback_##writeback_type() \ + +#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \ +{ \ + arm_decode_block_trans(); \ + u32 offset = 0; \ + u32 i; \ + \ + generate_load_reg(s0, rn); \ + arm_block_memory_offset_##offset_type(); \ + arm_block_memory_writeback_##access_type(writeback_type); \ + generate_and_imm(s0, ~0x03); \ + \ + for(i = 0; i < 16; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + generate_add_reg_reg_imm(a0, s0, offset) \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + arm_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + arm_block_memory_final_##access_type(); \ + } \ + } \ + } \ + \ + arm_block_memory_adjust_pc_##access_type(); \ +} \ + +#define arm_swap(type) \ +{ \ + arm_decode_swap(); \ + cycle_count += 3; \ + generate_load_reg(a0, rn); \ + generate_function_call(execute_load_##type); \ + generate_mov(s0, rv); \ + generate_load_reg(a0, rn); \ + generate_load_reg(a1, rm); \ + generate_function_call(execute_store_##type); \ + generate_store_reg(s0, rd); \ +} \ + +#define thumb_rn_op_reg(_rn) \ + generate_load_reg(a0, _rn) \ + +#define thumb_rn_op_imm(_imm) \ + generate_load_imm(a0, _imm) \ + +// Types: add_sub, add_sub_imm, alu_op, imm +// Affects N/Z/C/V flags + +#define thumb_data_proc(type, name, rn_type, _rd, _rs, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_rn_op_##rn_type(_rn); \ + generate_load_reg(a1, _rs); \ + generate_function_call(execute_##name); \ + generate_store_reg(rv, _rd); \ +} \ + +#define thumb_data_proc_test(type, name, rn_type, _rs, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_rn_op_##rn_type(_rn); \ + generate_load_reg(a1, _rs); \ + generate_function_call(execute_##name); \ +} \ + +#define thumb_data_proc_unary(type, name, rn_type, _rd, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_rn_op_##rn_type(_rn); \ + generate_function_call(execute_##name); \ + generate_store_reg(rv, _rd); \ +} \ + +#define thumb_data_proc_mov(type, rn_type, _rd, _rn) \ +{ \ + thumb_decode_##type(); \ + thumb_rn_op_##rn_type(_rn); \ + generate_store_reg(a0, _rd); \ +} \ + +#define generate_store_reg_pc_thumb(ireg) \ + generate_store_reg(ireg, rd); \ + if(rd == 15) \ + { \ + generate_indirect_branch_cycle_update(thumb); \ + } \ + +#define thumb_data_proc_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(a0, rs, 4); \ + generate_load_reg_pc(a1, rd, 4); \ + generate_function_call(execute_##name); \ + generate_store_reg_pc_thumb(rv); \ +} \ + +#define thumb_data_proc_test_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(a0, rs, 4); \ + generate_load_reg_pc(a1, rd, 4); \ + generate_function_call(execute_##name); \ +} \ + +#define thumb_data_proc_unary_hi(name) \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(a0, rn, 4); \ + generate_function_call(execute_##name); \ + generate_store_reg_pc_thumb(rv); \ +} \ + +#define thumb_data_proc_mov_hi() \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(a0, rs, 4); \ + generate_store_reg_pc_thumb(a0); \ +} \ + +#define thumb_load_pc(_rd) \ +{ \ + thumb_decode_imm(); \ + generate_load_pc(a0, (((pc & ~2) + 4) + (imm * 4))); \ + generate_store_reg(a0, _rd); \ +} \ + +#define thumb_load_sp(_rd) \ +{ \ + thumb_decode_imm(); \ + generate_load_reg(a0, 13); \ + generate_add_imm(a0, (imm * 4)); \ + generate_store_reg(a0, _rd); \ +} \ + +#define thumb_adjust_sp_up() \ + generate_add_imm(a0, imm * 4) \ + +#define thumb_adjust_sp_down() \ + generate_sub_imm(a0, imm * 4) \ + + +#define thumb_adjust_sp(direction) \ +{ \ + thumb_decode_add_sp(); \ + generate_load_reg(a0, REG_SP); \ + thumb_adjust_sp_##direction(); \ + generate_store_reg(a0, REG_SP); \ +} \ + +// Decode types: shift, alu_op +// Operation types: lsl, lsr, asr, ror +// Affects N/Z/C flags + +u32 function_cc execute_lsl_reg_op(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + if(shift == 32) + reg[REG_C_FLAG] = value & 0x01; + else + reg[REG_C_FLAG] = 0; + + value = 0; + } + else + { + reg[REG_C_FLAG] = (value >> (32 - shift)) & 0x01; + value <<= shift; + } + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_lsr_reg_op(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + if(shift == 32) + reg[REG_C_FLAG] = (value >> 31) & 0x01; + else + reg[REG_C_FLAG] = 0; + + value = 0; + } + else + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value >>= shift; + } + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_asr_reg_op(u32 value, u32 shift) +{ + if(shift != 0) + { + if(shift > 31) + { + value = (s32)value >> 31; + reg[REG_C_FLAG] = value & 0x01; + } + else + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value = (s32)value >> shift; + } + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_ror_reg_op(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + ror(value, value, shift); + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_lsl_imm_op(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (32 - shift)) & 0x01; + value <<= shift; + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_lsr_imm_op(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value >>= shift; + } + else + { + reg[REG_C_FLAG] = value >> 31; + value = 0; + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_asr_imm_op(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + value = (s32)value >> shift; + } + else + { + value = (s32)value >> 31; + reg[REG_C_FLAG] = value & 0x01; + } + + calculate_flags_logic(value); + return value; +} + +u32 function_cc execute_ror_imm_op(u32 value, u32 shift) +{ + if(shift != 0) + { + reg[REG_C_FLAG] = (value >> (shift - 1)) & 0x01; + ror(value, value, shift); + } + else + { + u32 c_flag = reg[REG_C_FLAG]; + reg[REG_C_FLAG] = value & 0x01; + value = (value >> 1) | (c_flag << 31); + } + + calculate_flags_logic(value); + return value; +} + +#define generate_shift_load_operands_reg() \ + generate_load_reg(a0, rd); \ + generate_load_reg(a1, rs) \ + +#define generate_shift_load_operands_imm() \ + generate_load_reg(a0, rs); \ + generate_load_imm(a1, imm) \ + +#define thumb_shift(decode_type, op_type, value_type) \ +{ \ + thumb_decode_##decode_type(); \ + generate_shift_load_operands_##value_type(); \ + generate_function_call(execute_##op_type##_##value_type##_op); \ + generate_store_reg(rv, rd); \ +} \ + +// Operation types: imm, mem_reg, mem_imm + +#define thumb_access_memory_load(mem_type, reg_rd) \ + cycle_count += 2; \ + generate_function_call(execute_load_##mem_type); \ + generate_store_reg(rv, reg_rd) \ + +#define thumb_access_memory_store(mem_type, reg_rd) \ + cycle_count++; \ + generate_load_reg(a1, reg_rd); \ + generate_load_pc(a2, (pc + 2)); \ + generate_function_call(execute_store_##mem_type) \ + +#define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro) \ + generate_load_pc(a0, (offset)) \ + +#define thumb_access_memory_generate_address_reg_imm_sp(offset, _rb, _ro) \ + generate_load_reg(a0, _rb); \ + generate_add_imm(a0, (offset * 4)) \ + +#define thumb_access_memory_generate_address_reg_imm(offset, _rb, _ro) \ + generate_load_reg(a0, _rb); \ + generate_add_imm(a0, (offset)) \ + +#define thumb_access_memory_generate_address_reg_reg(offset, _rb, _ro) \ + generate_load_reg(a0, _rb); \ + generate_load_reg(a1, _ro); \ + generate_add(a0, a1) \ + +#define thumb_access_memory(access_type, op_type, _rd, _rb, _ro, \ + address_type, offset, mem_type) \ +{ \ + thumb_decode_##op_type(); \ + thumb_access_memory_generate_address_##address_type(offset, _rb, _ro); \ + thumb_access_memory_##access_type(mem_type, _rd); \ +} \ + +#define thumb_block_address_preadjust_up() \ + generate_add_imm(s0, (bit_count[reg_list] * 4)) \ + +#define thumb_block_address_preadjust_down() \ + generate_sub_imm(s0, (bit_count[reg_list] * 4)) \ + +#define thumb_block_address_preadjust_push_lr() \ + generate_sub_imm(s0, ((bit_count[reg_list] + 1) * 4)) \ + +#define thumb_block_address_preadjust_no() \ + +#define thumb_block_address_postadjust_no(base_reg) \ + generate_store_reg(s0, base_reg) \ + +#define thumb_block_address_postadjust_up(base_reg) \ + generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \ + generate_store_reg(a0, base_reg) \ + +#define thumb_block_address_postadjust_down(base_reg) \ + generate_mov(a0, s0); \ + generate_sub_imm(a0, (bit_count[reg_list] * 4)); \ + generate_store_reg(a0, base_reg) \ + +#define thumb_block_address_postadjust_pop_pc(base_reg) \ + generate_add_reg_reg_imm(a0, s0, ((bit_count[reg_list] + 1) * 4)); \ + generate_store_reg(a0, base_reg) \ + +#define thumb_block_address_postadjust_push_lr(base_reg) \ + generate_store_reg(s0, base_reg) \ + +#define thumb_block_memory_extra_no() \ + +#define thumb_block_memory_extra_up() \ + +#define thumb_block_memory_extra_down() \ + +#define thumb_block_memory_extra_pop_pc() \ + generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \ + generate_function_call(execute_aligned_load32); \ + generate_store_reg(rv, REG_PC); \ + generate_mov(a0, rv); \ + generate_indirect_branch_cycle_update(thumb) \ + +#define thumb_block_memory_extra_push_lr(base_reg) \ + generate_add_reg_reg_imm(a0, s0, (bit_count[reg_list] * 4)); \ + generate_load_reg(a1, REG_LR); \ + generate_function_call(execute_aligned_store32) \ + +#define thumb_block_memory_load() \ + generate_function_call(execute_aligned_load32); \ + generate_store_reg(rv, i) \ + +#define thumb_block_memory_store() \ + generate_load_reg(a1, i); \ + generate_function_call(execute_aligned_store32) \ + +#define thumb_block_memory_final_load() \ + thumb_block_memory_load() \ + +#define thumb_block_memory_final_store() \ + generate_load_reg(a1, i); \ + generate_load_pc(a2, (pc + 2)); \ + generate_function_call(execute_store_u32) \ + +#define thumb_block_memory_final_no(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_up(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_down(access_type) \ + thumb_block_memory_final_##access_type() \ + +#define thumb_block_memory_final_push_lr(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory_final_pop_pc(access_type) \ + thumb_block_memory_##access_type() \ + +#define thumb_block_memory(access_type, pre_op, post_op, base_reg) \ +{ \ + thumb_decode_rlist(); \ + u32 i; \ + u32 offset = 0; \ + \ + generate_load_reg(s0, base_reg); \ + generate_and_imm(s0, ~0x03); \ + thumb_block_address_preadjust_##pre_op(); \ + thumb_block_address_postadjust_##post_op(base_reg); \ + \ + for(i = 0; i < 8; i++) \ + { \ + if((reg_list >> i) & 0x01) \ + { \ + cycle_count++; \ + generate_add_reg_reg_imm(a0, s0, offset) \ + if(reg_list & ~((2 << i) - 1)) \ + { \ + thumb_block_memory_##access_type(); \ + offset += 4; \ + } \ + else \ + { \ + thumb_block_memory_final_##post_op(access_type); \ + } \ + } \ + } \ + \ + thumb_block_memory_extra_##post_op(); \ +} \ + + +#define thumb_conditional_branch(condition) \ +{ \ + condition_check_type condition_check; \ + generate_cycle_update(); \ + generate_condition_##condition(a0, a1); \ + generate_conditional_branch_type(a0, a1); \ + generate_branch_no_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + generate_branch_patch_conditional(backpatch_address, translation_ptr); \ + block_exit_position++; \ +} \ + +#define flags_vars(src_a, src_b) \ + u32 dest; \ + const u32 _sa = src_a; \ + const u32 _sb = src_b \ + +#define data_proc_generate_logic_function(name, expr) \ +u32 function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + return expr; \ +} \ + \ +u32 function_cc execute_##name##s(u32 rm, u32 rn) \ +{ \ + u32 dest = expr; \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + return expr; \ +} \ + +#define data_proc_generate_logic_unary_function(name, expr) \ +u32 function_cc execute_##name(u32 rm) \ +{ \ + return expr; \ +} \ + \ +u32 function_cc execute_##name##s(u32 rm) \ +{ \ + u32 dest = expr; \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ + return expr; \ +} \ + + +#define data_proc_generate_sub_function(name, src_a, src_b) \ +u32 function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + return (src_a) - (src_b); \ +} \ + \ +u32 function_cc execute_##name##s(u32 rm, u32 rn) \ +{ \ + flags_vars(src_a, src_b); \ + dest = _sa - _sb; \ + calculate_flags_sub(dest, _sa, _sb); \ + return dest; \ +} \ + +#define data_proc_generate_add_function(name, src_a, src_b) \ +u32 function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + return (src_a) + (src_b); \ +} \ + \ +u32 function_cc execute_##name##s(u32 rm, u32 rn) \ +{ \ + flags_vars(src_a, src_b); \ + dest = _sa + _sb; \ + calculate_flags_add(dest, _sa, _sb); \ + return dest; \ +} \ + +#define data_proc_generate_sub_test_function(name, src_a, src_b) \ +void function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + flags_vars(src_a, src_b); \ + dest = _sa - _sb; \ + calculate_flags_sub(dest, _sa, _sb); \ +} \ + +#define data_proc_generate_add_test_function(name, src_a, src_b) \ +void function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + flags_vars(src_a, src_b); \ + dest = _sa + _sb; \ + calculate_flags_add(dest, _sa, _sb); \ +} \ + +#define data_proc_generate_logic_test_function(name, expr) \ +void function_cc execute_##name(u32 rm, u32 rn) \ +{ \ + u32 dest = expr; \ + calculate_z_flag(dest); \ + calculate_n_flag(dest); \ +} \ + +u32 function_cc execute_neg(u32 rm) \ +{ \ + u32 dest = 0 - rm; \ + calculate_flags_sub(dest, 0, rm); \ + return dest; \ +} \ + +// Execute functions + +data_proc_generate_logic_function(and, rn & rm); +data_proc_generate_logic_function(eor, rn ^ rm); +data_proc_generate_logic_function(orr, rn | rm); +data_proc_generate_logic_function(bic, rn & (~rm)); +data_proc_generate_logic_function(mul, rn * rm); +data_proc_generate_logic_unary_function(mov, rm); +data_proc_generate_logic_unary_function(mvn, ~rm); + +data_proc_generate_sub_function(sub, rn, rm); +data_proc_generate_sub_function(rsb, rm, rn); +data_proc_generate_sub_function(sbc, rn, (rm + (reg[REG_C_FLAG] ^ 1))); +data_proc_generate_sub_function(rsc, (rm + reg[REG_C_FLAG] - 1), rn); +data_proc_generate_add_function(add, rn, rm); +data_proc_generate_add_function(adc, rn, rm + reg[REG_C_FLAG]); + +data_proc_generate_logic_test_function(tst, rn & rm); +data_proc_generate_logic_test_function(teq, rn ^ rm); +data_proc_generate_sub_test_function(cmp, rn, rm); +data_proc_generate_add_test_function(cmn, rn, rm); + +u32 function_cc execute_swi(u32 pc) +{ + reg_mode[MODE_SUPERVISOR][6] = pc; + collapse_flags(); + spsr[MODE_SUPERVISOR] = reg[REG_CPSR]; + reg[REG_CPSR] = (reg[REG_CPSR] & ~0x3F) | 0x13; + set_cpu_mode(MODE_SUPERVISOR); +} + +#define arm_conditional_block_header() \ +{ \ + condition_check_type condition_check; \ + generate_condition(a0, a1); \ + generate_conditional_branch_type(a0, a1); \ +} + +#define arm_b() \ + generate_branch() \ + +#define arm_bl() \ + generate_update_pc((pc + 4)); \ + generate_store_reg(a0, REG_LR); \ + generate_branch() \ + +#define arm_bx() \ + arm_decode_branchx(); \ + generate_load_reg(a0, rn); \ + generate_indirect_branch_dual(); \ + +#define arm_swi() \ + generate_swi_hle_handler((opcode >> 16) & 0xFF); \ + generate_update_pc((pc + 4)); \ + generate_function_call(execute_swi); \ + generate_branch() \ + +#define thumb_b() \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +#define thumb_bl() \ + generate_update_pc(((pc + 2) | 0x01)); \ + generate_store_reg(a0, REG_LR); \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +#define thumb_blh() \ +{ \ + thumb_decode_branch(); \ + generate_update_pc(((pc + 2) | 0x01)); \ + generate_load_reg(a1, REG_LR); \ + generate_store_reg(a0, REG_LR); \ + generate_mov(a0, a1); \ + generate_add_imm(a0, (offset * 2)); \ + generate_indirect_branch_cycle_update(thumb); \ +} \ + +#define thumb_bx() \ +{ \ + thumb_decode_hireg_op(); \ + generate_load_reg_pc(a0, rs, 4); \ + generate_indirect_branch_cycle_update(dual); \ +} \ + +#define thumb_swi() \ + generate_swi_hle_handler(opcode & 0xFF); \ + generate_update_pc((pc + 2)); \ + generate_function_call(execute_swi); \ + generate_branch_cycle_update( \ + block_exits[block_exit_position].branch_source, \ + block_exits[block_exit_position].branch_target); \ + block_exit_position++ \ + +u8 swi_hle_handle[256] = +{ + 0x0, // SWI 0: SoftReset + 0x0, // SWI 1: RegisterRAMReset + 0x0, // SWI 2: Halt + 0x0, // SWI 3: Stop/Sleep + 0x0, // SWI 4: IntrWait + 0x0, // SWI 5: VBlankIntrWait + 0x1, // SWI 6: Div + 0x0, // SWI 7: DivArm + 0x0, // SWI 8: Sqrt + 0x0, // SWI 9: ArcTan + 0x0, // SWI A: ArcTan2 + 0x0, // SWI B: CpuSet + 0x0, // SWI C: CpuFastSet + 0x0, // SWI D: GetBIOSCheckSum + 0x0, // SWI E: BgAffineSet + 0x0, // SWI F: ObjAffineSet + 0x0, // SWI 10: BitUnpack + 0x0, // SWI 11: LZ77UnCompWram + 0x0, // SWI 12: LZ77UnCompVram + 0x0, // SWI 13: HuffUnComp + 0x0, // SWI 14: RLUnCompWram + 0x0, // SWI 15: RLUnCompVram + 0x0, // SWI 16: Diff8bitUnFilterWram + 0x0, // SWI 17: Diff8bitUnFilterVram + 0x0, // SWI 18: Diff16bitUnFilter + 0x0, // SWI 19: SoundBias + 0x0, // SWI 1A: SoundDriverInit + 0x0, // SWI 1B: SoundDriverMode + 0x0, // SWI 1C: SoundDriverMain + 0x0, // SWI 1D: SoundDriverVSync + 0x0, // SWI 1E: SoundChannelClear + 0x0, // SWI 1F: MidiKey2Freq + 0x0, // SWI 20: SoundWhatever0 + 0x0, // SWI 21: SoundWhatever1 + 0x0, // SWI 22: SoundWhatever2 + 0x0, // SWI 23: SoundWhatever3 + 0x0, // SWI 24: SoundWhatever4 + 0x0, // SWI 25: MultiBoot + 0x0, // SWI 26: HardReset + 0x0, // SWI 27: CustomHalt + 0x0, // SWI 28: SoundDriverVSyncOff + 0x0, // SWI 29: SoundDriverVSyncOn + 0x0 // SWI 2A: SoundGetJumpList +}; + +void function_cc swi_hle_div() +{ + s32 result = (s32)reg[0] / (s32)reg[1]; + reg[1] = (s32)reg[0] % (s32)reg[1]; + reg[0] = result; + reg[3] = (result ^ (result >> 31)) - (result >> 31); +} + +#define generate_swi_hle_handler(_swi_number) \ +{ \ + u32 swi_number = _swi_number; \ + if(swi_hle_handle[swi_number]) \ + { \ + /* Div */ \ + if(swi_number == 0x06) \ + { \ + generate_function_call(swi_hle_div); \ + } \ + break; \ + } \ +} \ + +#define generate_translation_gate(type) \ + generate_update_pc(pc); \ + generate_indirect_branch_no_cycle_update(type) \ + +#define generate_step_debug() \ + generate_load_imm(a0, pc); \ + generate_function_call(step_debug_x86) \ + +#endif diff --git a/x86/x86_stub.S b/x86/x86_stub.S new file mode 100644 index 0000000..8fc16b7 --- /dev/null +++ b/x86/x86_stub.S @@ -0,0 +1,501 @@ +# gameplaySP +# +# Copyright (C) 2006 Exophase +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +.align 4 + +.global _x86_update_gba +.global _x86_indirect_branch_arm +.global _x86_indirect_branch_thumb +.global _x86_indirect_branch_dual +.global _execute_store_u8 +.global _execute_store_u16 +.global _execute_store_u32 +.global _execute_store_cpsr +.global _execute_arm_translate +.global _step_debug_x86 + +.global _memory_map_read +.global _memory_map_write +.global _reg + +.global _oam_update + +.global _iwram +.global _ewram +.global _vram +.global _oam_ram +.global _bios_rom +.global _io_registers + +.extern _spsr + +.equ REG_SP, (13 * 4) +.equ REG_LR, (14 * 4) +.equ REG_PC, (15 * 4) +.equ REG_N_FLAG, (16 * 4) +.equ REG_Z_FLAG, (17 * 4) +.equ REG_C_FLAG, (18 * 4) +.equ REG_V_FLAG, (19 * 4) +.equ REG_CPSR, (20 * 4) +.equ REG_SAVE, (21 * 4) +.equ REG_SAVE2, (22 * 4) +.equ REG_SAVE3, (23 * 4) +.equ CPU_MODE, (29 * 4) +.equ CPU_HALT_STATE, (30 * 4) +.equ CHANGED_PC_STATUS, (31 * 4) + +# destroys ecx and edx + +.macro collapse_flag offset, shift + mov \offset(%ebx), %ecx + shl $\shift, %ecx + or %ecx, %edx +.endm + +.macro collapse_flags_no_update + xor %edx, %edx + collapse_flag REG_N_FLAG, 31 + collapse_flag REG_Z_FLAG, 30 + collapse_flag REG_C_FLAG, 29 + collapse_flag REG_V_FLAG, 28 + mov REG_CPSR(%ebx), %ecx + and $0xFF, %ecx + or %ecx, %edx +.endm + + +.macro collapse_flags + collapse_flags_no_update + mov %edx, REG_CPSR(%ebx) +.endm + +.macro extract_flag shift, offset + mov REG_CPSR(%ebx), %edx + shr $\shift, %edx + and $0x01, %edx + mov %edx, _reg + \offset +.endm + +.macro extract_flags + extract_flag 31, REG_N_FLAG + extract_flag 30, REG_Z_FLAG + extract_flag 29, REG_C_FLAG + extract_flag 28, REG_V_FLAG +.endm + +# Process a hardware event. Since an interrupt might be +# raised we have to check if the PC has changed. + +# eax: current address + +st: + .asciz "u\n" + +_x86_update_gba: + mov %eax, REG_PC(%ebx) # current PC = eax + collapse_flags # update cpsr, trashes ecx and edx + + call _update_gba # process the next event + + mov %eax, %edi # edi = new cycle count + # did the PC change? + cmpl $1, CHANGED_PC_STATUS(%ebx) + je lookup_pc + ret # if not, go back to caller + +# Perform this on an indirect branch that will definitely go to +# ARM code, IE anything that changes the PC in ARM mode except +# for BX and data processing to PC with the S bit set. + +# eax: GBA address to branch to +# edi: Cycle counter + +_x86_indirect_branch_arm: + call _block_lookup_address_arm + jmp *%eax + +# For indirect branches that'll definitely go to Thumb. In +# Thumb mode any indirect branches except for BX. + +_x86_indirect_branch_thumb: + call _block_lookup_address_thumb + jmp *%eax + +# For indirect branches that can go to either Thumb or ARM, +# mainly BX (also data processing to PC with S bit set, be +# sure to adjust the target with a 1 in the lowest bit for this) + +_x86_indirect_branch_dual: + call _block_lookup_address_dual + jmp *%eax + + +# General ext memory routines + +ext_store_ignore: + ret # ignore these writes + +write_epilogue: + cmp $0, %eax # 0 return means nothing happened + jz no_alert # if so we can leave + + collapse_flags # make sure flags are good for function call + cmp $2, %eax # see if it was an SMC trigger + je smc_write + +alert_loop: + call _update_gba # process the next event + + # see if the halt status has changed + mov CPU_HALT_STATE(%ebx), %edx + + cmp $0, %edx # 0 means it has + jnz alert_loop # if not go again + + mov %eax, %edi # edi = new cycle count + jmp lookup_pc # pc has definitely changed + +no_alert: + ret + +ext_store_eeprom: + jmp _write_eeprom # perform eeprom write + + +# 8bit ext memory routines + +ext_store_io8: + and $0x3FF, %eax # wrap around address + and $0xFF, %edx + call _write_io_register8 # perform 8bit I/O register write + jmp write_epilogue # see if it requires any system update + +ext_store_palette8: + and $0x3FE, %eax # wrap around address and align to 16bits + jmp ext_store_palette16b # perform 16bit palette write + +ext_store_vram8: + and $0x1FFFE, %eax # wrap around address and align to 16bits + mov %dl, %dh # copy lower 8bits of value into full 16bits + cmp $0x18000, %eax # see if address is in upper region + jb ext_store_vram8b + sub $0x8000, %eax # if so wrap down + +ext_store_vram8b: + mov %dx, _vram(%eax) # perform 16bit store + ret + +ext_store_oam8: + movl $1, _oam_update # flag OAM update + and $0x3FE, %eax # wrap around address and align to 16bits + mov %dl, %dh # copy lower 8bits of value into full 16bits + mov %dx, _oam_ram(%eax) # perform 16bit store + ret + +ext_store_backup: + and $0xFF, %edx # make value 8bit + and $0xFFFF, %eax # mask address + jmp _write_backup # perform backup write + +ext_store_u8_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io8 # 0x04 I/O registers + .long ext_store_palette8 # 0x05 Palette RAM + .long ext_store_vram8 # 0x06 VRAM + .long ext_store_oam8 # 0x07 OAM RAM + .long ext_store_ignore # 0x08 gamepak (no RTC accepted in 8bit) + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_backup # 0x0E Flash ROM/SRAM + +ext_store_u8: + mov %eax, %ecx # ecx = address + shr $24, %ecx # ecx = address >> 24 + cmp $15, %ecx + ja ext_store_ignore + # ecx = ext_store_u8_jtable[address >> 24] + mov ext_store_u8_jtable(, %ecx, 4), %ecx + jmp *%ecx # jump to table index + +# eax: address to write to +# edx: value to write +# ecx: current pc + +_execute_store_u8: + mov %ecx, REG_PC(%ebx) # write out the PC + mov %eax, %ecx # ecx = address + test $0xF0000000, %ecx # check address range + jnz ext_store_u8 # if above perform an extended write + shr $15, %ecx # ecx = page number of address + # load the corresponding memory map offset + mov _memory_map_write(, %ecx, 4), %ecx + test %ecx, %ecx # see if it's NULL + jz ext_store_u8 # if so perform an extended write + and $0x7FFF, %eax # isolate the lower 15bits of the address + mov %dl, (%eax, %ecx) # store the value + # check for self-modifying code + testb $0xFF, -32768(%eax, %ecx) + jne smc_write + ret # return + +_execute_store_u16: + mov %ecx, REG_PC(%ebx) # write out the PC + and $~0x01, %eax # fix alignment + mov %eax, %ecx # ecx = address + test $0xF0000000, %ecx # check address range + jnz ext_store_u16 # if above perform an extended write + shr $15, %ecx # ecx = page number of address + # load the corresponding memory map offset + mov _memory_map_write(, %ecx, 4), %ecx + test %ecx, %ecx # see if it's NULL + jz ext_store_u16 # if so perform an extended write + and $0x7FFF, %eax # isolate the lower 15bits of the address + mov %dx, (%eax, %ecx) # store the value + # check for self-modifying code + testw $0xFFFF, -32768(%eax, %ecx) + jne smc_write + ret # return + +# 16bit ext memory routines + +ext_store_io16: + and $0x3FF, %eax # wrap around address + and $0xFFFF, %edx + call _write_io_register16 # perform 16bit I/O register write + jmp write_epilogue # see if it requires any system update + +ext_store_palette16: + and $0x3FF, %eax # wrap around address + +ext_store_palette16b: # entry point for 8bit write + mov %dx, _palette_ram(%eax) # write out palette value + mov %edx, %ecx # cx = dx + shl $11, %ecx # cx <<= 11 (red component is in high bits) + mov %dh, %cl # bottom bits of cx = top bits of dx + shr $2, %cl # move the blue component to the bottom of cl + and $0x03E0, %dx # isolate green component of dx + shl $1, %dx # make green component 6bits + or %edx, %ecx # combine green component into ecx + # write out the freshly converted palette value + mov %cx, _palette_ram_converted(%eax) + ret # done + +ext_store_vram16: + and $0x1FFFF, %eax # wrap around address + cmp $0x18000, %eax # see if address is in upper region + jb ext_store_vram16b + sub $0x8000, %eax # if so wrap down + +ext_store_vram16b: + mov %dx, _vram(%eax) # perform 16bit store + ret + +ext_store_oam16: + movl $1, _oam_update # flag OAM update + and $0x3FF, %eax # wrap around address + mov %dx, _oam_ram(%eax) # perform 16bit store + ret + +ext_store_rtc: + and $0xFFFF, %edx # make value 16bit + and $0xFF, %eax # mask address + jmp _write_rtc # write out RTC register + +ext_store_u16_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io16 # 0x04 I/O registers + .long ext_store_palette16 # 0x05 Palette RAM + .long ext_store_vram16 # 0x06 VRAM + .long ext_store_oam16 # 0x07 OAM RAM + .long ext_store_rtc # 0x08 gamepak or RTC + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_ignore # 0x0E Flash ROM/SRAM must be 8bit + +ext_store_u16: + mov %eax, %ecx # ecx = address + shr $24, %ecx # ecx = address >> 24 + cmp $15, %ecx + ja ext_store_ignore + # ecx = ext_store_u16_jtable[address >> 24] + mov ext_store_u16_jtable(, %ecx, 4), %ecx + jmp *%ecx # jump to table index + +_execute_store_u32: + mov %ecx, REG_PC(%ebx) # write out the PC + and $~0x03, %eax # fix alignment + mov %eax, %ecx # ecx = address + test $0xF0000000, %ecx # check address range + jnz ext_store_u32 # if above perform an extended write + shr $15, %ecx # ecx = page number of address + # load the corresponding memory map offset + mov _memory_map_write(, %ecx, 4), %ecx + test %ecx, %ecx # see if it's NULL + jz ext_store_u32 # if so perform an extended write + and $0x7FFF, %eax # isolate the lower 15bits of the address + mov %edx, (%eax, %ecx) # store the value + # check for self-modifying code + testl $0xFFFFFFFF, -32768(%eax, %ecx) + jne smc_write + ret # return it + +# 32bit ext memory routines + +ext_store_io32: + and $0x3FF, %eax # wrap around address + call _write_io_register32 # perform 32bit I/O register write + jmp write_epilogue # see if it requires any system update + +ext_store_palette32: + and $0x3FF, %eax # wrap around address + call ext_store_palette16b # write first 16bits + add $2, %eax # go to next address + shr $16, %edx # go to next 16bits + jmp ext_store_palette16b # write next 16bits + +ext_store_vram32: + and $0x1FFFF, %eax # wrap around address + cmp $0x18000, %eax # see if address is in upper region + jb ext_store_vram32b + sub $0x8000, %eax # if so wrap down + +ext_store_vram32b: + mov %edx, _vram(%eax) # perform 32bit store + ret + +ext_store_oam32: + movl $1, _oam_update # flag OAM update + and $0x3FF, %eax # wrap around address + mov %edx, _oam_ram(%eax) # perform 32bit store + ret + +ext_store_u32_jtable: + .long ext_store_ignore # 0x00 BIOS, ignore + .long ext_store_ignore # 0x01 invalid, ignore + .long ext_store_ignore # 0x02 EWRAM, should have been hit already + .long ext_store_ignore # 0x03 IWRAM, should have been hit already + .long ext_store_io32 # 0x04 I/O registers + .long ext_store_palette32 # 0x05 Palette RAM + .long ext_store_vram32 # 0x06 VRAM + .long ext_store_oam32 # 0x07 OAM RAM + .long ext_store_ignore # 0x08 gamepak, ignore (no RTC in 32bit) + .long ext_store_ignore # 0x09 gamepak, ignore + .long ext_store_ignore # 0x0A gamepak, ignore + .long ext_store_ignore # 0x0B gamepak, ignore + .long ext_store_ignore # 0x0C gamepak, ignore + .long ext_store_eeprom # 0x0D EEPROM (possibly) + .long ext_store_ignore # 0x0E Flash ROM/SRAM must be 8bit + + +ext_store_u32: + mov %eax, %ecx # ecx = address + shr $24, %ecx # ecx = address >> 24 + cmp $15, %ecx + ja ext_store_ignore + # ecx = ext_store_u32_jtable[address >> 24] + mov ext_store_u32_jtable(, %ecx, 4), %ecx + jmp *%ecx + +# %eax = new_cpsr +# %edx = store_mask + +_execute_store_cpsr: + mov %edx, REG_SAVE(%ebx) # save store_mask + mov %ecx, REG_SAVE2(%ebx) # save PC too + + mov %eax, %ecx # ecx = new_cpsr + and %edx, %ecx # ecx = new_cpsr & store_mask + mov REG_CPSR(%ebx), %eax # eax = cpsr + not %edx # edx = ~store_mask + and %edx, %eax # eax = cpsr & ~store_mask + or %ecx, %eax # eax = new cpsr combined with old + + call _execute_store_cpsr_body # do the dirty work in this C function + + extract_flags # pull out flag vars from new CPSR + + cmp $0, %eax # see if return value is 0 + jnz changed_pc_cpsr # might have changed the PC + + ret # return + +changed_pc_cpsr: + add $4, %esp # get rid of current return address + call _block_lookup_address_arm # lookup new PC + jmp *%eax + +smc_write: + call _flush_translation_cache_ram + +lookup_pc: + add $4, %esp + movl $0, CHANGED_PC_STATUS(%ebx) + mov REG_PC(%ebx), %eax + testl $0x20, REG_CPSR(%ebx) + jz lookup_pc_arm + +lookup_pc_thumb: + call _block_lookup_address_thumb + jmp *%eax + +lookup_pc_arm: + call _block_lookup_address_arm + jmp *%eax + +# eax: cycle counter + +_execute_arm_translate: + movl $_reg, %ebx # load base register + extract_flags # load flag variables + movl %eax, %edi # load edi cycle counter + + movl REG_PC(%ebx), %eax # load PC + + testl $0x20, REG_CPSR(%ebx) + jnz 1f + + call _block_lookup_address_arm + jmp *%eax # jump to it + +1: + call _block_lookup_address_thumb + jmp *%eax + +_step_debug_x86: + collapse_flags +# mov $100, %edi + mov %edi, %edx + jmp _step_debug + +.comm _memory_map_read 0x8000 +.comm _memory_map_write 0x8000 +.comm _reg 0x100 + + diff --git a/zip.c b/zip.c new file mode 100644 index 0000000..dd1d52c --- /dev/null +++ b/zip.c @@ -0,0 +1,155 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * Copyright (C) 2006 SiberianSTAR + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "common.h" + +#define ZIP_BUFFER_SIZE (128 * 1024) + +struct SZIPFileDataDescriptor +{ + s32 CRC32; + s32 CompressedSize; + s32 UncompressedSize; +} __attribute__((packed)); + +struct SZIPFileHeader +{ + char Sig[4]; // EDIT: Used to be s32 Sig; + s16 VersionToExtract; + s16 GeneralBitFlag; + s16 CompressionMethod; + s16 LastModFileTime; + s16 LastModFileDate; + struct SZIPFileDataDescriptor DataDescriptor; + s16 FilenameLength; + s16 ExtraFieldLength; +} __attribute__((packed)); + +u32 load_file_zip(char *filename) +{ + struct SZIPFileHeader data; + u8 tmp[1024]; + s32 retval = -1; + u8 *buffer = NULL; + u8 *cbuffer; + u8 *ext; + + file_open(fd, filename, read); + + if(!file_check_valid(fd)) + return -1; + +#if 0 // EDIT: Why this while(1) is used is unknown and can cause a crash. + while(1) +#endif + { + file_read(fd, &data, sizeof(struct SZIPFileHeader)); + + // EDIT: Check if this is a zip file without worrying about endian + // It checks for the following: 0x50 0x4B 0x03 0x04 (PK..) + // Used to be: if(data.Sig != 0x04034b50) break; + if( data.Sig[0] != 0x50 || data.Sig[1] != 0x4B || + data.Sig[2] != 0x03 || data.Sig[3] != 0x04 ) + { + goto outcode; + } + + file_read(fd, tmp, data.FilenameLength); + tmp[data.FilenameLength] = 0; // end string + + if(data.ExtraFieldLength) + file_seek(fd, data.ExtraFieldLength, SEEK_CUR); + + if(data.GeneralBitFlag & 0x0008) + { + file_read(fd, &data.DataDescriptor, + sizeof(struct SZIPFileDataDescriptor)); + } + + ext = strrchr(tmp, '.') + 1; + + // file is too big + if(data.DataDescriptor.UncompressedSize > gamepak_ram_buffer_size) + goto outcode; + + if(!strcasecmp(ext, "bin") || !strcasecmp(ext, "gba")) + { + buffer = gamepak_rom; + + // ok, found + switch(data.CompressionMethod) + { + case 0: + retval = data.DataDescriptor.UncompressedSize; + file_read(fd, buffer, retval); + + goto outcode; + + case 8: + { + z_stream stream; + s32 err; + + cbuffer = malloc(ZIP_BUFFER_SIZE); + + stream.next_in = (Bytef*)cbuffer; + stream.avail_in = (u32)ZIP_BUFFER_SIZE; + + stream.next_out = (Bytef*)buffer; + + // EDIT: Now uses proper conversion of data types for retval. + retval = (u32)data.DataDescriptor.UncompressedSize; + stream.avail_out = data.DataDescriptor.UncompressedSize; + + stream.zalloc = (alloc_func)0; + stream.zfree = (free_func)0; + + err = inflateInit2(&stream, -MAX_WBITS); + + file_read(fd, cbuffer, ZIP_BUFFER_SIZE); + + if(err == Z_OK) + { + while(err != Z_STREAM_END) + { + err = inflate(&stream, Z_SYNC_FLUSH); + if(err == Z_BUF_ERROR) + { + stream.avail_in = ZIP_BUFFER_SIZE; + stream.next_in = (Bytef*)cbuffer; + file_read(fd, cbuffer, ZIP_BUFFER_SIZE); + } + } + err = Z_OK; + inflateEnd(&stream); + } + free(cbuffer); + goto outcode; + } + } + } + } + +outcode: + file_close(fd); + + return retval; +} diff --git a/zip.h b/zip.h new file mode 100644 index 0000000..a63be6b --- /dev/null +++ b/zip.h @@ -0,0 +1,26 @@ +/* gameplaySP + * + * Copyright (C) 2006 Exophase + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef COMMON_H +#define COMMON_H + +u32 load_file_zip(char *filename); + +#endif + -- 2.39.5