merge mappers from FCEU-mm
[fceu.git] / boards / KS7030.c
CommitLineData
43725da7 1/* FCE Ultra - NES/Famicom Emulator\r
2 *\r
3 * Copyright notice for this file:\r
4 * Copyright (C) 2007 CaH4e3\r
5 *\r
6 * This program is free software; you can redistribute it and/or modify\r
7 * it under the terms of the GNU General Public License as published by\r
8 * the Free Software Foundation; either version 2 of the License, or\r
9 * (at your option) any later version.\r
10 *\r
11 * This program is distributed in the hope that it will be useful,\r
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
14 * GNU General Public License for more details.\r
15 *\r
16 * You should have received a copy of the GNU General Public License\r
17 * along with this program; if not, write to the Free Software\r
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
19 *\r
20 * FDS Conversion\r
21 *\r
22 * Logical bank layot 32 K BANK 0, 64K BANK 1, 32K ~0 hardwired, 8K is missing\r
23 * need redump from MASKROM!\r
24 * probably need refix mapper after hard dump\r
25 *\r
26 */\r
27\r
28#include "mapinc.h"\r
29\r
30static uint8 reg0, reg1;\r
31static uint8 *WRAM=NULL;\r
32static uint32 WRAMSIZE;\r
33\r
34static SFORMAT StateRegs[]=\r
35{\r
36 {&reg0, 1, "REG0"},\r
37 {&reg1, 1, "REG1"},\r
38 {0}\r
39};\r
40\r
41static void Sync(void)\r
42{\r
43 setchr8(0);\r
44 setprg32(0x8000,~0);\r
45 setprg4(0xb800,reg0);\r
46 setprg4(0xc800,8+reg1);\r
47}\r
48\r
49// 6000 - 6BFF - RAM\r
50// 6C00 - 6FFF - BANK 1K REG1\r
51// 7000 - 7FFF - BANK 4K REG0\r
52\r
53static DECLFW(UNLKS7030RamWrite0)\r
54{\r
55 if((A >= 0x6000) && A <= 0x6BFF) {\r
56 WRAM[A-0x6000]=V;\r
57 } else if((A >= 0x6C00) && A <= 0x6FFF) {\r
58 CartBW(0xC800 + (A - 0x6C00), V);\r
59 } else if((A >= 0x7000) && A <= 0x7FFF) {\r
60 CartBW(0xB800 + (A - 0x7000), V);\r
61 }\r
62}\r
63\r
64static DECLFR(UNLKS7030RamRead0)\r
65{\r
66 if((A >= 0x6000) && A <= 0x6BFF) {\r
67 return WRAM[A-0x6000];\r
68 } else if((A >= 0x6C00) && A <= 0x6FFF) {\r
69 return CartBR(0xC800 + (A - 0x6C00));\r
70 } else if((A >= 0x7000) && A <= 0x7FFF) {\r
71 return CartBR(0xB800 + (A - 0x7000));\r
72 }\r
73 return 0;\r
74}\r
75\r
76// B800 - BFFF - RAM\r
77// C000 - CBFF - BANK 3K\r
78// CC00 - D7FF - RAM\r
79\r
80static DECLFW(UNLKS7030RamWrite1)\r
81{\r
82 if((A >= 0xB800) && A <= 0xBFFF) {\r
83 WRAM[0x0C00+(A-0xB800)]=V;\r
84 } else if((A >= 0xC000) && A <= 0xCBFF) {\r
85 CartBW(0xCC00 + (A - 0xC000), V);\r
86 } else if((A >= 0xCC00) && A <= 0xD7FF) {\r
87 WRAM[0x1400+(A-0xCC00)]=V;\r
88 }\r
89}\r
90\r
91static DECLFR(UNLKS7030RamRead1)\r
92{\r
93 if((A >= 0xB800) && A <= 0xBFFF) {\r
94 return WRAM[0x0C00+(A-0xB800)];\r
95 } else if((A >= 0xC000) && A <= 0xCBFF) {\r
96 return CartBR(0xCC00 + (A - 0xC000));\r
97 } else if((A >= 0xCC00) && A <= 0xD7FF) {\r
98 return WRAM[0x1400+(A-0xCC00)];\r
99 }\r
100 return 0;\r
101}\r
102\r
103static DECLFW(UNLKS7030Write0)\r
104{\r
105 reg0=A&7;\r
106 Sync();\r
107}\r
108\r
109static DECLFW(UNLKS7030Write1)\r
110{\r
111 reg1=A&15;\r
112 Sync();\r
113}\r
114\r
115static void UNLKS7030Power(void)\r
116{\r
117 reg0=reg1=~0;\r
118 Sync();\r
119 SetReadHandler(0x6000,0x7FFF,UNLKS7030RamRead0);\r
120 SetWriteHandler(0x6000,0x7FFF,UNLKS7030RamWrite0);\r
121 SetReadHandler(0x8000,0xFFFF,CartBR);\r
122 SetWriteHandler(0x8000,0x8FFF,UNLKS7030Write0);\r
123 SetWriteHandler(0x9000,0x9FFF,UNLKS7030Write1);\r
124 SetReadHandler(0xB800,0xD7FF,UNLKS7030RamRead1);\r
125 SetWriteHandler(0xB800,0xD7FF,UNLKS7030RamWrite1);\r
126}\r
127\r
128static void UNLKS7030Close(void)\r
129{\r
130 if(WRAM)\r
131 FCEU_gfree(WRAM);\r
132 WRAM=NULL;\r
133}\r
134\r
135static void StateRestore(int version)\r
136{\r
137 Sync();\r
138}\r
139\r
140void UNLKS7030_Init(CartInfo *info)\r
141{\r
142 info->Power=UNLKS7030Power;\r
143 info->Close=UNLKS7030Close;\r
144 GameStateRestore=StateRestore;\r
145\r
146 WRAMSIZE=8192;\r
147 WRAM=(uint8*)FCEU_gmalloc(WRAMSIZE);\r
148 AddExState(WRAM, WRAMSIZE, 0, "WRAM");\r
149\r
150 AddExState(&StateRegs, ~0, 0, 0);\r
151}\r