save key config
[fceu.git] / x6502.h
CommitLineData
c62d2810 1/* FCE Ultra - NES/Famicom Emulator
2 *
3 * Copyright notice for this file:
4 * Copyright (C) 2002 Ben Parnell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21typedef struct {
22 int32 count; /* Cycle counter */
23 int32 tcount; /* Temporary cycle counter */
24 uint16 PC; /* I'll change this to uint32 later... */
25 /* I'll need to AND PC after increments to 0xFFFF */
26 /* when I do, though. Perhaps an IPC() macro? */
92e249b1 27 uint8 A,X,Y,S,P,mooPI;
c62d2810 28 uint8 DB; /* Data bus "cache" for reads from certain areas */
29 uint8 IRQlow; /* Simulated IRQ pin held low(or is it high?). */
30 uint8 jammed;
31} X6502;
32
33extern X6502 X;
34
35#define N_FLAG 0x80
36#define V_FLAG 0x40
37#define U_FLAG 0x20
38#define B_FLAG 0x10
39#define D_FLAG 0x08
40#define I_FLAG 0x04
41#define Z_FLAG 0x02
42#define C_FLAG 0x01
43
44extern uint32 timestamp;
45extern void FP_FASTAPASS(1) (*MapIRQHook)(int a);
46
47#define NTSC_CPU 1789772.7272727272727272
48#define PAL_CPU 1662607.125
49
50#define FCEU_IQEXT 0x01
51#define FCEU_IQNMI 0x08
52#define FCEU_IQDPCM 0x10
53#define FCEU_IQFCOUNT 0x20
54#define FCEU_IQTEMP 0x80
d97315ac 55// from 0.98.15
56#define FCEU_IQEXT2 0x02
c62d2810 57
af32b6c2 58#if defined(DEBUG_ASM_6502)
59#define TriggerIRQ TriggerIRQ_d
60#define TriggerNMI TriggerNMI_d
af32b6c2 61#define X6502_Run X6502_Run_d
62#define X6502_Reset X6502_Reset_d
63#define X6502_Power X6502_Power_d
64#define X6502_AddCycles X6502_AddCycles_d
65#define X6502_IRQBegin X6502_IRQBegin_d
66#define X6502_IRQEnd X6502_IRQEnd_d
c0bf6f9f 67#define X6502_Rebase X6502_Rebase_d
0b65fdb3 68#define X6502_GetCycleCount() g_cnt
af32b6c2 69#define X6502_C
70#define X6502_A
71#define X6502_D
72
73#elif defined(ASM_6502)
74#define TriggerIRQ TriggerIRQ_a
75#define TriggerNMI TriggerNMI_a
af32b6c2 76#define X6502_Reset X6502_Reset_a
77#define X6502_Power X6502_Power_a
78#define X6502_AddCycles X6502_AddCycles_a
e1591a12 79//#define X6502_IRQBegin X6502_IRQBegin_a
80//#define X6502_IRQEnd X6502_IRQEnd_a
81#define X6502_IRQBegin(w) nes_registers[4]|=w<<8
82#define X6502_IRQEnd(w) nes_registers[4]&=~(w<<8)
c0bf6f9f 83#define X6502_Rebase X6502_Rebase_a
4fdfab07 84#define X6502_GetCycleCount() ((int32)nes_registers[7]>>16)
af32b6c2 85#define X6502_A
86
af32b6c2 87#define X6502_Run(c) \
88{ \
89 int32 cycles = (c) << 4; /* *16 */ \
90 if (PAL) cycles -= (c); /* *15 */ \
8fa5eb33 91 nes_registers[7]+=cycles<<16; \
92 cycles=(int32)nes_registers[7]>>16; \
93 if (cycles > 0) { \
92e249b1 94 X6502_Run_a(); \
8fa5eb33 95 cycles -= (int32)nes_registers[7]>>16; \
92e249b1 96 asmcpu_update(cycles); \
97 } \
af32b6c2 98}
99
100#else
92e249b1 101#define TriggerIRQ TriggerIRQ_c
102#define TriggerNMI TriggerNMI_c
92e249b1 103#define X6502_Reset X6502_Reset_c
104#define X6502_Power X6502_Power_c
105#define X6502_AddCycles X6502_AddCycles_c
106#define X6502_IRQBegin X6502_IRQBegin_c
107#define X6502_IRQEnd X6502_IRQEnd_c
c0bf6f9f 108#define X6502_Rebase(...)
4fdfab07 109#define X6502_GetCycleCount() X.count
92e249b1 110#define X6502_C
111
937bf65b 112#define X6502_Run(c) \
113{ \
114 int32 cycles = (c) << 4; /* *16 */ \
115 if (PAL) cycles -= (c); /* *15 */ \
116 X.count+=cycles; \
af32b6c2 117 if (X.count > 0) X6502_Run_c(); \
937bf65b 118}
af32b6c2 119#define X6502_C
120#endif
937bf65b 121
af32b6c2 122// c
123#ifdef X6502_C
0b65fdb3 124extern int32 g_cnt;
af32b6c2 125void TriggerIRQ_c(void);
126void TriggerNMI_c(void);
af32b6c2 127void X6502_Run_c(void);
128void X6502_Reset_c(void);
129void X6502_Power_c(void);
130void FASTAPASS(1) X6502_AddCycles_c(int x);
131void FASTAPASS(1) X6502_IRQBegin_c(int w);
132void FASTAPASS(1) X6502_IRQEnd_c(int w);
133#endif
c62d2810 134
af32b6c2 135// asm
136#ifdef X6502_A
92e249b1 137extern uint32 nes_registers[0x10];
138extern uint32 pc_base;
af32b6c2 139void TriggerIRQ_a(void);
140void TriggerNMI_a(void);
af32b6c2 141void X6502_Run_a(void);
142void X6502_Reset_a(void);
143void X6502_Power_a(void);
144void X6502_AddCycles_a(int x);
145void X6502_IRQBegin_a(int w);
146void X6502_IRQEnd_a(int w);
c0bf6f9f 147void X6502_Rebase_a(void);
af32b6c2 148#endif
c62d2810 149
af32b6c2 150// debug
151#ifdef X6502_D
152void TriggerIRQ_d(void);
153void TriggerNMI_d(void);
af32b6c2 154void X6502_Run_d(int32 c);
155void X6502_Reset_d(void);
156void X6502_Power_d(void);
157void X6502_AddCycles_d(int x);
158void X6502_IRQBegin_d(int w);
159void X6502_IRQEnd_d(int w);
c0bf6f9f 160void X6502_Rebase_d(void);
af32b6c2 161#endif
937bf65b 162