merge mappers from FCEU-mm

[fceu.git] / boards / KS7030.c

diff --git a/boards/KS7030.c b/boards/KS7030.c
new file mode 100644 (file)
index 0000000..58abf0e
--- /dev/null
+++ b/boards/KS7030.c
@@ -0,0 +1,151 @@
+/* FCE Ultra - NES/Famicom Emulator\r
+ *\r
+ * Copyright notice for this file:\r
+ *  Copyright (C) 2007 CaH4e3\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; either version 2 of the License, or\r
+ * (at your option) any later version.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+ *\r
+ * FDS Conversion\r
+ *\r
+ * Logical bank layot 32 K BANK 0, 64K BANK 1, 32K ~0 hardwired, 8K is missing\r
+ * need redump from MASKROM!\r
+ * probably need refix mapper after hard dump\r
+ *\r
+ */\r
+\r
+#include "mapinc.h"\r
+\r
+static uint8 reg0, reg1;\r
+static uint8 *WRAM=NULL;\r
+static uint32 WRAMSIZE;\r
+\r
+static SFORMAT StateRegs[]=\r
+{\r
+  {&reg0, 1, "REG0"},\r
+  {&reg1, 1, "REG1"},\r
+  {0}\r
+};\r
+\r
+static void Sync(void)\r
+{\r
+  setchr8(0);\r
+  setprg32(0x8000,~0);\r
+  setprg4(0xb800,reg0);\r
+  setprg4(0xc800,8+reg1);\r
+}\r
+\r
+// 6000 - 6BFF - RAM\r
+// 6C00 - 6FFF - BANK 1K REG1\r
+// 7000 - 7FFF - BANK 4K REG0\r
+\r
+static DECLFW(UNLKS7030RamWrite0)\r
+{\r
+  if((A >= 0x6000) && A <= 0x6BFF) {\r
+    WRAM[A-0x6000]=V;\r
+  } else if((A >= 0x6C00) && A <= 0x6FFF) {\r
+    CartBW(0xC800 + (A - 0x6C00), V);\r
+  } else if((A >= 0x7000) && A <= 0x7FFF) {\r
+    CartBW(0xB800 + (A - 0x7000), V);\r
+  }\r
+}\r
+\r
+static DECLFR(UNLKS7030RamRead0)\r
+{\r
+  if((A >= 0x6000) && A <= 0x6BFF) {\r
+    return WRAM[A-0x6000];\r
+  } else if((A >= 0x6C00) && A <= 0x6FFF) {\r
+    return CartBR(0xC800 + (A - 0x6C00));\r
+  } else if((A >= 0x7000) && A <= 0x7FFF) {\r
+    return CartBR(0xB800 + (A - 0x7000));\r
+  }\r
+  return 0;\r
+}\r
+\r
+// B800 - BFFF - RAM\r
+// C000 - CBFF - BANK 3K\r
+// CC00 - D7FF - RAM\r
+\r
+static DECLFW(UNLKS7030RamWrite1)\r
+{\r
+  if((A >= 0xB800) && A <= 0xBFFF) {\r
+    WRAM[0x0C00+(A-0xB800)]=V;\r
+  } else if((A >= 0xC000) && A <= 0xCBFF) {\r
+    CartBW(0xCC00 + (A - 0xC000), V);\r
+  } else if((A >= 0xCC00) && A <= 0xD7FF) {\r
+    WRAM[0x1400+(A-0xCC00)]=V;\r
+  }\r
+}\r
+\r
+static DECLFR(UNLKS7030RamRead1)\r
+{\r
+  if((A >= 0xB800) && A <= 0xBFFF) {\r
+    return WRAM[0x0C00+(A-0xB800)];\r
+  } else if((A >= 0xC000) && A <= 0xCBFF) {\r
+    return CartBR(0xCC00 + (A - 0xC000));\r
+  } else if((A >= 0xCC00) && A <= 0xD7FF) {\r
+    return WRAM[0x1400+(A-0xCC00)];\r
+  }\r
+  return 0;\r
+}\r
+\r
+static DECLFW(UNLKS7030Write0)\r
+{\r
+  reg0=A&7;\r
+  Sync();\r
+}\r
+\r
+static DECLFW(UNLKS7030Write1)\r
+{\r
+  reg1=A&15;\r
+  Sync();\r
+}\r
+\r
+static void UNLKS7030Power(void)\r
+{\r
+  reg0=reg1=~0;\r
+  Sync();\r
+  SetReadHandler(0x6000,0x7FFF,UNLKS7030RamRead0);\r
+  SetWriteHandler(0x6000,0x7FFF,UNLKS7030RamWrite0);\r
+  SetReadHandler(0x8000,0xFFFF,CartBR);\r
+  SetWriteHandler(0x8000,0x8FFF,UNLKS7030Write0);\r
+  SetWriteHandler(0x9000,0x9FFF,UNLKS7030Write1);\r
+  SetReadHandler(0xB800,0xD7FF,UNLKS7030RamRead1);\r
+  SetWriteHandler(0xB800,0xD7FF,UNLKS7030RamWrite1);\r
+}\r
+\r
+static void UNLKS7030Close(void)\r
+{\r
+  if(WRAM)\r
+    FCEU_gfree(WRAM);\r
+  WRAM=NULL;\r
+}\r
+\r
+static void StateRestore(int version)\r
+{\r
+  Sync();\r
+}\r
+\r
+void UNLKS7030_Init(CartInfo *info)\r
+{\r
+  info->Power=UNLKS7030Power;\r
+  info->Close=UNLKS7030Close;\r
+  GameStateRestore=StateRestore;\r
+\r
+  WRAMSIZE=8192;\r
+  WRAM=(uint8*)FCEU_gmalloc(WRAMSIZE);\r
+  AddExState(WRAM, WRAMSIZE, 0, "WRAM");\r
+\r
+  AddExState(&StateRegs, ~0, 0, 0);\r
+}\r