#define OTOFFS_NES_REGS (nes_registers - cpu_exec_table)
#define OTOFFS_PC_BASE (pc_base - cpu_exec_table)
#define OTOFFS_IRQ_HOOK (MapIRQHook - cpu_exec_table)
-#define OTOFFS_IRQH_CYC (MapIRQHookCyc - cpu_exec_table)
+#define OTOFFS_TIMESTAMP (timestamp - cpu_exec_table)
#define OTOFFS_X (X_ - cpu_exec_table)
@ fceu
/*
bbbb:
-.ascii "rebase: %04x"
+.ascii "lsr_a: %02x"
.byte 0x0a,0
.align 4
+stmfd sp!,{r0-r3,r12,lr}
+mov r1,r0
+ldr r0,=bbbb
+bl printf
+ldmfd sp!,{r0-r3,r12,lr}
*/
@@@
.endm
+@ updates fceu "timestamp" variable
+@ loads cycles to reg, reg!=r1, trashes r1
+.macro FLUSH_TIMESTAMP reg
+ ldr r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
+ and \reg, REG_CYCLE, #0xff
+ add r1, r1, \reg
+ bic REG_CYCLE, REG_CYCLE, #0xff
+ str r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
+.endm
+
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
.macro CYCLE_NEXT n, hook_check=1
@@DEBUG_INFO
- subs REG_CYCLE, REG_CYCLE, #\n*48
+ add REG_CYCLE, REG_CYCLE, #\n
+ subs REG_CYCLE, REG_CYCLE, #\n*48<<16
ble cpu_exec_end
.if \hook_check
tst REG_P_REST, #1<<16
@@@ CLI¡¦PHP¤Ê¤É¥Õ¥é¥°¤òÊѹ¹¤·¤¿¾ì¹ç¤Ï¤³¤ì
@@@
.macro CYCLE_NEXT_INT n
-@ @@DEBUG_INFO
-@
-@ subs REG_CYCLE, REG_CYCLE, #\n*48
-@ bgt cpu_exec_check_int
-@ RETURN_FROM_CPU_EXEC
CYCLE_NEXT \n
.endm
@@@ ¥¹¥È¥¢¤¹¤ë¤À¤±¤ÎÌ¿Îá
@@@
-@@@ 16¥Ó¥Ã¥È¥¢¥É¥ì¥¹¤«¤é¥í¡¼¥É¤Î¤ß
-@@@
-@@@ RAM¤«¤é¤Î¥í¡¼¥É¤¬°ìÈÖ¿¤¤¤Î¤ÇÍ¥À褹¤ë
-@@@
-@@@ READ_1
-@@@ OP
-@@@ READ_2
-@@@ OP
+@@@ Read byte
@@@
-@@@ ¤Î¤è¤¦¤Ë»È¤¦
-
-.macro READ_1
- movs r1, REG_ADDR, lsr #13
- adr lr, 9999f
- @@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
- @@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
- ldrne pc, [lr, -r1, lsl #2]
- @@ RAM¤«¤é¥í¡¼¥É
- bic r0, REG_ADDR, #0x1800
- add r0, r0, #OTOFFS_NES_RAM
- ldrb r0, [r0, REG_OP_TABLE]
-.endm
-
-.macro READ_2
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
- .long read_save_ram
- .long read_high_reg
- .long read_ppu_reg
-9999:
-.endm
.macro READ
- mov r1, REG_ADDR, lsr #13
adr lr, 1f
- ldr pc, [pc, r1, lsl #2]
- nop
- .long 2f @ fast path
- .long read_ppu_reg
- .long read_high_reg
- .long read_save_ram
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
-2:
+ tst REG_ADDR, #0x8000
+ bne read_rom_byte
+ tst REG_ADDR, #0xe000
+ bne read_byte
+ @ RAM
bic r0, REG_ADDR, #0x1800
add r0, r0, #OTOFFS_NES_RAM
ldrb r0, [r0, REG_OP_TABLE]
@@@ OP¤Ç¤Ïr3¤òÊݸ¤·¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤
.macro READ_WRITE_1
- movs r3, REG_ADDR, lsr #13
adr lr, 9999f
- @@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
- @@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
- ldrne pc, [lr, -r3, lsl #2]
- @@ RAM¤«¤é¥í¡¼¥É
+ tst REG_ADDR, #0x8000
+ bne read_rom_byte
+ tst REG_ADDR, #0xe000
+ bne read_byte
+ @ RAM
bic REG_ADDR, REG_ADDR, #0x1800
add REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
ldrb r0, [REG_ADDR, REG_OP_TABLE]!
.endm
.macro READ_WRITE_3
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
- .long read_rom_byte
- .long read_save_ram
- .long read_high_reg
- .long read_ppu_reg
9999:
+ bl write_byte @ rmw first writes unmodified data
.endm
.macro READ_WRITE_4
- adr lr, 1f
- ldr pc, [pc, r3, lsl #2]
- nop
- nop
- .long write_ppu_reg
- .long write_high_reg
- .long write_save_ram
- .long write_rom_byte
- .long write_rom_byte
- .long write_rom_byte
- .long write_rom_byte
-1:
+ bl write_byte @ and only then modified (Blaster Master)
.endm
@@@
-@@@ ½ñ¤¹þ¤ß¤À¤±¤Î¾ì¹ç
+@@@ Write r0 to [addr]
@@@
-@@@ WRITE_1
-@@@ TAIL
-@@@ WRITE_2
-@@@ TAIL
-@@@ ¤È¤¹¤ë
.macro WRITE_1
@@DEBUG_INFO
- movs r1, REG_ADDR, lsr #13
- adr lr, 9999f
- ldrne pc, [lr, -r1, lsl #2]
- bic REG_ADDR, REG_ADDR, #0x1800
- add REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
+ tst REG_ADDR, #0xe000
+ biceq REG_ADDR, REG_ADDR, #0x1800
+ addeq REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
- strb r0, [REG_ADDR, REG_OP_TABLE]
-.endm
-
-.macro WRITE_2
- .long write_rom_byte
- .long write_rom_byte
- .long write_rom_byte
- .long write_rom_byte
- .long write_save_ram
- .long write_high_reg
- .long write_ppu_reg
-9999:
+ streqb r0, [REG_ADDR, REG_OP_TABLE]
+ blne write_byte
.endm
@@@
bic REG_ADDR, REG_ADDR, #0x10000
and r0,REG_ADDR,#0xff
cmp REG_Y,r0
- subgt REG_CYCLE,REG_CYCLE,#1*48
+ addgt REG_CYCLE, REG_CYCLE, #1
+ subgt REG_CYCLE, REG_CYCLE, #1*48<<16
.endm
@ Indirect Indexed (for writes and rmws)
bic REG_ADDR, REG_ADDR, #0x10000
and r0,REG_ADDR,#0xff
cmp REG_X,r0
- subgt REG_CYCLE,REG_CYCLE,#1*48
+ addgt REG_CYCLE, REG_CYCLE, #1
+ subgt REG_CYCLE, REG_CYCLE, #1*48<<16
.endm
@ Absolute Indexed (for writes and rmws)
bic REG_ADDR, REG_ADDR, #0x10000
and r0,REG_ADDR,#0xff
cmp REG_Y,r0
- subgt REG_CYCLE,REG_CYCLE,#1*48
+ addgt REG_CYCLE, REG_CYCLE, #1
+ subgt REG_CYCLE, REG_CYCLE, #1*48<<16
.endm
@ Absolute Indexed (for writes and rmws)
opAD: @ LDA $nnnn
ABS_ADDR
- READ_1
- OP_LDA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDA
CYCLE_NEXT 4
opBD: @ LDA $nnnn, X
ABSX_ADDR
- READ_1
- OP_LDA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDA
CYCLE_NEXT 4
opB9: @ LDA $nnnn, Y
ABSY_ADDR
- READ_1
- OP_LDA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDA
CYCLE_NEXT 4
opA1: @ LDA ($nn, X)
INDX_ADDR
- READ_1
- OP_LDA
- CYCLE_NEXT 6
- READ_2
+ READ
OP_LDA
CYCLE_NEXT 6
opB1: @ LDA ($nn), Y
INDY_ADDR
- READ_1
- OP_LDA
- CYCLE_NEXT 5
- READ_2
+ READ
OP_LDA
CYCLE_NEXT 5
-
opA2: @ LDX #$nn
IMM_VALUE
OP_LDX
opAE: @ LDX $nnnn
ABS_ADDR
- READ_1
- OP_LDX
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDX
CYCLE_NEXT 4
opBE: @ LDX $nnnn, Y
ABSY_ADDR
- READ_1
- OP_LDX
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDX
CYCLE_NEXT 4
opAC: @ LDY $nnnn
ABS_ADDR
- READ_1
- OP_LDY
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDY
CYCLE_NEXT 4
opBC: @ LDY $nnnn, X
ABSX_ADDR
- READ_1
- OP_LDY
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LDY
CYCLE_NEXT 4
OP_STA
WRITE_1
CYCLE_NEXT 4
- WRITE_2
- CYCLE_NEXT 4
op9D: @ STA $nnnn, X
ABSX_ADDR_W
OP_STA
WRITE_1
CYCLE_NEXT 5
- WRITE_2
- CYCLE_NEXT 5
op99: @ STA $nnnn, Y
ABSY_ADDR_W
OP_STA
WRITE_1
CYCLE_NEXT 5
- WRITE_2
- CYCLE_NEXT 5
op81: @ STA ($nn, X)
INDX_ADDR
OP_STA
WRITE_1
CYCLE_NEXT 6
- WRITE_2
- CYCLE_NEXT 6
op91: @ STA ($nn), Y
INDY_ADDR_W
OP_STA
WRITE_1
CYCLE_NEXT 6
- WRITE_2
- CYCLE_NEXT 6
op86: @ STX $nn
mov r0, REG_X
WRITE_1
CYCLE_NEXT 4
- WRITE_2
- CYCLE_NEXT 4
op84: @ STY $nn
mov r0, REG_Y
WRITE_1
CYCLE_NEXT 4
- WRITE_2
- CYCLE_NEXT 4
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
op6D: @ ADC $nnnn
ABS_ADDR
- READ_1
- OP_ADC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ADC
CYCLE_NEXT 4
op7D: @ ADC $nnnn, X
ABSX_ADDR
- READ_1
- OP_ADC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ADC
CYCLE_NEXT 4
op79: @ ADC $nnnn, Y
ABSY_ADDR
- READ_1
- OP_ADC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ADC
CYCLE_NEXT 4
op61: @ ADC ($nn, X)
INDX_ADDR
- READ_1
- OP_ADC
- CYCLE_NEXT 6
- READ_2
+ READ
OP_ADC
CYCLE_NEXT 6
op71: @ ADC ($nn), Y
INDY_ADDR
- READ_1
- OP_ADC
- CYCLE_NEXT 5
- READ_2
+ READ
OP_ADC
CYCLE_NEXT 5
opED: @ SBC $nnnn
ABS_ADDR
- READ_1
- OP_SBC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_SBC
CYCLE_NEXT 4
opFD: @ SBC $nnnn, X
ABSX_ADDR
- READ_1
- OP_SBC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_SBC
CYCLE_NEXT 4
opF9: @ SBC $nnnn, Y
ABSY_ADDR
- READ_1
- OP_SBC
- CYCLE_NEXT 4
- READ_2
+ READ
OP_SBC
CYCLE_NEXT 4
opE1: @ SBC ($nn, X)
INDX_ADDR
- READ_1
- OP_SBC
- CYCLE_NEXT 6
- READ_2
+ READ
OP_SBC
CYCLE_NEXT 6
opF1: @ SBC ($nn), Y
INDY_ADDR
- READ_1
- OP_SBC
- CYCLE_NEXT 5
- READ_2
+ READ
OP_SBC
CYCLE_NEXT 5
op2D: @ AND $nnnn
ABS_ADDR
- READ_1
- OP_AND
- CYCLE_NEXT 4
- READ_2
+ READ
OP_AND
CYCLE_NEXT 4
op3D: @ AND $nnnn, X
ABSX_ADDR
- READ_1
- OP_AND
- CYCLE_NEXT 4
- READ_2
+ READ
OP_AND
CYCLE_NEXT 4
op39: @ AND $nnnn, Y
ABSY_ADDR
- READ_1
- OP_AND
- CYCLE_NEXT 4
- READ_2
+ READ
OP_AND
CYCLE_NEXT 4
op21: @ AND ($nn, X)
INDX_ADDR
- READ_1
- OP_AND
- CYCLE_NEXT 6
- READ_2
+ READ
OP_AND
CYCLE_NEXT 6
op31: @ AND ($nn), Y
INDY_ADDR
- READ_1
- OP_AND
- CYCLE_NEXT 5
- READ_2
+ READ
OP_AND
CYCLE_NEXT 5
op4D: @ EOR $nnnn
ABS_ADDR
- READ_1
- OP_EOR
- CYCLE_NEXT 4
- READ_2
+ READ
OP_EOR
CYCLE_NEXT 4
op5D: @ EOR $nnnn, X
ABSX_ADDR
- READ_1
- OP_EOR
- CYCLE_NEXT 4
- READ_2
+ READ
OP_EOR
CYCLE_NEXT 4
op59: @ EOR $nnnn, Y
ABSY_ADDR
- READ_1
- OP_EOR
- CYCLE_NEXT 4
- READ_2
+ READ
OP_EOR
CYCLE_NEXT 4
op41: @ EOR ($nn, X)
INDX_ADDR
- READ_1
- OP_EOR
- CYCLE_NEXT 6
- READ_2
+ READ
OP_EOR
CYCLE_NEXT 6
op51: @ EOR ($nn), Y
INDY_ADDR
- READ_1
- OP_EOR
- CYCLE_NEXT 5
- READ_2
+ READ
OP_EOR
CYCLE_NEXT 5
op0D: @ ORA $nnnn
ABS_ADDR
- READ_1
- OP_ORA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ORA
CYCLE_NEXT 4
op1D: @ ORA $nnnn, X
ABSX_ADDR
- READ_1
- OP_ORA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ORA
CYCLE_NEXT 4
op19: @ ORA $nnnn, Y
ABSY_ADDR
- READ_1
- OP_ORA
- CYCLE_NEXT 4
- READ_2
+ READ
OP_ORA
CYCLE_NEXT 4
op01: @ ORA ($nn, X)
INDX_ADDR
- READ_1
- OP_ORA
- CYCLE_NEXT 6
- READ_2
+ READ
OP_ORA
CYCLE_NEXT 6
op11: @ ORA ($nn), Y
INDY_ADDR
- READ_1
- OP_ORA
- CYCLE_NEXT 5
- READ_2
+ READ
OP_ORA
CYCLE_NEXT 5
opCD: @ CMP $nnnn
ABS_ADDR
- READ_1
- OP_CMP
- CYCLE_NEXT 4
- READ_2
+ READ
OP_CMP
CYCLE_NEXT 4
opDD: @ CMP $nnnn, X
ABSX_ADDR
- READ_1
- OP_CMP
- CYCLE_NEXT 4
- READ_2
+ READ
OP_CMP
CYCLE_NEXT 4
opD9: @ CMP $nnnn, Y
ABSY_ADDR
- READ_1
- OP_CMP
- CYCLE_NEXT 4
- READ_2
+ READ
OP_CMP
CYCLE_NEXT 4
opC1: @ CMP ($nn, X)
INDX_ADDR
- READ_1
- OP_CMP
- CYCLE_NEXT 6
- READ_2
+ READ
OP_CMP
CYCLE_NEXT 6
opD1: @ CMP ($nn), Y
INDY_ADDR
- READ_1
- OP_CMP
- CYCLE_NEXT 5
- READ_2
+ READ
OP_CMP
CYCLE_NEXT 5
opEC: @ CPX $nnnn
ABS_ADDR
- READ_1
- OP_CPX
- CYCLE_NEXT 4
- READ_2
+ READ
OP_CPX
CYCLE_NEXT 4
opCC: @ CPY $nnnn
ABS_ADDR
- READ_1
- OP_CPY
- CYCLE_NEXT 4
- READ_2
+ READ
OP_CPY
CYCLE_NEXT 4
op2C: @ BIT $nnnn
ABS_ADDR
- READ_1
- OP_BIT
- CYCLE_NEXT 4
- READ_2
+ READ
OP_BIT
CYCLE_NEXT 4
and r1,r1,#0xff
add r1,r3,r1
tst r1,#0x100
- subne REG_CYCLE,REG_CYCLE, #1*48
+ addne REG_CYCLE, REG_CYCLE, #1
+ subne REG_CYCLE, REG_CYCLE, #1*48<<16
.endm
.macro BRANCH_EQ
ldreqsb r1, [REG_PC], #1
movne r1, #1
add REG_PC, REG_PC, r1
- subeq REG_CYCLE, REG_CYCLE, #1*48
+ addeq REG_CYCLE, REG_CYCLE, #1
+ subeq REG_CYCLE, REG_CYCLE, #1*48<<16
bne 1f
HAD_BRANCH
1:
ldrnesb r1, [REG_PC], #1
moveq r1, #1
add REG_PC, REG_PC, r1
- subne REG_CYCLE, REG_CYCLE, #1*48
+ addne REG_CYCLE, REG_CYCLE, #1
+ subne REG_CYCLE, REG_CYCLE, #1*48<<16
beq 1f
HAD_BRANCH
1:
OP_SHY
WRITE_1
CYCLE_NEXT 5
- WRITE_2
- CYCLE_NEXT 5
opE7: @ ISB $nn
ZERO_ADDR
opAF: @ LAX $nnnn
ABS_ADDR
- READ_1
- OP_LAX
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LAX
CYCLE_NEXT 4
opBF: @ LAX $nnnn, Y
ABSY_ADDR
- READ_1
- OP_LAX
- CYCLE_NEXT 4
- READ_2
+ READ
OP_LAX
CYCLE_NEXT 4
opA3: @ LAX ($nn, X)
INDX_ADDR
- READ_1
- OP_LAX
- CYCLE_NEXT 6
- READ_2
+ READ
OP_LAX
CYCLE_NEXT 6
opB3: @ LAX ($nn), Y
INDY_ADDR
- READ_1
- OP_LAX
- CYCLE_NEXT 5
- READ_2
+ READ
OP_LAX
CYCLE_NEXT 5
REBASE_PC
@ CYCLE_NEXT 7
- subs REG_CYCLE, REG_CYCLE, #7*48
+ add REG_CYCLE, REG_CYCLE, #7
+ subs REG_CYCLE, REG_CYCLE, #7*48<<16
ble cpu_exec_end
ldrb r0, [REG_PC], #1
tst REG_P_REST, #0xff<<8
orr r1, r1, r1, lsr #4
ldr r1, [r2, r1, lsl #2] @ if (ARead[0xfff0] == CartBR)
cmp r0, r1
- bne read_ppu_reg
+ bne read_byte
ldr r2, =Page
mov r1, REG_ADDR, lsr #11
ldr r2, [r2, r1, lsl #2]
#endif
-read_ppu_reg:
-read_high_reg:
-read_save_ram:
+read_byte:
@ must preserve r3 for the callers too
@ TODO: check if all of saves are needed, _DB (is full needed?)
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
bx lr
-write_ppu_reg:
-write_high_reg:
-write_save_ram:
-write_rom_byte:
+write_byte:
+ FLUSH_TIMESTAMP r2 @ Blaster Master, more...
#ifndef DEBUG_ASM_6502
- @ must preserve r3 for the callers too
+ @ must preserve r0 (data) and r3 for the callers
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
str REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
mov REG_PC, lr @ r7
mov REG_P_REST, r3 @ r8
+ mov REG_CYCLE, r0 @ r11
ldr r2, =BWrite
mov r1, r0
ldr REG_OP_TABLE, =cpu_exec_table @ got trashed because was in r12
mov lr, REG_PC
mov r3, REG_P_REST
+ mov r0, REG_CYCLE
ldr REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
ldr REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
ldr REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
ldr r2, =dwrite_count_a
add r1, r1, #1
str r1, [r2]
+ and r0, r0, #0xff
#endif
bx lr
@ ldr REG_OP_TABLE, = cpu_exec_table @ set on init
- tst REG_P_REST, #1<<16
- strne REG_CYCLE, [REG_OP_TABLE, #OTOFFS_IRQH_CYC]
-
CYCLE_NEXT 0, 0
cpu_exec_end:
+ FLUSH_TIMESTAMP r0
+
tst REG_P_REST, #1<<16
- blne do_irq_hook
+ blne do_irq_hook_noflushts
ldr r0, =nes_registers
stmia r0, {r4-r12}
.long 0
MapIRQHook:
.long 0
-MapIRQHookCyc:
- .long 0
timestamp:
+timestamp_a:
.long 0
#ifndef DEBUG_ASM_6502
X:
.globl timestamp
#else
.globl nes_internal_ram
+ .globl timestamp_a
#endif
.globl X6502_Reset_a @ (void);
.globl X6502_Power_a @ (void);
X6502_AddCycles_a:
+ ldr r3, =timestamp
ldr r2, =nes_registers
- ldr r1, [r2, #0x1c]
+ ldr r1, [r3]
+ add r1, r1, r0
+ str r1, [r3]
+ ldrsh r1, [r2, #0x1e]
mvn r3, #47 @ r3=-48
mla r0, r3, r0, r1
- str r0, [r2, #0x1c]
+ strh r0, [r2, #0x1e]
bx lr
@ the nasty MapIRQHook thing from FCE..
@ test Gradius 2 (J) if you change this
do_irq_hook:
- @ ((cycles >> 4) * 43) >> 7; // aproximating /= 48
- ldr r1, [REG_OP_TABLE, #OTOFFS_IRQH_CYC]
- str REG_CYCLE, [REG_OP_TABLE, #OTOFFS_IRQH_CYC]
- mov r0, #43
- sub r1, r1, REG_CYCLE
- mul r0, r1, r0
- mov r0, r0, lsr #11
+ FLUSH_TIMESTAMP r0
+do_irq_hook_noflushts:
#ifndef DEBUG_ASM_6502
@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
notaz.gp2x.de / fceu.git / blobdiff