X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=fceu.git;a=blobdiff_plain;f=ncpu.S;h=dcade08fabf64a4d74ac9939594561487f078899;hp=6b68fe7ae4f827d059f6a815b9490d6e00cc428f;hb=e328100eecae3adfce1c3b57364bee5d166217ef;hpb=8fa5eb3371d902b8d58dba6e6bf62726d7ed8dbc

diff --git a/ncpu.S b/ncpu.S
index 6b68fe7..dcade08 100644
--- a/ncpu.S
+++ b/ncpu.S
@@ -33,7 +33,7 @@
 
 /*
 bbbb:
-.ascii "lsr_a: %02x"
+.ascii "ab_a: %04x"
 .byte 0x0a,0
 .align 4
 stmfd sp!,{r0-r3,r12,lr}
@@ -68,13 +68,16 @@ ldmfd sp!,{r0-r3,r12,lr}
 
 
 @ updates fceu "timestamp" variable
-@ loads cycles to reg, reg!=r1, trashes r1
+@ loads cycles to reg, reg!=r1, trashes r1, kills flags
 .macro	FLUSH_TIMESTAMP reg
+	ands	\reg, REG_CYCLE, #0xff
+	beq	1f
 	ldr	r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
-	and	\reg, REG_CYCLE, #0xff
+	orr	REG_CYCLE, REG_CYCLE, \reg, lsl #8	@ put cycles for do_irq_hook
 	add	r1, r1, \reg
 	bic	REG_CYCLE, REG_CYCLE, #0xff
 	str	r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
+1:
 .endm
 
 
@@ -88,23 +91,25 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@
 @@@ ¤Ê¤ó¤«Ì¾Á°¤¬ÊѤÀ¤Ê(¤É¡¼¤Ç¤â¤¤¡¼¤±¤É¡¼
 @@@
-.macro	CYCLE_NEXT	n, hook_check=1
+.macro	CYCLE_NEXT	n, unused=0, do_cyc_add=1
 	@@DEBUG_INFO
 
+.if \do_cyc_add
 	add	REG_CYCLE, REG_CYCLE, #\n
+.endif
 	subs	REG_CYCLE, REG_CYCLE, #\n*48<<16
 	ble	cpu_exec_end
-.if \hook_check
 	tst	REG_P_REST, #1<<16
-	blne	do_irq_hook
-.endif
+	bne	do_irq_hook
+
 	ldrb	r0, [REG_PC], #1
 	tst	REG_P_REST, #0xff<<8
 	ldreq	pc, [REG_OP_TABLE, r0, lsl #2]
 
 	@ do some messing to find out which IRQ is pending..
-	tst	REG_P_REST, #FCEU_IQNMI<<8
-	bne	do_int
+	@ assumption: NMI can be set only on very first run, because it is only set once before vblank..
+@	tst	REG_P_REST, #FCEU_IQNMI<<8
+@	bne	do_int
 	tst	REG_P_REST, #P_REST_I_FLAG
 	@@ if I_FLAG=1, continue execution, don't trigger IRQ
 	bicne	REG_P_REST, REG_P_REST, #FCEU_IQTEMP<<8
@@ -113,6 +118,12 @@ ldmfd sp!,{r0-r3,r12,lr}
 	b	do_int
 .endm
 
+@ fceu needs timestamp cycles to be inremented before doing actual opcode.
+@ this is only needed for ops which do memory i/o
+.macro	CYCLE_PRE	n
+	add	REG_CYCLE, REG_CYCLE, #\n
+.endm
+
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -191,59 +202,16 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@ ¥¹¥È¥¢¤¹¤ë¤À¤±¤ÎÌ¿Îá
 
 @@@
-@@@ 16¥Ó¥Ã¥È¥¢¥É¥ì¥¹¤«¤é¥í¡¼¥É¤Î¤ß
-@@@
-@@@ RAM¤«¤é¤Î¥í¡¼¥É¤¬°ìÈÖ¿¤¤¤Î¤ÇÍ¥À褹¤ë
+@@@ Read byte
 @@@
-@@@ READ_1
-@@@ OP
-@@@ READ_2
-@@@ OP
-@@@
-@@@ ¤Î¤è¤¦¤Ë»È¤¦
-
-.macro	READ_1
-	movs	r1, REG_ADDR, lsr #13
-	adr	lr, 9999f
-	@@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
-	@@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
-	ldrne	pc, [lr, -r1, lsl #2]
-	@@ RAM¤«¤é¥í¡¼¥É
-	bic	r0, REG_ADDR, #0x1800
-	add	r0, r0, #OTOFFS_NES_RAM
-	ldrb	r0, [r0, REG_OP_TABLE]
-.endm
-
-.macro	READ_2
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_save_ram
-	.long	read_high_reg
-	.long	read_ppu_reg
-9999:
-.endm
 
-.macro	READ
-	mov	r1, REG_ADDR, lsr #13
-	adr	lr, 1f
-	ldr	pc, [pc, r1, lsl #2]
-	nop
-	.long	2f		@ fast path
-	.long	read_ppu_reg
-	.long	read_high_reg
-	.long	read_save_ram
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-2:
-	bic	r0, REG_ADDR, #0x1800
-	add	r0, r0, #OTOFFS_NES_RAM
-	ldrb	r0, [r0, REG_OP_TABLE]
-	@@ ¤È¤¤¤¦¤ï¤±¤Ç¥¸¥ã¥ó¥×¤¹¤ëɬÍפϤʤ¤
-1:
+.macro	READ unused_param
+	tst	REG_ADDR, #0xe000
+	@ RAM
+	biceq	r0, REG_ADDR, #0x1800
+	addeq	r0, r0, #OTOFFS_NES_RAM
+	ldreqb	r0, [r0, REG_OP_TABLE]
+	blne	read_byte
 .endm
 
 @@@
@@ -260,12 +228,10 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@ OP¤Ç¤Ïr3¤òÊݸ¤·¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤
 
 .macro	READ_WRITE_1
-	movs	r3, REG_ADDR, lsr #13
-	adr	lr, 9999f
-	@@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
-	@@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
-	ldrne	pc, [lr, -r3, lsl #2]
-	@@ RAM¤«¤é¥í¡¼¥É
+	tst	REG_ADDR, #0xe000
+	adrne	lr, 9999f
+	bne	read_byte
+	@ RAM
 	bic	REG_ADDR, REG_ADDR, #0x1800
 	add	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
 	ldrb	r0, [REG_ADDR, REG_OP_TABLE]!
@@ -275,67 +241,28 @@ ldmfd sp!,{r0-r3,r12,lr}
 	strb	r0, [REG_ADDR]
 .endm
 
-.macro	READ_WRITE_W
-	adr	lr, 1f
-	ldr	pc, [pc, r3, lsl #2]
-	nop
-	nop
-	.long	write_ppu_reg
-	.long	write_high_reg
-	.long	write_save_ram
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-1:
-.endm
-
 .macro	READ_WRITE_3
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_save_ram
-	.long	read_high_reg
-	.long	read_ppu_reg
 9999:
-	READ_WRITE_W		@ rmw first writes unmodified data
+	bl	write_byte	@ rmw first writes unmodified data
 .endm
 
 .macro	READ_WRITE_4
-	READ_WRITE_W		@ and only then modified (Blaster Master)
+	bl	write_byte	@ and only then modified (Blaster Master)
 .endm
 
 @@@
-@@@ ½ñ¤­¹þ¤ß¤À¤±¤Î¾ì¹ç
+@@@ Write r0 to [addr]
 @@@
-@@@ WRITE_1
-@@@ TAIL
-@@@ WRITE_2
-@@@ TAIL
-@@@ ¤È¤¹¤ë
 
 .macro	WRITE_1
 	@@DEBUG_INFO
 
-	movs	r1, REG_ADDR, lsr #13
-	adr	lr, 9999f
-	ldrne	pc, [lr, -r1, lsl #2]
-	bic	REG_ADDR, REG_ADDR, #0x1800
-	add	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
-
-	strb	r0, [REG_ADDR, REG_OP_TABLE]
-.endm
+	tst	REG_ADDR, #0xe000
+	biceq	REG_ADDR, REG_ADDR, #0x1800
+	addeq	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
 
-.macro	WRITE_2
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_save_ram
-	.long	write_high_reg
-	.long	write_ppu_reg
-9999:
+	streqb	r0, [REG_ADDR, REG_OP_TABLE]
+	blne	write_byte
 .endm
 
 @@@
@@ -346,10 +273,10 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@ REG_ADDR¤òÊѹ¹¤¹¤ë¤¬µ¤¤Ë¤¹¤ë¤Ê
 @@@
 .macro	READ_WORD
-	READ
+	READ    0
 	mov	REG_PC, r0
 	add	REG_ADDR, REG_ADDR, #1
-	READ
+	READ	0
 	orr	r0, REG_PC, r0, lsl #8
 .endm
 
@@ -478,18 +405,25 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@ $nnnn
 
-.macro	ABS_ADDR
+.macro	ABS_ADDR update_db=0
+.if \update_db
+	ldrb	r0, [REG_PC, #1]
+	ldrb	REG_ADDR, [REG_PC], #2
+	strb    r0, [REG_OP_TABLE, #(OTOFFS_X + 0x10)]		@ X.DB
+	orr	REG_ADDR, REG_ADDR, r0, lsl #8
+.else
 	tst	REG_PC, #1
 	ldrneb	REG_ADDR, [REG_PC], #1
 	ldrneb	r0, [REG_PC], #1
 	ldreqh	REG_ADDR, [REG_PC], #2
 	orrne	REG_ADDR, REG_ADDR, r0, lsl #8
+.endif
 .endm
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@ $nnnn, X
 .macro	ABSX_ADDR
-	ABS_ADDR
+	ABS_ADDR 1
 	add	REG_ADDR, REG_ADDR, REG_X
 	bic	REG_ADDR, REG_ADDR, #0x10000
 	and	r0,REG_ADDR,#0xff
@@ -508,7 +442,7 @@ ldmfd sp!,{r0-r3,r12,lr}
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@ $nnnn, Y
 .macro	ABSY_ADDR
-	ABS_ADDR
+	ABS_ADDR 1					@ a hack needed for Paperboy, Dirty Harry controls to work
 	add	REG_ADDR, REG_ADDR, REG_Y
 	bic	REG_ADDR, REG_ADDR, #0x10000
 	and	r0,REG_ADDR,#0xff
@@ -746,50 +680,39 @@ opB5:	@ LDA $nn, X
 	CYCLE_NEXT	4
 
 opAD:	@ LDA $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opBD:	@ LDA $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opB9:	@ LDA $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opA1:	@ LDA ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_LDA
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opB1:	@ LDA ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_LDA
-	CYCLE_NEXT	5
-
+	CYCLE_NEXT	5,1,0
 
 opA2:	@ LDX #$nn
 	IMM_VALUE
@@ -809,22 +732,18 @@ opB6:	@ LDX $nn, Y
 	CYCLE_NEXT	4
 
 opAE:	@ LDX $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_LDX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDX
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opBE:	@ LDX $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_LDX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDX
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 
 
@@ -848,22 +767,18 @@ opB4:	@ LDY $nn, X
 
 
 opAC:	@ LDY $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_LDY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDY
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opBC:	@ LDY $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_LDY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDY
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -892,44 +807,39 @@ op95:	@ STA $nn, X
 	CYCLE_NEXT	4
 
 op8D:	@ STA $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
 	OP_STA
 	WRITE_1
-	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
+	CYCLE_NEXT	4,1,0
 
 op9D:	@ STA $nnnn, X
+	CYCLE_PRE	5
 	ABSX_ADDR_W
 	OP_STA
 	WRITE_1
-	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
+	CYCLE_NEXT	5,1,0
 
 op99:	@ STA $nnnn, Y
+	CYCLE_PRE	5
 	ABSY_ADDR_W
 	OP_STA
 	WRITE_1
-	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
+	CYCLE_NEXT	5,1,0
 
 op81:	@ STA ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
 	OP_STA
 	WRITE_1
-	CYCLE_NEXT 6
-	WRITE_2
-	CYCLE_NEXT 6
+	CYCLE_NEXT	6,1,0
 
 op91:	@ STA ($nn), Y
+	CYCLE_PRE	6
 	INDY_ADDR_W
 	OP_STA
 	WRITE_1
-	CYCLE_NEXT 6
-	WRITE_2
-	CYCLE_NEXT 6
+	CYCLE_NEXT	6,1,0
 
 
 op86:	@ STX $nn
@@ -943,12 +853,11 @@ op96:	@ STX $nn, Y
 	CYCLE_NEXT	4
 
 op8E:	@ STX $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
 	mov	r0, REG_X
 	WRITE_1
-	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
+	CYCLE_NEXT	4,1,0
 
 
 op84:	@ STY $nn
@@ -962,12 +871,11 @@ op94:	@ STY $nn, X
 	CYCLE_NEXT	4
 
 op8C:	@ STY $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
 	mov	r0, REG_Y
 	WRITE_1
-	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
+	CYCLE_NEXT	4,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -1020,26 +928,28 @@ opF6:	@ INC $nn, X
 	CYCLE_NEXT	6
 
 opEE:	@ INC $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_INC
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_INC
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opFE:	@ INC $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_INC
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_INC
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opE8:	@ INX
 	IMPLIED
@@ -1066,26 +976,28 @@ opD6:	@ DEC $nn, X
 	CYCLE_NEXT	6
 
 opCE:	@ DEC $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_DEC
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_DEC
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opDE:	@ DEC $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_DEC
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_DEC
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opCA:	@ DEX
 	IMPLIED
@@ -1148,49 +1060,39 @@ op75:	@ ADC $nn, X
 	CYCLE_NEXT	4
 
 op6D:	@ ADC $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op7D:	@ ADC $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op79:	@ ADC $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op61:	@ ADC ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_ADC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op71:	@ ADC ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_ADC
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 opEB:	@ USBC #$nn
 opE9:	@ SBC #$nn
@@ -1211,49 +1113,39 @@ opF5:	@ SBC $nn, X
 	CYCLE_NEXT	4
 
 opED:	@ SBC $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opFD:	@ SBC $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opF9:	@ SBC $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opE1:	@ SBC ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_SBC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opF1:	@ SBC ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_SBC
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -1299,49 +1191,39 @@ op35:	@ AND $nn, X
 	CYCLE_NEXT	4
 
 op2D:	@ AND $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op3D:	@ AND $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op39:	@ AND $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op21:	@ AND ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_AND
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op31:	@ AND ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_AND
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 op49:	@ EOR #$nn
@@ -1362,49 +1244,39 @@ op55:	@ EOR $nn, X
 	CYCLE_NEXT	4
 
 op4D:	@ EOR $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op5D:	@ EOR $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op59:	@ EOR $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op41:	@ EOR ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_EOR
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op51:	@ EOR ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_EOR
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 op09:	@ ORA #$nn
@@ -1425,49 +1297,39 @@ op15:	@ ORA $nn, X
 	CYCLE_NEXT	4
 
 op0D:	@ ORA $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op1D:	@ ORA $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op19:	@ ORA $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 op01:	@ ORA ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_ORA
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op11:	@ ORA ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_ORA
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 
@@ -1522,49 +1384,39 @@ opD5:	@ CMP $nn, X
 	CYCLE_NEXT	4
 
 opCD:	@ CMP $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opDD:	@ CMP $nnnn, X
+	CYCLE_PRE	4
 	ABSX_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opD9:	@ CMP $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opC1:	@ CMP ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_CMP
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opD1:	@ CMP ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_CMP
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 opE0:	@ CPX #$nn
@@ -1579,13 +1431,11 @@ opE4:	@ CPX $nn
 	CYCLE_NEXT	3
 
 opEC:	@ CPX $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_CPX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CPX
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 
 opC0:	@ CPY #$nn
@@ -1600,13 +1450,11 @@ opC4:	@ CPY $nn
 	CYCLE_NEXT	3
 
 opCC:	@ CPY $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_CPY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CPY
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -1637,13 +1485,11 @@ op24:	@ BIT $nn
 	CYCLE_NEXT	3
 
 op2C:	@ BIT $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_BIT
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_BIT
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -1706,26 +1552,28 @@ op16:	@ ASL $nn, X
 	CYCLE_NEXT	6
 
 op0E:	@ ASL $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_ASL
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_ASL
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op1E:	@ ASL $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ASL
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ASL
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 
 op4A:	@ LSR A
@@ -1748,26 +1596,28 @@ op56:	@ LSR $nn, X
 	CYCLE_NEXT	6
 
 op4E:	@ LSR $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_LSR
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_LSR
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op5E:	@ LSR $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_LSR
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_LSR
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -1835,27 +1685,29 @@ op36:	@ ROL $nn, X
 	CYCLE_NEXT	6
 
 op2E:	@ ROL $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_ROL
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_ROL
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 
 op3E:	@ ROL $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ROL
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ROL
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 
 op6A:	@ ROR A
@@ -1878,26 +1730,28 @@ op76:	@ ROR $nn, X
 	CYCLE_NEXT	6
 
 op6E:	@ ROR $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_ROR
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_ROR
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op7E:	@ ROR $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ROR
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ROR
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -2094,68 +1948,72 @@ op57:	@ SRE $nn, X
 	CYCLE_NEXT	6
 
 op4F:	@ SRE $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_SRE
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op5F:	@ SRE $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_SRE
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op5B:	@ SRE $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_SRE
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op43:	@ SRE ($nn, X)
+	CYCLE_PRE	8
 	INDX_ADDR
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_SRE
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op53:	@ SRE ($nn), Y
+	CYCLE_PRE	8
 	INDY_ADDR_W
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_SRE
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 
 op9C:	@ SHY $nnnn, X
+	CYCLE_PRE	5
 	ABSX_ADDR_W
 	OP_SHY
 	WRITE_1
-	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
+	CYCLE_NEXT	5,1,0
 
 opE7:	@ ISB $nn
 	ZERO_ADDR
@@ -2174,70 +2032,75 @@ opF7:	@ ISB $nn, X
 	CYCLE_NEXT	6
 
 opEF:   @ ISB $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_ISB
 	READ_WRITE_2
 	OP_SBC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_ISB
 	READ_WRITE_4
 	OP_SBC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 
 opFF:   @ ISB $nnnn,X
+	CYCLE_PRE	7
 	ABSX_ADDR
 	READ_WRITE_1
 	OP_ISB
 	READ_WRITE_2
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ISB
 	READ_WRITE_4
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opFB:	@ ISB $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR
 	READ_WRITE_1
 	OP_ISB
 	READ_WRITE_2
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ISB
 	READ_WRITE_4
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opE3:	@ ISB ($nn, X)
+	CYCLE_PRE	7
 	INDX_ADDR
 	READ_WRITE_1
 	OP_ISB
 	READ_WRITE_2
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ISB
 	READ_WRITE_4
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opF3:	@ ISB ($nn), Y
+	CYCLE_PRE	7
 	INDY_ADDR
 	READ_WRITE_1
 	OP_ISB
 	READ_WRITE_2
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_ISB
 	READ_WRITE_4
 	OP_SBC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opA7:	@ LAX $nn
 	ZERO_ADDR
@@ -2252,47 +2115,40 @@ opB7:	@ LAX $nn, Y
 	CYCLE_NEXT	4
 
 opAF:	@ LAX $nnnn
+	CYCLE_PRE	4
 	ABS_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LAX
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opBF:	@ LAX $nnnn, Y
+	CYCLE_PRE	4
 	ABSY_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LAX
-	CYCLE_NEXT	4
+	CYCLE_NEXT	4,1,0
 
 opA3:	@ LAX ($nn, X)
+	CYCLE_PRE	6
 	INDX_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_LAX
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opB3:	@ LAX ($nn), Y
+	CYCLE_PRE	5
 	INDY_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_LAX
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 op07:	@ SLO $nn
+	CYCLE_PRE	5
 	ZERO_ADDR
 	ZP_READ_W
 	OP_SLO
 	ZP_WRITE_W
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 op17:	@ SLO $nn, X
 	ZEROX_ADDR
@@ -2302,59 +2158,64 @@ op17:	@ SLO $nn, X
 	CYCLE_NEXT	6
 
 op0F:	@ SLO $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_SLO
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op1F:	@ SLO $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_SLO
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op1B:	@ SLO $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_SLO
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op03:	@ SLO ($nn, X)
+	CYCLE_PRE	8
 	INDX_ADDR
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_SLO
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op13:	@ SLO ($nn), Y
+	CYCLE_PRE	8
 	INDY_ADDR_W
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_SLO
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 opCB:	@ SBX #$nn
 	IMM_VALUE
@@ -2378,70 +2239,75 @@ opD7:	@ DCP $nn, X
 	CYCLE_NEXT	6
 
 opCF:	@ DCP $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_DCP
 	READ_WRITE_2
 	OP_CMP
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_DCP
 	READ_WRITE_4
 	OP_CMP
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 opDF:	@ DCP $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR
 	READ_WRITE_1
 	OP_DCP
 	READ_WRITE_2
 	OP_CMP
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_DCP
 	READ_WRITE_4
 	OP_CMP
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 opDB:	@ DCP $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR
 	READ_WRITE_1
 	OP_DCP
 	READ_WRITE_2
 	OP_CMP
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_DCP
 	READ_WRITE_4
 	OP_CMP
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 
 opC3:	@ DCP ($nn, X)
+	CYCLE_PRE	8
 	INDX_ADDR
 	READ_WRITE_1
 	OP_DCP
 	READ_WRITE_2
 	OP_CMP
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_DCP
 	READ_WRITE_4
 	OP_CMP
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 opD3:	@ DCP ($nn), Y
+	CYCLE_PRE	8
 	INDY_ADDR
 	READ_WRITE_1
 	OP_DCP
 	READ_WRITE_2
 	OP_CMP
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_DCP
 	READ_WRITE_4
 	OP_CMP
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op27:	@ RLA $nn
 	ZERO_ADDR
@@ -2458,59 +2324,64 @@ op37:	@ RLA $nn, X
 	CYCLE_NEXT	6
 
 op2F:	@ RLA $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op3F:	@ RLA $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op3B:	@ RLA $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op23:	@ RLA ($nn, X)
+	CYCLE_PRE	8
 	INDX_ADDR
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op33:	@ RLA ($nn), Y
+	CYCLE_PRE	8
 	INDY_ADDR_W
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op67:	@ RRA $nn
 	ZERO_ADDR
@@ -2529,69 +2400,74 @@ op77:	@ RRA $nn, X
 	CYCLE_NEXT	6
 
 op6F:	@ RRA $nnnn
+	CYCLE_PRE	6
 	ABS_ADDR
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
 	OP_ADC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 	READ_WRITE_3
 	OP_RRA
 	READ_WRITE_4
 	OP_ADC
-	CYCLE_NEXT	6
+	CYCLE_NEXT	6,1,0
 
 op7F:	@ RRA $nnnn, X
+	CYCLE_PRE	7
 	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
 	OP_ADC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_RRA
 	READ_WRITE_4
 	OP_ADC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op7B:	@ RRA $nnnn, Y
+	CYCLE_PRE	7
 	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
 	OP_ADC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 	READ_WRITE_3
 	OP_RRA
 	READ_WRITE_4
 	OP_ADC
-	CYCLE_NEXT	7
+	CYCLE_NEXT	7,1,0
 
 op63:	@ RRA ($nn, X)
+	CYCLE_PRE	8
 	INDX_ADDR
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
 	OP_ADC
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_RRA
 	READ_WRITE_4
 	OP_ADC
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 op73:	@ RRA ($nn), Y
+	CYCLE_PRE	8
 	INDY_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
 	OP_ADC
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 	READ_WRITE_3
 	OP_RRA
 	READ_WRITE_4
 	OP_ADC
-	CYCLE_NEXT	8
+	CYCLE_NEXT	8,1,0
 
 
 op04:	@ NOP $nn
@@ -2650,26 +2526,27 @@ opE2:
 @@@ ----
 @ JMP ($nnnn)
 op6C:
+	CYCLE_PRE	5
 	ABS_ADDR
 	and	r0, REG_ADDR, #0xFF
 	teq	r0, #0xFF
 	beq	jmp_indirect_bug
 	READ_WORD
 	REBASE_PC
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 jmp_indirect_bug:
 @@
 @@ BUG is : to not read word at REG_ADDR, because it loops
 @@ but read low part at REG_ADDR and high part at REG_ADDR&0xFF00 instead of REG_ADDR+1
 @@
-        READ
+	READ	0
 	mov	REG_PC, r0
 	and	REG_ADDR, REG_ADDR, #0xff00
-	READ
+	READ	0
 	orr	r0, REG_PC, r0, lsl #8
         REBASE_PC
 
-	CYCLE_NEXT	5
+	CYCLE_NEXT	5,1,0
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -2771,6 +2648,7 @@ op60:
 @@@ WARNING: decrements REG_PC
 @@@
 do_int:
+	add	REG_CYCLE, REG_CYCLE, #7
 	ldr	r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
 	sub	REG_PC, REG_PC, #1
 	sub	r0, REG_PC, r0
@@ -2788,7 +2666,6 @@ do_int:
 	REBASE_PC
 @	CYCLE_NEXT	7
 
-	add	REG_CYCLE, REG_CYCLE, #7
 	subs	REG_CYCLE, REG_CYCLE, #7*48<<16
 	ble	cpu_exec_end
 	ldrb	r0, [REG_PC], #1
@@ -2843,28 +2720,30 @@ reset_cpu:
 @@@ low-level memhandlers
 @@@
 
+/*
+@ disabled because no improvements noticed, only causes trouble (with gg for example)
 read_rom_byte:
-#ifndef DEBUG_ASM_6502
+@ try to avoid lookup of every address at least for ROM and RAM areas
+@ I've verified that if ARead[0xfff0] points to CartBR, it is always normal ROM read.
 	ldr	r0, =CartBR
 	ldr	r2, =ARead
 	mov	r1, #0xff00
 	orr	r1, r1, r1, lsr #4
 	ldr	r1, [r2, r1, lsl #2]		@ if (ARead[0xfff0] == CartBR)
 	cmp	r0, r1
-	bne	read_ppu_reg
+	bne	read_byte
 	ldr	r2, =Page
 	mov	r1, REG_ADDR, lsr #11
 	ldr	r2, [r2, r1, lsl #2]
 	ldrb	r0, [r2, REG_ADDR]
 	bx	lr
-#endif
+*/
 
 
-read_ppu_reg:
-read_high_reg:
-read_save_ram:
+read_byte:
 	@ must preserve r3 for the callers too
 	@ TODO: check if all of saves are needed, _DB (is full needed?)
+	FLUSH_TIMESTAMP r2			@ needed for TryFixit1
 	str     REG_PC,     [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)]	@ might get rebased
 	str     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 	str     REG_CYCLE,  [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)]	@ might get used
@@ -2895,10 +2774,7 @@ read_save_ram:
 	bx	lr
 
 
-write_ppu_reg:
-write_high_reg:
-write_save_ram:
-write_rom_byte:
+write_byte:
 	FLUSH_TIMESTAMP r2			@ Blaster Master, more...
 #ifndef DEBUG_ASM_6502
 	@ must preserve r0 (data) and r3 for the callers
@@ -2957,13 +2833,26 @@ cpu_exec:
 
 @	ldr   REG_OP_TABLE, = cpu_exec_table @ set on init
 
-	CYCLE_NEXT	0, 0
+	ldrb	r0, [REG_PC], #1
+	tst	REG_P_REST, #0xff<<8
+	ldreq	pc, [REG_OP_TABLE, r0, lsl #2]
+
+	@ assumption: NMI can be set only on very first run, because it is only set once before vblank..
+	tst	REG_P_REST, #FCEU_IQNMI<<8
+	bne	do_int
+	tst	REG_P_REST, #P_REST_I_FLAG
+	@@ if I_FLAG=1, continue execution, don't trigger IRQ
+	bicne	REG_P_REST, REG_P_REST, #FCEU_IQTEMP<<8
+	ldrne	pc, [REG_OP_TABLE, r0, lsl #2]
+	@@ I_FLAG=0 and REST is checked, we have a IRQ
+	b	do_int
+
 
 cpu_exec_end:
 	FLUSH_TIMESTAMP r0
 
 	tst	REG_P_REST, #1<<16
-	blne	do_irq_hook_noflushts
+	bne	do_irq_hook_final
 
 	ldr     r0, =nes_registers
 	stmia	r0, {r4-r12}
@@ -3042,7 +2931,6 @@ nes_internal_ram:
 	.fill	0x100, 1, 0
 nes_stack:
 	.fill	0x700, 1, 0
-@ TODO: write code which keeps it up-to-date
 pc_base:
 	.long	0
 MapIRQHook:
@@ -3170,6 +3058,7 @@ op9E:	@ SHX $nnnn, Y
 	.globl	RAM
 	.globl	timestamp
 #else
+	.globl	X_
 	.globl	nes_internal_ram
 	.globl	timestamp_a
 #endif
@@ -3239,12 +3128,20 @@ TriggerNMINSF_a:
 
 
 X6502_AddCycles_a:
+	ldr	r3, =timestamp
 	ldr	r2, =nes_registers
+	ldr	r1, [r3]
+	add	r1, r1, r0
+	str	r1, [r3]
 	ldrsh	r1, [r2, #0x1e]
 	mvn	r3, #47			@ r3=-48
-	mla	r0, r3, r0, r1
-	strh	r0, [r2, #0x1e]
-	bx	lr
+	mla	r3, r0, r3, r1
+	ldr	r1, =MapIRQHook		@ hack..
+	strh	r3, [r2, #0x1e]
+	ldr	r1, [r1]
+	tst	r1, r1
+	bxeq	lr
+	bx	r1
 
 
 @ rebase PC when not executing or in memhandlers
@@ -3266,25 +3163,60 @@ X6502_Rebase_a:
 do_irq_hook:
 	FLUSH_TIMESTAMP r0
 
-do_irq_hook_noflushts:
+	@ get irqhook cycles
+	and	r0, REG_CYCLE, #0xff00
+	mov	r0, r0, lsr #8
 #ifndef DEBUG_ASM_6502
 	@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
 	str     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
-	mov	REG_P_REST, lr			@ r8
+	mov	REG_P_REST, REG_OP_TABLE				@ r8
 
 	@ if somebody modifies MapIRQHook without calling reset, we are doomed
 	mov	lr, pc
 	ldr	pc, [REG_OP_TABLE, #OTOFFS_IRQ_HOOK]
 
-	ldr	REG_OP_TABLE, =cpu_exec_table	@ got trashed because was in r12
-	mov	lr, REG_P_REST
+	mov	REG_OP_TABLE, REG_P_REST				@ got trashed because was in r12
 	ldr     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 #else
 	ldr	r1, =mapirq_cyc_a
 	str	r0, [r1]
 	mov	r1, r0
 #endif
+
+	ldrb	r0, [REG_PC], #1
+	bic	REG_CYCLE, REG_CYCLE, #0xff00
+	tst	REG_P_REST, #0xff<<8
+	ldreq	pc, [REG_OP_TABLE, r0, lsl #2]
+
+	@ do some messing to find out which IRQ is pending..
+	tst	REG_P_REST, #P_REST_I_FLAG
+	@@ if I_FLAG=1, continue execution, don't trigger IRQ
+	bicne	REG_P_REST, REG_P_REST, #FCEU_IQTEMP<<8
+	ldrne	pc, [REG_OP_TABLE, r0, lsl #2]
+	@@ I_FLAG=0 and REST is checked, we have a IRQ
+	b	do_int
+
+
+do_irq_hook_final:
+	ldr     r1, =nes_registers
+
+	@ get irqhook cycles
+	and	r0, REG_CYCLE, #0xff00
+	bic	REG_CYCLE, REG_CYCLE, #0xff00
+	mov	r0, r0, lsr #8
+
+	stmia	r1, {r4-r12}
+
+	ldmfd   r13!,{r4-r11,lr}
+
+#ifndef DEBUG_ASM_6502
+	ldr	pc, [REG_OP_TABLE, #OTOFFS_IRQ_HOOK]
+#else
+	ldr	r1, =mapirq_cyc_a
+	str	r0, [r1]
+	mov	r1, r0
 	bx	lr
+#endif
 
 
 @ vim:filetype=armasm