X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?p=fceu.git;a=blobdiff_plain;f=ncpu.S;h=fcf8fed8806607b611cd606733f88fe0d3d0be2b;hp=381437f05363af7d1be7f9d72db95dce04ed4a48;hb=c92577a7feb5f17d4386ed0554e9626b456d4461;hpb=af32b6c2f0ed2f1a4582c3e8d7ac704b9c61fa4c

diff --git a/ncpu.S b/ncpu.S
index 381437f..fcf8fed 100644
--- a/ncpu.S
+++ b/ncpu.S
@@ -15,6 +15,9 @@
 #define OTOFFS_NES_STACK (nes_stack        - cpu_exec_table)
 #define OTOFFS_NES_REGS  (nes_registers    - cpu_exec_table)
 #define OTOFFS_PC_BASE   (pc_base          - cpu_exec_table)
+#define OTOFFS_IRQ_HOOK  (MapIRQHook       - cpu_exec_table)
+#define OTOFFS_TIMESTAMP (timestamp        - cpu_exec_table)
+#define OTOFFS_X         (X_               - cpu_exec_table)
 
 @ fceu
 #define FCEU_IQNMI      0x08
@@ -28,7 +31,17 @@
 	SECTION_TEXT
 	ALIGN
 
-
+/*
+bbbb:
+.ascii "lsr_a: %02x"
+.byte 0x0a,0
+.align 4
+stmfd sp!,{r0-r3,r12,lr}
+mov r1,r0
+ldr r0,=bbbb
+bl printf
+ldmfd sp!,{r0-r3,r12,lr}
+*/
 
 @@@
 @@@ r0	=  Address (unbased)
@@ -36,6 +49,12 @@
 @@@
 .macro	REBASE_PC
 	@ FIXME: do something with mem not in Page[].
+@	stmfd	sp!, {r0-r3,r12,lr}
+@	mov	r1, r0
+@	ldr     r0, =bbbb
+@	bl      printf
+@	ldmfd	sp!, {r0-r3,r12,lr}
+
 	cmp     r0, #0x2000
 	ldrge	r1, =Page
 	movge	r2, r0, lsr #11
@@ -48,8 +67,14 @@
 .endm
 
 
-.macro	RETURN_FROM_CPU_EXEC
-	b	cpu_exec_end
+@ updates fceu "timestamp" variable
+@ loads cycles to reg, reg!=r1, trashes r1
+.macro	FLUSH_TIMESTAMP reg
+	ldr	r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
+	and	\reg, REG_CYCLE, #0xff
+	add	r1, r1, \reg
+	bic	REG_CYCLE, REG_CYCLE, #0xff
+	str	r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
 .endm
 
 
@@ -63,11 +88,16 @@
 @@@
 @@@ ¤Ê¤ó¤«Ì¾Á°¤¬ÊѤÀ¤Ê(¤É¡¼¤Ç¤â¤¤¡¼¤±¤É¡¼
 @@@
-.macro	CYCLE_NEXT	n
+.macro	CYCLE_NEXT	n, hook_check=1
 	@@DEBUG_INFO
 
-	subs	REG_CYCLE, REG_CYCLE, #\n*48
+	add	REG_CYCLE, REG_CYCLE, #\n
+	subs	REG_CYCLE, REG_CYCLE, #\n*48<<16
 	ble	cpu_exec_end
+.if \hook_check
+	tst	REG_P_REST, #1<<16
+	blne	do_irq_hook
+.endif
 	ldrb	r0, [REG_PC], #1
 	tst	REG_P_REST, #0xff<<8
 	ldreq	pc, [REG_OP_TABLE, r0, lsl #2]
@@ -93,11 +123,6 @@
 @@@ CLI¡¦PHP¤Ê¤É¥Õ¥é¥°¤òÊѹ¹¤·¤¿¾ì¹ç¤Ï¤³¤ì
 @@@
 .macro	CYCLE_NEXT_INT	n
-@	@@DEBUG_INFO
-@
-@	subs	REG_CYCLE, REG_CYCLE, #\n*48
-@	bgt	cpu_exec_check_int
-@	RETURN_FROM_CPU_EXEC
 	CYCLE_NEXT	\n
 .endm
 
@@ -166,54 +191,16 @@
 @@@ ¥¹¥È¥¢¤¹¤ë¤À¤±¤ÎÌ¿Îá
 
 @@@
-@@@ 16¥Ó¥Ã¥È¥¢¥É¥ì¥¹¤«¤é¥í¡¼¥É¤Î¤ß
-@@@
-@@@ RAM¤«¤é¤Î¥í¡¼¥É¤¬°ìÈÖ¿¤¤¤Î¤ÇÍ¥À褹¤ë
-@@@
-@@@ READ_1
-@@@ OP
-@@@ READ_2
-@@@ OP
+@@@ Read byte
 @@@
-@@@ ¤Î¤è¤¦¤Ë»È¤¦
-
-.macro	READ_1
-	movs	r1, REG_ADDR, lsr #13
-	adr	lr, 9999f
-	@@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
-	@@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
-	ldrne	pc, [lr, -r1, lsl #2]
-	@@ RAM¤«¤é¥í¡¼¥É
-	bic	r0, REG_ADDR, #0x1800
-	add	r0, r0, #OTOFFS_NES_RAM
-	ldrb	r0, [r0, REG_OP_TABLE]
-.endm
-
-.macro	READ_2
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_save_ram
-	.long	read_high_reg
-	.long	read_ppu_reg
-9999:
-.endm
 
 .macro	READ
-	mov	r1, REG_ADDR, lsr #13
 	adr	lr, 1f
-	ldr	pc, [pc, r1, lsl #2]
-	nop
-	.long	2f		@ fast path
-	.long	read_ppu_reg
-	.long	read_high_reg
-	.long	read_save_ram
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-2:
+	tst	REG_ADDR, #0x8000
+	bne	read_rom_byte
+	tst	REG_ADDR, #0xe000
+	bne	read_byte
+	@ RAM
 	bic	r0, REG_ADDR, #0x1800
 	add	r0, r0, #OTOFFS_NES_RAM
 	ldrb	r0, [r0, REG_OP_TABLE]
@@ -235,12 +222,12 @@
 @@@ OP¤Ç¤Ïr3¤òÊݸ¤·¤Ê¤±¤ì¤Ð¤Ê¤é¤Ê¤¤
 
 .macro	READ_WRITE_1
-	movs	r3, REG_ADDR, lsr #13
 	adr	lr, 9999f
-	@@ 0¤Ç¤Ê¤¤»þ¤Ï¥¸¥ã¥ó¥×¤¹¤ë¡£
-	@@ ¤Á¤ç¤Ã¤È¹©Éפ·¤Æ1¥¯¥í¥Ã¥¯¸º¤é¤¹
-	ldrne	pc, [lr, -r3, lsl #2]
-	@@ RAM¤«¤é¥í¡¼¥É
+	tst	REG_ADDR, #0x8000
+	bne	read_rom_byte
+	tst	REG_ADDR, #0xe000
+	bne	read_byte
+	@ RAM
 	bic	REG_ADDR, REG_ADDR, #0x1800
 	add	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
 	ldrb	r0, [REG_ADDR, REG_OP_TABLE]!
@@ -251,61 +238,27 @@
 .endm
 
 .macro	READ_WRITE_3
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_rom_byte
-	.long	read_save_ram
-	.long	read_high_reg
-	.long	read_ppu_reg
 9999:
+	bl	write_byte	@ rmw first writes unmodified data
 .endm
 
 .macro	READ_WRITE_4
-	adr	lr, 1f
-	ldr	pc, [pc, r3, lsl #2]
-	nop
-	nop
-	.long	write_ppu_reg
-	.long	write_high_reg
-	.long	write_save_ram
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-1:
+	bl	write_byte	@ and only then modified (Blaster Master)
 .endm
 
 @@@
-@@@ ½ñ¤­¹þ¤ß¤À¤±¤Î¾ì¹ç
+@@@ Write r0 to [addr]
 @@@
-@@@ WRITE_1
-@@@ TAIL
-@@@ WRITE_2
-@@@ TAIL
-@@@ ¤È¤¹¤ë
 
 .macro	WRITE_1
 	@@DEBUG_INFO
 
-	movs	r1, REG_ADDR, lsr #13
-	adr	lr, 9999f
-	ldrne	pc, [lr, -r1, lsl #2]
-	bic	REG_ADDR, REG_ADDR, #0x1800
-	add	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
-
-	strb	r0, [REG_ADDR, REG_OP_TABLE]
-.endm
+	tst	REG_ADDR, #0xe000
+	biceq	REG_ADDR, REG_ADDR, #0x1800
+	addeq	REG_ADDR, REG_ADDR, #OTOFFS_NES_RAM
 
-.macro	WRITE_2
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_rom_byte
-	.long	write_save_ram
-	.long	write_high_reg
-	.long	write_ppu_reg
-9999:
+	streqb	r0, [REG_ADDR, REG_OP_TABLE]
+	blne	write_byte
 .endm
 
 @@@
@@ -426,7 +379,16 @@
 	bic	REG_ADDR, REG_ADDR, #0x10000
 	and	r0,REG_ADDR,#0xff
 	cmp	REG_Y,r0
-	subgt	REG_CYCLE,REG_CYCLE,#1*48
+	addgt	REG_CYCLE, REG_CYCLE, #1
+	subgt	REG_CYCLE, REG_CYCLE, #1*48<<16
+.endm
+
+@ Indirect Indexed (for writes and rmws)
+.macro	INDY_ADDR_W
+	ZERO_ADDR
+	ZP_READ_ADDR
+	add	REG_ADDR, REG_ADDR, REG_Y
+	bic	REG_ADDR, REG_ADDR, #0x10000
 .endm
 
 
@@ -455,7 +417,15 @@
 	bic	REG_ADDR, REG_ADDR, #0x10000
 	and	r0,REG_ADDR,#0xff
 	cmp	REG_X,r0
-	subgt	REG_CYCLE,REG_CYCLE,#1*48
+	addgt	REG_CYCLE, REG_CYCLE, #1
+	subgt	REG_CYCLE, REG_CYCLE, #1*48<<16
+.endm
+
+@ Absolute Indexed (for writes and rmws)
+.macro	ABSX_ADDR_W
+	ABS_ADDR
+	add	REG_ADDR, REG_ADDR, REG_X
+	bic	REG_ADDR, REG_ADDR, #0x10000
 .endm
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -466,9 +436,19 @@
 	bic	REG_ADDR, REG_ADDR, #0x10000
 	and	r0,REG_ADDR,#0xff
 	cmp	REG_Y,r0
-	subgt	REG_CYCLE,REG_CYCLE,#1*48
+	addgt	REG_CYCLE, REG_CYCLE, #1
+	subgt	REG_CYCLE, REG_CYCLE, #1*48<<16
+.endm
+
+@ Absolute Indexed (for writes and rmws)
+.macro	ABSY_ADDR_W
+	ABS_ADDR
+	add	REG_ADDR, REG_ADDR, REG_Y
+	bic	REG_ADDR, REG_ADDR, #0x10000
 .endm
 
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+
 @@@ P ¤òÉü¸µ¤¹¤ë
 @@@ r0		=> 6502 ¤Î P ¥ì¥¸¥¹¥¿
 @@@ REG_NZ	<= Éü¸µ¤µ¤ì¤¿ REG_NZ
@@ -690,50 +670,34 @@ opB5:	@ LDA $nn, X
 
 opAD:	@ LDA $nnnn
 	ABS_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
 	CYCLE_NEXT	4
 
 opBD:	@ LDA $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
 	CYCLE_NEXT	4
 
 opB9:	@ LDA $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDA
 	CYCLE_NEXT	4
 
 opA1:	@ LDA ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_LDA
 	CYCLE_NEXT	6
 
 opB1:	@ LDA ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_LDA
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_LDA
 	CYCLE_NEXT	5
 
-
 opA2:	@ LDX #$nn
 	IMM_VALUE
 	OP_LDX
@@ -753,19 +717,13 @@ opB6:	@ LDX $nn, Y
 
 opAE:	@ LDX $nnnn
 	ABS_ADDR
-	READ_1
-	OP_LDX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDX
 	CYCLE_NEXT	4
 
 opBE:	@ LDX $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_LDX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDX
 	CYCLE_NEXT	4
 
@@ -792,19 +750,13 @@ opB4:	@ LDY $nn, X
 
 opAC:	@ LDY $nnnn
 	ABS_ADDR
-	READ_1
-	OP_LDY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDY
 	CYCLE_NEXT	4
 
 opBC:	@ LDY $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_LDY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LDY
 	CYCLE_NEXT	4
 
@@ -839,40 +791,30 @@ op8D:	@ STA $nnnn
 	OP_STA
 	WRITE_1
 	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
 
 op9D:	@ STA $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	OP_STA
 	WRITE_1
 	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
 
 op99:	@ STA $nnnn, Y
-	ABSY_ADDR
+	ABSY_ADDR_W
 	OP_STA
 	WRITE_1
 	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
 
 op81:	@ STA ($nn, X)
 	INDX_ADDR
 	OP_STA
 	WRITE_1
 	CYCLE_NEXT 6
-	WRITE_2
-	CYCLE_NEXT 6
 
 op91:	@ STA ($nn), Y
-	INDY_ADDR
+	INDY_ADDR_W
 	OP_STA
 	WRITE_1
 	CYCLE_NEXT 6
-	WRITE_2
-	CYCLE_NEXT 6
 
 
 op86:	@ STX $nn
@@ -890,8 +832,6 @@ op8E:	@ STX $nnnn
 	mov	r0, REG_X
 	WRITE_1
 	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
 
 
 op84:	@ STY $nn
@@ -909,8 +849,6 @@ op8C:	@ STY $nnnn
 	mov	r0, REG_Y
 	WRITE_1
 	CYCLE_NEXT 4
-	WRITE_2
-	CYCLE_NEXT 4
 
 
 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@ -974,7 +912,7 @@ opEE:	@ INC $nnnn
 	CYCLE_NEXT	6
 
 opFE:	@ INC $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_INC
 	READ_WRITE_2
@@ -1020,7 +958,7 @@ opCE:	@ DEC $nnnn
 	CYCLE_NEXT	6
 
 opDE:	@ DEC $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_DEC
 	READ_WRITE_2
@@ -1092,46 +1030,31 @@ op75:	@ ADC $nn, X
 
 op6D:	@ ADC $nnnn
 	ABS_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
 	CYCLE_NEXT	4
 
 op7D:	@ ADC $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
 	CYCLE_NEXT	4
 
 op79:	@ ADC $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ADC
 	CYCLE_NEXT	4
 
 op61:	@ ADC ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_ADC
 	CYCLE_NEXT	6
 
 op71:	@ ADC ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_ADC
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_ADC
 	CYCLE_NEXT	5
 
@@ -1155,46 +1078,31 @@ opF5:	@ SBC $nn, X
 
 opED:	@ SBC $nnnn
 	ABS_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
 	CYCLE_NEXT	4
 
 opFD:	@ SBC $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
 	CYCLE_NEXT	4
 
 opF9:	@ SBC $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_SBC
 	CYCLE_NEXT	4
 
 opE1:	@ SBC ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_SBC
 	CYCLE_NEXT	6
 
 opF1:	@ SBC ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_SBC
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_SBC
 	CYCLE_NEXT	5
 
@@ -1243,46 +1151,31 @@ op35:	@ AND $nn, X
 
 op2D:	@ AND $nnnn
 	ABS_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
 	CYCLE_NEXT	4
 
 op3D:	@ AND $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
 	CYCLE_NEXT	4
 
 op39:	@ AND $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_AND
 	CYCLE_NEXT	4
 
 op21:	@ AND ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_AND
 	CYCLE_NEXT	6
 
 op31:	@ AND ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_AND
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_AND
 	CYCLE_NEXT	5
 
@@ -1306,46 +1199,31 @@ op55:	@ EOR $nn, X
 
 op4D:	@ EOR $nnnn
 	ABS_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
 	CYCLE_NEXT	4
 
 op5D:	@ EOR $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
 	CYCLE_NEXT	4
 
 op59:	@ EOR $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_EOR
 	CYCLE_NEXT	4
 
 op41:	@ EOR ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_EOR
 	CYCLE_NEXT	6
 
 op51:	@ EOR ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_EOR
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_EOR
 	CYCLE_NEXT	5
 
@@ -1369,46 +1247,31 @@ op15:	@ ORA $nn, X
 
 op0D:	@ ORA $nnnn
 	ABS_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
 	CYCLE_NEXT	4
 
 op1D:	@ ORA $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
 	CYCLE_NEXT	4
 
 op19:	@ ORA $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_ORA
 	CYCLE_NEXT	4
 
 op01:	@ ORA ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_ORA
 	CYCLE_NEXT	6
 
 op11:	@ ORA ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_ORA
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_ORA
 	CYCLE_NEXT	5
 
@@ -1466,46 +1329,31 @@ opD5:	@ CMP $nn, X
 
 opCD:	@ CMP $nnnn
 	ABS_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
 	CYCLE_NEXT	4
 
 opDD:	@ CMP $nnnn, X
 	ABSX_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
 	CYCLE_NEXT	4
 
 opD9:	@ CMP $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CMP
 	CYCLE_NEXT	4
 
 opC1:	@ CMP ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_CMP
 	CYCLE_NEXT	6
 
 opD1:	@ CMP ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_CMP
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_CMP
 	CYCLE_NEXT	5
 
@@ -1523,10 +1371,7 @@ opE4:	@ CPX $nn
 
 opEC:	@ CPX $nnnn
 	ABS_ADDR
-	READ_1
-	OP_CPX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CPX
 	CYCLE_NEXT	4
 
@@ -1544,10 +1389,7 @@ opC4:	@ CPY $nn
 
 opCC:	@ CPY $nnnn
 	ABS_ADDR
-	READ_1
-	OP_CPY
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_CPY
 	CYCLE_NEXT	4
 
@@ -1581,10 +1423,7 @@ op24:	@ BIT $nn
 
 op2C:	@ BIT $nnnn
 	ABS_ADDR
-	READ_1
-	OP_BIT
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_BIT
 	CYCLE_NEXT	4
 
@@ -1660,7 +1499,7 @@ op0E:	@ ASL $nnnn
 	CYCLE_NEXT	6
 
 op1E:	@ ASL $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ASL
 	READ_WRITE_2
@@ -1702,7 +1541,7 @@ op4E:	@ LSR $nnnn
 	CYCLE_NEXT	6
 
 op5E:	@ LSR $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_LSR
 	READ_WRITE_2
@@ -1790,7 +1629,7 @@ op2E:	@ ROL $nnnn
 
 
 op3E:	@ ROL $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ROL
 	READ_WRITE_2
@@ -1832,7 +1671,7 @@ op6E:	@ ROR $nnnn
 	CYCLE_NEXT	6
 
 op7E:	@ ROR $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_ROR
 	READ_WRITE_2
@@ -1863,14 +1702,16 @@ op7E:	@ ROR $nnnn, X
 	and	r1,r1,#0xff
 	add	r1,r3,r1
 	tst	r1,#0x100
-	subne	REG_CYCLE,REG_CYCLE, #1*48
+	addne	REG_CYCLE, REG_CYCLE, #1
+	subne	REG_CYCLE, REG_CYCLE, #1*48<<16
 .endm
 
 .macro	BRANCH_EQ
 	ldreqsb	r1, [REG_PC], #1
 	movne	r1, #1
 	add	REG_PC, REG_PC, r1
-	subeq	REG_CYCLE, REG_CYCLE, #1*48
+	addeq	REG_CYCLE, REG_CYCLE, #1
+	subeq	REG_CYCLE, REG_CYCLE, #1*48<<16
 	bne	1f
 	HAD_BRANCH
 1:
@@ -1880,7 +1721,8 @@ op7E:	@ ROR $nnnn, X
 	ldrnesb	r1, [REG_PC], #1
 	moveq	r1, #1
 	add	REG_PC, REG_PC, r1
-	subne	REG_CYCLE, REG_CYCLE, #1*48
+	addne	REG_CYCLE, REG_CYCLE, #1
+	subne	REG_CYCLE, REG_CYCLE, #1*48<<16
 	beq	1f
 	HAD_BRANCH
 1:
@@ -2078,7 +1920,7 @@ op43:	@ SRE ($nn, X)
 	CYCLE_NEXT	8
 
 op53:	@ SRE ($nn), Y
-	INDY_ADDR
+	INDY_ADDR_W
 	READ_WRITE_1
 	OP_SRE
 	READ_WRITE_2
@@ -2090,12 +1932,10 @@ op53:	@ SRE ($nn), Y
 
 
 op9C:	@ SHY $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	OP_SHY
 	WRITE_1
 	CYCLE_NEXT 5
-	WRITE_2
-	CYCLE_NEXT 5
 
 opE7:	@ ISB $nn
 	ZERO_ADDR
@@ -2193,37 +2033,25 @@ opB7:	@ LAX $nn, Y
 
 opAF:	@ LAX $nnnn
 	ABS_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LAX
 	CYCLE_NEXT	4
 
 opBF:	@ LAX $nnnn, Y
 	ABSY_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	4
-	READ_2
+	READ
 	OP_LAX
 	CYCLE_NEXT	4
 
 opA3:	@ LAX ($nn, X)
 	INDX_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	6
-	READ_2
+	READ
 	OP_LAX
 	CYCLE_NEXT	6
 
 opB3:	@ LAX ($nn), Y
 	INDY_ADDR
-	READ_1
-	OP_LAX
-	CYCLE_NEXT	5
-	READ_2
+	READ
 	OP_LAX
 	CYCLE_NEXT	5
 
@@ -2264,7 +2092,7 @@ op1F:	@ SLO $nnnn, X
 	CYCLE_NEXT	7
 
 op1B:	@ SLO $nnnn, Y
-	ABSY_ADDR
+	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
@@ -2286,7 +2114,7 @@ op03:	@ SLO ($nn, X)
 	CYCLE_NEXT	8
 
 op13:	@ SLO ($nn), Y
-	INDY_ADDR
+	INDY_ADDR_W
 	READ_WRITE_1
 	OP_SLO
 	READ_WRITE_2
@@ -2409,7 +2237,7 @@ op2F:	@ RLA $nnnn
 	CYCLE_NEXT	6
 
 op3F:	@ RLA $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
@@ -2420,11 +2248,11 @@ op3F:	@ RLA $nnnn, X
 	CYCLE_NEXT	7
 
 op3B:	@ RLA $nnnn, Y
-	ABSY_ADDR
+	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_RLA
-    READ_WRITE_2
-    CYCLE_NEXT	7
+	READ_WRITE_2
+	CYCLE_NEXT	7
 	READ_WRITE_3
 	OP_RLA
 	READ_WRITE_4
@@ -2442,7 +2270,7 @@ op23:	@ RLA ($nn, X)
 	CYCLE_NEXT	8
 
 op33:	@ RLA ($nn), Y
-	INDY_ADDR
+	INDY_ADDR_W
 	READ_WRITE_1
 	OP_RLA
 	READ_WRITE_2
@@ -2482,7 +2310,7 @@ op6F:	@ RRA $nnnn
 	CYCLE_NEXT	6
 
 op7F:	@ RRA $nnnn, X
-	ABSX_ADDR
+	ABSX_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
@@ -2495,7 +2323,7 @@ op7F:	@ RRA $nnnn, X
 	CYCLE_NEXT	7
 
 op7B:	@ RRA $nnnn, Y
-	ABSY_ADDR
+	ABSY_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
@@ -2521,7 +2349,7 @@ op63:	@ RRA ($nn, X)
 	CYCLE_NEXT	8
 
 op73:	@ RRA ($nn), Y
-	INDY_ADDR
+	INDY_ADDR_W
 	READ_WRITE_1
 	OP_RRA
 	READ_WRITE_2
@@ -2708,9 +2536,11 @@ op60:
 
 @@@
 @@@ ³ä¤ê¹þ¤ß¤Î½èÍý
+@@@ WARNING: decrements REG_PC
 @@@
 do_int:
 	ldr	r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
+	sub	REG_PC, REG_PC, #1
 	sub	r0, REG_PC, r0
 	PUSH_WORD
 	bic	REG_P_REST, REG_P_REST, #P_REST_B_FLAG
@@ -2724,7 +2554,19 @@ do_int:
 	subne	REG_ADDR, REG_ADDR, #NMI_VECTOR
 	READ_WORD
 	REBASE_PC
-	CYCLE_NEXT	7
+@	CYCLE_NEXT	7
+
+	add	REG_CYCLE, REG_CYCLE, #7
+	subs	REG_CYCLE, REG_CYCLE, #7*48<<16
+	ble	cpu_exec_end
+	ldrb	r0, [REG_PC], #1
+	tst	REG_P_REST, #0xff<<8
+	ldreq	pc, [REG_OP_TABLE, r0, lsl #2]
+
+	tst	REG_P_REST, #P_REST_I_FLAG
+	ldrne	pc, [REG_OP_TABLE, r0, lsl #2]
+	b	do_int
+
 
 @@@
 @@@ ¥ê¥»¥Ã¥È¤Î½èÍý
@@ -2742,6 +2584,12 @@ reset_cpu:
 	@@REG_P_REST = 0, don't touch REG_S
 	bic	REG_P_REST, REG_P_REST, #0xff
 
+	@ fceu: set MapIRQHook present flag
+	ldr	r0, [REG_OP_TABLE, #OTOFFS_IRQ_HOOK]
+	tst	r0, r0
+	orrne	REG_P_REST, REG_P_REST, #1<<16
+	biceq	REG_P_REST, REG_P_REST, #1<<16
+
 	@@ R bit is always 1
 	orr	REG_NZ, REG_NZ, #P_R_FLAG
 
@@ -2763,22 +2611,45 @@ reset_cpu:
 @@@ low-level memhandlers
 @@@
 
-read_ppu_reg:
-read_high_reg:
-read_save_ram:
 read_rom_byte:
+#ifndef DEBUG_ASM_6502
+	ldr	r0, =CartBR
+	ldr	r2, =ARead
+	mov	r1, #0xff00
+	orr	r1, r1, r1, lsr #4
+	ldr	r1, [r2, r1, lsl #2]		@ if (ARead[0xfff0] == CartBR)
+	cmp	r0, r1
+	bne	read_byte
+	ldr	r2, =Page
+	mov	r1, REG_ADDR, lsr #11
+	ldr	r2, [r2, r1, lsl #2]
+	ldrb	r0, [r2, REG_ADDR]
+	bx	lr
+#endif
+
+
+read_byte:
 	@ must preserve r3 for the callers too
-	@ TODO: check if all of saves are needed, optimize read_rom_byte, _DB
+	@ TODO: check if all of saves are needed, _DB (is full needed?)
 	str     REG_PC,     [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)]	@ might get rebased
 	str     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 	str     REG_CYCLE,  [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)]	@ might get used
 	mov     REG_PC, lr			@ r7
 	mov	REG_P_REST, r3			@ r8
 
+#ifndef DEBUG_ASM_6502
 	ldr	r2, =ARead
 	bic     r0, REG_ADDR, #0x00ff0000
 	mov	lr, pc
 	ldr	pc, [r2, r0, lsl #2]
+#else
+	ldr	r2, =dread_count_a
+	ldr	r0, =dreads
+	ldr	r1, [r2]
+	ldrb	r0, [r0, r1]
+	add	r1, r1, #1
+	str	r1, [r2]
+#endif
 
 	ldr	REG_OP_TABLE, =cpu_exec_table	@ got trashed because was in r12
 	mov	lr, REG_PC
@@ -2786,19 +2657,20 @@ read_rom_byte:
 	ldr     REG_PC,     [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)]	@ might get rebased
 	ldr     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 	ldr     REG_CYCLE,  [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)]	@ might get used
+	strb    r0,         [REG_OP_TABLE, #(OTOFFS_X + 0x10)]		@ X.DB
 	bx	lr
 
 
-write_ppu_reg:
-write_high_reg:
-write_save_ram:
-write_rom_byte:
-	@ must preserve r3 for the callers too
+write_byte:
+	FLUSH_TIMESTAMP r2			@ Blaster Master, more...
+#ifndef DEBUG_ASM_6502
+	@ must preserve r0 (data) and r3 for the callers
 	str     REG_PC,     [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)]	@ might get rebased
 	str     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 	str     REG_CYCLE,  [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)]	@ might get used
 	mov     REG_PC, lr			@ r7
 	mov	REG_P_REST, r3			@ r8
+	mov	REG_CYCLE, r0			@ r11
 
 	ldr	r2, =BWrite
 	mov	r1, r0
@@ -2809,9 +2681,22 @@ write_rom_byte:
 	ldr	REG_OP_TABLE, =cpu_exec_table	@ got trashed because was in r12
 	mov	lr, REG_PC
 	mov	r3, REG_P_REST
+	mov	r0, REG_CYCLE
 	ldr     REG_PC,     [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)]	@ might get rebased
 	ldr     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
 	ldr     REG_CYCLE,  [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)]	@ might get used
+#else
+	ldr	r1, =dwrite_count_a
+	ldr	r2, =dwrites_a
+	ldr	r1, [r1]
+	and	r0, r0, #0xff
+	orr	r0, r0, REG_ADDR, lsl #8
+	str	r0, [r2, r1, lsl #2]
+	ldr	r2, =dwrite_count_a
+	add	r1, r1, #1
+	str	r1, [r2]
+	and	r0, r0, #0xff
+#endif
 	bx	lr
 
 
@@ -2835,9 +2720,14 @@ cpu_exec:
 
 @	ldr   REG_OP_TABLE, = cpu_exec_table @ set on init
 
-	CYCLE_NEXT	0
+	CYCLE_NEXT	0, 0
 
 cpu_exec_end:
+	FLUSH_TIMESTAMP r0
+
+	tst	REG_P_REST, #1<<16
+	blne	do_irq_hook_noflushts
+
 	ldr     r0, =nes_registers
 	stmia	r0, {r4-r12}
 
@@ -2918,6 +2808,15 @@ nes_stack:
 @ TODO: write code which keeps it up-to-date
 pc_base:
 	.long	0
+MapIRQHook:
+	.long	0
+timestamp:
+timestamp_a:
+	.long	0
+#ifndef DEBUG_ASM_6502
+X:
+#endif
+X_:	.fill   0x20, 1, 0
 
 .pool
 
@@ -2982,16 +2881,12 @@ opAB:	@ LXA #$nn
 @op37:	@ RLA $nn, X
 @op2F:	@ RLA $nnnn
 @op3F:	@ RLA $nnnn, X
-@op3B:	@ RLA $nnnn, Y
 @op23:	@ RLA ($nn, X)
-@op33:	@ RLA ($nn), Y
 @op67:	@ RRA $nn
 @op77:	@ RRA $nn, X
 @op6F:	@ RRA $nnnn
 @op7F:	@ RRA $nnnn, X
-@op7B:	@ RRA $nnnn, Y
 @op63:	@ RRA ($nn, X)
-@op73:	@ RRA ($nn), Y
 op87:	@ SAX $nn
 op97:	@ SAX $nn, Y
 op8F:	@ SAX $nnnn
@@ -3001,21 +2896,17 @@ op9F:	@ SHA $nnnn, Y
 op93:	@ SHA ($nn), Y
 op9B:	@ SHS $nnnn, Y
 op9E:	@ SHX $nnnn, Y
-@op9C:	@ SHY $nnnn, X
 @op03:   @ SLO ($nn, X)
 @op07:	@ SLO $nn
 @op17:	@ SLO $nn, X
 @op0F:	@ SLO $nnnn
 @op1F:	@ SLO $nnnn, X
-@op1B:	@ SLO $nnnn, Y
-@op13:	@ SLO ($nn), Y
 @op47:	@ SRE $nn
 @op57:	@ SRE $nn, X
 @op4F:	@ SRE $nnnn
 @op5F:	@ SRE $nnnn, X
 @op5B:	@ SRE $nnnn, Y
 @op43:	@ SRE ($nn, X)
-@op53:	@ SRE ($nn), Y
 	CYCLE_NEXT   1
 @ emu_panic?
 
@@ -3029,20 +2920,22 @@ op9E:	@ SHX $nnnn, Y
 .extern Page
 .extern ARead
 .extern BWrite
+.extern MapIRQHook
 
 
 	SECTION_DATA
 	ALIGN
-@	.globl	X
-	.globl	RAM
 	.globl	nes_registers @ TODO: hide?
 	.globl	pc_base
-@	.globl	timestamp
-@	.globl	MapIRQHook @ (int a)
-@ TODO... .. conversion X <-> nes_registers for savestates
-@timestamp:	.long	0
-@MapIRQHook:	.long   0
-@X:		.fill   0x20, 1, 0
+	.globl	MapIRQHook @ (int a)
+#ifndef DEBUG_ASM_6502
+	.globl	X
+	.globl	RAM
+	.globl	timestamp
+#else
+	.globl	nes_internal_ram
+	.globl	timestamp_a
+#endif
 	.globl	X6502_Reset_a @ (void);
 	.globl	X6502_Power_a @ (void);
 	.globl	X6502_Run_a @ (int32 cycles);
@@ -3052,7 +2945,7 @@ op9E:	@ SHX $nnnn, Y
 	.globl	X6502_AddCycles_a @ (int x);
 	.globl	X6502_IRQBegin_a @ (int w);
 	.globl	X6502_IRQEnd_a @ (int w);
-	.globl	X6502_rebase_a @ (void);
+	.globl	X6502_Rebase_a @ (void);
 
 	SECTION_TEXT
 	ALIGN
@@ -3099,7 +2992,7 @@ X6502_IRQEnd_a:
 
 
 TriggerNMI_a:
-	mov     r0, #FCEU_IQTEMP
+	mov     r0, #FCEU_IQNMI
 	b	X6502_IRQBegin_a
 
 
@@ -3109,16 +3002,20 @@ TriggerNMINSF_a:
 
 
 X6502_AddCycles_a:
+	ldr	r3, =timestamp
 	ldr	r2, =nes_registers
-	ldr	r1, [r2, #0x1c]
-	mvn	r3, #49
+	ldr	r1, [r3]
+	add	r1, r1, r0
+	str	r1, [r3]
+	ldrsh	r1, [r2, #0x1e]
+	mvn	r3, #47			@ r3=-48
 	mla	r0, r3, r0, r1
-	str	r0, [r2, #0x1c]
+	strh	r0, [r2, #0x1e]
 	bx	lr
 
 
 @ rebase PC when not executing or in memhandlers
-X6502_rebase_a:
+X6502_Rebase_a:
 	stmfd	sp!,{REG_PC,REG_OP_TABLE}
 	ldr	REG_OP_TABLE, =cpu_exec_table
 	ldr	r0, [REG_OP_TABLE, #(OTOFFS_NES_REGS+0x0c)] @ PC
@@ -3131,5 +3028,31 @@ X6502_rebase_a:
 .pool
 
 
+@ the nasty MapIRQHook thing from FCE..
+@ test Gradius 2 (J) if you change this
+do_irq_hook:
+	FLUSH_TIMESTAMP r0
+
+do_irq_hook_noflushts:
+#ifndef DEBUG_ASM_6502
+	@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
+	str     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
+	mov	REG_P_REST, lr			@ r8
+
+	@ if somebody modifies MapIRQHook without calling reset, we are doomed
+	mov	lr, pc
+	ldr	pc, [REG_OP_TABLE, #OTOFFS_IRQ_HOOK]
+
+	ldr	REG_OP_TABLE, =cpu_exec_table	@ got trashed because was in r12
+	mov	lr, REG_P_REST
+	ldr     REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)]	@ might set irq
+#else
+	ldr	r1, =mapirq_cyc_a
+	str	r0, [r1]
+	mov	r1, r0
+#endif
+	bx	lr
+
+
 @ vim:filetype=armasm