- if(scanline>=FSettings.FirstSLine && scanline<=Settings.LastSLine)
+ if(scanline>=FSettings.FirstSLine && scanline<=FSettings.LastSLine)
FSettings.FirstSLine=FSettings.UsrFirstSLine[0];
FSettings.LastSLine=FSettings.UsrLastSLine[0];
}
FSettings.FirstSLine=FSettings.UsrFirstSLine[0];
FSettings.LastSLine=FSettings.UsrLastSLine[0];
}
- printf("PAL = %i\n", PAL);
+ printf("ResetVidSys: PAL = %i\n", PAL);
.byte 0x0a,0
.align 4
stmfd sp!,{r0-r3,r12,lr}
.byte 0x0a,0
.align 4
stmfd sp!,{r0-r3,r12,lr}
@ updates fceu "timestamp" variable
@ updates fceu "timestamp" variable
-@ loads cycles to reg, reg!=r1, trashes r1
+@ loads cycles to reg, reg!=r1, trashes r1, kills flags
.macro FLUSH_TIMESTAMP reg
.macro FLUSH_TIMESTAMP reg
+ ands \reg, REG_CYCLE, #0xff
+ beq 1f
ldr r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
ldr r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
- and \reg, REG_CYCLE, #0xff
+ orr REG_CYCLE, REG_CYCLE, \reg, lsl #8 @ put cycles for do_irq_hook
add r1, r1, \reg
bic REG_CYCLE, REG_CYCLE, #0xff
str r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
add r1, r1, \reg
bic REG_CYCLE, REG_CYCLE, #0xff
str r1, [REG_OP_TABLE, #OTOFFS_TIMESTAMP]
@@@
@@@ ¤Ê¤ó¤«Ì¾Á°¤¬ÊѤÀ¤Ê(¤É¡¼¤Ç¤â¤¤¡¼¤±¤É¡¼
@@@
@@@
@@@ ¤Ê¤ó¤«Ì¾Á°¤¬ÊѤÀ¤Ê(¤É¡¼¤Ç¤â¤¤¡¼¤±¤É¡¼
@@@
-.macro CYCLE_NEXT n, hook_check=1
+.macro CYCLE_NEXT n, hook_check=1, do_cyc_add=1
add REG_CYCLE, REG_CYCLE, #\n
add REG_CYCLE, REG_CYCLE, #\n
subs REG_CYCLE, REG_CYCLE, #\n*48<<16
ble cpu_exec_end
.if \hook_check
subs REG_CYCLE, REG_CYCLE, #\n*48<<16
ble cpu_exec_end
.if \hook_check
+@ fceu needs timestamp cycles to be inremented before doing actual opcode.
+@ this is only needed for ops which do memory i/o
+.macro CYCLE_PRE n
+ add REG_CYCLE, REG_CYCLE, #\n
+.endm
+
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+.macro READ rom_optimize=1
tst REG_ADDR, #0x8000
bne read_rom_byte
tst REG_ADDR, #0x8000
bne read_rom_byte
tst REG_ADDR, #0xe000
bne read_byte
@ RAM
tst REG_ADDR, #0xe000
bne read_byte
@ RAM
@@@ REG_ADDR¤òÊѹ¹¤¹¤ë¤¬µ¤¤Ë¤¹¤ë¤Ê
@@@
.macro READ_WORD
@@@ REG_ADDR¤òÊѹ¹¤¹¤ë¤¬µ¤¤Ë¤¹¤ë¤Ê
@@@
.macro READ_WORD
+ @ don't do ROM check, because we might be fetching important stuff like vectors
+ READ 0
mov REG_PC, r0
add REG_ADDR, REG_ADDR, #1
mov REG_PC, r0
add REG_ADDR, REG_ADDR, #1
orr r0, REG_PC, r0, lsl #8
.endm
orr r0, REG_PC, r0, lsl #8
.endm
CYCLE_NEXT 4
opAD: @ LDA $nnnn
CYCLE_NEXT 4
opAD: @ LDA $nnnn
opA2: @ LDX #$nn
IMM_VALUE
opA2: @ LDX #$nn
IMM_VALUE
CYCLE_NEXT 4
opAE: @ LDX $nnnn
CYCLE_NEXT 4
opAE: @ LDX $nnnn
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 4
op8D: @ STA $nnnn
CYCLE_NEXT 4
op8D: @ STA $nnnn
ABSX_ADDR_W
OP_STA
WRITE_1
ABSX_ADDR_W
OP_STA
WRITE_1
ABSY_ADDR_W
OP_STA
WRITE_1
ABSY_ADDR_W
OP_STA
WRITE_1
INDY_ADDR_W
OP_STA
WRITE_1
INDY_ADDR_W
OP_STA
WRITE_1
CYCLE_NEXT 4
op8E: @ STX $nnnn
CYCLE_NEXT 4
op8E: @ STX $nnnn
ABS_ADDR
mov r0, REG_X
WRITE_1
ABS_ADDR
mov r0, REG_X
WRITE_1
CYCLE_NEXT 4
op8C: @ STY $nnnn
CYCLE_NEXT 4
op8C: @ STY $nnnn
ABS_ADDR
mov r0, REG_Y
WRITE_1
ABS_ADDR
mov r0, REG_Y
WRITE_1
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
opEE: @ INC $nnnn
CYCLE_NEXT 6
opEE: @ INC $nnnn
ABS_ADDR
READ_WRITE_1
OP_INC
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_INC
READ_WRITE_2
READ_WRITE_3
OP_INC
READ_WRITE_4
READ_WRITE_3
OP_INC
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_INC
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_INC
READ_WRITE_2
READ_WRITE_3
OP_INC
READ_WRITE_4
READ_WRITE_3
OP_INC
READ_WRITE_4
CYCLE_NEXT 6
opCE: @ DEC $nnnn
CYCLE_NEXT 6
opCE: @ DEC $nnnn
ABS_ADDR
READ_WRITE_1
OP_DEC
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_DEC
READ_WRITE_2
READ_WRITE_3
OP_DEC
READ_WRITE_4
READ_WRITE_3
OP_DEC
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_DEC
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_DEC
READ_WRITE_2
READ_WRITE_3
OP_DEC
READ_WRITE_4
READ_WRITE_3
OP_DEC
READ_WRITE_4
CYCLE_NEXT 4
op6D: @ ADC $nnnn
CYCLE_NEXT 4
op6D: @ ADC $nnnn
opEB: @ USBC #$nn
opE9: @ SBC #$nn
opEB: @ USBC #$nn
opE9: @ SBC #$nn
CYCLE_NEXT 4
opED: @ SBC $nnnn
CYCLE_NEXT 4
opED: @ SBC $nnnn
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 4
op2D: @ AND $nnnn
CYCLE_NEXT 4
op2D: @ AND $nnnn
CYCLE_NEXT 4
op4D: @ EOR $nnnn
CYCLE_NEXT 4
op4D: @ EOR $nnnn
CYCLE_NEXT 4
op0D: @ ORA $nnnn
CYCLE_NEXT 4
op0D: @ ORA $nnnn
CYCLE_NEXT 4
opCD: @ CMP $nnnn
CYCLE_NEXT 4
opCD: @ CMP $nnnn
CYCLE_NEXT 3
opEC: @ CPX $nnnn
CYCLE_NEXT 3
opEC: @ CPX $nnnn
CYCLE_NEXT 3
opCC: @ CPY $nnnn
CYCLE_NEXT 3
opCC: @ CPY $nnnn
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 3
op2C: @ BIT $nnnn
CYCLE_NEXT 3
op2C: @ BIT $nnnn
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op0E: @ ASL $nnnn
CYCLE_NEXT 6
op0E: @ ASL $nnnn
ABS_ADDR
READ_WRITE_1
OP_ASL
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_ASL
READ_WRITE_2
READ_WRITE_3
OP_ASL
READ_WRITE_4
READ_WRITE_3
OP_ASL
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_ASL
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_ASL
READ_WRITE_2
READ_WRITE_3
OP_ASL
READ_WRITE_4
READ_WRITE_3
OP_ASL
READ_WRITE_4
CYCLE_NEXT 6
op4E: @ LSR $nnnn
CYCLE_NEXT 6
op4E: @ LSR $nnnn
ABS_ADDR
READ_WRITE_1
OP_LSR
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_LSR
READ_WRITE_2
READ_WRITE_3
OP_LSR
READ_WRITE_4
READ_WRITE_3
OP_LSR
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_LSR
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_LSR
READ_WRITE_2
READ_WRITE_3
OP_LSR
READ_WRITE_4
READ_WRITE_3
OP_LSR
READ_WRITE_4
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op2E: @ ROL $nnnn
CYCLE_NEXT 6
op2E: @ ROL $nnnn
ABS_ADDR
READ_WRITE_1
OP_ROL
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_ROL
READ_WRITE_2
READ_WRITE_3
OP_ROL
READ_WRITE_4
READ_WRITE_3
OP_ROL
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_ROL
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_ROL
READ_WRITE_2
READ_WRITE_3
OP_ROL
READ_WRITE_4
READ_WRITE_3
OP_ROL
READ_WRITE_4
CYCLE_NEXT 6
op6E: @ ROR $nnnn
CYCLE_NEXT 6
op6E: @ ROR $nnnn
ABS_ADDR
READ_WRITE_1
OP_ROR
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_ROR
READ_WRITE_2
READ_WRITE_3
OP_ROR
READ_WRITE_4
READ_WRITE_3
OP_ROR
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_ROR
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_ROR
READ_WRITE_2
READ_WRITE_3
OP_ROR
READ_WRITE_4
READ_WRITE_3
OP_ROR
READ_WRITE_4
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
CYCLE_NEXT 6
op4F: @ SRE $nnnn
CYCLE_NEXT 6
op4F: @ SRE $nnnn
ABS_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
READ_WRITE_3
OP_SRE
READ_WRITE_4
READ_WRITE_3
OP_SRE
READ_WRITE_4
ABSX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
ABSX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
READ_WRITE_3
OP_SRE
READ_WRITE_4
READ_WRITE_3
OP_SRE
READ_WRITE_4
ABSY_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
ABSY_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
READ_WRITE_3
OP_SRE
READ_WRITE_4
READ_WRITE_3
OP_SRE
READ_WRITE_4
INDX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
INDX_ADDR
READ_WRITE_1
OP_SRE
READ_WRITE_2
READ_WRITE_3
OP_SRE
READ_WRITE_4
READ_WRITE_3
OP_SRE
READ_WRITE_4
INDY_ADDR_W
READ_WRITE_1
OP_SRE
READ_WRITE_2
INDY_ADDR_W
READ_WRITE_1
OP_SRE
READ_WRITE_2
READ_WRITE_3
OP_SRE
READ_WRITE_4
READ_WRITE_3
OP_SRE
READ_WRITE_4
ABSX_ADDR_W
OP_SHY
WRITE_1
ABSX_ADDR_W
OP_SHY
WRITE_1
opE7: @ ISB $nn
ZERO_ADDR
opE7: @ ISB $nn
ZERO_ADDR
CYCLE_NEXT 6
opEF: @ ISB $nnnn
CYCLE_NEXT 6
opEF: @ ISB $nnnn
ABS_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
ABS_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
ABSX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
ABSX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
ABSY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
ABSY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
INDX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
INDX_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
INDY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
INDY_ADDR
READ_WRITE_1
OP_ISB
READ_WRITE_2
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
READ_WRITE_3
OP_ISB
READ_WRITE_4
OP_SBC
opA7: @ LAX $nn
ZERO_ADDR
opA7: @ LAX $nn
ZERO_ADDR
CYCLE_NEXT 4
opAF: @ LAX $nnnn
CYCLE_NEXT 4
opAF: @ LAX $nnnn
ZERO_ADDR
ZP_READ_W
OP_SLO
ZP_WRITE_W
ZERO_ADDR
ZP_READ_W
OP_SLO
ZP_WRITE_W
op17: @ SLO $nn, X
ZEROX_ADDR
op17: @ SLO $nn, X
ZEROX_ADDR
CYCLE_NEXT 6
op0F: @ SLO $nnnn
CYCLE_NEXT 6
op0F: @ SLO $nnnn
ABS_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
READ_WRITE_3
OP_SLO
READ_WRITE_4
READ_WRITE_3
OP_SLO
READ_WRITE_4
ABSX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
ABSX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
READ_WRITE_3
OP_SLO
READ_WRITE_4
READ_WRITE_3
OP_SLO
READ_WRITE_4
ABSY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
ABSY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
READ_WRITE_3
OP_SLO
READ_WRITE_4
READ_WRITE_3
OP_SLO
READ_WRITE_4
INDX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
INDX_ADDR
READ_WRITE_1
OP_SLO
READ_WRITE_2
READ_WRITE_3
OP_SLO
READ_WRITE_4
READ_WRITE_3
OP_SLO
READ_WRITE_4
INDY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
INDY_ADDR_W
READ_WRITE_1
OP_SLO
READ_WRITE_2
READ_WRITE_3
OP_SLO
READ_WRITE_4
READ_WRITE_3
OP_SLO
READ_WRITE_4
opCB: @ SBX #$nn
IMM_VALUE
opCB: @ SBX #$nn
IMM_VALUE
CYCLE_NEXT 6
opCF: @ DCP $nnnn
CYCLE_NEXT 6
opCF: @ DCP $nnnn
ABS_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
ABS_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
ABSX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
ABSX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
ABSY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
ABSY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
INDX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
INDX_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
INDY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
INDY_ADDR
READ_WRITE_1
OP_DCP
READ_WRITE_2
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
READ_WRITE_3
OP_DCP
READ_WRITE_4
OP_CMP
op27: @ RLA $nn
ZERO_ADDR
op27: @ RLA $nn
ZERO_ADDR
CYCLE_NEXT 6
op2F: @ RLA $nnnn
CYCLE_NEXT 6
op2F: @ RLA $nnnn
ABS_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
ABS_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
READ_WRITE_3
OP_RLA
READ_WRITE_4
READ_WRITE_3
OP_RLA
READ_WRITE_4
ABSX_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
ABSX_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
READ_WRITE_3
OP_RLA
READ_WRITE_4
READ_WRITE_3
OP_RLA
READ_WRITE_4
ABSY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
ABSY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
READ_WRITE_3
OP_RLA
READ_WRITE_4
READ_WRITE_3
OP_RLA
READ_WRITE_4
INDX_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
INDX_ADDR
READ_WRITE_1
OP_RLA
READ_WRITE_2
READ_WRITE_3
OP_RLA
READ_WRITE_4
READ_WRITE_3
OP_RLA
READ_WRITE_4
INDY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
INDY_ADDR_W
READ_WRITE_1
OP_RLA
READ_WRITE_2
READ_WRITE_3
OP_RLA
READ_WRITE_4
READ_WRITE_3
OP_RLA
READ_WRITE_4
op67: @ RRA $nn
ZERO_ADDR
op67: @ RRA $nn
ZERO_ADDR
CYCLE_NEXT 6
op6F: @ RRA $nnnn
CYCLE_NEXT 6
op6F: @ RRA $nnnn
ABS_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
ABS_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
ABSX_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
ABSX_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
ABSY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
ABSY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
INDX_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
INDX_ADDR
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
INDY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
INDY_ADDR_W
READ_WRITE_1
OP_RRA
READ_WRITE_2
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
READ_WRITE_3
OP_RRA
READ_WRITE_4
OP_ADC
@@@ ----
@ JMP ($nnnn)
op6C:
@@@ ----
@ JMP ($nnnn)
op6C:
ABS_ADDR
and r0, REG_ADDR, #0xFF
teq r0, #0xFF
beq jmp_indirect_bug
READ_WORD
REBASE_PC
ABS_ADDR
and r0, REG_ADDR, #0xFF
teq r0, #0xFF
beq jmp_indirect_bug
READ_WORD
REBASE_PC
jmp_indirect_bug:
@@
@@ BUG is : to not read word at REG_ADDR, because it loops
@@ but read low part at REG_ADDR and high part at REG_ADDR&0xFF00 instead of REG_ADDR+1
@@
jmp_indirect_bug:
@@
@@ BUG is : to not read word at REG_ADDR, because it loops
@@ but read low part at REG_ADDR and high part at REG_ADDR&0xFF00 instead of REG_ADDR+1
@@
mov REG_PC, r0
and REG_ADDR, REG_ADDR, #0xff00
mov REG_PC, r0
and REG_ADDR, REG_ADDR, #0xff00
orr r0, REG_PC, r0, lsl #8
REBASE_PC
orr r0, REG_PC, r0, lsl #8
REBASE_PC
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@@@ WARNING: decrements REG_PC
@@@
do_int:
@@@ WARNING: decrements REG_PC
@@@
do_int:
+ add REG_CYCLE, REG_CYCLE, #7
ldr r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
sub REG_PC, REG_PC, #1
sub r0, REG_PC, r0
ldr r0, [REG_OP_TABLE, #OTOFFS_PC_BASE]
sub REG_PC, REG_PC, #1
sub r0, REG_PC, r0
- add REG_CYCLE, REG_CYCLE, #7
subs REG_CYCLE, REG_CYCLE, #7*48<<16
ble cpu_exec_end
ldrb r0, [REG_PC], #1
subs REG_CYCLE, REG_CYCLE, #7*48<<16
ble cpu_exec_end
ldrb r0, [REG_PC], #1
+@ try to avoid lookup of every address at least for ROM and RAM areas
+@ I've verified that if ARead[0xfff0] points to CartBR, it is always normal ROM read.
#ifndef DEBUG_ASM_6502
ldr r0, =CartBR
ldr r2, =ARead
#ifndef DEBUG_ASM_6502
ldr r0, =CartBR
ldr r2, =ARead
read_byte:
@ must preserve r3 for the callers too
@ TODO: check if all of saves are needed, _DB (is full needed?)
read_byte:
@ must preserve r3 for the callers too
@ TODO: check if all of saves are needed, _DB (is full needed?)
+ FLUSH_TIMESTAMP r2 @ needed for TryFixit1
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
str REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
str REG_PC, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x0c)] @ might get rebased
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
str REG_CYCLE, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x1c)] @ might get used
str r1, [r3]
ldrsh r1, [r2, #0x1e]
mvn r3, #47 @ r3=-48
str r1, [r3]
ldrsh r1, [r2, #0x1e]
mvn r3, #47 @ r3=-48
- mla r0, r3, r0, r1
- strh r0, [r2, #0x1e]
- bx lr
+ mla r3, r0, r3, r1
+ ldr r1, =MapIRQHook @ hack..
+ strh r3, [r2, #0x1e]
+ ldr r1, [r1]
+ tst r1, r1
+ bxeq lr
+ bx r1
@ rebase PC when not executing or in memhandlers
@ rebase PC when not executing or in memhandlers
FLUSH_TIMESTAMP r0
do_irq_hook_noflushts:
FLUSH_TIMESTAMP r0
do_irq_hook_noflushts:
+ @ get irqhook cycles
+ and r0, REG_CYCLE, #0xff00
+ bic REG_CYCLE, REG_CYCLE, #0xff00
+ mov r0, r0, lsr #8
#ifndef DEBUG_ASM_6502
@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
#ifndef DEBUG_ASM_6502
@ I have reviewed all MapIRQHook functions, they only seem to cause IRQs, not messing cycles or something
str REG_P_REST, [REG_OP_TABLE, #(OTOFFS_NES_REGS + 0x10)] @ might set irq
#define REG_P_REST r8
#define REG_NZ r9 // 14
#define REG_ADDR r10 // 18
#define REG_P_REST r8
#define REG_NZ r9 // 14
#define REG_ADDR r10 // 18
-#define REG_CYCLE r11 // 1c
+#define REG_CYCLE r11 // 1c [31:16] - fceu cycles, [15:8] - fceu irqhook cycles, [7:0] - fceu timestamp cycles
#define REG_OP_TABLE r12 // 20
#define REG_OP_TABLE r12 // 20
extern uint32 pc_base;
extern uint8 nes_internal_ram[0x800];
extern uint32 timestamp_a;
extern uint32 pc_base;
extern uint8 nes_internal_ram[0x800];
extern uint32 timestamp_a;
+extern uint32 framecount;
+static uint32 framecount_d;
uint32 PC_prev = 0xcccccc, OP_prev = 0xcccccc;
int32 g_cnt = 0;
uint32 PC_prev = 0xcccccc, OP_prev = 0xcccccc;
int32 g_cnt = 0;
static void leave(void)
{
printf("\nA: %02x, X: %02x, Y: %02x, S: %02x\n", X.A, X.X, X.Y, X.S);
static void leave(void)
{
printf("\nA: %02x, X: %02x, Y: %02x, S: %02x\n", X.A, X.X, X.Y, X.S);
- printf("PC = %04lx, OP=%02lX\n", PC_prev, OP_prev);
- printf("rest = %08lx\n", nes_registers[4]);
+ printf("PC = %04x, OP=%02X\n", PC_prev, OP_prev);
+ printf("rest = %08x\n", nes_registers[4]);
int i, fail = 0;
if ((nes_registers[0] >> 24) != X.A) {
int i, fail = 0;
if ((nes_registers[0] >> 24) != X.A) {
- printf("A: %02lx vs %02x\n", nes_registers[0] >> 24, X.A);
+ printf("A: %02x vs %02x\n", nes_registers[0] >> 24, X.A);
fail = 1;
}
if ((nes_registers[1] & 0xff) != X.X) {
fail = 1;
}
if ((nes_registers[1] & 0xff) != X.X) {
- printf("X: %02lx vs %02x\n", nes_registers[1] & 0xff, X.X);
+ printf("X: %02x vs %02x\n", nes_registers[1] & 0xff, X.X);
fail = 1;
}
if ((nes_registers[2] & 0xff) != X.Y) {
fail = 1;
}
if ((nes_registers[2] & 0xff) != X.Y) {
- printf("Y: %02lx vs %02x\n", nes_registers[2] & 0xff, X.Y);
+ printf("Y: %02x vs %02x\n", nes_registers[2] & 0xff, X.Y);
fail = 1;
}
if (nes_registers[3] - pc_base != X.PC) {
fail = 1;
}
if (nes_registers[3] - pc_base != X.PC) {
- printf("PC: %04lx vs %04x\n", nes_registers[3] - pc_base, X.PC);
+ printf("PC: %04x vs %04x\n", nes_registers[3] - pc_base, X.PC);
fail = 1;
}
if ((nes_registers[4] >> 24) != X.S) {
fail = 1;
}
if ((nes_registers[4] >> 24) != X.S) {
- printf("S: %02lx vs %02x\n", nes_registers[4] >> 24, X.S);
+ printf("S: %02x vs %02x\n", nes_registers[4] >> 24, X.S);
fail = 1;
}
if (((nes_registers[4]>>8)&0xff) != X.IRQlow) {
fail = 1;
}
if (((nes_registers[4]>>8)&0xff) != X.IRQlow) {
- printf("IRQlow: %02lx vs %02x\n", ((nes_registers[4]>>8)&0xff), X.IRQlow);
+ printf("IRQlow: %02x vs %02x\n", ((nes_registers[4]>>8)&0xff), X.IRQlow);
}
if (((int32)nes_registers[7] >> 16) != X.count) {
}
if (((int32)nes_registers[7] >> 16) != X.count) {
- printf("cycles: %li vs %li\n", (int32)nes_registers[7] >> 16, X.count);
+ printf("cycles: %i vs %i\n", (int32)nes_registers[7] >> 16, X.count);
for (i = dwrite_count_a - 1; !fail && i >= 0; i--)
if (dwrites_a[i] != dwrites_c[i]) {
for (i = dwrite_count_a - 1; !fail && i >= 0; i--)
if (dwrites_a[i] != dwrites_c[i]) {
- printf("dwrites[%i]: %06lx vs %06lx\n", dwrite_count_a, dwrites_a[i], dwrites_c[i]);
+ printf("dwrites[%i]: %06x vs %06x\n", dwrite_count_a, dwrites_a[i], dwrites_c[i]);
}
if (timestamp_a != timestamp) {
}
if (timestamp_a != timestamp) {
- printf("timestamp: %lu vs %lu\n", timestamp_a, timestamp);
+ printf("timestamp: %u vs %u\n", timestamp_a, timestamp);
//printf("-- %06i: run(%i)\n", (int)g_cnt, (int)c);
g_cnt += cycles;
//printf("-- %06i: run(%i)\n", (int)g_cnt, (int)c);
g_cnt += cycles;
+ if (framecount != framecount_d) {
+ framecount_d = framecount;
+ }
+
+ timestamp_a = timestamp;
dread_count_c = dread_count_a = dwrite_count_c = dwrite_count_a = 0;
mapirq_cyc_a = mapirq_cyc_c = 0;
dread_count_c = dread_count_a = dwrite_count_c = dwrite_count_a = 0;
mapirq_cyc_a = mapirq_cyc_c = 0;
- timestamp_a = timestamp;
+ //timestamp_a = timestamp;
g_cnt -= 1 - X.count;
if (pending_add_cycles) {
g_cnt -= pending_add_cycles*48;
g_cnt -= 1 - X.count;
if (pending_add_cycles) {
g_cnt -= pending_add_cycles*48;
+ //X6502_AddCycles_c(pending_add_cycles);
+ //X6502_AddCycles_a(pending_add_cycles);
+ timestamp += pending_add_cycles;
+ timestamp_a += pending_add_cycles;
pending_add_cycles = 0;
}
if (pending_rebase) {
pending_add_cycles = 0;
}
if (pending_rebase) {
static INLINE uint8 RdMem(unsigned int A)
{
static INLINE uint8 RdMem(unsigned int A)
{
- // notaz: try to avoid lookup of every address at least for ROM and RAM areas
- // I've verified that if ARead[0xfff0] points to CartBR, it is always normal ROM read.
-#if 0
- if ((A&0x8000)/* && ARead[0xfff0] == CartBR*/) {
- return (_DB=Page[A>>11][A]);
- }
-#endif
-#if 0 // enabling this causes 4fps slowdown. Why?
- if ((A&0xe000) == 0) { // RAM area (always 0-0x1fff)
- return (_DB=RAM[A&0x7FF]);
- }
-#endif
- _DB=ARead[A](A);
+ int _DB1=ARead[A](A);
+ /*if (A >= 0x2000)*/ _DB=_DB1;
#ifdef DEBUG_ASM_6502
//printf("a == %x, pc == %x\n", A, _PC);
if (A >= 0x2000 && A != _PC && A != _PC - 1 && A != _PC + 1) {
#ifdef DEBUG_ASM_6502
//printf("a == %x, pc == %x\n", A, _PC);
if (A >= 0x2000 && A != _PC && A != _PC - 1 && A != _PC + 1) {
- dreads[dread_count_c++] = _DB;
+ dreads[dread_count_c++] = _DB1;
if (dread_count_c > 4) { printf("dread_count out of range\n"); exit(1); }
}
#endif
if (dread_count_c > 4) { printf("dread_count out of range\n"); exit(1); }
}
#endif
}
static INLINE void WrMem(unsigned int A, uint8 V)
}
static INLINE void WrMem(unsigned int A, uint8 V)
static INLINE uint8 RdRAM(unsigned int A)
{
static INLINE uint8 RdRAM(unsigned int A)
{
+ //return((_DB=RAM[A]));
#define X6502_IRQBegin X6502_IRQBegin_d
#define X6502_IRQEnd X6502_IRQEnd_d
#define X6502_Rebase X6502_Rebase_d
#define X6502_IRQBegin X6502_IRQBegin_d
#define X6502_IRQEnd X6502_IRQEnd_d
#define X6502_Rebase X6502_Rebase_d
-#define X6502_GetCycleCount() 0
+#define X6502_GetCycleCount() g_cnt
#define X6502_C
#define X6502_A
#define X6502_D
#define X6502_C
#define X6502_A
#define X6502_D
void TriggerIRQ_c(void);
void TriggerNMI_c(void);
void TriggerNMINSF_c(void);
void TriggerIRQ_c(void);
void TriggerNMI_c(void);
void TriggerNMINSF_c(void);