32x mostly works

but not reset, can it work at all with RV=1?

diff --git a/.gitignore b/.gitignore
index 5457b76..6934b51 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,5 @@
 *.o
 *.gen
+*.swp
+tags
+cscope.out

diff --git a/testpico/Makefile b/testpico/Makefile
index 20b6e64..67e4a84 100644 (file)
--- a/testpico/Makefile
+++ b/testpico/Makefile
@@ -17,7 +17,7 @@ CFLAGS += -Wall -g -O2 -m68000 -fomit-frame-pointer
 LDLIBS += $(shell $(CC) -print-file-name=libgcc.a)
 
 TARGET = testpico
-OBJS = sega_gcc.o main.o asmtools.o data.o
+OBJS = sega_gcc.o main.o asmtools.o
 
 all: $(TARGET).bin
 
@@ -60,7 +60,7 @@ $(TARGET_SH).elf: $(OBJS_SH)
        $(CC_SH) -o $@ -c $< $(CFLAGS_SH)
 
 # manual deps
-data.o: z80_test.bin80
+sega_gcc.o: z80_test.bin80
 sega_gcc.o: sh2_test.binsh
 
 up: $(TARGET).bin

diff --git a/testpico/asmtools.S b/testpico/asmtools.S
index fac52bb..d6b9091 100644 (file)
--- a/testpico/asmtools.S
+++ b/testpico/asmtools.S
@@ -221,13 +221,24 @@ test_vint_end:
 .global x32x_enable
 x32x_enable:
     movea.l     #0xa15100, a0
-    movea.l     #0xa15120, a1
+    movea.l     #0xa15122, a1
+    move.w      #1, (a0)          /* ADEN */
+# wait for min(20_sh2_cycles, pll_setup_time)
+# pll time is unclear, icd_mars.prg mentions 10ms which sounds
+# way too much. Hope 40 68k cycles is enough
+    move.w      #40/10, d0
+0:
+    dbra        d0, 0b
     move.w      #3, (a0)          /* ADEN, nRES */
 0:
-    nop
-    nop
+    move.w      #0xffff, d0       /* waste some cycles */
     tst.w       (a1)
-    beq         0b                /* BIOS busy */
+    beq         0b                /* master BIOS busy */
+
+0:                                /* for slave, use a limit, as it */
+    tst.w       4(a1)             /* won't respond on master error. */
+    dbne        d0, 0b            /* slave BIOS busy */
+
     or.w        #1, 6(a0)         /* RV */
     rts
 .global x32x_enable_end

diff --git a/testpico/common.h b/testpico/common.h
index e167c7a..944e7e4 100644 (file)
--- a/testpico/common.h
+++ b/testpico/common.h
@@ -28,6 +28,7 @@
 
 enum x32x_cmd {
     CMD_ECHO = 1,
+    CMD_READ_FRT = 2, // read Free-Running Timer
 };
 
 // vim:ts=4:sw=4:expandtab

diff --git a/testpico/data.s b/testpico/data.s
deleted file mode 100644 (file)
index 9eceaff..0000000
--- a/testpico/data.s
+++ /dev/null
@@ -1,14 +0,0 @@
-.section .rodata
-.align 2
-
-.global font_base
-font_base:
-.incbin "font.bin"
-
-.global z80_test
-.global z80_test_end
-z80_test:
-.incbin "z80_test.bin80"
-z80_test_end:
-
-# vim:filetype=asmM68k:ts=4:sw=4:expandtab

diff --git a/testpico/main.c b/testpico/main.c
index 29fee32..c51181f 100644 (file)
--- a/testpico/main.c
+++ b/testpico/main.c
@@ -1510,8 +1510,15 @@ static int t_32x_init(void)
     u32 S_OK = MKLONG('S','_','O','K');
     u32 *r = (u32 *)0xa15100;
     u16 *r16 = (u16 *)r;
-    int ok = 1;
+    int i, ok = 1;
 
+    //v1070 = read32(0x1070);
+
+    /* what does REN mean exactly?
+     * Seems to be sometimes clear after reset */
+    for (i = 0; i < 1000000; i++)
+        if (read16(r16) & 0x80)
+            break;
     expect(ok, r16[0x00/2], 0x82);
     expect(ok, r16[0x02/2], 0);
     expect(ok, r16[0x04/2], 0);
@@ -1521,6 +1528,8 @@ static int t_32x_init(void)
     expect(ok, r[0x1c/4], 0);
     write32(&r[0x20/4], 0); // master resp
     write32(&r[0x24/4], 0); // slave resp
+    write32(&r[0x28/4], 0);
+    write32(&r[0x2c/4], 0);
 
     // could just set RV, but BIOS reads ROM, so can't
     memcpy_(do_32x_enable, x32x_enable,
@@ -1545,12 +1554,15 @@ static void x32_cmd(enum x32x_cmd cmd, u16 is_slave)
 {
     u16 v, *r = (u16 *)0xa15120;
     u16 cmd_s = cmd | (is_slave << 15);
+    int i;
     write16(r, cmd_s);
     mem_barrier();
-    while ((v = read16(r)) == cmd_s)
+    for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
         burn10(1);
-    if (v != 0)
+    if (v != 0) {
         printf("cmd clr: %x\n", v);
+        write16(r, 0);
+    }
 }
 
 static int t_32x_echo(void)
@@ -1562,9 +1574,11 @@ static int t_32x_echo(void)
     x32_cmd(CMD_ECHO, 0);
     expect(ok, r[0x04/2], 0x1234);
     write16(&r[0x02/2], 0x2345);
-    // mysteriously broken (random hangs)
-    //x32_cmd(CMD_ECHO, 1);
-    //expect(ok, r[0x04/2], 0x8345);
+    write16(&r[0x04/2], 0);
+    x32_cmd(CMD_ECHO, 1);
+    expect(ok, r[0x04/2], 0xa345);
+    expect(ok, r[0x0c/2], 0);
+    expect(ok, r[0x0e/2], 0);
     return ok;
 }
 
@@ -1576,12 +1590,14 @@ static int t_32x_md_rom(void)
     expect(ok, rl[0x004/4], 0x880200);
     expect(ok, rl[0x100/4], 0x53454741);
     expect(ok, rl[0x70/4], 0);
-    write32(&rl[0x70/4], ~0);
+    write32(&rl[0x70/4], 0xa5123456);
     write32(&rl[0x78/4], ~0);
     mem_barrier();
-    expect(ok, rl[0x70/4], ~0);
     expect(ok, rl[0x78/4], 0x8802ae);
-    // not tested: with RV 0x880000/0x900000 hangs
+    expect(ok, rl[0x70/4], 0xa5123456);
+    //expect(ok, rl[0x1070/4], v1070);
+    write32(&rl[0x70/4], 0);
+    // with RV 0x880000/0x900000 hangs, can't test
     return ok;
 }
 
@@ -1595,7 +1611,6 @@ static const struct {
     int (*test)(void);
     const char *name;
 } g_tests[] = {
-#if 0
     { T_MD, t_dma_zero_wrap,       "dma zero len + wrap" },
     { T_MD, t_dma_zero_fill,       "dma zero len + fill" },
     { T_MD, t_dma_ram_wrap,        "dma ram wrap" },
@@ -1636,7 +1651,6 @@ static const struct {
     { T_MD, t_irq_ack_h_v,         "irq ack h-v" },
     { T_MD, t_irq_ack_h_v_2,       "irq ack h-v 2" },
     { T_MD, t_irq_f_flag_h40,      "irq f flag h40" },
-#endif
     { T_MD, t_irq_f_flag_h32,      "irq f flag h32" },
 
     // the first one enables 32X, so should be kept

diff --git a/testpico/sega_gcc.s b/testpico/sega_gcc.s
index 10f5f62..efe0a00 100644 (file)
--- a/testpico/sega_gcc.s
+++ b/testpico/sega_gcc.s
@@ -1,5 +1,5 @@
 exc_tab:\r
-    dc.l     0, 0x200, exc02, exc03, exc04, exc05, exc06, exc07\r
+    dc.l     0,   RST, exc02, exc03, exc04, exc05, exc06, exc07\r
     dc.l exc08, exc09, exc0a, exc0b, exc0c, exc0d, exc0e, exc0f\r
     dc.l exc10, exc11, exc12, exc13, exc14, exc15, exc16, exc17\r
     dc.l exc18, exc19, exc1a, exc1b, 0xff0100, exc1d, 0xff0140, exc1f\r
@@ -23,84 +23,11 @@ exc_tab:
     .ascii "                        "\r
     .ascii "JUE             "                        /* 1f0 */\r
 \r
-RST:\r
-    move.w  #0x2700, %sr\r
-\r
-    move.b (0xA10001), %d0\r
-    andi.b #0x0F, %d0\r
-    beq.s 0f\r
-    move.l  #0x53454741, (0xA14000) /* 'SEGA' */\r
-0:\r
-       tst.w   (0xc00004).l\r
-\r
-    moveq   #0, %d0\r
-    movea.l %d0, %a7\r
-    move    %a7, %usp\r
-\r
-    /* clear .bss */\r
-    lea     __bss_start, %a0\r
-    lea     __end, %a1\r
-0:\r
-    move.l  %d0, (%a0)+\r
-    cmp.l   %a1, %a0\r
-    blt.s   0b\r
-\r
-#    move.w  #0x2000, %sr\r
-    jsr     main\r
-0:\r
-    bra     0b\r
-\r
-#HBL:\r
-#VBL:\r
-#    rte\r
-\r
-pre_exception:\r
-    move.w  #0x2700, %sr\r
-    movem.l %d0-%d7/%a0-%a7,-(%sp)\r
-    move.l %sp, %d0\r
-    move.l %d0,-(%sp)\r
-    jsr exception\r
-0:\r
-    bra 0b\r
-\r
-.macro exc_stub num\r
-exc\num:\r
-    move.w #0x\num, -(%sp)\r
-    jmp pre_exception\r
-.endm\r
-\r
-exc_stub 02\r
-exc_stub 03\r
-exc_stub 04\r
-exc_stub 05\r
-exc_stub 06\r
-exc_stub 07\r
-exc_stub 08\r
-exc_stub 09\r
-exc_stub 0a\r
-exc_stub 0b\r
-exc_stub 0c\r
-exc_stub 0d\r
-exc_stub 0e\r
-exc_stub 0f\r
-exc_stub 10\r
-exc_stub 11\r
-exc_stub 12\r
-exc_stub 13\r
-exc_stub 14\r
-exc_stub 15\r
-exc_stub 16\r
-exc_stub 17\r
-exc_stub 18\r
-exc_stub 19\r
-exc_stub 1a\r
-exc_stub 1b\r
-HBL:\r
-exc_stub 1c\r
-exc_stub 1d\r
-VBL:\r
-exc_stub 1e\r
-exc_stub 1f\r
+# mystery landing area for reset with 32X on and RV=1\r
+# 2c8 - 304 in multiples of 4\r
+.rept 0x1c0/2\r
+    illegal\r
+.endr\r
 \r
     /* MARS data */\r
     .org 0x3c0\r
@@ -109,10 +36,10 @@ exc_stub 1f
     .long sh2_test   /* ROM src */\r
     .long 0          /* SDRAM dst */\r
     .long sh2_test_end-sh2_test /* length */\r
-    .long 0x06000244 /* master entry */\r
-    .long 0x06000248 /* slave entry */\r
+    .long 0x06000400 /* master entry */\r
+    .long 0x06000404 /* slave entry */\r
     .long 0x06000000 /* master VBR */\r
-    .long 0x06000124 /* slave VBR */\r
+    .long 0x06000200 /* slave VBR */\r
     /* Standard 32X startup code for MD side at 0x3F0 */\r
     .org 0x3f0\r
     .word 0x287C,0xFFFF,0xFFC0,0x23FC,0x0000,0x0000,0x00A1,0x5128\r
@@ -181,6 +108,87 @@ exc_stub 1f
     .word 0xFFC0,0x4CD6,0x7FF9,0x44FC,0x0000,0x6014,0x43F9,0x00A1\r
     .word 0x5100,0x3340,0x0006,0x303C,0x8000,0x6004,0x44FC,0x0001\r
 \r
+RST:\r
+    move.w  #0x2600, %sr\r
+\r
+    move.b (0xA10001), %d0\r
+    andi.b #0x0F, %d0\r
+    beq.s 0f\r
+    move.l  #0x53454741, (0xA14000) /* 'SEGA' */\r
+0:\r
+    tst.w   (0xc00004).l\r
+\r
+    moveq   #0, %d0\r
+    movea.l %d0, %a7\r
+    move    %a7, %usp\r
+\r
+    /* clear .bss */\r
+    lea     __bss_start, %a0\r
+    lea     __end, %a1\r
+0:\r
+    move.l  %d0, (%a0)+\r
+    cmp.l   %a1, %a0\r
+    blt.s   0b\r
+\r
+#    move.w  #0x2000, %sr\r
+    jsr     main\r
+0:\r
+    bra     0b\r
+\r
+#HBL:\r
+#VBL:\r
+#    rte\r
+\r
+pre_exception:\r
+    move.w  #0x2700, %sr\r
+    movem.l %d0-%d7/%a0-%a7,-(%sp)\r
+    add.w   #2, 0x3e(%sp)\r
+    move.l  %sp, %d0\r
+    move.l  %d0,-(%sp)\r
+    jsr     exception\r
+0:\r
+    bra     0b\r
+\r
+.macro exc_stub num\r
+exc\num:\r
+    move.w #0x\num, -(%sp)\r
+    jmp pre_exception\r
+.endm\r
+\r
+exc_stub 02\r
+exc_stub 03\r
+exc_stub 04\r
+exc_stub 05\r
+exc_stub 06\r
+exc_stub 07\r
+exc_stub 08\r
+exc_stub 09\r
+exc_stub 0a\r
+exc_stub 0b\r
+exc_stub 0c\r
+exc_stub 0d\r
+exc_stub 0e\r
+exc_stub 0f\r
+\r
+exc_stub 10\r
+exc_stub 11\r
+exc_stub 12\r
+exc_stub 13\r
+exc_stub 14\r
+exc_stub 15\r
+exc_stub 16\r
+exc_stub 17\r
+exc_stub 18\r
+exc_stub 19\r
+exc_stub 1a\r
+exc_stub 1b\r
+HBL:\r
+exc_stub 1c\r
+exc_stub 1d\r
+VBL:\r
+exc_stub 1e\r
+exc_stub 1f\r
+\r
 exc_stub 20\r
 exc_stub 21\r
 exc_stub 22\r
@@ -214,8 +222,17 @@ exc_stub 3d
 exc_stub 3e\r
 exc_stub 3f\r
 \r
-.section .rodata\r
-.align 2\r
+.align 4\r
+\r
+# must avoid anything use 1070, 2070, 3070 after RV is set,\r
+# so let's place some data here\r
+.global z80_test\r
+.global z80_test_end\r
+z80_test:\r
+.incbin "z80_test.bin80"\r
+z80_test_end:\r
+\r
+.align 4\r
 \r
 .global sh2_test\r
 .global sh2_test_end\r
@@ -223,4 +240,14 @@ sh2_test:
 .incbin "sh2_test.binsh"\r
 sh2_test_end:\r
 \r
+.org 0x2070\r
+.long 0x1234567f\r
+\r
+.global font_base\r
+font_base:\r
+.incbin "font.bin"\r
+\r
+.org 0x3070\r
+.long 0x3456789f\r
+\r
 # vim:filetype=asmM68k:ts=4:sw=4:expandtab\r

diff --git a/testpico/sh2_main.c b/testpico/sh2_main.c
index eaa69a9..9c84b46 100644 (file)
--- a/testpico/sh2_main.c
+++ b/testpico/sh2_main.c
@@ -1,6 +1,7 @@
 #include "common.h"
 
 void spin(int loops);
+u16  read_frt(void);
 
 void main_c(u32 is_slave)
 {
@@ -8,11 +9,14 @@ void main_c(u32 is_slave)
 
     for (;;)
     {
-        u16 cmd;
+        u16 cmd, cmdr;
 
         mem_barrier();
         cmd = read16(&r[0x20/2]);
-        if ((cmd & 0x8000) ^ (is_slave << 15)) {
+        mem_barrier();
+        cmdr = read16(&r[0x20/2]);
+        if (cmd != cmdr  // documented as "normal" case
+            || ((cmd & 0x8000) ^ (is_slave << 15))) {
             spin(64);
             continue;
         }
@@ -21,13 +25,16 @@ void main_c(u32 is_slave)
         {
         case 0:
         case 0x4d5f:    // 'M_' from BIOS
-        case 0x535f:    // 'S_' from BIOS
             spin(64);
             continue;
         case CMD_ECHO:
             v = read16(&r[0x22/2]) ^ (is_slave << 15);
             write16(&r[0x24/2], v);
             break;
+        case CMD_READ_FRT:
+            v = read_frt();
+            write16(&r[0x24/2], v);
+            break;
         }
         write16(&r[0x20/2], 0);
     }

diff --git a/testpico/sh2_test.sh2 b/testpico/sh2_test.sh2
index 37ab204..1f3d61a 100644 (file)
--- a/testpico/sh2_test.sh2
+++ b/testpico/sh2_test.sh2
@@ -7,48 +7,21 @@
         .long   0x06040000  /* Cold Start SP */
         .long   mstart      /* Manual Reset PC */
         .long   0x06040000  /* Manual Reset SP */
-        .long   main_err    /* Illegal instruction */
-        .long   0x00000000  /* reserved */
-        .long   main_err    /* Invalid slot instruction */
-        .long   0x20100400  /* reserved */
-        .long   0x20100420  /* reserved */
-        .long   main_err    /* CPU address error */
-        .long   main_err    /* DMA address error */
-        .long   main_err    /* NMI vector */
-        .long   main_err    /* User break vector */
-        .space  76          /* reserved */
-        .long   main_err    /* TRAPA #32 */
-        .long   main_err    /* TRAPA #33 */
-        .long   main_err    /* TRAPA #34 */
-        .long   main_err    /* TRAPA #35 */
-        .long   main_err    /* TRAPA #36 */
-        .long   main_err    /* TRAPA #37 */
-        .long   main_err    /* TRAPA #38 */
-        .long   main_err    /* TRAPA #39 */
-        .long   main_err    /* TRAPA #40 */
-        .long   main_err    /* TRAPA #41 */
-        .long   main_err    /* TRAPA #42 */
-        .long   main_err    /* TRAPA #43 */
-        .long   main_err    /* TRAPA #44 */
-        .long   main_err    /* TRAPA #45 */
-        .long   main_err    /* TRAPA #46 */
-        .long   main_err    /* TRAPA #47 */
-        .long   main_err    /* TRAPA #48 */
-        .long   main_err    /* TRAPA #49 */
-        .long   main_err    /* TRAPA #50 */
-        .long   main_err    /* TRAPA #51 */
-        .long   main_err    /* TRAPA #52 */
-        .long   main_err    /* TRAPA #53 */
-        .long   main_err    /* TRAPA #54 */
-        .long   main_err    /* TRAPA #55 */
-        .long   main_err    /* TRAPA #56 */
-        .long   main_err    /* TRAPA #57 */
-        .long   main_err    /* TRAPA #58 */
-        .long   main_err    /* TRAPA #59 */
-        .long   main_err    /* TRAPA #60 */
-        .long   main_err    /* TRAPA #61 */
-        .long   main_err    /* TRAPA #62 */
-        .long   main_err    /* TRAPA #63 */
+        .long   master_e4   /* Illegal instruction */
+        .long   master_e5   /* reserved */
+        .long   master_e6   /* Invalid slot instruction */
+        .long   master_e7   /* reserved */
+        .long   master_e8   /* reserved */
+        .long   master_e9   /* CPU address error */
+        .long   master_e10  /* DMA address error */
+        .long   master_e11  /* NMI vector */
+        .long   master_e12  /* User break vector */
+.rept 19
+        .long   main_err    /* reserved */
+.endr
+.rept 32
+        .long   main_err    /* TRAPA #32-63 */
+.endr
         .long   main_irq    /* Level 1 IRQ */
         .long   main_irq    /* Level 2 & 3 IRQ's */
         .long   main_irq    /* Level 4 & 5 IRQ's */
@@ -57,94 +30,141 @@
         .long   main_irq    /* H Blank interupt */
         .long   main_irq    /* V Blank interupt */
         .long   main_irq    /* Reset Button */
-        .long   main_irq    /* DMA1 TE INT */
+.rept 56
+        .long   main_err    /* peripherals */
+.endr
 
-! Slave Vector Base Table at 0x06000124
+! Slave Vector Base Table at 0x06000200
 
         .long   sstart      /* Cold Start PC */
         .long   0x0603f800  /* Cold Start SP */
         .long   sstart      /* Manual Reset PC */
         .long   0x0603f800  /* Manual Reset SP */
-        .long   slav_err    /* Illegal instruction */
-        .long   0x00000000  /* reserved */
-        .long   slav_err    /* Invalid slot instruction */
-        .long   0x20100400  /* reserved */
-        .long   0x20100420  /* reserved */
-        .long   slav_err    /* CPU address error */
-        .long   slav_err    /* DMA address error */
-        .long   slav_err    /* NMI vector */
-        .long   slav_err    /* User break vector */
-        .space  76          /* reserved */
-        .long   slav_err    /* TRAPA #32 */
-        .long   slav_err    /* TRAPA #33 */
-        .long   slav_err    /* TRAPA #34 */
-        .long   slav_err    /* TRAPA #35 */
-        .long   slav_err    /* TRAPA #36 */
-        .long   slav_err    /* TRAPA #37 */
-        .long   slav_err    /* TRAPA #38 */
-        .long   slav_err    /* TRAPA #39 */
-        .long   slav_err    /* TRAPA #40 */
-        .long   slav_err    /* TRAPA #41 */
-        .long   slav_err    /* TRAPA #42 */
-        .long   slav_err    /* TRAPA #43 */
-        .long   slav_err    /* TRAPA #44 */
-        .long   slav_err    /* TRAPA #45 */
-        .long   slav_err    /* TRAPA #46 */
-        .long   slav_err    /* TRAPA #47 */
-        .long   slav_err    /* TRAPA #48 */
-        .long   slav_err    /* TRAPA #49 */
-        .long   slav_err    /* TRAPA #50 */
-        .long   slav_err    /* TRAPA #51 */
-        .long   slav_err    /* TRAPA #52 */
-        .long   slav_err    /* TRAPA #53 */
-        .long   slav_err    /* TRAPA #54 */
-        .long   slav_err    /* TRAPA #55 */
-        .long   slav_err    /* TRAPA #56 */
-        .long   slav_err    /* TRAPA #57 */
-        .long   slav_err    /* TRAPA #58 */
-        .long   slav_err    /* TRAPA #59 */
-        .long   slav_err    /* TRAPA #60 */
-        .long   slav_err    /* TRAPA #61 */
-        .long   slav_err    /* TRAPA #62 */
-        .long   slav_err    /* TRAPA #63 */
-        .long   slav_irq    /* Level 1 IRQ */
-        .long   slav_irq    /* Level 2 & 3 IRQ's */
-        .long   slav_irq    /* Level 4 & 5 IRQ's */
-        .long   slav_irq    /* PWM interupt */
-        .long   slav_irq    /* Command interupt */
-        .long   slav_irq    /* H Blank interupt */
-        .long   slav_irq    /* V Blank interupt */
-        .long   slav_irq    /* Reset Button */
+        .long   slave_e4    /* Illegal instruction */
+        .long   slave_e5    /* reserved */
+        .long   slave_e6    /* Invalid slot instruction */
+        .long   slave_e7    /* reserved */
+        .long   slave_e8    /* reserved */
+        .long   slave_e9    /* CPU address error */
+        .long   slave_e10   /* DMA address error */
+        .long   slave_e11   /* NMI vector */
+        .long   slave_e12   /* User break vector */
+.rept 19
+        .long   slave_err   /* reserved */
+.endr
+.rept 32
+        .long   slave_err   /* TRAPA #32-63 */
+.endr
+        .long   slave_irq   /* Level 1 IRQ */
+        .long   slave_irq   /* Level 2 & 3 IRQ's */
+        .long   slave_irq   /* Level 4 & 5 IRQ's */
+        .long   slave_irq   /* PWM interupt */
+        .long   slave_irq   /* Command interupt */
+        .long   slave_irq   /* H Blank interupt */
+        .long   slave_irq   /* V Blank interupt */
+        .long   slave_irq   /* Reset Button */
+.rept 56
+        .long   slave_err   /* peripherals */
+.endr
+
+! trashes r0
+.macro mov_bc const ofs reg
+        mov     #\const, r0
+.if \ofs == 0
+        mov.b   r0, @\reg
+.else
+        mov.b   r0, @(\ofs, \reg)
+.endif
+.endm
 
 ! Stacks set up by BIOS
 
-! The main SH2 starts here at 0x06000244
+! The main SH2 starts here at 0x06000400
 
 mstart:
-        bra     mcont
+        bra     xstart
         mov     #0, r4
 
-! The slave SH2 starts here at 0x06000248
+! The slave SH2 starts here at 0x06000404
 
 sstart:
-        sleep
-! broken
-        bra     xstart
         mov     #1, r4
 
-mcont:
-
 xstart:
-        mov.l   l_cctl, r0
-        mov     #0x11, r1
-        mov.b   r1, @r0
+.if 0
+! cache init - done by BIOS with single 0x11 write
+        mov.l   l_cctl, r1   /* cache */
+        mov_bc  0x00, 0, r1  /* disable */
+        mov.b   @r1, r0      /* dummy read */
+        mov_bc  0x10, 0, r1  /* purge */
+        mov.b   @r1, r0
+        mov_bc  0x01, 0, r1  /* enable */
+.endif
+        mov     #0xd0, r0    /* enable irqs */
+        ldc     r0, sr
         mov.l   l_main_c, r0
         jmp     @r0
         nop
 
+main_irq:
+        mov.l   r0, @-r15
+
+        stc     sr, r0       /* SR holds IRQ level in I3-I0 */
+        shlr2   r0
+        and     #0x38,r0
+        cmp/eq  #0x38,r0
+        bt      main_irq_vres
+! todo
+0:
+        bra     0b
+        nop
+
+main_irq_vres:
+        mov.w   r0, @(0x14, gbr)  /* ack */
+        mov.b   @(7, gbr), r0     /* RV */
+        tst     #1, r0
+        bt      main_irq_ret
+
+! Try to set FTOB pin that's wired to 32X hard reset.
+! Doesn't seem to be working right though, it somehow disturbs
+! 68k reset PC fetch which mysteriously ends up at range
+! 2c8 - 304 in multiples of 4, proportionally to reset delay
+! (0 - ~300 (?) sh2 cycles). Longer delay just hangs, presumably
+! at 880200?
+        mov.l   l_frt, r1
+        mov_bc  0xf1, 7, r1  /* TOCR sel OCRB, pin on B match */
+        mov     #0, r0
+        mov.b   r0, @(4, r1) /* OCRB H - output compare B */
+        mov.b   r0, @(5, r1) /* OCRB L */
+        mov.b   r0, @(2, r1) /* FRC H */
+        mov.b   r0, @(3, r1) /* FRC L */
+        mov.b   @(7, r1), r0
+! sleep - docs say not to use
+!        sleep
+0:
+        bra     0b
+        nop
+
+main_irq_ret:
+        rte
+        mov.l   @r15+, r0
+
+.global _read_frt
+_read_frt:
+        mov.l   l_frt, r2
+        mov.b   @(2, r2), r0
+        extu.b  r0, r1
+        mov.b   @(3, r2), r0
+        extu.b  r0, r0
+        shll8   r1
+        rts
+        or      r1, r0
+
 .align 2
 l_cctl:
         .long   0xFFFFFE92
+l_frt:
+        .long   0xFFFFFE10
 l_main_c:
         .long   _main_c
 
@@ -152,6 +172,58 @@ l_main_c:
 .global _start
 _start:
 
+main_err:
+        bra     do_exc_master
+        mov     #0xff, r0
+slave_err:
+slave_irq:
+        bra     do_exc_slave
+        mov     #0xff, r0
+
+.macro exc_master num
+master_e\num:
+        bra     do_exc_master
+        mov     #\num, r0
+.endm
+
+.macro exc_slave num
+slave_e\num:
+        bra     do_exc_slave
+        mov     #\num, r0
+.endm
+
+exc_master 4
+exc_master 5
+exc_master 6
+exc_master 7
+exc_master 8
+exc_master 9
+exc_master 10
+exc_master 11
+exc_master 12
+
+exc_slave 4
+exc_slave 5
+exc_slave 6
+exc_slave 7
+exc_slave 8
+exc_slave 9
+exc_slave 10
+exc_slave 11
+exc_slave 12
+
+do_exc_master:
+        mov.w   r0, @(0x2c, gbr)
+0:
+        bra     0b
+        nop
+
+do_exc_slave:
+        mov.w   r0, @(0x2e, gbr)
+0:
+        bra     0b
+        nop
+
 .global _spin
 _spin:
         dt      r4
@@ -159,12 +231,4 @@ _spin:
         rts
         nop
 
-main_err:
-main_irq:
-slav_err:
-slav_irq:
-0:
-        bra     0b
-        nop
-
 ! vim:ts=8:sw=8:expandtab